mirror of
git://projects.qi-hardware.com/xue.git
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3676 lines
59 KiB
Plaintext
3676 lines
59 KiB
Plaintext
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# EESchema Netlist Version 1.1 created Thu 23 Dec 2010 03:47:57 PM COT
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(
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( /4C69ED5F/4D135027 $noname U12 LM2621 {Lib=LM2621}
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( 1 ? )
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( 2 ? )
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( 3 ? )
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( 4 ? )
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( 5 ? )
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( 6 ? )
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( 7 ? )
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( 8 ? )
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)
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( /4C69ED5F/4D12A632 $noname U10 NCP1529 {Lib=NCP1529}
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( 1 ? )
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( 2 ? )
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( 3 ? )
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( 4 ? )
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( 5 ? )
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( 6 ? )
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)
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( /4C69ED5F/4D129D51 $noname U11 BD9130NV {Lib=BD9130NV}
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( 1 ? )
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( 2 ? )
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( 3 ? )
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( 4 ? )
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( 5 ? )
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( 6 ? )
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( 7 ? )
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( 8 ? )
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)
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( /4C69ED5F/4D128F46 MLF20m1 U9 BD9132MUV {Lib=BD9132MUV}
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( 1 N-000170 )
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( 2 ? )
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( 3 ? )
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( 4 ? )
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( 5 ? )
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( 6 ? )
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( 7 ? )
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( 8 ? )
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( 9 ? )
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( 10 ? )
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( 11 ? )
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( 12 ? )
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( 13 ? )
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( 14 ? )
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( 15 ? )
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( 16 ? )
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( 17 ? )
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( 18 ? )
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( 19 ? )
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( 20 ? )
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( 21 ? )
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)
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( /4C7BC2B2/4CD34D8C 0402 C156 10nF {Lib=C}
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( 1 GND )
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( 2 VCCO2 )
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)
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( /4C7BC2B2/4CD34D72 $noname X2 FXO-HC536R {Lib=FXO-HC536R}
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( 1 ? )
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( 2 GND )
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( 3 /expansion/FPGA_BANK0_IO_38 )
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( 4 VCCO2 )
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)
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( /4C7BC2B2/4C749A0C 0402 C94 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C748EDB 0402 C92 470nF {Lib=C}
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( 1 +1.2V )
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( 2 GND )
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)
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( /4C7BC2B2/4C748EDA 0402 C93 470nF {Lib=C}
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( 1 +1.2V )
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( 2 GND )
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)
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( /4C7BC2B2/4C73D252 0402 C91 470nF {Lib=C}
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( 1 +3.3V )
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( 2 GND )
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)
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( /4C7BC2B2/4C73D074 0402 C90 470nF {Lib=C}
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( 1 +3.3V )
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( 2 GND )
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)
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( /4C7BC2B2/4C7168DD 0402 R30 330 {Lib=R}
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( 1 +3.3V )
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( 2 N-000359 )
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)
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( /4C7BC2B2/4C716877 0402 R29 4.7k {Lib=R}
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( 1 +3.3V )
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( 2 N-000356 )
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)
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( /4C7BC2B2/4C6B29DA 0402 C77 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C6B29A3 0402 C76 470nF {Lib=C}
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( 1 +1.2V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D9D 0402 C66 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D9A 0402 C63 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D99 0402 C60 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D98 0603 C57 4.7uF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D97 1210 C54 100uF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D53 0402 C69 470nF {Lib=C}
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( 1 VCCO2 )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D49 0602 C67 470nF {Lib=C}
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( 1 VCCO2 )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D46 0402 C64 470nF {Lib=C}
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( 1 VCCO2 )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D45 0402 C61 470nF {Lib=C}
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( 1 VCCO2 )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D44 0603 C58 4.7uF {Lib=C}
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( 1 VCCO2 )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D43 1210 C55 100uF {Lib=C}
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( 1 VCCO2 )
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( 2 GND )
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)
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( /4C7BC2B2/4C656D08 0402 C68 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656CFC 0402 C65 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656CFB 0402 C62 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656CFA 0603 C59 4.7uF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656CF9 1210 C56 100uF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656CBB 0402 C50 470nF {Lib=C}
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( 1 +3.3V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656CBA 0402 C47 470nF {Lib=C}
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( 1 +3.3V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656CB9 0603 C44 4.7uF {Lib=C}
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( 1 +3.3V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656CB7 1210 C41 100uF {Lib=C}
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( 1 +3.3V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656C49 0402 C53 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656C27 0402 C51 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656C24 0402 C49 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656C16 0402 C46 4.7uF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656BFA 0402 C52 470nF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656BF9 0603 C43 4.7uF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656BF8 1210 C40 100uF {Lib=C}
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( 1 +2.5V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656AC2 0402 C48 470nF {Lib=C}
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( 1 +1.2V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656AC0 0402 C45 470nF {Lib=C}
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( 1 +1.2V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656ABD 0603 C42 4.7uF {Lib=C}
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( 1 +1.2V )
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( 2 GND )
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)
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( /4C7BC2B2/4C656A80 1210 C39 100uF {Lib=C}
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( 1 +1.2V )
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( 2 GND )
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)
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( /4C7BC2B2/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
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( A1 GND )
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( A2 ? )
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( A3 GND )
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( A4 /fpga1/ETH_CLK )
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( A5 /fpga1/ETH_RXD1 )
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( A6 /ether/ETH_RXDV )
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( A7 /fpga1/ETH_RXC )
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( A8 /fpga1/ETH_TXD3 )
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( A9 /fpga1/ETH_COL )
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( A10 /ether/ETH_INT )
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( A11 /fpga1/NF_D6 )
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( A12 /flash/NF_D4 )
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( A13 /flash/NF_D2 )
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( A14 /fpga1/NF_ALE )
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( A15 /fpga1/NF_RNB )
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( A16 /flash/SD_DAT2 )
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( A17 /fpga1/SD_CLK )
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( A18 /fpga1/SD_DAT0 )
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( A19 ? )
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( A20 /fpga2/USBD_RCV )
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( A21 /usb/USBD_OE_N )
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( A22 GND )
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( AA1 N-000356 )
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( AA2 ? )
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( AA3 VCCO2 )
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( AA4 ? )
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( AA5 GND )
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( AA6 ? )
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( AA7 VCCO2 )
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( AA8 ? )
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( AA9 GND )
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( AA10 ? )
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( AA11 VCCO2 )
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( AA12 ? )
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( AA13 GND )
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( AA14 /fpga1/FPGA_BANK0_IO_22 )
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( AA15 VCCO2 )
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( AA16 /fpga1/FPGA_BANK0_IO_28 )
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( AA17 GND )
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( AA18 /fpga1/FPGA_BANK0_IO_18 )
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( AA19 VCCO2 )
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( AA20 /fpga1/PROG_MISO1 )
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( AA21 /fpga1/PROG_CCLK )
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( AA22 VCCO2 )
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( AB1 GND )
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( AB2 ? )
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( AB3 ? )
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( AB4 ? )
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( AB5 ? )
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( AB6 ? )
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( AB7 ? )
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( AB8 ? )
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( AB9 ? )
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( AB10 ? )
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( AB11 ? )
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( AB12 ? )
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( AB13 /expansion/FPGA_BANK0_IO_39 )
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( AB14 ? )
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( AB15 /fpga1/FPGA_BANK0_IO_33 )
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( AB16 /expansion/FPGA_BANK0_IO_29 )
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( AB17 /expansion/FPGA_BANK0_IO_21 )
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( AB18 ? )
|
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( AB19 ? )
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( AB20 /fpga1/PROG_MISO0 )
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( AB21 ? )
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( AB22 GND )
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( B1 ? )
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( B2 ? )
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( B3 ? )
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( B4 +3.3V )
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( B5 GND )
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( B6 /ether/ETH_RXD0 )
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( B7 +3.3V )
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( B8 /ether/ETH_RXER )
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( B9 GND )
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( B10 /ether/ETH_CRS )
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( B11 +3.3V )
|
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( B12 /fpga1/NF_D3 )
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( B13 GND )
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( B14 /flash/NF_CLE )
|
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( B15 +3.3V )
|
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( B16 /flash/SD_DAT3 )
|
||
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( B17 GND )
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( B18 /flash/SD_DAT1 )
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( B19 +3.3V )
|
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( B20 /usb/USBD_SPD )
|
||
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( B21 /usb/USBD_VP )
|
||
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( B22 /usb/USBD_VM )
|
||
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( C1 /fpga2/R_M0_A11 )
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( C2 +2.5V )
|
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( C3 ? )
|
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( C4 ? )
|
||
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( C5 /fpga1/ETH_RXD3 )
|
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( C6 /fpga1/ETH_RXD2 )
|
||
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( C7 /fpga1/ETH_RESET_N )
|
||
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( C8 /fpga1/ETH_TXC )
|
||
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( C9 /fpga1/ETH_TXD1 )
|
||
|
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( C10 /fpga1/ETH_TXD2 )
|
||
|
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( C11 /flash/NF_D5 )
|
||
|
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( C12 /fpga1/NF_D0 )
|
||
|
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( C13 ? )
|
||
|
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( C14 /flash/NF_WE_N )
|
||
|
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( C15 /flash/NF_RE_N )
|
||
|
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( C16 /flash/SD_CMD )
|
||
|
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( C17 ? )
|
||
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( C18 ? )
|
||
|
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( C19 /usb/USBA_OE_N )
|
||
|
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( C20 /fpga2/R_M1_A8 )
|
||
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( C21 +2.5V )
|
||
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( C22 /fpga2/R_M1_A9 )
|
||
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( D1 /fpga2/R_M0_A12 )
|
||
|
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( D2 /fpga2/R_M0_CKE )
|
||
|
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( D3 ? )
|
||
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( D4 GND )
|
||
|
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( D5 ? )
|
||
|
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( D6 /ether/ETH_MDIO )
|
||
|
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( D7 /fpga1/ETH_MDC )
|
||
|
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( D8 /ether/ETH_TXER )
|
||
|
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( D9 /fpga1/ETH_TXEN )
|
||
|
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( D10 /fpga1/ETH_TXD0 )
|
||
|
|
( D11 /fpga1/NF_D7 )
|
||
|
|
( D12 ? )
|
||
|
|
( D13 ? )
|
||
|
|
( D14 /fpga1/NF_D1 )
|
||
|
|
( D15 /fpga1/NF_CS1_N )
|
||
|
|
( D16 +2.5V )
|
||
|
|
( D17 ? )
|
||
|
|
( D18 GND )
|
||
|
|
( D19 /fpga2/USBA_VP )
|
||
|
|
( D20 /fpga2/USBA_VM )
|
||
|
|
( D21 /fpga2/R_M1_CKE )
|
||
|
|
( D22 /fpga2/R_M1_A12 )
|
||
|
|
( E1 /fpga2/R_M0_A9 )
|
||
|
|
( E2 GND )
|
||
|
|
( E3 /fpga2/R_M0_A8 )
|
||
|
|
( E4 ? )
|
||
|
|
( E5 ? )
|
||
|
|
( E6 ? )
|
||
|
|
( E7 GND )
|
||
|
|
( E8 ? )
|
||
|
|
( E9 +3.3V )
|
||
|
|
( E10 ? )
|
||
|
|
( E11 GND )
|
||
|
|
( E12 ? )
|
||
|
|
( E13 +3.3V )
|
||
|
|
( E14 ? )
|
||
|
|
( E15 GND )
|
||
|
|
( E16 ? )
|
||
|
|
( E17 +3.3V )
|
||
|
|
( E18 ? )
|
||
|
|
( E19 +2.5V )
|
||
|
|
( E20 /fpga2/R_M1_A7 )
|
||
|
|
( E21 GND )
|
||
|
|
( E22 /fpga2/R_M1_A2 )
|
||
|
|
( F1 ? )
|
||
|
|
( F2 /fpga2/R_M0_WE# )
|
||
|
|
( F3 /fpga2/R_M0_A4 )
|
||
|
|
( F4 +2.5V )
|
||
|
|
( F5 ? )
|
||
|
|
( F6 +2.5V )
|
||
|
|
( F7 ? )
|
||
|
|
( F8 ? )
|
||
|
|
( F9 ? )
|
||
|
|
( F10 ? )
|
||
|
|
( F11 +2.5V )
|
||
|
|
( F12 ? )
|
||
|
|
( F13 ? )
|
||
|
|
( F14 ? )
|
||
|
|
( F15 ? )
|
||
|
|
( F16 /usb/USBA_SPD )
|
||
|
|
( F17 /fpga2/USBA_RCV )
|
||
|
|
( F18 ? )
|
||
|
|
( F19 /fpga2/R_M1_A11 )
|
||
|
|
( F20 /fpga2/R_M1_A4 )
|
||
|
|
( F21 /fpga2/R_M1_A0 )
|
||
|
|
( F22 /fpga2/R_M1_A1 )
|
||
|
|
( G1 /fpga2/R_M0_BA1 )
|
||
|
|
( G2 +2.5V )
|
||
|
|
( G3 /fpga2/R_M0_BA0 )
|
||
|
|
( G4 /fpga2/R_M0_A10 )
|
||
|
|
( G5 GND )
|
||
|
|
( G6 ? )
|
||
|
|
( G7 ? )
|
||
|
|
( G8 ? )
|
||
|
|
( G9 ? )
|
||
|
|
( G10 +3.3V )
|
||
|
|
( G11 ? )
|
||
|
|
( G12 +2.5V )
|
||
|
|
( G13 ? )
|
||
|
|
( G14 +3.3V )
|
||
|
|
( G15 ? )
|
||
|
|
( G16 ? )
|
||
|
|
( G17 ? )
|
||
|
|
( G18 GND )
|
||
|
|
( G19 /fpga2/R_M1_A10 )
|
||
|
|
( G20 /fpga2/R_M1_A3 )
|
||
|
|
( G21 +2.5V )
|
||
|
|
( G22 ? )
|
||
|
|
( H1 /fpga2/R_M0_A1 )
|
||
|
|
( H2 /fpga2/R_M0_A0 )
|
||
|
|
( H3 /sdram/M0_CLK# )
|
||
|
|
( H4 /fpga2/M0_CLK )
|
||
|
|
( H5 /fpga2/R_M0_A2 )
|
||
|
|
( H6 /fpga2/R_M0_A7 )
|
||
|
|
( H7 GND )
|
||
|
|
( H8 ? )
|
||
|
|
( H9 +2.5V )
|
||
|
|
( H10 ? )
|
||
|
|
( H11 ? )
|
||
|
|
( H12 ? )
|
||
|
|
( H13 ? )
|
||
|
|
( H14 ? )
|
||
|
|
( H15 +2.5V )
|
||
|
|
( H16 /fpga2/R_M1_CS# )
|
||
|
|
( H17 ? )
|
||
|
|
( H18 ? )
|
||
|
|
( H19 /fpga2/R_M1_WE# )
|
||
|
|
( H20 /sdram/M1_CLK )
|
||
|
|
( H21 /fpga2/R_M1_RAS# )
|
||
|
|
( H22 /fpga2/R_M1_CAS# )
|
||
|
|
( J1 /fpga2/R_M0_DQ5 )
|
||
|
|
( J2 GND )
|
||
|
|
( J3 /fpga2/R_M0_DQ4 )
|
||
|
|
( J4 /fpga2/R_M0_A6 )
|
||
|
|
( J5 +2.5V )
|
||
|
|
( J6 ? )
|
||
|
|
( J7 ? )
|
||
|
|
( J8 +1.2V )
|
||
|
|
( J9 GND )
|
||
|
|
( J10 +1.2V )
|
||
|
|
( J11 GND )
|
||
|
|
( J12 +1.2V )
|
||
|
|
( J13 GND )
|
||
|
|
( J14 +1.2V )
|
||
|
|
( J15 GND )
|
||
|
|
( J16 ? )
|
||
|
|
( J17 /fpga2/R_M1_BA0 )
|
||
|
|
( J18 +2.5V )
|
||
|
|
( J19 /sdram/M1_CLK# )
|
||
|
|
( J20 /fpga2/R_M1_DQ4 )
|
||
|
|
( J21 GND )
|
||
|
|
( J22 /fpga2/R_M1_DQ5 )
|
||
|
|
( K1 /fpga2/R_M0_DQ7 )
|
||
|
|
( K2 /fpga2/R_M0_DQ6 )
|
||
|
|
( K3 /fpga2/R_M0_A5 )
|
||
|
|
( K4 /fpga2/R_M0_CAS# )
|
||
|
|
( K5 /fpga2/R_M0_RAS# )
|
||
|
|
( K6 /fpga2/R_M0_A3 )
|
||
|
|
( K7 ? )
|
||
|
|
( K8 ? )
|
||
|
|
( K9 +1.2V )
|
||
|
|
( K10 GND )
|
||
|
|
( K11 +1.2V )
|
||
|
|
( K12 GND )
|
||
|
|
( K13 +1.2V )
|
||
|
|
( K14 GND )
|
||
|
|
( K15 +2.5V )
|
||
|
|
( K16 ? )
|
||
|
|
( K17 /fpga2/R_M1_BA1 )
|
||
|
|
( K18 ? )
|
||
|
|
( K19 /fpga2/R_M1_A6 )
|
||
|
|
( K20 /fpga2/R_M1_A5 )
|
||
|
|
( K21 /fpga2/R_M1_DQ6 )
|
||
|
|
( K22 /fpga2/R_M1_DQ7 )
|
||
|
|
( L1 ? )
|
||
|
|
( L2 +2.5V )
|
||
|
|
( L3 /fpga2/R_M0_LDQS )
|
||
|
|
( L4 /fpga2/R_M0_LDM )
|
||
|
|
( L5 GND )
|
||
|
|
( L6 ? )
|
||
|
|
( L7 +2.5V )
|
||
|
|
( L8 +2.5V )
|
||
|
|
( L9 GND )
|
||
|
|
( L10 +1.2V )
|
||
|
|
( L11 GND )
|
||
|
|
( L12 +1.2V )
|
||
|
|
( L13 GND )
|
||
|
|
( L14 +1.2V )
|
||
|
|
( L15 ? )
|
||
|
|
( L16 +2.5V )
|
||
|
|
( L17 ? )
|
||
|
|
( L18 GND )
|
||
|
|
( L19 /fpga2/R_M1_LDM )
|
||
|
|
( L20 /fpga2/R_M1_LDQS )
|
||
|
|
( L21 +2.5V )
|
||
|
|
( L22 ? )
|
||
|
|
( M1 /fpga2/R_M0_DQ3 )
|
||
|
|
( M2 /fpga2/R_M0_DQ2 )
|
||
|
|
( M3 /fpga2/R_M0_UDM )
|
||
|
|
( M4 ? )
|
||
|
|
( M5 ? )
|
||
|
|
( M6 ? )
|
||
|
|
( M7 ? )
|
||
|
|
( M8 ? )
|
||
|
|
( M9 +1.2V )
|
||
|
|
( M10 GND )
|
||
|
|
( M11 +1.2V )
|
||
|
|
( M12 GND )
|
||
|
|
( M13 +1.2V )
|
||
|
|
( M14 GND )
|
||
|
|
( M15 +2.5V )
|
||
|
|
( M16 ? )
|
||
|
|
( M17 ? )
|
||
|
|
( M18 ? )
|
||
|
|
( M19 ? )
|
||
|
|
( M20 /fpga2/R_M1_UDM )
|
||
|
|
( M21 /fpga2/R_M1_DQ2 )
|
||
|
|
( M22 /fpga2/R_M1_DQ3 )
|
||
|
|
( N1 /fpga2/R_M0_DQ1 )
|
||
|
|
( N2 GND )
|
||
|
|
( N3 /fpga2/R_M0_DQ0 )
|
||
|
|
( N4 ? )
|
||
|
|
( N5 +2.5V )
|
||
|
|
( N6 ? )
|
||
|
|
( N7 ? )
|
||
|
|
( N8 +2.5V )
|
||
|
|
( N9 GND )
|
||
|
|
( N10 +1.2V )
|
||
|
|
( N11 GND )
|
||
|
|
( N12 +1.2V )
|
||
|
|
( N13 GND )
|
||
|
|
( N14 +1.2V )
|
||
|
|
( N15 GND )
|
||
|
|
( N16 ? )
|
||
|
|
( N17 GND )
|
||
|
|
( N18 +2.5V )
|
||
|
|
( N19 ? )
|
||
|
|
( N20 /fpga2/R_M1_DQ0 )
|
||
|
|
( N21 GND )
|
||
|
|
( N22 /fpga2/R_M1_DQ1 )
|
||
|
|
( P1 /fpga2/R_M0_DQ9 )
|
||
|
|
( P2 /fpga2/R_M0_DQ8 )
|
||
|
|
( P3 ? )
|
||
|
|
( P4 ? )
|
||
|
|
( P5 ? )
|
||
|
|
( P6 ? )
|
||
|
|
( P7 ? )
|
||
|
|
( P8 ? )
|
||
|
|
( P9 +1.2V )
|
||
|
|
( P10 GND )
|
||
|
|
( P11 +1.2V )
|
||
|
|
( P12 GND )
|
||
|
|
( P13 +1.2V )
|
||
|
|
( P14 GND )
|
||
|
|
( P15 ? )
|
||
|
|
( P16 ? )
|
||
|
|
( P17 ? )
|
||
|
|
( P18 ? )
|
||
|
|
( P19 ? )
|
||
|
|
( P20 ? )
|
||
|
|
( P21 /fpga2/R_M1_DQ8 )
|
||
|
|
( P22 /fpga2/R_M1_DQ9 )
|
||
|
|
( R1 /fpga2/R_M0_DQ11 )
|
||
|
|
( R2 +2.5V )
|
||
|
|
( R3 /fpga2/R_M0_DQ10 )
|
||
|
|
( R4 ? )
|
||
|
|
( R5 GND )
|
||
|
|
( R6 +2.5V )
|
||
|
|
( R7 ? )
|
||
|
|
( R8 ? )
|
||
|
|
( R9 /fpga1/FPGA_BANK0_IO_58 )
|
||
|
|
( R10 +2.5V )
|
||
|
|
( R11 ? )
|
||
|
|
( R12 +2.5V )
|
||
|
|
( R13 ? )
|
||
|
|
( R14 +1.2V )
|
||
|
|
( R15 ? )
|
||
|
|
( R16 /expansion/FPGA_BANK0_IO_12 )
|
||
|
|
( R17 ? )
|
||
|
|
( R18 GND )
|
||
|
|
( R19 ? )
|
||
|
|
( R20 /fpga2/R_M1_DQ10 )
|
||
|
|
( R21 +2.5V )
|
||
|
|
( R22 /fpga2/R_M1_DQ11 )
|
||
|
|
( T1 ? )
|
||
|
|
( T2 /fpga2/R_M0_UDQS )
|
||
|
|
( T3 ? )
|
||
|
|
( T4 ? )
|
||
|
|
( T5 /fpga1/PROG_CSO )
|
||
|
|
( T6 ? )
|
||
|
|
( T7 /expansion/FPGA_BANK0_IO_60 )
|
||
|
|
( T8 /expansion/FPGA_BANK0_IO_53 )
|
||
|
|
( T9 VCCO2 )
|
||
|
|
( T10 ? )
|
||
|
|
( T11 ? )
|
||
|
|
( T12 /expansion/FPGA_BANK0_IO_34 )
|
||
|
|
( T13 VCCO2 )
|
||
|
|
( T14 /expansion/FPGA_BANK0_IO_36 )
|
||
|
|
( T15 /fpga1/FPGA_BANK0_IO_7 )
|
||
|
|
( T16 /fpga1/FPGA_BANK0_IO_6 )
|
||
|
|
( T17 /fpga1/FPGA_BANK0_IO_2 )
|
||
|
|
( T18 /expansion/FPGA_BANK0_IO_1 )
|
||
|
|
( T19 ? )
|
||
|
|
( T20 ? )
|
||
|
|
( T21 /fpga2/R_M1_UDQS )
|
||
|
|
( T22 ? )
|
||
|
|
( U1 /fpga2/R_M0_DQ13 )
|
||
|
|
( U2 GND )
|
||
|
|
( U3 /fpga2/R_M0_DQ12 )
|
||
|
|
( U4 ? )
|
||
|
|
( U5 +2.5V )
|
||
|
|
( U6 /fpga1/FPGA_BANK0_IO_62 )
|
||
|
|
( U7 GND )
|
||
|
|
( U8 /expansion/FPGA_BANK0_IO_54 )
|
||
|
|
( U9 /fpga1/FPGA_BANK0_IO_51 )
|
||
|
|
( U10 /fpga1/FPGA_BANK0_IO_56 )
|
||
|
|
( U11 +2.5V )
|
||
|
|
( U12 ? )
|
||
|
|
( U13 /fpga1/PROG_MISO3 )
|
||
|
|
( U14 /fpga1/PROG_MISO2 )
|
||
|
|
( U15 GND )
|
||
|
|
( U16 /expansion/FPGA_BANK0_IO_9 )
|
||
|
|
( U17 /expansion/FPGA_BANK0_IO_8 )
|
||
|
|
( U18 +2.5V )
|
||
|
|
( U19 ? )
|
||
|
|
( U20 /fpga2/R_M1_DQ12 )
|
||
|
|
( U21 GND )
|
||
|
|
( U22 /fpga2/R_M1_DQ13 )
|
||
|
|
( V1 /fpga2/R_M0_DQ15 )
|
||
|
|
( V2 /fpga2/R_M0_DQ14 )
|
||
|
|
( V3 ? )
|
||
|
|
( V4 GND )
|
||
|
|
( V5 /expansion/FPGA_BANK0_IO_63 )
|
||
|
|
( V6 +2.5V )
|
||
|
|
( V7 /expansion/FPGA_BANK0_IO_49 )
|
||
|
|
( V8 VCCO2 )
|
||
|
|
( V9 /fpga1/FPGA_BANK0_IO_52 )
|
||
|
|
( V10 GND )
|
||
|
|
( V11 /expansion/FPGA_BANK0_IO_43 )
|
||
|
|
( V12 VCCO2 )
|
||
|
|
( V13 ? )
|
||
|
|
( V14 GND )
|
||
|
|
( V15 /expansion/FPGA_BANK0_IO_17 )
|
||
|
|
( V16 VCCO2 )
|
||
|
|
( V17 /expansion/FPGA_BANK0_IO_14 )
|
||
|
|
( V18 /fpga1/FPGA_BANK0_IO_11 )
|
||
|
|
( V19 /expansion/FPGA_BANK0_IO_10 )
|
||
|
|
( V20 ? )
|
||
|
|
( V21 /fpga2/R_M1_DQ14 )
|
||
|
|
( V22 /fpga2/R_M1_DQ15 )
|
||
|
|
( W1 ? )
|
||
|
|
( W2 +2.5V )
|
||
|
|
( W3 ? )
|
||
|
|
( W4 ? )
|
||
|
|
( W5 VCCO2 )
|
||
|
|
( W6 /expansion/FPGA_BANK0_IO_57 )
|
||
|
|
( W7 GND )
|
||
|
|
( W8 /fpga1/FPGA_BANK0_IO_48 )
|
||
|
|
( W9 /fpga1/FPGA_BANK0_IO_50 )
|
||
|
|
( W10 /expansion/FPGA_BANK0_IO_46 )
|
||
|
|
( W11 /fpga1/FPGA_BANK0_IO_44 )
|
||
|
|
( W12 ? )
|
||
|
|
( W13 /expansion/FPGA_BANK0_IO_27 )
|
||
|
|
( W14 /expansion/FPGA_BANK0_IO_30 )
|
||
|
|
( W15 /fpga1/FPGA_BANK0_IO_25 )
|
||
|
|
( W16 GND )
|
||
|
|
( W17 /expansion/FPGA_BANK0_IO_15 )
|
||
|
|
( W18 ? )
|
||
|
|
( W19 GND )
|
||
|
|
( W20 ? )
|
||
|
|
( W21 +2.5V )
|
||
|
|
( W22 ? )
|
||
|
|
( Y1 ? )
|
||
|
|
( Y2 ? )
|
||
|
|
( Y3 ? )
|
||
|
|
( Y4 ? )
|
||
|
|
( Y5 ? )
|
||
|
|
( Y6 ? )
|
||
|
|
( Y7 ? )
|
||
|
|
( Y8 ? )
|
||
|
|
( Y9 /expansion/FPGA_BANK0_IO_45 )
|
||
|
|
( Y10 /expansion/FPGA_BANK0_IO_47 )
|
||
|
|
( Y11 /fpga1/FPGA_BANK0_IO_40 )
|
||
|
|
( Y12 ? )
|
||
|
|
( Y13 /expansion/FPGA_BANK0_IO_38 )
|
||
|
|
( Y14 ? )
|
||
|
|
( Y15 /expansion/FPGA_BANK0_IO_32 )
|
||
|
|
( Y16 /expansion/FPGA_BANK0_IO_24 )
|
||
|
|
( Y17 /fpga1/FPGA_BANK0_IO_20 )
|
||
|
|
( Y18 /expansion/FPGA_BANK0_IO_5 )
|
||
|
|
( Y19 /expansion/FPGA_BANK0_IO_3 )
|
||
|
|
( Y20 +3.3V )
|
||
|
|
( Y21 ? )
|
||
|
|
( Y22 N-000359 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4CCF27AA 0402 R81 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M1_LDM )
|
||
|
|
( 2 /sdram/M1_LDM )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4CCF27A9 0402 R80 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M1_WE# )
|
||
|
|
( 2 /fpga2/M1_WE# )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4CCF27A8 0402 R82 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M1_LDQS )
|
||
|
|
( 2 /fpga2/M1_LDQS )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4CCF27A7 0402 R79 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M1_CAS# )
|
||
|
|
( 2 /fpga2/M1_CAS# )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4CCF2733 0402 R83 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M0_CAS# )
|
||
|
|
( 2 /sdram/M0_CAS# )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4CCF2730 0402 R86 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M0_LDQS )
|
||
|
|
( 2 /fpga2/M0_LDQS )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4CCF272F 0402 R84 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M0_WE# )
|
||
|
|
( 2 /sdram/M0_WE# )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4CCF272E 0402 R85 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M0_LDM )
|
||
|
|
( 2 /sdram/M0_LDM )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C6B216E 0402 R23 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M0_UDM )
|
||
|
|
( 2 /fpga2/M0_UDM )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C6B216D 0402 R22 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M0_UDQS )
|
||
|
|
( 2 /fpga2/M0_UDQS )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C6B216B 0402 R24 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M0_CKE )
|
||
|
|
( 2 /fpga2/M0_CKE )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C6B1B90 0402 R21 120 {Lib=R}
|
||
|
|
( 1 /fpga2/M0_CLK )
|
||
|
|
( 2 /sdram/M0_CLK# )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M0_A0 )
|
||
|
|
( 2 /fpga2/R_M0_A1 )
|
||
|
|
( 3 /fpga2/R_M0_A2 )
|
||
|
|
( 4 /fpga2/R_M0_A3 )
|
||
|
|
( 5 /fpga2/M0_A3 )
|
||
|
|
( 6 /fpga2/M0_A2 )
|
||
|
|
( 7 /fpga2/M0_A1 )
|
||
|
|
( 8 /sdram/M0_A0 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M0_RAS# )
|
||
|
|
( 2 /fpga2/R_M0_BA0 )
|
||
|
|
( 3 /fpga2/R_M0_BA1 )
|
||
|
|
( 4 /fpga2/R_M0_A10 )
|
||
|
|
( 5 /fpga2/M0_A10 )
|
||
|
|
( 6 /fpga2/M0_BA1 )
|
||
|
|
( 7 /sdram/M0_BA0 )
|
||
|
|
( 8 /fpga2/M0_RAS# )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M0_A7 )
|
||
|
|
( 2 /fpga2/R_M0_A6 )
|
||
|
|
( 3 /fpga2/R_M0_A5 )
|
||
|
|
( 4 /fpga2/R_M0_A4 )
|
||
|
|
( 5 /sdram/M0_A4 )
|
||
|
|
( 6 /fpga2/M0_A5 )
|
||
|
|
( 7 /fpga2/M0_A6 )
|
||
|
|
( 8 /fpga2/M0_A7 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M0_A12 )
|
||
|
|
( 2 /fpga2/R_M0_A11 )
|
||
|
|
( 3 /fpga2/R_M0_A9 )
|
||
|
|
( 4 /fpga2/R_M0_A8 )
|
||
|
|
( 5 /fpga2/M0_A8 )
|
||
|
|
( 6 /fpga2/M0_A9 )
|
||
|
|
( 7 /fpga2/M0_A11 )
|
||
|
|
( 8 /fpga2/M0_A12 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M0_DQ4 )
|
||
|
|
( 2 /fpga2/R_M0_DQ5 )
|
||
|
|
( 3 /fpga2/R_M0_DQ6 )
|
||
|
|
( 4 /fpga2/R_M0_DQ7 )
|
||
|
|
( 5 /sdram/M0_DQ7 )
|
||
|
|
( 6 /sdram/M0_DQ6 )
|
||
|
|
( 7 /sdram/M0_DQ5 )
|
||
|
|
( 8 /sdram/M0_DQ4 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M0_DQ0 )
|
||
|
|
( 2 /fpga2/R_M0_DQ1 )
|
||
|
|
( 3 /fpga2/R_M0_DQ2 )
|
||
|
|
( 4 /fpga2/R_M0_DQ3 )
|
||
|
|
( 5 /fpga2/M0_DQ3 )
|
||
|
|
( 6 /fpga2/M0_DQ2 )
|
||
|
|
( 7 /sdram/M0_DQ1 )
|
||
|
|
( 8 /fpga2/M0_DQ0 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M0_DQ8 )
|
||
|
|
( 2 /fpga2/R_M0_DQ9 )
|
||
|
|
( 3 /fpga2/R_M0_DQ10 )
|
||
|
|
( 4 /fpga2/R_M0_DQ11 )
|
||
|
|
( 5 /fpga2/M0_DQ11 )
|
||
|
|
( 6 /fpga2/M0_DQ10 )
|
||
|
|
( 7 /fpga2/M0_DQ9 )
|
||
|
|
( 8 /sdram/M0_DQ8 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M0_DQ12 )
|
||
|
|
( 2 /fpga2/R_M0_DQ13 )
|
||
|
|
( 3 /fpga2/R_M0_DQ14 )
|
||
|
|
( 4 /fpga2/R_M0_DQ15 )
|
||
|
|
( 5 /sdram/M0_DQ15 )
|
||
|
|
( 6 /fpga2/M0_DQ14 )
|
||
|
|
( 7 /sdram/M0_DQ13 )
|
||
|
|
( 8 /fpga2/M0_DQ12 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69E7DD 0402 R19 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M1_UDQS )
|
||
|
|
( 2 /fpga2/M1_UDQS )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69E92D 0402 R20 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M1_CS# )
|
||
|
|
( 2 /sdram/M1_CS# )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69E7F8 0402 R17 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M1_CKE )
|
||
|
|
( 2 /fpga2/M1_CKE )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69E7C2 0402 R18 33 {Lib=R}
|
||
|
|
( 1 /fpga2/R_M1_UDM )
|
||
|
|
( 2 /fpga2/M1_UDM )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /sdram/M1_DQ11 )
|
||
|
|
( 2 /fpga2/M1_DQ10 )
|
||
|
|
( 3 /sdram/M1_DQ9 )
|
||
|
|
( 4 /fpga2/M1_DQ8 )
|
||
|
|
( 5 /fpga2/R_M1_DQ8 )
|
||
|
|
( 6 /fpga2/R_M1_DQ9 )
|
||
|
|
( 7 /fpga2/R_M1_DQ10 )
|
||
|
|
( 8 /fpga2/R_M1_DQ11 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /sdram/M1_DQ15 )
|
||
|
|
( 2 /sdram/M1_DQ14 )
|
||
|
|
( 3 /fpga2/M1_DQ13 )
|
||
|
|
( 4 /fpga2/M1_DQ12 )
|
||
|
|
( 5 /fpga2/R_M1_DQ12 )
|
||
|
|
( 6 /fpga2/R_M1_DQ13 )
|
||
|
|
( 7 /fpga2/R_M1_DQ14 )
|
||
|
|
( 8 /fpga2/R_M1_DQ15 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69DF7A 0402 R16 120 {Lib=R}
|
||
|
|
( 1 /sdram/M1_CLK# )
|
||
|
|
( 2 /sdram/M1_CLK )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /sdram/M1_A12 )
|
||
|
|
( 2 /sdram/M1_A11 )
|
||
|
|
( 3 /sdram/M1_A9 )
|
||
|
|
( 4 /sdram/M1_A8 )
|
||
|
|
( 5 /fpga2/R_M1_A8 )
|
||
|
|
( 6 /fpga2/R_M1_A9 )
|
||
|
|
( 7 /fpga2/R_M1_A11 )
|
||
|
|
( 8 /fpga2/R_M1_A12 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /sdram/M1_A7 )
|
||
|
|
( 2 /sdram/M1_A6 )
|
||
|
|
( 3 /fpga2/M1_A5 )
|
||
|
|
( 4 /fpga2/M1_A4 )
|
||
|
|
( 5 /fpga2/R_M1_A4 )
|
||
|
|
( 6 /fpga2/R_M1_A5 )
|
||
|
|
( 7 /fpga2/R_M1_A6 )
|
||
|
|
( 8 /fpga2/R_M1_A7 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M1_DQ0 )
|
||
|
|
( 2 /fpga2/R_M1_DQ1 )
|
||
|
|
( 3 /fpga2/R_M1_DQ2 )
|
||
|
|
( 4 /fpga2/R_M1_DQ3 )
|
||
|
|
( 5 /fpga2/M1_DQ3 )
|
||
|
|
( 6 /sdram/M1_DQ2 )
|
||
|
|
( 7 /sdram/M1_DQ1 )
|
||
|
|
( 8 /sdram/M1_DQ0 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M1_DQ4 )
|
||
|
|
( 2 /fpga2/R_M1_DQ5 )
|
||
|
|
( 3 /fpga2/R_M1_DQ6 )
|
||
|
|
( 4 /fpga2/R_M1_DQ7 )
|
||
|
|
( 5 /fpga2/M1_DQ7 )
|
||
|
|
( 6 /fpga2/M1_DQ6 )
|
||
|
|
( 7 /fpga2/M1_DQ5 )
|
||
|
|
( 8 /fpga2/M1_DQ4 )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M1_RAS# )
|
||
|
|
( 2 /fpga2/R_M1_BA0 )
|
||
|
|
( 3 /fpga2/R_M1_BA1 )
|
||
|
|
( 4 /fpga2/R_M1_A10 )
|
||
|
|
( 5 /sdram/M1_A10 )
|
||
|
|
( 6 /fpga2/M1_BA1 )
|
||
|
|
( 7 /fpga2/M1_BA0 )
|
||
|
|
( 8 /fpga2/M1_RAS# )
|
||
|
|
)
|
||
|
|
( /4C7BC2A2/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4}
|
||
|
|
( 1 /fpga2/R_M1_A0 )
|
||
|
|
( 2 /fpga2/R_M1_A1 )
|
||
|
|
( 3 /fpga2/R_M1_A2 )
|
||
|
|
( 4 /fpga2/R_M1_A3 )
|
||
|
|
( 5 /fpga2/M1_A3 )
|
||
|
|
( 6 /fpga2/M1_A2 )
|
||
|
|
( 7 /fpga2/M1_A1 )
|
||
|
|
( 8 /fpga2/M1_A0 )
|
||
|
|
)
|
||
|
|
( /4C4227FE/4C6969AB $noname C75 100nF {Lib=C}
|
||
|
|
( 1 GND )
|
||
|
|
( 2 +3.3V )
|
||
|
|
)
|
||
|
|
( /4C4227FE/4C65D681 0603 C74 1uF {Lib=CAP}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4227FE/4C65D67C 0402 C73 100nF {Lib=CAP}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4227FE/4C65D661 0402 C72 100nF {Lib=CAP}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB}
|
||
|
|
( 1 /fpga1/PROG_CSO )
|
||
|
|
( 2 /fpga1/PROG_MISO1 )
|
||
|
|
( 3 /fpga1/PROG_MISO2 )
|
||
|
|
( 4 GND )
|
||
|
|
( 5 /fpga1/PROG_MISO0 )
|
||
|
|
( 6 /fpga1/PROG_CCLK )
|
||
|
|
( 7 /fpga1/PROG_MISO3 )
|
||
|
|
( 8 VCCO2 )
|
||
|
|
)
|
||
|
|
( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD}
|
||
|
|
( 1 /flash/SD_DAT2 )
|
||
|
|
( 2 /flash/SD_DAT3 )
|
||
|
|
( 3 /flash/SD_CMD )
|
||
|
|
( 4 +3.3V )
|
||
|
|
( 5 /fpga1/SD_CLK )
|
||
|
|
( 6 GND )
|
||
|
|
( 7 /fpga1/SD_DAT0 )
|
||
|
|
( 8 /flash/SD_DAT1 )
|
||
|
|
( CASE GND )
|
||
|
|
( CD ? )
|
||
|
|
( COM GND )
|
||
|
|
)
|
||
|
|
( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M}
|
||
|
|
( 1 ? )
|
||
|
|
( 2 ? )
|
||
|
|
( 3 ? )
|
||
|
|
( 4 ? )
|
||
|
|
( 5 ? )
|
||
|
|
( 6 /fpga1/NF_RNB )
|
||
|
|
( 7 /fpga1/NF_RNB )
|
||
|
|
( 8 /flash/NF_RE_N )
|
||
|
|
( 9 /fpga1/NF_CS1_N )
|
||
|
|
( 10 ? )
|
||
|
|
( 11 ? )
|
||
|
|
( 12 +3.3V )
|
||
|
|
( 13 GND )
|
||
|
|
( 14 ? )
|
||
|
|
( 15 ? )
|
||
|
|
( 16 /flash/NF_CLE )
|
||
|
|
( 17 /fpga1/NF_ALE )
|
||
|
|
( 18 /flash/NF_WE_N )
|
||
|
|
( 19 +3.3V )
|
||
|
|
( 20 ? )
|
||
|
|
( 21 ? )
|
||
|
|
( 22 ? )
|
||
|
|
( 23 ? )
|
||
|
|
( 24 ? )
|
||
|
|
( 25 ? )
|
||
|
|
( 26 ? )
|
||
|
|
( 27 ? )
|
||
|
|
( 28 ? )
|
||
|
|
( 29 /fpga1/NF_D0 )
|
||
|
|
( 30 /fpga1/NF_D1 )
|
||
|
|
( 31 /flash/NF_D2 )
|
||
|
|
( 32 /fpga1/NF_D3 )
|
||
|
|
( 33 ? )
|
||
|
|
( 34 ? )
|
||
|
|
( 35 ? )
|
||
|
|
( 36 GND )
|
||
|
|
( 37 +3.3V )
|
||
|
|
( 38 ? )
|
||
|
|
( 39 ? )
|
||
|
|
( 40 ? )
|
||
|
|
( 41 /flash/NF_D4 )
|
||
|
|
( 42 /flash/NF_D5 )
|
||
|
|
( 43 /fpga1/NF_D6 )
|
||
|
|
( 44 /fpga1/NF_D7 )
|
||
|
|
( 45 ? )
|
||
|
|
( 46 ? )
|
||
|
|
( 47 ? )
|
||
|
|
( 48 ? )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 /sdram/M1_DQ0 )
|
||
|
|
( 3 +2.5V )
|
||
|
|
( 4 /sdram/M1_DQ1 )
|
||
|
|
( 5 /sdram/M1_DQ2 )
|
||
|
|
( 6 GND )
|
||
|
|
( 7 /fpga2/M1_DQ3 )
|
||
|
|
( 8 /fpga2/M1_DQ4 )
|
||
|
|
( 9 +2.5V )
|
||
|
|
( 10 /fpga2/M1_DQ5 )
|
||
|
|
( 11 /fpga2/M1_DQ6 )
|
||
|
|
( 12 GND )
|
||
|
|
( 13 /fpga2/M1_DQ7 )
|
||
|
|
( 14 ? )
|
||
|
|
( 15 +2.5V )
|
||
|
|
( 16 /fpga2/M1_LDQS )
|
||
|
|
( 17 ? )
|
||
|
|
( 18 +2.5V )
|
||
|
|
( 19 ? )
|
||
|
|
( 20 /sdram/M1_LDM )
|
||
|
|
( 21 /fpga2/M1_WE# )
|
||
|
|
( 22 /fpga2/M1_CAS# )
|
||
|
|
( 23 /fpga2/M1_RAS# )
|
||
|
|
( 24 /sdram/M1_CS# )
|
||
|
|
( 25 ? )
|
||
|
|
( 26 /fpga2/M1_BA0 )
|
||
|
|
( 27 /fpga2/M1_BA1 )
|
||
|
|
( 28 /sdram/M1_A10 )
|
||
|
|
( 29 /fpga2/M1_A0 )
|
||
|
|
( 30 /fpga2/M1_A1 )
|
||
|
|
( 31 /fpga2/M1_A2 )
|
||
|
|
( 32 /fpga2/M1_A3 )
|
||
|
|
( 33 +2.5V )
|
||
|
|
( 34 GND )
|
||
|
|
( 35 /fpga2/M1_A4 )
|
||
|
|
( 36 /fpga2/M1_A5 )
|
||
|
|
( 37 /sdram/M1_A6 )
|
||
|
|
( 38 /sdram/M1_A7 )
|
||
|
|
( 39 /sdram/M1_A8 )
|
||
|
|
( 40 /sdram/M1_A9 )
|
||
|
|
( 41 /sdram/M1_A11 )
|
||
|
|
( 42 /sdram/M1_A12 )
|
||
|
|
( 43 ? )
|
||
|
|
( 44 /sdram/M1_CLK# )
|
||
|
|
( 45 /fpga2/M1_CKE )
|
||
|
|
( 46 /sdram/M1_CLK )
|
||
|
|
( 47 /fpga2/M1_UDM )
|
||
|
|
( 48 GND )
|
||
|
|
( 49 /sdram/M1_VREF )
|
||
|
|
( 50 ? )
|
||
|
|
( 51 /fpga2/M1_UDQS )
|
||
|
|
( 52 GND )
|
||
|
|
( 53 ? )
|
||
|
|
( 54 /fpga2/M1_DQ8 )
|
||
|
|
( 55 +2.5V )
|
||
|
|
( 56 /sdram/M1_DQ9 )
|
||
|
|
( 57 /fpga2/M1_DQ10 )
|
||
|
|
( 58 GND )
|
||
|
|
( 59 /sdram/M1_DQ11 )
|
||
|
|
( 60 /fpga2/M1_DQ12 )
|
||
|
|
( 61 +2.5V )
|
||
|
|
( 62 /fpga2/M1_DQ13 )
|
||
|
|
( 63 /sdram/M1_DQ14 )
|
||
|
|
( 64 GND )
|
||
|
|
( 65 /sdram/M1_DQ15 )
|
||
|
|
( 66 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C65D28E 0402 C71 10nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61D1D4 1206 C34 10uF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61D151 1206 C33 10uF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 /sdram/M1_VREF )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R}
|
||
|
|
( 1 /sdram/M1_VREF )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R}
|
||
|
|
( 1 /sdram/M0_VREF )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 /sdram/M0_VREF )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 /sdram/M1_VREF )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP}
|
||
|
|
( 1 /sdram/M1_VREF )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP}
|
||
|
|
( 1 /sdram/M0_VREF )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 /sdram/M0_VREF )
|
||
|
|
)
|
||
|
|
( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 /fpga2/M0_DQ0 )
|
||
|
|
( 3 +2.5V )
|
||
|
|
( 4 /sdram/M0_DQ1 )
|
||
|
|
( 5 /fpga2/M0_DQ2 )
|
||
|
|
( 6 GND )
|
||
|
|
( 7 /fpga2/M0_DQ3 )
|
||
|
|
( 8 /sdram/M0_DQ4 )
|
||
|
|
( 9 +2.5V )
|
||
|
|
( 10 /sdram/M0_DQ5 )
|
||
|
|
( 11 /sdram/M0_DQ6 )
|
||
|
|
( 12 GND )
|
||
|
|
( 13 /sdram/M0_DQ7 )
|
||
|
|
( 14 ? )
|
||
|
|
( 15 +2.5V )
|
||
|
|
( 16 /fpga2/M0_LDQS )
|
||
|
|
( 17 ? )
|
||
|
|
( 18 +2.5V )
|
||
|
|
( 19 ? )
|
||
|
|
( 20 /sdram/M0_LDM )
|
||
|
|
( 21 /sdram/M0_WE# )
|
||
|
|
( 22 /sdram/M0_CAS# )
|
||
|
|
( 23 /fpga2/M0_RAS# )
|
||
|
|
( 24 GND )
|
||
|
|
( 25 ? )
|
||
|
|
( 26 /sdram/M0_BA0 )
|
||
|
|
( 27 /fpga2/M0_BA1 )
|
||
|
|
( 28 /fpga2/M0_A10 )
|
||
|
|
( 29 /sdram/M0_A0 )
|
||
|
|
( 30 /fpga2/M0_A1 )
|
||
|
|
( 31 /fpga2/M0_A2 )
|
||
|
|
( 32 /fpga2/M0_A3 )
|
||
|
|
( 33 +2.5V )
|
||
|
|
( 34 GND )
|
||
|
|
( 35 /sdram/M0_A4 )
|
||
|
|
( 36 /fpga2/M0_A5 )
|
||
|
|
( 37 /fpga2/M0_A6 )
|
||
|
|
( 38 /fpga2/M0_A7 )
|
||
|
|
( 39 /fpga2/M0_A8 )
|
||
|
|
( 40 /fpga2/M0_A9 )
|
||
|
|
( 41 /fpga2/M0_A11 )
|
||
|
|
( 42 /fpga2/M0_A12 )
|
||
|
|
( 43 ? )
|
||
|
|
( 44 /sdram/M0_CLK# )
|
||
|
|
( 45 /fpga2/M0_CKE )
|
||
|
|
( 46 /fpga2/M0_CLK )
|
||
|
|
( 47 /fpga2/M0_UDM )
|
||
|
|
( 48 GND )
|
||
|
|
( 49 /sdram/M0_VREF )
|
||
|
|
( 50 ? )
|
||
|
|
( 51 /fpga2/M0_UDQS )
|
||
|
|
( 52 GND )
|
||
|
|
( 53 ? )
|
||
|
|
( 54 /sdram/M0_DQ8 )
|
||
|
|
( 55 +2.5V )
|
||
|
|
( 56 /fpga2/M0_DQ9 )
|
||
|
|
( 57 /fpga2/M0_DQ10 )
|
||
|
|
( 58 GND )
|
||
|
|
( 59 /fpga2/M0_DQ11 )
|
||
|
|
( 60 /fpga2/M0_DQ12 )
|
||
|
|
( 61 +2.5V )
|
||
|
|
( 62 /sdram/M0_DQ13 )
|
||
|
|
( 63 /fpga2/M0_DQ14 )
|
||
|
|
( 64 GND )
|
||
|
|
( 65 /sdram/M0_DQ15 )
|
||
|
|
( 66 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D8114 0402 C9 100nF {Lib=C}
|
||
|
|
( 1 /ether/ETH_PLL1.8V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D810A 0402 L3 FB {Lib=INDUCTOR}
|
||
|
|
( 1 /ether/ETH_A1.8V )
|
||
|
|
( 2 /ether/ETH_PLL1.8V )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D8104 0402 C6 100nF {Lib=C}
|
||
|
|
( 1 /ether/ETH_A1.8V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D80F3 0402 L1 FB {Lib=INDUCTOR}
|
||
|
|
( 1 +1.8V )
|
||
|
|
( 2 /ether/ETH_A1.8V )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D80F0 0402 C4 100nF {Lib=C}
|
||
|
|
( 1 +1.8V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D80ED 0402 C2 1uF {Lib=C}
|
||
|
|
( 1 +1.8V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7FB7 0402 L2 FB {Lib=INDUCTOR}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 /ether/ETH_A3.3V )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C}
|
||
|
|
( 1 /ether/ETH_A3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C}
|
||
|
|
( 1 /ether/ETH_A3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7FA3 0402 C5 100nF {Lib=C}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7FA1 0402 C3 100nF {Lib=C}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7F9F 0603 C1 1uF {Lib=C}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7F39 0402 R1 4.7K {Lib=R}
|
||
|
|
( 1 /ether/ETH_MDIO )
|
||
|
|
( 2 +3.3V )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7ECF 0402 R2 6.65K {Lib=R}
|
||
|
|
( 1 N-000133 )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7E43 0402 C11 100nF {Lib=C}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7E41 0402 C10 100nF {Lib=C}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C}
|
||
|
|
( 1 /ether/MAG_SHIELD )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7DC4 0603 R9 1M {Lib=R}
|
||
|
|
( 1 /ether/MAG_SHIELD )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001}
|
||
|
|
( 1 /ether/ETH_MDIO )
|
||
|
|
( 2 /fpga1/ETH_MDC )
|
||
|
|
( 3 /fpga1/ETH_RXD3 )
|
||
|
|
( 4 /fpga1/ETH_RXD2 )
|
||
|
|
( 5 /fpga1/ETH_RXD1 )
|
||
|
|
( 6 /ether/ETH_RXD0 )
|
||
|
|
( 7 +3.3V )
|
||
|
|
( 8 GND )
|
||
|
|
( 9 /ether/ETH_RXDV )
|
||
|
|
( 10 /fpga1/ETH_RXC )
|
||
|
|
( 11 /ether/ETH_RXER )
|
||
|
|
( 12 GND )
|
||
|
|
( 13 +1.8V )
|
||
|
|
( 14 /ether/ETH_TXER )
|
||
|
|
( 15 /fpga1/ETH_TXC )
|
||
|
|
( 16 /fpga1/ETH_TXEN )
|
||
|
|
( 17 /fpga1/ETH_TXD0 )
|
||
|
|
( 18 /fpga1/ETH_TXD1 )
|
||
|
|
( 19 /fpga1/ETH_TXD2 )
|
||
|
|
( 20 /fpga1/ETH_TXD3 )
|
||
|
|
( 21 /fpga1/ETH_COL )
|
||
|
|
( 22 /ether/ETH_CRS )
|
||
|
|
( 23 GND )
|
||
|
|
( 24 +3.3V )
|
||
|
|
( 25 /ether/ETH_INT )
|
||
|
|
( 26 /ether/ETH_LED0 )
|
||
|
|
( 27 /ether/ETH_LED1 )
|
||
|
|
( 28 ? )
|
||
|
|
( 29 ? )
|
||
|
|
( 30 ? )
|
||
|
|
( 31 /ether/ETH_A1.8V )
|
||
|
|
( 32 /ether/MAG_RX- )
|
||
|
|
( 33 /ether/MAG_RX+ )
|
||
|
|
( 34 ? )
|
||
|
|
( 35 GND )
|
||
|
|
( 36 GND )
|
||
|
|
( 37 N-000133 )
|
||
|
|
( 38 /ether/ETH_A3.3V )
|
||
|
|
( 39 GND )
|
||
|
|
( 40 /ether/MAG_TX- )
|
||
|
|
( 41 /ether/MAG_TX+ )
|
||
|
|
( 42 ? )
|
||
|
|
( 43 ? )
|
||
|
|
( 44 GND )
|
||
|
|
( 45 ? )
|
||
|
|
( 46 /fpga1/ETH_CLK )
|
||
|
|
( 47 /ether/ETH_PLL1.8V )
|
||
|
|
( 48 /fpga1/ETH_RESET_N )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7AFE 0402 R3 49.9 {Lib=R}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 /ether/MAG_TX+ )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7AFC 0402 R4 49.9 {Lib=R}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 /ether/MAG_TX- )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7AF9 0402 R6 49.9 {Lib=R}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 /ether/MAG_RX- )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D7AF7 0402 R5 49.9 {Lib=R}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 /ether/MAG_RX+ )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D71DB 0402 R8 220 {Lib=R}
|
||
|
|
( 1 N-000120 )
|
||
|
|
( 2 /ether/ETH_LED1 )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D719D 0402 R7 220 {Lib=R}
|
||
|
|
( 1 N-000121 )
|
||
|
|
( 2 /ether/ETH_LED0 )
|
||
|
|
)
|
||
|
|
( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025}
|
||
|
|
( 1 /ether/MAG_TX+ )
|
||
|
|
( 2 /ether/MAG_TX- )
|
||
|
|
( 3 +3.3V )
|
||
|
|
( 4 GND )
|
||
|
|
( 5 GND )
|
||
|
|
( 6 +3.3V )
|
||
|
|
( 7 /ether/MAG_RX+ )
|
||
|
|
( 8 /ether/MAG_RX- )
|
||
|
|
( 9 +3.3V )
|
||
|
|
( 10 N-000121 )
|
||
|
|
( 11 +3.3V )
|
||
|
|
( 12 N-000120 )
|
||
|
|
( 13 /ether/MAG_SHIELD )
|
||
|
|
( 14 /ether/MAG_SHIELD )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C7D3661 0402 R53 15k {Lib=R}
|
||
|
|
( 1 GND )
|
||
|
|
( 2 /usb/USBD_D+ )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C7D3660 0402 R54 15k {Lib=R}
|
||
|
|
( 1 GND )
|
||
|
|
( 2 /usb/USBD_D- )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C7D365F $noname R55 15k {Lib=R}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 /usb/USBD_D+ )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C7D354D 0402 R49 24 {Lib=R}
|
||
|
|
( 1 /usb/USBD_D+ )
|
||
|
|
( 2 N-000146 )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C7D354C $noname R50 24 {Lib=R}
|
||
|
|
( 1 /usb/USBD_D- )
|
||
|
|
( 2 N-000145 )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C7D350E 0402 R52 24 {Lib=R}
|
||
|
|
( 1 /usb/USBA_D- )
|
||
|
|
( 2 N-000147 )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C7D3508 0402 R51 24 {Lib=R}
|
||
|
|
( 1 /usb/USBA_D+ )
|
||
|
|
( 2 N-000144 )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C7D32A3 0402 R48 15k {Lib=R}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 /usb/USBA_D+ )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C7D3098 0402 R47 15k {Lib=R}
|
||
|
|
( 1 GND )
|
||
|
|
( 2 /usb/USBA_D+ )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C7D3075 0402 R46 15k {Lib=R}
|
||
|
|
( 1 GND )
|
||
|
|
( 2 /usb/USBA_D- )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C75F027 ZX62D-B-5P8 J7 ZX62D-B-5P8 {Lib=ZX62D-B-5P8}
|
||
|
|
( 1 ? )
|
||
|
|
( 2 /usb/USBD_D- )
|
||
|
|
( 3 /usb/USBD_D+ )
|
||
|
|
( 4 N-000143 )
|
||
|
|
( 5 N-000143 )
|
||
|
|
( 6 /usb/USB_CASE_DEV )
|
||
|
|
( 7 /usb/USB_CASE_DEV )
|
||
|
|
( 8 /usb/USB_CASE_DEV )
|
||
|
|
( 9 /usb/USB_CASE_DEV )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C71BA25 MLF16 U7 MIC2550-MLF {Lib=MIC2550-MLF}
|
||
|
|
( 1 /usb/USBD_SPD )
|
||
|
|
( 2 /fpga2/USBD_RCV )
|
||
|
|
( 3 /usb/USBD_VP )
|
||
|
|
( 4 /usb/USBD_VM )
|
||
|
|
( 6 GND )
|
||
|
|
( 7 GND )
|
||
|
|
( 9 /usb/USBD_OE_N )
|
||
|
|
( 10 N-000145 )
|
||
|
|
( 11 N-000146 )
|
||
|
|
( 12 +3.3V )
|
||
|
|
( 14 +3.3V )
|
||
|
|
( 15 +2.5V )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C71BA1D MLF16 U6 MIC2550-MLF {Lib=MIC2550-MLF}
|
||
|
|
( 1 /usb/USBA_SPD )
|
||
|
|
( 2 /fpga2/USBA_RCV )
|
||
|
|
( 3 /fpga2/USBA_VP )
|
||
|
|
( 4 /fpga2/USBA_VM )
|
||
|
|
( 6 GND )
|
||
|
|
( 7 GND )
|
||
|
|
( 9 /usb/USBA_OE_N )
|
||
|
|
( 10 N-000147 )
|
||
|
|
( 11 N-000144 )
|
||
|
|
( 12 +3.3V )
|
||
|
|
( 14 +3.3V )
|
||
|
|
( 15 +2.5V )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C6552BD 0402 C36 100nF {Lib=C}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C6552BC 0402 C37 100nF {Lib=C}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C6552B9 0603 V4 V0402MHS03 {Lib=V0402MHS03}
|
||
|
|
( 1 /usb/USBD_D- )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C6552B8 0603 V3 V0402MHS03 {Lib=V0402MHS03}
|
||
|
|
( 1 /usb/USBD_D+ )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C6552B7 1206 C38 4.7nF {Lib=C}
|
||
|
|
( 1 /usb/USB_CASE_DEV )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C6552B6 0603 R15 1M {Lib=R}
|
||
|
|
( 1 /usb/USB_CASE_DEV )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR}
|
||
|
|
( 1 N-000143 )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR}
|
||
|
|
( 1 N-000150 )
|
||
|
|
( 2 N-000149 )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR}
|
||
|
|
( 1 N-000142 )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C5F2D27 0603 R10 1M {Lib=R}
|
||
|
|
( 1 /usb/USB_CASE_HOST )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C5F2D1E 0402 C16 4.7nF {Lib=C}
|
||
|
|
( 1 /usb/USB_CASE_HOST )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 {Lib=V0402MHS03}
|
||
|
|
( 1 /usb/USBA_D+ )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 {Lib=V0402MHS03}
|
||
|
|
( 1 /usb/USBA_D- )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F}
|
||
|
|
( 1 N-000150 )
|
||
|
|
( 2 +5V )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001}
|
||
|
|
( 1 N-000149 )
|
||
|
|
( 2 /usb/USBA_D- )
|
||
|
|
( 3 /usb/USBA_D+ )
|
||
|
|
( 4 N-000142 )
|
||
|
|
( S1 /usb/USB_CASE_HOST )
|
||
|
|
( S2 /usb/USB_CASE_HOST )
|
||
|
|
( S3 /usb/USB_CASE_HOST )
|
||
|
|
( S4 /usb/USB_CASE_HOST )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C5F2039 0402 C15 100nF {Lib=C}
|
||
|
|
( 1 +2.5V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C5F2037 0402 C14 100nF {Lib=C}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4C5F1EDC/4C5F2033 0603 C13 1uF {Lib=C}
|
||
|
|
( 1 +3.3V )
|
||
|
|
( 2 GND )
|
||
|
|
)
|
||
|
|
( /4CB0D95D/4CBAFE50 header25x2_smd_2mm P1 CONN_25X2 {Lib=CONN_25X2}
|
||
|
|
( 1 /expansion/FPGA_BANK0_IO_8 )
|
||
|
|
( 2 /expansion/FPGA_BANK0_IO_1 )
|
||
|
|
( 3 GND )
|
||
|
|
( 4 /expansion/FPGA_BANK0_IO_9 )
|
||
|
|
( 5 VCCO2 )
|
||
|
|
( 6 /expansion/FPGA_BANK0_IO_14 )
|
||
|
|
( 7 /expansion/FPGA_BANK0_IO_10 )
|
||
|
|
( 8 /expansion/FPGA_BANK0_IO_15 )
|
||
|
|
( 9 /fpga1/FPGA_BANK0_IO_11 )
|
||
|
|
( 10 /expansion/FPGA_BANK0_IO_3 )
|
||
|
|
( 11 /expansion/FPGA_BANK0_IO_5 )
|
||
|
|
( 12 /fpga1/FPGA_BANK0_IO_18 )
|
||
|
|
( 13 /expansion/FPGA_BANK0_IO_17 )
|
||
|
|
( 14 /expansion/FPGA_BANK0_IO_21 )
|
||
|
|
( 15 /fpga1/FPGA_BANK0_IO_20 )
|
||
|
|
( 16 /expansion/FPGA_BANK0_IO_24 )
|
||
|
|
( 17 /fpga1/FPGA_BANK0_IO_28 )
|
||
|
|
( 18 /expansion/FPGA_BANK0_IO_29 )
|
||
|
|
( 19 /fpga1/FPGA_BANK0_IO_22 )
|
||
|
|
( 20 /expansion/FPGA_BANK0_IO_30 )
|
||
|
|
( 21 /expansion/FPGA_BANK0_IO_27 )
|
||
|
|
( 22 /fpga1/FPGA_BANK0_IO_25 )
|
||
|
|
( 23 /expansion/FPGA_BANK0_IO_39 )
|
||
|
|
( 24 /fpga1/FPGA_BANK0_IO_33 )
|
||
|
|
( 25 /fpga1/FPGA_BANK0_IO_2 )
|
||
|
|
( 26 /expansion/FPGA_BANK0_IO_32 )
|
||
|
|
( 27 /fpga1/FPGA_BANK0_IO_7 )
|
||
|
|
( 28 /fpga1/FPGA_BANK0_IO_6 )
|
||
|
|
( 29 /expansion/FPGA_BANK0_IO_12 )
|
||
|
|
( 30 /expansion/FPGA_BANK0_IO_36 )
|
||
|
|
( 31 /fpga1/FPGA_BANK0_IO_44 )
|
||
|
|
( 32 /fpga1/FPGA_BANK0_IO_40 )
|
||
|
|
( 33 /expansion/FPGA_BANK0_IO_47 )
|
||
|
|
( 34 /expansion/FPGA_BANK0_IO_43 )
|
||
|
|
( 35 /expansion/FPGA_BANK0_IO_45 )
|
||
|
|
( 36 /expansion/FPGA_BANK0_IO_46 )
|
||
|
|
( 37 /fpga1/FPGA_BANK0_IO_52 )
|
||
|
|
( 38 /fpga1/FPGA_BANK0_IO_50 )
|
||
|
|
( 39 /fpga1/FPGA_BANK0_IO_56 )
|
||
|
|
( 40 /fpga1/FPGA_BANK0_IO_48 )
|
||
|
|
( 41 /fpga1/FPGA_BANK0_IO_51 )
|
||
|
|
( 42 /expansion/FPGA_BANK0_IO_34 )
|
||
|
|
( 43 /expansion/FPGA_BANK0_IO_54 )
|
||
|
|
( 44 /expansion/FPGA_BANK0_IO_49 )
|
||
|
|
( 45 /expansion/FPGA_BANK0_IO_63 )
|
||
|
|
( 46 /fpga1/FPGA_BANK0_IO_62 )
|
||
|
|
( 47 /expansion/FPGA_BANK0_IO_53 )
|
||
|
|
( 48 /expansion/FPGA_BANK0_IO_57 )
|
||
|
|
( 49 /fpga1/FPGA_BANK0_IO_58 )
|
||
|
|
( 50 /expansion/FPGA_BANK0_IO_60 )
|
||
|
|
)
|
||
|
|
)
|
||
|
|
*
|
||
|
|
{ Allowed footprints by component:
|
||
|
|
$component C156
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C94
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C92
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C93
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C91
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C90
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component R30
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R29
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component C77
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C76
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C66
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C63
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C60
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C57
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C54
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C69
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C67
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C64
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C61
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C58
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C55
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C68
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C65
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C62
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C59
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C56
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C50
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C47
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C44
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C41
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C53
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C51
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C49
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C46
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C52
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C43
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C40
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C48
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C45
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C42
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C39
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component R81
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R80
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R82
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R79
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R83
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R86
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R84
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R85
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R23
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R22
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R24
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R21
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R19
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R20
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R17
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R18
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R16
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component C75
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C74
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C73
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C72
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C70
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C71
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C34
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C33
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C28
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C29
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C31
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C30
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C32
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C27
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C21
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C26
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C24
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C25
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C23
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C22
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component R13
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R14
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R12
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R11
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component C19
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C20
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C18
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C17
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C9
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C6
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C4
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C2
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C8
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C7
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C5
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C3
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C1
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component R1
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R2
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component C11
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C10
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C12
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component R9
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R3
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R4
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R6
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R5
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R8
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R7
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R53
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R54
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R55
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R49
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R50
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R52
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R51
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R48
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R47
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R46
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component C35
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C36
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C37
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C38
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component R15
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component R10
|
||
|
|
R?
|
||
|
|
SM0603
|
||
|
|
SM0805
|
||
|
|
R?-*
|
||
|
|
$endlist
|
||
|
|
$component C16
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C15
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C14
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$component C13
|
||
|
|
SM*
|
||
|
|
C?
|
||
|
|
C1-1
|
||
|
|
$endlist
|
||
|
|
$endfootprintlist
|
||
|
|
}
|
||
|
|
{ Pin List by Nets
|
||
|
|
Net 1 "/fpga2/M0_CKE" "M0_CKE"
|
||
|
|
U2 45
|
||
|
|
R24 2
|
||
|
|
Net 2 "/sdram/M0_CAS#" "M0_CAS#"
|
||
|
|
U2 22
|
||
|
|
R83 2
|
||
|
|
Net 3 "/fpga2/M1_WE#" "M1_WE#"
|
||
|
|
U3 21
|
||
|
|
R80 2
|
||
|
|
Net 4 "/fpga2/M1_RAS#" "M1_RAS#"
|
||
|
|
U3 23
|
||
|
|
RP2 8
|
||
|
|
Net 5 "/fpga2/M0_RAS#" "M0_RAS#"
|
||
|
|
U2 23
|
||
|
|
RP15 8
|
||
|
|
Net 6 "/sdram/M0_WE#" "M0_WE#"
|
||
|
|
U2 21
|
||
|
|
R84 2
|
||
|
|
Net 7 "/flash/NF_RE_N" "NF_RE_N"
|
||
|
|
U1 C15
|
||
|
|
U5 8
|
||
|
|
Net 8 "/fpga1/NF_CS1_N" "NF_CS1_N"
|
||
|
|
U1 D15
|
||
|
|
U5 9
|
||
|
|
Net 9 "/fpga1/NF_ALE" "NF_ALE"
|
||
|
|
U5 17
|
||
|
|
U1 A14
|
||
|
|
Net 10 "/fpga2/M0_LDQS" "M0_LDQS"
|
||
|
|
R86 2
|
||
|
|
U2 16
|
||
|
|
Net 11 "/fpga2/M0_UDM" "M0_UDM"
|
||
|
|
U2 47
|
||
|
|
R23 2
|
||
|
|
Net 12 "/fpga2/M1_CKE" "M1_CKE"
|
||
|
|
U3 45
|
||
|
|
R17 2
|
||
|
|
Net 13 "/fpga2/M1_CAS#" "M1_CAS#"
|
||
|
|
U3 22
|
||
|
|
R79 2
|
||
|
|
Net 14 "/fpga1/SD_CLK" "SD_CLK"
|
||
|
|
J1 5
|
||
|
|
U1 A17
|
||
|
|
Net 15 "/sdram/M0_CLK#" "M0_CLK#"
|
||
|
|
U1 H3
|
||
|
|
R21 2
|
||
|
|
U2 44
|
||
|
|
Net 16 "/fpga2/M0_CLK" "M0_CLK"
|
||
|
|
U2 46
|
||
|
|
U1 H4
|
||
|
|
R21 1
|
||
|
|
Net 17 "/sdram/M1_CLK#" "M1_CLK#"
|
||
|
|
U3 44
|
||
|
|
U1 J19
|
||
|
|
R16 1
|
||
|
|
Net 18 "/sdram/M1_CLK" "M1_CLK"
|
||
|
|
U3 46
|
||
|
|
U1 H20
|
||
|
|
R16 2
|
||
|
|
Net 19 "/usb/USBD_VM" "USBD_VM"
|
||
|
|
U1 B22
|
||
|
|
U7 4
|
||
|
|
Net 20 "/sdram/M0_LDM" "M0_LDM"
|
||
|
|
U2 20
|
||
|
|
R85 2
|
||
|
|
Net 21 "/fpga2/M0_UDQS" "M0_UDQS"
|
||
|
|
R22 2
|
||
|
|
U2 51
|
||
|
|
Net 22 "/fpga2/M1_UDQS" "M1_UDQS"
|
||
|
|
U3 51
|
||
|
|
R19 2
|
||
|
|
Net 23 "/sdram/M1_LDM" "M1_LDM"
|
||
|
|
U3 20
|
||
|
|
R81 2
|
||
|
|
Net 24 "/fpga2/M1_LDQS" "M1_LDQS"
|
||
|
|
U3 16
|
||
|
|
R82 2
|
||
|
|
Net 25 "/fpga2/M1_UDM" "M1_UDM"
|
||
|
|
R18 2
|
||
|
|
U3 47
|
||
|
|
Net 26 "/sdram/M1_CS#" "M1_CS#"
|
||
|
|
U3 24
|
||
|
|
R20 2
|
||
|
|
Net 27 "/usb/USBD_VP" "USBD_VP"
|
||
|
|
U7 3
|
||
|
|
U1 B21
|
||
|
|
Net 28 "/fpga2/USBD_RCV" "USBD_RCV"
|
||
|
|
U7 2
|
||
|
|
U1 A20
|
||
|
|
Net 29 "/usb/USBD_OE_N" "USBD_OE_N"
|
||
|
|
U7 9
|
||
|
|
U1 A21
|
||
|
|
Net 30 "/usb/USBD_SPD" "USBD_SPD"
|
||
|
|
U1 B20
|
||
|
|
U7 1
|
||
|
|
Net 31 "/fpga2/USBA_VM" "USBA_VM"
|
||
|
|
U6 4
|
||
|
|
U1 D20
|
||
|
|
Net 32 "/fpga2/USBA_VP" "USBA_VP"
|
||
|
|
U1 D19
|
||
|
|
U6 3
|
||
|
|
Net 33 "/fpga2/USBA_RCV" "USBA_RCV"
|
||
|
|
U6 2
|
||
|
|
U1 F17
|
||
|
|
Net 34 "/usb/USBA_OE_N" "USBA_OE_N"
|
||
|
|
U6 9
|
||
|
|
U1 C19
|
||
|
|
Net 35 "/usb/USBA_SPD" "USBA_SPD"
|
||
|
|
U1 F16
|
||
|
|
U6 1
|
||
|
|
Net 36 "/ether/ETH_INT" "ETH_INT"
|
||
|
|
U1 A10
|
||
|
|
U4 25
|
||
|
|
Net 37 "/fpga1/ETH_RESET_N" "ETH_RESET_N"
|
||
|
|
U4 48
|
||
|
|
U1 C7
|
||
|
|
Net 38 "/fpga1/ETH_COL" "ETH_COL"
|
||
|
|
U4 21
|
||
|
|
U1 A9
|
||
|
|
Net 39 "/ether/ETH_MDIO" "ETH_MDIO"
|
||
|
|
R1 1
|
||
|
|
U4 1
|
||
|
|
U1 D6
|
||
|
|
Net 40 "/fpga1/ETH_MDC" "ETH_MDC"
|
||
|
|
U4 2
|
||
|
|
U1 D7
|
||
|
|
Net 41 "/fpga1/PROG_CSO" "PROG_CSO"
|
||
|
|
U8 1
|
||
|
|
U1 T5
|
||
|
|
Net 42 "/fpga1/PROG_CCLK" "PROG_CCLK"
|
||
|
|
U1 AA21
|
||
|
|
U8 6
|
||
|
|
Net 54 "/ether/ETH_RXDV" "ETH_RXDV"
|
||
|
|
U4 9
|
||
|
|
U1 A6
|
||
|
|
Net 55 "/ether/ETH_RXER" "ETH_RXER"
|
||
|
|
U1 B8
|
||
|
|
U4 11
|
||
|
|
Net 56 "/ether/ETH_TXER" "ETH_TXER"
|
||
|
|
U4 14
|
||
|
|
U1 D8
|
||
|
|
Net 57 "/fpga1/ETH_TXEN" "ETH_TXEN"
|
||
|
|
U4 16
|
||
|
|
U1 D9
|
||
|
|
Net 58 "/fpga1/ETH_TXC" "ETH_TXC"
|
||
|
|
U1 C8
|
||
|
|
U4 15
|
||
|
|
Net 59 "/fpga1/ETH_RXC" "ETH_RXC"
|
||
|
|
U1 A7
|
||
|
|
U4 10
|
||
|
|
Net 60 "/fpga1/ETH_CLK" "ETH_CLK"
|
||
|
|
U4 46
|
||
|
|
U1 A4
|
||
|
|
Net 61 "/ether/ETH_CRS" "ETH_CRS"
|
||
|
|
U4 22
|
||
|
|
U1 B10
|
||
|
|
Net 62 "/flash/NF_WE_N" "NF_WE_N"
|
||
|
|
U1 C14
|
||
|
|
U5 18
|
||
|
|
Net 63 "/flash/NF_CLE" "NF_CLE"
|
||
|
|
U5 16
|
||
|
|
U1 B14
|
||
|
|
Net 64 "/fpga1/NF_RNB" "NF_RNB"
|
||
|
|
U1 A15
|
||
|
|
U5 6
|
||
|
|
U5 7
|
||
|
|
Net 65 "/flash/SD_CMD" "SD_CMD"
|
||
|
|
J1 3
|
||
|
|
U1 C16
|
||
|
|
Net 73 "+2.5V" "+2.5V"
|
||
|
|
U3 15
|
||
|
|
U3 18
|
||
|
|
U1 J18
|
||
|
|
U1 L7
|
||
|
|
U1 W21
|
||
|
|
U3 55
|
||
|
|
U3 1
|
||
|
|
U1 R21
|
||
|
|
U1 E19
|
||
|
|
U3 61
|
||
|
|
U1 U18
|
||
|
|
U1 N18
|
||
|
|
U3 9
|
||
|
|
U3 3
|
||
|
|
U1 N5
|
||
|
|
U1 J5
|
||
|
|
U1 L21
|
||
|
|
U1 G21
|
||
|
|
U1 C21
|
||
|
|
U3 33
|
||
|
|
U1 F6
|
||
|
|
U1 U5
|
||
|
|
U1 U11
|
||
|
|
C56 1
|
||
|
|
U1 G12
|
||
|
|
U1 N8
|
||
|
|
U1 H9
|
||
|
|
C59 1
|
||
|
|
U1 F4
|
||
|
|
U1 R10
|
||
|
|
U1 H15
|
||
|
|
U1 K15
|
||
|
|
U1 M15
|
||
|
|
U1 D16
|
||
|
|
U1 R12
|
||
|
|
C15 1
|
||
|
|
C37 1
|
||
|
|
C17 1
|
||
|
|
C19 1
|
||
|
|
R11 1
|
||
|
|
R13 1
|
||
|
|
C46 1
|
||
|
|
C49 1
|
||
|
|
U2 9
|
||
|
|
U2 1
|
||
|
|
U2 3
|
||
|
|
C51 1
|
||
|
|
C53 1
|
||
|
|
U1 W2
|
||
|
|
U1 F11
|
||
|
|
U1 L8
|
||
|
|
U7 15
|
||
|
|
U1 L2
|
||
|
|
U1 R2
|
||
|
|
U6 15
|
||
|
|
C68 1
|
||
|
|
C65 1
|
||
|
|
C62 1
|
||
|
|
C40 1
|
||
|
|
C43 1
|
||
|
|
C52 1
|
||
|
|
C54 1
|
||
|
|
C57 1
|
||
|
|
C60 1
|
||
|
|
C63 1
|
||
|
|
C66 1
|
||
|
|
U1 C2
|
||
|
|
U1 G2
|
||
|
|
U1 R6
|
||
|
|
U1 V6
|
||
|
|
C31 1
|
||
|
|
C29 1
|
||
|
|
C28 1
|
||
|
|
C33 1
|
||
|
|
C22 1
|
||
|
|
C23 1
|
||
|
|
C25 1
|
||
|
|
C24 1
|
||
|
|
C26 1
|
||
|
|
C77 1
|
||
|
|
C21 1
|
||
|
|
U1 L16
|
||
|
|
C27 1
|
||
|
|
C32 1
|
||
|
|
C30 1
|
||
|
|
U2 55
|
||
|
|
U2 18
|
||
|
|
U2 61
|
||
|
|
C94 1
|
||
|
|
C70 1
|
||
|
|
C71 1
|
||
|
|
C34 1
|
||
|
|
U2 33
|
||
|
|
U2 15
|
||
|
|
Net 87 "/sdram/M0_VREF" "M0_VREF"
|
||
|
|
R11 2
|
||
|
|
R12 1
|
||
|
|
C17 2
|
||
|
|
C18 1
|
||
|
|
U2 49
|
||
|
|
Net 88 "/sdram/M1_VREF" "M1_VREF"
|
||
|
|
C20 1
|
||
|
|
C19 2
|
||
|
|
R13 2
|
||
|
|
R14 1
|
||
|
|
U3 49
|
||
|
|
Net 119 "+3.3V" "+3.3V"
|
||
|
|
R3 1
|
||
|
|
C50 1
|
||
|
|
C47 1
|
||
|
|
C44 1
|
||
|
|
C41 1
|
||
|
|
R4 1
|
||
|
|
U5 37
|
||
|
|
U1 B4
|
||
|
|
U1 B7
|
||
|
|
U7 14
|
||
|
|
U7 12
|
||
|
|
U1 E13
|
||
|
|
U1 G14
|
||
|
|
U1 B15
|
||
|
|
C91 1
|
||
|
|
C90 1
|
||
|
|
U1 G10
|
||
|
|
U6 14
|
||
|
|
U6 12
|
||
|
|
U1 E9
|
||
|
|
U1 B19
|
||
|
|
U1 E17
|
||
|
|
U4 24
|
||
|
|
U4 7
|
||
|
|
U1 B11
|
||
|
|
R48 1
|
||
|
|
R1 2
|
||
|
|
C11 1
|
||
|
|
C10 1
|
||
|
|
L2 1
|
||
|
|
C5 1
|
||
|
|
C3 1
|
||
|
|
C1 1
|
||
|
|
C73 1
|
||
|
|
U1 Y20
|
||
|
|
C72 1
|
||
|
|
C36 1
|
||
|
|
J4 6
|
||
|
|
J4 9
|
||
|
|
J4 11
|
||
|
|
C75 2
|
||
|
|
C74 1
|
||
|
|
R55 1
|
||
|
|
J1 4
|
||
|
|
C13 1
|
||
|
|
R5 1
|
||
|
|
R6 1
|
||
|
|
R29 1
|
||
|
|
R30 1
|
||
|
|
C35 1
|
||
|
|
U5 19
|
||
|
|
U5 12
|
||
|
|
J4 3
|
||
|
|
C14 1
|
||
|
|
Net 120 "" ""
|
||
|
|
R8 1
|
||
|
|
J4 12
|
||
|
|
Net 121 "" ""
|
||
|
|
R7 1
|
||
|
|
J4 10
|
||
|
|
Net 124 "/ether/ETH_PLL1.8V" "ETH_PLL1.8V"
|
||
|
|
L3 2
|
||
|
|
U4 47
|
||
|
|
C9 1
|
||
|
|
Net 125 "+1.8V" "+1.8V"
|
||
|
|
U4 13
|
||
|
|
L1 1
|
||
|
|
C4 1
|
||
|
|
C2 1
|
||
|
|
Net 126 "/ether/ETH_A1.8V" "ETH_A1.8V"
|
||
|
|
C6 1
|
||
|
|
L1 2
|
||
|
|
L3 1
|
||
|
|
U4 31
|
||
|
|
Net 130 "/ether/MAG_RX-" "MAG_RX-"
|
||
|
|
R6 2
|
||
|
|
U4 32
|
||
|
|
J4 8
|
||
|
|
Net 133 "" ""
|
||
|
|
R2 1
|
||
|
|
U4 37
|
||
|
|
Net 134 "/ether/MAG_TX-" "MAG_TX-"
|
||
|
|
R4 2
|
||
|
|
J4 2
|
||
|
|
U4 40
|
||
|
|
Net 135 "/ether/ETH_LED1" "ETH_LED1"
|
||
|
|
U4 27
|
||
|
|
R8 2
|
||
|
|
Net 136 "/ether/ETH_A3.3V" "ETH_A3.3V"
|
||
|
|
C7 1
|
||
|
|
C8 1
|
||
|
|
L2 2
|
||
|
|
U4 38
|
||
|
|
Net 137 "/ether/MAG_TX+" "MAG_TX+"
|
||
|
|
R3 2
|
||
|
|
J4 1
|
||
|
|
U4 41
|
||
|
|
Net 138 "/ether/ETH_LED0" "ETH_LED0"
|
||
|
|
U4 26
|
||
|
|
R7 2
|
||
|
|
Net 139 "/ether/MAG_RX+" "MAG_RX+"
|
||
|
|
J4 7
|
||
|
|
R5 2
|
||
|
|
U4 33
|
||
|
|
Net 140 "/ether/MAG_SHIELD" "MAG_SHIELD"
|
||
|
|
J4 13
|
||
|
|
J4 14
|
||
|
|
C12 1
|
||
|
|
R9 1
|
||
|
|
Net 142 "" ""
|
||
|
|
J5 4
|
||
|
|
L5 1
|
||
|
|
Net 143 "" ""
|
||
|
|
L7 1
|
||
|
|
J7 4
|
||
|
|
J7 5
|
||
|
|
Net 144 "" ""
|
||
|
|
U6 11
|
||
|
|
R51 2
|
||
|
|
Net 145 "" ""
|
||
|
|
U7 10
|
||
|
|
R50 2
|
||
|
|
Net 146 "" ""
|
||
|
|
R49 2
|
||
|
|
U7 11
|
||
|
|
Net 147 "" ""
|
||
|
|
U6 10
|
||
|
|
R52 2
|
||
|
|
Net 149 "" ""
|
||
|
|
J5 1
|
||
|
|
L4 2
|
||
|
|
Net 150 "" ""
|
||
|
|
L4 1
|
||
|
|
F1 1
|
||
|
|
Net 151 "/usb/USB_CASE_HOST" "USB_CASE_HOST"
|
||
|
|
C16 1
|
||
|
|
R10 1
|
||
|
|
J5 S1
|
||
|
|
J5 S2
|
||
|
|
J5 S3
|
||
|
|
J5 S4
|
||
|
|
Net 152 "/usb/USB_CASE_DEV" "USB_CASE_DEV"
|
||
|
|
J7 9
|
||
|
|
J7 8
|
||
|
|
J7 7
|
||
|
|
J7 6
|
||
|
|
R15 1
|
||
|
|
C38 1
|
||
|
|
Net 153 "/usb/USBD_D-" "USBD_D-"
|
||
|
|
R50 1
|
||
|
|
R54 2
|
||
|
|
J7 2
|
||
|
|
V4 1
|
||
|
|
V4 1
|
||
|
|
Net 154 "/usb/USBA_D-" "USBA_D-"
|
||
|
|
R52 1
|
||
|
|
J5 2
|
||
|
|
V2 1
|
||
|
|
V2 1
|
||
|
|
R46 2
|
||
|
|
Net 155 "/usb/USBA_D+" "USBA_D+"
|
||
|
|
R51 1
|
||
|
|
R48 2
|
||
|
|
R47 2
|
||
|
|
V1 1
|
||
|
|
V1 1
|
||
|
|
J5 3
|
||
|
|
Net 156 "/usb/USBD_D+" "USBD_D+"
|
||
|
|
J7 3
|
||
|
|
V3 1
|
||
|
|
R53 2
|
||
|
|
V3 1
|
||
|
|
R49 1
|
||
|
|
R55 2
|
||
|
|
Net 170 "" ""
|
||
|
|
U9 1
|
||
|
|
U9 1
|
||
|
|
U9 1
|
||
|
|
U9 1
|
||
|
|
U9 1
|
||
|
|
Net 200 "/fpga2/R_M1_A7" "R_M1_A7"
|
||
|
|
U1 E20
|
||
|
|
RP6 8
|
||
|
|
Net 201 "/fpga2/R_M1_A8" "R_M1_A8"
|
||
|
|
RP7 5
|
||
|
|
U1 C20
|
||
|
|
Net 202 "/fpga2/R_M1_A9" "R_M1_A9"
|
||
|
|
U1 C22
|
||
|
|
RP7 6
|
||
|
|
Net 203 "/fpga2/R_M1_A11" "R_M1_A11"
|
||
|
|
RP7 7
|
||
|
|
U1 F19
|
||
|
|
Net 204 "/fpga2/R_M1_A12" "R_M1_A12"
|
||
|
|
U1 D22
|
||
|
|
RP7 8
|
||
|
|
Net 205 "/fpga2/R_M1_A4" "R_M1_A4"
|
||
|
|
RP6 5
|
||
|
|
U1 F20
|
||
|
|
Net 206 "/fpga2/R_M1_A5" "R_M1_A5"
|
||
|
|
U1 K20
|
||
|
|
RP6 6
|
||
|
|
Net 207 "/fpga2/R_M1_A6" "R_M1_A6"
|
||
|
|
U1 K19
|
||
|
|
RP6 7
|
||
|
|
Net 208 "/fpga2/R_M1_A10" "R_M1_A10"
|
||
|
|
U1 G19
|
||
|
|
RP2 4
|
||
|
|
Net 209 "/fpga2/R_M1_A0" "R_M1_A0"
|
||
|
|
U1 F21
|
||
|
|
RP1 1
|
||
|
|
Net 210 "/fpga2/R_M1_A1" "R_M1_A1"
|
||
|
|
U1 F22
|
||
|
|
RP1 2
|
||
|
|
Net 211 "/fpga2/R_M1_A2" "R_M1_A2"
|
||
|
|
U1 E22
|
||
|
|
RP1 3
|
||
|
|
Net 212 "/fpga2/R_M1_A3" "R_M1_A3"
|
||
|
|
RP1 4
|
||
|
|
U1 G20
|
||
|
|
Net 213 "/fpga2/R_M1_BA0" "R_M1_BA0"
|
||
|
|
U1 J17
|
||
|
|
RP2 2
|
||
|
|
Net 214 "/fpga2/R_M1_BA1" "R_M1_BA1"
|
||
|
|
RP2 3
|
||
|
|
U1 K17
|
||
|
|
Net 217 "/fpga2/R_M1_DQ4" "R_M1_DQ4"
|
||
|
|
RP4 1
|
||
|
|
U1 J20
|
||
|
|
Net 218 "/fpga2/R_M1_LDQS" "R_M1_LDQS"
|
||
|
|
U1 L20
|
||
|
|
R82 1
|
||
|
|
Net 219 "/fpga2/R_M1_UDM" "R_M1_UDM"
|
||
|
|
R18 1
|
||
|
|
U1 M20
|
||
|
|
Net 220 "/fpga2/R_M1_DQ0" "R_M1_DQ0"
|
||
|
|
RP5 1
|
||
|
|
U1 N20
|
||
|
|
Net 222 "/fpga2/R_M1_DQ10" "R_M1_DQ10"
|
||
|
|
U1 R20
|
||
|
|
RP9 7
|
||
|
|
Net 224 "/fpga2/R_M1_DQ12" "R_M1_DQ12"
|
||
|
|
RP8 5
|
||
|
|
U1 U20
|
||
|
|
Net 227 "/fpga2/R_M1_CKE" "R_M1_CKE"
|
||
|
|
R17 1
|
||
|
|
U1 D21
|
||
|
|
Net 228 "/fpga2/R_M1_RAS#" "R_M1_RAS#"
|
||
|
|
U1 H21
|
||
|
|
RP2 1
|
||
|
|
Net 229 "/fpga2/R_M1_DQ6" "R_M1_DQ6"
|
||
|
|
U1 K21
|
||
|
|
RP4 3
|
||
|
|
Net 230 "/fpga2/R_M1_DQ2" "R_M1_DQ2"
|
||
|
|
U1 M21
|
||
|
|
RP5 3
|
||
|
|
Net 236 "/fpga2/R_M0_A2" "R_M0_A2"
|
||
|
|
RP14 3
|
||
|
|
U1 H5
|
||
|
|
Net 241 "/fpga2/R_M0_A7" "R_M0_A7"
|
||
|
|
RP17 1
|
||
|
|
U1 H6
|
||
|
|
Net 243 "/fpga2/R_M0_A3" "R_M0_A3"
|
||
|
|
U1 K6
|
||
|
|
RP14 4
|
||
|
|
Net 267 "/fpga2/R_M1_WE#" "R_M1_WE#"
|
||
|
|
U1 H19
|
||
|
|
R80 1
|
||
|
|
Net 268 "/fpga2/R_M1_LDM" "R_M1_LDM"
|
||
|
|
U1 L19
|
||
|
|
R81 1
|
||
|
|
Net 275 "/fpga2/R_M1_DQ8" "R_M1_DQ8"
|
||
|
|
U1 P21
|
||
|
|
RP9 5
|
||
|
|
Net 276 "/fpga2/R_M1_DQ14" "R_M1_DQ14"
|
||
|
|
RP8 7
|
||
|
|
U1 V21
|
||
|
|
Net 278 "/fpga2/R_M1_CAS#" "R_M1_CAS#"
|
||
|
|
U1 H22
|
||
|
|
R79 1
|
||
|
|
Net 279 "/fpga2/R_M1_DQ5" "R_M1_DQ5"
|
||
|
|
U1 J22
|
||
|
|
RP4 2
|
||
|
|
Net 280 "/fpga2/R_M1_DQ7" "R_M1_DQ7"
|
||
|
|
U1 K22
|
||
|
|
RP4 4
|
||
|
|
Net 282 "/fpga2/R_M1_DQ3" "R_M1_DQ3"
|
||
|
|
U1 M22
|
||
|
|
RP5 4
|
||
|
|
Net 283 "/fpga2/R_M1_DQ1" "R_M1_DQ1"
|
||
|
|
U1 N22
|
||
|
|
RP5 2
|
||
|
|
Net 284 "/fpga2/R_M1_DQ9" "R_M1_DQ9"
|
||
|
|
U1 P22
|
||
|
|
RP9 6
|
||
|
|
Net 285 "/fpga2/R_M1_DQ11" "R_M1_DQ11"
|
||
|
|
RP9 8
|
||
|
|
U1 R22
|
||
|
|
Net 287 "/fpga2/R_M1_DQ13" "R_M1_DQ13"
|
||
|
|
RP8 6
|
||
|
|
U1 U22
|
||
|
|
Net 288 "/fpga2/R_M1_DQ15" "R_M1_DQ15"
|
||
|
|
U1 V22
|
||
|
|
RP8 8
|
||
|
|
Net 301 "/fpga2/R_M0_A8" "R_M0_A8"
|
||
|
|
RP18 4
|
||
|
|
U1 E3
|
||
|
|
Net 302 "/fpga2/R_M0_A4" "R_M0_A4"
|
||
|
|
RP17 4
|
||
|
|
U1 F3
|
||
|
|
Net 303 "/fpga2/R_M0_BA0" "R_M0_BA0"
|
||
|
|
RP15 2
|
||
|
|
U1 G3
|
||
|
|
Net 304 "/fpga2/R_M0_DQ4" "R_M0_DQ4"
|
||
|
|
U1 J3
|
||
|
|
RP12 1
|
||
|
|
Net 305 "/fpga2/R_M0_A5" "R_M0_A5"
|
||
|
|
U1 K3
|
||
|
|
RP17 3
|
||
|
|
Net 306 "/fpga2/R_M0_DQ0" "R_M0_DQ0"
|
||
|
|
U1 N3
|
||
|
|
RP13 1
|
||
|
|
Net 308 "/fpga2/R_M0_DQ10" "R_M0_DQ10"
|
||
|
|
RP11 3
|
||
|
|
U1 R3
|
||
|
|
Net 310 "/fpga2/R_M0_DQ12" "R_M0_DQ12"
|
||
|
|
RP10 1
|
||
|
|
U1 U3
|
||
|
|
Net 315 "/fpga2/R_M0_A10" "R_M0_A10"
|
||
|
|
U1 G4
|
||
|
|
RP15 4
|
||
|
|
Net 316 "/fpga2/R_M0_A6" "R_M0_A6"
|
||
|
|
U1 J4
|
||
|
|
RP17 2
|
||
|
|
Net 321 "/fpga2/R_M0_A11" "R_M0_A11"
|
||
|
|
RP18 2
|
||
|
|
U1 C1
|
||
|
|
Net 322 "/fpga2/R_M0_A12" "R_M0_A12"
|
||
|
|
U1 D1
|
||
|
|
RP18 1
|
||
|
|
Net 323 "/fpga2/R_M0_A9" "R_M0_A9"
|
||
|
|
RP18 3
|
||
|
|
U1 E1
|
||
|
|
Net 325 "/fpga2/R_M0_BA1" "R_M0_BA1"
|
||
|
|
RP15 3
|
||
|
|
U1 G1
|
||
|
|
Net 326 "/fpga2/R_M0_A1" "R_M0_A1"
|
||
|
|
U1 H1
|
||
|
|
RP14 2
|
||
|
|
Net 327 "/fpga2/R_M0_DQ5" "R_M0_DQ5"
|
||
|
|
U1 J1
|
||
|
|
RP12 2
|
||
|
|
Net 328 "/fpga2/R_M0_DQ7" "R_M0_DQ7"
|
||
|
|
RP12 4
|
||
|
|
U1 K1
|
||
|
|
Net 330 "/fpga2/R_M0_DQ3" "R_M0_DQ3"
|
||
|
|
U1 M1
|
||
|
|
RP13 4
|
||
|
|
Net 331 "/fpga2/R_M0_DQ1" "R_M0_DQ1"
|
||
|
|
U1 N1
|
||
|
|
RP13 2
|
||
|
|
Net 332 "/fpga2/R_M0_DQ9" "R_M0_DQ9"
|
||
|
|
U1 P1
|
||
|
|
RP11 2
|
||
|
|
Net 333 "/fpga2/R_M0_DQ11" "R_M0_DQ11"
|
||
|
|
U1 R1
|
||
|
|
RP11 4
|
||
|
|
Net 335 "/fpga2/R_M0_DQ13" "R_M0_DQ13"
|
||
|
|
U1 U1
|
||
|
|
RP10 2
|
||
|
|
Net 336 "/fpga2/R_M0_DQ15" "R_M0_DQ15"
|
||
|
|
RP10 4
|
||
|
|
U1 V1
|
||
|
|
Net 341 "/fpga2/R_M0_A0" "R_M0_A0"
|
||
|
|
RP14 1
|
||
|
|
U1 H2
|
||
|
|
Net 342 "/fpga2/R_M0_DQ6" "R_M0_DQ6"
|
||
|
|
U1 K2
|
||
|
|
RP12 3
|
||
|
|
Net 343 "/fpga2/R_M0_DQ2" "R_M0_DQ2"
|
||
|
|
U1 M2
|
||
|
|
RP13 3
|
||
|
|
Net 344 "/fpga2/R_M0_DQ8" "R_M0_DQ8"
|
||
|
|
RP11 1
|
||
|
|
U1 P2
|
||
|
|
Net 345 "/fpga2/R_M0_DQ14" "R_M0_DQ14"
|
||
|
|
U1 V2
|
||
|
|
RP10 3
|
||
|
|
Net 346 "/fpga2/R_M0_RAS#" "R_M0_RAS#"
|
||
|
|
U1 K5
|
||
|
|
RP15 1
|
||
|
|
Net 347 "/fpga2/R_M0_LDM" "R_M0_LDM"
|
||
|
|
R85 1
|
||
|
|
U1 L4
|
||
|
|
Net 348 "/fpga2/R_M0_CAS#" "R_M0_CAS#"
|
||
|
|
R83 1
|
||
|
|
U1 K4
|
||
|
|
Net 349 "/fpga2/R_M0_WE#" "R_M0_WE#"
|
||
|
|
U1 F2
|
||
|
|
R84 1
|
||
|
|
Net 350 "/fpga2/R_M1_UDQS" "R_M1_UDQS"
|
||
|
|
U1 T21
|
||
|
|
R19 1
|
||
|
|
Net 351 "/fpga2/R_M1_CS#" "R_M1_CS#"
|
||
|
|
R20 1
|
||
|
|
U1 H16
|
||
|
|
Net 352 "/fpga2/R_M0_LDQS" "R_M0_LDQS"
|
||
|
|
R86 1
|
||
|
|
U1 L3
|
||
|
|
Net 353 "/fpga2/R_M0_UDQS" "R_M0_UDQS"
|
||
|
|
U1 T2
|
||
|
|
R22 1
|
||
|
|
Net 354 "/fpga2/R_M0_CKE" "R_M0_CKE"
|
||
|
|
R24 1
|
||
|
|
U1 D2
|
||
|
|
Net 355 "/fpga2/R_M0_UDM" "R_M0_UDM"
|
||
|
|
U1 M3
|
||
|
|
R23 1
|
||
|
|
Net 356 "" ""
|
||
|
|
R29 2
|
||
|
|
U1 AA1
|
||
|
|
Net 359 "" ""
|
||
|
|
R30 2
|
||
|
|
U1 Y22
|
||
|
|
Net 364 "+1.2V" "+1.2V"
|
||
|
|
C93 1
|
||
|
|
C92 1
|
||
|
|
U1 J8
|
||
|
|
U1 P13
|
||
|
|
C39 1
|
||
|
|
U1 M13
|
||
|
|
U1 M11
|
||
|
|
U1 P11
|
||
|
|
U1 N12
|
||
|
|
U1 L12
|
||
|
|
U1 J12
|
||
|
|
U1 K9
|
||
|
|
U1 M9
|
||
|
|
U1 P9
|
||
|
|
C45 1
|
||
|
|
C48 1
|
||
|
|
U1 R14
|
||
|
|
U1 N14
|
||
|
|
U1 L14
|
||
|
|
U1 J14
|
||
|
|
U1 J10
|
||
|
|
U1 L10
|
||
|
|
U1 N10
|
||
|
|
C42 1
|
||
|
|
C76 1
|
||
|
|
U1 K13
|
||
|
|
U1 K11
|
||
|
|
Net 397 "/fpga2/M1_BA1" "M1_BA1"
|
||
|
|
RP2 6
|
||
|
|
U3 27
|
||
|
|
Net 398 "/fpga2/M1_BA0" "M1_BA0"
|
||
|
|
U3 26
|
||
|
|
RP2 7
|
||
|
|
Net 399 "/fpga2/M0_BA1" "M0_BA1"
|
||
|
|
U2 27
|
||
|
|
RP15 6
|
||
|
|
Net 400 "/sdram/M0_BA0" "M0_BA0"
|
||
|
|
RP15 7
|
||
|
|
U2 26
|
||
|
|
Net 401 "/fpga1/PROG_MISO3" "PROG_MISO3"
|
||
|
|
U8 7
|
||
|
|
U1 U13
|
||
|
|
Net 402 "/fpga1/PROG_MISO2" "PROG_MISO2"
|
||
|
|
U8 3
|
||
|
|
U1 U14
|
||
|
|
Net 403 "/fpga1/PROG_MISO1" "PROG_MISO1"
|
||
|
|
U8 2
|
||
|
|
U1 AA20
|
||
|
|
Net 404 "/fpga1/PROG_MISO0" "PROG_MISO0"
|
||
|
|
U8 5
|
||
|
|
U1 AB20
|
||
|
|
Net 405 "/fpga1/NF_D7" "NF_D7"
|
||
|
|
U1 D11
|
||
|
|
U5 44
|
||
|
|
Net 406 "/fpga1/NF_D6" "NF_D6"
|
||
|
|
U1 A11
|
||
|
|
U5 43
|
||
|
|
Net 407 "/flash/NF_D5" "NF_D5"
|
||
|
|
U5 42
|
||
|
|
U1 C11
|
||
|
|
Net 408 "/flash/NF_D4" "NF_D4"
|
||
|
|
U1 A12
|
||
|
|
U5 41
|
||
|
|
Net 409 "/fpga1/NF_D3" "NF_D3"
|
||
|
|
U1 B12
|
||
|
|
U5 32
|
||
|
|
Net 410 "/fpga2/M0_A12" "M0_A12"
|
||
|
|
U2 42
|
||
|
|
RP18 8
|
||
|
|
Net 411 "/fpga2/M0_A11" "M0_A11"
|
||
|
|
RP18 7
|
||
|
|
U2 41
|
||
|
|
Net 412 "/fpga2/M0_A10" "M0_A10"
|
||
|
|
RP15 5
|
||
|
|
U2 28
|
||
|
|
Net 413 "/fpga2/M0_A9" "M0_A9"
|
||
|
|
RP18 6
|
||
|
|
U2 40
|
||
|
|
Net 414 "/fpga2/M0_A8" "M0_A8"
|
||
|
|
U2 39
|
||
|
|
RP18 5
|
||
|
|
Net 415 "/fpga2/M0_A7" "M0_A7"
|
||
|
|
RP17 8
|
||
|
|
U2 38
|
||
|
|
Net 416 "/fpga2/M0_A6" "M0_A6"
|
||
|
|
RP17 7
|
||
|
|
U2 37
|
||
|
|
Net 417 "/fpga2/M0_A5" "M0_A5"
|
||
|
|
U2 36
|
||
|
|
RP17 6
|
||
|
|
Net 418 "/sdram/M0_A4" "M0_A4"
|
||
|
|
U2 35
|
||
|
|
RP17 5
|
||
|
|
Net 419 "/fpga2/M0_A3" "M0_A3"
|
||
|
|
RP14 5
|
||
|
|
U2 32
|
||
|
|
Net 420 "/fpga2/M0_A2" "M0_A2"
|
||
|
|
U2 31
|
||
|
|
RP14 6
|
||
|
|
Net 421 "/fpga2/M0_A1" "M0_A1"
|
||
|
|
U2 30
|
||
|
|
RP14 7
|
||
|
|
Net 422 "/sdram/M0_A0" "M0_A0"
|
||
|
|
U2 29
|
||
|
|
RP14 8
|
||
|
|
Net 423 "/sdram/M0_DQ15" "M0_DQ15"
|
||
|
|
RP10 5
|
||
|
|
U2 65
|
||
|
|
Net 424 "/fpga2/M0_DQ0" "M0_DQ0"
|
||
|
|
RP13 8
|
||
|
|
U2 2
|
||
|
|
Net 425 "/sdram/M0_DQ1" "M0_DQ1"
|
||
|
|
U2 4
|
||
|
|
RP13 7
|
||
|
|
Net 426 "/fpga2/M0_DQ2" "M0_DQ2"
|
||
|
|
RP13 6
|
||
|
|
U2 5
|
||
|
|
Net 427 "/fpga2/M0_DQ3" "M0_DQ3"
|
||
|
|
U2 7
|
||
|
|
RP13 5
|
||
|
|
Net 428 "/sdram/M0_DQ4" "M0_DQ4"
|
||
|
|
U2 8
|
||
|
|
RP12 8
|
||
|
|
Net 429 "/sdram/M0_DQ5" "M0_DQ5"
|
||
|
|
U2 10
|
||
|
|
RP12 7
|
||
|
|
Net 430 "/sdram/M0_DQ6" "M0_DQ6"
|
||
|
|
U2 11
|
||
|
|
RP12 6
|
||
|
|
Net 431 "/sdram/M0_DQ7" "M0_DQ7"
|
||
|
|
U2 13
|
||
|
|
RP12 5
|
||
|
|
Net 432 "/sdram/M0_DQ8" "M0_DQ8"
|
||
|
|
U2 54
|
||
|
|
RP11 8
|
||
|
|
Net 433 "/fpga2/M0_DQ9" "M0_DQ9"
|
||
|
|
U2 56
|
||
|
|
RP11 7
|
||
|
|
Net 434 "/fpga2/M0_DQ10" "M0_DQ10"
|
||
|
|
RP11 6
|
||
|
|
U2 57
|
||
|
|
Net 435 "/fpga2/M0_DQ11" "M0_DQ11"
|
||
|
|
U2 59
|
||
|
|
RP11 5
|
||
|
|
Net 436 "/fpga2/M0_DQ12" "M0_DQ12"
|
||
|
|
U2 60
|
||
|
|
RP10 8
|
||
|
|
Net 437 "/sdram/M0_DQ13" "M0_DQ13"
|
||
|
|
U2 62
|
||
|
|
RP10 7
|
||
|
|
Net 438 "/fpga2/M0_DQ14" "M0_DQ14"
|
||
|
|
RP10 6
|
||
|
|
U2 63
|
||
|
|
Net 439 "/fpga2/M1_DQ6" "M1_DQ6"
|
||
|
|
U3 11
|
||
|
|
RP4 6
|
||
|
|
Net 440 "/fpga2/M1_DQ7" "M1_DQ7"
|
||
|
|
RP4 5
|
||
|
|
U3 13
|
||
|
|
Net 441 "/fpga2/M1_DQ8" "M1_DQ8"
|
||
|
|
RP9 4
|
||
|
|
U3 54
|
||
|
|
Net 442 "/sdram/M1_DQ9" "M1_DQ9"
|
||
|
|
RP9 3
|
||
|
|
U3 56
|
||
|
|
Net 443 "/fpga2/M1_DQ10" "M1_DQ10"
|
||
|
|
U3 57
|
||
|
|
RP9 2
|
||
|
|
Net 444 "/sdram/M1_DQ11" "M1_DQ11"
|
||
|
|
U3 59
|
||
|
|
RP9 1
|
||
|
|
Net 445 "/fpga2/M1_DQ12" "M1_DQ12"
|
||
|
|
U3 60
|
||
|
|
RP8 4
|
||
|
|
Net 446 "/fpga2/M1_DQ13" "M1_DQ13"
|
||
|
|
U3 62
|
||
|
|
RP8 3
|
||
|
|
Net 447 "/sdram/M1_DQ14" "M1_DQ14"
|
||
|
|
RP8 2
|
||
|
|
U3 63
|
||
|
|
Net 448 "/sdram/M1_DQ15" "M1_DQ15"
|
||
|
|
RP8 1
|
||
|
|
U3 65
|
||
|
|
Net 449 "/flash/NF_D2" "NF_D2"
|
||
|
|
U1 A13
|
||
|
|
U5 31
|
||
|
|
Net 450 "/fpga1/NF_D1" "NF_D1"
|
||
|
|
U1 D14
|
||
|
|
U5 30
|
||
|
|
Net 451 "/fpga1/NF_D0" "NF_D0"
|
||
|
|
U1 C12
|
||
|
|
U5 29
|
||
|
|
Net 452 "/flash/SD_DAT3" "SD_DAT3"
|
||
|
|
J1 2
|
||
|
|
U1 B16
|
||
|
|
Net 453 "/flash/SD_DAT2" "SD_DAT2"
|
||
|
|
U1 A16
|
||
|
|
J1 1
|
||
|
|
Net 454 "/flash/SD_DAT1" "SD_DAT1"
|
||
|
|
J1 8
|
||
|
|
U1 B18
|
||
|
|
Net 455 "/fpga1/SD_DAT0" "SD_DAT0"
|
||
|
|
U1 A18
|
||
|
|
J1 7
|
||
|
|
Net 456 "/sdram/M1_A12" "M1_A12"
|
||
|
|
RP7 1
|
||
|
|
U3 42
|
||
|
|
Net 457 "/sdram/M1_A11" "M1_A11"
|
||
|
|
RP7 2
|
||
|
|
U3 41
|
||
|
|
Net 458 "/sdram/M1_A10" "M1_A10"
|
||
|
|
U3 28
|
||
|
|
RP2 5
|
||
|
|
Net 459 "/fpga2/M1_A0" "M1_A0"
|
||
|
|
U3 29
|
||
|
|
RP1 8
|
||
|
|
Net 460 "/fpga2/M1_A1" "M1_A1"
|
||
|
|
RP1 7
|
||
|
|
U3 30
|
||
|
|
Net 461 "/fpga2/M1_A2" "M1_A2"
|
||
|
|
U3 31
|
||
|
|
RP1 6
|
||
|
|
Net 462 "/fpga2/M1_A3" "M1_A3"
|
||
|
|
RP1 5
|
||
|
|
U3 32
|
||
|
|
Net 463 "/fpga2/M1_A4" "M1_A4"
|
||
|
|
U3 35
|
||
|
|
RP6 4
|
||
|
|
Net 464 "/fpga2/M1_A5" "M1_A5"
|
||
|
|
RP6 3
|
||
|
|
U3 36
|
||
|
|
Net 465 "/sdram/M1_A6" "M1_A6"
|
||
|
|
U3 37
|
||
|
|
RP6 2
|
||
|
|
Net 466 "/sdram/M1_A7" "M1_A7"
|
||
|
|
RP6 1
|
||
|
|
U3 38
|
||
|
|
Net 467 "/sdram/M1_A8" "M1_A8"
|
||
|
|
RP7 4
|
||
|
|
U3 39
|
||
|
|
Net 468 "/sdram/M1_A9" "M1_A9"
|
||
|
|
RP7 3
|
||
|
|
U3 40
|
||
|
|
Net 470 "/expansion/FPGA_BANK0_IO_30" "FPGA_BANK0_IO_30"
|
||
|
|
U1 W14
|
||
|
|
P1 20
|
||
|
|
Net 471 "/expansion/FPGA_BANK0_IO_29" "FPGA_BANK0_IO_29"
|
||
|
|
U1 AB16
|
||
|
|
P1 18
|
||
|
|
Net 472 "/fpga1/FPGA_BANK0_IO_28" "FPGA_BANK0_IO_28"
|
||
|
|
P1 17
|
||
|
|
U1 AA16
|
||
|
|
Net 473 "/expansion/FPGA_BANK0_IO_27" "FPGA_BANK0_IO_27"
|
||
|
|
U1 W13
|
||
|
|
P1 21
|
||
|
|
Net 475 "/fpga1/FPGA_BANK0_IO_25" "FPGA_BANK0_IO_25"
|
||
|
|
P1 22
|
||
|
|
U1 W15
|
||
|
|
Net 476 "/expansion/FPGA_BANK0_IO_24" "FPGA_BANK0_IO_24"
|
||
|
|
P1 16
|
||
|
|
U1 Y16
|
||
|
|
Net 478 "/fpga1/FPGA_BANK0_IO_22" "FPGA_BANK0_IO_22"
|
||
|
|
P1 19
|
||
|
|
U1 AA14
|
||
|
|
Net 479 "/expansion/FPGA_BANK0_IO_21" "FPGA_BANK0_IO_21"
|
||
|
|
U1 AB17
|
||
|
|
P1 14
|
||
|
|
Net 480 "/fpga1/FPGA_BANK0_IO_20" "FPGA_BANK0_IO_20"
|
||
|
|
P1 15
|
||
|
|
U1 Y17
|
||
|
|
Net 482 "/fpga1/FPGA_BANK0_IO_18" "FPGA_BANK0_IO_18"
|
||
|
|
U1 AA18
|
||
|
|
P1 12
|
||
|
|
Net 483 "/expansion/FPGA_BANK0_IO_17" "FPGA_BANK0_IO_17"
|
||
|
|
P1 13
|
||
|
|
U1 V15
|
||
|
|
Net 484 "GND" "GND"
|
||
|
|
U2 6
|
||
|
|
U4 8
|
||
|
|
C20 2
|
||
|
|
U2 64
|
||
|
|
C18 2
|
||
|
|
R12 2
|
||
|
|
R14 2
|
||
|
|
C22 2
|
||
|
|
U1 K14
|
||
|
|
U1 M14
|
||
|
|
U1 P14
|
||
|
|
U1 V14
|
||
|
|
U1 E15
|
||
|
|
U1 J15
|
||
|
|
R9 2
|
||
|
|
U1 N15
|
||
|
|
U1 AA5
|
||
|
|
U1 W16
|
||
|
|
U1 B17
|
||
|
|
U1 K12
|
||
|
|
U1 M12
|
||
|
|
U1 P12
|
||
|
|
U1 A22
|
||
|
|
U1 B13
|
||
|
|
U1 J13
|
||
|
|
U1 L13
|
||
|
|
U1 N13
|
||
|
|
C12 2
|
||
|
|
C10 2
|
||
|
|
C11 2
|
||
|
|
R2 2
|
||
|
|
U4 35
|
||
|
|
U1 E11
|
||
|
|
U4 44
|
||
|
|
U4 23
|
||
|
|
U4 12
|
||
|
|
U1 J11
|
||
|
|
C1 2
|
||
|
|
U1 L11
|
||
|
|
C3 2
|
||
|
|
U1 N11
|
||
|
|
U1 E21
|
||
|
|
U1 J21
|
||
|
|
U1 N21
|
||
|
|
U1 U21
|
||
|
|
C5 2
|
||
|
|
U1 AB1
|
||
|
|
C90 2
|
||
|
|
U1 B9
|
||
|
|
U1 J9
|
||
|
|
C7 2
|
||
|
|
U1 L9
|
||
|
|
U1 N9
|
||
|
|
C8 2
|
||
|
|
U1 K10
|
||
|
|
U1 M10
|
||
|
|
U1 P10
|
||
|
|
U1 V10
|
||
|
|
C2 2
|
||
|
|
C4 2
|
||
|
|
U2 52
|
||
|
|
C6 2
|
||
|
|
U2 12
|
||
|
|
C9 2
|
||
|
|
U2 66
|
||
|
|
U3 58
|
||
|
|
C34 2
|
||
|
|
C71 2
|
||
|
|
C70 2
|
||
|
|
U2 34
|
||
|
|
U2 24
|
||
|
|
V1 2
|
||
|
|
V4 2
|
||
|
|
C37 2
|
||
|
|
C36 2
|
||
|
|
C35 2
|
||
|
|
C76 2
|
||
|
|
C77 2
|
||
|
|
L7 2
|
||
|
|
C69 2
|
||
|
|
C67 2
|
||
|
|
C64 2
|
||
|
|
C61 2
|
||
|
|
C16 2
|
||
|
|
R10 2
|
||
|
|
L5 2
|
||
|
|
C13 2
|
||
|
|
C14 2
|
||
|
|
C15 2
|
||
|
|
V2 2
|
||
|
|
R47 1
|
||
|
|
C52 2
|
||
|
|
C43 2
|
||
|
|
P1 3
|
||
|
|
C40 2
|
||
|
|
C48 2
|
||
|
|
C45 2
|
||
|
|
C42 2
|
||
|
|
C39 2
|
||
|
|
C59 2
|
||
|
|
C56 2
|
||
|
|
C50 2
|
||
|
|
C47 2
|
||
|
|
C44 2
|
||
|
|
C41 2
|
||
|
|
C53 2
|
||
|
|
C51 2
|
||
|
|
C49 2
|
||
|
|
C58 2
|
||
|
|
C55 2
|
||
|
|
C68 2
|
||
|
|
C65 2
|
||
|
|
C62 2
|
||
|
|
R15 2
|
||
|
|
C38 2
|
||
|
|
V3 2
|
||
|
|
U7 7
|
||
|
|
U7 6
|
||
|
|
U6 6
|
||
|
|
U6 7
|
||
|
|
C66 2
|
||
|
|
C63 2
|
||
|
|
C60 2
|
||
|
|
C57 2
|
||
|
|
R46 1
|
||
|
|
C54 2
|
||
|
|
C46 2
|
||
|
|
U1 E7
|
||
|
|
U1 H7
|
||
|
|
U1 U7
|
||
|
|
U1 W7
|
||
|
|
U4 39
|
||
|
|
U1 A3
|
||
|
|
U4 36
|
||
|
|
J4 4
|
||
|
|
C91 2
|
||
|
|
U1 A1
|
||
|
|
U1 E2
|
||
|
|
U1 J2
|
||
|
|
U1 N2
|
||
|
|
U1 U2
|
||
|
|
U1 D4
|
||
|
|
U1 V4
|
||
|
|
U1 B5
|
||
|
|
U1 G5
|
||
|
|
U1 L5
|
||
|
|
U1 R5
|
||
|
|
U1 D18
|
||
|
|
U1 G18
|
||
|
|
U1 L18
|
||
|
|
U1 R18
|
||
|
|
U1 W19
|
||
|
|
U1 AA9
|
||
|
|
U1 AB22
|
||
|
|
U1 AA13
|
||
|
|
U1 AA17
|
||
|
|
U1 U15
|
||
|
|
C92 2
|
||
|
|
C94 2
|
||
|
|
C93 2
|
||
|
|
R53 1
|
||
|
|
R54 1
|
||
|
|
U1 N17
|
||
|
|
J1 CASE
|
||
|
|
J1 CASE
|
||
|
|
J1 CASE
|
||
|
|
J1 COM
|
||
|
|
U3 6
|
||
|
|
U3 64
|
||
|
|
U2 48
|
||
|
|
X2 2
|
||
|
|
U3 34
|
||
|
|
J1 6
|
||
|
|
U5 13
|
||
|
|
U5 36
|
||
|
|
U2 58
|
||
|
|
C75 1
|
||
|
|
C27 2
|
||
|
|
C32 2
|
||
|
|
C30 2
|
||
|
|
C31 2
|
||
|
|
C29 2
|
||
|
|
C74 2
|
||
|
|
C21 2
|
||
|
|
J4 5
|
||
|
|
C28 2
|
||
|
|
C33 2
|
||
|
|
C23 2
|
||
|
|
C25 2
|
||
|
|
C24 2
|
||
|
|
C26 2
|
||
|
|
U8 4
|
||
|
|
U3 66
|
||
|
|
C72 2
|
||
|
|
C73 2
|
||
|
|
C156 1
|
||
|
|
U3 52
|
||
|
|
U3 12
|
||
|
|
U3 48
|
||
|
|
Net 485 "VCCO2" "VCCO2"
|
||
|
|
U1 AA11
|
||
|
|
C156 2
|
||
|
|
U1 AA15
|
||
|
|
X2 4
|
||
|
|
U1 V16
|
||
|
|
U1 AA19
|
||
|
|
U1 AA22
|
||
|
|
U1 V12
|
||
|
|
U1 W5
|
||
|
|
U1 T9
|
||
|
|
U1 V8
|
||
|
|
U1 AA3
|
||
|
|
U1 T13
|
||
|
|
U1 AA7
|
||
|
|
U8 8
|
||
|
|
P1 5
|
||
|
|
C55 1
|
||
|
|
C58 1
|
||
|
|
C61 1
|
||
|
|
C64 1
|
||
|
|
C67 1
|
||
|
|
C69 1
|
||
|
|
Net 486 "/expansion/FPGA_BANK0_IO_1" "FPGA_BANK0_IO_1"
|
||
|
|
U1 T18
|
||
|
|
P1 2
|
||
|
|
Net 487 "/fpga1/FPGA_BANK0_IO_2" "FPGA_BANK0_IO_2"
|
||
|
|
P1 25
|
||
|
|
U1 T17
|
||
|
|
Net 488 "/expansion/FPGA_BANK0_IO_3" "FPGA_BANK0_IO_3"
|
||
|
|
P1 10
|
||
|
|
U1 Y19
|
||
|
|
Net 490 "/expansion/FPGA_BANK0_IO_5" "FPGA_BANK0_IO_5"
|
||
|
|
U1 Y18
|
||
|
|
P1 11
|
||
|
|
Net 491 "/fpga1/FPGA_BANK0_IO_6" "FPGA_BANK0_IO_6"
|
||
|
|
U1 T16
|
||
|
|
P1 28
|
||
|
|
Net 492 "/fpga1/FPGA_BANK0_IO_7" "FPGA_BANK0_IO_7"
|
||
|
|
P1 27
|
||
|
|
U1 T15
|
||
|
|
Net 493 "/expansion/FPGA_BANK0_IO_8" "FPGA_BANK0_IO_8"
|
||
|
|
U1 U17
|
||
|
|
P1 1
|
||
|
|
Net 494 "/expansion/FPGA_BANK0_IO_9" "FPGA_BANK0_IO_9"
|
||
|
|
U1 U16
|
||
|
|
P1 4
|
||
|
|
Net 495 "/expansion/FPGA_BANK0_IO_10" "FPGA_BANK0_IO_10"
|
||
|
|
U1 V19
|
||
|
|
P1 7
|
||
|
|
Net 496 "/fpga1/FPGA_BANK0_IO_11" "FPGA_BANK0_IO_11"
|
||
|
|
U1 V18
|
||
|
|
P1 9
|
||
|
|
Net 497 "/expansion/FPGA_BANK0_IO_12" "FPGA_BANK0_IO_12"
|
||
|
|
P1 29
|
||
|
|
U1 R16
|
||
|
|
Net 499 "/expansion/FPGA_BANK0_IO_14" "FPGA_BANK0_IO_14"
|
||
|
|
U1 V17
|
||
|
|
P1 6
|
||
|
|
Net 500 "/expansion/FPGA_BANK0_IO_15" "FPGA_BANK0_IO_15"
|
||
|
|
P1 8
|
||
|
|
U1 W17
|
||
|
|
Net 502 "/expansion/FPGA_BANK0_IO_63" "FPGA_BANK0_IO_63"
|
||
|
|
U1 V5
|
||
|
|
P1 45
|
||
|
|
Net 503 "/fpga1/FPGA_BANK0_IO_62" "FPGA_BANK0_IO_62"
|
||
|
|
P1 46
|
||
|
|
U1 U6
|
||
|
|
Net 505 "/expansion/FPGA_BANK0_IO_60" "FPGA_BANK0_IO_60"
|
||
|
|
U1 T7
|
||
|
|
P1 50
|
||
|
|
Net 507 "/fpga1/FPGA_BANK0_IO_58" "FPGA_BANK0_IO_58"
|
||
|
|
U1 R9
|
||
|
|
P1 49
|
||
|
|
Net 508 "/expansion/FPGA_BANK0_IO_57" "FPGA_BANK0_IO_57"
|
||
|
|
U1 W6
|
||
|
|
P1 48
|
||
|
|
Net 509 "/fpga1/FPGA_BANK0_IO_56" "FPGA_BANK0_IO_56"
|
||
|
|
U1 U10
|
||
|
|
P1 39
|
||
|
|
Net 511 "/expansion/FPGA_BANK0_IO_54" "FPGA_BANK0_IO_54"
|
||
|
|
P1 43
|
||
|
|
U1 U8
|
||
|
|
Net 512 "/expansion/FPGA_BANK0_IO_53" "FPGA_BANK0_IO_53"
|
||
|
|
U1 T8
|
||
|
|
P1 47
|
||
|
|
Net 513 "/fpga1/FPGA_BANK0_IO_52" "FPGA_BANK0_IO_52"
|
||
|
|
U1 V9
|
||
|
|
P1 37
|
||
|
|
Net 514 "/fpga1/FPGA_BANK0_IO_51" "FPGA_BANK0_IO_51"
|
||
|
|
U1 U9
|
||
|
|
P1 41
|
||
|
|
Net 515 "/fpga1/FPGA_BANK0_IO_50" "FPGA_BANK0_IO_50"
|
||
|
|
U1 W9
|
||
|
|
P1 38
|
||
|
|
Net 516 "/expansion/FPGA_BANK0_IO_49" "FPGA_BANK0_IO_49"
|
||
|
|
U1 V7
|
||
|
|
P1 44
|
||
|
|
Net 517 "/expansion/FPGA_BANK0_IO_32" "FPGA_BANK0_IO_32"
|
||
|
|
U1 Y15
|
||
|
|
P1 26
|
||
|
|
Net 518 "/fpga1/FPGA_BANK0_IO_33" "FPGA_BANK0_IO_33"
|
||
|
|
U1 AB15
|
||
|
|
P1 24
|
||
|
|
Net 519 "/expansion/FPGA_BANK0_IO_34" "FPGA_BANK0_IO_34"
|
||
|
|
U1 T12
|
||
|
|
P1 42
|
||
|
|
Net 521 "/expansion/FPGA_BANK0_IO_36" "FPGA_BANK0_IO_36"
|
||
|
|
U1 T14
|
||
|
|
P1 30
|
||
|
|
Net 523 "/expansion/FPGA_BANK0_IO_38" "FPGA_BANK0_IO_38"
|
||
|
|
X2 3
|
||
|
|
U1 Y13
|
||
|
|
Net 524 "/expansion/FPGA_BANK0_IO_39" "FPGA_BANK0_IO_39"
|
||
|
|
U1 AB13
|
||
|
|
P1 23
|
||
|
|
Net 525 "/fpga1/FPGA_BANK0_IO_40" "FPGA_BANK0_IO_40"
|
||
|
|
P1 32
|
||
|
|
U1 Y11
|
||
|
|
Net 528 "/expansion/FPGA_BANK0_IO_43" "FPGA_BANK0_IO_43"
|
||
|
|
U1 V11
|
||
|
|
P1 34
|
||
|
|
Net 529 "/fpga1/FPGA_BANK0_IO_44" "FPGA_BANK0_IO_44"
|
||
|
|
P1 31
|
||
|
|
U1 W11
|
||
|
|
Net 530 "/expansion/FPGA_BANK0_IO_45" "FPGA_BANK0_IO_45"
|
||
|
|
P1 35
|
||
|
|
U1 Y9
|
||
|
|
Net 531 "/expansion/FPGA_BANK0_IO_46" "FPGA_BANK0_IO_46"
|
||
|
|
P1 36
|
||
|
|
U1 W10
|
||
|
|
Net 532 "/expansion/FPGA_BANK0_IO_47" "FPGA_BANK0_IO_47"
|
||
|
|
U1 Y10
|
||
|
|
P1 33
|
||
|
|
Net 533 "/fpga1/FPGA_BANK0_IO_48" "FPGA_BANK0_IO_48"
|
||
|
|
P1 40
|
||
|
|
U1 W8
|
||
|
|
Net 534 "/fpga2/M1_DQ5" "M1_DQ5"
|
||
|
|
RP4 7
|
||
|
|
U3 10
|
||
|
|
Net 535 "/fpga2/M1_DQ4" "M1_DQ4"
|
||
|
|
U3 8
|
||
|
|
RP4 8
|
||
|
|
Net 536 "/fpga2/M1_DQ3" "M1_DQ3"
|
||
|
|
U3 7
|
||
|
|
RP5 5
|
||
|
|
Net 537 "/sdram/M1_DQ2" "M1_DQ2"
|
||
|
|
U3 5
|
||
|
|
RP5 6
|
||
|
|
Net 538 "/sdram/M1_DQ1" "M1_DQ1"
|
||
|
|
U3 4
|
||
|
|
RP5 7
|
||
|
|
Net 539 "/sdram/M1_DQ0" "M1_DQ0"
|
||
|
|
RP5 8
|
||
|
|
U3 2
|
||
|
|
Net 540 "/fpga1/ETH_TXD3" "ETH_TXD3"
|
||
|
|
U1 A8
|
||
|
|
U4 20
|
||
|
|
Net 541 "/fpga1/ETH_TXD2" "ETH_TXD2"
|
||
|
|
U1 C10
|
||
|
|
U4 19
|
||
|
|
Net 542 "/fpga1/ETH_TXD1" "ETH_TXD1"
|
||
|
|
U1 C9
|
||
|
|
U4 18
|
||
|
|
Net 543 "/ether/ETH_RXD0" "ETH_RXD0"
|
||
|
|
U4 6
|
||
|
|
U1 B6
|
||
|
|
Net 544 "/fpga1/ETH_RXD1" "ETH_RXD1"
|
||
|
|
U1 A5
|
||
|
|
U4 5
|
||
|
|
Net 545 "/fpga1/ETH_RXD2" "ETH_RXD2"
|
||
|
|
U4 4
|
||
|
|
U1 C6
|
||
|
|
Net 546 "/fpga1/ETH_RXD3" "ETH_RXD3"
|
||
|
|
U4 3
|
||
|
|
U1 C5
|
||
|
|
Net 547 "/fpga1/ETH_TXD0" "ETH_TXD0"
|
||
|
|
U4 17
|
||
|
|
U1 D10
|
||
|
|
}
|
||
|
|
#End
|