xue/kicad/xue-rnc/xue-rnc.net

# EESchema Netlist Version 1.1 created  Mon 09 Aug 2010 10:11:11 PM COT
(
 ( /4C431A63/4C431E53 $noname  U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
  (   P7 ? )
  (   N7 ? )
  (   M7 ? )
  (   L7 N-000153 )
  (   K7 ? )
  (   J7 ? )
  (   G7 ? )
  (   F7 ? )
  (   P6 ? )
  (   N6 ? )
  (   M6 ? )
  (   L6 ? )
  (   K6 /FPGA_Spartan6/M0_A3 )
  (   J6 ? )
  (   H6 /DDR_Banks/M0_A7 )
  (   G6 ? )
  (   F6 N-000153 )
  (   E6 ? )
  (   U5 N-000153 )
  (   P5 ? )
  (   N5 N-000153 )
  (   M5 ? )
  (   K5 /DDR_Banks/M0_RAS# )
  (   J5 N-000153 )
  (   H5 /FPGA_Spartan6/M0_A2 )
  (   F5 ? )
  (   E5 ? )
  (   D5 ? )
  (   U4 ? )
  (  H21 /FPGA_Spartan6/M1_RAS# )
  (  G21 N-000155 )
  (  F21 /FPGA_Spartan6/M1_A0 )
  (  D21 /FPGA_Spartan6/M1_CKE )
  (  C21 N-000155 )
  (  B21 ? )
  (  A21 ? )
  (  W20 ? )
  (  V20 ? )
  (  U20 /FPGA_Spartan6/M1_DQ12 )
  (  T20 ? )
  (  R20 /DDR_Banks/M1_DQ10 )
  (  P20 ? )
  (  N20 /FPGA_Spartan6/M1_DQ0 )
  (  M20 /DDR_Banks/M1_UDM )
  (  L20 /DDR_Banks/M1_LDQS )
  (  K20 /DDR_Banks/M1_A5 )
  (  J20 ? )
  (  H20 /FPGA_Spartan6/M1_CLK )
  (  G20 /DDR_Banks/M1_A3 )
  (  F20 /FPGA_Spartan6/M1_A4 )
  (  E20 /DDR_Banks/M1_A7 )
  (  D20 ? )
  (  C20 /FPGA_Spartan6/M1_A8 )
  (  B20 ? )
  (  A20 ? )
  (   P8 ? )
  (   M8 ? )
  (   K8 ? )
  (   H8 ? )
  (   B3 ? )
  (   W2 N-000153 )
  (   V2 /FPGA_Spartan6/M0_DQ14 )
  (   T2 /DDR_Banks/M0_UDQS )
  (   R2 N-000153 )
  (   P2 /DDR_Banks/M0_DQ8 )
  (   M2 /FPGA_Spartan6/M0_DQ2 )
  (   L2 N-000153 )
  (   K2 /FPGA_Spartan6/M0_DQ6 )
  (   H2 /FPGA_Spartan6/M0_A0 )
  (   G2 N-000153 )
  (   F2 /FPGA_Spartan6/M0_WE# )
  (   D2 /FPGA_Spartan6/M0_CKE )
  (   C2 N-000153 )
  (   B2 ? )
  (   A2 ? )
  (   Y1 ? )
  (   W1 ? )
  (   V1 /FPGA_Spartan6/M0_DQ15 )
  (   U1 /FPGA_Spartan6/M0_DQ13 )
  (   T1 ? )
  (   R1 /FPGA_Spartan6/M0_DQ11 )
  (   P1 /FPGA_Spartan6/M0_DQ9 )
  (   N1 /FPGA_Spartan6/M0_DQ1 )
  (   M1 /DDR_Banks/M0_DQ3 )
  (   L1 ? )
  (   K1 /FPGA_Spartan6/M0_DQ7 )
  (   J1 /FPGA_Spartan6/M0_DQ5 )
  (   H1 /DDR_Banks/M0_A1 )
  (   G1 ? )
  (   T4 ? )
  (   R4 ? )
  (   P4 ? )
  (   N4 ? )
  (   M4 ? )
  (   L4 /DDR_Banks/M0_LDM )
  (   K4 /DDR_Banks/M0_CAS# )
  (   J4 /DDR_Banks/M0_A6 )
  (   H4 /FPGA_Spartan6/M0_CLK )
  (   G4 /DDR_Banks/M0_A10 )
  (   F4 N-000153 )
  (   E4 ? )
  (   C4 ? )
  (   W3 ? )
  (   V3 ? )
  (   U3 /FPGA_Spartan6/M0_DQ12 )
  (   T3 ? )
  (   R3 /DDR_Banks/M0_DQ10 )
  (   P3 ? )
  (   N3 /FPGA_Spartan6/M0_DQ0 )
  (   M3 /FPGA_Spartan6/M0_UDM )
  (   L3 /DDR_Banks/M0_LDQS )
  (   K3 /FPGA_Spartan6/M0_A5 )
  (   J3 /FPGA_Spartan6/M0_DQ4 )
  (   H3 /DDR_Banks/M0_CLK# )
  (   G3 ? )
  (   F3 /FPGA_Spartan6/M0_A4 )
  (   E3 /FPGA_Spartan6/M0_A8 )
  (   D3 ? )
  (   C3 ? )
  (  G10 N-000137 )
  (  D10 ? )
  (  C10 ? )
  (  B10 ? )
  (  A10 ? )
  (   E9 N-000137 )
  (   D9 ? )
  (   C9 ? )
  (   A9 ? )
  (   D8 ? )
  (   C8 ? )
  (   B8 ? )
  (   A8 ? )
  (   D7 ? )
  (   C7 ? )
  (   B7 N-000137 )
  (   A7 ? )
  (   D6 ? )
  (   C6 ? )
  (   B6 ? )
  (   A6 ? )
  (   C5 ? )
  (   A5 /Ethernet_Phy/ETH_INT )
  (   B4 N-000137 )
  (   A4 ? )
  (  U19 ? )
  (  T19 ? )
  (  R19 ? )
  (  P19 ? )
  (  N19 ? )
  (  B19 N-000137 )
  (  B18 ? )
  (  A18 ? )
  (  E17 N-000137 )
  (  D17 ? )
  (  C17 ? )
  (  A17 ? )
  (  E16 ? )
  (  C16 ? )
  (  B16 ? )
  (  A16 ? )
  (  D15 ? )
  (  C15 ? )
  (  B15 N-000137 )
  (  A15 ? )
  (  G14 N-000137 )
  (  D14 ? )
  (  C14 ? )
  (  B14 ? )
  (  A14 ? )
  (  E13 N-000137 )
  (  C13 ? )
  (  A13 ? )
  (  C12 ? )
  (  B12 ? )
  (  A12 ? )
  (  D11 ? )
  (  C11 ? )
  (  B11 N-000137 )
  (  A11 ? )
  (  H16 ? )
  (  G16 ? )
  (  F16 ? )
  (  L15 ? )
  (  W22 ? )
  (  V22 /DDR_Banks/M1_DQ15 )
  (  U22 /FPGA_Spartan6/M1_DQ13 )
  (  T22 ? )
  (  R22 /DDR_Banks/M1_DQ11 )
  (  P22 /FPGA_Spartan6/M1_DQ9 )
  (  N22 /FPGA_Spartan6/M1_DQ1 )
  (  M22 ? )
  (  L22 ? )
  (  K22 /FPGA_Spartan6/M1_DQ7 )
  (  J22 /DDR_Banks/M1_DQ5 )
  (  H22 /FPGA_Spartan6/M1_CAS# )
  (  G22 ? )
  (  F22 /FPGA_Spartan6/M1_A1 )
  (  E22 /FPGA_Spartan6/M1_A2 )
  (  D22 /DDR_Banks/M1_A12 )
  (  C22 /FPGA_Spartan6/M1_A9 )
  (  B22 ? )
  (  W21 N-000155 )
  (  V21 /DDR_Banks/M1_DQ14 )
  (  T21 /FPGA_Spartan6/M1_UDQS )
  (  R21 N-000155 )
  (  P21 /DDR_Banks/M1_DQ8 )
  (  M21 ? )
  (  L21 N-000155 )
  (  K21 /FPGA_Spartan6/M1_DQ6 )
  (  M19 ? )
  (  L19 /FPGA_Spartan6/M1_LDM )
  (  K19 /DDR_Banks/M1_A6 )
  (  J19 /FPGA_Spartan6/M1_CLK# )
  (  H19 /DDR_Banks/M1_WE# )
  (  G19 /FPGA_Spartan6/M1_A10 )
  (  F19 /FPGA_Spartan6/M1_A11 )
  (  E19 N-000155 )
  (  D19 ? )
  (  U18 N-000155 )
  (  P18 ? )
  (  N18 N-000155 )
  (  M18 ? )
  (  K18 ? )
  (  J18 N-000155 )
  (  H18 ? )
  (  F18 ? )
  (  P17 ? )
  (  M17 ? )
  (  L17 ? )
  (  K17 ? )
  (  J17 ? )
  (  H17 ? )
  (  G17 ? )
  (  F17 ? )
  (  N16 ? )
  (  M16 ? )
  (  L16 N-000155 )
  (  K16 ? )
  (  J16 ? )
  (  J14 N-000156 )
  (  H14 ? )
  (  F14 ? )
  (  E14 ? )
  (  P13 N-000156 )
  (  N13 GND )
  (  M13 N-000156 )
  (  L13 GND )
  (  K13 N-000156 )
  (  J13 GND )
  (  H13 ? )
  (  G13 ? )
  (  F13 ? )
  (  D13 ? )
  (  B13 GND )
  (  Y22 ? )
  (  A22 GND )
  (  R12 N-000157 )
  (  P12 GND )
  (  N12 N-000156 )
  (  M12 GND )
  (  L12 N-000156 )
  (  K12 ? )
  (  J12 N-000156 )
  (  H12 ? )
  (  G12 N-000157 )
  (  F12 ? )
  (  E12 ? )
  (  D12 ? )
  (  AB1 GND )
  (  A19 ? )
  (  R18 GND )
  (  L18 GND )
  (  G18 GND )
  (  E18 ? )
  (  D18 GND )
  (  C18 ? )
  (  R17 ? )
  (  N17 GND )
  (  B17 GND )
  (  W16 GND )
  (  P16 ? )
  (  D16 N-000157 )
  (  AA5 GND )
  (  P15 ? )
  (  N15 ? )
  (  M15 N-000157 )
  (  K15 N-000157 )
  (  J15 GND )
  (  H15 N-000157 )
  (  G15 ? )
  (  F15 ? )
  (  E15 GND )
  (  V14 GND )
  (  R14 N-000156 )
  (  P14 GND )
  (  N14 N-000156 )
  (  M14 GND )
  (  L14 N-000156 )
  (  K14 GND )
  (   L9 GND )
  (   K9 N-000156 )
  (   J9 GND )
  (   H9 N-000157 )
  (   G9 ? )
  (   F9 ? )
  (   B9 GND )
  (   N8 N-000157 )
  (   L8 N-000157 )
  (   J8 N-000156 )
  (   G8 ? )
  (   F8 ? )
  (   E8 ? )
  (   W7 GND )
  (   U7 GND )
  (   H7 GND )
  (   E7 GND )
  (   V6 N-000157 )
  (   R6 N-000157 )
  (   R5 GND )
  (   L5 GND )
  (   G5 GND )
  (   B5 GND )
  (   V4 GND )
  (   D4 GND )
  (   U2 GND )
  (   N2 GND )
  (   J2 GND )
  (   E2 GND )
  (   A1 GND )
  (  AA1 ? )
  (  U21 GND )
  (  N21 GND )
  (  J21 GND )
  (  E21 GND )
  (  U11 N-000157 )
  (  P11 N-000156 )
  (  N11 GND )
  (  M11 N-000156 )
  (  L11 GND )
  (  K11 N-000156 )
  (  J11 GND )
  (  H11 ? )
  (  G11 ? )
  (  F11 N-000157 )
  (  E11 ? )
  (  V10 GND )
  (  R10 N-000157 )
  (  P10 GND )
  (  N10 N-000156 )
  (  M10 GND )
  (  L10 N-000156 )
  (  K10 GND )
  (  J10 N-000156 )
  (  H10 ? )
  (  F10 ? )
  (  E10 ? )
  (   P9 N-000156 )
  (   N9 GND )
  (   M9 N-000156 )
  (  V19 ? )
  (  AB8 ? )
  (  AA8 ? )
  (  Y18 ? )
  (  W18 ? )
  (  V18 ? )
  (  T18 ? )
  (  AB7 ? )
  (  AA7 N-000154 )
  (  Y17 ? )
  (  W17 ? )
  (  V17 ? )
  (  U17 ? )
  (  T17 ? )
  (  AB6 ? )
  (  AA6 ? )
  (  Y16 ? )
  (  V16 N-000154 )
  (  U16 ? )
  (  T16 ? )
  (  R16 ? )
  (  AB5 ? )
  (  Y15 ? )
  (  W15 ? )
  (  V15 ? )
  (  U15 ? )
  (  T15 ? )
  (  R15 ? )
  (  AB4 ? )
  (  AA4 ? )
  (   F1 ? )
  (   E1 /FPGA_Spartan6/M0_A9 )
  (   D1 /DDR_Banks/M0_A12 )
  (   C1 /FPGA_Spartan6/M0_A11 )
  (   B1 ? )
  ( AB19 ? )
  ( AA19 N-000154 )
  ( AB18 ? )
  ( AA18 ? )
  ( AB17 ? )
  ( AB16 ? )
  ( AA16 ? )
  ( AB15 ? )
  ( AA15 N-000154 )
  ( AB14 ? )
  ( AA14 ? )
  ( AB13 ? )
  ( AA22 ? )
  ( AB12 ? )
  ( AA12 ? )
  ( AB21 ? )
  ( AA21 ? )
  ( AB11 ? )
  ( AA11 N-000154 )
  ( AB20 ? )
  ( AA20 ? )
  ( AB10 ? )
  ( AA10 ? )
  (  AB9 ? )
  (  Y19 ? )
  (   V9 ? )
  (   U9 ? )
  (   T9 N-000154 )
  (   R9 ? )
  (   Y8 ? )
  (   W8 ? )
  (   V8 N-000154 )
  (   U8 ? )
  (   T8 ? )
  (   R8 ? )
  (   Y7 ? )
  (   V7 ? )
  (   T7 ? )
  (   R7 ? )
  (   Y6 ? )
  (   W6 ? )
  (   U6 ? )
  (   T6 ? )
  (   Y5 ? )
  (   W5 N-000154 )
  (   V5 ? )
  (   T5 ? )
  (   Y4 ? )
  (   W4 ? )
  (   Y3 ? )
  ( AA17 GND )
  ( AA13 GND )
  ( AB22 GND )
  (  AA9 GND )
  (  W19 GND )
  (  Y14 ? )
  (  W14 ? )
  (  U14 ? )
  (  T14 ? )
  (  AB3 ? )
  (  AA3 N-000154 )
  (  Y13 ? )
  (  W13 ? )
  (  V13 ? )
  (  U13 ? )
  (  T13 N-000154 )
  (  R13 ? )
  (  AB2 ? )
  (  AA2 ? )
  (  Y12 ? )
  (  W12 ? )
  (  V12 N-000154 )
  (  U12 ? )
  (  T12 ? )
  (  Y11 ? )
  (  W11 ? )
  (  V11 ? )
  (  T11 ? )
  (  R11 ? )
  (  Y10 ? )
  (  W10 ? )
  (  U10 ? )
  (  T10 ? )
  (   Y9 ? )
  (   W9 ? )
 )
 ( /4C5F1EDC/4C5F2D27 $noname  R10 1M {Lib=R}
  (    1 N-000426 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2D1E $noname  C16 4.7nF {Lib=C}
  (    1 N-000426 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2CA7 $noname  V1 V0402MHS03 {Lib=V0402MHS03}
  (    1 N-000420 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2CA3 $noname  V2 V0402MHS03 {Lib=V0402MHS03}
  (    1 N-000419 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2B55 $noname  F1 MICROSMD075F {Lib=MICROSMD075F}
  (    1 N-000425 )
  (    2 ? )
 )
 ( /4C5F1EDC/4C5F23DD $noname  J5 USB-48204-0001 {Lib=USB-48204-0001}
  (   S1 N-000426 )
  (   S2 N-000426 )
  (   S3 N-000426 )
  (   S4 N-000426 )
  (    1 N-000425 )
  (    2 N-000419 )
  (    3 N-000420 )
  (    4 GND )
 )
 ( /4C5F1EDC/4C5F2039 $noname  C15 470nF {Lib=C}
  (    1 3.3V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2037 $noname  C14 1uF {Lib=C}
  (    1 3.3V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2033 $noname  C13 1uF {Lib=C}
  (    1 3.3V )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2025 $noname  U6 MIC2550AYTS {Lib=MIC2550AYTS}
  (    1 3.3V )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    7 GND )
  (    8 GND )
  (    9 ? )
  (   10 N-000419 )
  (   11 N-000420 )
  (   12 3.3V )
  (   14 3.3V )
 )
 ( /4C4320F3/4C5D8114 $noname  C9 C {Lib=C}
  (    1 /Ethernet_Phy/ETH_PLL1.8V )
  (    2 N-000416 )
 )
 ( /4C4320F3/4C5D810A $noname  L3 INDUCTOR {Lib=INDUCTOR}
  (    1 /Ethernet_Phy/ETH_A1.8V )
  (    2 /Ethernet_Phy/ETH_PLL1.8V )
 )
 ( /4C4320F3/4C5D8104 $noname  C6 C {Lib=C}
  (    1 /Ethernet_Phy/ETH_A1.8V )
  (    2 N-000416 )
 )
 ( /4C4320F3/4C5D80F3 $noname  L1 INDUCTOR {Lib=INDUCTOR}
  (    1 N-000417 )
  (    2 /Ethernet_Phy/ETH_A1.8V )
 )
 ( /4C4320F3/4C5D80F0 $noname  C4 C {Lib=C}
  (    1 N-000417 )
  (    2 N-000416 )
 )
 ( /4C4320F3/4C5D80ED $noname  C2 C {Lib=C}
  (    1 /Ethernet_Phy/ETH_1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FB7 $noname  L2 FB {Lib=INDUCTOR}
  (    1 3.3V )
  (    2 /Ethernet_Phy/ETH_A3.3V )
 )
 ( /4C4320F3/4C5D7FA7 $noname  C8 100nF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA5 $noname  C7 1uF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA3 $noname  C5 100nF {Lib=C}
  (    1 3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA1 $noname  C3 100nF {Lib=C}
  (    1 3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7F9F $noname  C1 1uF {Lib=C}
  (    1 3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7F39 $noname  R1 4.7K {Lib=R}
  (    1 /ETH_MDIO )
  (    2 3.3V )
 )
 ( /4C4320F3/4C5D7ECF $noname  R2 6.65K {Lib=R}
  (    1 N-000406 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7E43 $noname  C11 100nF {Lib=C}
  (    1 3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7E41 $noname  C10 100nF {Lib=C}
  (    1 3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7DCB $noname  C12 47nF {Lib=C}
  (    1 N-000400 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7DC4 $noname  R9 1M {Lib=R}
  (    1 N-000400 )
  (    2 GND )
 )
 ( /4C4320F3/4C432132 $noname  U4 K8001 {Lib=K8001}
  (    1 /ETH_MDIO )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 ? )
  (    7 3.3V )
  (    8 GND )
  (    9 ? )
  (   10 ? )
  (   11 ? )
  (   12 GND )
  (   13 /Ethernet_Phy/ETH_1.8V )
  (   14 ? )
  (   15 ? )
  (   16 ? )
  (   17 ? )
  (   18 ? )
  (   19 ? )
  (   20 ? )
  (   21 ? )
  (   22 ? )
  (   23 GND )
  (   24 3.3V )
  (   25 /Ethernet_Phy/ETH_INT )
  (   26 /Ethernet_Phy/ETH_LED0 )
  (   27 /Ethernet_Phy/ETH_LED1 )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 /Ethernet_Phy/ETH_A1.8V )
  (   32 N-000407 )
  (   33 N-000399 )
  (   34 ? )
  (   35 GND )
  (   36 GND )
  (   37 N-000406 )
  (   38 /Ethernet_Phy/ETH_A3.3V )
  (   39 GND )
  (   40 N-000408 )
  (   41 N-000398 )
  (   42 ? )
  (   43 ? )
  (   44 GND )
  (   45 ? )
  (   46 ? )
  (   47 /Ethernet_Phy/ETH_PLL1.8V )
  (   48 ? )
 )
 ( /4C4320F3/4C5D7AFE $noname  R3 49.9 {Lib=R}
  (    1 3.3V )
  (    2 N-000398 )
 )
 ( /4C4320F3/4C5D7AFC $noname  R4 49.9 {Lib=R}
  (    1 3.3V )
  (    2 N-000408 )
 )
 ( /4C4320F3/4C5D7AF9 $noname  R6 49.9 {Lib=R}
  (    1 3.3V )
  (    2 N-000407 )
 )
 ( /4C4320F3/4C5D7AF7 $noname  R5 49.9 {Lib=R}
  (    1 3.3V )
  (    2 N-000399 )
 )
 ( /4C4320F3/4C5D71DB $noname  R8 220 {Lib=R}
  (    1 N-000405 )
  (    2 /Ethernet_Phy/ETH_LED1 )
 )
 ( /4C4320F3/4C5D719D $noname  R7 220 {Lib=R}
  (    1 N-000396 )
  (    2 /Ethernet_Phy/ETH_LED0 )
 )
 ( /4C4320F3/4C5D6F5A $noname  J4 RJ45-48025 {Lib=RJ45-48025}
  (    1 N-000398 )
  (    2 N-000408 )
  (    3 3.3V )
  (    4 GND )
  (    5 GND )
  (    6 3.3V )
  (    7 N-000399 )
  (    8 N-000407 )
  (    9 3.3V )
  (   10 N-000396 )
  (   11 3.3V )
  (   12 N-000405 )
  (   13 N-000400 )
  (   14 N-000400 )
 )
 ( /4C4227FE/4B76F5E2 $noname  J1 MICROSD {Lib=MICROSD}
  ( CASE GND )
  (  COM GND )
  (   CD ? )
  (    1 ? )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 ? )
  (    7 ? )
  (    8 ? )
 )
 ( /4C4227FE/4B76F108 $noname  U5 NAND {Lib=HY27UG088G5M}
  (    1 ? )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 /Non_volatile_memories/FRB_N )
  (    7 /Non_volatile_memories/FRB_N )
  (    8 ? )
  (    9 ? )
  (   10 ? )
  (   11 ? )
  (   12 3.3V )
  (   13 GND )
  (   14 ? )
  (   15 ? )
  (   16 ? )
  (   17 ? )
  (   18 ? )
  (   19 3.3V )
  (   20 ? )
  (   21 ? )
  (   22 ? )
  (   23 ? )
  (   24 ? )
  (   25 ? )
  (   26 ? )
  (   27 ? )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 ? )
  (   32 ? )
  (   33 ? )
  (   34 ? )
  (   35 ? )
  (   36 GND )
  (   37 3.3V )
  (   38 ? )
  (   39 ? )
  (   40 ? )
  (   41 ? )
  (   42 ? )
  (   43 ? )
  (   44 ? )
  (   45 ? )
  (   46 ? )
  (   47 ? )
  (   48 ? )
 )
 ( /4C421DD3/4C609C8E $noname  U3 MT46V32M16TG {Lib=MT46V32M16TG}
  (    1 N-000047 )
  (    2 /FPGA_Spartan6/M1_DQ0 )
  (    3 N-000047 )
  (    4 /FPGA_Spartan6/M1_DQ1 )
  (    5 ? )
  (    6 GND )
  (    7 ? )
  (    8 ? )
  (    9 N-000047 )
  (   10 /DDR_Banks/M1_DQ5 )
  (   11 /FPGA_Spartan6/M1_DQ6 )
  (   12 GND )
  (   13 /FPGA_Spartan6/M1_DQ7 )
  (   14 ? )
  (   15 N-000047 )
  (   16 /DDR_Banks/M1_LDQS )
  (   17 ? )
  (   18 N-000047 )
  (   19 ? )
  (   20 /FPGA_Spartan6/M1_LDM )
  (   21 /DDR_Banks/M1_WE# )
  (   22 /FPGA_Spartan6/M1_CAS# )
  (   23 /FPGA_Spartan6/M1_RAS# )
  (   24 GND )
  (   25 ? )
  (   26 ? )
  (   27 ? )
  (   28 /FPGA_Spartan6/M1_A10 )
  (   29 /FPGA_Spartan6/M1_A0 )
  (   30 /FPGA_Spartan6/M1_A1 )
  (   31 /FPGA_Spartan6/M1_A2 )
  (   32 /DDR_Banks/M1_A3 )
  (   33 N-000047 )
  (   34 GND )
  (   35 /FPGA_Spartan6/M1_A4 )
  (   36 /DDR_Banks/M1_A5 )
  (   37 /DDR_Banks/M1_A6 )
  (   38 /DDR_Banks/M1_A7 )
  (   39 /FPGA_Spartan6/M1_A8 )
  (   40 /FPGA_Spartan6/M1_A9 )
  (   41 /FPGA_Spartan6/M1_A11 )
  (   42 /DDR_Banks/M1_A12 )
  (   43 ? )
  (   44 /FPGA_Spartan6/M1_CLK# )
  (   45 /FPGA_Spartan6/M1_CKE )
  (   46 /FPGA_Spartan6/M1_CLK )
  (   47 /DDR_Banks/M1_UDM )
  (   48 GND )
  (   49 ? )
  (   50 ? )
  (   51 /FPGA_Spartan6/M1_UDQS )
  (   52 GND )
  (   53 ? )
  (   54 /DDR_Banks/M1_DQ8 )
  (   55 N-000047 )
  (   56 /FPGA_Spartan6/M1_DQ9 )
  (   57 /DDR_Banks/M1_DQ10 )
  (   58 GND )
  (   59 /DDR_Banks/M1_DQ11 )
  (   60 /FPGA_Spartan6/M1_DQ12 )
  (   61 N-000047 )
  (   62 /FPGA_Spartan6/M1_DQ13 )
  (   63 /DDR_Banks/M1_DQ14 )
  (   64 GND )
  (   65 /DDR_Banks/M1_DQ15 )
  (   66 GND )
 )
 ( /4C421DD3/4C609B99 $noname  U2 MT46V32M16TG {Lib=MT46V32M16TG}
  (    1 N-000054 )
  (    2 /FPGA_Spartan6/M0_DQ0 )
  (    3 N-000054 )
  (    4 /FPGA_Spartan6/M0_DQ1 )
  (    5 /FPGA_Spartan6/M0_DQ2 )
  (    6 GND )
  (    7 /DDR_Banks/M0_DQ3 )
  (    8 /FPGA_Spartan6/M0_DQ4 )
  (    9 N-000054 )
  (   10 /FPGA_Spartan6/M0_DQ5 )
  (   11 /FPGA_Spartan6/M0_DQ6 )
  (   12 GND )
  (   13 /FPGA_Spartan6/M0_DQ7 )
  (   14 ? )
  (   15 N-000054 )
  (   16 /DDR_Banks/M0_LDQS )
  (   17 ? )
  (   18 N-000054 )
  (   19 ? )
  (   20 /DDR_Banks/M0_LDM )
  (   21 /FPGA_Spartan6/M0_WE# )
  (   22 /DDR_Banks/M0_CAS# )
  (   23 /DDR_Banks/M0_RAS# )
  (   24 GND )
  (   25 ? )
  (   26 ? )
  (   27 ? )
  (   28 /DDR_Banks/M0_A10 )
  (   29 /FPGA_Spartan6/M0_A0 )
  (   30 /DDR_Banks/M0_A1 )
  (   31 /FPGA_Spartan6/M0_A2 )
  (   32 /FPGA_Spartan6/M0_A3 )
  (   33 N-000054 )
  (   34 GND )
  (   35 /FPGA_Spartan6/M0_A4 )
  (   36 /FPGA_Spartan6/M0_A5 )
  (   37 /DDR_Banks/M0_A6 )
  (   38 /DDR_Banks/M0_A7 )
  (   39 /FPGA_Spartan6/M0_A8 )
  (   40 /FPGA_Spartan6/M0_A9 )
  (   41 /FPGA_Spartan6/M0_A11 )
  (   42 /DDR_Banks/M0_A12 )
  (   43 ? )
  (   44 /DDR_Banks/M0_CLK# )
  (   45 /FPGA_Spartan6/M0_CKE )
  (   46 /FPGA_Spartan6/M0_CLK )
  (   47 /FPGA_Spartan6/M0_UDM )
  (   48 GND )
  (   49 ? )
  (   50 ? )
  (   51 /DDR_Banks/M0_UDQS )
  (   52 GND )
  (   53 ? )
  (   54 /DDR_Banks/M0_DQ8 )
  (   55 N-000054 )
  (   56 /FPGA_Spartan6/M0_DQ9 )
  (   57 /DDR_Banks/M0_DQ10 )
  (   58 GND )
  (   59 /FPGA_Spartan6/M0_DQ11 )
  (   60 /FPGA_Spartan6/M0_DQ12 )
  (   61 N-000054 )
  (   62 /FPGA_Spartan6/M0_DQ13 )
  (   63 /FPGA_Spartan6/M0_DQ14 )
  (   64 GND )
  (   65 /FPGA_Spartan6/M0_DQ15 )
  (   66 GND )
 )
)
*
{ Allowed footprints by component:
$component R10
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C16
 SM*
 C?
 C1-1
$endlist
$component C15
 SM*
 C?
 C1-1
$endlist
$component C14
 SM*
 C?
 C1-1
$endlist
$component C13
 SM*
 C?
 C1-1
$endlist
$component C9
 SM*
 C?
 C1-1
$endlist
$component C6
 SM*
 C?
 C1-1
$endlist
$component C4
 SM*
 C?
 C1-1
$endlist
$component C2
 SM*
 C?
 C1-1
$endlist
$component C8
 SM*
 C?
 C1-1
$endlist
$component C7
 SM*
 C?
 C1-1
$endlist
$component C5
 SM*
 C?
 C1-1
$endlist
$component C3
 SM*
 C?
 C1-1
$endlist
$component C1
 SM*
 C?
 C1-1
$endlist
$component R1
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R2
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component C11
 SM*
 C?
 C1-1
$endlist
$component C10
 SM*
 C?
 C1-1
$endlist
$component C12
 SM*
 C?
 C1-1
$endlist
$component R9
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R3
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R4
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R6
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R5
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R8
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R7
 R?
 SM0603
 SM0805
 R?-*
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 5 "/Ethernet Phy/ETH_INT" "ETH_INT"
 U4 25
 U1 A5
Net 6 "/FPGA Spartan6/M1_CAS#" "M1_CAS#"
 U3 22
 U1 H22
Net 7 "/FPGA Spartan6/M1_CKE" "M1_CKE"
 U1 D21
 U3 45
Net 8 "/FPGA Spartan6/M1_CLK" "M1_CLK"
 U1 H20
 U3 46
Net 9 "/FPGA Spartan6/M1_CLK#" "M1_CLK#"
 U3 44
 U1 J19
Net 10 "GND" "GND"
 U3 58
 U2 6
 U2 66
 U2 48
 U2 58
 J1 COM
 J1 CASE
 J1 CASE
 J1 CASE
 U5 13
 U5 36
 U2 12
 U2 52
 U2 24
 U2 34
 U2 64
 U3 48
 U4 35
 U4 36
 U4 39
 U4 12
 U4 23
 U4 44
 J4 5
 J4 4
 C2 2
 C16 2
 V1 2
 V2 2
 J5 4
 C15 2
 C14 2
 C13 2
 U6 7
 U6 8
 R10 2
 R2 2
 C11 2
 C10 2
 C12 2
 R9 2
 U4 8
 C1 2
 C3 2
 C5 2
 C7 2
 C8 2
 U1 B13
 U1 J13
 U1 L13
 U1 N13
 U1 K14
 U1 J21
 U1 N21
 U1 U21
 U1 AB1
 U1 M12
 U1 P12
 U1 A22
 U1 W16
 U1 R5
 U1 E7
 U1 H7
 U1 U7
 U1 W7
 U1 A1
 U1 E2
 U1 J2
 U1 M10
 U1 P10
 U1 V10
 U1 J11
 U1 L11
 U1 N11
 U1 E21
 U1 B9
 U1 J9
 U1 L9
 U1 N9
 U1 K10
 U1 B17
 U1 N17
 U1 D18
 U1 G18
 U1 L18
 U1 R18
 U1 W19
 U1 AA9
 U1 AB22
 U1 AA13
 U1 AA17
 U1 M14
 U1 P14
 U1 V14
 U1 E15
 U1 J15
 U1 AA5
 U1 N2
 U1 U2
 U1 D4
 U1 V4
 U1 B5
 U1 G5
 U1 L5
 U3 24
 U3 34
 U3 64
 U3 66
 U3 6
 U3 12
 U3 52
Net 11 "/DDR Banks/M0_CLK#" "M0_CLK#"
 U1 H3
 U2 44
Net 12 "/FPGA Spartan6/M0_CLK" "M0_CLK"
 U2 46
 U1 H4
Net 13 "/FPGA Spartan6/M0_CKE" "M0_CKE"
 U2 45
 U1 D2
Net 14 "/DDR Banks/M0_CAS#" "M0_CAS#"
 U1 K4
 U2 22
Net 15 "/DDR Banks/M1_WE#" "M1_WE#"
 U3 21
 U1 H19
Net 16 "/DDR Banks/M0_RAS#" "M0_RAS#"
 U1 K5
 U2 23
Net 17 "/FPGA Spartan6/M0_WE#" "M0_WE#"
 U1 F2
 U2 21
Net 18 "/FPGA Spartan6/M1_RAS#" "M1_RAS#"
 U1 H21
 U3 23
Net 26 "/FPGA Spartan6/M1_LDM" "M1_LDM"
 U1 L19
 U3 20
Net 27 "/DDR Banks/M1_LDQS" "M1_LDQS"
 U1 L20
 U3 16
Net 28 "/DDR Banks/M1_UDM" "M1_UDM"
 U1 M20
 U3 47
Net 29 "/FPGA Spartan6/M0_UDM" "M0_UDM"
 U1 M3
 U2 47
Net 30 "/FPGA Spartan6/M1_UDQS" "M1_UDQS"
 U3 51
 U1 T21
Net 31 "/DDR Banks/M0_UDQS" "M0_UDQS"
 U1 T2
 U2 51
Net 32 "/DDR Banks/M0_LDM" "M0_LDM"
 U1 L4
 U2 20
Net 33 "/DDR Banks/M0_LDQS" "M0_LDQS"
 U1 L3
 U2 16
Net 36 "/ETH_MDIO" "ETH_MDIO"
 U4 1
 R1 1
Net 47 "" ""
 U3 9
 U3 55
 U3 15
 U3 1
 U3 3
 U3 61
 U3 18
 U3 33
Net 54 "" ""
 U2 61
 U2 33
 U2 18
 U2 15
 U2 3
 U2 1
 U2 55
 U2 9
Net 117 "/Non volatile memories/FRB_N" "FRB_N"
 U5 6
 U5 7
Net 122 "3.3V" "3.3V"
 C1 1
 C3 1
 U6 12
 C5 1
 U6 14
 R1 2
 J4 3
 U4 7
 C14 1
 L2 1
 C15 1
 C10 1
 C11 1
 U5 12
 U5 19
 U5 37
 C13 1
 R3 1
 U4 24
 J4 6
 J4 9
 J4 11
 U6 1
 R5 1
 R6 1
 R4 1
Net 137 "" ""
 U1 B4
 U1 B11
 U1 G10
 U1 B19
 U1 E17
 U1 E13
 U1 G14
 U1 E9
 U1 B15
 U1 B7
Net 153 "" ""
 U1 R2
 U1 L2
 U1 G2
 U1 C2
 U1 F4
 U1 N5
 U1 U5
 U1 F6
 U1 J5
 U1 L7
 U1 W2
Net 154 "" ""
 U1 AA19
 U1 AA11
 U1 AA15
 U1 AA7
 U1 AA3
 U1 T13
 U1 V12
 U1 V16
 U1 V8
 U1 W5
 U1 T9
Net 155 "" ""
 U1 U18
 U1 E19
 U1 L16
 U1 R21
 U1 W21
 U1 L21
 U1 G21
 U1 C21
 U1 J18
 U1 N18
Net 156 "" ""
 U1 K13
 U1 M13
 U1 P13
 U1 J14
 U1 J12
 U1 L12
 U1 N12
 U1 R14
 U1 L14
 U1 N14
 U1 L10
 U1 J10
 U1 P9
 U1 M9
 U1 K9
 U1 J8
 U1 P11
 U1 M11
 U1 K11
 U1 N10
Net 157 "" ""
 U1 R12
 U1 D16
 U1 M15
 U1 H9
 U1 N8
 U1 L8
 U1 U11
 U1 K15
 U1 H15
 U1 F11
 U1 R10
 U1 V6
 U1 R6
 U1 G12
Net 396 "" ""
 R7 1
 J4 10
Net 397 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
 R7 2
 U4 26
Net 398 "" ""
 U4 41
 R3 2
 J4 1
Net 399 "" ""
 J4 7
 R5 2
 U4 33
Net 400 "" ""
 C12 1
 R9 1
 J4 14
 J4 13
Net 401 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V"
 C2 1
 U4 13
Net 402 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
 C9 1
 L3 2
 U4 47
Net 403 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
 U4 38
 C7 1
 C8 1
 L2 2
Net 404 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
 R8 2
 U4 27
Net 405 "" ""
 R8 1
 J4 12
Net 406 "" ""
 R2 1
 U4 37
Net 407 "" ""
 R6 2
 U4 32
 J4 8
Net 408 "" ""
 R4 2
 J4 2
 U4 40
Net 416 "" ""
 C4 2
 C6 2
 C9 2
Net 417 "" ""
 L1 1
 C4 1
Net 418 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
 L3 1
 C6 1
 U4 31
 L1 2
Net 419 "" ""
 J5 2
 V2 1
 V2 1
 U6 10
Net 420 "" ""
 V1 1
 V1 1
 U6 11
 J5 3
Net 425 "" ""
 J5 1
 F1 1
Net 426 "" ""
 J5 S1
 R10 1
 C16 1
 J5 S2
 J5 S3
 J5 S4
Net 438 "/FPGA Spartan6/M0_DQ0" "M0_DQ0"
 U1 N3
 U2 2
Net 442 "/FPGA Spartan6/M1_DQ0" "M1_DQ0"
 U3 2
 U1 N20
Net 443 "/FPGA Spartan6/M1_DQ1" "M1_DQ1"
 U3 4
 U1 N22
Net 447 "/DDR Banks/M1_DQ5" "M1_DQ5"
 U1 J22
 U3 10
Net 448 "/FPGA Spartan6/M1_DQ6" "M1_DQ6"
 U3 11
 U1 K21
Net 449 "/FPGA Spartan6/M1_DQ7" "M1_DQ7"
 U3 13
 U1 K22
Net 450 "/DDR Banks/M1_DQ8" "M1_DQ8"
 U1 P21
 U3 54
Net 451 "/FPGA Spartan6/M1_DQ9" "M1_DQ9"
 U3 56
 U1 P22
Net 452 "/DDR Banks/M1_DQ10" "M1_DQ10"
 U1 R20
 U3 57
Net 453 "/DDR Banks/M1_DQ15" "M1_DQ15"
 U3 65
 U1 V22
Net 454 "/DDR Banks/M1_DQ14" "M1_DQ14"
 U3 63
 U1 V21
Net 455 "/FPGA Spartan6/M1_DQ13" "M1_DQ13"
 U3 62
 U1 U22
Net 456 "/FPGA Spartan6/M1_DQ12" "M1_DQ12"
 U1 U20
 U3 60
Net 457 "/DDR Banks/M1_DQ11" "M1_DQ11"
 U1 R22
 U3 59
Net 458 "/FPGA Spartan6/M1_A0" "M1_A0"
 U3 29
 U1 F21
Net 459 "/FPGA Spartan6/M1_A1" "M1_A1"
 U3 30
 U1 F22
Net 460 "/FPGA Spartan6/M1_A2" "M1_A2"
 U1 E22
 U3 31
Net 461 "/DDR Banks/M1_A3" "M1_A3"
 U1 G20
 U3 32
Net 462 "/FPGA Spartan6/M1_A4" "M1_A4"
 U1 F20
 U3 35
Net 463 "/DDR Banks/M1_A5" "M1_A5"
 U1 K20
 U3 36
Net 464 "/DDR Banks/M1_A6" "M1_A6"
 U1 K19
 U3 37
Net 465 "/DDR Banks/M1_A7" "M1_A7"
 U1 E20
 U3 38
Net 466 "/FPGA Spartan6/M1_A8" "M1_A8"
 U3 39
 U1 C20
Net 467 "/FPGA Spartan6/M1_A9" "M1_A9"
 U1 C22
 U3 40
Net 468 "/FPGA Spartan6/M1_A10" "M1_A10"
 U1 G19
 U3 28
Net 469 "/FPGA Spartan6/M1_A11" "M1_A11"
 U1 F19
 U3 41
Net 470 "/DDR Banks/M1_A12" "M1_A12"
 U3 42
 U1 D22
Net 471 "/FPGA Spartan6/M0_DQ1" "M0_DQ1"
 U1 N1
 U2 4
Net 472 "/FPGA Spartan6/M0_DQ2" "M0_DQ2"
 U1 M2
 U2 5
Net 473 "/DDR Banks/M0_DQ3" "M0_DQ3"
 U1 M1
 U2 7
Net 474 "/FPGA Spartan6/M0_DQ4" "M0_DQ4"
 U1 J3
 U2 8
Net 475 "/FPGA Spartan6/M0_DQ5" "M0_DQ5"
 U2 10
 U1 J1
Net 476 "/FPGA Spartan6/M0_DQ6" "M0_DQ6"
 U2 11
 U1 K2
Net 477 "/FPGA Spartan6/M0_DQ7" "M0_DQ7"
 U1 K1
 U2 13
Net 478 "/DDR Banks/M0_DQ8" "M0_DQ8"
 U1 P2
 U2 54
Net 479 "/FPGA Spartan6/M0_DQ9" "M0_DQ9"
 U1 P1
 U2 56
Net 480 "/DDR Banks/M0_DQ10" "M0_DQ10"
 U2 57
 U1 R3
Net 481 "/FPGA Spartan6/M0_DQ11" "M0_DQ11"
 U1 R1
 U2 59
Net 482 "/FPGA Spartan6/M0_DQ12" "M0_DQ12"
 U2 60
 U1 U3
Net 483 "/FPGA Spartan6/M0_DQ13" "M0_DQ13"
 U2 62
 U1 U1
Net 484 "/FPGA Spartan6/M0_DQ14" "M0_DQ14"
 U2 63
 U1 V2
Net 485 "/FPGA Spartan6/M0_DQ15" "M0_DQ15"
 U1 V1
 U2 65
Net 486 "/DDR Banks/M0_A12" "M0_A12"
 U2 42
 U1 D1
Net 487 "/FPGA Spartan6/M0_A11" "M0_A11"
 U1 C1
 U2 41
Net 488 "/DDR Banks/M0_A10" "M0_A10"
 U2 28
 U1 G4
Net 489 "/FPGA Spartan6/M0_A9" "M0_A9"
 U2 40
 U1 E1
Net 490 "/FPGA Spartan6/M0_A8" "M0_A8"
 U1 E3
 U2 39
Net 491 "/DDR Banks/M0_A7" "M0_A7"
 U2 38
 U1 H6
Net 492 "/DDR Banks/M0_A6" "M0_A6"
 U1 J4
 U2 37
Net 493 "/FPGA Spartan6/M0_A5" "M0_A5"
 U2 36
 U1 K3
Net 494 "/FPGA Spartan6/M0_A4" "M0_A4"
 U2 35
 U1 F3
Net 495 "/FPGA Spartan6/M0_A3" "M0_A3"
 U2 32
 U1 K6
Net 496 "/FPGA Spartan6/M0_A2" "M0_A2"
 U1 H5
 U2 31
Net 497 "/DDR Banks/M0_A1" "M0_A1"
 U2 30
 U1 H1
Net 498 "/FPGA Spartan6/M0_A0" "M0_A0"
 U1 H2
 U2 29
}
#End