2010-08-23 01:24:37 +03:00
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EESchema Schematic File Version 2 date Sun 22 Aug 2010 05:24:03 PM COT
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2010-08-22 21:35:28 +03:00
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LIBS:power
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LIBS:r_pack2
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LIBS:v0402mhs03
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LIBS:usb-48204-0001
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LIBS:microsmd075f
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LIBS:mic2550ayts
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LIBS:rj45-48025
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LIBS:xue-nv
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LIBS:xc6slx75fgg484
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LIBS:xc6slx45fgg484
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LIBS:micron_mobile_ddr
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LIBS:micron_ddr_512Mb
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LIBS:k8001
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:special
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:pasives-connectors
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LIBS:x25x64mb
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LIBS:attiny
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LIBS:PSU
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LIBS:xue-rnc-cache
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EELAYER 24 0
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EELAYER END
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$Descr A4 11700 8267
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Sheet 2 8
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Title ""
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Date "22 aug 2010"
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Comp
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L CONN_8X2 J6
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U 1 1 4C716CAB
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P 2550 2350
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F 0 "J6" H 2550 2800 60 0000 C CNN
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F 1 "CONN_8X2" V 2550 2350 50 0000 C CNN
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1 2550 2350
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1 0 0 -1
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$EndComp
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Wire Wire Line
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2150 2200 1900 2200
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Text HLabel 1900 2200 0 60 BiDi ~ 0
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FPGA_TDO
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Text HLabel 1900 2300 0 60 BiDi ~ 0
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FPGA_TDI
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Wire Wire Line
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2150 2300 1900 2300
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Wire Wire Line
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2150 2100 1900 2100
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Text HLabel 1900 2100 0 60 BiDi ~ 0
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FPGA_TMS
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Text HLabel 1900 2000 0 60 BiDi ~ 0
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FPGA_TCK
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Wire Wire Line
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2150 2000 1900 2000
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$EndSCHEMATC
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