From 01429d2ac05e3949558735dd4e5c975959526d7e Mon Sep 17 00:00:00 2001 From: Juan64Bits Date: Mon, 30 Aug 2010 19:48:29 -0500 Subject: [PATCH] Making power source --- kicad/xue-rnc/DBG_PRG.sch | 4 +- kicad/xue-rnc/DRAM.sch | 68 +- kicad/xue-rnc/FPGA_0_2_PROG.sch | 76 +- kicad/xue-rnc/FPGA_1_3.sch | 16 +- kicad/xue-rnc/NV_MEMORIES.sch | 36 +- kicad/xue-rnc/PSU.sch | 754 +- kicad/xue-rnc/USB.sch | 80 +- kicad/xue-rnc/eth_phy.sch | 4 +- kicad/xue-rnc/xue-rnc-cache.lib | 7 +- kicad/xue-rnc/xue-rnc.brd | 16416 ++++++++++++++++-------------- kicad/xue-rnc/xue-rnc.cmp | 300 +- kicad/xue-rnc/xue-rnc.net | 5344 ++++------ kicad/xue-rnc/xue-rnc.pro | 8 +- kicad/xue-rnc/xue-rnc.sch | 4 +- 14 files changed, 11623 insertions(+), 11494 deletions(-) diff --git a/kicad/xue-rnc/DBG_PRG.sch b/kicad/xue-rnc/DBG_PRG.sch index 2cc78bb..147b725 100644 --- a/kicad/xue-rnc/DBG_PRG.sch +++ b/kicad/xue-rnc/DBG_PRG.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 30 Aug 2010 10:27:20 AM COT +EESchema Schematic File Version 2 date Mon 30 Aug 2010 07:47:12 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -51,7 +51,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 2 9 Title "" -Date "30 aug 2010" +Date "31 aug 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 9360a2f..9aea7ab 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 30 Aug 2010 10:27:20 AM COT +EESchema Schematic File Version 2 date Mon 30 Aug 2010 07:47:12 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -51,7 +51,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 7 9 Title "" -Date "30 aug 2010" +Date "31 aug 2010" Rev "" Comp "" Comment1 "" @@ -535,19 +535,19 @@ Entry Wire Line Entry Wire Line 10100 4400 10200 4500 $Comp -L GND #PWR072 +L GND #PWR077 U 1 1 4C699C4D P 9950 2100 -F 0 "#PWR072" H 9950 2100 30 0001 C CNN +F 0 "#PWR077" H 9950 2100 30 0001 C CNN F 1 "GND" H 9950 2030 30 0001 C CNN 1 9950 2100 1 0 0 -1 $EndComp $Comp -L GND #PWR073 +L GND #PWR078 U 1 1 4C699C48 P 4550 2150 -F 0 "#PWR073" H 4550 2150 30 0001 C CNN +F 0 "#PWR078" H 4550 2150 30 0001 C CNN F 1 "GND" H 4550 2080 30 0001 C CNN 1 4550 2150 1 0 0 -1 @@ -605,37 +605,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR074 +L GND #PWR079 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR074" H 6900 6200 30 0001 C CNN +F 0 "#PWR079" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR075 +L +2.5V #PWR080 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR075" H 6900 5750 20 0001 C CNN +F 0 "#PWR080" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR076 +L +2.5V #PWR081 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR076" H 1700 5750 20 0001 C CNN +F 0 "#PWR081" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR077 +L GND #PWR082 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR077" H 1700 6200 30 0001 C CNN +F 0 "#PWR082" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -651,19 +651,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR078 +L +2.5V #PWR083 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR078" H 3050 1700 20 0001 C CNN +F 0 "#PWR083" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR079 +L +2.5V #PWR084 U 1 1 4C61CFC6 P 8400 1700 -F 0 "#PWR079" H 8400 1650 20 0001 C CNN +F 0 "#PWR084" H 8400 1650 20 0001 C CNN F 1 "+2.5V" H 8400 1800 30 0000 C CNN 1 8400 1700 1 0 0 -1 @@ -729,37 +729,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR080 +L +2.5V #PWR085 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR080" H 8300 5700 20 0001 C CNN +F 0 "#PWR085" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR081 +L GND #PWR086 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR081" H 8300 6350 30 0001 C CNN +F 0 "#PWR086" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR082 +L GND #PWR087 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR082" H 3050 6350 30 0001 C CNN +F 0 "#PWR087" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR083 +L +2.5V #PWR088 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR083" H 3050 5700 20 0001 C CNN +F 0 "#PWR088" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -845,19 +845,19 @@ F 2 "0402" H 9950 1750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR084 +L +2.5V #PWR089 U 1 1 4C61CE2F P 9950 800 -F 0 "#PWR084" H 9950 750 20 0001 C CNN +F 0 "#PWR089" H 9950 750 20 0001 C CNN F 1 "+2.5V" H 9950 900 30 0000 C CNN 1 9950 800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR085 +L +2.5V #PWR090 U 1 1 4C61CDF1 P 4550 850 -F 0 "#PWR085" H 4550 800 20 0001 C CNN +F 0 "#PWR090" H 4550 800 20 0001 C CNN F 1 "+2.5V" H 4550 950 30 0000 C CNN 1 4550 850 1 0 0 -1 @@ -940,10 +940,10 @@ $EndComp Text HLabel 5000 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR086 +L GND #PWR091 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR086" H 3000 5200 30 0001 C CNN +F 0 "#PWR091" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1219,10 +1219,10 @@ Entry Wire Line Entry Wire Line 10100 3600 10200 3700 $Comp -L GND #PWR087 +L GND #PWR092 U 1 1 4C437C3F P 8350 5150 -F 0 "#PWR087" H 8350 5150 30 0001 C CNN +F 0 "#PWR092" H 8350 5150 30 0001 C CNN F 1 "GND" H 8350 5080 30 0001 C CNN 1 8350 5150 1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA_0_2_PROG.sch b/kicad/xue-rnc/FPGA_0_2_PROG.sch index 3360e92..3e699c7 100644 --- a/kicad/xue-rnc/FPGA_0_2_PROG.sch +++ b/kicad/xue-rnc/FPGA_0_2_PROG.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 30 Aug 2010 10:27:20 AM COT +EESchema Schematic File Version 2 date Mon 30 Aug 2010 07:47:12 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -51,7 +51,7 @@ EELAYER END $Descr A3 16535 11700 Sheet 2 9 Title "" -Date "30 aug 2010" +Date "31 aug 2010" Rev "" Comp "" Comment1 "" @@ -924,19 +924,19 @@ F 2 "0402" H 7150 7800 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR051 +L +3.3V #PWR01 U 1 1 4C7168D5 P 7150 7500 -F 0 "#PWR051" H 7150 7460 30 0001 C CNN +F 0 "#PWR01" H 7150 7460 30 0001 C CNN F 1 "+3.3V" H 7150 7610 30 0000 C CNN 1 7150 7500 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR052 +L +3.3V #PWR02 U 1 1 4C716889 P 15400 7850 -F 0 "#PWR052" H 15400 7810 30 0001 C CNN +F 0 "#PWR02" H 15400 7810 30 0001 C CNN F 1 "+3.3V" H 15400 7960 30 0000 C CNN 1 15400 7850 1 0 0 -1 @@ -952,10 +952,10 @@ F 2 "0402" H 15400 8150 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR053 +L GND #PWR03 U 1 1 4C716816 P 14750 8600 -F 0 "#PWR053" H 14750 8600 30 0001 C CNN +F 0 "#PWR03" H 14750 8600 30 0001 C CNN F 1 "GND" H 14750 8530 30 0001 C CNN 1 14750 8600 1 0 0 -1 @@ -1017,28 +1017,28 @@ VCC02 Text GLabel 5200 800 3 30 BiDi ~ 0 VCCO2 $Comp -L +3.3V #PWR054 +L +3.3V #PWR04 U 1 1 4C65CF66 P 1150 10400 -F 0 "#PWR054" H 1150 10360 30 0001 C CNN +F 0 "#PWR04" H 1150 10360 30 0001 C CNN F 1 "+3.3V" H 1150 10510 30 0000 C CNN 1 1150 10400 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR055 +L +2.5V #PWR05 U 1 1 4C65C84B P 4100 10400 -F 0 "#PWR055" H 4100 10350 20 0001 C CNN +F 0 "#PWR05" H 4100 10350 20 0001 C CNN F 1 "+2.5V" H 4100 10500 30 0000 C CNN 1 4100 10400 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR056 +L +2.5V #PWR06 U 1 1 4C65C837 P 4100 8450 -F 0 "#PWR056" H 4100 8400 20 0001 C CNN +F 0 "#PWR06" H 4100 8400 20 0001 C CNN F 1 "+2.5V" H 4100 8550 30 0000 C CNN 1 4100 8450 1 0 0 -1 @@ -1085,10 +1085,10 @@ F 1 "470nF" H 5550 8650 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR057 +L GND #PWR07 U 1 1 4C656D9B P 4100 9050 -F 0 "#PWR057" H 4100 9050 30 0001 C CNN +F 0 "#PWR07" H 4100 9050 30 0001 C CNN F 1 "GND" H 4100 8980 30 0001 C CNN 1 4100 9050 1 0 0 -1 @@ -1150,10 +1150,10 @@ F 1 "470nF" H 5550 9650 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR058 +L GND #PWR08 U 1 1 4C656D47 P 4100 10050 -F 0 "#PWR058" H 4100 10050 30 0001 C CNN +F 0 "#PWR08" H 4100 10050 30 0001 C CNN F 1 "GND" H 4100 9980 30 0001 C CNN 1 4100 10050 1 0 0 -1 @@ -1206,10 +1206,10 @@ F 1 "470nF" H 5550 10600 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR059 +L GND #PWR09 U 1 1 4C656CFD P 4100 11000 -F 0 "#PWR059" H 4100 11000 30 0001 C CNN +F 0 "#PWR09" H 4100 11000 30 0001 C CNN F 1 "GND" H 4100 10930 30 0001 C CNN 1 4100 11000 1 0 0 -1 @@ -1253,10 +1253,10 @@ F 1 "100uF" H 4150 10600 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR060 +L GND #PWR010 U 1 1 4C656CBC P 1150 11000 -F 0 "#PWR060" H 1150 11000 30 0001 C CNN +F 0 "#PWR010" H 1150 11000 30 0001 C CNN F 1 "GND" H 1150 10930 30 0001 C CNN 1 1150 11000 1 0 0 -1 @@ -1302,10 +1302,10 @@ $EndComp Text Notes 1250 9500 0 30 ~ 0 VCC_AUX Decoupling Capacitors (7) $Comp -L GND #PWR061 +L GND #PWR011 U 1 1 4C656C68 P 1150 10100 -F 0 "#PWR061" H 1150 10100 30 0001 C CNN +F 0 "#PWR011" H 1150 10100 30 0001 C CNN F 1 "GND" H 1150 10030 30 0001 C CNN 1 1150 10100 1 0 0 -1 @@ -1374,19 +1374,19 @@ F 1 "100uF" H 1200 9700 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR062 +L +2.5V #PWR012 U 1 1 4C656BBA P 1150 9500 -F 0 "#PWR062" H 1150 9450 20 0001 C CNN +F 0 "#PWR012" H 1150 9450 20 0001 C CNN F 1 "+2.5V" H 1150 9600 30 0000 C CNN 1 1150 9500 1 0 0 -1 $EndComp $Comp -L GND #PWR063 +L GND #PWR013 U 1 1 4C656BA8 P 1150 9050 -F 0 "#PWR063" H 1150 9050 30 0001 C CNN +F 0 "#PWR013" H 1150 9050 30 0001 C CNN F 1 "GND" H 1150 8980 30 0001 C CNN 1 1150 9050 1 0 0 -1 @@ -1421,10 +1421,10 @@ F 1 "4.7uF" H 1550 8650 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR064 +L +1.2V #PWR014 U 1 1 4C656AA1 P 1150 8450 -F 0 "#PWR064" H 1150 8590 20 0001 C CNN +F 0 "#PWR014" H 1150 8590 20 0001 C CNN F 1 "+1.2V" H 1150 8560 30 0000 C CNN 1 1150 8450 1 0 0 -1 @@ -1489,28 +1489,28 @@ NF_RE_N Text HLabel 13750 4650 2 60 BiDi ~ 0 NF_RNB $Comp -L +3.3V #PWR065 +L +3.3V #PWR015 U 1 1 4C61E5B3 P 11650 3100 -F 0 "#PWR065" H 11650 3060 30 0001 C CNN +F 0 "#PWR015" H 11650 3060 30 0001 C CNN F 1 "+3.3V" H 11650 3210 30 0000 C CNN 1 11650 3100 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR066 +L +1.2V #PWR016 U 1 1 4C61E58C P 11550 7400 -F 0 "#PWR066" H 11550 7540 20 0001 C CNN +F 0 "#PWR016" H 11550 7540 20 0001 C CNN F 1 "+1.2V" H 11550 7510 30 0000 C CNN 1 11550 7400 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR067 +L +2.5V #PWR017 U 1 1 4C61E577 P 10050 7400 -F 0 "#PWR067" H 10050 7350 20 0001 C CNN +F 0 "#PWR017" H 10050 7350 20 0001 C CNN F 1 "+2.5V" H 10050 7500 30 0000 C CNN 1 10050 7400 1 0 0 -1 @@ -1596,10 +1596,10 @@ ETH_MDC Text HLabel 9950 5750 0 60 BiDi ~ 0 ETH_INT $Comp -L GND #PWR071 +L GND #PWR018 U 1 1 4C439B7E P 11450 10200 -F 0 "#PWR071" H 11450 10200 30 0001 C CNN +F 0 "#PWR018" H 11450 10200 30 0001 C CNN F 1 "GND" H 11450 10130 30 0001 C CNN 1 11450 10200 -1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA_1_3.sch b/kicad/xue-rnc/FPGA_1_3.sch index d46a9eb..84ed122 100644 --- a/kicad/xue-rnc/FPGA_1_3.sch +++ b/kicad/xue-rnc/FPGA_1_3.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 30 Aug 2010 10:27:20 AM COT +EESchema Schematic File Version 2 date Mon 30 Aug 2010 07:47:12 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -51,7 +51,7 @@ EELAYER END $Descr A3 16535 11700 Sheet 3 9 Title "" -Date "30 aug 2010" +Date "31 aug 2010" Rev "" Comp "" Comment1 "" @@ -1452,19 +1452,19 @@ F 1 "R_PACK4" H 3400 6600 40 0000 C CNN -1 0 0 1 $EndComp $Comp -L +2.5V #PWR068 +L +2.5V #PWR019 U 1 1 4C61E523 P 9200 6250 -F 0 "#PWR068" H 9200 6200 20 0001 C CNN +F 0 "#PWR019" H 9200 6200 20 0001 C CNN F 1 "+2.5V" H 9200 6350 30 0000 C CNN 1 9200 6250 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR069 +L +2.5V #PWR020 U 1 1 4C61E51F P 9200 850 -F 0 "#PWR069" H 9200 800 20 0001 C CNN +F 0 "#PWR020" H 9200 800 20 0001 C CNN F 1 "+2.5V" H 9200 950 30 0000 C CNN 1 9200 850 1 0 0 -1 @@ -1482,10 +1482,10 @@ M1_BA[0..1] Text HLabel 4700 9500 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR070 +L GND #PWR021 U 1 1 4C60C21D P 5700 5350 -F 0 "#PWR070" H 5700 5350 30 0001 C CNN +F 0 "#PWR021" H 5700 5350 30 0001 C CNN F 1 "GND" H 5700 5280 30 0001 C CNN 1 5700 5350 -1 0 0 -1 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index a3a0be1..66a8060 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 30 Aug 2010 10:27:20 AM COT +EESchema Schematic File Version 2 date Mon 30 Aug 2010 07:47:12 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -51,7 +51,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 4 9 Title "" -Date "30 aug 2010" +Date "31 aug 2010" Rev "" Comp "" Comment1 "" @@ -244,19 +244,19 @@ F 1 "100nF" H 4000 5400 50 0000 L CNN -1 0 0 1 $EndComp $Comp -L GND #PWR024 +L GND #PWR050 U 1 1 4C65D6AB P 9350 3150 -F 0 "#PWR024" H 9350 3150 30 0001 C CNN +F 0 "#PWR050" H 9350 3150 30 0001 C CNN F 1 "GND" H 9350 3080 30 0001 C CNN 1 9350 3150 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR025 +L +3.3V #PWR051 U 1 1 4C65D69B P 9350 2650 -F 0 "#PWR025" H 9350 2610 30 0001 C CNN +F 0 "#PWR051" H 9350 2610 30 0001 C CNN F 1 "+3.3V" H 9350 2760 30 0000 C CNN 1 9350 2650 1 0 0 -1 @@ -320,10 +320,10 @@ SPI_DQ[0..3] Text HLabel 2450 1700 0 60 Input ~ 0 SPI_FLASH_CS# $Comp -L GND #PWR026 +L GND #PWR052 U 1 1 4C65ABE9 P 2650 2450 -F 0 "#PWR026" H 2650 2450 30 0001 C CNN +F 0 "#PWR052" H 2650 2450 30 0001 C CNN F 1 "GND" H 2650 2380 30 0001 C CNN 1 2650 2450 1 0 0 -1 @@ -356,19 +356,19 @@ Entry Wire Line Entry Wire Line 8150 3150 8250 3050 $Comp -L +3.3V #PWR027 +L +3.3V #PWR053 U 1 1 4C646C14 P 7950 2900 -F 0 "#PWR027" H 7950 2860 30 0001 C CNN +F 0 "#PWR053" H 7950 2860 30 0001 C CNN F 1 "+3.3V" H 7950 3010 30 0000 C CNN 1 7950 2900 1 0 0 -1 $EndComp $Comp -L GND #PWR028 +L GND #PWR054 U 1 1 4C646BEA P 7950 3000 -F 0 "#PWR028" H 7950 3000 30 0001 C CNN +F 0 "#PWR054" H 7950 3000 30 0001 C CNN F 1 "GND" H 7950 2930 30 0001 C CNN 1 7950 3000 1 0 0 -1 @@ -418,10 +418,10 @@ SD_DAT3 Text Label 4200 6100 0 30 ~ 0 SD_CMD $Comp -L GND #PWR029 +L GND #PWR055 U 1 1 4C61D875 P 3950 5800 -F 0 "#PWR029" H 3950 5800 30 0001 C CNN +F 0 "#PWR055" H 3950 5800 30 0001 C CNN F 1 "GND" H 3950 5730 30 0001 C CNN 1 3950 5800 1 0 0 -1 @@ -433,19 +433,19 @@ SD_DAT0 Text Label 4200 5850 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR030 +L GND #PWR056 U 1 1 4C438ADC P 5800 6200 -F 0 "#PWR030" H 5800 6200 30 0001 C CNN +F 0 "#PWR056" H 5800 6200 30 0001 C CNN F 1 "GND" H 5800 6130 30 0001 C CNN 1 5800 6200 1 0 0 -1 $EndComp $Comp -L GND #PWR031 +L GND #PWR057 U 1 1 4C438AD5 P 5350 6550 -F 0 "#PWR031" H 5350 6550 30 0001 C CNN +F 0 "#PWR057" H 5350 6550 30 0001 C CNN F 1 "GND" H 5350 6480 30 0001 C CNN 1 5350 6550 1 0 0 -1 diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index ffee70e..393583a 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 30 Aug 2010 10:27:20 AM COT +EESchema Schematic File Version 2 date Mon 30 Aug 2010 07:47:12 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,9 +49,9 @@ LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 3 9 +Sheet 5 9 Title "" -Date "30 aug 2010" +Date "31 aug 2010" Rev "" Comp "" Comment1 "" @@ -59,254 +59,488 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Text Label 7750 5100 0 60 ~ 12 +lout_5.0 Wire Wire Line - 7000 2700 8250 2700 + 8250 5500 7750 5500 Wire Wire Line - 8650 2200 8850 2200 + 8250 5100 7750 5100 Wire Wire Line - 5800 3050 6200 3050 + 3100 6400 3100 6550 Wire Wire Line - 7300 2950 7350 2950 + 3100 6550 3550 6550 Wire Wire Line - 6200 3650 6200 3600 + 3550 6550 3550 6450 Wire Wire Line - 6200 3050 6200 3100 + 3650 5800 3700 5800 Wire Wire Line - 6200 2700 6200 2950 + 2700 5850 2700 6050 Wire Wire Line - 6100 2700 6500 2700 -Connection ~ 6200 2700 + 2700 5250 2700 5450 +Connection ~ 3450 5350 Wire Wire Line - 7500 3650 7500 3450 + 3700 5350 3450 5350 +Connection ~ 5300 5400 Wire Wire Line - 7500 2700 7500 3250 -Connection ~ 7500 2700 + 5450 5400 5150 5400 Wire Wire Line - 7350 2950 7350 2700 -Connection ~ 7350 2700 + 5300 5400 5300 5300 Wire Wire Line - 7300 3050 7300 3650 + 5300 5300 5150 5300 Wire Wire Line - 8850 3650 8850 3550 -Connection ~ 10100 2700 + 6050 5400 6400 5400 Wire Wire Line - 8250 5300 7750 5300 + 8050 2200 7850 2200 +Connection ~ 7850 2700 Wire Wire Line - 700 1100 1100 1100 + 7850 2200 7850 2700 Wire Wire Line - 7400 1100 7400 1700 -Connection ~ 7450 750 + 8250 3050 8150 3050 +Connection ~ 7650 2700 Wire Wire Line - 7450 750 7450 1000 + 7650 3050 7650 2700 +Connection ~ 10200 2700 Wire Wire Line - 1100 1700 1100 1650 + 9450 2700 10300 2700 +Connection ~ 10200 3250 Wire Wire Line - 1100 1100 1100 1150 + 10200 2700 10200 3250 Wire Wire Line - 1100 750 1100 1000 -Connection ~ 2200 750 + 10000 3300 10000 3250 Wire Wire Line - 2200 1300 2200 1100 -Connection ~ 2400 750 + 10000 3250 10350 3250 Wire Wire Line - 3850 1650 3850 1700 -Connection ~ 4550 1600 + 10350 3250 10350 3300 Wire Wire Line - 4700 1550 4700 1600 + 10000 3500 10000 3550 +Connection ~ 10100 2900 Wire Wire Line - 4700 1600 4350 1600 + 10100 2700 10100 3050 Wire Wire Line - 4550 1600 4550 1700 -Connection ~ 4450 750 + 9700 2900 9500 2900 Wire Wire Line - 4400 1100 4450 1100 + 9500 2900 9500 3100 Wire Wire Line - 4450 950 4250 950 -Connection ~ 3850 1100 + 9550 3050 9450 3050 +Connection ~ 9500 3050 Wire Wire Line - 2400 1700 2400 1500 -Connection ~ 2500 750 + 10100 2900 9900 2900 Wire Wire Line - 3150 6350 3150 6400 -Wire Wire Line - 3150 6400 2850 6400 -Wire Wire Line - 2850 6400 2850 6350 -Connection ~ 8200 4900 -Wire Wire Line - 8250 4900 8050 4900 -Wire Wire Line - 8250 5000 8200 5000 -Wire Wire Line - 8200 5000 8200 4900 -Wire Wire Line - 8050 4900 8050 4950 -Wire Wire Line - 8250 4800 8050 4800 -Wire Wire Line - 8050 4800 8050 4700 -Wire Wire Line - 3000 6450 3000 6350 -Connection ~ 3000 6400 -Wire Wire Line - 3200 1700 3200 1600 -Wire Wire Line - 2600 1100 2500 1100 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6350 +F 0 "#PWR025" H 5500 6350 30 0001 C CNN +F 1 "GND" H 5500 6280 30 0001 C CNN + 1 5500 6350 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR026 +U 1 1 4C7C4CF2 +P 6200 6350 +F 0 "#PWR026" H 6200 6350 30 0001 C CNN +F 1 "GND" H 6200 6280 30 0001 C CNN + 1 6200 6350 + 1 0 0 -1 +$EndComp +$Comp +L CAP C103 +U 1 1 4C7C4CF1 +P 6350 6100 +F 0 "C103" H 6400 6200 50 0000 L CNN +F 1 "100nF" H 6400 6000 50 0000 L CNN +F 2 "0402" H 6350 6100 60 0001 C CNN + 1 6350 6100 + 1 0 0 -1 +$EndComp +$Comp +L INDUCTOR L11 +U 1 1 4C7C4CF0 +P 5750 5400 +F 0 "L11" V 5700 5350 40 0000 C CNN +F 1 "2.2uH" V 5700 5650 40 0000 C CNN +F 2 "1210" H 5750 5400 60 0001 C CNN + 1 5750 5400 + 0 1 1 0 +$EndComp +$Comp +L R R43 +U 1 1 4C7C4CEF +P 5800 5750 +F 0 "R43" V 5880 5750 50 0000 C CNN +F 1 "51K" V 5800 5750 50 0000 C CNN +F 2 "0402" H 5800 5750 60 0001 C CNN + 1 5800 5750 + 0 1 1 0 +$EndComp +$Comp +L R R42 +U 1 1 4C7C4CEE +P 5500 6050 +F 0 "R42" V 5580 6050 50 0000 C CNN +F 1 "24K" V 5500 6050 50 0000 C CNN +F 2 "0402" H 5500 6050 60 0001 C CNN + 1 5500 6050 + 1 0 0 -1 +$EndComp +$Comp +L CAP C102 +U 1 1 4C7C4CED +P 6000 6100 +F 0 "C102" H 6050 6200 50 0000 L CNN +F 1 "10uF" H 6050 6000 50 0000 L CNN +F 2 "1206" H 6000 6100 60 0001 C CNN + 1 6000 6100 + 1 0 0 -1 +$EndComp +$Comp +L CAP C101 +U 1 1 4C7C4CEC +P 5800 5600 +F 0 "C101" V 5700 5500 50 0000 L CNN +F 1 "22pF" V 5700 5750 50 0000 L CNN +F 2 "0402" H 5800 5600 60 0001 C CNN + 1 5800 5600 + 0 1 1 0 +$EndComp +Text Label 5500 5600 0 30 ~ 0 +VFB2.5 +Text Label 5450 5400 0 30 ~ 0 +SW_1.2 +$Comp +L GND #PWR027 U 1 1 4C79C99F P 7500 3650 -F 0 "#PWR01" H 7500 3650 30 0001 C CNN +F 0 "#PWR027" H 7500 3650 30 0001 C CNN F 1 "GND" H 7500 3580 30 0001 C CNN 1 7500 3650 1 0 0 -1 @@ -324,10 +558,10 @@ $EndComp Text Label 7150 2700 0 30 ~ 0 VIN_DC-DC-5.0 $Comp -L GND #PWR02 +L GND #PWR028 U 1 1 4C79C99D P 6200 3650 -F 0 "#PWR02" H 6200 3650 30 0001 C CNN +F 0 "#PWR028" H 6200 3650 30 0001 C CNN F 1 "GND" H 6200 3580 30 0001 C CNN 1 6200 3650 1 0 0 -1 @@ -363,10 +597,10 @@ F 2 "MLP6" H 6750 3050 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR03 +L GND #PWR029 U 1 1 4C79C999 P 7300 3650 -F 0 "#PWR03" H 7300 3650 30 0001 C CNN +F 0 "#PWR029" H 7300 3650 30 0001 C CNN F 1 "GND" H 7300 3580 30 0001 C CNN 1 7300 3650 1 0 0 -1 @@ -374,37 +608,37 @@ $EndComp Text Label 5800 3050 0 60 ~ 12 Iout_5.0 $Comp -L GND #PWR04 +L GND #PWR030 U 1 1 4C79C962 P 8850 3650 -F 0 "#PWR04" H 8850 3650 30 0001 C CNN +F 0 "#PWR030" H 8850 3650 30 0001 C CNN F 1 "GND" H 8850 3580 30 0001 C CNN 1 8850 3650 1 0 0 -1 $EndComp $Comp -L +5V #PWR05 +L +5V #PWR031 U 1 1 4C79C951 P 10300 2700 -F 0 "#PWR05" H 10300 2790 20 0001 C CNN +F 0 "#PWR031" H 10300 2790 20 0001 C CNN F 1 "+5V" H 10300 2790 30 0000 C CNN 1 10300 2700 1 0 0 -1 $EndComp $Comp -L GND #PWR06 +L GND #PWR032 U 1 1 4C79C8B4 P 9500 3650 -F 0 "#PWR06" H 9500 3650 30 0001 C CNN +F 0 "#PWR032" H 9500 3650 30 0001 C CNN F 1 "GND" H 9500 3580 30 0001 C CNN 1 9500 3650 1 0 0 -1 $EndComp $Comp -L GND #PWR07 +L GND #PWR033 U 1 1 4C79C8B3 P 10200 3650 -F 0 "#PWR07" H 10200 3650 30 0001 C CNN +F 0 "#PWR033" H 10200 3650 30 0001 C CNN F 1 "GND" H 10200 3580 30 0001 C CNN 1 10200 3650 1 0 0 -1 @@ -424,7 +658,7 @@ L R R39 U 1 1 4C79C8B1 P 9800 3050 F 0 "R39" V 9880 3050 50 0000 C CNN -F 1 "R" V 9800 3050 50 0000 C CNN +F 1 "1.02M" V 9800 3050 50 0000 C CNN F 2 "0402" H 9800 3050 60 0001 C CNN 1 9800 3050 0 1 1 0 @@ -434,7 +668,7 @@ L R R38 U 1 1 4C79C8B0 P 9500 3350 F 0 "R38" V 9580 3350 50 0000 C CNN -F 1 "R" V 9500 3350 50 0000 C CNN +F 1 "332K" V 9500 3350 50 0000 C CNN F 2 "0402" H 9500 3350 60 0001 C CNN 1 9500 3350 1 0 0 -1 @@ -476,7 +710,7 @@ L R R37 U 1 1 4C79C7C0 P 7900 3050 F 0 "R37" V 7980 3050 50 0000 C CNN -F 1 "R" V 7900 3050 50 0000 C CNN +F 1 "1M" V 7900 3050 50 0000 C CNN F 2 "0402" H 7900 3050 60 0001 C CNN 1 7900 3050 0 1 1 0 @@ -500,10 +734,10 @@ Iout_3.3 Text Label 5900 1100 0 60 ~ 12 Iout_1.2 $Comp -L GND #PWR08 +L GND #PWR034 U 1 1 4C77073C P 7400 1700 -F 0 "#PWR08" H 7400 1700 30 0001 C CNN +F 0 "#PWR034" H 7400 1700 30 0001 C CNN F 1 "GND" H 7400 1630 30 0001 C CNN 1 7400 1700 1 0 0 -1 @@ -539,19 +773,19 @@ F 2 "0402" H 6300 1400 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR09 +L GND #PWR035 U 1 1 4C770711 P 6300 1700 -F 0 "#PWR09" H 6300 1700 30 0001 C CNN +F 0 "#PWR035" H 6300 1700 30 0001 C CNN F 1 "GND" H 6300 1630 30 0001 C CNN 1 6300 1700 1 0 0 -1 $EndComp $Comp -L GND #PWR010 +L GND #PWR036 U 1 1 4C77068E P 1100 1700 -F 0 "#PWR010" H 1100 1700 30 0001 C CNN +F 0 "#PWR036" H 1100 1700 30 0001 C CNN F 1 "GND" H 1100 1630 30 0001 C CNN 1 1100 1700 1 0 0 -1 @@ -567,10 +801,10 @@ F 2 "0402" H 1100 1400 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR011 +L GND #PWR037 U 1 1 4C77064A P 2200 1300 -F 0 "#PWR011" H 2200 1300 30 0001 C CNN +F 0 "#PWR037" H 2200 1300 30 0001 C CNN F 1 "GND" H 2200 1230 30 0001 C CNN 1 2200 1300 1 0 0 -1 @@ -608,19 +842,19 @@ VFB1.2 Text Label 3850 950 0 30 ~ 0 VFB3.3 $Comp -L +3.3V #PWR012 +L +3.3V #PWR038 U 1 1 4C6D30A1 P 4850 750 -F 0 "#PWR012" H 4850 710 30 0001 C CNN +F 0 "#PWR038" H 4850 710 30 0001 C CNN F 1 "+3.3V" H 4850 860 30 0000 C CNN 1 4850 750 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR013 +L +1.2V #PWR039 U 1 1 4C6D3097 P 10150 750 -F 0 "#PWR013" H 10150 890 20 0001 C CNN +F 0 "#PWR039" H 10150 890 20 0001 C CNN F 1 "+1.2V" H 10150 860 30 0000 C CNN 1 10150 750 1 0 0 -1 @@ -656,10 +890,10 @@ F 2 "1206" H 9650 1450 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR014 +L GND #PWR040 U 1 1 4C6D2FD4 P 7700 1700 -F 0 "#PWR014" H 7700 1700 30 0001 C CNN +F 0 "#PWR040" H 7700 1700 30 0001 C CNN F 1 "GND" H 7700 1630 30 0001 C CNN 1 7700 1700 1 0 0 -1 @@ -669,7 +903,7 @@ L R R27 U 1 1 4C6D2FD3 P 9150 1400 F 0 "R27" V 9230 1400 50 0000 C CNN -F 1 "R" V 9150 1400 50 0000 C CNN +F 1 "200K" V 9150 1400 50 0000 C CNN F 2 "0402" H 9150 1400 60 0001 C CNN 1 9150 1400 1 0 0 -1 @@ -679,7 +913,7 @@ L R R28 U 1 1 4C6D2FD2 P 9450 1100 F 0 "R28" V 9530 1100 50 0000 C CNN -F 1 "R" V 9450 1100 50 0000 C CNN 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0 0 -1 @@ -765,7 +999,7 @@ L R R26 U 1 1 4C6D2DDD P 4150 1100 F 0 "R26" V 4230 1100 50 0000 C CNN -F 1 "R" V 4150 1100 50 0000 C CNN +F 1 "900K" V 4150 1100 50 0000 C CNN F 2 "0402" H 4150 1100 60 0001 C CNN 1 4150 1100 0 1 1 0 @@ -775,16 +1009,16 @@ L R R25 U 1 1 4C6D2DBC P 3850 1400 F 0 "R25" V 3930 1400 50 0000 C CNN -F 1 "R" V 3850 1400 50 0000 C CNN +F 1 "200K" V 3850 1400 50 0000 C CNN F 2 "0402" H 3850 1400 60 0001 C CNN 1 3850 1400 1 0 0 -1 $EndComp $Comp -L GND #PWR019 +L GND #PWR045 U 1 1 4C6D2CCE P 2400 1700 -F 0 "#PWR019" H 2400 1700 30 0001 C CNN +F 0 "#PWR045" H 2400 1700 30 0001 C CNN F 1 "GND" H 2400 1630 30 0001 C CNN 1 2400 1700 1 0 0 -1 @@ -820,19 +1054,19 @@ F 2 "0805" H 2400 1400 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR020 +L GND #PWR046 U 1 1 4C6D2C02 P 8500 1700 -F 0 "#PWR020" H 8500 1700 30 0001 C CNN +F 0 "#PWR046" H 8500 1700 30 0001 C CNN F 1 "GND" H 8500 1630 30 0001 C CNN 1 8500 1700 1 0 0 -1 $EndComp $Comp -L GND #PWR021 +L GND #PWR047 U 1 1 4C6D2BFC P 3200 1700 -F 0 "#PWR021" H 3200 1700 30 0001 C CNN +F 0 "#PWR047" H 3200 1700 30 0001 C CNN F 1 "GND" H 3200 1630 30 0001 C CNN 1 3200 1700 1 0 0 -1 @@ -858,29 +1092,29 @@ F 2 "SOT23-5" H 3100 1050 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR022 +L GND #PWR048 U 1 1 4C6C9F96 -P 3000 6450 -F 0 "#PWR022" H 3000 6450 30 0001 C CNN -F 1 "GND" H 3000 6380 30 0001 C CNN - 1 3000 6450 +P 4500 6700 +F 0 "#PWR048" H 4500 6700 30 0001 C CNN +F 1 "GND" H 4500 6630 30 0001 C CNN + 1 4500 6700 1 0 0 -1 $EndComp $Comp L A7130 U10 U 1 1 4C6C9DB9 -P 2750 5200 -F 0 "U10" H 2600 4450 60 0000 C CNN -F 1 "A7130" H 2900 5050 60 0000 C CNN -F 2 "DFN10" H 2750 5200 60 0001 C CNN - 1 2750 5200 +P 4250 5450 +F 0 "U10" H 4100 4700 60 0000 C CNN +F 1 "A7130" H 4400 5300 60 0000 C CNN +F 2 "DFN10" H 4250 5450 60 0001 C CNN + 1 4250 5450 1 0 0 -1 $EndComp $Comp -L GND #PWR023 +L GND #PWR049 U 1 1 4C69F7A5 P 8050 4950 -F 0 "#PWR023" H 8050 4950 30 0001 C CNN +F 0 "#PWR049" H 8050 4950 30 0001 C CNN F 1 "GND" H 8050 4880 30 0001 C CNN 1 8050 4950 1 0 0 -1 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 7336d9e..59f061e 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 30 Aug 2010 10:27:20 AM COT +EESchema Schematic File Version 2 date Mon 30 Aug 2010 07:47:12 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -51,7 +51,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 5 9 Title "" -Date "30 aug 2010" +Date "31 aug 2010" Rev "" Comp "" Comment1 "" @@ -320,91 +320,91 @@ F 2 "MLF16" H 2000 2750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR032 +L +3.3V #PWR058 U 1 1 4C695F50 P 2700 4600 -F 0 "#PWR032" H 2700 4560 30 0001 C CNN +F 0 "#PWR058" H 2700 4560 30 0001 C CNN F 1 "+3.3V" H 2700 4710 30 0000 C CNN 1 2700 4600 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR033 +L +3.3V #PWR059 U 1 1 4C695F4B P 2550 6100 -F 0 "#PWR033" H 2550 6060 30 0001 C CNN +F 0 "#PWR059" H 2550 6060 30 0001 C CNN F 1 "+3.3V" H 2550 6210 30 0000 C CNN 1 2550 6100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR034 +L +3.3V #PWR060 U 1 1 4C695F43 P 2650 1100 -F 0 "#PWR034" H 2650 1060 30 0001 C CNN +F 0 "#PWR060" H 2650 1060 30 0001 C CNN F 1 "+3.3V" H 2650 1210 30 0000 C CNN 1 2650 1100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR035 +L +3.3V #PWR061 U 1 1 4C695F3B P 2500 2400 -F 0 "#PWR035" H 2500 2360 30 0001 C CNN +F 0 "#PWR061" H 2500 2360 30 0001 C CNN F 1 "+3.3V" H 2500 2510 30 0000 C CNN 1 2500 2400 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR036 +L +2.5V #PWR062 U 1 1 4C695DCD P 3200 4550 -F 0 "#PWR036" H 3200 4500 20 0001 C CNN +F 0 "#PWR062" H 3200 4500 20 0001 C CNN F 1 "+2.5V" H 3200 4650 30 0000 C CNN 1 3200 4550 1 0 0 -1 $EndComp $Comp -L GND #PWR037 +L GND #PWR063 U 1 1 4C695F0A P 3200 5550 -F 0 "#PWR037" H 3200 5550 30 0001 C CNN +F 0 "#PWR063" H 3200 5550 30 0001 C CNN F 1 "GND" H 3200 5480 30 0001 C CNN 1 3200 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR038 +L GND #PWR064 U 1 1 4C695F09 P 2650 5550 -F 0 "#PWR038" H 2650 5550 30 0001 C CNN +F 0 "#PWR064" H 2650 5550 30 0001 C CNN F 1 "GND" H 2650 5480 30 0001 C CNN 1 2650 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR039 +L GND #PWR065 U 1 1 4C695DFE P 3150 1850 -F 0 "#PWR039" H 3150 1850 30 0001 C CNN +F 0 "#PWR065" H 3150 1850 30 0001 C CNN F 1 "GND" H 3150 1780 30 0001 C CNN 1 3150 1850 1 0 0 -1 $EndComp $Comp -L GND #PWR040 +L GND #PWR066 U 1 1 4C695DF8 P 2600 1850 -F 0 "#PWR040" H 2600 1850 30 0001 C CNN +F 0 "#PWR066" H 2600 1850 30 0001 C CNN F 1 "GND" H 2600 1780 30 0001 C CNN 1 2600 1850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR041 +L +2.5V #PWR067 U 1 1 4C695DA7 P 3150 1100 -F 0 "#PWR041" H 3150 1050 20 0001 C CNN +F 0 "#PWR067" H 3150 1050 20 0001 C CNN F 1 "+2.5V" H 3150 1200 30 0000 C CNN 1 3150 1100 1 0 0 -1 @@ -485,28 +485,28 @@ USBD_VP Text HLabel 1650 6750 0 40 BiDi ~ 0 USBD_VM $Comp -L GND #PWR042 +L GND #PWR068 U 1 1 4C6552B5 P 4900 7400 -F 0 "#PWR042" H 4900 7400 30 0001 C CNN +F 0 "#PWR068" H 4900 7400 30 0001 C CNN F 1 "GND" H 4900 7330 30 0001 C CNN 1 4900 7400 1 0 0 -1 $EndComp $Comp -L GND #PWR043 +L GND #PWR069 U 1 1 4C6552B4 P 2200 7500 -F 0 "#PWR043" H 2200 7500 30 0001 C CNN +F 0 "#PWR069" H 2200 7500 30 0001 C CNN F 1 "GND" H 2200 7430 30 0001 C CNN 1 2200 7500 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR044 +L +2.5V #PWR070 U 1 1 4C6552B2 P 1600 6150 -F 0 "#PWR044" H 1600 6100 20 0001 C CNN +F 0 "#PWR070" H 1600 6100 20 0001 C CNN F 1 "+2.5V" H 1600 6250 30 0000 C CNN 1 1600 6150 1 0 0 -1 @@ -522,28 +522,28 @@ F 2 "0603" H 4050 7000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR045 +L GND #PWR071 U 1 1 4C6552AE P 4050 7350 -F 0 "#PWR045" H 4050 7350 30 0001 C CNN +F 0 "#PWR071" H 4050 7350 30 0001 C CNN F 1 "GND" H 4050 7280 30 0001 C CNN 1 4050 7350 1 0 0 -1 $EndComp $Comp -L GND #PWR046 +L GND #PWR072 U 1 1 4C63F2B5 P 4550 3700 -F 0 "#PWR046" H 4550 3700 30 0001 C CNN +F 0 "#PWR072" H 4550 3700 30 0001 C CNN F 1 "GND" H 4550 3630 30 0001 C CNN 1 4550 3700 1 0 0 -1 $EndComp $Comp -L +5V #PWR047 +L +5V #PWR073 U 1 1 4C63F295 P 4350 1350 -F 0 "#PWR047" H 4350 1440 20 0001 C CNN +F 0 "#PWR073" H 4350 1440 20 0001 C CNN F 1 "+5V" H 4350 1440 30 0000 C CNN 1 4350 1350 1 0 0 -1 @@ -569,28 +569,28 @@ F 2 "0603" H 4550 3350 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR048 +L +2.5V #PWR074 U 1 1 4C63EC16 P 1550 2450 -F 0 "#PWR048" H 1550 2400 20 0001 C CNN +F 0 "#PWR074" H 1550 2400 20 0001 C CNN F 1 "+2.5V" H 1550 2550 30 0000 C CNN 1 1550 2450 1 0 0 -1 $EndComp $Comp -L GND #PWR049 +L GND #PWR075 U 1 1 4C63EA1B P 2150 3800 -F 0 "#PWR049" H 2150 3800 30 0001 C CNN +F 0 "#PWR075" H 2150 3800 30 0001 C CNN F 1 "GND" H 2150 3730 30 0001 C CNN 1 2150 3800 1 0 0 -1 $EndComp $Comp -L GND #PWR050 +L GND #PWR076 U 1 1 4C63E9FA P 5600 3750 -F 0 "#PWR050" H 5600 3750 30 0001 C CNN +F 0 "#PWR076" H 5600 3750 30 0001 C CNN F 1 "GND" H 5600 3680 30 0001 C CNN 1 5600 3750 1 0 0 -1 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index cd2b2ac..a559f0b 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 30 Aug 2010 10:27:20 AM COT +EESchema Schematic File Version 2 date Mon 30 Aug 2010 07:47:12 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -51,7 +51,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 7 9 Title "" -Date "30 aug 2010" +Date "31 aug 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index bac2f0d..ef4275c 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Mon 30 Aug 2010 10:27:20 AM COT +EESchema-LIBRARY Version 2.3 Date: Mon 30 Aug 2010 07:47:12 PM COT # # +1.2V # @@ -219,7 +219,7 @@ DEF ~GND #PWR 0 0 Y Y 1 F P F0 "#PWR" 0 0 30 H I C CNN F1 "GND" 0 -70 30 H I C CNN DRAW -P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +P 4 0 1 4 -50 0 0 -50 50 0 -50 0 N X GND 1 0 0 0 U 30 30 1 1 W N ENDDRAW ENDDEF @@ -500,10 +500,9 @@ $FPLIST R? SM0603 SM0805 - R?-* $ENDFPLIST DRAW -S -40 150 40 -150 0 1 12 N +S -40 150 40 -150 0 1 8 N X ~ 1 0 250 100 D 60 60 1 1 P X ~ 2 0 -250 100 U 60 60 1 1 P ENDDRAW diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index e3ccc08..961e179 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,26 +1,26 @@ -PCBNEW-BOARD Version 1 date Mon 30 Aug 2010 10:28:26 AM COT +PCBNEW-BOARD Version 1 date Mon 30 Aug 2010 07:47:02 PM COT -# Created by Pcbnew(2010-08-24 BZR 2457)-unstable +# Created by Pcbnew(2010-08-29 BZR 2460)-unstable $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 13FF801F -Links 882 -NoConn 222 -Di 45499 9696 67399 49179 +Links 768 +NoConn 111 +Di 45499 9696 72481 49179 Ndraw 6 Ntrack 4100 Nzone 0 BoardThickness 630 -Nmodule 186 -Nnets 137 +Nmodule 196 +Nnets 279 $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "30 aug 2010" +Date "31 aug 2010" Rev "" Comp "" Comment1 "" @@ -97,527 +97,1095 @@ Na 5 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DBG_PRG/FPGA_TCK" +Na 6 "/DBG_PRG20" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DBG_PRG/FPGA_TDI" +Na 7 "/DBG_PRG21" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DBG_PRG/FPGA_TDO" +Na 8 "/DBG_PRG22" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DBG_PRG/FPGA_TMS" +Na 9 "/DBG_PRG23" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_A0" +Na 10 "/DDR_Ban114" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_A12" +Na 11 "/DDR_Ban116" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_A2" +Na 12 "/DDR_Ban117" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_A4" +Na 13 "/DDR_Ban125" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_A5" +Na 14 "/DDR_Ban130" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_A6" +Na 15 "/DDR_Ban131" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_A8" +Na 16 "/DDR_Ban138" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_BA1" +Na 17 "/DDR_Ban156" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_CLK#" +Na 18 "/DDR_Ban157" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_DQ11" +Na 19 "/DDR_Ban163" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M0_DQ12" +Na 20 "/DDR_Ban165" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M0_DQ15" +Na 21 "/DDR_Ban27" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M0_DQ2" +Na 22 "/DDR_Ban32" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M0_RAS#" +Na 23 "/DDR_Ban34" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M0_UDM" +Na 24 "/DDR_Ban36" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M0_VREF" +Na 25 "/DDR_Ban40" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_A11" +Na 26 "/DDR_Ban44" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_A12" +Na 27 "/DDR_Ban5" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_A5" +Na 28 "/DDR_Ban56" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_A9" +Na 29 "/DDR_Ban57" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_CAS#" +Na 30 "/DDR_Ban6" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_CLK#" +Na 31 "/DDR_Ban62" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_CS#" +Na 32 "/DDR_Ban65" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_DQ0" +Na 33 "/DDR_Ban70" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_DQ13" +Na 34 "/DDR_Ban88" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_DQ2" +Na 35 "/DDR_Ban95" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/DDR_Banks/M1_DQ4" +Na 36 "/DDR_Banks/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/DDR_Banks/M1_DQ5" +Na 37 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M1_DQ9" +Na 38 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/DDR_Banks/M1_VREF" +Na 39 "/DDR_Banks/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Ethernet_Phy/ETH_A1.8V" +Na 40 "/DDR_Banks/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_A3.3V" +Na 41 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_CRS" +Na 42 "/DDR_Banks/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_INT" +Na 43 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_LED0" +Na 44 "/DDR_Banks/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_LED1" +Na 45 "/Etherne1" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_MDC" +Na 46 "/Etherne16" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_PLL1.8V" +Na 47 "/Etherne17" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_RXD1" +Na 48 "/Etherne18" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_RXD2" +Na 49 "/Etherne180" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/ETH_RXD3" +Na 50 "/Etherne181" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Ethernet_Phy/ETH_RXDV" +Na 51 "/Etherne183" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/Ethernet_Phy/ETH_TXC" +Na 52 "/Etherne185" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/Ethernet_Phy/ETH_TXD1" +Na 53 "/Etherne19" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/Ethernet_Phy/ETH_TXER" +Na 54 "/Etherne196" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/Ethernet_Phy/MAG_RX+" +Na 55 "/Etherne197" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/Ethernet_Phy/MAG_RX-" +Na 56 "/Etherne2" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/Ethernet_Phy/MAG_SHIELD" +Na 57 "/Etherne205" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/Ethernet_Phy/MAG_TX+" +Na 58 "/Etherne212" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/Ethernet_Phy/MAG_TX-" +Na 59 "/Etherne25" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK" +Na 60 "/Etherne26" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" +Na 61 "/Etherne3" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" +Na 62 "/Etherne4" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" +Na 63 "/FPGA,_P14" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" +Na 64 "/FPGA,_P15" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" +Na 65 "/FPGA,_P182" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER" +Na 66 "/FPGA,_P184" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" +Na 67 "/FPGA,_P186" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" +Na 68 "/FPGA,_P187" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" +Na 69 "/FPGA,_P188" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" +Na 70 "/FPGA,_P189" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" +Na 71 "/FPGA,_P190" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" +Na 72 "/FPGA,_P191" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" +Na 73 "/FPGA,_P192" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" +Na 74 "/FPGA,_P193" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" +Na 75 "/FPGA,_P194" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" +Na 76 "/FPGA,_P195" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO" +Na 77 "/FPGA,_P198" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0" +Na 78 "/FPGA,_P199" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1" +Na 79 "/FPGA,_P202" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" +Na 80 "/FPGA,_P203" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" +Na 81 "/FPGA,_P204" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA,_Port0,_Port2,_PROG_IF/SD_CMD" +Na 82 "/FPGA,_P206" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" +Na 83 "/FPGA,_P207" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Port_1,_Port_3_" +Na 84 "/FPGA,_P208" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/Non_volatile_memories/NF_ALE" +Na 85 "/FPGA,_P213" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/Non_volatile_memories/NF_CLE" +Na 86 "/FPGA,_P214" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/Non_volatile_memories/NF_CS1_N" +Na 87 "/FPGA,_P215" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/Non_volatile_memories/NF_D0" +Na 88 "/FPGA,_P216" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/Non_volatile_memories/NF_D1" +Na 89 "/FPGA,_P217" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/Non_volatile_memories/NF_D2" +Na 90 "/FPGA,_P221" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/Non_volatile_memories/NF_D7" +Na 91 "/FPGA,_P222" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/Non_volatile_memories/NF_RNB" +Na 92 "/FPGA,_P223" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/Non_volatile_memories/NF_WE_N" +Na 93 "/FPGA,_P24" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/Non_volatile_memories/SD_CLK" +Na 94 "/FPGA_Po100" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/Non_volatile_memories/SD_DAT0" +Na 95 "/FPGA_Po101" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/Non_volatile_memories/SD_DAT1" +Na 96 "/FPGA_Po102" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/Non_volatile_memories/SD_DAT3" +Na 97 "/FPGA_Po103" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/PSU/Iout_1.2" +Na 98 "/FPGA_Po104" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/PSU/Iout_3.3" +Na 99 "/FPGA_Po105" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/PSU/Iout_5.0" +Na 100 "/FPGA_Po106" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/PSU/SW_1.2" +Na 101 "/FPGA_Po107" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/PSU/SW_3.3" +Na 102 "/FPGA_Po108" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/PSU/VFB1.2" +Na 103 "/FPGA_Po109" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/PSU/VFB3.3" +Na 104 "/FPGA_Po110" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/PSU/VIN_DC-DC-1.2" +Na 105 "/FPGA_Po111" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/PSU/VIN_DC-DC-3.3" +Na 106 "/FPGA_Po112" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/PSU/VIN_DC-DC-5.0" +Na 107 "/FPGA_Po113" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/USB/USBA_D+" +Na 108 "/FPGA_Po115" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/USB/USBA_D-" +Na 109 "/FPGA_Po118" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/USB/USBA_OE_N" +Na 110 "/FPGA_Po119" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/USB/USBA_SPD" +Na 111 "/FPGA_Po120" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/USB/USBA_VM" +Na 112 "/FPGA_Po121" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/USB/USBD_D+" +Na 113 "/FPGA_Po122" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/USB/USBD_D-" +Na 114 "/FPGA_Po123" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/USB/USBD_OE_N" +Na 115 "/FPGA_Po124" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/USB/USBD_SPD" +Na 116 "/FPGA_Po126" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/USB/USBD_VP" +Na 117 "/FPGA_Po127" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "GND" +Na 118 "/FPGA_Po128" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "N-000117" +Na 119 "/FPGA_Po129" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "N-000118" +Na 120 "/FPGA_Po132" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "N-000123" +Na 121 "/FPGA_Po133" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "N-000130" +Na 122 "/FPGA_Po134" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "N-000131" +Na 123 "/FPGA_Po135" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "N-000132" +Na 124 "/FPGA_Po136" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "N-000134" +Na 125 "/FPGA_Po137" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "N-000135" +Na 126 "/FPGA_Po139" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "N-000136" +Na 127 "/FPGA_Po140" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "N-000137" +Na 128 "/FPGA_Po141" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "N-000142" +Na 129 "/FPGA_Po142" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "N-000143" +Na 130 "/FPGA_Po143" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "N-000145" +Na 131 "/FPGA_Po144" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "N-000148" +Na 132 "/FPGA_Po145" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "N-000153" +Na 133 "/FPGA_Po146" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "N-000357" +Na 134 "/FPGA_Po147" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "N-000359" +Na 135 "/FPGA_Po148" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "VCCO2" +Na 136 "/FPGA_Po149" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 137 "/FPGA_Po150" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 138 "/FPGA_Po151" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 139 "/FPGA_Po152" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 140 "/FPGA_Po153" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 141 "/FPGA_Po154" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 142 "/FPGA_Po155" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 143 "/FPGA_Po158" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 144 "/FPGA_Po159" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 145 "/FPGA_Po160" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 146 "/FPGA_Po161" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 147 "/FPGA_Po162" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 148 "/FPGA_Po164" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 149 "/FPGA_Po166" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 150 "/FPGA_Po167" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 151 "/FPGA_Po168" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 152 "/FPGA_Po169" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 153 "/FPGA_Po170" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 154 "/FPGA_Po171" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 155 "/FPGA_Po172" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 156 "/FPGA_Po173" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 157 "/FPGA_Po174" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 158 "/FPGA_Po175" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 159 "/FPGA_Po176" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 160 "/FPGA_Po177" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 161 "/FPGA_Po178" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 162 "/FPGA_Po179" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 163 "/FPGA_Po200" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 164 "/FPGA_Po201" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 165 "/FPGA_Po219" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 166 "/FPGA_Po220" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 167 "/FPGA_Po28" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 168 "/FPGA_Po29" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 169 "/FPGA_Po30" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 170 "/FPGA_Po31" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 171 "/FPGA_Po33" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 172 "/FPGA_Po35" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 173 "/FPGA_Po37" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 174 "/FPGA_Po38" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 175 "/FPGA_Po39" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 176 "/FPGA_Po41" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 177 "/FPGA_Po42" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 178 "/FPGA_Po43" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 179 "/FPGA_Po45" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 180 "/FPGA_Po46" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 181 "/FPGA_Po47" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 182 "/FPGA_Po48" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 183 "/FPGA_Po49" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 184 "/FPGA_Po50" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 185 "/FPGA_Po51" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 186 "/FPGA_Po52" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 187 "/FPGA_Po53" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 188 "/FPGA_Po54" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 189 "/FPGA_Po55" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 190 "/FPGA_Po58" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 191 "/FPGA_Po59" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 192 "/FPGA_Po60" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 193 "/FPGA_Po61" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 194 "/FPGA_Po63" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 195 "/FPGA_Po64" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 196 "/FPGA_Po66" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 197 "/FPGA_Po67" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 198 "/FPGA_Po68" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 199 "/FPGA_Po69" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 200 "/FPGA_Po71" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 201 "/FPGA_Po72" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 202 "/FPGA_Po73" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 203 "/FPGA_Po74" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 204 "/FPGA_Po75" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 205 "/FPGA_Po76" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 206 "/FPGA_Po77" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 207 "/FPGA_Po78" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 208 "/FPGA_Po79" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 209 "/FPGA_Po80" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 210 "/FPGA_Po81" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 211 "/FPGA_Po82" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 212 "/FPGA_Po83" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 213 "/FPGA_Po84" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 214 "/FPGA_Po85" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 215 "/FPGA_Po86" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 216 "/FPGA_Po87" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 217 "/FPGA_Po89" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 218 "/FPGA_Po90" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 219 "/FPGA_Po91" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 220 "/FPGA_Po92" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 221 "/FPGA_Po93" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 222 "/FPGA_Po94" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 223 "/FPGA_Po96" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 224 "/FPGA_Po97" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 225 "/FPGA_Po98" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 226 "/FPGA_Po99" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 227 "/Non_vol10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 228 "/Non_vol11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 229 "/Non_vol12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 230 "/Non_vol13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 231 "/Non_vol209" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 232 "/Non_vol210" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 233 "/Non_vol211" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 234 "/Non_vol218" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 235 "/PSU/Iout_1.2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 236 "/PSU/Iout_3.3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 237 "/PSU/Iout_5.0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 238 "/PSU/SW_1.2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 239 "/PSU/SW_3.3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 240 "/PSU/VFB1.2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 241 "/PSU/VFB2.5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 242 "/PSU/VFB3.3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 243 "/PSU/VIN7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 244 "/PSU/VIN8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 245 "/PSU/VIN9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 246 "/USB/USBA_D+" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 247 "/USB/USBA_D-" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 248 "/USB/USBA_OE_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 249 "/USB/USBA_RCV" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 250 "/USB/USBA_VP" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 251 "/USB/USBD_D+" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 252 "/USB/USBD_D-" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 253 "/USB/USBD_OE_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 254 "/USB/USBD_RCV" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 255 "/USB/USBD_VP" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 256 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 257 "N-000117" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 258 "N-000118" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 259 "N-000123" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 260 "N-000130" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 261 "N-000131" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 262 "N-000132" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 263 "N-000134" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 264 "N-000135" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 265 "N-000136" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 266 "N-000137" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 267 "N-000143" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 268 "N-000144" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 269 "N-000147" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 270 "N-000148" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 271 "N-000150" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 272 "N-000151" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 273 "N-000156" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 274 "N-000157" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 275 "N-000160" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 276 "N-000354" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 277 "N-000356" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 278 "VCCO2" St ~ $EndEQUIPOT $NCLASS @@ -630,111 +1198,249 @@ ViaDrill 79 uViaDia 197 uViaDrill 79 AddNet "" -AddNet "/DBG_PRG/FPGA_TCK" -AddNet "/DBG_PRG/FPGA_TDI" -AddNet "/DBG_PRG/FPGA_TDO" -AddNet "/DBG_PRG/FPGA_TMS" -AddNet "/DDR_Banks/M0_A0" -AddNet "/DDR_Banks/M0_A12" -AddNet "/DDR_Banks/M0_A2" +AddNet "/DBG_PRG20" +AddNet "/DBG_PRG21" +AddNet "/DBG_PRG22" +AddNet "/DBG_PRG23" +AddNet "/DDR_Ban114" +AddNet "/DDR_Ban116" +AddNet "/DDR_Ban117" +AddNet "/DDR_Ban125" +AddNet "/DDR_Ban130" +AddNet "/DDR_Ban131" +AddNet "/DDR_Ban138" +AddNet "/DDR_Ban156" +AddNet "/DDR_Ban157" +AddNet "/DDR_Ban163" +AddNet "/DDR_Ban165" +AddNet "/DDR_Ban27" +AddNet "/DDR_Ban32" +AddNet "/DDR_Ban34" +AddNet "/DDR_Ban36" +AddNet "/DDR_Ban40" +AddNet "/DDR_Ban44" +AddNet "/DDR_Ban5" +AddNet "/DDR_Ban56" +AddNet "/DDR_Ban57" +AddNet "/DDR_Ban6" +AddNet "/DDR_Ban62" +AddNet "/DDR_Ban65" +AddNet "/DDR_Ban70" +AddNet "/DDR_Ban88" +AddNet "/DDR_Ban95" AddNet "/DDR_Banks/M0_A4" -AddNet "/DDR_Banks/M0_A5" -AddNet "/DDR_Banks/M0_A6" -AddNet "/DDR_Banks/M0_A8" -AddNet "/DDR_Banks/M0_BA1" -AddNet "/DDR_Banks/M0_CLK#" -AddNet "/DDR_Banks/M0_DQ11" -AddNet "/DDR_Banks/M0_DQ12" -AddNet "/DDR_Banks/M0_DQ15" -AddNet "/DDR_Banks/M0_DQ2" -AddNet "/DDR_Banks/M0_RAS#" -AddNet "/DDR_Banks/M0_UDM" -AddNet "/DDR_Banks/M0_VREF" -AddNet "/DDR_Banks/M1_A11" -AddNet "/DDR_Banks/M1_A12" +AddNet "/DDR_Banks/M0_A7" +AddNet "/DDR_Banks/M1_A0" +AddNet "/DDR_Banks/M1_A1" +AddNet "/DDR_Banks/M1_A3" AddNet "/DDR_Banks/M1_A5" +AddNet "/DDR_Banks/M1_A7" +AddNet "/DDR_Banks/M1_A8" AddNet "/DDR_Banks/M1_A9" -AddNet "/DDR_Banks/M1_CAS#" -AddNet "/DDR_Banks/M1_CLK#" -AddNet "/DDR_Banks/M1_CS#" -AddNet "/DDR_Banks/M1_DQ0" -AddNet "/DDR_Banks/M1_DQ13" -AddNet "/DDR_Banks/M1_DQ2" -AddNet "/DDR_Banks/M1_DQ4" -AddNet "/DDR_Banks/M1_DQ5" -AddNet "/DDR_Banks/M1_DQ9" -AddNet "/DDR_Banks/M1_VREF" -AddNet "/Ethernet_Phy/ETH_A1.8V" -AddNet "/Ethernet_Phy/ETH_A3.3V" -AddNet "/Ethernet_Phy/ETH_CRS" -AddNet "/Ethernet_Phy/ETH_INT" -AddNet "/Ethernet_Phy/ETH_LED0" -AddNet "/Ethernet_Phy/ETH_LED1" -AddNet "/Ethernet_Phy/ETH_MDC" -AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/ETH_RXD1" -AddNet "/Ethernet_Phy/ETH_RXD2" -AddNet "/Ethernet_Phy/ETH_RXD3" -AddNet "/Ethernet_Phy/ETH_RXDV" -AddNet "/Ethernet_Phy/ETH_TXC" -AddNet "/Ethernet_Phy/ETH_TXD1" -AddNet "/Ethernet_Phy/ETH_TXER" -AddNet "/Ethernet_Phy/MAG_RX+" -AddNet "/Ethernet_Phy/MAG_RX-" -AddNet "/Ethernet_Phy/MAG_SHIELD" -AddNet "/Ethernet_Phy/MAG_TX+" -AddNet "/Ethernet_Phy/MAG_TX-" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/SD_CMD" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" -AddNet "/FPGA_Port_1,_Port_3_" -AddNet "/Non_volatile_memories/NF_ALE" -AddNet "/Non_volatile_memories/NF_CLE" -AddNet "/Non_volatile_memories/NF_CS1_N" -AddNet "/Non_volatile_memories/NF_D0" -AddNet "/Non_volatile_memories/NF_D1" -AddNet "/Non_volatile_memories/NF_D2" -AddNet "/Non_volatile_memories/NF_D7" -AddNet "/Non_volatile_memories/NF_RNB" -AddNet "/Non_volatile_memories/NF_WE_N" -AddNet "/Non_volatile_memories/SD_CLK" -AddNet "/Non_volatile_memories/SD_DAT0" -AddNet "/Non_volatile_memories/SD_DAT1" -AddNet "/Non_volatile_memories/SD_DAT3" +AddNet "/Etherne1" +AddNet "/Etherne16" +AddNet "/Etherne17" +AddNet "/Etherne18" +AddNet "/Etherne180" +AddNet "/Etherne181" +AddNet "/Etherne183" +AddNet "/Etherne185" +AddNet "/Etherne19" +AddNet "/Etherne196" +AddNet "/Etherne197" +AddNet "/Etherne2" +AddNet "/Etherne205" +AddNet "/Etherne212" +AddNet "/Etherne25" +AddNet "/Etherne26" +AddNet "/Etherne3" +AddNet "/Etherne4" +AddNet "/FPGA,_P14" +AddNet "/FPGA,_P15" +AddNet "/FPGA,_P182" +AddNet "/FPGA,_P184" +AddNet "/FPGA,_P186" +AddNet "/FPGA,_P187" +AddNet "/FPGA,_P188" +AddNet "/FPGA,_P189" +AddNet "/FPGA,_P190" +AddNet "/FPGA,_P191" +AddNet "/FPGA,_P192" +AddNet "/FPGA,_P193" +AddNet "/FPGA,_P194" +AddNet "/FPGA,_P195" +AddNet "/FPGA,_P198" +AddNet "/FPGA,_P199" +AddNet "/FPGA,_P202" +AddNet "/FPGA,_P203" +AddNet "/FPGA,_P204" +AddNet "/FPGA,_P206" +AddNet "/FPGA,_P207" +AddNet "/FPGA,_P208" +AddNet "/FPGA,_P213" +AddNet "/FPGA,_P214" +AddNet "/FPGA,_P215" +AddNet "/FPGA,_P216" +AddNet "/FPGA,_P217" +AddNet "/FPGA,_P221" +AddNet "/FPGA,_P222" +AddNet "/FPGA,_P223" +AddNet "/FPGA,_P24" +AddNet "/FPGA_Po100" +AddNet "/FPGA_Po101" +AddNet "/FPGA_Po102" +AddNet "/FPGA_Po103" +AddNet "/FPGA_Po104" +AddNet "/FPGA_Po105" +AddNet "/FPGA_Po106" +AddNet "/FPGA_Po107" +AddNet "/FPGA_Po108" +AddNet "/FPGA_Po109" +AddNet "/FPGA_Po110" +AddNet "/FPGA_Po111" +AddNet "/FPGA_Po112" +AddNet "/FPGA_Po113" +AddNet "/FPGA_Po115" +AddNet "/FPGA_Po118" +AddNet "/FPGA_Po119" +AddNet "/FPGA_Po120" +AddNet "/FPGA_Po121" +AddNet "/FPGA_Po122" +AddNet "/FPGA_Po123" +AddNet "/FPGA_Po124" +AddNet "/FPGA_Po126" +AddNet "/FPGA_Po127" +AddNet "/FPGA_Po128" +AddNet "/FPGA_Po129" +AddNet "/FPGA_Po132" +AddNet "/FPGA_Po133" +AddNet "/FPGA_Po134" +AddNet "/FPGA_Po135" +AddNet "/FPGA_Po136" +AddNet "/FPGA_Po137" +AddNet "/FPGA_Po139" +AddNet "/FPGA_Po140" +AddNet "/FPGA_Po141" +AddNet "/FPGA_Po142" +AddNet "/FPGA_Po143" +AddNet "/FPGA_Po144" +AddNet "/FPGA_Po145" +AddNet "/FPGA_Po146" +AddNet "/FPGA_Po147" +AddNet "/FPGA_Po148" +AddNet "/FPGA_Po149" +AddNet "/FPGA_Po150" +AddNet "/FPGA_Po151" +AddNet "/FPGA_Po152" +AddNet "/FPGA_Po153" +AddNet "/FPGA_Po154" +AddNet "/FPGA_Po155" +AddNet "/FPGA_Po158" +AddNet "/FPGA_Po159" +AddNet "/FPGA_Po160" +AddNet "/FPGA_Po161" +AddNet "/FPGA_Po162" +AddNet "/FPGA_Po164" +AddNet "/FPGA_Po166" +AddNet "/FPGA_Po167" +AddNet "/FPGA_Po168" +AddNet "/FPGA_Po169" +AddNet "/FPGA_Po170" +AddNet "/FPGA_Po171" +AddNet "/FPGA_Po172" +AddNet "/FPGA_Po173" +AddNet "/FPGA_Po174" +AddNet "/FPGA_Po175" +AddNet "/FPGA_Po176" +AddNet "/FPGA_Po177" +AddNet "/FPGA_Po178" +AddNet "/FPGA_Po179" +AddNet "/FPGA_Po200" +AddNet "/FPGA_Po201" +AddNet "/FPGA_Po219" +AddNet "/FPGA_Po220" +AddNet "/FPGA_Po28" +AddNet "/FPGA_Po29" +AddNet "/FPGA_Po30" +AddNet "/FPGA_Po31" +AddNet "/FPGA_Po33" +AddNet "/FPGA_Po35" +AddNet "/FPGA_Po37" +AddNet "/FPGA_Po38" +AddNet "/FPGA_Po39" +AddNet "/FPGA_Po41" +AddNet "/FPGA_Po42" +AddNet "/FPGA_Po43" +AddNet "/FPGA_Po45" +AddNet "/FPGA_Po46" +AddNet "/FPGA_Po47" +AddNet "/FPGA_Po48" +AddNet "/FPGA_Po49" +AddNet "/FPGA_Po50" +AddNet "/FPGA_Po51" +AddNet "/FPGA_Po52" +AddNet "/FPGA_Po53" +AddNet "/FPGA_Po54" +AddNet "/FPGA_Po55" +AddNet "/FPGA_Po58" +AddNet "/FPGA_Po59" +AddNet "/FPGA_Po60" +AddNet "/FPGA_Po61" +AddNet "/FPGA_Po63" +AddNet "/FPGA_Po64" +AddNet "/FPGA_Po66" +AddNet "/FPGA_Po67" +AddNet "/FPGA_Po68" +AddNet "/FPGA_Po69" +AddNet "/FPGA_Po71" +AddNet "/FPGA_Po72" +AddNet "/FPGA_Po73" +AddNet "/FPGA_Po74" +AddNet "/FPGA_Po75" +AddNet "/FPGA_Po76" +AddNet "/FPGA_Po77" +AddNet "/FPGA_Po78" +AddNet "/FPGA_Po79" +AddNet "/FPGA_Po80" +AddNet "/FPGA_Po81" +AddNet "/FPGA_Po82" +AddNet "/FPGA_Po83" +AddNet "/FPGA_Po84" +AddNet "/FPGA_Po85" +AddNet "/FPGA_Po86" +AddNet "/FPGA_Po87" +AddNet "/FPGA_Po89" +AddNet "/FPGA_Po90" +AddNet "/FPGA_Po91" +AddNet "/FPGA_Po92" +AddNet "/FPGA_Po93" +AddNet "/FPGA_Po94" +AddNet "/FPGA_Po96" +AddNet "/FPGA_Po97" +AddNet "/FPGA_Po98" +AddNet "/FPGA_Po99" +AddNet "/Non_vol10" +AddNet "/Non_vol11" +AddNet "/Non_vol12" +AddNet "/Non_vol13" +AddNet "/Non_vol209" +AddNet "/Non_vol210" +AddNet "/Non_vol211" +AddNet "/Non_vol218" AddNet "/PSU/Iout_1.2" AddNet "/PSU/Iout_3.3" AddNet "/PSU/Iout_5.0" AddNet "/PSU/VFB1.2" +AddNet "/PSU/VFB2.5" AddNet "/PSU/VFB3.3" -AddNet "/PSU/VIN_DC-DC-1.2" -AddNet "/PSU/VIN_DC-DC-3.3" -AddNet "/PSU/VIN_DC-DC-5.0" +AddNet "/PSU/VIN7" +AddNet "/PSU/VIN8" +AddNet "/PSU/VIN9" AddNet "/USB/USBA_OE_N" -AddNet "/USB/USBA_SPD" -AddNet "/USB/USBA_VM" +AddNet "/USB/USBA_RCV" +AddNet "/USB/USBA_VP" AddNet "/USB/USBD_OE_N" -AddNet "/USB/USBD_SPD" +AddNet "/USB/USBD_RCV" AddNet "/USB/USBD_VP" AddNet "N-000117" AddNet "N-000118" @@ -746,13 +1452,17 @@ AddNet "N-000134" AddNet "N-000135" AddNet "N-000136" AddNet "N-000137" -AddNet "N-000142" AddNet "N-000143" -AddNet "N-000145" +AddNet "N-000144" +AddNet "N-000147" AddNet "N-000148" -AddNet "N-000153" -AddNet "N-000357" -AddNet "N-000359" +AddNet "N-000150" +AddNet "N-000151" +AddNet "N-000156" +AddNet "N-000157" +AddNet "N-000160" +AddNet "N-000354" +AddNet "N-000356" $EndNCLASS $NCLASS Name "ADDRESS/DDR" @@ -848,7 +1558,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -4133 -4133 $EndPAD $PAD @@ -869,133 +1579,133 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK" +Ne 49 "/Etherne180" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_RXD1" +Ne 50 "/Etherne181" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXDV" +Ne 65 "/FPGA,_P182" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" +Ne 51 "/Etherne183" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" +Ne 66 "/FPGA,_P184" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" +Ne 52 "/Etherne185" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_INT" +Ne 67 "/FPGA,_P186" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" +Ne 68 "/FPGA,_P187" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" +Ne 69 "/FPGA,_P188" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/Non_volatile_memories/NF_D2" +Ne 70 "/FPGA,_P189" Po 590 -4133 $EndPAD $PAD Sh "A14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/Non_volatile_memories/NF_ALE" +Ne 71 "/FPGA,_P190" Po 983 -4133 $EndPAD $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/Non_volatile_memories/NF_RNB" +Ne 72 "/FPGA,_P191" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" +Ne 227 "/Non_vol10" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/Non_volatile_memories/SD_CLK" +Ne 230 "/Non_vol13" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/Non_volatile_memories/SD_DAT0" +Ne 63 "/FPGA,_P14" Po 2558 -4133 $EndPAD $PAD Sh "A19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DBG_PRG/FPGA_TDO" +Ne 8 "/DBG_PRG22" Po 2952 -4133 $EndPAD $PAD Sh "A20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 254 "/USB/USBD_RCV" Po 3346 -4133 $EndPAD $PAD Sh "A21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/USB/USBD_OE_N" +Ne 253 "/USB/USBD_OE_N" Po 3739 -4133 $EndPAD $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 4133 -4133 $EndPAD $PAD @@ -1030,14 +1740,14 @@ $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2558 -3739 $EndPAD $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" +Ne 76 "/FPGA,_P195" Po -2165 -3739 $EndPAD $PAD @@ -1051,21 +1761,21 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER" +Ne 54 "/Etherne196" Po -1377 -3739 $EndPAD $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -983 -3739 $EndPAD $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_CRS" +Ne 55 "/Etherne197" Po -590 -3739 $EndPAD $PAD @@ -1079,21 +1789,21 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" +Ne 77 "/FPGA,_P198" Po 196 -3739 $EndPAD $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 590 -3739 $EndPAD $PAD Sh "B14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/Non_volatile_memories/NF_CLE" +Ne 78 "/FPGA,_P199" Po 983 -3739 $EndPAD $PAD @@ -1107,21 +1817,21 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/Non_volatile_memories/SD_DAT3" +Ne 228 "/Non_vol11" Po 1771 -3739 $EndPAD $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 2165 -3739 $EndPAD $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/Non_volatile_memories/SD_DAT1" +Ne 64 "/FPGA,_P15" Po 2558 -3739 $EndPAD $PAD @@ -1135,28 +1845,28 @@ $PAD Sh "B20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/USB/USBD_SPD" +Ne 163 "/FPGA_Po200" Po 3346 -3739 $EndPAD $PAD Sh "B21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/USB/USBD_VP" +Ne 255 "/USB/USBD_VP" Po 3739 -3739 $EndPAD $PAD Sh "B22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 164 "/FPGA_Po201" Po 4133 -3739 $EndPAD $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 156 "/FPGA_Po173" Po -4133 -3346 $EndPAD $PAD @@ -1184,56 +1894,56 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_RXD3" +Ne 79 "/FPGA,_P202" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_RXD2" +Ne 80 "/FPGA,_P203" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" +Ne 81 "/FPGA,_P204" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_TXC" +Ne 57 "/Etherne205" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_TXD1" +Ne 82 "/FPGA,_P206" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" +Ne 83 "/FPGA,_P207" Po -590 -3346 $EndPAD $PAD Sh "C11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" +Ne 84 "/FPGA,_P208" Po -196 -3346 $EndPAD $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/Non_volatile_memories/NF_D0" +Ne 231 "/Non_vol209" Po 196 -3346 $EndPAD $PAD @@ -1247,21 +1957,21 @@ $PAD Sh "C14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/Non_volatile_memories/NF_WE_N" +Ne 232 "/Non_vol210" Po 983 -3346 $EndPAD $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" +Ne 233 "/Non_vol211" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA,_Port0,_Port2,_PROG_IF/SD_CMD" +Ne 229 "/Non_vol12" Po 1771 -3346 $EndPAD $PAD @@ -1275,21 +1985,21 @@ $PAD Sh "C18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DBG_PRG/FPGA_TMS" +Ne 7 "/DBG_PRG21" Po 2558 -3346 $EndPAD $PAD Sh "C19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/USB/USBA_OE_N" +Ne 248 "/USB/USBA_OE_N" Po 2952 -3346 $EndPAD $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 218 "/FPGA_Po90" Po 3346 -3346 $EndPAD $PAD @@ -1303,21 +2013,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 219 "/FPGA_Po91" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 155 "/FPGA_Po172" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 178 "/FPGA_Po43" Po -3739 -2952 $EndPAD $PAD @@ -1331,7 +2041,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1345,42 +2055,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" +Ne 93 "/FPGA,_P24" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_MDC" +Ne 58 "/Etherne212" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXER" +Ne 85 "/FPGA,_P213" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" +Ne 86 "/FPGA,_P214" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" +Ne 87 "/FPGA,_P215" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/Non_volatile_memories/NF_D7" +Ne 88 "/FPGA,_P216" Po -196 -2952 $EndPAD $PAD @@ -1401,14 +2111,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/Non_volatile_memories/NF_D1" +Ne 89 "/FPGA,_P217" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/Non_volatile_memories/NF_CS1_N" +Ne 234 "/Non_vol218" Po 1377 -2952 $EndPAD $PAD @@ -1429,56 +2139,56 @@ $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 2558 -2952 $EndPAD $PAD Sh "D19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 250 "/USB/USBA_VP" Po 2952 -2952 $EndPAD $PAD Sh "D20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/USB/USBA_VM" +Ne 165 "/FPGA_Po219" Po 3346 -2952 $EndPAD $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 168 "/FPGA_Po29" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 221 "/FPGA_Po93" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 157 "/FPGA_Po174" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 158 "/FPGA_Po175" Po -3346 -2558 $EndPAD $PAD @@ -1506,7 +2216,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -1771 -2558 $EndPAD $PAD @@ -1534,7 +2244,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -196 -2558 $EndPAD $PAD @@ -1562,7 +2272,7 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 1377 -2558 $EndPAD $PAD @@ -1583,7 +2293,7 @@ $PAD Sh "E18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DBG_PRG/FPGA_TDI" +Ne 9 "/DBG_PRG23" Po 2558 -2558 $EndPAD $PAD @@ -1597,21 +2307,21 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 216 "/FPGA_Po87" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 181 "/FPGA_Po47" Po 4133 -2558 $EndPAD $PAD @@ -1625,14 +2335,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 145 "/FPGA_Po160" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 152 "/FPGA_Po169" Po -3346 -2165 $EndPAD $PAD @@ -1723,14 +2433,14 @@ $PAD Sh "F16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/USB/USBA_SPD" +Ne 166 "/FPGA_Po220" Po 1771 -2165 $EndPAD $PAD Sh "F17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 249 "/USB/USBA_RCV" Po 2165 -2165 $EndPAD $PAD @@ -1744,35 +2454,35 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 220 "/FPGA_Po92" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 213 "/FPGA_Po84" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 179 "/FPGA_Po45" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 180 "/FPGA_Po46" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 139 "/FPGA_Po152" Po -4133 -1771 $EndPAD $PAD @@ -1786,21 +2496,21 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 138 "/FPGA_Po151" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 140 "/FPGA_Po153" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2558 -1771 $EndPAD $PAD @@ -1870,7 +2580,7 @@ $PAD Sh "G15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DBG_PRG/FPGA_TCK" +Ne 6 "/DBG_PRG20" Po 1377 -1771 $EndPAD $PAD @@ -1891,21 +2601,21 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 187 "/FPGA_Po53" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 182 "/FPGA_Po48" Po 3346 -1771 $EndPAD $PAD @@ -1926,49 +2636,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 130 "/FPGA_Po143" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 129 "/FPGA_Po142" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_CLK#" +Ne 174 "/FPGA_Po38" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 173 "/FPGA_Po37" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 131 "/FPGA_Po144" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 149 "/FPGA_Po166" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -1771 -1377 $EndPAD $PAD @@ -2031,7 +2741,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 172 "/FPGA_Po35" Po 1771 -1377 $EndPAD $PAD @@ -2052,56 +2762,56 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 192 "/FPGA_Po60" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 167 "/FPGA_Po28" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 184 "/FPGA_Po50" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 193 "/FPGA_Po61" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 117 "/FPGA_Po127" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 116 "/FPGA_Po126" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 150 "/FPGA_Po167" Po -2952 -983 $EndPAD $PAD @@ -2136,7 +2846,7 @@ $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -983 -983 $EndPAD $PAD @@ -2150,7 +2860,7 @@ $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -196 -983 $EndPAD $PAD @@ -2164,7 +2874,7 @@ $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 590 -983 $EndPAD $PAD @@ -2178,7 +2888,7 @@ $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 1377 -983 $EndPAD $PAD @@ -2192,7 +2902,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 185 "/FPGA_Po51" Po 2165 -983 $EndPAD $PAD @@ -2206,70 +2916,70 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_CLK#" +Ne 21 "/DDR_Ban27" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 196 "/FPGA_Po66" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 197 "/FPGA_Po67" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 119 "/FPGA_Po129" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 118 "/FPGA_Po128" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 151 "/FPGA_Po168" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 146 "/FPGA_Po161" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 137 "/FPGA_Po150" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 132 "/FPGA_Po145" Po -2165 -590 $EndPAD $PAD @@ -2297,7 +3007,7 @@ $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -590 -590 $EndPAD $PAD @@ -2311,7 +3021,7 @@ $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 196 -590 $EndPAD $PAD @@ -2325,7 +3035,7 @@ $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 983 -590 $EndPAD $PAD @@ -2346,7 +3056,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 186 "/FPGA_Po52" Po 2165 -590 $EndPAD $PAD @@ -2360,28 +3070,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 215 "/FPGA_Po86" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 214 "/FPGA_Po85" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 198 "/FPGA_Po68" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 199 "/FPGA_Po69" Po 4133 -590 $EndPAD $PAD @@ -2402,21 +3112,21 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 143 "/FPGA_Po158" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 144 "/FPGA_Po159" Po -2952 -196 $EndPAD $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2558 -196 $EndPAD $PAD @@ -2444,7 +3154,7 @@ $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -983 -196 $EndPAD $PAD @@ -2458,7 +3168,7 @@ $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -196 -196 $EndPAD $PAD @@ -2472,7 +3182,7 @@ $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 590 -196 $EndPAD $PAD @@ -2507,21 +3217,21 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 191 "/FPGA_Po59" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 190 "/FPGA_Po58" Po 3346 -196 $EndPAD $PAD @@ -2542,21 +3252,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 125 "/FPGA_Po137" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 124 "/FPGA_Po136" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 176 "/FPGA_Po41" Po -3346 196 $EndPAD $PAD @@ -2605,7 +3315,7 @@ $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -590 196 $EndPAD $PAD @@ -2619,7 +3329,7 @@ $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 196 196 $EndPAD $PAD @@ -2633,7 +3343,7 @@ $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 983 196 $EndPAD $PAD @@ -2675,42 +3385,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 170 "/FPGA_Po31" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 205 "/FPGA_Po76" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 206 "/FPGA_Po77" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 123 "/FPGA_Po135" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 122 "/FPGA_Po134" Po -3346 590 $EndPAD $PAD @@ -2752,7 +3462,7 @@ $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -983 590 $EndPAD $PAD @@ -2766,7 +3476,7 @@ $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -196 590 $EndPAD $PAD @@ -2780,7 +3490,7 @@ $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 590 590 $EndPAD $PAD @@ -2794,7 +3504,7 @@ $PAD Sh "N15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 1377 590 $EndPAD $PAD @@ -2808,7 +3518,7 @@ $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 2165 590 $EndPAD $PAD @@ -2829,35 +3539,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 203 "/FPGA_Po74" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 204 "/FPGA_Po75" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 110 "/FPGA_Po119" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 109 "/FPGA_Po118" Po -3739 983 $EndPAD $PAD @@ -2913,7 +3623,7 @@ $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -590 983 $EndPAD $PAD @@ -2927,7 +3637,7 @@ $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 196 983 $EndPAD $PAD @@ -2941,7 +3651,7 @@ $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 983 983 $EndPAD $PAD @@ -2990,21 +3700,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 100 "/FPGA_Po106" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 101 "/FPGA_Po107" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 112 "/FPGA_Po121" Po -4133 1377 $EndPAD $PAD @@ -3018,7 +3728,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 111 "/FPGA_Po120" Po -3346 1377 $EndPAD $PAD @@ -3032,7 +3742,7 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2558 1377 $EndPAD $PAD @@ -3123,7 +3833,7 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 2558 1377 $EndPAD $PAD @@ -3137,7 +3847,7 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 102 "/FPGA_Po108" Po 3346 1377 $EndPAD $PAD @@ -3151,7 +3861,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 103 "/FPGA_Po109" Po 4133 1377 $EndPAD $PAD @@ -3165,7 +3875,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 175 "/FPGA_Po39" Po -3739 1771 $EndPAD $PAD @@ -3186,7 +3896,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO" +Ne 90 "/FPGA,_P221" Po -2558 1771 $EndPAD $PAD @@ -3214,7 +3924,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -983 1771 $EndPAD $PAD @@ -3242,7 +3952,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po 590 1771 $EndPAD $PAD @@ -3298,7 +4008,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 171 "/FPGA_Po33" Po 3739 1771 $EndPAD $PAD @@ -3312,21 +4022,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 105 "/FPGA_Po111" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 104 "/FPGA_Po110" Po -3346 2165 $EndPAD $PAD @@ -3354,7 +4064,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -1771 2165 $EndPAD $PAD @@ -3396,14 +4106,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" +Ne 91 "/FPGA,_P222" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" +Ne 92 "/FPGA,_P223" Po 983 2165 $EndPAD $PAD @@ -3445,35 +4155,35 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 225 "/FPGA_Po98" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 226 "/FPGA_Po99" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 107 "/FPGA_Po113" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 106 "/FPGA_Po112" Po -3739 2558 $EndPAD $PAD @@ -3487,7 +4197,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2952 2558 $EndPAD $PAD @@ -3515,7 +4225,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -1377 2558 $EndPAD $PAD @@ -3529,7 +4239,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -590 2558 $EndPAD $PAD @@ -3543,7 +4253,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po 196 2558 $EndPAD $PAD @@ -3557,7 +4267,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 983 2558 $EndPAD $PAD @@ -3571,7 +4281,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po 1771 2558 $EndPAD $PAD @@ -3606,14 +4316,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 94 "/FPGA_Po100" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 95 "/FPGA_Po101" Po 4133 2558 $EndPAD $PAD @@ -3648,7 +4358,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -2558 2952 $EndPAD $PAD @@ -3662,7 +4372,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -1771 2952 $EndPAD $PAD @@ -3725,7 +4435,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 1771 2952 $EndPAD $PAD @@ -3746,7 +4456,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 2952 2952 $EndPAD $PAD @@ -3921,14 +4631,14 @@ $PAD Sh "Y22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "N-000359" +Ne 277 "N-000356" Po 4133 3346 $EndPAD $PAD Sh "AA1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "N-000357" +Ne 276 "N-000354" Po -4133 3739 $EndPAD $PAD @@ -3942,7 +4652,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -3346 3739 $EndPAD $PAD @@ -3956,7 +4666,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2558 3739 $EndPAD $PAD @@ -3970,7 +4680,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -1771 3739 $EndPAD $PAD @@ -3984,7 +4694,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -983 3739 $EndPAD $PAD @@ -3998,7 +4708,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -196 3739 $EndPAD $PAD @@ -4012,7 +4722,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 590 3739 $EndPAD $PAD @@ -4026,7 +4736,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po 1377 3739 $EndPAD $PAD @@ -4040,7 +4750,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 2165 3739 $EndPAD $PAD @@ -4054,21 +4764,21 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po 2952 3739 $EndPAD $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1" +Ne 73 "/FPGA,_P192" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" +Ne 74 "/FPGA,_P193" Po 3739 3739 $EndPAD $PAD @@ -4082,7 +4792,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -4133 4133 $EndPAD $PAD @@ -4215,7 +4925,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0" +Ne 75 "/FPGA,_P194" Po 3346 4133 $EndPAD $PAD @@ -4229,12 +4939,12 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 $MODULE DFN10 -Po 66413 19106 0 15 4C7AAFAD 4C6C9ECB ~~ +Po 69634 18543 0 15 4C7AAFAD 4C6C9ECB ~~ Li DFN10 Sc 4C6C9ECB AR /4C69ED5F/4C6C9DB9 @@ -4251,77 +4961,77 @@ $PAD Sh "PAD" R 904 628 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 0 0 $EndPAD $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 270 "N-000148" Po -393 491 $EndPAD $PAD Sh "10" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 271 "N-000150" Po -393 -491 $EndPAD $PAD Sh "2" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -196 491 $EndPAD $PAD Sh "9" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 241 "/PSU/VFB2.5" Po -196 -491 $EndPAD $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 238 "/PSU/SW_1.2" Po 0 491 $EndPAD $PAD Sh "8" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 273 "N-000156" Po 0 -491 $EndPAD $PAD Sh "4" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 238 "/PSU/SW_1.2" Po 196 491 $EndPAD $PAD Sh "7" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 273 "N-000156" Po 196 -491 $EndPAD $PAD Sh "5" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 393 491 $EndPAD $PAD Sh "6" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 273 "N-000156" Po 393 -491 $EndPAD $EndMODULE DFN10 @@ -4349,7 +5059,7 @@ $PAD Sh "2" R 157 236 0 0 1350 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4377,7 +5087,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4398,14 +5108,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 176 "/FPGA_Po41" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Banks/M0_UDM" +Ne 177 "/FPGA_Po42" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4426,14 +5136,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 175 "/FPGA_Po39" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 25 "/DDR_Ban40" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4454,14 +5164,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 178 "/FPGA_Po43" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 26 "/DDR_Ban44" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4482,14 +5192,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 173 "/FPGA_Po37" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Banks/M0_CLK#" +Ne 174 "/FPGA_Po38" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4508,56 +5218,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 129 "/FPGA_Po142" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 130 "/FPGA_Po143" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 131 "/FPGA_Po144" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 132 "/FPGA_Po145" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 133 "/FPGA_Po146" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 12 "/DDR_Banks/M0_A2" +Ne 134 "/FPGA_Po147" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 135 "/FPGA_Po148" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 10 "/DDR_Banks/M0_A0" +Ne 136 "/FPGA_Po149" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -4576,56 +5286,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 137 "/FPGA_Po150" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 138 "/FPGA_Po151" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 139 "/FPGA_Po152" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 140 "/FPGA_Po153" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 141 "/FPGA_Po154" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 17 "/DDR_Banks/M0_BA1" +Ne 142 "/FPGA_Po155" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 17 "/DDR_Ban156" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/DDR_Banks/M0_RAS#" +Ne 18 "/DDR_Ban157" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -4644,56 +5354,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 143 "/FPGA_Po158" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 144 "/FPGA_Po159" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 145 "/FPGA_Po160" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 146 "/FPGA_Po161" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 147 "/FPGA_Po162" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 19 "/DDR_Ban163" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 148 "/FPGA_Po164" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 20 "/DDR_Ban165" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -4712,56 +5422,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 149 "/FPGA_Po166" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 150 "/FPGA_Po167" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 151 "/FPGA_Po168" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 152 "/FPGA_Po169" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 13 "/DDR_Banks/M0_A4" +Ne 36 "/DDR_Banks/M0_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 14 "/DDR_Banks/M0_A5" +Ne 153 "/FPGA_Po170" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 15 "/DDR_Banks/M0_A6" +Ne 154 "/FPGA_Po171" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 37 "/DDR_Banks/M0_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -4780,56 +5490,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 155 "/FPGA_Po172" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 156 "/FPGA_Po173" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 157 "/FPGA_Po174" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 158 "/FPGA_Po175" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 16 "/DDR_Banks/M0_A8" +Ne 159 "/FPGA_Po176" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 160 "/FPGA_Po177" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 161 "/FPGA_Po178" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 11 "/DDR_Banks/M0_A12" +Ne 162 "/FPGA_Po179" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -4848,56 +5558,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 116 "/FPGA_Po126" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 117 "/FPGA_Po127" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 118 "/FPGA_Po128" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 119 "/FPGA_Po129" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 14 "/DDR_Ban130" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 15 "/DDR_Ban131" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 120 "/FPGA_Po132" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 121 "/FPGA_Po133" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -4916,56 +5626,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 122 "/FPGA_Po134" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 123 "/FPGA_Po135" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 124 "/FPGA_Po136" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 125 "/FPGA_Po137" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 16 "/DDR_Ban138" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 22 "/DDR_Banks/M0_DQ2" +Ne 126 "/FPGA_Po139" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 127 "/FPGA_Po140" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 128 "/FPGA_Po141" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -4984,56 +5694,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 109 "/FPGA_Po118" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 110 "/FPGA_Po119" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 111 "/FPGA_Po120" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 112 "/FPGA_Po121" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 19 "/DDR_Banks/M0_DQ11" +Ne 113 "/FPGA_Po122" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 114 "/FPGA_Po123" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 115 "/FPGA_Po124" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 13 "/DDR_Ban125" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5052,61 +5762,61 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 104 "/FPGA_Po110" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 105 "/FPGA_Po111" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 106 "/FPGA_Po112" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 107 "/FPGA_Po113" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 21 "/DDR_Banks/M0_DQ15" +Ne 10 "/DDR_Ban114" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 108 "/FPGA_Po115" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 11 "/DDR_Ban116" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/DDR_Banks/M0_DQ12" +Ne 12 "/DDR_Ban117" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 $MODULE MLF20m1 -Po 61043 22374 0 15 4C7ABDFC 4C69F729 ~~ +Po 59642 19398 0 15 4C7ABDFC 4C69F729 ~~ Li MLF20m1 Sc 4C69F729 AR /4C69ED5F/4C69EE11 @@ -5123,28 +5833,28 @@ $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -235 -235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 235 -235 $EndPAD $PAD @@ -5186,7 +5896,7 @@ $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/PSU/Iout_1.2" +Ne 235 "/PSU/Iout_1.2" Po 0 -688 $EndPAD $PAD @@ -5200,7 +5910,7 @@ $PAD Sh "4" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/PSU/Iout_3.3" +Ne 236 "/PSU/Iout_3.3" Po 196 -688 $EndPAD $PAD @@ -5256,7 +5966,7 @@ $PAD Sh "8" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 688 0 $EndPAD $PAD @@ -5305,14 +6015,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 171 "/FPGA_Po33" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 23 "/DDR_Ban34" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5333,14 +6043,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 172 "/FPGA_Po35" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Banks/M1_CS#" +Ne 24 "/DDR_Ban36" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5361,14 +6071,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 168 "/FPGA_Po29" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 169 "/FPGA_Po30" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5389,14 +6099,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 170 "/FPGA_Po31" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 22 "/DDR_Ban32" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5415,56 +6125,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 222 "/FPGA_Po94" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 35 "/DDR_Ban95" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/DDR_Banks/M1_DQ13" +Ne 223 "/FPGA_Po96" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 224 "/FPGA_Po97" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 225 "/FPGA_Po98" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 226 "/FPGA_Po99" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 94 "/FPGA_Po100" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 95 "/FPGA_Po101" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5483,56 +6193,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 96 "/FPGA_Po102" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 97 "/FPGA_Po103" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_DQ9" +Ne 98 "/FPGA_Po104" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 99 "/FPGA_Po105" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 100 "/FPGA_Po106" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 101 "/FPGA_Po107" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 102 "/FPGA_Po108" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 103 "/FPGA_Po109" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5553,14 +6263,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/DDR_Banks/M1_CLK#" +Ne 21 "/DDR_Ban27" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 167 "/FPGA_Po28" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5579,56 +6289,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Banks/M1_A12" +Ne 34 "/DDR_Ban88" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Banks/M1_A11" +Ne 217 "/FPGA_Po89" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/DDR_Banks/M1_A9" +Ne 44 "/DDR_Banks/M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 43 "/DDR_Banks/M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 218 "/FPGA_Po90" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 219 "/FPGA_Po91" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 220 "/FPGA_Po92" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 221 "/FPGA_Po93" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5647,56 +6357,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 42 "/DDR_Banks/M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 211 "/FPGA_Po82" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M1_A5" +Ne 41 "/DDR_Banks/M1_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 212 "/FPGA_Po83" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 213 "/FPGA_Po84" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 214 "/FPGA_Po85" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 215 "/FPGA_Po86" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 216 "/FPGA_Po87" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5715,56 +6425,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 203 "/FPGA_Po74" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 204 "/FPGA_Po75" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 205 "/FPGA_Po76" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 206 "/FPGA_Po77" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 207 "/FPGA_Po78" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/DDR_Banks/M1_DQ2" +Ne 208 "/FPGA_Po79" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 209 "/FPGA_Po80" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_DQ0" +Ne 210 "/FPGA_Po81" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5783,56 +6493,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 190 "/FPGA_Po58" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 191 "/FPGA_Po59" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 192 "/FPGA_Po60" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 193 "/FPGA_Po61" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Banks/M1_CAS#" +Ne 31 "/DDR_Ban62" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 194 "/FPGA_Po63" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 195 "/FPGA_Po64" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 32 "/DDR_Ban65" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5851,56 +6561,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 196 "/FPGA_Po66" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 197 "/FPGA_Po67" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 198 "/FPGA_Po68" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 199 "/FPGA_Po69" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 33 "/DDR_Ban70" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 200 "/FPGA_Po71" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 37 "/DDR_Banks/M1_DQ5" +Ne 201 "/FPGA_Po72" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 36 "/DDR_Banks/M1_DQ4" +Ne 202 "/FPGA_Po73" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5919,56 +6629,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 184 "/FPGA_Po50" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 185 "/FPGA_Po51" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 186 "/FPGA_Po52" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 187 "/FPGA_Po53" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 188 "/FPGA_Po54" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 189 "/FPGA_Po55" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 28 "/DDR_Ban56" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 29 "/DDR_Ban57" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5987,56 +6697,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 179 "/FPGA_Po45" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 180 "/FPGA_Po46" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 181 "/FPGA_Po47" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 182 "/FPGA_Po48" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 40 "/DDR_Banks/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 183 "/FPGA_Po49" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 39 "/DDR_Banks/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 38 "/DDR_Banks/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6057,7 +6767,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -176 0 $EndPAD $PAD @@ -6085,14 +6795,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_A1.8V" +Ne 45 "/Etherne1" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 61 "/Etherne3" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6120,7 +6830,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_A1.8V" +Ne 45 "/Etherne1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6148,7 +6858,7 @@ $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -6176,7 +6886,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6204,7 +6914,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6232,7 +6942,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6260,7 +6970,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6287,56 +6997,56 @@ $PAD Sh "8" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -750 -1050 $EndPAD $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO" +Ne 90 "/FPGA,_P221" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" +Ne 91 "/FPGA,_P222" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" +Ne 74 "/FPGA,_P193" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0" +Ne 75 "/FPGA,_P194" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1" +Ne 73 "/FPGA,_P192" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" +Ne 92 "/FPGA,_P223" Po 250 1050 $EndPAD $PAD Sh "4" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 750 1050 $EndPAD $SHAPE3D @@ -6370,7 +7080,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -6398,7 +7108,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6426,7 +7136,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -6454,7 +7164,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -6482,7 +7192,7 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -6510,7 +7220,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -6531,14 +7241,14 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -6566,7 +7276,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -6594,7 +7304,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -6622,7 +7332,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -6650,7 +7360,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -6678,7 +7388,7 @@ $PAD Sh "2" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -6706,7 +7416,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -6727,14 +7437,14 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -6762,7 +7472,7 @@ $PAD Sh "2" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -6790,7 +7500,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6818,7 +7528,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6846,7 +7556,7 @@ $PAD Sh "2" R 157 236 0 0 2250 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6874,7 +7584,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6902,7 +7612,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6930,7 +7640,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6958,7 +7668,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6986,7 +7696,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7007,14 +7717,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7042,7 +7752,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7070,7 +7780,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7091,14 +7801,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7126,7 +7836,7 @@ $PAD Sh "2" R 157 236 0 0 450 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7154,7 +7864,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7175,14 +7885,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7210,7 +7920,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7231,14 +7941,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 136 "VCCO2" +Ne 278 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7259,14 +7969,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/USB/USBD_D+" +Ne 251 "/USB/USBD_D+" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7287,14 +7997,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/USB/USBD_D-" +Ne 252 "/USB/USBD_D-" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7322,7 +8032,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7343,14 +8053,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000132" +Ne 262 "N-000132" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7371,14 +8081,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000132" +Ne 262 "N-000132" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7399,14 +8109,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "N-000137" +Ne 266 "N-000137" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7427,14 +8137,14 @@ $PAD Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 125 "N-000134" +Ne 263 "N-000134" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 126 "N-000135" +Ne 264 "N-000135" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7455,14 +8165,14 @@ $PAD Sh "1" R 197 354 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 123 "N-000131" +Ne 261 "N-000131" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7483,14 +8193,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M1_VREF" +Ne 30 "/DDR_Ban6" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7518,7 +8228,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7546,7 +8256,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7574,7 +8284,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7602,7 +8312,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7630,7 +8340,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7658,7 +8368,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7686,7 +8396,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7714,7 +8424,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7742,7 +8452,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7770,7 +8480,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7798,7 +8508,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7826,7 +8536,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7854,7 +8564,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M1_VREF" +Ne 30 "/DDR_Ban6" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7875,14 +8585,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M0_VREF" +Ne 27 "/DDR_Ban5" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7910,7 +8620,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M0_VREF" +Ne 27 "/DDR_Ban5" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7938,7 +8648,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M1_VREF" +Ne 30 "/DDR_Ban6" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7959,14 +8669,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M1_VREF" +Ne 30 "/DDR_Ban6" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7987,14 +8697,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M0_VREF" +Ne 27 "/DDR_Ban5" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8022,7 +8732,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M0_VREF" +Ne 27 "/DDR_Ban5" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8048,56 +8758,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 126 "N-000135" +Ne 264 "N-000135" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 109 "/USB/USBA_D-" +Ne 247 "/USB/USBA_D-" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 108 "/USB/USBA_D+" +Ne 246 "/USB/USBA_D+" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 108 "/USB/USBA_D+" +Ne 246 "/USB/USBA_D+" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 122 "N-000130" +Ne 260 "N-000130" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 122 "N-000130" +Ne 260 "N-000130" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 122 "N-000130" +Ne 260 "N-000130" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 122 "N-000130" +Ne 260 "N-000130" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -8118,7 +8828,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000134" +Ne 263 "N-000134" Po -570 0 $EndPAD $PAD @@ -8153,7 +8863,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8174,14 +8884,14 @@ $PAD Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_A3.3V" +Ne 56 "/Etherne2" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8209,7 +8919,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8230,14 +8940,14 @@ $PAD Sh "1" R 197 354 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 108 "/USB/USBA_D+" +Ne 246 "/USB/USBA_D+" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8258,14 +8968,14 @@ $PAD Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 109 "/USB/USBA_D-" +Ne 247 "/USB/USBA_D-" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8293,7 +9003,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8321,7 +9031,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8349,7 +9059,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8377,7 +9087,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8398,14 +9108,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_A1.8V" +Ne 45 "/Etherne1" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8426,14 +9136,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_A3.3V" +Ne 56 "/Etherne2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8454,14 +9164,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 61 "/Etherne3" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8489,7 +9199,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8517,7 +9227,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8538,14 +9248,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 57 "/Ethernet_Phy/MAG_SHIELD" +Ne 62 "/Etherne4" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8566,14 +9276,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 122 "N-000130" +Ne 260 "N-000130" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8594,7 +9304,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 62 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" +Ne 93 "/FPGA,_P24" Po -176 0 $EndPAD $PAD @@ -8622,14 +9332,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 121 "N-000123" +Ne 259 "N-000123" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8657,7 +9367,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 58 "/Ethernet_Phy/MAG_TX+" +Ne 46 "/Etherne16" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8685,7 +9395,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 59 "/Ethernet_Phy/MAG_TX-" +Ne 47 "/Etherne17" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8713,7 +9423,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 55 "/Ethernet_Phy/MAG_RX+" +Ne 48 "/Etherne18" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8741,7 +9451,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 56 "/Ethernet_Phy/MAG_RX-" +Ne 53 "/Etherne19" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8762,14 +9472,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 119 "N-000117" +Ne 257 "N-000117" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 44 "/Ethernet_Phy/ETH_LED0" +Ne 59 "/Etherne25" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8790,14 +9500,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 120 "N-000118" +Ne 258 "N-000118" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 45 "/Ethernet_Phy/ETH_LED1" +Ne 60 "/Etherne26" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8818,14 +9528,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 57 "/Ethernet_Phy/MAG_SHIELD" +Ne 62 "/Etherne4" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8846,14 +9556,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 122 "N-000130" +Ne 260 "N-000130" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8882,7 +9592,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 128 "/FPGA_Po141" Po -3838 2176 $EndPAD $PAD @@ -8896,35 +9606,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 127 "/FPGA_Po140" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_DQ2" +Ne 126 "/FPGA_Po139" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 16 "/DDR_Ban138" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 121 "/FPGA_Po133" Po -2303 2176 $EndPAD $PAD @@ -8938,28 +9648,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 120 "/FPGA_Po132" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 15 "/DDR_Ban131" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 14 "/DDR_Ban130" Po -1023 2176 $EndPAD $PAD @@ -8980,7 +9690,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 20 "/DDR_Ban165" Po -255 2176 $EndPAD $PAD @@ -9008,35 +9718,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 148 "/FPGA_Po164" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 19 "/DDR_Ban163" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 147 "/FPGA_Po162" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M0_RAS#" +Ne 18 "/DDR_Ban157" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 1791 2176 $EndPAD $PAD @@ -9050,49 +9760,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 17 "/DDR_Ban156" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_BA1" +Ne 142 "/FPGA_Po155" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 141 "/FPGA_Po154" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_A0" +Ne 136 "/FPGA_Po149" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 135 "/FPGA_Po148" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_A2" +Ne 134 "/FPGA_Po147" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 133 "/FPGA_Po146" Po 3838 2176 $EndPAD $PAD @@ -9106,63 +9816,63 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_A4" +Ne 36 "/DDR_Banks/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_A5" +Ne 153 "/FPGA_Po170" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_A6" +Ne 154 "/FPGA_Po171" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 37 "/DDR_Banks/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_A8" +Ne 159 "/FPGA_Po176" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 160 "/FPGA_Po177" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 161 "/FPGA_Po178" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_A12" +Ne 162 "/FPGA_Po179" Po 2047 -2176 $EndPAD $PAD @@ -9176,42 +9886,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_CLK#" +Ne 174 "/FPGA_Po38" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 26 "/DDR_Ban44" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 173 "/FPGA_Po37" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M0_UDM" +Ne 177 "/FPGA_Po42" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M0_VREF" +Ne 27 "/DDR_Ban5" Po 255 -2176 $EndPAD $PAD @@ -9225,14 +9935,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 25 "/DDR_Ban40" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -511 -2176 $EndPAD $PAD @@ -9246,7 +9956,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 13 "/DDR_Ban125" Po -1023 -2176 $EndPAD $PAD @@ -9260,35 +9970,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 115 "/FPGA_Po124" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 114 "/FPGA_Po123" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_DQ11" +Ne 113 "/FPGA_Po122" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_DQ12" +Ne 12 "/DDR_Ban117" Po -2558 -2176 $EndPAD $PAD @@ -9302,35 +10012,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 11 "/DDR_Ban116" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 108 "/FPGA_Po115" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_DQ15" +Ne 10 "/DDR_Ban114" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -9359,7 +10069,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_DQ0" +Ne 210 "/FPGA_Po81" Po -3838 2176 $EndPAD $PAD @@ -9373,35 +10083,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 209 "/FPGA_Po80" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_DQ2" +Ne 208 "/FPGA_Po79" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 207 "/FPGA_Po78" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_DQ4" +Ne 202 "/FPGA_Po73" Po -2303 2176 $EndPAD $PAD @@ -9415,28 +10125,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/DDR_Banks/M1_DQ5" +Ne 201 "/FPGA_Po72" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 200 "/FPGA_Po71" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 33 "/DDR_Ban70" Po -1023 2176 $EndPAD $PAD @@ -9457,7 +10167,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 32 "/DDR_Ban65" Po -255 2176 $EndPAD $PAD @@ -9485,35 +10195,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 195 "/FPGA_Po64" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 194 "/FPGA_Po63" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_CAS#" +Ne 31 "/DDR_Ban62" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 29 "/DDR_Ban57" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_CS#" +Ne 24 "/DDR_Ban36" Po 1791 2176 $EndPAD $PAD @@ -9527,49 +10237,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 28 "/DDR_Ban56" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 189 "/FPGA_Po55" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 188 "/FPGA_Po54" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 38 "/DDR_Banks/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 39 "/DDR_Banks/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 183 "/FPGA_Po49" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 40 "/DDR_Banks/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -9583,63 +10293,63 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 212 "/FPGA_Po83" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_A5" +Ne 41 "/DDR_Banks/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 211 "/FPGA_Po82" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 42 "/DDR_Banks/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 43 "/DDR_Banks/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_A9" +Ne 44 "/DDR_Banks/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_A11" +Ne 217 "/FPGA_Po89" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_A12" +Ne 34 "/DDR_Ban88" Po 2047 -2176 $EndPAD $PAD @@ -9653,42 +10363,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_CLK#" +Ne 21 "/DDR_Ban27" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 169 "/FPGA_Po30" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 167 "/FPGA_Po28" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 22 "/DDR_Ban32" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M1_VREF" +Ne 30 "/DDR_Ban6" Po 255 -2176 $EndPAD $PAD @@ -9702,14 +10412,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 23 "/DDR_Ban34" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -511 -2176 $EndPAD $PAD @@ -9723,7 +10433,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 99 "/FPGA_Po105" Po -1023 -2176 $EndPAD $PAD @@ -9737,35 +10447,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_DQ9" +Ne 98 "/FPGA_Po104" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 97 "/FPGA_Po103" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 96 "/FPGA_Po102" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 224 "/FPGA_Po97" Po -2558 -2176 $EndPAD $PAD @@ -9779,35 +10489,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_DQ13" +Ne 223 "/FPGA_Po96" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 35 "/DDR_Ban95" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 222 "/FPGA_Po94" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -9827,35 +10537,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 57 "/Ethernet_Phy/MAG_SHIELD" +Ne 62 "/Etherne4" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 57 "/Ethernet_Phy/MAG_SHIELD" +Ne 62 "/Etherne4" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 57 "/Ethernet_Phy/MAG_SHIELD" +Ne 62 "/Etherne4" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 57 "/Ethernet_Phy/MAG_SHIELD" +Ne 62 "/Etherne4" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 58 "/Ethernet_Phy/MAG_TX+" +Ne 46 "/Etherne16" Po -1750 -2500 $EndPAD $PAD @@ -9869,28 +10579,28 @@ $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 118 "GND" +Ne 256 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 55 "/Ethernet_Phy/MAG_RX+" +Ne 48 "/Etherne18" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 59 "/Ethernet_Phy/MAG_TX-" +Ne 47 "/Etherne17" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 118 "GND" +Ne 256 "GND" Po -250 -3500 $EndPAD $PAD @@ -9904,7 +10614,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 56 "/Ethernet_Phy/MAG_RX-" +Ne 53 "/Etherne19" Po 1750 -3500 $EndPAD $PAD @@ -9918,7 +10628,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 119 "N-000117" +Ne 257 "N-000117" Po -1150 -5400 $EndPAD $PAD @@ -9932,7 +10642,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 120 "N-000118" +Ne 258 "N-000118" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -9957,21 +10667,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 83 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" +Ne 227 "/Non_vol10" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 97 "/Non_volatile_memories/SD_DAT3" +Ne 228 "/Non_vol11" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 82 "/FPGA,_Port0,_Port2,_PROG_IF/SD_CMD" +Ne 229 "/Non_vol12" Po -433 0 $EndPAD $PAD @@ -9985,56 +10695,56 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 94 "/Non_volatile_memories/SD_CLK" +Ne 230 "/Non_vol13" Po 433 0 $EndPAD $PAD Sh "6" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 866 0 $EndPAD $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 95 "/Non_volatile_memories/SD_DAT0" +Ne 63 "/FPGA,_P14" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 96 "/Non_volatile_memories/SD_DAT1" +Ne 64 "/FPGA,_P15" Po 1732 0 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po -2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po -2707 -2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 2707 -2244 $EndPAD $EndMODULE MICROSD-500901 @@ -10298,28 +11008,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/Non_volatile_memories/NF_RNB" +Ne 72 "/FPGA,_P191" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/Non_volatile_memories/NF_RNB" +Ne 72 "/FPGA,_P191" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" +Ne 233 "/Non_vol211" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/Non_volatile_memories/NF_CS1_N" +Ne 234 "/Non_vol218" Po -690 3850 $EndPAD $PAD @@ -10347,7 +11057,7 @@ $PAD Sh "13" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 100 3850 $EndPAD $PAD @@ -10368,21 +11078,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/Non_volatile_memories/NF_CLE" +Ne 78 "/FPGA,_P199" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/Non_volatile_memories/NF_ALE" +Ne 71 "/FPGA,_P190" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/Non_volatile_memories/NF_WE_N" +Ne 232 "/Non_vol210" Po 1080 3850 $EndPAD $PAD @@ -10459,28 +11169,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/Non_volatile_memories/NF_D0" +Ne 231 "/Non_vol209" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/Non_volatile_memories/NF_D1" +Ne 89 "/FPGA,_P217" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/Non_volatile_memories/NF_D2" +Ne 70 "/FPGA,_P189" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" +Ne 77 "/FPGA,_P198" Po 880 -3850 $EndPAD $PAD @@ -10508,7 +11218,7 @@ $PAD Sh "36" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 100 -3850 $EndPAD $PAD @@ -10543,28 +11253,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" +Ne 69 "/FPGA,_P188" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" +Ne 84 "/FPGA,_P208" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" +Ne 68 "/FPGA,_P187" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/Non_volatile_memories/NF_D7" +Ne 88 "/FPGA,_P216" Po -1480 -3850 $EndPAD $PAD @@ -10614,35 +11324,35 @@ $PAD Sh "12" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -1613 1082 $EndPAD $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER" +Ne 54 "/Etherne196" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" +Ne 51 "/Etherne183" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXDV" +Ne 65 "/FPGA,_P182" Po -1613 491 $EndPAD $PAD Sh "8" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -1613 295 $EndPAD $PAD @@ -10656,63 +11366,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" +Ne 76 "/FPGA,_P195" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_RXD1" +Ne 50 "/Etherne181" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_RXD2" +Ne 80 "/FPGA,_P203" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_RXD3" +Ne 79 "/FPGA,_P202" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_MDC" +Ne 58 "/Etherne212" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" +Ne 93 "/FPGA,_P24" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" +Ne 81 "/FPGA,_P204" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 61 "/Etherne3" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK" +Ne 49 "/Etherne180" Po -688 -1613 $EndPAD $PAD @@ -10726,7 +11436,7 @@ $PAD Sh "44" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po -295 -1613 $EndPAD $PAD @@ -10747,56 +11457,56 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/Ethernet_Phy/MAG_TX+" +Ne 46 "/Etherne16" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/Ethernet_Phy/MAG_TX-" +Ne 47 "/Etherne17" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_A3.3V" +Ne 56 "/Etherne2" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "N-000123" +Ne 259 "N-000123" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_INT" +Ne 67 "/FPGA,_P186" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_LED0" +Ne 59 "/Etherne25" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_LED1" +Ne 60 "/Etherne26" Po 1613 688 $EndPAD $PAD @@ -10824,21 +11534,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_A1.8V" +Ne 45 "/Etherne1" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/Ethernet_Phy/MAG_RX-" +Ne 53 "/Etherne19" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/MAG_RX+" +Ne 48 "/Etherne18" Po 1613 -491 $EndPAD $PAD @@ -10852,14 +11562,14 @@ $PAD Sh "35" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 1613 -1082 $EndPAD $PAD @@ -10873,70 +11583,70 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXER" +Ne 85 "/FPGA,_P213" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_TXC" +Ne 57 "/Etherne205" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" +Ne 86 "/FPGA,_P214" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" +Ne 87 "/FPGA,_P215" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_TXD1" +Ne 82 "/FPGA,_P206" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" +Ne 83 "/FPGA,_P207" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" +Ne 66 "/FPGA,_P184" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" +Ne 52 "/Etherne185" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_CRS" +Ne 55 "/Etherne197" Po 688 1613 $EndPAD $PAD Sh "23" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 885 1613 $EndPAD $PAD @@ -10971,7 +11681,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -10993,35 +11703,35 @@ $PAD Sh "1" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/PSU/VIN_DC-DC-3.3" +Ne 243 "/PSU/VIN7" Po -375 500 $EndPAD $PAD Sh "3" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/PSU/SW_3.3" +Ne 239 "/PSU/SW_3.3" Po 375 500 $EndPAD $PAD Sh "5" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/PSU/VFB3.3" +Ne 242 "/PSU/VFB3.3" Po -375 -500 $EndPAD $PAD Sh "2" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 0 500 $EndPAD $PAD Sh "4" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/PSU/VIN_DC-DC-3.3" +Ne 243 "/PSU/VIN7" Po 375 -500 $EndPAD $SHAPE3D @@ -11049,35 +11759,35 @@ $PAD Sh "1" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/PSU/VIN_DC-DC-1.2" +Ne 244 "/PSU/VIN8" Po -375 500 $EndPAD $PAD Sh "3" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/PSU/SW_1.2" +Ne 238 "/PSU/SW_1.2" Po 375 500 $EndPAD $PAD Sh "5" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/PSU/VFB1.2" +Ne 240 "/PSU/VFB1.2" Po -375 -500 $EndPAD $PAD Sh "2" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 0 500 $EndPAD $PAD Sh "4" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/PSU/VIN_DC-DC-1.2" +Ne 244 "/PSU/VIN8" Po 375 -500 $EndPAD $SHAPE3D @@ -11111,7 +11821,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/PSU/VFB3.3" +Ne 242 "/PSU/VFB3.3" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11123,7 +11833,7 @@ AR /4C69ED5F/4C6D2DBC Op 0 0 0 At SMD T0 638 32 200 200 0 40 M V 20 N"R25" -T1 0 -150 200 200 0 40 M I 20 N"R" +T1 0 -150 200 200 0 40 M I 20 N"200K" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 @@ -11132,14 +11842,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/PSU/VFB3.3" +Ne 242 "/PSU/VFB3.3" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11151,7 +11861,7 @@ AR /4C69ED5F/4C6D2DDD Op 0 0 0 At SMD T0 -650 -5 200 200 1800 40 M V 20 N"R26" -T1 0 -150 200 200 1800 40 M I 20 N"R" +T1 0 -150 200 200 1800 40 M I 20 N"900K" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 @@ -11167,7 +11877,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/PSU/VFB3.3" +Ne 242 "/PSU/VFB3.3" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11195,7 +11905,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11223,7 +11933,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11235,7 +11945,7 @@ AR /4C69ED5F/4C6D2FD2 Op 0 0 0 At SMD T0 -666 -14 200 200 1800 40 M V 20 N"R28" -T1 0 -150 200 200 1800 40 M I 20 N"R" +T1 0 -150 200 200 1800 40 M I 20 N"200K" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 @@ -11251,7 +11961,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/PSU/VFB1.2" +Ne 240 "/PSU/VFB1.2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11263,7 +11973,7 @@ AR /4C69ED5F/4C6D2FD3 Op 0 0 0 At SMD T0 646 21 200 200 0 40 M V 20 N"R27" -T1 0 -150 200 200 0 40 M I 20 N"R" +T1 0 -150 200 200 0 40 M I 20 N"200K" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 @@ -11272,14 +11982,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/PSU/VFB1.2" +Ne 240 "/PSU/VFB1.2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11307,7 +12017,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/PSU/VFB1.2" +Ne 240 "/PSU/VFB1.2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11328,14 +12038,14 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 106 "/PSU/VIN_DC-DC-3.3" +Ne 243 "/PSU/VIN7" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -11356,14 +12066,14 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 105 "/PSU/VIN_DC-DC-1.2" +Ne 244 "/PSU/VIN8" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -11391,7 +12101,7 @@ $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -11419,7 +12129,7 @@ $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -11447,7 +12157,7 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/PSU/SW_3.3" +Ne 239 "/PSU/SW_3.3" Po 570 0 $EndPAD $EndMODULE 1210 @@ -11475,7 +12185,7 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/PSU/SW_1.2" +Ne 238 "/PSU/SW_1.2" Po 570 0 $EndPAD $EndMODULE 1210 @@ -11503,7 +12213,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_A3.3V" +Ne 56 "/Etherne2" Po 294 0 $EndPAD $EndMODULE 0603 @@ -11531,7 +12241,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 135 "N-000359" +Ne 277 "N-000356" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11559,7 +12269,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 134 "N-000357" +Ne 276 "N-000354" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11581,7 +12291,7 @@ $PAD Sh "1" R 600 600 0 0 0 Dr 400 0 0 At STD N 00E0FFFF -Ne 6 "/DBG_PRG/FPGA_TCK" +Ne 6 "/DBG_PRG20" Po -3500 500 $EndPAD $PAD @@ -11595,7 +12305,7 @@ $PAD Sh "3" C 600 600 0 0 0 Dr 400 0 0 At STD N 00E0FFFF -Ne 9 "/DBG_PRG/FPGA_TMS" +Ne 7 "/DBG_PRG21" Po -2500 500 $EndPAD $PAD @@ -11609,7 +12319,7 @@ $PAD Sh "5" C 600 600 0 0 0 Dr 400 0 0 At STD N 00E0FFFF -Ne 8 "/DBG_PRG/FPGA_TDO" +Ne 8 "/DBG_PRG22" Po -1500 500 $EndPAD $PAD @@ -11623,7 +12333,7 @@ $PAD Sh "7" C 600 600 0 0 0 Dr 400 0 0 At STD N 00E0FFFF -Ne 7 "/DBG_PRG/FPGA_TDI" +Ne 9 "/DBG_PRG23" Po -500 500 $EndPAD $PAD @@ -11728,49 +12438,49 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 116 "/USB/USBD_SPD" +Ne 163 "/FPGA_Po200" Po -295 491 $EndPAD $PAD Sh "11" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 113 "/USB/USBD_D+" +Ne 251 "/USB/USBD_D+" Po -98 -491 $EndPAD $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 254 "/USB/USBD_RCV" Po -98 491 $EndPAD $PAD Sh "10" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 114 "/USB/USBD_D-" +Ne 252 "/USB/USBD_D-" Po 98 -491 $EndPAD $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 117 "/USB/USBD_VP" +Ne 255 "/USB/USBD_VP" Po 98 491 $EndPAD $PAD Sh "9" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 115 "/USB/USBD_OE_N" +Ne 253 "/USB/USBD_OE_N" Po 295 -491 $EndPAD $PAD Sh "4" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 164 "/FPGA_Po201" Po 295 491 $EndPAD $PAD @@ -11798,7 +12508,7 @@ $PAD Sh "6" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 491 98 $EndPAD $PAD @@ -11812,7 +12522,7 @@ $PAD Sh "7" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 491 -98 $EndPAD $PAD @@ -11862,49 +12572,49 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 111 "/USB/USBA_SPD" +Ne 166 "/FPGA_Po220" Po -295 491 $EndPAD $PAD Sh "11" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 108 "/USB/USBA_D+" +Ne 246 "/USB/USBA_D+" Po -98 -491 $EndPAD $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 249 "/USB/USBA_RCV" Po -98 491 $EndPAD $PAD Sh "10" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 109 "/USB/USBA_D-" +Ne 247 "/USB/USBA_D-" Po 98 -491 $EndPAD $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Port_1,_Port_3_" +Ne 250 "/USB/USBA_VP" Po 98 491 $EndPAD $PAD Sh "9" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 110 "/USB/USBA_OE_N" +Ne 248 "/USB/USBA_OE_N" Po 295 -491 $EndPAD $PAD Sh "4" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 112 "/USB/USBA_VM" +Ne 165 "/FPGA_Po219" Po 295 491 $EndPAD $PAD @@ -11932,7 +12642,7 @@ $PAD Sh "6" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 491 98 $EndPAD $PAD @@ -11946,7 +12656,7 @@ $PAD Sh "7" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 491 -98 $EndPAD $PAD @@ -11988,7 +12698,7 @@ $PAD Sh "2" R 157 236 0 0 1350 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12016,7 +12726,7 @@ $PAD Sh "2" R 157 236 0 0 1350 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12044,7 +12754,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -12072,7 +12782,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12100,7 +12810,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12128,7 +12838,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12156,7 +12866,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12184,7 +12894,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12212,7 +12922,7 @@ $PAD Sh "2" R 157 236 0 0 3150 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12238,35 +12948,35 @@ $PAD Sh "1" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 128 "N-000137" +Ne 266 "N-000137" Po 0 0 $EndPAD $PAD Sh "2" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/USB/USBD_D-" +Ne 252 "/USB/USBD_D-" Po 310 0 $EndPAD $PAD Sh "3" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/USB/USBD_D+" +Ne 251 "/USB/USBD_D+" Po 630 0 $EndPAD $PAD Sh "4" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000136" +Ne 265 "N-000136" Po 940 0 $EndPAD $PAD Sh "5" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000136" +Ne 265 "N-000136" Po 1260 0 $EndPAD $PAD @@ -12287,256 +12997,256 @@ $PAD Sh "8" R 860 900 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000132" +Ne 262 "N-000132" Po -1070 140 $EndPAD $PAD Sh "6" R 860 900 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000132" +Ne 262 "N-000132" Po 2320 2310 $EndPAD $PAD Sh "7" R 860 900 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000132" +Ne 262 "N-000132" Po -1070 2310 $EndPAD $PAD Sh "9" R 860 900 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000132" +Ne 262 "N-000132" Po 2320 140 $EndPAD $EndMODULE ZX62D-B-5P8 $MODULE 0402 -Po 62606 20638 900 15 4C7ABE61 4C7712F2 ~~ +Po 64184 20201 1800 0 4C7C40F4 4C7712F2 ~~ Li 0402 Sc 4C7712F2 AR /4C69ED5F/4C770712 Op 0 0 0 At SMD -T0 -488 -12 200 200 1800 40 N V 25 N"R33" -T1 0 150 200 200 900 40 N I 25 N"R" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 448 -28 200 200 4500 40 M V 20 N"R33" +T1 0 -150 200 200 1800 40 M I 20 N"R" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 900 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 98 "/PSU/Iout_1.2" +At SMD N 00440001 +Ne 235 "/PSU/Iout_1.2" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 900 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 118 "GND" +At SMD N 00440001 +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 61366 20701 900 15 4C7ABE4D 4C7712F4 ~~ +Po 62656 20169 1800 0 4C7C410A 4C7712F4 ~~ Li 0402 Sc 4C7712F4 AR /4C69ED5F/4C77067B Op 0 0 0 At SMD -T0 -480 27 200 200 1800 40 N V 25 N"R31" -T1 0 150 200 200 900 40 N I 25 N"R" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 453 -4 200 200 2700 40 M V 20 N"R31" +T1 0 -150 200 200 1800 40 M I 20 N"R" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 900 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 99 "/PSU/Iout_3.3" +At SMD N 00440001 +Ne 236 "/PSU/Iout_3.3" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 900 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 118 "GND" +At SMD N 00440001 +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 1206 -Po 64173 19087 0 15 4C5FF890 4C7712F5 ~~ +Po 64185 19630 900 15 4C7C40B0 4C7712F5 ~~ Li 1206 Sc 4C7712F5 AR /4C69ED5F/4C770713 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"R34" -T1 0 150 200 200 0 40 N I 25 N"R" +T0 -571 -523 200 200 900 40 N V 25 N"R34" +T1 0 150 200 200 900 40 N I 25 N"R" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 DS 798 -384 798 384 50 21 DS 798 384 -798 384 50 21 $PAD -Sh "1" R 355 668 0 0 0 +Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/PSU/VIN_DC-DC-1.2" +Ne 244 "/PSU/VIN8" Po -570 0 $EndPAD $PAD -Sh "2" R 355 668 0 0 0 +Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 130 "N-000143" +Ne 275 "N-000160" Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 62413 19004 0 15 4C5FF890 4C7712F7 ~~ +Po 62660 19594 2700 15 4C7C401C 4C7712F7 ~~ Li 1206 Sc 4C7712F7 AR /4C69ED5F/4C77060E Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"R32" -T1 0 150 200 200 0 40 N I 25 N"R" +T0 547 543 200 200 2700 40 N V 25 N"R32" +T1 0 150 200 200 2700 40 N I 25 N"R" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 DS 798 -384 798 384 50 21 DS 798 384 -798 384 50 21 $PAD -Sh "1" R 355 668 0 0 0 +Sh "1" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/PSU/VIN_DC-DC-3.3" +Ne 243 "/PSU/VIN7" Po -570 0 $EndPAD $PAD -Sh "2" R 355 668 0 0 0 +Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 129 "N-000142" +Ne 267 "N-000143" Po 570 0 $EndPAD $EndMODULE 1206 $MODULE MLP6 -Po 62075 20634 0 15 4C7ABE5A 4C7712F8 ~~ +Po 64188 19638 2700 0 4C7ABE5A 4C7712F8 ~~ Li MLP6 Sc 4C7712F8 AR /4C69ED5F/4C770714 Op 0 0 0 At SMD -T0 -8 -437 200 200 0 40 N V 25 N"U14" -T1 0 150 200 200 0 40 N I 25 N"FAN4010" -DC -354 354 -354 314 39 21 -DS -295 295 -295 -295 39 21 -DS -295 -295 295 -295 39 21 -DS 295 -295 295 295 39 21 -DS 295 295 -295 295 39 21 +T0 -8 437 200 200 2700 40 M V 20 N"U14" +T1 0 -150 200 200 2700 40 M I 20 N"FAN4010" +DC -354 -354 -354 -314 39 20 +DS -295 -295 -295 295 39 20 +DS -295 295 295 295 39 20 +DS 295 295 295 -295 39 20 +DS 295 -295 -295 -295 39 20 $PAD -Sh "1" R 118 204 0 0 0 +Sh "1" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 130 "N-000143" -Po -196 153 -$EndPAD -$PAD -Sh "6" R 118 204 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" +At SMD N 00440001 +Ne 275 "N-000160" Po -196 -153 $EndPAD $PAD -Sh "2" R 118 204 0 0 0 +Sh "6" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 0 153 +At SMD N 00440001 +Ne 244 "/PSU/VIN8" +Po -196 153 $EndPAD $PAD -Sh "5" R 118 204 0 0 0 +Sh "2" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 118 "GND" +At SMD N 00440001 +Ne 0 "" Po 0 -153 $EndPAD $PAD -Sh "3" R 118 204 0 0 0 +Sh "5" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 98 "/PSU/Iout_1.2" -Po 196 153 +At SMD N 00440001 +Ne 256 "GND" +Po 0 153 $EndPAD $PAD -Sh "4" R 118 204 0 0 0 +Sh "3" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" +At SMD N 00440001 +Ne 235 "/PSU/Iout_1.2" Po 196 -153 $EndPAD +$PAD +Sh "4" R 118 204 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 196 153 +$EndPAD $EndMODULE MLP6 $MODULE MLP6 -Po 60839 20701 0 15 4C7ABE3E 4C7712FA ~~ +Po 62656 19551 2700 0 4C7ABE3E 4C7712FA ~~ Li MLP6 Sc 4C7712FA AR /4C69ED5F/4C7705B0 Op 0 0 0 At SMD -T0 -12 -441 200 200 0 40 N V 25 N"U13" -T1 0 150 200 200 0 40 N I 25 N"FAN4010" -DC -354 354 -354 314 39 21 -DS -295 295 -295 -295 39 21 -DS -295 -295 295 -295 39 21 -DS 295 -295 295 295 39 21 -DS 295 295 -295 295 39 21 +T0 -12 441 200 200 2700 40 M V 20 N"U13" +T1 0 -150 200 200 2700 40 M I 20 N"FAN4010" +DC -354 -354 -354 -314 39 20 +DS -295 -295 -295 295 39 20 +DS -295 295 295 295 39 20 +DS 295 295 295 -295 39 20 +DS 295 -295 -295 -295 39 20 $PAD -Sh "1" R 118 204 0 0 0 +Sh "1" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 129 "N-000142" -Po -196 153 -$EndPAD -$PAD -Sh "6" R 118 204 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 106 "/PSU/VIN_DC-DC-3.3" +At SMD N 00440001 +Ne 267 "N-000143" Po -196 -153 $EndPAD $PAD -Sh "2" R 118 204 0 0 0 +Sh "6" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 0 153 +At SMD N 00440001 +Ne 243 "/PSU/VIN7" +Po -196 153 $EndPAD $PAD -Sh "5" R 118 204 0 0 0 +Sh "2" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 118 "GND" +At SMD N 00440001 +Ne 0 "" Po 0 -153 $EndPAD $PAD -Sh "3" R 118 204 0 0 0 +Sh "5" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 99 "/PSU/Iout_3.3" -Po 196 153 +At SMD N 00440001 +Ne 256 "GND" +Po 0 153 $EndPAD $PAD -Sh "4" R 118 204 0 0 0 +Sh "3" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" +At SMD N 00440001 +Ne 236 "/PSU/Iout_3.3" Po 196 -153 $EndPAD +$PAD +Sh "4" R 118 204 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 196 153 +$EndPAD $EndMODULE MLP6 $MODULE SOT23_6 Po 63685 22677 900 15 4C7ABE7D 4C79C70B ~~ @@ -12556,7 +13266,7 @@ $PAD Sh "6" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/PSU/VIN_DC-DC-5.0" +Ne 245 "/PSU/VIN9" Po -375 -500 $EndPAD $PAD @@ -12570,28 +13280,28 @@ $PAD Sh "4" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 133 "N-000153" +Ne 274 "N-000157" Po 375 -500 $EndPAD $PAD Sh "3" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/PSU/VFB1.2" +Ne 240 "/PSU/VFB1.2" Po 375 500 $EndPAD $PAD Sh "2" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "GND" +Ne 256 "GND" Po 0 500 $EndPAD $PAD Sh "1" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 131 "N-000145" +Ne 272 "N-000151" Po -375 500 $EndPAD $SHAPE3D @@ -12609,7 +13319,7 @@ AR /4C69ED5F/4C79C7C0 Op 0 0 0 At SMD T0 618 -20 200 200 0 40 M V 20 N"R37" -T1 0 -150 200 200 0 40 M I 20 N"R" +T1 0 -150 200 200 0 40 M I 20 N"1M" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 @@ -12618,14 +13328,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 133 "N-000153" +Ne 274 "N-000157" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/PSU/VIN_DC-DC-5.0" +Ne 245 "/PSU/VIN9" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12653,7 +13363,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/PSU/VFB1.2" +Ne 240 "/PSU/VFB1.2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12665,7 +13375,7 @@ AR /4C69ED5F/4C79C8B0 Op 0 0 0 At SMD T0 -591 -24 200 200 1800 40 M V 20 N"R38" -T1 0 -150 200 200 1800 40 M I 20 N"R" +T1 0 -150 200 200 1800 40 M I 20 N"332K" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 @@ -12674,14 +13384,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/PSU/VFB1.2" +Ne 240 "/PSU/VFB1.2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12693,7 +13403,7 @@ AR /4C69ED5F/4C79C8B1 Op 0 0 0 At SMD T0 595 16 200 200 0 40 M V 20 N"R39" -T1 0 -150 200 200 0 40 M I 20 N"R" +T1 0 -150 200 200 0 40 M I 20 N"1.02M" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 @@ -12709,7 +13419,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/PSU/VFB1.2" +Ne 240 "/PSU/VFB1.2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12737,35 +13447,35 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 64205 20650 900 15 4C7AC7A7 4C79CCA5 ~~ +Po 65700 20201 1800 0 4C7C4145 4C79CCA5 ~~ Li 0402 Sc 4C79CCA5 AR /4C69ED5F/4C79C99C Op 0 0 0 At SMD -T0 -480 -4 200 200 1800 40 N V 25 N"R35" -T1 0 150 200 200 900 40 N I 25 N"R" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 453 -4 200 200 2700 40 M V 20 N"R35" +T1 0 -150 200 200 1800 40 M I 20 N"R" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 900 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 100 "/PSU/Iout_5.0" +At SMD N 00440001 +Ne 237 "/PSU/Iout_5.0" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 900 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 118 "GND" +At SMD N 00440001 +Ne 256 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12786,14 +13496,14 @@ $PAD Sh "1" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/PSU/VIN_DC-DC-5.0" +Ne 245 "/PSU/VIN9" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -12821,35 +13531,35 @@ $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "GND" +Ne 256 "GND" Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 65343 20783 1800 15 4C5FF890 4C79CCA9 ~~ +Po 65689 19645 900 15 4C5FF890 4C79CCA9 ~~ Li 1206 Sc 4C79CCA9 AR /4C69ED5F/4C79C99B Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"R36" -T1 0 150 200 200 1800 40 N I 25 N"R" +T0 0 -150 200 200 900 40 N V 25 N"R36" +T1 0 150 200 200 900 40 N I 25 N"R" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 DS 798 -384 798 384 50 21 DS 798 384 -798 384 50 21 $PAD -Sh "1" R 355 668 0 0 1800 +Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/PSU/VIN_DC-DC-5.0" +Ne 245 "/PSU/VIN9" Po -570 0 $EndPAD $PAD -Sh "2" R 355 668 0 0 1800 +Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000148" +Ne 268 "N-000144" Po 570 0 $EndPAD $EndMODULE 1206 @@ -12870,74 +13580,354 @@ $PAD Sh "1" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 131 "N-000145" +Ne 272 "N-000151" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/PSU/VIN_DC-DC-5.0" +Ne 245 "/PSU/VIN9" Po 570 0 $EndPAD $EndMODULE 1210 $MODULE MLP6 -Po 63685 20650 0 15 4C7AC798 4C7AC78E ~~ +Po 65696 19622 2700 0 4C7AC798 4C7AC78E ~~ Li MLP6 Sc 4C7AC78E AR /4C69ED5F/4C79C99A Op 0 0 0 At SMD -T0 20 -441 200 200 0 40 N V 25 N"U16" -T1 0 150 200 200 0 40 N I 25 N"FAN4010" -DC -354 354 -354 314 39 21 -DS -295 295 -295 -295 39 21 -DS -295 -295 295 -295 39 21 -DS 295 -295 295 295 39 21 -DS 295 295 -295 295 39 21 +T0 20 441 200 200 2700 40 M V 20 N"U16" +T1 0 -150 200 200 2700 40 M I 20 N"FAN4010" +DC -354 -354 -354 -314 39 20 +DS -295 -295 -295 295 39 20 +DS -295 295 295 295 39 20 +DS 295 295 295 -295 39 20 +DS 295 -295 -295 -295 39 20 $PAD -Sh "1" R 118 204 0 0 0 +Sh "1" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 132 "N-000148" -Po -196 153 -$EndPAD -$PAD -Sh "6" R 118 204 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 107 "/PSU/VIN_DC-DC-5.0" +At SMD N 00440001 +Ne 268 "N-000144" Po -196 -153 $EndPAD $PAD -Sh "2" R 118 204 0 0 0 +Sh "6" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 0 "" -Po 0 153 +Po -196 153 $EndPAD $PAD -Sh "5" R 118 204 0 0 0 +Sh "2" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 118 "GND" +At SMD N 00440001 +Ne 0 "" Po 0 -153 $EndPAD $PAD -Sh "3" R 118 204 0 0 0 +Sh "5" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 100 "/PSU/Iout_5.0" -Po 196 153 +At SMD N 00440001 +Ne 256 "GND" +Po 0 153 $EndPAD $PAD -Sh "4" R 118 204 0 0 0 +Sh "3" R 118 204 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" +At SMD N 00440001 +Ne 237 "/PSU/Iout_5.0" Po 196 -153 $EndPAD +$PAD +Sh "4" R 118 204 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 196 153 +$EndPAD $EndMODULE MLP6 +$MODULE 0402 +Po 71902 20413 0 15 4C5FF890 4C7C4FF3 ~~ +Li 0402 +Sc 4C7C4FF3 +AR /4C69ED5F/4C7C4CEF +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R43" +T1 0 150 200 200 0 40 N I 25 N"51K" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 241 "/PSU/VFB2.5" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 71835 18839 0 15 4C5FF890 4C7C4FF5 ~~ +Li 0402 +Sc 4C7C4FF5 +AR /4C69ED5F/4C7C4CEE +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R42" +T1 0 150 200 200 0 40 N I 25 N"24K" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 241 "/PSU/VFB2.5" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 256 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 70622 18594 0 15 4C5FF890 4C7C4FF7 ~~ +Li 0402 +Sc 4C7C4FF7 +AR /4C69ED5F/4C7C4DAA +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R41" +T1 0 150 200 200 0 40 N I 25 N"160K" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 270 "N-000148" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 256 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 70443 19380 0 15 4C5FF890 4C7C4FF9 ~~ +Li 0402 +Sc 4C7C4FF9 +AR /4C69ED5F/4C7C4D9E +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R40" +T1 0 150 200 200 0 40 N I 25 N"47K" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 271 "N-000150" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 269 "N-000147" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 70047 17740 0 15 4C5FF890 4C7C4FFB ~~ +Li 0402 +Sc 4C7C4FFB +AR /4C69ED5F/4C7C4CF1 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C103" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 256 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 71740 19594 0 15 4C5FF890 4C7C4FFD ~~ +Li 0402 +Sc 4C7C4FFD +AR /4C69ED5F/4C7C4CEC +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C101" +T1 0 150 200 200 0 40 N I 25 N"22pF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 241 "/PSU/VFB2.5" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 70350 20394 0 15 4C5FF890 4C7C4FFF ~~ +Li 0402 +Sc 4C7C4FFF +AR /4C69ED5F/4C7C4D94 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C100" +T1 0 150 200 200 0 40 N I 25 N"220pF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 269 "N-000147" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 256 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 1206 +Po 68921 20594 1800 15 4C5FF890 4C7C5000 ~~ +Li 1206 +Sc 4C7C5000 +AR /4C69ED5F/4C7C4CED +Op 0 0 0 +At SMD +T0 0 -150 200 200 1800 40 N V 25 N"C102" +T1 0 150 200 200 1800 40 N I 25 N"10uF" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 256 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 +$MODULE 1206 +Po 68531 18894 2700 15 4C5FF890 4C7C5002 ~~ +Li 1206 +Sc 4C7C5002 +AR /4C69ED5F/4C7C4D8E +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 25 N"C99" +T1 0 150 200 200 2700 40 N I 25 N"22uF" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 273 "N-000156" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 256 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 +$MODULE 1210 +Po 68563 16866 900 15 4C7C5007 4C7C5003 ~~ +Li 1210 +Sc 4C7C5003 +AR /4C69ED5F/4C7C4CF0 +Op 0 0 0 +At SMD +T0 0 -150 200 200 900 40 N V 25 N"L11" +T1 0 150 200 200 900 40 N I 25 N"2.2uH" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 238 "/PSU/SW_1.2" +Po 570 0 +$EndPAD +$EndMODULE 1210 $COTATION Ge 0 25 0 Va 21500 @@ -14447,27 +15437,27 @@ Po 3 57799 32445 57799 32445 157 -1 De 15 1 6 0 0 Po 0 57646 32598 57799 32445 59 -1 De 15 0 6 0 0 -Po 0 59614 31098 59614 30563 59 -1 +Po 0 59134 29925 59134 30638 59 -1 De 3 0 7 0 0 -Po 0 59732 30315 61031 29016 59 -1 -De 3 0 7 0 0 -Po 0 59732 30445 59732 30315 59 -1 -De 3 0 7 0 0 -Po 0 59614 30563 59732 30445 59 -1 -De 3 0 7 0 0 -Po 0 59024 32004 59425 32004 59 -1 -De 3 0 7 0 0 -Po 0 58840 31820 59024 32004 59 -1 -De 15 0 7 0 0 -Po 3 59024 32004 59024 32004 157 -1 +Po 0 58827 31027 58827 31032 59 -1 +De 15 0 7 0 400 +Po 3 58965 30807 58965 30807 157 -1 De 15 1 7 0 0 -Po 0 58827 31820 58840 31820 59 -1 -De 15 0 7 0 800 -Po 0 59614 31815 59614 31098 59 -1 +Po 0 58827 31027 58965 30807 59 -1 +De 15 0 7 0 0 +Po 0 59134 30638 58965 30807 59 -1 De 3 0 7 0 0 -Po 0 59614 31098 59614 31114 59 -1 +Po 0 59209 29846 59209 29850 59 -1 De 3 0 7 0 0 -Po 0 59425 32004 59614 31815 59 -1 +Po 0 59209 29850 59134 29925 59 -1 +De 3 0 7 0 0 +Po 0 59134 29925 59138 29921 59 -1 +De 3 0 7 0 0 +Po 0 60464 28591 60465 28591 59 -1 +De 3 0 7 0 0 +Po 0 59213 29842 59209 29846 59 -1 +De 3 0 7 0 0 +Po 0 59209 29846 60464 28591 59 -1 De 3 0 7 0 0 Po 0 59221 30245 59221 30082 59 -1 De 15 0 8 0 800 @@ -14481,4818 +15471,1544 @@ Po 0 59221 30082 59366 29937 59 -1 De 15 0 8 0 0 Po 0 59221 30245 59239 30245 59 -1 De 15 0 8 0 800 -Po 0 59134 29925 59134 30638 59 -1 +Po 0 59614 31098 59614 30563 59 -1 De 3 0 9 0 0 -Po 0 58827 31027 58827 31032 59 -1 -De 15 0 9 0 400 -Po 3 58965 30807 58965 30807 157 -1 -De 15 1 9 0 0 -Po 0 58827 31027 58965 30807 59 -1 +Po 0 59732 30315 61031 29016 59 -1 +De 3 0 9 0 0 +Po 0 59732 30445 59732 30315 59 -1 +De 3 0 9 0 0 +Po 0 59614 30563 59732 30445 59 -1 +De 3 0 9 0 0 +Po 0 59024 32004 59425 32004 59 -1 +De 3 0 9 0 0 +Po 0 58840 31820 59024 32004 59 -1 De 15 0 9 0 0 -Po 0 59134 30638 58965 30807 59 -1 +Po 3 59024 32004 59024 32004 157 -1 +De 15 1 9 0 0 +Po 0 58827 31820 58840 31820 59 -1 +De 15 0 9 0 800 +Po 0 59614 31815 59614 31098 59 -1 De 3 0 9 0 0 -Po 0 59209 29846 59209 29850 59 -1 +Po 0 59614 31098 59614 31114 59 -1 De 3 0 9 0 0 -Po 0 59209 29850 59134 29925 59 -1 +Po 0 59425 32004 59614 31815 59 -1 De 3 0 9 0 0 -Po 0 59134 29925 59138 29921 59 -1 -De 3 0 9 0 0 -Po 0 60464 28591 60465 28591 59 -1 -De 3 0 9 0 0 -Po 0 59213 29842 59209 29846 59 -1 -De 3 0 9 0 0 -Po 0 59209 29846 60464 28591 59 -1 -De 3 0 9 0 0 -Po 0 50995 31576 50694 31576 39 -1 -De 15 0 10 0 800 -Po 0 49921 31535 49768 31535 39 -1 -De 0 0 10 0 400 -Po 0 49961 31575 49921 31535 39 -1 -De 0 0 10 0 0 -Po 0 50693 31575 49961 31575 39 -1 -De 0 0 10 0 0 -Po 3 50693 31575 50693 31575 157 -1 -De 15 1 10 0 0 -Po 0 50694 31576 50693 31575 39 -1 -De 15 0 10 0 0 -Po 0 47941 31937 47657 31937 39 -1 -De 0 0 11 0 800 -Po 0 47460 32599 46643 32599 39 -1 -De 15 0 11 0 400 -Po 0 47583 32476 47460 32599 39 -1 -De 15 0 11 0 0 -Po 0 47583 32011 47583 32476 39 -1 -De 15 0 11 0 0 -Po 0 47657 31937 47583 32011 39 -1 -De 15 0 11 0 0 -Po 3 47657 31937 47657 31937 157 -1 -De 15 1 11 0 0 -Po 0 50995 31064 50688 31064 39 -1 -De 15 0 12 0 800 -Po 0 50189 31142 49768 31142 39 -1 -De 0 0 12 0 400 -Po 0 50264 31067 50189 31142 39 -1 -De 0 0 12 0 0 -Po 0 50685 31067 50264 31067 39 -1 -De 0 0 12 0 0 -Po 3 50685 31067 50685 31067 157 -1 -De 15 1 12 0 0 -Po 0 50688 31064 50685 31067 39 -1 -De 15 0 12 0 0 -Po 0 47937 31535 47145 31535 39 -1 -De 0 0 13 0 800 -Po 0 46843 30808 46643 30808 39 -1 -De 15 0 13 0 400 -Po 0 46941 30906 46843 30808 39 -1 -De 15 0 13 0 0 -Po 3 46941 30906 46941 30906 157 -1 -De 15 1 13 0 0 -Po 0 46941 31331 46941 30906 39 -1 -De 0 0 13 0 0 -Po 0 47145 31535 46941 31331 39 -1 -De 0 0 13 0 0 -Po 0 47937 31338 47294 31338 39 -1 -De 0 0 14 0 800 -Po 0 47020 31064 46643 31064 39 -1 -De 15 0 14 0 400 -Po 0 47110 31154 47020 31064 39 -1 -De 15 0 14 0 0 -Po 3 47110 31154 47110 31154 157 -1 -De 15 1 14 0 0 -Po 0 47294 31338 47110 31154 39 -1 -De 0 0 14 0 0 -Po 0 47937 31142 47417 31142 39 -1 -De 0 0 15 0 800 -Po 0 47239 31320 46643 31320 39 -1 -De 15 0 15 0 400 -Po 0 47417 31142 47239 31320 39 -1 -De 15 0 15 0 0 -Po 3 47417 31142 47417 31142 157 -1 -De 15 1 15 0 0 -Po 0 47941 32527 47256 32527 39 -1 -De 0 0 16 0 800 -Po 0 46883 31832 46643 31832 39 -1 -De 15 0 16 0 400 -Po 0 46980 31929 46883 31832 39 -1 -De 15 0 16 0 0 -Po 3 46980 31929 46980 31929 157 -1 -De 15 1 16 0 0 -Po 0 46980 32251 46980 31929 39 -1 -De 0 0 16 0 0 -Po 0 47256 32527 46980 32251 39 -1 -De 0 0 16 0 0 -Po 0 50995 32088 50706 32088 39 -1 -De 15 0 17 0 800 -Po 0 50657 32119 49775 32119 39 -1 -De 0 0 17 0 400 -Po 0 50697 32079 50657 32119 39 -1 -De 0 0 17 0 0 -Po 3 50697 32079 50697 32079 157 -1 -De 15 1 17 0 0 -Po 0 50706 32088 50697 32079 39 -1 -De 15 0 17 0 0 -Po 0 48219 33358 48108 33358 39 -1 -De 3 0 18 0 0 -Po 0 51567 33358 48219 33358 39 -1 -De 3 0 18 0 0 -Po 0 47018 33237 47139 33358 39 -1 -De 3 0 18 0 0 -Po 0 47139 33358 48108 33358 39 -1 -De 3 0 18 0 0 -Po 0 47018 33237 46959 33169 39 -1 -De 3 0 18 0 0 -Po 0 46643 33111 46891 33111 39 -1 -De 15 0 18 0 800 -Po 0 46891 33111 46999 33219 39 -1 -De 15 0 18 0 0 -Po 0 46999 33219 46959 33169 39 -1 -De 15 0 18 0 0 -Po 3 46959 33169 46959 33169 157 -1 -De 15 1 18 0 0 -Po 0 51823 33358 52591 33358 39 -1 -De 3 0 18 0 0 -Po 0 52740 33209 52923 33026 39 -1 -De 15 0 18 0 0 -Po 3 52740 33209 52740 33209 157 -1 -De 15 1 18 0 0 -Po 0 51658 33358 51823 33358 39 -1 -De 3 0 18 0 0 -Po 0 52923 33026 52923 33001 39 -1 -De 15 0 18 0 400 -Po 0 52591 33358 52740 33209 39 -1 -De 3 0 18 0 0 -Po 0 51610 33264 51610 33310 39 -1 -De 3 0 18 0 0 -Po 0 51610 33310 51658 33358 39 -1 -De 3 0 18 0 0 -Po 0 51610 33264 51610 33315 39 -1 -De 3 0 18 0 0 -Po 0 51610 33315 51567 33358 39 -1 -De 3 0 18 0 0 -Po 0 51614 33358 51614 33268 39 -1 -De 3 0 18 0 0 -Po 0 51587 33241 51370 33241 39 -1 -De 0 0 18 0 400 -Po 0 51610 33264 51587 33241 39 -1 -De 0 0 18 0 0 -Po 3 51610 33264 51610 33264 157 -1 -De 15 1 18 0 0 -Po 0 51614 33268 51610 33264 39 -1 -De 3 0 18 0 0 -Po 0 51567 33358 51614 33358 39 -1 -De 3 0 18 0 0 -Po 0 51614 33358 51658 33358 39 -1 -De 3 0 18 0 0 -Po 0 47351 36590 47209 36590 39 -1 -De 0 0 19 0 800 -Po 0 46850 36949 46643 36949 39 -1 -De 15 0 19 0 400 -Po 0 47000 36799 46850 36949 39 -1 -De 15 0 19 0 0 -Po 3 47000 36799 47000 36799 157 -1 -De 15 1 19 0 0 -Po 0 47209 36590 47000 36799 39 -1 -De 0 0 19 0 0 -Po 0 46643 37204 46900 37204 39 -1 -De 15 0 20 0 800 -Po 0 47188 37492 47362 37492 39 -1 -De 0 0 20 0 400 -Po 0 47035 37339 47188 37492 39 -1 -De 0 0 20 0 0 -Po 3 47035 37339 47035 37339 157 -1 -De 15 1 20 0 0 -Po 0 46900 37204 47035 37339 39 -1 -De 15 0 20 0 0 Po 0 47362 38082 47260 38082 39 -1 -De 0 0 21 0 800 +De 0 0 10 0 800 Po 0 46858 38484 46643 38484 39 -1 -De 15 0 21 0 400 +De 15 0 10 0 400 Po 0 46972 38370 46858 38484 39 -1 -De 15 0 21 0 0 +De 15 0 10 0 0 Po 3 46972 38370 46972 38370 157 -1 -De 15 1 21 0 0 +De 15 1 10 0 0 Po 0 47260 38082 46972 38370 39 -1 -De 0 0 21 0 0 -Po 0 49838 37693 50661 37693 39 -1 -De 0 0 22 0 800 -Po 0 50684 37716 50995 37716 39 -1 -De 15 0 22 0 400 -Po 0 50661 37693 50684 37716 39 -1 -De 15 0 22 0 0 -Po 3 50661 37693 50661 37693 157 -1 -De 15 1 22 0 0 -Po 0 50995 33111 50716 33111 39 -1 -De 15 0 23 0 800 -Po 0 49858 32512 50039 32693 39 -1 -De 0 0 23 0 0 -Po 3 50039 32693 50039 32693 157 -1 -De 15 1 23 0 0 -Po 0 49858 32512 49775 32512 39 -1 -De 0 0 23 0 400 -Po 0 50039 33102 50039 32693 39 -1 -De 15 0 23 0 0 -Po 0 50224 33287 50039 33102 39 -1 -De 15 0 23 0 0 -Po 0 50540 33287 50224 33287 39 -1 -De 15 0 23 0 0 -Po 0 50716 33111 50540 33287 39 -1 -De 15 0 23 0 0 -Po 0 46643 33879 47916 33879 39 -1 -De 15 0 24 0 800 -Po 0 48102 34055 48151 34055 39 -1 -De 0 0 24 0 400 -Po 0 47921 33874 48102 34055 39 -1 -De 0 0 24 0 0 -Po 3 47921 33874 47921 33874 157 -1 -De 15 1 24 0 0 -Po 0 47916 33879 47921 33874 39 -1 -De 15 0 24 0 0 -Po 0 46643 34391 47017 34391 79 -1 -De 15 0 25 0 800 -Po 0 47265 34290 47265 34154 79 -1 -De 0 0 25 0 400 -Po 0 47165 34390 47265 34290 79 -1 -De 0 0 25 0 0 -Po 0 47018 34390 47165 34390 79 -1 -De 0 0 25 0 0 -Po 3 47018 34390 47018 34390 157 -1 -De 15 1 25 0 0 -Po 0 47017 34391 47018 34390 79 -1 -De 15 0 25 0 0 -Po 0 47265 34646 47265 34154 79 -1 -De 0 0 25 0 C00 -Po 0 47265 33661 47265 34154 79 -1 -De 0 0 25 0 C00 -Po 0 47265 33169 47265 33661 79 -1 -De 0 0 25 0 C00 -Po 0 62748 32299 62539 32299 39 -1 -De 0 0 26 0 800 -Po 0 62487 32343 61604 32343 39 -1 -De 15 0 26 0 400 -Po 0 62535 32295 62487 32343 39 -1 -De 15 0 26 0 0 -Po 3 62535 32295 62535 32295 157 -1 -De 15 1 26 0 0 -Po 0 62539 32299 62535 32295 39 -1 -De 0 0 26 0 0 -Po 0 62748 32496 61984 32496 39 -1 -De 0 0 27 0 800 -Po 0 61875 32599 61604 32599 39 -1 -De 15 0 27 0 400 -Po 0 61878 32602 61875 32599 39 -1 -De 15 0 27 0 0 -Po 3 61878 32602 61878 32602 157 -1 -De 15 1 27 0 0 -Po 0 61984 32496 61878 32602 39 -1 -De 0 0 27 0 0 -Po 0 62752 31075 61894 31075 39 -1 -De 0 0 28 0 800 -Po 0 61883 31064 61604 31064 39 -1 -De 15 0 28 0 400 -Po 0 61894 31075 61883 31064 39 -1 -De 15 0 28 0 0 -Po 3 61894 31075 61894 31075 157 -1 -De 15 1 28 0 0 -Po 0 62748 32103 61853 32103 39 -1 -De 0 0 29 0 800 -Po 0 61832 32088 61604 32088 39 -1 -De 15 0 29 0 400 -Po 0 61850 32106 61832 32088 39 -1 -De 15 0 29 0 0 -Po 3 61850 32106 61850 32106 157 -1 -De 15 1 29 0 0 -Po 0 61853 32103 61850 32106 39 -1 -De 0 0 29 0 0 -Po 0 65130 33819 65260 33819 39 -1 -De 0 0 30 0 800 -Po 0 65712 33367 65956 33367 39 -1 -De 15 0 30 0 400 -Po 0 65677 33402 65712 33367 39 -1 -De 15 0 30 0 0 -Po 3 65677 33402 65677 33402 157 -1 -De 15 1 30 0 0 -Po 0 65260 33819 65677 33402 39 -1 -De 0 0 30 0 0 -Po 0 60067 33433 60740 33433 39 -1 -De 3 0 31 0 0 -Po 0 60803 33496 60740 33433 39 -1 -De 3 0 31 0 0 -Po 0 59631 33213 59753 33335 39 -1 -De 3 0 31 0 0 -Po 0 59753 33335 59969 33335 39 -1 -De 3 0 31 0 0 -Po 0 59969 33335 60067 33433 39 -1 -De 3 0 31 0 0 -Po 0 59421 33213 59623 33213 39 -1 -De 3 0 31 0 0 -Po 3 59421 33213 59421 33213 157 -1 -De 15 1 31 0 0 -Po 0 59421 33213 59239 33395 39 -1 -De 15 0 31 0 0 -Po 0 59239 33395 59221 33395 39 -1 -De 15 0 31 0 400 -Po 0 59623 33213 59631 33213 39 -1 -De 3 0 31 0 0 -Po 0 61604 33111 61188 33111 39 -1 -De 15 0 31 0 800 -Po 0 61188 33111 60803 33496 39 -1 -De 15 0 31 0 0 -Po 0 60803 33496 60970 33496 39 -1 -De 0 0 31 0 0 -Po 0 60970 33496 61020 33546 39 -1 -De 0 0 31 0 400 -Po 0 59211 33395 59221 33395 39 -1 -De 15 0 31 0 400 -Po 3 60803 33496 60803 33496 157 -1 -De 15 1 31 0 0 -Po 0 62886 33177 63060 33177 39 -1 -De 15 0 32 0 0 -Po 0 63135 33102 65229 33102 39 -1 -De 15 0 32 0 0 -Po 0 63060 33177 63135 33102 39 -1 -De 15 0 32 0 0 -Po 0 62605 33098 62807 33098 39 -1 -De 0 0 32 0 800 -Po 0 65476 32855 65956 32855 39 -1 -De 15 0 32 0 400 -Po 0 65229 33102 65476 32855 39 -1 -De 15 0 32 0 0 -Po 0 62886 33177 62894 33169 39 -1 -De 15 0 32 0 0 -Po 3 62886 33177 62886 33177 157 -1 -De 15 1 32 0 0 -Po 0 62807 33098 62886 33177 39 -1 -De 0 0 32 0 0 -Po 0 65118 37893 65122 37893 39 -1 -De 0 0 33 0 800 -Po 0 65713 38484 65956 38484 39 -1 -De 15 0 33 0 400 -Po 0 65268 38039 65713 38484 39 -1 -De 15 0 33 0 0 -Po 3 65268 38039 65268 38039 157 -1 -De 15 1 33 0 0 -Po 0 65122 37893 65268 38039 39 -1 -De 0 0 33 0 0 -Po 0 62886 37906 62087 37906 39 -1 -De 0 0 34 0 800 -Po 0 61897 37716 61604 37716 39 -1 -De 15 0 34 0 400 -Po 0 61909 37728 61897 37716 39 -1 -De 15 0 34 0 0 -Po 3 61909 37728 61909 37728 157 -1 -De 15 1 34 0 0 -Po 0 62087 37906 61909 37728 39 -1 -De 0 0 34 0 0 -Po 0 65118 37500 65444 37500 39 -1 -De 0 0 35 0 800 -Po 0 65660 37716 65956 37716 39 -1 -De 15 0 35 0 400 -Po 0 65657 37713 65660 37716 39 -1 -De 15 0 35 0 0 -Po 3 65657 37713 65657 37713 157 -1 -De 15 1 35 0 0 -Po 0 65444 37500 65657 37713 39 -1 -De 0 0 35 0 0 -Po 0 65126 36622 65331 36622 39 -1 -De 0 0 36 0 800 -Po 0 65658 36949 65956 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39 -1 +De 15 0 274 0 0 +Po 0 60745 37756 60642 37756 39 -1 +De 0 0 277 0 800 +Po 0 60500 37724 60402 37724 39 -1 +De 15 0 277 0 400 +Po 0 60555 37669 60500 37724 39 -1 +De 15 0 277 0 0 +Po 3 60555 37669 60555 37669 157 -1 +De 15 1 277 0 0 +Po 0 60642 37756 60555 37669 39 -1 +De 0 0 277 0 0 +Po 0 59566 39482 59273 39482 79 -1 +De 15 0 278 0 800 +Po 0 59076 39285 59076 38900 79 -1 +De 0 0 278 0 400 Po 0 59114 39323 59076 39285 79 -1 -De 0 0 136 0 0 +De 0 0 278 0 0 Po 3 59114 39323 59114 39323 157 -1 -De 15 1 136 0 0 +De 15 1 278 0 0 Po 0 59273 39482 59114 39323 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 0 56300 37226 56491 37226 79 -1 -De 0 0 136 0 800 +De 0 0 278 0 800 Po 0 56487 36936 56634 37083 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 3 56634 37083 56634 37083 157 -1 -De 15 1 136 0 0 +De 15 1 278 0 0 Po 0 56487 36936 56465 36936 79 -1 -De 15 0 136 0 400 +De 15 0 278 0 400 Po 0 56491 37226 56634 37083 79 -1 -De 0 0 136 0 0 +De 0 0 278 0 0 Po 0 56073 38117 56068 38117 79 -1 -De 15 0 136 0 800 +De 15 0 278 0 800 Po 3 55882 38303 55882 38303 157 -1 -De 15 1 136 0 0 +De 15 1 278 0 0 Po 0 56068 38117 55882 38303 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 0 56859 36149 56859 36162 79 -1 -De 15 0 136 0 800 +De 15 0 278 0 800 Po 3 57059 36362 57059 36362 157 -1 -De 15 1 136 0 0 +De 15 1 278 0 0 Po 0 56859 36162 57059 36362 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 0 55286 36149 55286 36151 79 -1 -De 15 0 136 0 800 +De 15 0 278 0 800 Po 3 55094 36697 55094 36697 157 -1 -De 15 1 136 0 0 +De 15 1 278 0 0 Po 0 55091 36694 55094 36697 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 0 55091 36346 55091 36694 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 0 55286 36151 55091 36346 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 0 54892 36936 54887 36936 79 -1 -De 15 0 136 0 800 +De 15 0 278 0 800 Po 3 54713 37110 54713 37110 157 -1 -De 15 1 136 0 0 +De 15 1 278 0 0 Po 0 54887 36936 54713 37110 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 3 52720 38303 52720 38303 157 -1 -De 15 1 136 0 0 +De 15 1 278 0 0 Po 0 52720 38303 52906 38117 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 0 52906 38117 52923 38117 79 -1 -De 15 0 136 0 400 +De 15 0 278 0 400 Po 0 54498 38117 54493 38117 79 -1 -De 15 0 136 0 800 +De 15 0 278 0 800 Po 3 54323 38287 54323 38287 157 -1 -De 15 1 136 0 0 +De 15 1 278 0 0 Po 0 54493 38117 54323 38287 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 0 53711 37330 53705 37330 79 -1 -De 15 0 136 0 800 +De 15 0 278 0 800 Po 3 53543 37492 53543 37492 157 -1 -De 15 1 136 0 0 +De 15 1 278 0 0 Po 0 53705 37330 53543 37492 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 Po 0 58040 36936 58046 36936 79 -1 -De 15 0 136 0 800 +De 15 0 278 0 800 Po 3 58236 37126 58236 37126 157 -1 -De 15 1 136 0 0 +De 15 1 278 0 0 Po 0 58046 36936 58236 37126 79 -1 -De 15 0 136 0 0 +De 15 0 278 0 0 $EndTRACK $ZONE $EndZONE @@ -21190,7 +22180,7 @@ ZLayer 4 ZAux 43 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 57465 32756 0 ZCorner 57465 32441 0 ZCorner 57807 32441 0 @@ -23675,7 +24665,7 @@ ZLayer 4 ZAux 51 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 50610 40110 0 ZCorner 51756 37996 0 ZCorner 51843 37949 0 @@ -29378,12 +30368,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C74868B 118 "GND" +ZInfo 4C74868B 256 "GND" ZLayer 1 ZAux 12 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 66094 41240 0 ZCorner 66339 30043 0 ZCorner 66339 29488 0 @@ -37306,7 +38296,7 @@ ZLayer 2 ZAux 9 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 58146 36236 0 ZCorner 58146 33566 0 ZCorner 63350 28362 0 @@ -38509,12 +39499,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75CC96 102 "/PSU/SW_3.3" +ZInfo 4C75CC96 239 "/PSU/SW_3.3" ZLayer 15 ZAux 4 F ZClearance 157 T ZMinThickness 39 -ZOptions 0 16 F 39 197 +ZOptions 0 16 S 39 197 ZCorner 65823 25014 0 ZCorner 65823 24285 0 ZCorner 63953 24285 0 @@ -38597,12 +39587,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75CDA9 105 "/PSU/VIN_DC-DC-1.2" +ZInfo 4C75CDA9 -1 "/PSU/VIN_DC-DC-1.2" ZLayer 15 ZAux 14 F ZClearance 39 T ZMinThickness 39 -ZOptions 0 16 F 39 79 +ZOptions 0 16 S 39 79 ZCorner 64362 27985 0 ZCorner 64362 27828 0 ZCorner 64370 27828 0 @@ -38705,12 +39695,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75CF67 106 "/PSU/VIN_DC-DC-3.3" +ZInfo 4C75CF67 -1 "/PSU/VIN_DC-DC-3.3" ZLayer 15 ZAux 9 F ZClearance 157 T ZMinThickness 100 -ZOptions 1 16 F 39 197 +ZOptions 1 16 S 39 197 ZCorner 64366 25986 0 ZCorner 64366 25470 0 ZCorner 63949 25470 0 @@ -38844,7 +39834,7 @@ ZLayer 15 ZAux 5 E ZClearance 59 T ZMinThickness 59 -ZOptions 1 16 F 79 79 +ZOptions 1 16 S 79 79 ZCorner 65685 26091 0 ZCorner 65685 25552 0 ZCorner 65673 25540 0 @@ -38896,12 +39886,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75DFA9 101 "/PSU/SW_1.2" +ZInfo 4C75DFA9 238 "/PSU/SW_1.2" ZLayer 15 ZAux 4 F ZClearance 157 T ZMinThickness 39 -ZOptions 0 16 F 39 197 +ZOptions 0 16 S 39 197 ZCorner 65720 27016 0 ZCorner 65720 26362 0 ZCorner 63894 26362 0 @@ -38992,12 +39982,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75E13A 118 "GND" +ZInfo 4C75E13A 256 "GND" ZLayer 0 ZAux 18 F ZClearance 98 T ZMinThickness 100 -ZOptions 1 16 F 39 197 +ZOptions 1 16 S 39 197 ZCorner 62665 28102 0 ZCorner 62720 28091 0 ZCorner 66091 28091 0 @@ -40039,12 +41029,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75FAF2 136 "VCCO2" +ZInfo 4C75FAF2 278 "VCCO2" ZLayer 4 ZAux 22 F ZClearance 59 T ZMinThickness 59 -ZOptions 1 16 F 79 79 +ZOptions 1 16 S 79 79 ZCorner 60594 38772 0 ZCorner 60594 38020 0 ZCorner 59642 38020 0 diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp index a582886..3eeb3b4 100644 --- a/kicad/xue-rnc/xue-rnc.cmp +++ b/kicad/xue-rnc/xue-rnc.cmp @@ -1,4 +1,4 @@ -Cmp-Mod V01 Created by CvPCB (2010-08-24 BZR 2457)-unstable date = Thu 26 Aug 2010 08:20:42 PM COT +Cmp-Mod V01 Created by CvPCB (2010-08-29 BZR 2460)-unstable date = Mon 30 Aug 2010 07:42:21 PM COT BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; @@ -267,217 +267,217 @@ IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656A80; +TimeStamp = /4C7BC2B2/4C656A80; Reference = C39; ValeurCmp = 100uF; IdModule = 1210; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656BF8; +TimeStamp = /4C7BC2B2/4C656BF8; Reference = C40; ValeurCmp = 100uF; IdModule = 1210; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656CB7; +TimeStamp = /4C7BC2B2/4C656CB7; Reference = C41; ValeurCmp = 100uF; IdModule = 1210; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656ABD; +TimeStamp = /4C7BC2B2/4C656ABD; Reference = C42; ValeurCmp = 4.7uF; IdModule = 0805; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656BF9; +TimeStamp = /4C7BC2B2/4C656BF9; Reference = C43; ValeurCmp = 4.7uF; IdModule = 0805; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656CB9; +TimeStamp = /4C7BC2B2/4C656CB9; Reference = C44; ValeurCmp = 4.7uF; IdModule = 0805; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656AC0; +TimeStamp = /4C7BC2B2/4C656AC0; Reference = C45; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656C16; +TimeStamp = /4C7BC2B2/4C656C16; Reference = C46; ValeurCmp = 4.7uF; IdModule = 0805; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656CBA; +TimeStamp = /4C7BC2B2/4C656CBA; Reference = C47; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656AC2; +TimeStamp = /4C7BC2B2/4C656AC2; Reference = C48; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656C24; +TimeStamp = /4C7BC2B2/4C656C24; Reference = C49; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656CBB; +TimeStamp = /4C7BC2B2/4C656CBB; Reference = C50; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656C27; +TimeStamp = /4C7BC2B2/4C656C27; Reference = C51; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656BFA; +TimeStamp = /4C7BC2B2/4C656BFA; Reference = C52; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656C49; +TimeStamp = /4C7BC2B2/4C656C49; Reference = C53; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D97; +TimeStamp = /4C7BC2B2/4C656D97; Reference = C54; ValeurCmp = 100uF; IdModule = 1210; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D43; +TimeStamp = /4C7BC2B2/4C656D43; Reference = C55; ValeurCmp = 100uF; IdModule = 1210; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656CF9; +TimeStamp = /4C7BC2B2/4C656CF9; Reference = C56; ValeurCmp = 100uF; IdModule = 1210; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D98; +TimeStamp = /4C7BC2B2/4C656D98; Reference = C57; ValeurCmp = 4.7uF; IdModule = 0805; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D44; +TimeStamp = /4C7BC2B2/4C656D44; Reference = C58; ValeurCmp = 4.7uF; IdModule = 0805; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656CFA; +TimeStamp = /4C7BC2B2/4C656CFA; Reference = C59; ValeurCmp = 4.7uF; IdModule = 0805; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D99; +TimeStamp = /4C7BC2B2/4C656D99; Reference = C60; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D45; +TimeStamp = /4C7BC2B2/4C656D45; Reference = C61; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656CFB; +TimeStamp = /4C7BC2B2/4C656CFB; Reference = C62; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D9A; +TimeStamp = /4C7BC2B2/4C656D9A; Reference = C63; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D46; +TimeStamp = /4C7BC2B2/4C656D46; Reference = C64; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656CFC; +TimeStamp = /4C7BC2B2/4C656CFC; Reference = C65; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D9D; +TimeStamp = /4C7BC2B2/4C656D9D; Reference = C66; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D49; +TimeStamp = /4C7BC2B2/4C656D49; Reference = C67; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D08; +TimeStamp = /4C7BC2B2/4C656D08; Reference = C68; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C656D53; +TimeStamp = /4C7BC2B2/4C656D53; Reference = C69; ValeurCmp = 470nF; IdModule = 0402; @@ -526,14 +526,14 @@ IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6B29A3; +TimeStamp = /4C7BC2B2/4C6B29A3; Reference = C76; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6B29DA; +TimeStamp = /4C7BC2B2/4C6B29DA; Reference = C77; ValeurCmp = 470nF; IdModule = 0402; @@ -596,40 +596,103 @@ IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C73D074; +TimeStamp = /4C7BC2B2/4C73D074; Reference = C90; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C73D252; +TimeStamp = /4C7BC2B2/4C73D252; Reference = C91; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C748EDB; +TimeStamp = /4C7BC2B2/4C748EDB; Reference = C92; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C748EDA; +TimeStamp = /4C7BC2B2/4C748EDA; Reference = C93; ValeurCmp = 470nF; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C749A0C; +TimeStamp = /4C7BC2B2/4C749A0C; Reference = C94; ValeurCmp = 470nF; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4C79C99E; +Reference = C95; +ValeurCmp = 4.7uF; +IdModule = 0805; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C79C8AE; +Reference = C96; +ValeurCmp = 22pF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C79C8AF; +Reference = C97; +ValeurCmp = 10uF; +IdModule = 1206; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C79C8B2; +Reference = C98; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C7C4D8E; +Reference = C99; +ValeurCmp = 22uF; +IdModule = 1206; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C7C4D94; +Reference = C100; +ValeurCmp = 220pF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C7C4CEC; +Reference = C101; +ValeurCmp = 22pF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C7C4CED; +Reference = C102; +ValeurCmp = 10uF; +IdModule = 1206; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C7C4CF1; +Reference = C103; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + BeginCmp TimeStamp = /4C5F1EDC/4C5F2B55; Reference = F1; @@ -728,6 +791,20 @@ ValeurCmp = 2.2uH; IdModule = 1210; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4C79C828; +Reference = L10; +ValeurCmp = 4.7uH; +IdModule = 1210; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C7C4CF0; +Reference = L11; +ValeurCmp = 2.2uH; +IdModule = 1210; +EndCmp + BeginCmp TimeStamp = /4C4320F3/4C5D7F39; Reference = R1; @@ -834,63 +911,63 @@ IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69DF7A; +TimeStamp = /4C7BC2A2/4C69DF7A; Reference = R16; ValeurCmp = 120; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69E7F8; +TimeStamp = /4C7BC2A2/4C69E7F8; Reference = R17; ValeurCmp = 33; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69E7C2; +TimeStamp = /4C7BC2A2/4C69E7C2; Reference = R18; ValeurCmp = 33; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69E7DD; +TimeStamp = /4C7BC2A2/4C69E7DD; Reference = R19; ValeurCmp = 33; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69E92D; +TimeStamp = /4C7BC2A2/4C69E92D; Reference = R20; ValeurCmp = 33; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6B1B90; +TimeStamp = /4C7BC2A2/4C6B1B90; Reference = R21; ValeurCmp = 120; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6B216D; +TimeStamp = /4C7BC2A2/4C6B216D; Reference = R22; ValeurCmp = 33; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6B216E; +TimeStamp = /4C7BC2A2/4C6B216E; Reference = R23; ValeurCmp = 33; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6B216B; +TimeStamp = /4C7BC2A2/4C6B216B; Reference = R24; ValeurCmp = 33; IdModule = 0402; @@ -899,40 +976,40 @@ EndCmp BeginCmp TimeStamp = /4C69ED5F/4C6D2DBC; Reference = R25; -ValeurCmp = R; +ValeurCmp = 200K; IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C69ED5F/4C6D2DDD; Reference = R26; -ValeurCmp = R; +ValeurCmp = 900K; IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C69ED5F/4C6D2FD3; Reference = R27; -ValeurCmp = R; +ValeurCmp = 200K; IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C69ED5F/4C6D2FD2; Reference = R28; -ValeurCmp = R; +ValeurCmp = 200K; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C716877; +TimeStamp = /4C7BC2B2/4C716877; Reference = R29; ValeurCmp = 4.7k; IdModule = 0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C7168DD; +TimeStamp = /4C7BC2B2/4C7168DD; Reference = R30; ValeurCmp = 330; IdModule = 0402; @@ -967,133 +1044,196 @@ IdModule = 1206; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69C6B2; +TimeStamp = /4C69ED5F/4C79C99C; +Reference = R35; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C79C99B; +Reference = R36; +ValeurCmp = R; +IdModule = 1206; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C79C7C0; +Reference = R37; +ValeurCmp = 1M; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C79C8B0; +Reference = R38; +ValeurCmp = 332K; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C79C8B1; +Reference = R39; +ValeurCmp = 1.02M; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C7C4D9E; +Reference = R40; +ValeurCmp = 47K; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C7C4DAA; +Reference = R41; +ValeurCmp = 160K; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C7C4CEE; +Reference = R42; +ValeurCmp = 24K; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C7C4CEF; +Reference = R43; +ValeurCmp = 51K; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C7BC2A2/4C69C6B2; Reference = RP1; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69CEE8; +TimeStamp = /4C7BC2A2/4C69CEE8; Reference = RP2; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69D3A4; +TimeStamp = /4C7BC2A2/4C69D3A4; Reference = RP3; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69D3A3; +TimeStamp = /4C7BC2A2/4C69D3A3; Reference = RP4; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69D3A9; +TimeStamp = /4C7BC2A2/4C69D3A9; Reference = RP5; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69DA8A; +TimeStamp = /4C7BC2A2/4C69DA8A; Reference = RP6; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69DC05; +TimeStamp = /4C7BC2A2/4C69DC05; Reference = RP7; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69E299; +TimeStamp = /4C7BC2A2/4C69E299; Reference = RP8; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69E3A6; +TimeStamp = /4C7BC2A2/4C69E3A6; Reference = RP9; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69FC19; +TimeStamp = /4C7BC2A2/4C69FC19; Reference = RP10; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69FCE6; +TimeStamp = /4C7BC2A2/4C69FCE6; Reference = RP11; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69FCE8; +TimeStamp = /4C7BC2A2/4C69FCE8; Reference = RP12; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C69FCE7; +TimeStamp = /4C7BC2A2/4C69FCE7; Reference = RP13; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6A0D58; +TimeStamp = /4C7BC2A2/4C6A0D58; Reference = RP14; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6A0D57; +TimeStamp = /4C7BC2A2/4C6A0D57; Reference = RP15; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6A0D56; +TimeStamp = /4C7BC2A2/4C6A0D56; Reference = RP16; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6A0D55; +TimeStamp = /4C7BC2A2/4C6A0D55; Reference = RP17; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C6A0D54; +TimeStamp = /4C7BC2A2/4C6A0D54; Reference = RP18; ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp BeginCmp -TimeStamp = /4C431A63/4C431E53; +TimeStamp = /4C7BC2B2/4C431E53; Reference = U1; ValeurCmp = XC6SLX45FGG484; IdModule = FGG484BGA-P10; @@ -1190,6 +1330,20 @@ ValeurCmp = FAN4010; IdModule = MLP6; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4C79C65B; +Reference = U15; +ValeurCmp = A7117; +IdModule = SOT23_6; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C79C99A; +Reference = U16; +ValeurCmp = FAN4010; +IdModule = MLP6; +EndCmp + BeginCmp TimeStamp = /4C5F1EDC/4C5F2CA7; Reference = V1; diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 7e65150..b49b1ba 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,197 +1,897 @@ -# EESchema Netlist Version 1.1 created Mon 30 Aug 2010 10:27:30 AM COT +# EESchema Netlist Version 1.1 created Mon 30 Aug 2010 07:42:21 PM COT ( - ( /4C7BC2B2/4C749A0C 0402 C94 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7F9F 0603 C1 1uF + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C748EDB 0402 C92 470nF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) + ( /4C4320F3/4C5D80ED 0402 C2 1uF + ( 1 +1.8V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C748EDA 0402 C93 470nF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) + ( /4C4320F3/4C5D7FA1 0402 C3 100nF + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C73D252 0402 C91 470nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) + ( /4C4320F3/4C5D80F0 0402 C4 100nF + ( 1 +1.8V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C73D074 0402 C90 470nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) + ( /4C4320F3/4C5D7FA3 0402 C5 100nF + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C7168DD 0402 R30 330 {Lib=R} - ( 1 +3.3V ) - ( 2 N-000359 ) + ( /4C4320F3/4C5D8104 0402 C6 100nF + ( 1 /Etherne1 ) + ( 2 GND ) ) - ( /4C7BC2B2/4C716877 0402 R29 4.7k {Lib=R} - ( 1 +3.3V ) - ( 2 N-000357 ) + ( /4C4320F3/4C5D7FA5 0603 C7 1uF + ( 1 /Etherne2 ) + ( 2 GND ) ) - ( /4C7BC2B2/4C6B29DA 0402 C77 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7FA7 0402 C8 100nF + ( 1 /Etherne2 ) + ( 2 GND ) ) - ( /4C7BC2B2/4C6B29A3 0402 C76 470nF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) + ( /4C4320F3/4C5D8114 0402 C9 100nF + ( 1 /Etherne3 ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656D9D $noname C66 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7E41 0402 C10 100nF + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656D9A $noname C63 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7E43 0402 C11 100nF + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656D99 $noname C60 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7DCB 0402 C12 47nF + ( 1 /Etherne4 ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656D98 $noname C57 4.7uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2033 0603 C13 1uF + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656D97 $noname C54 100uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2037 0402 C14 100nF + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656D53 $noname C69 470nF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2039 0402 C15 100nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656D49 $noname C67 470nF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2D1E 0402 C16 4.7nF + ( 1 N-000130 ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656D46 $noname C64 470nF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) + ( /4C421DD3/4C61CC73 0402 C17 100nF + ( 1 +2.5V ) + ( 2 /DDR_Ban5 ) ) - ( /4C7BC2B2/4C656D45 $noname C61 470nF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) + ( /4C421DD3/4C61CC96 0402 C18 100nF + ( 1 /DDR_Ban5 ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656D44 $noname C58 4.7uF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) + ( /4C421DD3/4C61CCE3 0402 C19 100nF + ( 1 +2.5V ) + ( 2 /DDR_Ban6 ) ) - ( /4C7BC2B2/4C656D43 $noname C55 100uF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) + ( /4C421DD3/4C61CCE2 0402 C20 100nF + ( 1 /DDR_Ban6 ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656D08 $noname C68 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C421DD3/4C61CF2F 0603 C21 1uF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656CFC $noname C65 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C421DD3/4C61CEB9 0402 C22 100nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656CFB $noname C62 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C421DD3/4C61CEF7 0402 C23 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656CFA $noname C59 4.7uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C421DD3/4C61CF17 0402 C24 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656CF9 $noname C56 100uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C421DD3/4C61CF16 0402 C25 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656CBB $noname C50 470nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CF27 0402 C26 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656CBA $noname C47 470nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CFA0 0603 C27 1uF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656CB9 $noname C44 4.7uF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CFA5 0402 C28 100nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656CB7 $noname C41 100uF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CFA4 0402 C29 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656C49 $noname C53 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C421DD3/4C61CFA2 0402 C30 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656C27 $noname C51 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C421DD3/4C61CFA3 0402 C31 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656C24 $noname C49 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C421DD3/4C61CFA1 0402 C32 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656C16 $noname C46 4.7uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C421DD3/4C61D151 1206 C33 10uF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656BFA $noname C52 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C421DD3/4C61D1D4 1206 C34 10uF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656BF9 $noname C43 4.7uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C5F1EDC/4C6552BE 0603 C35 1uF + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656BF8 $noname C40 100uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C5F1EDC/4C6552BD 0402 C36 100nF + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656AC2 $noname C48 470nF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) + ( /4C5F1EDC/4C6552BC 0402 C37 100nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656AC0 $noname C45 470nF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B7 0402 C38 4.7nF + ( 1 N-000132 ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656ABD $noname C42 4.7uF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) + ( /4C7BC2B2/4C656A80 1210 C39 100uF + ( 1 +1.2V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C656A80 $noname C39 100uF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) + ( /4C7BC2B2/4C656BF8 1210 C40 100uF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C7BC2B2/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} - ( A1 GND ) - ( A2 ? ) - ( A3 ? ) - ( A4 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK ) - ( A5 /Ethernet_Phy/ETH_RXD1 ) - ( A6 /Ethernet_Phy/ETH_RXDV ) - ( A7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC ) - ( A8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3 ) - ( A9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_COL ) - ( A10 /Ethernet_Phy/ETH_INT ) - ( A11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D6 ) - ( A12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D4 ) - ( A13 /Non_volatile_memories/NF_D2 ) - ( A14 /Non_volatile_memories/NF_ALE ) - ( A15 /Non_volatile_memories/NF_RNB ) - ( A16 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2 ) - ( A17 /Non_volatile_memories/SD_CLK ) - ( A18 /Non_volatile_memories/SD_DAT0 ) - ( A19 /DBG_PRG/FPGA_TDO ) - ( A20 /FPGA_Port_1,_Port_3_(DDR,_USB)/USBD_RCV ) - ( A21 /USB/USBD_OE_N ) - ( A22 GND ) - ( AA1 N-000357 ) - ( AA2 ? ) - ( AA3 VCCO2 ) - ( AA4 ? ) - ( AA5 GND ) - ( AA6 ? ) - ( AA7 VCCO2 ) - ( AA8 ? ) - ( AA9 GND ) + ( /4C7BC2B2/4C656CB7 1210 C41 100uF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656ABD 0805 C42 4.7uF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656BF9 0805 C43 4.7uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656CB9 0805 C44 4.7uF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656AC0 0402 C45 470nF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656C16 0805 C46 4.7uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656CBA 0402 C47 470nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656AC2 0402 C48 470nF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656C24 0402 C49 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656CBB 0402 C50 470nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656C27 0402 C51 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656BFA 0402 C52 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656C49 0402 C53 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D97 1210 C54 100uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D43 1210 C55 100uF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656CF9 1210 C56 100uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D98 0805 C57 4.7uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D44 0805 C58 4.7uF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656CFA 0805 C59 4.7uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D99 0402 C60 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D45 0402 C61 470nF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656CFB 0402 C62 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D9A 0402 C63 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D46 0402 C64 470nF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656CFC 0402 C65 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D9D 0402 C66 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D49 0402 C67 470nF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D08 0402 C68 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C656D53 0402 C69 470nF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C421DD3/4C65D2A9 0402 C70 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C65D28E 0402 C71 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65D661 0402 C72 100nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65D67C 0402 C73 100nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65D681 0603 C74 1uF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C6969AB 0402 C75 100nF + ( 1 GND ) + ( 2 +3.3V ) + ) + ( /4C7BC2B2/4C6B29A3 0402 C76 470nF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C6B29DA 0402 C77 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2C7C 0805 C78 4.7uF + ( 1 /PSU/VIN7 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2C7F 0402 C79 22pF + ( 1 +3.3V ) + ( 2 /PSU/VFB3.3 ) + ) + ( /4C69ED5F/4C6D2C83 1206 C80 10uF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2F0B 0402 C81 100nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2FD7 0805 C82 4.7uF + ( 1 /PSU/VIN8 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2FD6 0402 C83 22pF + ( 1 +1.2V ) + ( 2 /PSU/VFB1.2 ) + ) + ( /4C69ED5F/4C6D2FD5 1206 C84 10uF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2FD0 0402 C85 100nF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C73D074 0402 C90 470nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C73D252 0402 C91 470nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C748EDB 0402 C92 470nF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C748EDA 0402 C93 470nF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C7BC2B2/4C749A0C 0402 C94 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C79C99E 0805 C95 4.7uF + ( 1 /PSU/VIN9 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C79C8AE 0402 C96 22pF + ( 1 +5V ) + ( 2 /PSU/VFB1.2 ) + ) + ( /4C69ED5F/4C79C8AF 1206 C97 10uF + ( 1 +5V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C79C8B2 0402 C98 100nF + ( 1 +5V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C7C4D8E 1206 C99 22uF + ( 1 N-000156 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C7C4D94 0402 C100 220pF + ( 1 N-000147 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C7C4CEC 0402 C101 22pF + ( 1 +2.5V ) + ( 2 /PSU/VFB2.5 ) + ) + ( /4C69ED5F/4C7C4CED 1206 C102 10uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C7C4CF1 0402 C103 100nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2B55 1210 F1 MICROSMD075F + ( 1 N-000134 ) + ( 2 +5V ) + ) + ( /4C4227FE/4B76F5E2 MICROSD-500901 J1 MICROSD + ( 1 /Non_vol10 ) + ( 2 /Non_vol11 ) + ( 3 /Non_vol12 ) + ( 4 +3.3V ) + ( 5 /Non_vol13 ) + ( 6 GND ) + ( 7 /FPGA,_P14 ) + ( 8 /FPGA,_P15 ) + ( CASE GND ) + ( CD ? ) + ( COM GND ) + ) + ( /4C4320F3/4C5D6F5A SD-48025 J4 RJ45-48025 + ( 1 /Etherne16 ) + ( 2 /Etherne17 ) + ( 3 +3.3V ) + ( 4 GND ) + ( 5 GND ) + ( 6 +3.3V ) + ( 7 /Etherne18 ) + ( 8 /Etherne19 ) + ( 9 +3.3V ) + ( 10 N-000117 ) + ( 11 +3.3V ) + ( 12 N-000118 ) + ( 13 /Etherne4 ) + ( 14 /Etherne4 ) + ) + ( /4C5F1EDC/4C5F23DD USB-48204 J5 USB-48204-0001 + ( 1 N-000135 ) + ( 2 /USB/USBA_D- ) + ( 3 /USB/USBA_D+ ) + ( 4 N-000131 ) + ( S1 N-000130 ) + ( S2 N-000130 ) + ( S3 N-000130 ) + ( S4 N-000130 ) + ) + ( /4C716A4D/4C716CAB pin_array_8x2 J6 CONN_8X2 + ( 1 /DBG_PRG20 ) + ( 2 ? ) + ( 3 /DBG_PRG21 ) + ( 4 ? ) + ( 5 /DBG_PRG22 ) + ( 6 ? ) + ( 7 /DBG_PRG23 ) + ( 8 ? ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 ? ) + ( 13 ? ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ) + ( /4C5F1EDC/4C75F027 ZX62D-B-5P8 J7 ZX62D-B-5P8 + ( 1 N-000137 ) + ( 2 /USB/USBD_D- ) + ( 3 /USB/USBD_D+ ) + ( 4 N-000136 ) + ( 5 N-000136 ) + ( 6 N-000132 ) + ( 7 N-000132 ) + ( 8 N-000132 ) + ( 9 N-000132 ) + ) + ( /4C4320F3/4C5D80F3 0402 L1 FB + ( 1 +1.8V ) + ( 2 /Etherne1 ) + ) + ( /4C4320F3/4C5D7FB7 0603 L2 FB + ( 1 +3.3V ) + ( 2 /Etherne2 ) + ) + ( /4C4320F3/4C5D810A 0402 L3 FB + ( 1 /Etherne1 ) + ( 2 /Etherne3 ) + ) + ( /4C5F1EDC/4C63F252 0603 L4 FB + ( 1 N-000134 ) + ( 2 N-000135 ) + ) + ( /4C5F1EDC/4C63F248 0603 L5 FB + ( 1 N-000131 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C6552B1 0603 L7 FB + ( 1 N-000137 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2E6A 1210 L8 2.2uH + ( 1 +3.3V ) + ( 2 /PSU/SW_3.3 ) + ) + ( /4C69ED5F/4C6D2FD1 1210 L9 2.2uH + ( 1 +1.2V ) + ( 2 /PSU/SW_1.2 ) + ) + ( /4C69ED5F/4C79C828 1210 L10 4.7uH + ( 1 N-000151 ) + ( 2 /PSU/VIN9 ) + ) + ( /4C69ED5F/4C7C4CF0 1210 L11 2.2uH + ( 1 +2.5V ) + ( 2 /PSU/SW_1.2 ) + ) + ( /4C4320F3/4C5D7F39 0402 R1 4.7K + ( 1 /FPGA,_P24 ) + ( 2 +3.3V ) + ) + ( /4C4320F3/4C5D7ECF 0402 R2 6.65K + ( 1 N-000123 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7AFE 0402 R3 49.9 + ( 1 +3.3V ) + ( 2 /Etherne16 ) + ) + ( /4C4320F3/4C5D7AFC 0402 R4 49.9 + ( 1 +3.3V ) + ( 2 /Etherne17 ) + ) + ( /4C4320F3/4C5D7AF7 0402 R5 49.9 + ( 1 +3.3V ) + ( 2 /Etherne18 ) + ) + ( /4C4320F3/4C5D7AF9 0402 R6 49.9 + ( 1 +3.3V ) + ( 2 /Etherne19 ) + ) + ( /4C4320F3/4C5D719D 0402 R7 220 + ( 1 N-000117 ) + ( 2 /Etherne25 ) + ) + ( /4C4320F3/4C5D71DB 0402 R8 220 + ( 1 N-000118 ) + ( 2 /Etherne26 ) + ) + ( /4C4320F3/4C5D7DC4 0402 R9 1M + ( 1 /Etherne4 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2D27 0402 R10 1M + ( 1 N-000130 ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CD4A 0402 R11 1K_1% + ( 1 +2.5V ) + ( 2 /DDR_Ban5 ) + ) + ( /4C421DD3/4C61CDB5 0402 R12 1K_1% + ( 1 /DDR_Ban5 ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CE31 0402 R13 1K_1% + ( 1 +2.5V ) + ( 2 /DDR_Ban6 ) + ) + ( /4C421DD3/4C61CE30 0402 R14 1K_1% + ( 1 /DDR_Ban6 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C6552B6 0402 R15 1M + ( 1 N-000132 ) + ( 2 GND ) + ) + ( /4C7BC2A2/4C69DF7A 0402 R16 120 + ( 1 /DDR_Ban27 ) + ( 2 /FPGA_Po28 ) + ) + ( /4C7BC2A2/4C69E7F8 0402 R17 33 + ( 1 /FPGA_Po29 ) + ( 2 /FPGA_Po30 ) + ) + ( /4C7BC2A2/4C69E7C2 0402 R18 33 + ( 1 /FPGA_Po31 ) + ( 2 /DDR_Ban32 ) + ) + ( /4C7BC2A2/4C69E7DD 0402 R19 33 + ( 1 /FPGA_Po33 ) + ( 2 /DDR_Ban34 ) + ) + ( /4C7BC2A2/4C69E92D 0402 R20 33 + ( 1 /FPGA_Po35 ) + ( 2 /DDR_Ban36 ) + ) + ( /4C7BC2A2/4C6B1B90 0402 R21 120 + ( 1 /FPGA_Po37 ) + ( 2 /FPGA_Po38 ) + ) + ( /4C7BC2A2/4C6B216D 0402 R22 33 + ( 1 /FPGA_Po39 ) + ( 2 /DDR_Ban40 ) + ) + ( /4C7BC2A2/4C6B216E 0402 R23 33 + ( 1 /FPGA_Po41 ) + ( 2 /FPGA_Po42 ) + ) + ( /4C7BC2A2/4C6B216B 0402 R24 33 + ( 1 /FPGA_Po43 ) + ( 2 /DDR_Ban44 ) + ) + ( /4C69ED5F/4C6D2DBC 0402 R25 200K + ( 1 /PSU/VFB3.3 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2DDD 0402 R26 900K + ( 1 +3.3V ) + ( 2 /PSU/VFB3.3 ) + ) + ( /4C69ED5F/4C6D2FD3 0402 R27 200K + ( 1 /PSU/VFB1.2 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2FD2 0402 R28 200K + ( 1 +1.2V ) + ( 2 /PSU/VFB1.2 ) + ) + ( /4C7BC2B2/4C716877 0402 R29 4.7k + ( 1 +3.3V ) + ( 2 N-000354 ) + ) + ( /4C7BC2B2/4C7168DD 0402 R30 330 + ( 1 +3.3V ) + ( 2 N-000356 ) + ) + ( /4C69ED5F/4C77067B 0402 R31 R + ( 1 /PSU/Iout_3.3 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C77060E 1206 R32 R + ( 1 /PSU/VIN7 ) + ( 2 N-000143 ) + ) + ( /4C69ED5F/4C770712 0402 R33 R + ( 1 /PSU/Iout_1.2 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C770713 1206 R34 R + ( 1 /PSU/VIN8 ) + ( 2 N-000160 ) + ) + ( /4C69ED5F/4C79C99C 0402 R35 R + ( 1 /PSU/Iout_5.0 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C79C99B 1206 R36 R + ( 1 /PSU/VIN9 ) + ( 2 N-000144 ) + ) + ( /4C69ED5F/4C79C7C0 0402 R37 1M + ( 1 N-000157 ) + ( 2 /PSU/VIN9 ) + ) + ( /4C69ED5F/4C79C8B0 0402 R38 332K + ( 1 /PSU/VFB1.2 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C79C8B1 0402 R39 1.02M + ( 1 +5V ) + ( 2 /PSU/VFB1.2 ) + ) + ( /4C69ED5F/4C7C4D9E 0402 R40 47K + ( 1 N-000150 ) + ( 2 N-000147 ) + ) + ( /4C69ED5F/4C7C4DAA 0402 R41 160K + ( 1 N-000148 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C7C4CEE 0402 R42 24K + ( 1 /PSU/VFB2.5 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C7C4CEF 0402 R43 51K + ( 1 +2.5V ) + ( 2 /PSU/VFB2.5 ) + ) + ( /4C7BC2A2/4C69C6B2 R_PACK4-0402 RP1 R_PACK4 + ( 1 /FPGA_Po45 ) + ( 2 /FPGA_Po46 ) + ( 3 /FPGA_Po47 ) + ( 4 /FPGA_Po48 ) + ( 5 /DDR_Banks/M1_A3 ) + ( 6 /FPGA_Po49 ) + ( 7 /DDR_Banks/M1_A1 ) + ( 8 /DDR_Banks/M1_A0 ) + ) + ( /4C7BC2A2/4C69CEE8 R_PACK4-0402 RP2 R_PACK4 + ( 1 /FPGA_Po50 ) + ( 2 /FPGA_Po51 ) + ( 3 /FPGA_Po52 ) + ( 4 /FPGA_Po53 ) + ( 5 /FPGA_Po54 ) + ( 6 /FPGA_Po55 ) + ( 7 /DDR_Ban56 ) + ( 8 /DDR_Ban57 ) + ) + ( /4C7BC2A2/4C69D3A4 R_PACK4-0402 RP3 R_PACK4 + ( 1 /FPGA_Po58 ) + ( 2 /FPGA_Po59 ) + ( 3 /FPGA_Po60 ) + ( 4 /FPGA_Po61 ) + ( 5 /DDR_Ban62 ) + ( 6 /FPGA_Po63 ) + ( 7 /FPGA_Po64 ) + ( 8 /DDR_Ban65 ) + ) + ( /4C7BC2A2/4C69D3A3 R_PACK4-0402 RP4 R_PACK4 + ( 1 /FPGA_Po66 ) + ( 2 /FPGA_Po67 ) + ( 3 /FPGA_Po68 ) + ( 4 /FPGA_Po69 ) + ( 5 /DDR_Ban70 ) + ( 6 /FPGA_Po71 ) + ( 7 /FPGA_Po72 ) + ( 8 /FPGA_Po73 ) + ) + ( /4C7BC2A2/4C69D3A9 R_PACK4-0402 RP5 R_PACK4 + ( 1 /FPGA_Po74 ) + ( 2 /FPGA_Po75 ) + ( 3 /FPGA_Po76 ) + ( 4 /FPGA_Po77 ) + ( 5 /FPGA_Po78 ) + ( 6 /FPGA_Po79 ) + ( 7 /FPGA_Po80 ) + ( 8 /FPGA_Po81 ) + ) + ( /4C7BC2A2/4C69DA8A R_PACK4-0402 RP6 R_PACK4 + ( 1 /DDR_Banks/M1_A7 ) + ( 2 /FPGA_Po82 ) + ( 3 /DDR_Banks/M1_A5 ) + ( 4 /FPGA_Po83 ) + ( 5 /FPGA_Po84 ) + ( 6 /FPGA_Po85 ) + ( 7 /FPGA_Po86 ) + ( 8 /FPGA_Po87 ) + ) + ( /4C7BC2A2/4C69DC05 R_PACK4-0402 RP7 R_PACK4 + ( 1 /DDR_Ban88 ) + ( 2 /FPGA_Po89 ) + ( 3 /DDR_Banks/M1_A9 ) + ( 4 /DDR_Banks/M1_A8 ) + ( 5 /FPGA_Po90 ) + ( 6 /FPGA_Po91 ) + ( 7 /FPGA_Po92 ) + ( 8 /FPGA_Po93 ) + ) + ( /4C7BC2A2/4C69E299 R_PACK4-0402 RP8 R_PACK4 + ( 1 /FPGA_Po94 ) + ( 2 /DDR_Ban95 ) + ( 3 /FPGA_Po96 ) + ( 4 /FPGA_Po97 ) + ( 5 /FPGA_Po98 ) + ( 6 /FPGA_Po99 ) + ( 7 /FPGA_Po100 ) + ( 8 /FPGA_Po101 ) + ) + ( /4C7BC2A2/4C69E3A6 R_PACK4-0402 RP9 R_PACK4 + ( 1 /FPGA_Po102 ) + ( 2 /FPGA_Po103 ) + ( 3 /FPGA_Po104 ) + ( 4 /FPGA_Po105 ) + ( 5 /FPGA_Po106 ) + ( 6 /FPGA_Po107 ) + ( 7 /FPGA_Po108 ) + ( 8 /FPGA_Po109 ) + ) + ( /4C7BC2A2/4C69FC19 R_PACK4-0402 RP10 R_PACK4 + ( 1 /FPGA_Po110 ) + ( 2 /FPGA_Po111 ) + ( 3 /FPGA_Po112 ) + ( 4 /FPGA_Po113 ) + ( 5 /DDR_Ban114 ) + ( 6 /FPGA_Po115 ) + ( 7 /DDR_Ban116 ) + ( 8 /DDR_Ban117 ) + ) + ( /4C7BC2A2/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 + ( 1 /FPGA_Po118 ) + ( 2 /FPGA_Po119 ) + ( 3 /FPGA_Po120 ) + ( 4 /FPGA_Po121 ) + ( 5 /FPGA_Po122 ) + ( 6 /FPGA_Po123 ) + ( 7 /FPGA_Po124 ) + ( 8 /DDR_Ban125 ) + ) + ( /4C7BC2A2/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 + ( 1 /FPGA_Po126 ) + ( 2 /FPGA_Po127 ) + ( 3 /FPGA_Po128 ) + ( 4 /FPGA_Po129 ) + ( 5 /DDR_Ban130 ) + ( 6 /DDR_Ban131 ) + ( 7 /FPGA_Po132 ) + ( 8 /FPGA_Po133 ) + ) + ( /4C7BC2A2/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 + ( 1 /FPGA_Po134 ) + ( 2 /FPGA_Po135 ) + ( 3 /FPGA_Po136 ) + ( 4 /FPGA_Po137 ) + ( 5 /DDR_Ban138 ) + ( 6 /FPGA_Po139 ) + ( 7 /FPGA_Po140 ) + ( 8 /FPGA_Po141 ) + ) + ( /4C7BC2A2/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 + ( 1 /FPGA_Po142 ) + ( 2 /FPGA_Po143 ) + ( 3 /FPGA_Po144 ) + ( 4 /FPGA_Po145 ) + ( 5 /FPGA_Po146 ) + ( 6 /FPGA_Po147 ) + ( 7 /FPGA_Po148 ) + ( 8 /FPGA_Po149 ) + ) + ( /4C7BC2A2/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 + ( 1 /FPGA_Po150 ) + ( 2 /FPGA_Po151 ) + ( 3 /FPGA_Po152 ) + ( 4 /FPGA_Po153 ) + ( 5 /FPGA_Po154 ) + ( 6 /FPGA_Po155 ) + ( 7 /DDR_Ban156 ) + ( 8 /DDR_Ban157 ) + ) + ( /4C7BC2A2/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 + ( 1 /FPGA_Po158 ) + ( 2 /FPGA_Po159 ) + ( 3 /FPGA_Po160 ) + ( 4 /FPGA_Po161 ) + ( 5 /FPGA_Po162 ) + ( 6 /DDR_Ban163 ) + ( 7 /FPGA_Po164 ) + ( 8 /DDR_Ban165 ) + ) + ( /4C7BC2A2/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 + ( 1 /FPGA_Po166 ) + ( 2 /FPGA_Po167 ) + ( 3 /FPGA_Po168 ) + ( 4 /FPGA_Po169 ) + ( 5 /DDR_Banks/M0_A4 ) + ( 6 /FPGA_Po170 ) + ( 7 /FPGA_Po171 ) + ( 8 /DDR_Banks/M0_A7 ) + ) + ( /4C7BC2A2/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 + ( 1 /FPGA_Po172 ) + ( 2 /FPGA_Po173 ) + ( 3 /FPGA_Po174 ) + ( 4 /FPGA_Po175 ) + ( 5 /FPGA_Po176 ) + ( 6 /FPGA_Po177 ) + ( 7 /FPGA_Po178 ) + ( 8 /FPGA_Po179 ) + ) + ( /4C7BC2B2/4C431E53 FGG484BGA-P10 U1 XC6SLX45FGG484 + ( A1 GND ) + ( A2 ? ) + ( A3 ? ) + ( A4 /Etherne180 ) + ( A5 /Etherne181 ) + ( A6 /FPGA,_P182 ) + ( A7 /Etherne183 ) + ( A8 /FPGA,_P184 ) + ( A9 /Etherne185 ) + ( A10 /FPGA,_P186 ) + ( A11 /FPGA,_P187 ) + ( A12 /FPGA,_P188 ) + ( A13 /FPGA,_P189 ) + ( A14 /FPGA,_P190 ) + ( A15 /FPGA,_P191 ) + ( A16 /Non_vol10 ) + ( A17 /Non_vol13 ) + ( A18 /FPGA,_P14 ) + ( A19 /DBG_PRG22 ) + ( A20 /USB/USBD_RCV ) + ( A21 /USB/USBD_OE_N ) + ( A22 GND ) + ( AA1 N-000354 ) + ( AA2 ? ) + ( AA3 VCCO2 ) + ( AA4 ? ) + ( AA5 GND ) + ( AA6 ? ) + ( AA7 VCCO2 ) + ( AA8 ? ) + ( AA9 GND ) ( AA10 ? ) ( AA11 VCCO2 ) ( AA12 ? ) @@ -202,18 +902,18 @@ ( AA17 GND ) ( AA18 ? ) ( AA19 VCCO2 ) - ( AA20 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1 ) - ( AA21 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK ) + ( AA20 /FPGA,_P192 ) + ( AA21 /FPGA,_P193 ) ( AA22 ? ) - ( AB1 GND ) - ( AB2 ? ) - ( AB3 ? ) - ( AB4 ? ) - ( AB5 ? ) - ( AB6 ? ) - ( AB7 ? ) - ( AB8 ? ) - ( AB9 ? ) + ( AB1 GND ) + ( AB2 ? ) + ( AB3 ? ) + ( AB4 ? ) + ( AB5 ? ) + ( AB6 ? ) + ( AB7 ? ) + ( AB8 ? ) + ( AB9 ? ) ( AB10 ? ) ( AB11 ? ) ( AB12 ? ) @@ -224,1870 +924,966 @@ ( AB17 ? ) ( AB18 ? ) ( AB19 ? ) - ( AB20 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0 ) + ( AB20 /FPGA,_P194 ) ( AB21 ? ) ( AB22 GND ) - ( B1 ? ) - ( B2 ? ) - ( B3 ? ) - ( B4 +3.3V ) - ( B5 GND ) - ( B6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 ) - ( B7 +3.3V ) - ( B8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER ) - ( B9 GND ) - ( B10 /Ethernet_Phy/ETH_CRS ) - ( B11 +3.3V ) - ( B12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D3 ) - ( B13 GND ) - ( B14 /Non_volatile_memories/NF_CLE ) - ( B15 +3.3V ) - ( B16 /Non_volatile_memories/SD_DAT3 ) - ( B17 GND ) - ( B18 /Non_volatile_memories/SD_DAT1 ) - ( B19 +3.3V ) - ( B20 /USB/USBD_SPD ) - ( B21 /USB/USBD_VP ) - ( B22 /FPGA_Port_1,_Port_3_(DDR,_USB)/USBD_VM ) - ( C1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A11 ) - ( C2 +2.5V ) - ( C3 ? ) - ( C4 ? ) - ( C5 /Ethernet_Phy/ETH_RXD3 ) - ( C6 /Ethernet_Phy/ETH_RXD2 ) - ( C7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N ) - ( C8 /Ethernet_Phy/ETH_TXC ) - ( C9 /Ethernet_Phy/ETH_TXD1 ) - ( C10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2 ) - ( C11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 ) - ( C12 /Non_volatile_memories/NF_D0 ) - ( C13 ? ) - ( C14 /Non_volatile_memories/NF_WE_N ) - ( C15 /FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N ) - ( C16 /FPGA,_Port0,_Port2,_PROG_IF/SD_CMD ) - ( C17 ? ) - ( C18 /DBG_PRG/FPGA_TMS ) - ( C19 /USB/USBA_OE_N ) - ( C20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A8 ) - ( C21 +2.5V ) - ( C22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A9 ) - ( D1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A12 ) - ( D2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_CKE ) - ( D3 ? ) - ( D4 GND ) - ( D5 ? ) - ( D6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO ) - ( D7 /Ethernet_Phy/ETH_MDC ) - ( D8 /Ethernet_Phy/ETH_TXER ) - ( D9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN ) - ( D10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 ) - ( D11 /Non_volatile_memories/NF_D7 ) - ( D12 ? ) - ( D13 ? ) - ( D14 /Non_volatile_memories/NF_D1 ) - ( D15 /Non_volatile_memories/NF_CS1_N ) - ( D16 +2.5V ) - ( D17 ? ) - ( D18 GND ) - ( D19 /FPGA_Port_1,_Port_3_(DDR,_USB)/USBA_VP ) - ( D20 /USB/USBA_VM ) - ( D21 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_CKE ) - ( D22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A12 ) - ( E1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A9 ) - ( E2 GND ) - ( E3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A8 ) - ( E4 ? ) - ( E5 ? ) - ( E6 ? ) - ( E7 GND ) - ( E8 ? ) - ( E9 +3.3V ) - ( E10 ? ) - ( E11 GND ) - ( E12 ? ) - ( E13 +3.3V ) - ( E14 ? ) - ( E15 GND ) - ( E16 ? ) - ( E17 +3.3V ) - ( E18 /DBG_PRG/FPGA_TDI ) - ( E19 +2.5V ) - ( E20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A7 ) - ( E21 GND ) - ( E22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A2 ) - ( F1 ? ) - ( F2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_WE# ) - ( F3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A4 ) - ( F4 +2.5V ) - ( F5 ? ) - ( F6 +2.5V ) - ( F7 ? ) - ( F8 ? ) - ( F9 ? ) - ( F10 ? ) - ( F11 +2.5V ) - ( F12 ? ) - ( F13 ? ) - ( F14 ? ) - ( F15 ? ) - ( F16 /USB/USBA_SPD ) - ( F17 /FPGA_Port_1,_Port_3_(DDR,_USB)/USBA_RCV ) - ( F18 ? ) - ( F19 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A11 ) - ( F20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A4 ) - ( F21 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A0 ) - ( F22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A1 ) - ( G1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_BA1 ) - ( G2 +2.5V ) - ( G3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_BA0 ) - ( G4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A10 ) - ( G5 GND ) - ( G6 ? ) - ( G7 ? ) - ( G8 ? ) - ( G9 ? ) - ( G10 +3.3V ) - ( G11 ? ) - ( G12 +2.5V ) - ( G13 ? ) - ( G14 +3.3V ) - ( G15 /DBG_PRG/FPGA_TCK ) - ( G16 ? ) - ( G17 ? ) - ( G18 GND ) - ( G19 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A10 ) - ( G20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A3 ) - ( G21 +2.5V ) - ( G22 ? ) - ( H1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A1 ) - ( H2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A0 ) - ( H3 /DDR_Banks/M0_CLK# ) - ( H4 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_CLK ) - ( H5 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A2 ) - ( H6 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A7 ) - ( H7 GND ) - ( H8 ? ) - ( H9 +2.5V ) - ( H10 ? ) - ( H11 ? ) - ( H12 ? ) - ( H13 ? ) - ( H14 ? ) - ( H15 +2.5V ) - ( H16 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_CS# ) - ( H17 ? ) - ( H18 ? ) - ( H19 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_WE# ) - ( H20 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_CLK ) - ( H21 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_RAS# ) - ( H22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_CAS# ) - ( J1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ5 ) - ( J2 GND ) - ( J3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ4 ) - ( J4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A6 ) - ( J5 +2.5V ) - ( J6 ? ) - ( J7 ? ) - ( J8 +1.2V ) - ( J9 GND ) - ( J10 +1.2V ) - ( J11 GND ) - ( J12 +1.2V ) - ( J13 GND ) - ( J14 +1.2V ) - ( J15 GND ) - ( J16 ? ) - ( J17 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_BA0 ) - ( J18 +2.5V ) - ( J19 /DDR_Banks/M1_CLK# ) - ( J20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ4 ) - ( J21 GND ) - ( J22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ5 ) - ( K1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ7 ) - ( K2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ6 ) - ( K3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A5 ) - ( K4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_CAS# ) - ( K5 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_RAS# ) - ( K6 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A3 ) - ( K7 ? ) - ( K8 ? ) - ( K9 +1.2V ) - ( K10 GND ) - ( K11 +1.2V ) - ( K12 GND ) - ( K13 +1.2V ) - ( K14 GND ) - ( K15 +2.5V ) - ( K16 ? ) - ( K17 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_BA1 ) - ( K18 ? ) - ( K19 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A6 ) - ( K20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A5 ) - ( K21 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ6 ) - ( K22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ7 ) - ( L1 ? ) - ( L2 +2.5V ) - ( L3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_LDQS ) - ( L4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_LDM ) - ( L5 GND ) - ( L6 ? ) - ( L7 +2.5V ) - ( L8 +2.5V ) - ( L9 GND ) - ( L10 +1.2V ) - ( L11 GND ) - ( L12 +1.2V ) - ( L13 GND ) - ( L14 +1.2V ) - ( L15 ? ) - ( L16 +2.5V ) - ( L17 ? ) - ( L18 GND ) - ( L19 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_LDM ) - ( L20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_LDQS ) - ( L21 +2.5V ) - ( L22 ? ) - ( M1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ3 ) - ( M2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ2 ) - ( M3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_UDM ) - ( M4 ? ) - ( M5 ? ) - ( M6 ? ) - ( M7 ? ) - ( M8 ? ) - ( M9 +1.2V ) - ( M10 GND ) - ( M11 +1.2V ) - ( M12 GND ) - ( M13 +1.2V ) - ( M14 GND ) - ( M15 +2.5V ) - ( M16 ? ) - ( M17 ? ) - ( M18 ? ) - ( M19 ? ) - ( M20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_UDM ) - ( M21 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ2 ) - ( M22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ3 ) - ( N1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ1 ) - ( N2 GND ) - ( N3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ0 ) - ( N4 ? ) - ( N5 +2.5V ) - ( N6 ? ) - ( N7 ? ) - ( N8 +2.5V ) - ( N9 GND ) - ( N10 +1.2V ) - ( N11 GND ) - ( N12 +1.2V ) - ( N13 GND ) - ( N14 +1.2V ) - ( N15 GND ) - ( N16 ? ) - ( N17 GND ) - ( N18 +2.5V ) - ( N19 ? ) - ( N20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ0 ) - ( N21 GND ) - ( N22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ1 ) - ( P1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ9 ) - ( P2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ8 ) - ( P3 ? ) - ( P4 ? ) - ( P5 ? ) - ( P6 ? ) - ( P7 ? ) - ( P8 ? ) - ( P9 +1.2V ) - ( P10 GND ) - ( P11 +1.2V ) - ( P12 GND ) - ( P13 +1.2V ) - ( P14 GND ) - ( P15 ? ) - ( P16 ? ) - ( P17 ? ) - ( P18 ? ) - ( P19 ? ) - ( P20 ? ) - ( P21 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ8 ) - ( P22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ9 ) - ( R1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ11 ) - ( R2 +2.5V ) - ( R3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ10 ) - ( R4 ? ) - ( R5 GND ) - ( R6 +2.5V ) - ( R7 ? ) - ( R8 ? ) - ( R9 ? ) - ( R10 +2.5V ) - ( R11 ? ) - ( R12 +2.5V ) - ( R13 ? ) - ( R14 +1.2V ) - ( R15 ? ) - ( R16 ? ) - ( R17 ? ) - ( R18 GND ) - ( R19 ? ) - ( R20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ10 ) - ( R21 +2.5V ) - ( R22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ11 ) - ( T1 ? ) - ( T2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_UDQS ) - ( T3 ? ) - ( T4 ? ) - ( T5 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO ) - ( T6 ? ) - ( T7 ? ) - ( T8 ? ) - ( T9 VCCO2 ) - ( T10 ? ) - ( T11 ? ) - ( T12 ? ) - ( T13 VCCO2 ) - ( T14 ? ) - ( T15 ? ) - ( T16 ? ) - ( T17 ? ) - ( T18 ? ) - ( T19 ? ) - ( T20 ? ) - ( T21 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_UDQS ) - ( T22 ? ) - ( U1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ13 ) - ( U2 GND ) - ( U3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ12 ) - ( U4 ? ) - ( U5 +2.5V ) - ( U6 ? ) - ( U7 GND ) - ( U8 ? ) - ( U9 ? ) - ( U10 ? ) - ( U11 +2.5V ) - ( U12 ? ) - ( U13 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3 ) - ( U14 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 ) - ( U15 ? ) - ( U16 ? ) - ( U17 ? ) - ( U18 +2.5V ) - ( U19 ? ) - ( U20 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ12 ) - ( U21 GND ) - ( U22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ13 ) - ( V1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ15 ) - ( V2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ14 ) - ( V3 ? ) - ( V4 GND ) - ( V5 ? ) - ( V6 +2.5V ) - ( V7 ? ) - ( V8 VCCO2 ) - ( V9 ? ) - ( V10 GND ) - ( V11 ? ) - ( V12 VCCO2 ) - ( V13 ? ) - ( V14 GND ) - ( V15 ? ) - ( V16 VCCO2 ) - ( V17 ? ) - ( V18 ? ) - ( V19 ? ) - ( V20 ? ) - ( V21 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ14 ) - ( V22 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ15 ) - ( W1 ? ) - ( W2 +2.5V ) - ( W3 ? ) - ( W4 ? ) - ( W5 VCCO2 ) - ( W6 ? ) - ( W7 GND ) - ( W8 ? ) - ( W9 ? ) - ( W10 ? ) - ( W11 ? ) - ( W12 ? ) - ( W13 ? ) - ( W14 ? ) - ( W15 ? ) - ( W16 GND ) - ( W17 ? ) - ( W18 ? ) - ( W19 GND ) - ( W20 ? ) - ( W21 +2.5V ) - ( W22 ? ) - ( Y1 ? ) - ( Y2 ? ) - ( Y3 ? ) - ( Y4 ? ) - ( Y5 ? ) - ( Y6 ? ) - ( Y7 ? ) - ( Y8 ? ) - ( Y9 ? ) - ( Y10 ? ) - ( Y11 ? ) - ( Y12 ? ) - ( Y13 ? ) - ( Y14 ? ) - ( Y15 ? ) - ( Y16 ? ) - ( Y17 ? ) - ( Y18 ? ) - ( Y19 ? ) - ( Y20 +3.3V ) - ( Y21 ? ) - ( Y22 N-000359 ) - ) - ( /4C7BC2A2/4C6B216E 0402 R23 33 {Lib=R} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_UDM ) - ( 2 /DDR_Banks/M0_UDM ) - ) - ( /4C7BC2A2/4C6B216D 0402 R22 33 {Lib=R} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_UDQS ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_UDQS ) - ) - ( /4C7BC2A2/4C6B216B 0402 R24 33 {Lib=R} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_CKE ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_CKE ) - ) - ( /4C7BC2A2/4C6B1B90 0402 R21 120 {Lib=R} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_CLK ) - ( 2 /DDR_Banks/M0_CLK# ) - ) - ( /4C7BC2A2/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A0 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A1 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A2 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A3 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A3 ) - ( 6 /DDR_Banks/M0_A2 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A1 ) - ( 8 /DDR_Banks/M0_A0 ) - ) - ( /4C7BC2A2/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_RAS# ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_BA0 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_BA1 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A10 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A10 ) - ( 6 /DDR_Banks/M0_BA1 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_BA0 ) - ( 8 /DDR_Banks/M0_RAS# ) - ) - ( /4C7BC2A2/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_LDQS ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_LDM ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_WE# ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_CAS# ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_CAS# ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_WE# ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_LDM ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_LDQS ) - ) - ( /4C7BC2A2/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A7 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A6 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A5 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A4 ) - ( 5 /DDR_Banks/M0_A4 ) - ( 6 /DDR_Banks/M0_A5 ) - ( 7 /DDR_Banks/M0_A6 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A7 ) - ) - ( /4C7BC2A2/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A12 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A11 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A9 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_A8 ) - ( 5 /DDR_Banks/M0_A8 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A9 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A11 ) - ( 8 /DDR_Banks/M0_A12 ) - ) - ( /4C7BC2A2/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ4 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ5 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ6 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ7 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ7 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ6 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ5 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ4 ) - ) - ( /4C7BC2A2/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ0 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ1 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ2 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ3 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ3 ) - ( 6 /DDR_Banks/M0_DQ2 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ1 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ0 ) - ) - ( /4C7BC2A2/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ8 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ9 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ10 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ11 ) - ( 5 /DDR_Banks/M0_DQ11 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ10 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ9 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ8 ) - ) - ( /4C7BC2A2/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ12 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ13 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ14 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M0_DQ15 ) - ( 5 /DDR_Banks/M0_DQ15 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ14 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ13 ) - ( 8 /DDR_Banks/M0_DQ12 ) - ) - ( /4C7BC2A2/4C69E7DD 0402 R19 33 {Lib=R} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_UDQS ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_UDQS ) - ) - ( /4C7BC2A2/4C69E92D 0402 R20 33 {Lib=R} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_CS# ) - ( 2 /DDR_Banks/M1_CS# ) - ) - ( /4C7BC2A2/4C69E7F8 0402 R17 33 {Lib=R} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_CKE ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_CKE ) - ) - ( /4C7BC2A2/4C69E7C2 0402 R18 33 {Lib=R} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_UDM ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_UDM ) - ) - ( /4C7BC2A2/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ11 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ10 ) - ( 3 /DDR_Banks/M1_DQ9 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ8 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ8 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ9 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ10 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ11 ) - ) - ( /4C7BC2A2/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ15 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ14 ) - ( 3 /DDR_Banks/M1_DQ13 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ12 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ12 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ13 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ14 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ15 ) - ) - ( /4C7BC2A2/4C69DF7A 0402 R16 120 {Lib=R} - ( 1 /DDR_Banks/M1_CLK# ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_CLK ) - ) - ( /4C7BC2A2/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4} - ( 1 /DDR_Banks/M1_A12 ) - ( 2 /DDR_Banks/M1_A11 ) - ( 3 /DDR_Banks/M1_A9 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A8 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A8 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A9 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A11 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A12 ) - ) - ( /4C7BC2A2/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A7 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A6 ) - ( 3 /DDR_Banks/M1_A5 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A4 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A4 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A5 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A6 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A7 ) - ) - ( /4C7BC2A2/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ0 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ1 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ2 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ3 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ3 ) - ( 6 /DDR_Banks/M1_DQ2 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ1 ) - ( 8 /DDR_Banks/M1_DQ0 ) - ) - ( /4C7BC2A2/4C69D3A4 $noname RP3 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_LDQS ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_LDM ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_WE# ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_CAS# ) - ( 5 /DDR_Banks/M1_CAS# ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_WE# ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_LDM ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_LDQS ) - ) - ( /4C7BC2A2/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ4 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ5 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ6 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_DQ7 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ7 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ6 ) - ( 7 /DDR_Banks/M1_DQ5 ) - ( 8 /DDR_Banks/M1_DQ4 ) - ) - ( /4C7BC2A2/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_RAS# ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_BA0 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_BA1 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A10 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A10 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_BA1 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_BA0 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_RAS# ) - ) - ( /4C7BC2A2/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A0 ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A1 ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A2 ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/R_M1_A3 ) - ( 5 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A3 ) - ( 6 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A2 ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A1 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A0 ) - ) - ( /4C716A4D/4C716CAB $noname J6 CONN_8X2 {Lib=CONN_8X2} - ( 1 /DBG_PRG/FPGA_TCK ) - ( 2 ? ) - ( 3 /DBG_PRG/FPGA_TMS ) - ( 4 ? ) - ( 5 /DBG_PRG/FPGA_TDO ) - ( 6 ? ) - ( 7 /DBG_PRG/FPGA_TDI ) - ( 8 ? ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 ? ) - ( 13 ? ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ) - ( /4C69ED5F/4C79C99E 0805 C95 4.7uF {Lib=CAP} - ( 1 /PSU/VIN_DC-DC-5.0 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C79C99C 0402 R35 R {Lib=R} - ( 1 /PSU/Iout_5.0 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C79C99B 1206 R36 R {Lib=R} - ( 1 /PSU/VIN_DC-DC-5.0 ) - ( 2 N-000148 ) - ) - ( /4C69ED5F/4C79C99A MLP6 U16 FAN4010 {Lib=FAN4010} - ( 1 N-000148 ) - ( 2 ? ) - ( 3 /PSU/Iout_5.0 ) - ( 5 GND ) - ( 6 /PSU/VIN_DC-DC-5.0 ) - ) - ( /4C69ED5F/4C79C8B2 0402 C98 100nF {Lib=CAP} - ( 1 +5V ) - ( 2 GND ) - ) - ( /4C69ED5F/4C79C8B1 0402 R39 R {Lib=R} - ( 1 +5V ) - ( 2 /PSU/VFB1.2 ) - ) - ( /4C69ED5F/4C79C8B0 0402 R38 R {Lib=R} - ( 1 /PSU/VFB1.2 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C79C8AF 1206 C97 10uF {Lib=CAP} - ( 1 +5V ) - ( 2 GND ) - ) - ( /4C69ED5F/4C79C8AE 0402 C96 22pF {Lib=CAP} - ( 1 +5V ) - ( 2 /PSU/VFB1.2 ) - ) - ( /4C69ED5F/4C79C828 1210 L10 4.7uH {Lib=INDUCTOR} - ( 1 N-000145 ) - ( 2 /PSU/VIN_DC-DC-5.0 ) - ) - ( /4C69ED5F/4C79C7C0 0402 R37 R {Lib=R} - ( 1 N-000153 ) - ( 2 /PSU/VIN_DC-DC-5.0 ) - ) - ( /4C69ED5F/4C79C65B SOT23_6 U15 A7117 {Lib=A7117} - ( 1 N-000145 ) - ( 2 GND ) - ( 3 /PSU/VFB1.2 ) - ( 4 N-000153 ) - ( 5 +5V ) - ( 6 /PSU/VIN_DC-DC-5.0 ) - ) - ( /4C69ED5F/4C770714 MLP6 U14 FAN4010 {Lib=FAN4010} - ( 1 N-000143 ) - ( 2 ? ) - ( 3 /PSU/Iout_1.2 ) - ( 5 GND ) - ( 6 ? ) - ) - ( /4C69ED5F/4C770713 1206 R34 R {Lib=R} - ( 1 /PSU/VIN_DC-DC-1.2 ) - ( 2 N-000143 ) - ) - ( /4C69ED5F/4C770712 0402 R33 R {Lib=R} - ( 1 /PSU/Iout_1.2 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C77067B 0402 R31 R {Lib=R} - ( 1 /PSU/Iout_3.3 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C77060E 1206 R32 R {Lib=R} - ( 1 /PSU/VIN_DC-DC-3.3 ) - ( 2 N-000142 ) - ) - ( /4C69ED5F/4C7705B0 MLP6 U13 FAN4010 {Lib=FAN4010} - ( 1 N-000142 ) - ( 2 ? ) - ( 3 /PSU/Iout_3.3 ) - ( 5 GND ) - ( 6 /PSU/VIN_DC-DC-3.3 ) - ) - ( /4C69ED5F/4C6D2FD7 0805 C82 4.7uF {Lib=CAP} - ( 1 /PSU/VIN_DC-DC-1.2 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2FD6 0402 C83 22pF {Lib=CAP} - ( 1 +1.2V ) - ( 2 /PSU/VFB1.2 ) - ) - ( /4C69ED5F/4C6D2FD5 1206 C84 10uF {Lib=CAP} - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2FD3 0402 R27 R {Lib=R} - ( 1 /PSU/VFB1.2 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2FD2 0402 R28 R {Lib=R} - ( 1 +1.2V ) - ( 2 /PSU/VFB1.2 ) - ) - ( /4C69ED5F/4C6D2FD1 1210 L9 2.2uH {Lib=INDUCTOR} - ( 1 +1.2V ) - ( 2 /PSU/SW_1.2 ) - ) - ( /4C69ED5F/4C6D2FD0 0402 C85 100nF {Lib=CAP} - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2F0B 0402 C81 100nF {Lib=CAP} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2E6A 1210 L8 2.2uH {Lib=INDUCTOR} - ( 1 +3.3V ) - ( 2 /PSU/SW_3.3 ) - ) - ( /4C69ED5F/4C6D2DDD 0402 R26 R {Lib=R} - ( 1 +3.3V ) - ( 2 /PSU/VFB3.3 ) - ) - ( /4C69ED5F/4C6D2DBC 0402 R25 R {Lib=R} - ( 1 /PSU/VFB3.3 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2C83 1206 C80 10uF {Lib=CAP} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2C7F 0402 C79 22pF {Lib=CAP} - ( 1 +3.3V ) - ( 2 /PSU/VFB3.3 ) - ) - ( /4C69ED5F/4C6D2C7C 0805 C78 4.7uF {Lib=CAP} - ( 1 /PSU/VIN_DC-DC-3.3 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2AE0 SOT23-5 U12 A7108 {Lib=A7108} - ( 1 /PSU/VIN_DC-DC-1.2 ) - ( 2 GND ) - ( 3 /PSU/SW_1.2 ) - ( 4 /PSU/VIN_DC-DC-1.2 ) - ( 5 /PSU/VFB1.2 ) - ) - ( /4C69ED5F/4C6D2AA5 SOT23-5 U11 A7108 {Lib=A7108} - ( 1 /PSU/VIN_DC-DC-3.3 ) - ( 2 GND ) - ( 3 /PSU/SW_3.3 ) - ( 4 /PSU/VIN_DC-DC-3.3 ) - ( 5 /PSU/VFB3.3 ) - ) - ( /4C69ED5F/4C6C9DB9 DFN10 U10 A7130 {Lib=A7130} - ( 1 ? ) - ( 2 GND ) - ( 3 ? ) - ( 4 ? ) - ( 5 GND ) - ( 6 ? ) - ( 7 ? ) - ( 8 ? ) - ( 9 ? ) - ( 10 ? ) - ( PAD GND ) - ) - ( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF} - ( 1 ? ) - ( 2 ? ) - ( 3 /PSU/Iout_1.2 ) - ( 4 /PSU/Iout_3.3 ) - ( 5 ? ) - ( 6 ? ) - ( 7 ? ) - ( 8 GND ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 ? ) - ( 13 ? ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ( 17 ? ) - ( 18 ? ) - ( 19 ? ) - ( 20 ? ) - ( PAD GND ) - ) - ( /4C4227FE/4C6969AB $noname C75 100nF {Lib=C} - ( 1 GND ) - ( 2 +3.3V ) - ) - ( /4C4227FE/4C65D681 0603 C74 1uF {Lib=CAP} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4227FE/4C65D67C 0402 C73 100nF {Lib=CAP} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4227FE/4C65D661 0402 C72 100nF {Lib=CAP} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB} - ( 1 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO ) - ( 2 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1 ) - ( 3 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 ) - ( 4 GND ) - ( 5 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0 ) - ( 6 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK ) - ( 7 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3 ) - ( 8 VCCO2 ) - ) - ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} - ( 1 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2 ) - ( 2 /Non_volatile_memories/SD_DAT3 ) - ( 3 /FPGA,_Port0,_Port2,_PROG_IF/SD_CMD ) - ( 4 +3.3V ) - ( 5 /Non_volatile_memories/SD_CLK ) - ( 6 GND ) - ( 7 /Non_volatile_memories/SD_DAT0 ) - ( 8 /Non_volatile_memories/SD_DAT1 ) - ( CASE GND ) - ( CD ? ) - ( COM GND ) - ) - ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 /Non_volatile_memories/NF_RNB ) - ( 7 /Non_volatile_memories/NF_RNB ) - ( 8 /FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N ) - ( 9 /Non_volatile_memories/NF_CS1_N ) - ( 10 ? ) - ( 11 ? ) - ( 12 +3.3V ) - ( 13 GND ) - ( 14 ? ) - ( 15 ? ) - ( 16 /Non_volatile_memories/NF_CLE ) - ( 17 /Non_volatile_memories/NF_ALE ) - ( 18 /Non_volatile_memories/NF_WE_N ) - ( 19 +3.3V ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 ? ) - ( 24 ? ) - ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 ? ) - ( 29 /Non_volatile_memories/NF_D0 ) - ( 30 /Non_volatile_memories/NF_D1 ) - ( 31 /Non_volatile_memories/NF_D2 ) - ( 32 /FPGA,_Port0,_Port2,_PROG_IF/NF_D3 ) - ( 33 ? ) - ( 34 ? ) - ( 35 ? ) - ( 36 GND ) - ( 37 +3.3V ) - ( 38 ? ) - ( 39 ? ) - ( 40 ? ) - ( 41 /FPGA,_Port0,_Port2,_PROG_IF/NF_D4 ) - ( 42 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 ) - ( 43 /FPGA,_Port0,_Port2,_PROG_IF/NF_D6 ) - ( 44 /Non_volatile_memories/NF_D7 ) - ( 45 ? ) - ( 46 ? ) - ( 47 ? ) - ( 48 ? ) - ) - ( /4C5F1EDC/4C75F027 ZX62D-B-5P8 J7 ZX62D-B-5P8 {Lib=ZX62D-B-5P8} - ( 1 N-000137 ) - ( 2 /USB/USBD_D- ) - ( 3 /USB/USBD_D+ ) - ( 4 N-000136 ) - ( 5 N-000136 ) - ( 6 N-000132 ) - ( 7 N-000132 ) - ( 8 N-000132 ) - ( 9 N-000132 ) - ) - ( /4C5F1EDC/4C71BA25 MLF16 U7 MIC2550-MLF {Lib=MIC2550-MLF} - ( 1 /USB/USBD_SPD ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/USBD_RCV ) - ( 3 /USB/USBD_VP ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/USBD_VM ) - ( 6 GND ) - ( 7 GND ) - ( 9 /USB/USBD_OE_N ) - ( 10 /USB/USBD_D- ) - ( 11 /USB/USBD_D+ ) - ( 12 +3.3V ) - ( 14 +3.3V ) - ( 15 +2.5V ) - ) - ( /4C5F1EDC/4C71BA1D MLF16 U6 MIC2550-MLF {Lib=MIC2550-MLF} - ( 1 /USB/USBA_SPD ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/USBA_RCV ) - ( 3 /FPGA_Port_1,_Port_3_(DDR,_USB)/USBA_VP ) - ( 4 /USB/USBA_VM ) - ( 6 GND ) - ( 7 GND ) - ( 9 /USB/USBA_OE_N ) - ( 10 /USB/USBA_D- ) - ( 11 /USB/USBA_D+ ) - ( 12 +3.3V ) - ( 14 +3.3V ) - ( 15 +2.5V ) - ) - ( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552BD 0402 C36 100nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552BC 0402 C37 100nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03} - ( 1 /USB/USBD_D- ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03} - ( 1 /USB/USBD_D+ ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C} - ( 1 N-000132 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R} - ( 1 N-000132 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} - ( 1 N-000137 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000134 ) - ( 2 N-000135 ) - ) - ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000131 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000130 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000130 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 /USB/USBA_D+ ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 /USB/USBA_D- ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000134 ) - ( 2 +5V ) - ) - ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( 1 N-000135 ) - ( 2 /USB/USBA_D- ) - ( 3 /USB/USBA_D+ ) - ( 4 N-000131 ) - ( S1 N-000130 ) - ( S2 N-000130 ) - ( S3 N-000130 ) - ( S4 N-000130 ) - ) - ( /4C5F1EDC/4C5F2039 $noname C15 100nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2037 0402 C14 100nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D8114 $noname C9 100nF {Lib=C} - ( 1 /Ethernet_Phy/ETH_PLL1.8V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D810A 0402 L3 FB {Lib=INDUCTOR} - ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 /Ethernet_Phy/ETH_PLL1.8V ) - ) - ( /4C4320F3/4C5D8104 $noname C6 100nF {Lib=C} - ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D80F3 0402 L1 FB {Lib=INDUCTOR} - ( 1 +1.8V ) - ( 2 /Ethernet_Phy/ETH_A1.8V ) - ) - ( /4C4320F3/4C5D80F0 $noname C4 100nF {Lib=C} - ( 1 +1.8V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D80ED $noname C2 1uF {Lib=C} - ( 1 +1.8V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FB7 0402 L2 FB {Lib=INDUCTOR} - ( 1 +3.3V ) - ( 2 /Ethernet_Phy/ETH_A3.3V ) - ) - ( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C} - ( 1 /Ethernet_Phy/ETH_A3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C} - ( 1 /Ethernet_Phy/ETH_A3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} - ( 1 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO ) - ( 2 +3.3V ) - ) - ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000123 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 /Ethernet_Phy/MAG_SHIELD ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 /Ethernet_Phy/MAG_SHIELD ) - ( 2 GND ) - ) - ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO ) - ( 2 /Ethernet_Phy/ETH_MDC ) - ( 3 /Ethernet_Phy/ETH_RXD3 ) - ( 4 /Ethernet_Phy/ETH_RXD2 ) - ( 5 /Ethernet_Phy/ETH_RXD1 ) - ( 6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 ) - ( 7 +3.3V ) - ( 8 GND ) - ( 9 /Ethernet_Phy/ETH_RXDV ) - ( 10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC ) - ( 11 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER ) - ( 12 GND ) - ( 13 +1.8V ) - ( 14 /Ethernet_Phy/ETH_TXER ) - ( 15 /Ethernet_Phy/ETH_TXC ) - ( 16 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN ) - ( 17 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 ) - ( 18 /Ethernet_Phy/ETH_TXD1 ) - ( 19 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2 ) - ( 20 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3 ) - ( 21 /FPGA,_Port0,_Port2,_PROG_IF/ETH_COL ) - ( 22 /Ethernet_Phy/ETH_CRS ) - ( 23 GND ) - ( 24 +3.3V ) - ( 25 /Ethernet_Phy/ETH_INT ) - ( 26 /Ethernet_Phy/ETH_LED0 ) - ( 27 /Ethernet_Phy/ETH_LED1 ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 /Ethernet_Phy/MAG_RX- ) - ( 33 /Ethernet_Phy/MAG_RX+ ) - ( 34 ? ) - ( 35 GND ) - ( 36 GND ) - ( 37 N-000123 ) - ( 38 /Ethernet_Phy/ETH_A3.3V ) - ( 39 GND ) - ( 40 /Ethernet_Phy/MAG_TX- ) - ( 41 /Ethernet_Phy/MAG_TX+ ) - ( 42 ? ) - ( 43 ? ) - ( 44 GND ) - ( 45 ? ) - ( 46 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK ) - ( 47 /Ethernet_Phy/ETH_PLL1.8V ) - ( 48 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N ) - ) - ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} - ( 1 +3.3V ) - ( 2 /Ethernet_Phy/MAG_TX+ ) - ) - ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} - ( 1 +3.3V ) - ( 2 /Ethernet_Phy/MAG_TX- ) - ) - ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} - ( 1 +3.3V ) - ( 2 /Ethernet_Phy/MAG_RX- ) - ) - ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} - ( 1 +3.3V ) - ( 2 /Ethernet_Phy/MAG_RX+ ) - ) - ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000118 ) - ( 2 /Ethernet_Phy/ETH_LED1 ) - ) - ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000117 ) - ( 2 /Ethernet_Phy/ETH_LED0 ) - ) - ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 /Ethernet_Phy/MAG_TX+ ) - ( 2 /Ethernet_Phy/MAG_TX- ) - ( 3 +3.3V ) - ( 4 GND ) - ( 5 GND ) - ( 6 +3.3V ) - ( 7 /Ethernet_Phy/MAG_RX+ ) - ( 8 /Ethernet_Phy/MAG_RX- ) - ( 9 +3.3V ) - ( 10 N-000117 ) - ( 11 +3.3V ) - ( 12 N-000118 ) - ( 13 /Ethernet_Phy/MAG_SHIELD ) - ( 14 /Ethernet_Phy/MAG_SHIELD ) - ) - ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} - ( 1 +2.5V ) - ( 2 /DDR_Banks/M1_DQ0 ) - ( 3 +2.5V ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ1 ) - ( 5 /DDR_Banks/M1_DQ2 ) - ( 6 GND ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ3 ) - ( 8 /DDR_Banks/M1_DQ4 ) - ( 9 +2.5V ) - ( 10 /DDR_Banks/M1_DQ5 ) - ( 11 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ6 ) - ( 12 GND ) - ( 13 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ7 ) - ( 14 ? ) - ( 15 +2.5V ) - ( 16 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_LDQS ) - ( 17 ? ) - ( 18 +2.5V ) - ( 19 ? ) - ( 20 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_LDM ) - ( 21 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_WE# ) - ( 22 /DDR_Banks/M1_CAS# ) - ( 23 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_RAS# ) - ( 24 /DDR_Banks/M1_CS# ) - ( 25 ? ) - ( 26 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_BA0 ) - ( 27 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_BA1 ) - ( 28 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A10 ) - ( 29 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A0 ) - ( 30 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A1 ) - ( 31 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A2 ) - ( 32 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A3 ) - ( 33 +2.5V ) - ( 34 GND ) - ( 35 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A4 ) - ( 36 /DDR_Banks/M1_A5 ) - ( 37 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A6 ) - ( 38 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A7 ) - ( 39 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_A8 ) - ( 40 /DDR_Banks/M1_A9 ) - ( 41 /DDR_Banks/M1_A11 ) - ( 42 /DDR_Banks/M1_A12 ) - ( 43 ? ) - ( 44 /DDR_Banks/M1_CLK# ) - ( 45 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_CKE ) - ( 46 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_CLK ) - ( 47 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_UDM ) - ( 48 GND ) - ( 49 /DDR_Banks/M1_VREF ) - ( 50 ? ) - ( 51 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_UDQS ) - ( 52 GND ) - ( 53 ? ) - ( 54 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ8 ) - ( 55 +2.5V ) - ( 56 /DDR_Banks/M1_DQ9 ) - ( 57 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ10 ) - ( 58 GND ) - ( 59 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ11 ) - ( 60 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ12 ) - ( 61 +2.5V ) - ( 62 /DDR_Banks/M1_DQ13 ) - ( 63 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ14 ) - ( 64 GND ) - ( 65 /FPGA_Port_1,_Port_3_(DDR,_USB)/M1_DQ15 ) - ( 66 GND ) - ) - ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C65D28E 0402 C71 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61D1D4 1206 C34 10uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61D151 1206 C33 10uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R} - ( 1 +2.5V ) - ( 2 /DDR_Banks/M1_VREF ) - ) - ( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R} - ( 1 /DDR_Banks/M1_VREF ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R} - ( 1 /DDR_Banks/M0_VREF ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R} - ( 1 +2.5V ) - ( 2 /DDR_Banks/M0_VREF ) - ) - ( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 /DDR_Banks/M1_VREF ) - ) - ( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP} - ( 1 /DDR_Banks/M1_VREF ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP} - ( 1 /DDR_Banks/M0_VREF ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 /DDR_Banks/M0_VREF ) - ) - ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} - ( 1 +2.5V ) - ( 2 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ0 ) - ( 3 +2.5V ) - ( 4 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ1 ) - ( 5 /DDR_Banks/M0_DQ2 ) - ( 6 GND ) - ( 7 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ3 ) - ( 8 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ4 ) - ( 9 +2.5V ) - ( 10 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ5 ) - ( 11 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ6 ) - ( 12 GND ) - ( 13 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ7 ) - ( 14 ? ) - ( 15 +2.5V ) - ( 16 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_LDQS ) - ( 17 ? ) - ( 18 +2.5V ) - ( 19 ? ) - ( 20 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_LDM ) - ( 21 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_WE# ) - ( 22 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_CAS# ) - ( 23 /DDR_Banks/M0_RAS# ) - ( 24 GND ) - ( 25 ? ) - ( 26 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_BA0 ) - ( 27 /DDR_Banks/M0_BA1 ) - ( 28 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A10 ) - ( 29 /DDR_Banks/M0_A0 ) - ( 30 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A1 ) - ( 31 /DDR_Banks/M0_A2 ) - ( 32 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A3 ) - ( 33 +2.5V ) - ( 34 GND ) - ( 35 /DDR_Banks/M0_A4 ) - ( 36 /DDR_Banks/M0_A5 ) - ( 37 /DDR_Banks/M0_A6 ) - ( 38 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A7 ) - ( 39 /DDR_Banks/M0_A8 ) - ( 40 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A9 ) - ( 41 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_A11 ) - ( 42 /DDR_Banks/M0_A12 ) - ( 43 ? ) - ( 44 /DDR_Banks/M0_CLK# ) - ( 45 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_CKE ) - ( 46 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_CLK ) - ( 47 /DDR_Banks/M0_UDM ) - ( 48 GND ) - ( 49 /DDR_Banks/M0_VREF ) - ( 50 ? ) - ( 51 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_UDQS ) - ( 52 GND ) - ( 53 ? ) - ( 54 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ8 ) - ( 55 +2.5V ) - ( 56 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ9 ) - ( 57 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ10 ) - ( 58 GND ) - ( 59 /DDR_Banks/M0_DQ11 ) - ( 60 /DDR_Banks/M0_DQ12 ) - ( 61 +2.5V ) - ( 62 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ13 ) - ( 63 /FPGA_Port_1,_Port_3_(DDR,_USB)/M0_DQ14 ) - ( 64 GND ) - ( 65 /DDR_Banks/M0_DQ15 ) - ( 66 GND ) + ( B1 ? ) + ( B2 ? ) + ( B3 ? ) + ( B4 +3.3V ) + ( B5 GND ) + ( B6 /FPGA,_P195 ) + ( B7 +3.3V ) + ( B8 /Etherne196 ) + ( B9 GND ) + ( B10 /Etherne197 ) + ( B11 +3.3V ) + ( B12 /FPGA,_P198 ) + ( B13 GND ) + ( B14 /FPGA,_P199 ) + ( B15 +3.3V ) + ( B16 /Non_vol11 ) + ( B17 GND ) + ( B18 /FPGA,_P15 ) + ( B19 +3.3V ) + ( B20 /FPGA_Po200 ) + ( B21 /USB/USBD_VP ) + ( B22 /FPGA_Po201 ) + ( C1 /FPGA_Po173 ) + ( C2 +2.5V ) + ( C3 ? ) + ( C4 ? ) + ( C5 /FPGA,_P202 ) + ( C6 /FPGA,_P203 ) + ( C7 /FPGA,_P204 ) + ( C8 /Etherne205 ) + ( C9 /FPGA,_P206 ) + ( C10 /FPGA,_P207 ) + ( C11 /FPGA,_P208 ) + ( C12 /Non_vol209 ) + ( C13 ? ) + ( C14 /Non_vol210 ) + ( C15 /Non_vol211 ) + ( C16 /Non_vol12 ) + ( C17 ? ) + ( C18 /DBG_PRG21 ) + ( C19 /USB/USBA_OE_N ) + ( C20 /FPGA_Po90 ) + ( C21 +2.5V ) + ( C22 /FPGA_Po91 ) + ( D1 /FPGA_Po172 ) + ( D2 /FPGA_Po43 ) + ( D3 ? ) + ( D4 GND ) + ( D5 ? ) + ( D6 /FPGA,_P24 ) + ( D7 /Etherne212 ) + ( D8 /FPGA,_P213 ) + ( D9 /FPGA,_P214 ) + ( D10 /FPGA,_P215 ) + ( D11 /FPGA,_P216 ) + ( D12 ? ) + ( D13 ? ) + ( D14 /FPGA,_P217 ) + ( D15 /Non_vol218 ) + ( D16 +2.5V ) + ( D17 ? ) + ( D18 GND ) + ( D19 /USB/USBA_VP ) + ( D20 /FPGA_Po219 ) + ( D21 /FPGA_Po29 ) + ( D22 /FPGA_Po93 ) + ( E1 /FPGA_Po174 ) + ( E2 GND ) + ( E3 /FPGA_Po175 ) + ( E4 ? ) + ( E5 ? ) + ( E6 ? ) + ( E7 GND ) + ( E8 ? ) + ( E9 +3.3V ) + ( E10 ? ) + ( E11 GND ) + ( E12 ? ) + ( E13 +3.3V ) + ( E14 ? ) + ( E15 GND ) + ( E16 ? ) + ( E17 +3.3V ) + ( E18 /DBG_PRG23 ) + ( E19 +2.5V ) + ( E20 /FPGA_Po87 ) + ( E21 GND ) + ( E22 /FPGA_Po47 ) + ( F1 ? ) + ( F2 /FPGA_Po160 ) + ( F3 /FPGA_Po169 ) + ( F4 +2.5V ) + ( F5 ? ) + ( F6 +2.5V ) + ( F7 ? ) + ( F8 ? ) + ( F9 ? ) + ( F10 ? ) + ( F11 +2.5V ) + ( F12 ? ) + ( F13 ? ) + ( F14 ? ) + ( F15 ? ) + ( F16 /FPGA_Po220 ) + ( F17 /USB/USBA_RCV ) + ( F18 ? ) + ( F19 /FPGA_Po92 ) + ( F20 /FPGA_Po84 ) + ( F21 /FPGA_Po45 ) + ( F22 /FPGA_Po46 ) + ( G1 /FPGA_Po152 ) + ( G2 +2.5V ) + ( G3 /FPGA_Po151 ) + ( G4 /FPGA_Po153 ) + ( G5 GND ) + ( G6 ? ) + ( G7 ? ) + ( G8 ? ) + ( G9 ? ) + ( G10 +3.3V ) + ( G11 ? ) + ( G12 +2.5V ) + ( G13 ? ) + ( G14 +3.3V ) + ( G15 /DBG_PRG20 ) + ( G16 ? ) + ( G17 ? ) + ( G18 GND ) + ( G19 /FPGA_Po53 ) + ( G20 /FPGA_Po48 ) + ( G21 +2.5V ) + ( G22 ? ) + ( H1 /FPGA_Po143 ) + ( H2 /FPGA_Po142 ) + ( H3 /FPGA_Po38 ) + ( H4 /FPGA_Po37 ) + ( H5 /FPGA_Po144 ) + ( H6 /FPGA_Po166 ) + ( H7 GND ) + ( H8 ? ) + ( H9 +2.5V ) + ( H10 ? ) + ( H11 ? ) + ( H12 ? ) + ( H13 ? ) + ( H14 ? ) + ( H15 +2.5V ) + ( H16 /FPGA_Po35 ) + ( H17 ? ) + ( H18 ? ) + ( H19 /FPGA_Po60 ) + ( H20 /FPGA_Po28 ) + ( H21 /FPGA_Po50 ) + ( H22 /FPGA_Po61 ) + ( J1 /FPGA_Po127 ) + ( J2 GND ) + ( J3 /FPGA_Po126 ) + ( J4 /FPGA_Po167 ) + ( J5 +2.5V ) + ( J6 ? ) + ( J7 ? ) + ( J8 +1.2V ) + ( J9 GND ) + ( J10 +1.2V ) + ( J11 GND ) + ( J12 +1.2V ) + ( J13 GND ) + ( J14 +1.2V ) + ( J15 GND ) + ( J16 ? ) + ( J17 /FPGA_Po51 ) + ( J18 +2.5V ) + ( J19 /DDR_Ban27 ) + ( J20 /FPGA_Po66 ) + ( J21 GND ) + ( J22 /FPGA_Po67 ) + ( K1 /FPGA_Po129 ) + ( K2 /FPGA_Po128 ) + ( K3 /FPGA_Po168 ) + ( K4 /FPGA_Po161 ) + ( K5 /FPGA_Po150 ) + ( K6 /FPGA_Po145 ) + ( K7 ? ) + ( K8 ? ) + ( K9 +1.2V ) + ( K10 GND ) + ( K11 +1.2V ) + ( K12 GND ) + ( K13 +1.2V ) + ( K14 GND ) + ( K15 +2.5V ) + ( K16 ? ) + ( K17 /FPGA_Po52 ) + ( K18 ? ) + ( K19 /FPGA_Po86 ) + ( K20 /FPGA_Po85 ) + ( K21 /FPGA_Po68 ) + ( K22 /FPGA_Po69 ) + ( L1 ? ) + ( L2 +2.5V ) + ( L3 /FPGA_Po158 ) + ( L4 /FPGA_Po159 ) + ( L5 GND ) + ( L6 ? ) + ( L7 +2.5V ) + ( L8 +2.5V ) + ( L9 GND ) + ( L10 +1.2V ) + ( L11 GND ) + ( L12 +1.2V ) + ( L13 GND ) + ( L14 +1.2V ) + ( L15 ? ) + ( L16 +2.5V ) + ( L17 ? ) + ( L18 GND ) + ( L19 /FPGA_Po59 ) + ( L20 /FPGA_Po58 ) + ( L21 +2.5V ) + ( L22 ? ) + ( M1 /FPGA_Po137 ) + ( M2 /FPGA_Po136 ) + ( M3 /FPGA_Po41 ) + ( M4 ? ) + ( M5 ? ) + ( M6 ? ) + ( M7 ? ) + ( M8 ? ) + ( M9 +1.2V ) + ( M10 GND ) + ( M11 +1.2V ) + ( M12 GND ) + ( M13 +1.2V ) + ( M14 GND ) + ( M15 +2.5V ) + ( M16 ? ) + ( M17 ? ) + ( M18 ? ) + ( M19 ? ) + ( M20 /FPGA_Po31 ) + ( M21 /FPGA_Po76 ) + ( M22 /FPGA_Po77 ) + ( N1 /FPGA_Po135 ) + ( N2 GND ) + ( N3 /FPGA_Po134 ) + ( N4 ? ) + ( N5 +2.5V ) + ( N6 ? ) + ( N7 ? ) + ( N8 +2.5V ) + ( N9 GND ) + ( N10 +1.2V ) + ( N11 GND ) + ( N12 +1.2V ) + ( N13 GND ) + ( N14 +1.2V ) + ( N15 GND ) + ( N16 ? ) + ( N17 GND ) + ( N18 +2.5V ) + ( N19 ? ) + ( N20 /FPGA_Po74 ) + ( N21 GND ) + ( N22 /FPGA_Po75 ) + ( P1 /FPGA_Po119 ) + ( P2 /FPGA_Po118 ) + ( P3 ? ) + ( P4 ? ) + ( P5 ? ) + ( P6 ? ) + ( P7 ? ) + ( P8 ? ) + ( P9 +1.2V ) + ( P10 GND ) + ( P11 +1.2V ) + ( P12 GND ) + ( P13 +1.2V ) + ( P14 GND ) + ( P15 ? ) + ( P16 ? ) + ( P17 ? ) + ( P18 ? ) + ( P19 ? ) + ( P20 ? ) + ( P21 /FPGA_Po106 ) + ( P22 /FPGA_Po107 ) + ( R1 /FPGA_Po121 ) + ( R2 +2.5V ) + ( R3 /FPGA_Po120 ) + ( R4 ? ) + ( R5 GND ) + ( R6 +2.5V ) + ( R7 ? ) + ( R8 ? ) + ( R9 ? ) + ( R10 +2.5V ) + ( R11 ? ) + ( R12 +2.5V ) + ( R13 ? ) + ( R14 +1.2V ) + ( R15 ? ) + ( R16 ? ) + ( R17 ? ) + ( R18 GND ) + ( R19 ? ) + ( R20 /FPGA_Po108 ) + ( R21 +2.5V ) + ( R22 /FPGA_Po109 ) + ( T1 ? ) + ( T2 /FPGA_Po39 ) + ( T3 ? ) + ( T4 ? ) + ( T5 /FPGA,_P221 ) + ( T6 ? ) + ( T7 ? ) + ( T8 ? ) + ( T9 VCCO2 ) + ( T10 ? ) + ( T11 ? ) + ( T12 ? ) + ( T13 VCCO2 ) + ( T14 ? ) + ( T15 ? ) + ( T16 ? ) + ( T17 ? ) + ( T18 ? ) + ( T19 ? ) + ( T20 ? ) + ( T21 /FPGA_Po33 ) + ( T22 ? ) + ( U1 /FPGA_Po111 ) + ( U2 GND ) + ( U3 /FPGA_Po110 ) + ( U4 ? ) + ( U5 +2.5V ) + ( U6 ? ) + ( U7 GND ) + ( U8 ? ) + ( U9 ? ) + ( U10 ? ) + ( U11 +2.5V ) + ( U12 ? ) + ( U13 /FPGA,_P222 ) + ( U14 /FPGA,_P223 ) + ( U15 ? ) + ( U16 ? ) + ( U17 ? ) + ( U18 +2.5V ) + ( U19 ? ) + ( U20 /FPGA_Po98 ) + ( U21 GND ) + ( U22 /FPGA_Po99 ) + ( V1 /FPGA_Po113 ) + ( V2 /FPGA_Po112 ) + ( V3 ? ) + ( V4 GND ) + ( V5 ? ) + ( V6 +2.5V ) + ( V7 ? ) + ( V8 VCCO2 ) + ( V9 ? ) + ( V10 GND ) + ( V11 ? ) + ( V12 VCCO2 ) + ( V13 ? ) + ( V14 GND ) + ( V15 ? ) + ( V16 VCCO2 ) + ( V17 ? ) + ( V18 ? ) + ( V19 ? ) + ( V20 ? ) + ( V21 /FPGA_Po100 ) + ( V22 /FPGA_Po101 ) + ( W1 ? ) + ( W2 +2.5V ) + ( W3 ? ) + ( W4 ? ) + ( W5 VCCO2 ) + ( W6 ? ) + ( W7 GND ) + ( W8 ? ) + ( W9 ? ) + ( W10 ? ) + ( W11 ? ) + ( W12 ? ) + ( W13 ? ) + ( W14 ? ) + ( W15 ? ) + ( W16 GND ) + ( W17 ? ) + ( W18 ? ) + ( W19 GND ) + ( W20 ? ) + ( W21 +2.5V ) + ( W22 ? ) + ( Y1 ? ) + ( Y2 ? ) + ( Y3 ? ) + ( Y4 ? ) + ( Y5 ? ) + ( Y6 ? ) + ( Y7 ? ) + ( Y8 ? ) + ( Y9 ? ) + ( Y10 ? ) + ( Y11 ? ) + ( Y12 ? ) + ( Y13 ? ) + ( Y14 ? ) + ( Y15 ? ) + ( Y16 ? ) + ( Y17 ? ) + ( Y18 ? ) + ( Y19 ? ) + ( Y20 +3.3V ) + ( Y21 ? ) + ( Y22 N-000356 ) + ) + ( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG + ( 1 +2.5V ) + ( 2 /FPGA_Po141 ) + ( 3 +2.5V ) + ( 4 /FPGA_Po140 ) + ( 5 /FPGA_Po139 ) + ( 6 GND ) + ( 7 /DDR_Ban138 ) + ( 8 /FPGA_Po133 ) + ( 9 +2.5V ) + ( 10 /FPGA_Po132 ) + ( 11 /DDR_Ban131 ) + ( 12 GND ) + ( 13 /DDR_Ban130 ) + ( 14 ? ) + ( 15 +2.5V ) + ( 16 /DDR_Ban165 ) + ( 17 ? ) + ( 18 +2.5V ) + ( 19 ? ) + ( 20 /FPGA_Po164 ) + ( 21 /DDR_Ban163 ) + ( 22 /FPGA_Po162 ) + ( 23 /DDR_Ban157 ) + ( 24 GND ) + ( 25 ? ) + ( 26 /DDR_Ban156 ) + ( 27 /FPGA_Po155 ) + ( 28 /FPGA_Po154 ) + ( 29 /FPGA_Po149 ) + ( 30 /FPGA_Po148 ) + ( 31 /FPGA_Po147 ) + ( 32 /FPGA_Po146 ) + ( 33 +2.5V ) + ( 34 GND ) + ( 35 /DDR_Banks/M0_A4 ) + ( 36 /FPGA_Po170 ) + ( 37 /FPGA_Po171 ) + ( 38 /DDR_Banks/M0_A7 ) + ( 39 /FPGA_Po176 ) + ( 40 /FPGA_Po177 ) + ( 41 /FPGA_Po178 ) + ( 42 /FPGA_Po179 ) + ( 43 ? ) + ( 44 /FPGA_Po38 ) + ( 45 /DDR_Ban44 ) + ( 46 /FPGA_Po37 ) + ( 47 /FPGA_Po42 ) + ( 48 GND ) + ( 49 /DDR_Ban5 ) + ( 50 ? ) + ( 51 /DDR_Ban40 ) + ( 52 GND ) + ( 53 ? ) + ( 54 /DDR_Ban125 ) + ( 55 +2.5V ) + ( 56 /FPGA_Po124 ) + ( 57 /FPGA_Po123 ) + ( 58 GND ) + ( 59 /FPGA_Po122 ) + ( 60 /DDR_Ban117 ) + ( 61 +2.5V ) + ( 62 /DDR_Ban116 ) + ( 63 /FPGA_Po115 ) + ( 64 GND ) + ( 65 /DDR_Ban114 ) + ( 66 GND ) + ) + ( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG + ( 1 +2.5V ) + ( 2 /FPGA_Po81 ) + ( 3 +2.5V ) + ( 4 /FPGA_Po80 ) + ( 5 /FPGA_Po79 ) + ( 6 GND ) + ( 7 /FPGA_Po78 ) + ( 8 /FPGA_Po73 ) + ( 9 +2.5V ) + ( 10 /FPGA_Po72 ) + ( 11 /FPGA_Po71 ) + ( 12 GND ) + ( 13 /DDR_Ban70 ) + ( 14 ? ) + ( 15 +2.5V ) + ( 16 /DDR_Ban65 ) + ( 17 ? ) + ( 18 +2.5V ) + ( 19 ? ) + ( 20 /FPGA_Po64 ) + ( 21 /FPGA_Po63 ) + ( 22 /DDR_Ban62 ) + ( 23 /DDR_Ban57 ) + ( 24 /DDR_Ban36 ) + ( 25 ? ) + ( 26 /DDR_Ban56 ) + ( 27 /FPGA_Po55 ) + ( 28 /FPGA_Po54 ) + ( 29 /DDR_Banks/M1_A0 ) + ( 30 /DDR_Banks/M1_A1 ) + ( 31 /FPGA_Po49 ) + ( 32 /DDR_Banks/M1_A3 ) + ( 33 +2.5V ) + ( 34 GND ) + ( 35 /FPGA_Po83 ) + ( 36 /DDR_Banks/M1_A5 ) + ( 37 /FPGA_Po82 ) + ( 38 /DDR_Banks/M1_A7 ) + ( 39 /DDR_Banks/M1_A8 ) + ( 40 /DDR_Banks/M1_A9 ) + ( 41 /FPGA_Po89 ) + ( 42 /DDR_Ban88 ) + ( 43 ? ) + ( 44 /DDR_Ban27 ) + ( 45 /FPGA_Po30 ) + ( 46 /FPGA_Po28 ) + ( 47 /DDR_Ban32 ) + ( 48 GND ) + ( 49 /DDR_Ban6 ) + ( 50 ? ) + ( 51 /DDR_Ban34 ) + ( 52 GND ) + ( 53 ? ) + ( 54 /FPGA_Po105 ) + ( 55 +2.5V ) + ( 56 /FPGA_Po104 ) + ( 57 /FPGA_Po103 ) + ( 58 GND ) + ( 59 /FPGA_Po102 ) + ( 60 /FPGA_Po97 ) + ( 61 +2.5V ) + ( 62 /FPGA_Po96 ) + ( 63 /DDR_Ban95 ) + ( 64 GND ) + ( 65 /FPGA_Po94 ) + ( 66 GND ) + ) + ( /4C4320F3/4C432132 LQFP48 U4 K8001 + ( 1 /FPGA,_P24 ) + ( 2 /Etherne212 ) + ( 3 /FPGA,_P202 ) + ( 4 /FPGA,_P203 ) + ( 5 /Etherne181 ) + ( 6 /FPGA,_P195 ) + ( 7 +3.3V ) + ( 8 GND ) + ( 9 /FPGA,_P182 ) + ( 10 /Etherne183 ) + ( 11 /Etherne196 ) + ( 12 GND ) + ( 13 +1.8V ) + ( 14 /FPGA,_P213 ) + ( 15 /Etherne205 ) + ( 16 /FPGA,_P214 ) + ( 17 /FPGA,_P215 ) + ( 18 /FPGA,_P206 ) + ( 19 /FPGA,_P207 ) + ( 20 /FPGA,_P184 ) + ( 21 /Etherne185 ) + ( 22 /Etherne197 ) + ( 23 GND ) + ( 24 +3.3V ) + ( 25 /FPGA,_P186 ) + ( 26 /Etherne25 ) + ( 27 /Etherne26 ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 /Etherne1 ) + ( 32 /Etherne19 ) + ( 33 /Etherne18 ) + ( 34 ? ) + ( 35 GND ) + ( 36 GND ) + ( 37 N-000123 ) + ( 38 /Etherne2 ) + ( 39 GND ) + ( 40 /Etherne17 ) + ( 41 /Etherne16 ) + ( 42 ? ) + ( 43 ? ) + ( 44 GND ) + ( 45 ? ) + ( 46 /Etherne180 ) + ( 47 /Etherne3 ) + ( 48 /FPGA,_P204 ) + ) + ( /4C4227FE/4B76F108 NAND-48TSOP U5 NAND + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 /FPGA,_P191 ) + ( 7 /FPGA,_P191 ) + ( 8 /Non_vol211 ) + ( 9 /Non_vol218 ) + ( 10 ? ) + ( 11 ? ) + ( 12 +3.3V ) + ( 13 GND ) + ( 14 ? ) + ( 15 ? ) + ( 16 /FPGA,_P199 ) + ( 17 /FPGA,_P190 ) + ( 18 /Non_vol210 ) + ( 19 +3.3V ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 ? ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 ? ) + ( 29 /Non_vol209 ) + ( 30 /FPGA,_P217 ) + ( 31 /FPGA,_P189 ) + ( 32 /FPGA,_P198 ) + ( 33 ? ) + ( 34 ? ) + ( 35 ? ) + ( 36 GND ) + ( 37 +3.3V ) + ( 38 ? ) + ( 39 ? ) + ( 40 ? ) + ( 41 /FPGA,_P188 ) + ( 42 /FPGA,_P208 ) + ( 43 /FPGA,_P187 ) + ( 44 /FPGA,_P216 ) + ( 45 ? ) + ( 46 ? ) + ( 47 ? ) + ( 48 ? ) + ) + ( /4C5F1EDC/4C71BA1D MLF16 U6 MIC2550-MLF + ( 1 /FPGA_Po220 ) + ( 2 /USB/USBA_RCV ) + ( 3 /USB/USBA_VP ) + ( 4 /FPGA_Po219 ) + ( 6 GND ) + ( 7 GND ) + ( 9 /USB/USBA_OE_N ) + ( 10 /USB/USBA_D- ) + ( 11 /USB/USBA_D+ ) + ( 12 +3.3V ) + ( 14 +3.3V ) + ( 15 +2.5V ) + ) + ( /4C5F1EDC/4C71BA25 MLF16 U7 MIC2550-MLF + ( 1 /FPGA_Po200 ) + ( 2 /USB/USBD_RCV ) + ( 3 /USB/USBD_VP ) + ( 4 /FPGA_Po201 ) + ( 6 GND ) + ( 7 GND ) + ( 9 /USB/USBD_OE_N ) + ( 10 /USB/USBD_D- ) + ( 11 /USB/USBD_D+ ) + ( 12 +3.3V ) + ( 14 +3.3V ) + ( 15 +2.5V ) + ) + ( /4C4227FE/4C65A75D SO8E U8 X25X64MB + ( 1 /FPGA,_P221 ) + ( 2 /FPGA,_P192 ) + ( 3 /FPGA,_P223 ) + ( 4 GND ) + ( 5 /FPGA,_P194 ) + ( 6 /FPGA,_P193 ) + ( 7 /FPGA,_P222 ) + ( 8 VCCO2 ) + ) + ( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF + ( 1 ? ) + ( 2 ? ) + ( 3 /PSU/Iout_1.2 ) + ( 4 /PSU/Iout_3.3 ) + ( 5 ? ) + ( 6 ? ) + ( 7 ? ) + ( 8 GND ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 ? ) + ( 13 ? ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ( 17 ? ) + ( 18 ? ) + ( 19 ? ) + ( 20 ? ) + ( PAD GND ) + ) + ( /4C69ED5F/4C6C9DB9 DFN10 U10 A7130 + ( 1 N-000148 ) + ( 2 GND ) + ( 3 /PSU/SW_1.2 ) + ( 4 /PSU/SW_1.2 ) + ( 5 GND ) + ( 6 N-000156 ) + ( 7 N-000156 ) + ( 8 N-000156 ) + ( 9 /PSU/VFB2.5 ) + ( 10 N-000150 ) + ( PAD GND ) + ) + ( /4C69ED5F/4C6D2AA5 SOT23-5 U11 A7108 + ( 1 /PSU/VIN7 ) + ( 2 GND ) + ( 3 /PSU/SW_3.3 ) + ( 4 /PSU/VIN7 ) + ( 5 /PSU/VFB3.3 ) + ) + ( /4C69ED5F/4C6D2AE0 SOT23-5 U12 A7108 + ( 1 /PSU/VIN8 ) + ( 2 GND ) + ( 3 /PSU/SW_1.2 ) + ( 4 /PSU/VIN8 ) + ( 5 /PSU/VFB1.2 ) + ) + ( /4C69ED5F/4C7705B0 MLP6 U13 FAN4010 + ( 1 N-000143 ) + ( 2 ? ) + ( 3 /PSU/Iout_3.3 ) + ( 5 GND ) + ( 6 /PSU/VIN7 ) + ) + ( /4C69ED5F/4C770714 MLP6 U14 FAN4010 + ( 1 N-000160 ) + ( 2 ? ) + ( 3 /PSU/Iout_1.2 ) + ( 5 GND ) + ( 6 /PSU/VIN8 ) + ) + ( /4C69ED5F/4C79C65B SOT23_6 U15 A7117 + ( 1 N-000151 ) + ( 2 GND ) + ( 3 /PSU/VFB1.2 ) + ( 4 N-000157 ) + ( 5 +5V ) + ( 6 /PSU/VIN9 ) + ) + ( /4C69ED5F/4C79C99A MLP6 U16 FAN4010 + ( 1 N-000144 ) + ( 2 ? ) + ( 3 /PSU/Iout_5.0 ) + ( 5 GND ) + ( 6 ? ) + ) + ( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 + ( 1 /USB/USBA_D+ ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 + ( 1 /USB/USBA_D- ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C6552B8 0603 V3 V0402MHS03 + ( 1 /USB/USBD_D+ ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C6552B9 0603 V4 V0402MHS03 + ( 1 /USB/USBD_D- ) + ( 2 GND ) ) ) * { Allowed footprints by component: -$component C94 +$component C1 SM* C? C1-1 $endlist -$component C92 +$component C2 SM* C? C1-1 $endlist -$component C93 +$component C3 SM* C? C1-1 $endlist -$component C91 +$component C4 SM* C? C1-1 $endlist -$component C90 +$component C5 SM* C? C1-1 $endlist -$component R30 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R29 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C77 +$component C6 SM* C? C1-1 $endlist -$component C76 +$component C7 SM* C? C1-1 $endlist -$component C66 +$component C8 SM* C? C1-1 $endlist -$component C63 +$component C9 SM* C? C1-1 $endlist -$component C60 +$component C10 SM* C? C1-1 $endlist -$component C57 +$component C11 SM* C? C1-1 $endlist -$component C54 +$component C12 SM* C? C1-1 $endlist -$component C69 +$component C13 SM* C? C1-1 $endlist -$component C67 +$component C14 SM* C? C1-1 $endlist -$component C64 +$component C15 SM* C? C1-1 $endlist -$component C61 +$component C16 SM* C? C1-1 $endlist -$component C58 +$component C17 SM* C? C1-1 $endlist -$component C55 +$component C18 SM* C? C1-1 $endlist -$component C68 +$component C19 SM* C? C1-1 $endlist -$component C65 +$component C20 SM* C? C1-1 $endlist -$component C62 +$component C21 SM* C? C1-1 $endlist -$component C59 +$component C22 SM* C? C1-1 $endlist -$component C56 +$component C23 SM* C? C1-1 $endlist -$component C50 +$component C24 SM* C? C1-1 $endlist -$component C47 +$component C25 SM* C? C1-1 $endlist -$component C44 +$component C26 SM* C? C1-1 $endlist -$component C41 +$component C27 SM* C? C1-1 $endlist -$component C53 +$component C28 SM* C? C1-1 $endlist -$component C51 +$component C29 SM* C? C1-1 $endlist -$component C49 +$component C30 SM* C? C1-1 $endlist -$component C46 +$component C31 SM* C? C1-1 $endlist -$component C52 +$component C32 SM* C? C1-1 $endlist -$component C43 +$component C33 SM* C? C1-1 $endlist -$component C40 - SM* - C? - C1-1 -$endlist -$component C48 - SM* - C? - C1-1 -$endlist -$component C45 - SM* - C? - C1-1 -$endlist -$component C42 - SM* - C? - C1-1 -$endlist -$component C39 - SM* - C? - C1-1 -$endlist -$component R23 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R22 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R24 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R21 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R19 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R20 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R17 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R18 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R16 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C95 - SM* - C? - C1-1 -$endlist -$component R35 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R36 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C98 - SM* - C? - C1-1 -$endlist -$component R39 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R38 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C97 - SM* - C? - C1-1 -$endlist -$component C96 - SM* - C? - C1-1 -$endlist -$component R37 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R34 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R33 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R31 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R32 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C82 - SM* - C? - C1-1 -$endlist -$component C83 - SM* - C? - C1-1 -$endlist -$component C84 - SM* - C? - C1-1 -$endlist -$component R27 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R28 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C85 - SM* - C? - C1-1 -$endlist -$component C81 - SM* - C? - C1-1 -$endlist -$component R26 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R25 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C80 - SM* - C? - C1-1 -$endlist -$component C79 - SM* - C? - C1-1 -$endlist -$component C78 - SM* - C? - C1-1 -$endlist -$component C75 - SM* - C? - C1-1 -$endlist -$component C74 - SM* - C? - C1-1 -$endlist -$component C73 - SM* - C? - C1-1 -$endlist -$component C72 +$component C34 SM* C? C1-1 @@ -2112,151 +1908,160 @@ $component C38 C? C1-1 $endlist -$component R15 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R10 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C16 +$component C39 SM* C? C1-1 $endlist -$component C15 +$component C40 SM* C? C1-1 $endlist -$component C14 +$component C41 SM* C? C1-1 $endlist -$component C13 +$component C42 SM* C? C1-1 $endlist -$component C9 +$component C43 SM* C? C1-1 $endlist -$component C6 +$component C44 SM* C? C1-1 $endlist -$component C4 +$component C45 SM* C? C1-1 $endlist -$component C2 +$component C46 SM* C? C1-1 $endlist -$component C8 +$component C47 SM* C? C1-1 $endlist -$component C7 +$component C48 SM* C? C1-1 $endlist -$component C5 +$component C49 SM* C? C1-1 $endlist -$component C3 +$component C50 SM* C? C1-1 $endlist -$component C1 +$component C51 SM* C? C1-1 $endlist -$component R1 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R2 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C11 +$component C52 SM* C? C1-1 $endlist -$component C10 +$component C53 SM* C? C1-1 $endlist -$component C12 +$component C54 SM* C? C1-1 $endlist -$component R9 - R? - SM0603 - SM0805 - R?-* +$component C55 + SM* + C? + C1-1 $endlist -$component R3 - R? - SM0603 - SM0805 - R?-* +$component C56 + SM* + C? + C1-1 $endlist -$component R4 - R? - SM0603 - SM0805 - R?-* +$component C57 + SM* + C? + C1-1 $endlist -$component R6 - R? - SM0603 - SM0805 - R?-* +$component C58 + SM* + C? + C1-1 $endlist -$component R5 - R? - SM0603 - SM0805 - R?-* +$component C59 + SM* + C? + C1-1 $endlist -$component R8 - R? - SM0603 - SM0805 - R?-* +$component C60 + SM* + C? + C1-1 $endlist -$component R7 - R? - SM0603 - SM0805 - R?-* +$component C61 + SM* + C? + C1-1 +$endlist +$component C62 + SM* + C? + C1-1 +$endlist +$component C63 + SM* + C? + C1-1 +$endlist +$component C64 + SM* + C? + C1-1 +$endlist +$component C65 + SM* + C? + C1-1 +$endlist +$component C66 + SM* + C? + C1-1 +$endlist +$component C67 + SM* + C? + C1-1 +$endlist +$component C68 + SM* + C? + C1-1 +$endlist +$component C69 + SM* + C? + C1-1 $endlist $component C70 SM* @@ -2268,1413 +2073,360 @@ $component C71 C? C1-1 $endlist -$component C34 +$component C72 SM* C? C1-1 $endlist -$component C33 +$component C73 SM* C? C1-1 $endlist -$component C28 +$component C74 SM* C? C1-1 $endlist -$component C29 +$component C75 SM* C? C1-1 $endlist -$component C31 +$component C76 SM* C? C1-1 $endlist -$component C30 +$component C77 SM* C? C1-1 $endlist -$component C32 +$component C78 SM* C? C1-1 $endlist -$component C27 +$component C79 SM* C? C1-1 $endlist -$component C21 +$component C80 SM* C? C1-1 $endlist -$component C26 +$component C81 SM* C? C1-1 $endlist -$component C24 +$component C82 SM* C? C1-1 $endlist -$component C25 +$component C83 SM* C? C1-1 $endlist -$component C23 +$component C84 SM* C? C1-1 $endlist -$component C22 +$component C85 SM* C? C1-1 $endlist -$component R13 +$component C90 + SM* + C? + C1-1 +$endlist +$component C91 + SM* + C? + C1-1 +$endlist +$component C92 + SM* + C? + C1-1 +$endlist +$component C93 + SM* + C? + C1-1 +$endlist +$component C94 + SM* + C? + C1-1 +$endlist +$component C95 + SM* + C? + C1-1 +$endlist +$component C96 + SM* + C? + C1-1 +$endlist +$component C97 + SM* + C? + C1-1 +$endlist +$component C98 + SM* + C? + C1-1 +$endlist +$component C99 + SM* + C? + C1-1 +$endlist +$component C100 + SM* + C? + C1-1 +$endlist +$component C101 + SM* + C? + C1-1 +$endlist +$component C102 + SM* + C? + C1-1 +$endlist +$component C103 + SM* + C? + C1-1 +$endlist +$component R1 R? SM0603 SM0805 - R?-* $endlist -$component R14 +$component R2 R? SM0603 SM0805 - R?-* $endlist -$component R12 +$component R3 + R? + SM0603 + SM0805 +$endlist +$component R4 + R? + SM0603 + SM0805 +$endlist +$component R5 + R? + SM0603 + SM0805 +$endlist +$component R6 + R? + SM0603 + SM0805 +$endlist +$component R7 + R? + SM0603 + SM0805 +$endlist +$component R8 + R? + SM0603 + SM0805 +$endlist +$component R9 + R? + SM0603 + SM0805 +$endlist +$component R10 R? SM0603 SM0805 - R?-* $endlist $component R11 R? SM0603 SM0805 - R?-* $endlist -$component C19 - SM* - C? - C1-1 +$component R12 + R? + SM0603 + SM0805 $endlist -$component C20 - SM* - C? - C1-1 +$component R13 + R? + SM0603 + SM0805 $endlist -$component C18 - SM* - C? - C1-1 +$component R14 + R? + SM0603 + SM0805 $endlist -$component C17 - SM* - C? - C1-1 +$component R15 + R? + SM0603 + SM0805 +$endlist +$component R16 + R? + SM0603 + SM0805 +$endlist +$component R17 + R? + SM0603 + SM0805 +$endlist +$component R18 + R? + SM0603 + SM0805 +$endlist +$component R19 + R? + SM0603 + SM0805 +$endlist +$component R20 + R? + SM0603 + SM0805 +$endlist +$component R21 + R? + SM0603 + SM0805 +$endlist +$component R22 + R? + SM0603 + SM0805 +$endlist +$component R23 + R? + SM0603 + SM0805 +$endlist +$component R24 + R? + SM0603 + SM0805 +$endlist +$component R25 + R? + SM0603 + SM0805 +$endlist +$component R26 + R? + SM0603 + SM0805 +$endlist +$component R27 + R? + SM0603 + SM0805 +$endlist +$component R28 + R? + SM0603 + SM0805 +$endlist +$component R29 + R? + SM0603 + SM0805 +$endlist +$component R30 + R? + SM0603 + SM0805 +$endlist +$component R31 + R? + SM0603 + SM0805 +$endlist +$component R32 + R? + SM0603 + SM0805 +$endlist +$component R33 + R? + SM0603 + SM0805 +$endlist +$component R34 + R? + SM0603 + SM0805 +$endlist +$component R35 + R? + SM0603 + SM0805 +$endlist +$component R36 + R? + SM0603 + SM0805 +$endlist +$component R37 + R? + SM0603 + SM0805 +$endlist +$component R38 + R? + SM0603 + SM0805 +$endlist +$component R39 + R? + SM0603 + SM0805 +$endlist +$component R40 + R? + SM0603 + SM0805 +$endlist +$component R41 + R? + SM0603 + SM0805 +$endlist +$component R42 + R? + SM0603 + SM0805 +$endlist +$component R43 + R? + SM0603 + SM0805 $endlist $endfootprintlist } -{ Pin List by Nets -Net 1 "/USB/USBA_OE_N" "USBA_OE_N" - U6 9 - U1 C19 -Net 2 "/FPGA, Port0, Port2, PROG IF/PROG_CSO" "PROG_CSO" - U1 T5 - U8 1 -Net 3 "/FPGA, Port0, Port2, PROG IF/PROG_CCLK" "PROG_CCLK" - U8 6 - U1 AA21 -Net 4 "/Non volatile memories/NF_RNB" "NF_RNB" - U1 A15 - U5 6 - U5 7 -Net 5 "/Non volatile memories/NF_WE_N" "NF_WE_N" - U5 18 - U1 C14 -Net 6 "/Non volatile memories/NF_CLE" "NF_CLE" - U5 16 - U1 B14 -Net 7 "/Ethernet Phy/ETH_TXC" "ETH_TXC" - U4 15 - U1 C8 -Net 8 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" - U1 A6 - U4 9 -Net 9 "/Ethernet Phy/ETH_MDC" "ETH_MDC" - U4 2 - U1 D7 -Net 10 "/Ethernet Phy/ETH_CRS" "ETH_CRS" - U4 22 - U1 B10 -Net 11 "/FPGA, Port0, Port2, PROG IF/ETH_RESET_N" "ETH_RESET_N" - U4 48 - U1 C7 -Net 12 "/USB/USBD_VP" "USBD_VP" - U7 3 - U1 B21 -Net 13 "/USB/USBD_OE_N" "USBD_OE_N" - U7 9 - U1 A21 -Net 14 "/FPGA Port 1, Port 3 (DDR, USB)/USBA_VP" "USBA_VP" - U6 3 - U1 D19 -Net 15 "/FPGA, Port0, Port2, PROG IF/ETH_CLK" "ETH_CLK" - U1 A4 - U4 46 -Net 16 "/FPGA, Port0, Port2, PROG IF/ETH_TXEN" "ETH_TXEN" - U4 16 - U1 D9 -Net 17 "/Ethernet Phy/ETH_INT" "ETH_INT" - U4 25 - U1 A10 -Net 18 "/FPGA Port 1, Port 3 (DDR, USB)/M1_UDQS" "M1_UDQS" - R19 2 - U3 51 -Net 19 "/FPGA Port 1, Port 3 (DDR, USB)/M1_LDQS" "M1_LDQS" - U3 16 - RP3 8 -Net 20 "/FPGA Port 1, Port 3 (DDR, USB)/M1_UDM" "M1_UDM" - U3 47 - R18 2 -Net 21 "/FPGA Port 1, Port 3 (DDR, USB)/M1_WE#" "M1_WE#" - RP3 6 - U3 21 -Net 22 "/FPGA Port 1, Port 3 (DDR, USB)/M1_RAS#" "M1_RAS#" - RP2 8 - U3 23 -Net 23 "GND" "GND" - C2 2 - C8 2 - C7 2 - C5 2 - C9 2 - V2 2 - V1 2 - C16 2 - R10 2 - C14 2 - C15 2 - U6 7 - U6 6 - C38 2 - V3 2 - V4 2 - C37 2 - C36 2 - C35 2 - C13 2 - C29 2 - C28 2 - C33 2 - C23 2 - C25 2 - C24 2 - C26 2 - C21 2 - C4 2 - C6 2 - C66 2 - C32 2 - C30 2 - C31 2 - U7 6 - U7 7 - U1 J15 - U1 E15 - U1 V14 - U1 P14 - U1 M14 - U1 K14 - L5 2 - L7 2 - R15 2 - U2 58 - U2 48 - C75 1 - C74 2 - J1 CASE - J1 CASE - J1 CASE - J1 COM - C45 2 - J1 6 - U8 4 - C73 2 - C72 2 - U2 6 - U5 13 - C77 2 - C76 2 - C50 2 - U5 36 - C47 2 - C41 2 - C44 2 - U4 12 - U4 8 - C34 2 - U4 44 - C71 2 - C70 2 - U4 35 - U4 36 - C63 2 - C11 2 - R2 2 - C1 2 - C3 2 - U2 34 - U2 24 - C10 2 - C12 2 - R9 2 - C27 2 - U4 23 - U3 58 - C18 2 - C20 2 - R12 2 - U4 39 - R14 2 - C22 2 - U2 52 - U2 12 - C60 2 - J4 5 - U2 66 - J4 4 - U2 64 - U1 E11 - U14 5 - U1 V10 - U1 P10 - U1 M10 - U15 2 - U1 K10 - U1 N9 - C82 2 - C94 2 - C97 2 - R38 2 - C98 2 - U1 L9 - U11 2 - U9 PAD - U1 J9 - U3 52 - U9 8 - U3 12 - U3 48 - C81 2 - U3 66 - C52 2 - U10 PAD - U10 5 - U3 64 - U10 2 - U3 34 - C55 2 - C68 2 - C42 2 - C90 2 - C91 2 - C93 2 - C92 2 - C65 2 - C62 2 - U13 5 - C59 2 - C40 2 - C48 2 - C57 2 - C54 2 - C39 2 - C69 2 - C67 2 - C43 2 - C64 2 - C61 2 - C58 2 - R33 2 - U1 N11 - U1 L11 - R27 2 - U1 J11 - C84 2 - C56 2 - U1 B9 - U1 W7 - U1 U7 - U1 H7 - U1 E7 - R31 2 - U1 R5 - U1 L5 - U1 G5 - U1 B5 - U1 V4 - U1 D4 - U1 U2 - U1 N2 - U1 J2 - U1 E2 - U1 A1 - U1 AB1 - U1 U21 - U1 N21 - U1 J21 - U1 N13 - U1 L13 - U1 J13 - U1 B13 - U1 A22 - U1 P12 - U1 M12 - U1 K12 - U1 E21 - U1 D18 - U1 N15 - U1 N17 - U16 5 - R35 2 - U1 AA5 - C95 2 - U1 W16 - U1 B17 - C53 2 - R25 2 - U3 6 - C46 2 - C49 2 - C85 2 - U12 2 - C78 2 - C51 2 - C80 2 - U1 AA17 - U1 AA13 - U1 AB22 - U1 AA9 - U1 W19 - U1 R18 - U1 L18 - U1 G18 -Net 24 "/DDR Banks/M0_RAS#" "M0_RAS#" - U2 23 - RP15 8 -Net 25 "/FPGA Port 1, Port 3 (DDR, USB)/M0_LDQS" "M0_LDQS" - RP16 8 - U2 16 -Net 26 "/FPGA Port 1, Port 3 (DDR, USB)/M0_LDM" "M0_LDM" - U2 20 - RP16 7 -Net 27 "/FPGA Port 1, Port 3 (DDR, USB)/M1_CLK" "M1_CLK" - R16 2 - U1 H20 - U3 46 -Net 28 "/FPGA, Port0, Port2, PROG IF/SD_CMD" "SD_CMD" - J1 3 - U1 C16 -Net 29 "/DBG_PRG/FPGA_TMS" "FPGA_TMS" - U1 C18 - J6 3 -Net 30 "/DBG_PRG/FPGA_TDI" "FPGA_TDI" - J6 7 - U1 E18 -Net 31 "/FPGA Port 1, Port 3 (DDR, USB)/M0_WE#" "M0_WE#" - RP16 6 - U2 21 -Net 32 "/FPGA Port 1, Port 3 (DDR, USB)/M0_CAS#" "M0_CAS#" - RP16 5 - U2 22 -Net 33 "/FPGA Port 1, Port 3 (DDR, USB)/M0_UDQS" "M0_UDQS" - R22 2 - U2 51 -Net 34 "/DDR Banks/M0_UDM" "M0_UDM" - R23 2 - U2 47 -Net 35 "/FPGA Port 1, Port 3 (DDR, USB)/M0_CKE" "M0_CKE" - R24 2 - U2 45 -Net 36 "/FPGA Port 1, Port 3 (DDR, USB)/USBD_VM" "USBD_VM" - U7 4 - U1 B22 -Net 37 "/FPGA Port 1, Port 3 (DDR, USB)/USBD_RCV" "USBD_RCV" - U7 2 - U1 A20 -Net 38 "/USB/USBD_SPD" "USBD_SPD" - U7 1 - U1 B20 -Net 39 "/FPGA, Port0, Port2, PROG IF/ETH_MDIO" "ETH_MDIO" - U4 1 - U1 D6 - R1 1 -Net 40 "/USB/USBA_SPD" "USBA_SPD" - U1 F16 - U6 1 -Net 41 "/FPGA Port 1, Port 3 (DDR, USB)/USBA_RCV" "USBA_RCV" - U6 2 - U1 F17 -Net 42 "/USB/USBA_VM" "USBA_VM" - U6 4 - U1 D20 -Net 43 "/DDR Banks/M1_CS#" "M1_CS#" - U3 24 - R20 2 -Net 44 "/DDR Banks/M1_CAS#" "M1_CAS#" - RP3 5 - U3 22 -Net 45 "/FPGA Port 1, Port 3 (DDR, USB)/M1_CKE" "M1_CKE" - R17 2 - U3 45 -Net 46 "/FPGA Port 1, Port 3 (DDR, USB)/M1_LDM" "M1_LDM" - U3 20 - RP3 7 -Net 47 "/Non volatile memories/NF_ALE" "NF_ALE" - U5 17 - U1 A14 -Net 48 "/FPGA, Port0, Port2, PROG IF/ETH_COL" "ETH_COL" - U1 A9 - U4 21 -Net 49 "/DBG_PRG/FPGA_TDO" "FPGA_TDO" - J6 5 - U1 A19 -Net 50 "/DBG_PRG/FPGA_TCK" "FPGA_TCK" - J6 1 - U1 G15 -Net 51 "/FPGA, Port0, Port2, PROG IF/ETH_RXER" "ETH_RXER" - U4 11 - U1 B8 -Net 52 "/Ethernet Phy/ETH_TXER" "ETH_TXER" - U4 14 - U1 D8 -Net 53 "/FPGA, Port0, Port2, PROG IF/ETH_RXC" "ETH_RXC" - U4 10 - U1 A7 -Net 54 "/Non volatile memories/SD_CLK" "SD_CLK" - J1 5 - U1 A17 -Net 55 "/FPGA, Port0, Port2, PROG IF/NF_RE_N" "NF_RE_N" - U5 8 - U1 C15 -Net 56 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" - U5 9 - U1 D15 -Net 57 "/DDR Banks/M0_CLK#" "M0_CLK#" - U2 44 - R21 2 - U1 H3 -Net 58 "/FPGA Port 1, Port 3 (DDR, USB)/M0_CLK" "M0_CLK" - U2 46 - U1 H4 - R21 1 -Net 59 "/DDR Banks/M1_CLK#" "M1_CLK#" - U3 44 - R16 1 - U1 J19 -Net 64 "+2.5V" "+2.5V" - C77 1 - C52 1 - U3 55 - U3 3 - U3 9 - C53 1 - U3 1 - C51 1 - C46 1 - C37 1 - C49 1 - U3 61 - U1 R10 - U3 18 - U1 H9 - U3 33 - U3 15 - U1 H15 - U1 K15 - U1 M15 - U1 D16 - U7 15 - C54 1 - U1 G12 - U1 R12 - C15 1 - U6 15 - C40 1 - U1 U11 - C68 1 - C17 1 - U1 C21 - C34 1 - C71 1 - C70 1 - U1 G21 - U1 L21 - C25 1 - C24 1 - U1 L16 - C26 1 - C21 1 - U2 18 - U1 C2 - C57 1 - U1 F4 - U1 L7 - U1 E19 - U1 U18 - U2 55 - U1 N18 - U2 15 - C19 1 - U1 J18 - R11 1 - U2 1 - U2 3 - U2 9 - U1 J5 - U1 N5 - U1 U5 - U1 W21 - U1 F6 - R13 1 - U1 W2 - U1 R21 - U1 R2 - U1 L2 - U2 33 - U1 G2 - C60 1 - U2 61 - C32 1 - U1 F11 - C30 1 - C31 1 - C29 1 - U1 R6 - U1 V6 - U1 L8 - U1 N8 - C56 1 - C28 1 - C59 1 - C62 1 - C65 1 - C33 1 - C66 1 - C94 1 - C63 1 - C27 1 - C43 1 - C23 1 - C22 1 -Net 67 "/DDR Banks/M0_VREF" "M0_VREF" - C18 1 - U2 49 - R11 2 - R12 1 - C17 2 -Net 68 "/DDR Banks/M1_VREF" "M1_VREF" - R14 1 - R13 2 - C20 1 - C19 2 - U3 49 -Net 107 "+3.3V" "+3.3V" - U1 Y20 - U1 B7 - U5 37 - U1 B19 - C91 1 - C50 1 - U6 14 - U6 12 - U1 G10 - C5 1 - C3 1 - R26 1 - L8 1 - C81 1 - C35 1 - C13 1 - C36 1 - C79 1 - C80 1 - U5 19 - C14 1 - L2 1 - U5 12 - U1 E9 - C41 1 - R5 1 - J1 4 - U1 B11 - U1 E17 - R29 1 - C74 1 - C75 2 - U7 14 - U7 12 - C1 1 - C90 1 - R1 2 - C11 1 - U1 B15 - U1 G14 - C10 1 - U1 E13 - U4 24 - U1 B4 - C44 1 - C47 1 - C73 1 - C72 1 - R3 1 - R4 1 - R6 1 - R30 1 - J4 3 - J4 6 - J4 9 - J4 11 - U4 7 -Net 108 "VCCO2" "VCCO2" - U8 8 - C61 1 - C64 1 - C58 1 - C55 1 - U1 AA19 - U1 V16 - U1 AA7 - U1 V8 - U1 W5 - U1 AA3 - U1 T13 - U1 V12 - U1 T9 - C69 1 - U1 AA11 - U1 AA15 - C67 1 -Net 109 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - L1 2 - C6 1 - U4 31 - L3 1 -Net 110 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - L3 2 - U4 47 - C9 1 -Net 111 "+1.8V" "+1.8V" - C2 1 - C4 1 - L1 1 - U4 13 -Net 112 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - U4 26 - R7 2 -Net 113 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - R8 2 - U4 27 -Net 115 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - C8 1 - L2 2 - U4 38 - C7 1 -Net 117 "" "" - J4 10 - R7 1 -Net 118 "" "" - J4 12 - R8 1 -Net 119 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD" - J4 14 - J4 13 - R9 1 - C12 1 -Net 123 "" "" - U4 37 - R2 1 -Net 126 "/Ethernet Phy/MAG_RX-" "MAG_RX-" - U4 32 - R6 2 - J4 8 -Net 127 "/Ethernet Phy/MAG_RX+" "MAG_RX+" - U4 33 - R5 2 - J4 7 -Net 128 "/Ethernet Phy/MAG_TX+" "MAG_TX+" - J4 1 - R3 2 - U4 41 -Net 129 "/Ethernet Phy/MAG_TX-" "MAG_TX-" - J4 2 - R4 2 - U4 40 -Net 130 "" "" - J5 S1 - R10 1 - J5 S4 - J5 S3 - C16 1 - J5 S2 -Net 131 "" "" - J5 4 - L5 1 -Net 132 "" "" - J7 9 - C38 1 - J7 8 - J7 7 - R15 1 - J7 6 -Net 133 "+5V" "+5V" - R39 1 - C97 1 - C96 1 - F1 2 - U15 5 - C98 1 -Net 134 "" "" - L4 1 - F1 1 -Net 135 "" "" - J5 1 - L4 2 -Net 136 "" "" - J7 4 - J7 5 -Net 137 "" "" - J7 1 - L7 1 -Net 138 "/USB/USBA_D-" "USBA_D-" - V2 1 - J5 2 - U6 10 - V2 1 -Net 139 "/USB/USBA_D+" "USBA_D+" - V1 1 - V1 1 - U6 11 - J5 3 -Net 140 "/USB/USBD_D-" "USBD_D-" - U7 10 - J7 2 - V4 1 - V4 1 -Net 141 "/USB/USBD_D+" "USBD_D+" - U7 11 - V3 1 - V3 1 - J7 3 -Net 142 "" "" - R32 2 - U13 1 -Net 143 "" "" - U14 1 - R34 2 -Net 144 "/PSU/Iout_3.3" "Iout_3.3" - R31 1 - U13 3 - U9 4 -Net 145 "" "" - U15 1 - L10 1 -Net 146 "/PSU/VFB1.2" "VFB1.2" - U15 3 - R27 1 - C83 2 - C96 2 - R38 1 - R39 2 - R28 2 - U12 5 -Net 147 "+1.2V" "+1.2V" - C39 1 - C48 1 - C76 1 - U1 J12 - U1 L12 - U1 N12 - U1 K13 - U1 M13 - U1 P13 - U1 J14 - U1 L14 - U1 N14 - U1 R14 - U1 M11 - U1 P11 - U1 J8 - C92 1 - C93 1 - C42 1 - C45 1 - U1 K9 - U1 M9 - U1 P9 - U1 J10 - U1 L10 - U1 N10 - U1 K11 - C85 1 - L9 1 - R28 1 - C83 1 - C84 1 -Net 148 "" "" - R36 2 - U16 1 -Net 150 "/PSU/VIN_DC-DC-5.0" "VIN_DC-DC-5.0" - U16 6 - U15 6 - R37 2 - R36 1 - C95 1 - L10 2 -Net 152 "/PSU/Iout_5.0" "Iout_5.0" - U16 3 - R35 1 -Net 153 "" "" - U15 4 - R37 1 -Net 154 "/PSU/VFB3.3" "VFB3.3" - R25 1 - U11 5 - C79 2 - R26 2 -Net 155 "/PSU/Iout_1.2" "Iout_1.2" - U14 3 - U9 3 - R33 1 -Net 157 "/PSU/SW_1.2" "SW_1.2" - L9 2 - U12 3 -Net 158 "/PSU/SW_3.3" "SW_3.3" - U11 3 - L8 2 -Net 185 "/PSU/VIN_DC-DC-3.3" "VIN_DC-DC-3.3" - U13 6 - R32 1 - U11 4 - C78 1 - U11 1 -Net 186 "/PSU/VIN_DC-DC-1.2" "VIN_DC-DC-1.2" - U14 6 - U12 4 - R34 1 - C82 1 - U12 1 -Net 202 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_UDM" "R_M1_UDM" - U1 M20 - R18 1 -Net 203 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A5" "R_M1_A5" - U1 K20 - RP6 6 -Net 204 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A3" "R_M1_A3" - RP1 4 - U1 G20 -Net 205 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A4" "R_M1_A4" - U1 F20 - RP6 5 -Net 206 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A7" "R_M1_A7" - RP6 8 - U1 E20 -Net 207 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A8" "R_M1_A8" - U1 C20 - RP7 5 -Net 212 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A0" "R_M1_A0" - U1 F21 - RP1 1 -Net 237 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_BA0" "R_M1_BA0" - U1 J17 - RP2 2 -Net 238 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_BA1" "R_M1_BA1" - RP2 3 - U1 K17 -Net 247 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A11" "R_M1_A11" - RP7 7 - U1 F19 -Net 248 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A10" "R_M1_A10" - U1 G19 - RP2 4 -Net 249 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A6" "R_M1_A6" - U1 K19 - RP6 7 -Net 256 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A9" "R_M1_A9" - RP7 6 - U1 C22 -Net 257 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A12" "R_M1_A12" - RP7 8 - U1 D22 -Net 258 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A2" "R_M1_A2" - RP1 3 - U1 E22 -Net 259 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_A1" "R_M1_A1" - U1 F22 - RP1 2 -Net 270 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_BA0" "R_M0_BA0" - U1 G3 - RP15 2 -Net 271 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_WE#" "R_M0_WE#" - U1 F2 - RP16 3 -Net 272 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_LDM" "R_M0_LDM" - U1 L4 - RP16 2 -Net 273 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_LDQS" "R_M0_LDQS" - U1 L3 - RP16 1 -Net 274 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A4" "R_M0_A4" - U1 F3 - RP17 4 -Net 275 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A6" "R_M0_A6" - U1 J4 - RP17 2 -Net 276 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A7" "R_M0_A7" - U1 H6 - RP17 1 -Net 277 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A5" "R_M0_A5" - U1 K3 - RP17 3 -Net 278 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A9" "R_M0_A9" - RP18 3 - U1 E1 -Net 279 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A12" "R_M0_A12" - RP18 1 - U1 D1 -Net 280 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A10" "R_M0_A10" - RP15 4 - U1 G4 -Net 281 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A8" "R_M0_A8" - RP18 4 - U1 E3 -Net 282 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ11" "R_M0_DQ11" - U1 R1 - RP11 4 -Net 283 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ9" "R_M0_DQ9" - RP11 2 - U1 P1 -Net 284 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ1" "R_M0_DQ1" - U1 N1 - RP13 2 -Net 285 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ3" "R_M0_DQ3" - U1 M1 - RP13 4 -Net 286 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ10" "R_M0_DQ10" - RP11 3 - U1 R3 -Net 287 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A11" "R_M0_A11" - U1 C1 - RP18 2 -Net 288 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_RAS#" "R_M0_RAS#" - RP15 1 - U1 K5 -Net 289 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_CAS#" "R_M0_CAS#" - RP16 4 - U1 K4 -Net 290 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_BA1" "R_M0_BA1" - RP15 3 - U1 G1 -Net 291 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_LDQS" "R_M1_LDQS" - U1 L20 - RP3 1 -Net 292 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_LDM" "R_M1_LDM" - RP3 2 - U1 L19 -Net 293 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_WE#" "R_M1_WE#" - RP3 3 - U1 H19 -Net 294 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ12" "R_M0_DQ12" - RP10 1 - U1 U3 -Net 295 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ14" "R_M0_DQ14" - RP10 3 - U1 V2 -Net 296 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_CKE" "R_M0_CKE" - U1 D2 - R24 1 -Net 297 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_UDQS" "R_M0_UDQS" - U1 T2 - R22 1 -Net 298 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_UDM" "R_M0_UDM" - U1 M3 - R23 1 -Net 299 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ6" "R_M0_DQ6" - RP12 3 - U1 K2 -Net 300 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ4" "R_M0_DQ4" - U1 J3 - RP12 1 -Net 301 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A0" "R_M0_A0" - U1 H2 - RP14 1 -Net 302 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A1" "R_M0_A1" - U1 H1 - RP14 2 -Net 303 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A3" "R_M0_A3" - RP14 4 - U1 K6 -Net 304 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_A2" "R_M0_A2" - U1 H5 - RP14 3 -Net 305 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ15" "R_M0_DQ15" - RP10 4 - U1 V1 -Net 306 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ13" "R_M0_DQ13" - U1 U1 - RP10 2 -Net 307 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ2" "R_M0_DQ2" - U1 M2 - RP13 3 -Net 308 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ0" "R_M0_DQ0" - RP13 1 - U1 N3 -Net 309 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ8" "R_M0_DQ8" - RP11 1 - U1 P2 -Net 310 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ5" "R_M0_DQ5" - RP12 2 - U1 J1 -Net 311 "/FPGA Port 1, Port 3 (DDR, USB)/R_M0_DQ7" "R_M0_DQ7" - RP12 4 - U1 K1 -Net 312 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_CAS#" "R_M1_CAS#" - U1 H22 - RP3 4 -Net 313 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_RAS#" "R_M1_RAS#" - RP2 1 - U1 H21 -Net 314 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ10" "R_M1_DQ10" - RP9 7 - U1 R20 -Net 315 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ11" "R_M1_DQ11" - RP9 8 - U1 R22 -Net 316 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ9" "R_M1_DQ9" - U1 P22 - RP9 6 -Net 317 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ12" "R_M1_DQ12" - U1 U20 - RP8 5 -Net 318 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ13" "R_M1_DQ13" - U1 U22 - RP8 6 -Net 319 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ15" "R_M1_DQ15" - RP8 8 - U1 V22 -Net 320 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ14" "R_M1_DQ14" - U1 V21 - RP8 7 -Net 321 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ6" "R_M1_DQ6" - RP4 3 - U1 K21 -Net 322 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ7" "R_M1_DQ7" - RP4 4 - U1 K22 -Net 323 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ5" "R_M1_DQ5" - U1 J22 - RP4 2 -Net 324 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ4" "R_M1_DQ4" - RP4 1 - U1 J20 -Net 325 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ8" "R_M1_DQ8" - RP9 5 - U1 P21 -Net 326 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ2" "R_M1_DQ2" - U1 M21 - RP5 3 -Net 327 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ3" "R_M1_DQ3" - RP5 4 - U1 M22 -Net 352 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_UDQS" "R_M1_UDQS" - R19 1 - U1 T21 -Net 353 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_CKE" "R_M1_CKE" - R17 1 - U1 D21 -Net 354 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_CS#" "R_M1_CS#" - R20 1 - U1 H16 -Net 355 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ1" "R_M1_DQ1" - RP5 2 - U1 N22 -Net 356 "/FPGA Port 1, Port 3 (DDR, USB)/R_M1_DQ0" "R_M1_DQ0" - U1 N20 - RP5 1 -Net 357 "" "" - U1 AA1 - R29 2 -Net 359 "" "" - R30 2 - U1 Y22 -Net 483 "/FPGA, Port0, Port2, PROG IF/PROG_MISO3" "PROG_MISO3" - U1 U13 - U8 7 -Net 484 "/FPGA, Port0, Port2, PROG IF/PROG_MISO2" "PROG_MISO2" - U8 3 - U1 U14 -Net 485 "/FPGA, Port0, Port2, PROG IF/PROG_MISO1" "PROG_MISO1" - U1 AA20 - U8 2 -Net 486 "/FPGA, Port0, Port2, PROG IF/PROG_MISO0" "PROG_MISO0" - U1 AB20 - U8 5 -Net 487 "/Non volatile memories/NF_D7" "NF_D7" - U5 44 - U1 D11 -Net 488 "/FPGA, Port0, Port2, PROG IF/NF_D6" "NF_D6" - U5 43 - U1 A11 -Net 489 "/FPGA, Port0, Port2, PROG IF/NF_D5" "NF_D5" - U1 C11 - U5 42 -Net 490 "/FPGA, Port0, Port2, PROG IF/NF_D4" "NF_D4" - U5 41 - U1 A12 -Net 491 "/FPGA, Port0, Port2, PROG IF/NF_D3" "NF_D3" - U5 32 - U1 B12 -Net 492 "/Non volatile memories/NF_D2" "NF_D2" - U5 31 - U1 A13 -Net 493 "/Non volatile memories/NF_D1" "NF_D1" - U1 D14 - U5 30 -Net 494 "/Non volatile memories/NF_D0" "NF_D0" - U1 C12 - U5 29 -Net 495 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" - U4 18 - U1 C9 -Net 496 "/FPGA, Port0, Port2, PROG IF/ETH_TXD0" "ETH_TXD0" - U4 17 - U1 D10 -Net 497 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" - U4 3 - U1 C5 -Net 498 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" - U4 4 - U1 C6 -Net 499 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" - U4 5 - U1 A5 -Net 500 "/FPGA, Port0, Port2, PROG IF/ETH_RXD0" "ETH_RXD0" - U1 B6 - U4 6 -Net 501 "/Non volatile memories/SD_DAT3" "SD_DAT3" - J1 2 - U1 B16 -Net 502 "/FPGA, Port0, Port2, PROG IF/SD_DAT2" "SD_DAT2" - U1 A16 - J1 1 -Net 503 "/Non volatile memories/SD_DAT1" "SD_DAT1" - U1 B18 - J1 8 -Net 504 "/Non volatile memories/SD_DAT0" "SD_DAT0" - J1 7 - U1 A18 -Net 505 "/DDR Banks/M1_A5" "M1_A5" - U3 36 - RP6 3 -Net 506 "/FPGA Port 1, Port 3 (DDR, USB)/M1_A4" "M1_A4" - RP6 4 - U3 35 -Net 507 "/FPGA Port 1, Port 3 (DDR, USB)/M1_A3" "M1_A3" - U3 32 - RP1 5 -Net 508 "/FPGA Port 1, Port 3 (DDR, USB)/M1_A2" "M1_A2" - U3 31 - RP1 6 -Net 509 "/FPGA Port 1, Port 3 (DDR, USB)/M1_A1" "M1_A1" - U3 30 - RP1 7 -Net 510 "/FPGA Port 1, Port 3 (DDR, USB)/M1_A0" "M1_A0" - U3 29 - RP1 8 -Net 511 "/DDR Banks/M0_A12" "M0_A12" - U2 42 - RP18 8 -Net 512 "/FPGA Port 1, Port 3 (DDR, USB)/M0_A11" "M0_A11" - U2 41 - RP18 7 -Net 513 "/FPGA Port 1, Port 3 (DDR, USB)/M0_A10" "M0_A10" - RP15 5 - U2 28 -Net 514 "/FPGA Port 1, Port 3 (DDR, USB)/M0_A9" "M0_A9" - U2 40 - RP18 6 -Net 515 "/DDR Banks/M0_A8" "M0_A8" - U2 39 - RP18 5 -Net 516 "/FPGA Port 1, Port 3 (DDR, USB)/M0_A7" "M0_A7" - RP17 8 - U2 38 -Net 517 "/DDR Banks/M0_A6" "M0_A6" - U2 37 - RP17 7 -Net 518 "/DDR Banks/M0_A5" "M0_A5" - RP17 6 - U2 36 -Net 519 "/DDR Banks/M0_A4" "M0_A4" - U2 35 - RP17 5 -Net 520 "/FPGA Port 1, Port 3 (DDR, USB)/M1_DQ15" "M1_DQ15" - U3 65 - RP8 1 -Net 521 "/FPGA Port 1, Port 3 (DDR, USB)/M1_DQ14" "M1_DQ14" - RP8 2 - U3 63 -Net 522 "/DDR Banks/M1_DQ13" "M1_DQ13" - RP8 3 - U3 62 -Net 523 "/FPGA Port 1, Port 3 (DDR, USB)/M1_DQ12" "M1_DQ12" - RP8 4 - U3 60 -Net 524 "/FPGA Port 1, Port 3 (DDR, USB)/M1_DQ11" "M1_DQ11" - U3 59 - RP9 1 -Net 525 "/FPGA Port 1, Port 3 (DDR, USB)/M1_DQ10" "M1_DQ10" - U3 57 - RP9 2 -Net 526 "/DDR Banks/M1_DQ9" "M1_DQ9" - U3 56 - RP9 3 -Net 527 "/FPGA Port 1, Port 3 (DDR, USB)/M1_DQ8" "M1_DQ8" - U3 54 - RP9 4 -Net 528 "/FPGA Port 1, Port 3 (DDR, USB)/M1_DQ7" "M1_DQ7" - RP4 5 - U3 13 -Net 529 "/FPGA Port 1, Port 3 (DDR, USB)/M1_DQ6" "M1_DQ6" - U3 11 - RP4 6 -Net 530 "/DDR Banks/M1_DQ5" "M1_DQ5" - U3 10 - RP4 7 -Net 531 "/DDR Banks/M1_DQ4" "M1_DQ4" - RP4 8 - U3 8 -Net 532 "/FPGA Port 1, Port 3 (DDR, USB)/M1_DQ3" "M1_DQ3" - U3 7 - RP5 5 -Net 533 "/DDR Banks/M1_DQ2" "M1_DQ2" - U3 5 - RP5 6 -Net 534 "/FPGA Port 1, Port 3 (DDR, USB)/M1_DQ1" "M1_DQ1" - U3 4 - RP5 7 -Net 535 "/DDR Banks/M1_DQ0" "M1_DQ0" - RP5 8 - U3 2 -Net 536 "/DDR Banks/M1_A12" "M1_A12" - RP7 1 - U3 42 -Net 537 "/DDR Banks/M1_A11" "M1_A11" - RP7 2 - U3 41 -Net 538 "/FPGA Port 1, Port 3 (DDR, USB)/M1_A10" "M1_A10" - RP2 5 - U3 28 -Net 539 "/DDR Banks/M1_A9" "M1_A9" - RP7 3 - U3 40 -Net 540 "/FPGA Port 1, Port 3 (DDR, USB)/M1_A8" "M1_A8" - U3 39 - RP7 4 -Net 541 "/FPGA Port 1, Port 3 (DDR, USB)/M1_A7" "M1_A7" - U3 38 - RP6 1 -Net 542 "/FPGA Port 1, Port 3 (DDR, USB)/M1_A6" "M1_A6" - RP6 2 - U3 37 -Net 543 "/FPGA Port 1, Port 3 (DDR, USB)/M1_BA1" "M1_BA1" - RP2 6 - U3 27 -Net 544 "/FPGA Port 1, Port 3 (DDR, USB)/M1_BA0" "M1_BA0" - RP2 7 - U3 26 -Net 545 "/DDR Banks/M0_BA1" "M0_BA1" - RP15 6 - U2 27 -Net 546 "/FPGA Port 1, Port 3 (DDR, USB)/M0_BA0" "M0_BA0" - RP15 7 - U2 26 -Net 547 "/FPGA, Port0, Port2, PROG IF/ETH_TXD3" "ETH_TXD3" - U1 A8 - U4 20 -Net 548 "/FPGA, Port0, Port2, PROG IF/ETH_TXD2" "ETH_TXD2" - U1 C10 - U4 19 -Net 549 "/FPGA Port 1, Port 3 (DDR, USB)/M0_A3" "M0_A3" - RP14 5 - U2 32 -Net 550 "/DDR Banks/M0_A2" "M0_A2" - U2 31 - RP14 6 -Net 551 "/FPGA Port 1, Port 3 (DDR, USB)/M0_A1" "M0_A1" - U2 30 - RP14 7 -Net 552 "/DDR Banks/M0_A0" "M0_A0" - RP14 8 - U2 29 -Net 553 "/DDR Banks/M0_DQ15" "M0_DQ15" - RP10 5 - U2 65 -Net 554 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ14" "M0_DQ14" - U2 63 - RP10 6 -Net 555 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ13" "M0_DQ13" - RP10 7 - U2 62 -Net 556 "/DDR Banks/M0_DQ12" "M0_DQ12" - U2 60 - RP10 8 -Net 557 "/DDR Banks/M0_DQ11" "M0_DQ11" - RP11 5 - U2 59 -Net 558 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ10" "M0_DQ10" - U2 57 - RP11 6 -Net 559 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ9" "M0_DQ9" - RP11 7 - U2 56 -Net 560 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ8" "M0_DQ8" - U2 54 - RP11 8 -Net 561 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ7" "M0_DQ7" - U2 13 - RP12 5 -Net 562 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ6" "M0_DQ6" - RP12 6 - U2 11 -Net 563 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ5" "M0_DQ5" - RP12 7 - U2 10 -Net 564 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ4" "M0_DQ4" - RP12 8 - U2 8 -Net 565 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ3" "M0_DQ3" - RP13 5 - U2 7 -Net 566 "/DDR Banks/M0_DQ2" "M0_DQ2" - U2 5 - RP13 6 -Net 567 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ1" "M0_DQ1" - RP13 7 - U2 4 -Net 568 "/FPGA Port 1, Port 3 (DDR, USB)/M0_DQ0" "M0_DQ0" - U2 2 - RP13 8 -} -#End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 890a8f6..22d558d 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,6 +1,6 @@ -update=Mon 30 Aug 2010 10:28:26 AM COT +update=Mon 30 Aug 2010 07:47:17 PM COT version=1 -last_client=pcbnew +last_client=kicad [common] NetDir= [eeschema] @@ -88,8 +88,6 @@ version=1 NetIExt=net [cvpcb/libraries] EquName1=devcms -[general] -version=1 [pcbnew] version=1 PadDrlX=0 @@ -142,3 +140,5 @@ LibName29=../modules/DFN10 LibName30=../modules/MLF16 LibName31=../modules/USBD LibName32=../modules/MLP6 +[general] +version=1 diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 5c52d52..671506a 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 30 Aug 2010 10:27:20 AM COT +EESchema Schematic File Version 2 date Mon 30 Aug 2010 07:47:12 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -51,7 +51,7 @@ EELAYER END $Descr A3 16535 11700 Sheet 1 9 Title "" -Date "30 aug 2010" +Date "31 aug 2010" Rev "" Comp "" Comment1 ""