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Routing some FPGA free GPIOs

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This commit is contained in:
Juan64Bits
2010-10-12 22:07:35 -05:00
parent 4abc118a97
commit 0411d60348
17 changed files with 16033 additions and 14351 deletions
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82
kicad/xue-rnc/FPGA_0_2_PROG.sch
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@@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Sun 10 Oct 2010 06:23:22 PM COT
EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@@ -55,7 +55,7 @@ EELAYER END
$Descr A3 16535 11700
Sheet 5 12
Title ""
Date "10 oct 2010"
Date "13 oct 2010"
Rev ""
Comp ""
Comment1 ""
@@ -82,7 +82,7 @@ Entry Wire Line
Entry Wire Line
10450 8550 10550 8450
Wire Bus Line
10450 6900 11150 6900
11150 6900 10450 6900
Wire Bus Line
10450 6900 10450 10850
Wire Wire Line
@@ -1498,10 +1498,10 @@ FPGA_BANK0_IO_1
Text Label 9250 7050 0 60 ~ 0
FPGA_BANK0_IO_0
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Text Notes 6050 10450 0 30 ~ 0
VCC_AUX Decoupling Capacitors (7)
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