From 11ade0f1e8678c326cbd7b1993989755f0c1617e Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Mon, 9 Aug 2010 21:29:52 -0500 Subject: [PATCH] ddr footprint changed --- kicad/xue-rnc/DRAM.sch | 2 +- kicad/xue-rnc/FPGA.sch | 2 +- kicad/xue-rnc/NV_MEMORIES.sch | 2 +- kicad/xue-rnc/USB.sch | 2 +- kicad/xue-rnc/eth_phy.sch | 2 +- kicad/xue-rnc/xue-rnc-cache.lib | 2 +- kicad/xue-rnc/xue-rnc.brd | 3705 ++++++++++++------------------- kicad/xue-rnc/xue-rnc.cmp | 310 +-- kicad/xue-rnc/xue-rnc.net | 2513 ++++++++------------- kicad/xue-rnc/xue-rnc.pro | 118 +- kicad/xue-rnc/xue-rnc.sch | 2 +- 11 files changed, 2658 insertions(+), 4002 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index b34dfda..c5d0d43 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 08:20:32 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 383d84a..197a862 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 08:20:32 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 54e28dd..f143890 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 08:20:32 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index c864d4c..3cf166e 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 08:20:32 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 5767761..79a3239 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 08:20:32 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 156c15d..32605ee 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Mon 09 Aug 2010 08:20:32 PM COT +EESchema-LIBRARY Version 2.3 Date: Mon 09 Aug 2010 09:20:06 PM COT # # C # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index fb741f0..eefbf42 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,22 +1,26 @@ -PCBNEW-BOARD Version 1 date Mon 09 Aug 2010 03:33:55 PM COT +PCBNEW-BOARD Version 1 date Mon 09 Aug 2010 09:26:54 PM COT + +# Created by Pcbnew(2010-07-15 BZR 2414)-unstable $GENERAL LayerCount 4 Ly 1FFF8007 -Links 288 -NoConn 288 -Di -500 -500 65516 48783 +EnabledLayers 1FFF8007 +Links 270 +NoConn 270 +Di 37146 11079 66209 48914 Ndraw 0 Ntrack 0 Nzone 0 -Nmodule 41 -Nnets 110 +BoardThickness 630 +Nmodule 8 +Nnets 105 $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "9 aug 2010" +Date "10 aug 2010" Rev "" Comp "" Comment1 "" @@ -34,18 +38,20 @@ Layer[1] Inner2 signal Layer[2] Inner3 signal Layer[15] Front signal TrackWidth 80 -TrackWidthHistory 80 TrackClearence 100 ZoneClearence 200 +TrackMinWidth 80 DrawSegmWidth 150 EdgeSegmWidth 150 ViaSize 350 ViaDrill 250 -ViaAltDrill 250 -ViaSizeHistory 350 +ViaMinSize 350 +ViaMinDrill 200 MicroViaSize 200 MicroViaDrill 50 MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 TextPcbWidth 120 TextPcbSize 600 800 EdgeModWidth 150 @@ -53,6 +59,7 @@ TextModSize 600 600 TextModWidth 120 PadSize 600 600 PadDrill 320 +Pad2MaskClearance 100 AuxiliaryAxisOrg 0 0 $EndSETUP @@ -61,441 +68,536 @@ Na 0 "" St ~ $EndEQUIPOT $EQUIPOT -Na 1 "GND" +Na 1 "/DDR_Ban11" St ~ $EndEQUIPOT $EQUIPOT -Na 2 "/FPGA_Spartan6/ETH_INT" +Na 2 "/DDR_Ban12" St ~ $EndEQUIPOT $EQUIPOT -Na 3 "N-000122" +Na 3 "/DDR_Ban27" St ~ $EndEQUIPOT $EQUIPOT -Na 4 "/DDR_Banks/M0_A11" +Na 4 "/DDR_Ban28" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "N-000120" +Na 5 "/DDR_Ban31" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M1_A8" +Na 6 "/DDR_Ban34" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "N-000121" +Na 7 "/DDR_Ban36" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M1_A9" +Na 8 "/DDR_Ban38" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_A12" +Na 9 "/DDR_Ban43" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_CKE" +Na 10 "/DDR_Ban44" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "N-000119" +Na 11 "/DDR_Ban47" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M1_CKE" +Na 12 "/DDR_Ban48" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M1_A12" +Na 13 "/DDR_Ban57" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_A9" +Na 14 "/DDR_Ban62" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_A8" +Na 15 "/DDR_Ban63" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M1_A7" +Na 16 "/DDR_Ban65" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M1_A2" +Na 17 "/DDR_Ban67" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_WE#" +Na 18 "/DDR_Ban68" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_A4" +Na 19 "/DDR_Ban70" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M1_A11" +Na 20 "/DDR_Ban72" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M1_A4" +Na 21 "/DDR_Ban75" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M1_A0" +Na 22 "/DDR_Ban76" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_A1" +Na 23 "/DDR_Ban78" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M0_A10" +Na 24 "/DDR_Ban8" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_A10" +Na 25 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_A3" +Na 26 "/DDR_Banks/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M0_A1" +Na 27 "/DDR_Banks/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M0_A0" +Na 28 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M0_CLK#" +Na 29 "/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M0_CLK" +Na 30 "/Etherne1" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M0_A2" +Na 31 "/Etherne2" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M0_A7" +Na 32 "/Etherne3" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_WE#" +Na 33 "/Etherne4" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_CLK" +Na 34 "/Etherne5" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_RAS#" +Na 35 "/Etherne6" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/DDR_Banks/M1_CAS#" +Na 36 "/Etherne7" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/DDR_Banks/M0_DQ5" +Na 37 "/FPGA_Sp10" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M0_DQ4" +Na 38 "/FPGA_Sp13" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/DDR_Banks/M0_A6" +Na 39 "/FPGA_Sp14" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "N-000118" +Na 40 "/FPGA_Sp15" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/DDR_Banks/M1_CLK#" +Na 41 "/FPGA_Sp16" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/DDR_Banks/M1_DQ4" +Na 42 "/FPGA_Sp17" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/DDR_Banks/M1_DQ5" +Na 43 "/FPGA_Sp18" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/DDR_Banks/M0_DQ7" +Na 44 "/FPGA_Sp19" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/DDR_Banks/M0_DQ6" +Na 45 "/FPGA_Sp20" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/DDR_Banks/M0_A5" +Na 46 "/FPGA_Sp21" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/DDR_Banks/M0_CAS#" +Na 47 "/FPGA_Sp22" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/DDR_Banks/M0_RAS#" +Na 48 "/FPGA_Sp23" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/DDR_Banks/M0_A3" +Na 49 "/FPGA_Sp24" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/DDR_Banks/M1_A6" +Na 50 "/FPGA_Sp25" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/DDR_Banks/M1_A5" +Na 51 "/FPGA_Sp26" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/DDR_Banks/M1_DQ6" +Na 52 "/FPGA_Sp29" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/DDR_Banks/M1_DQ7" +Na 53 "/FPGA_Sp30" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/DDR_Banks/M0_LDQS" +Na 54 "/FPGA_Sp32" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/DDR_Banks/M0_LDM" +Na 55 "/FPGA_Sp33" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/DDR_Banks/M1_LDM" +Na 56 "/FPGA_Sp35" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/DDR_Banks/M1_LDQS" +Na 57 "/FPGA_Sp37" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/DDR_Banks/M0_DQ3" +Na 58 "/FPGA_Sp39" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/DDR_Banks/M0_DQ2" +Na 59 "/FPGA_Sp40" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/DDR_Banks/M0_UDM" +Na 60 "/FPGA_Sp41" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/DDR_Banks/M1_UDM" +Na 61 "/FPGA_Sp42" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/DDR_Banks/M1_DQ2" +Na 62 "/FPGA_Sp45" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/DDR_Banks/M1_DQ3" +Na 63 "/FPGA_Sp46" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/DDR_Banks/M0_DQ1" +Na 64 "/FPGA_Sp49" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/DDR_Banks/M0_DQ0" +Na 65 "/FPGA_Sp50" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/DDR_Banks/M1_DQ0" +Na 66 "/FPGA_Sp51" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/DDR_Banks/M1_DQ1" +Na 67 "/FPGA_Sp52" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/DDR_Banks/M0_DQ9" +Na 68 "/FPGA_Sp53" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/DDR_Banks/M0_DQ8" +Na 69 "/FPGA_Sp54" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/DDR_Banks/M1_DQ8" +Na 70 "/FPGA_Sp55" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/DDR_Banks/M1_DQ9" +Na 71 "/FPGA_Sp56" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/DDR_Banks/M0_DQ11" +Na 72 "/FPGA_Sp58" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/DDR_Banks/M0_DQ10" +Na 73 "/FPGA_Sp59" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/DDR_Banks/M1_DQ10" +Na 74 "/FPGA_Sp60" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/DDR_Banks/M1_DQ11" +Na 75 "/FPGA_Sp61" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/DDR_Banks/M0_UDQS" +Na 76 "/FPGA_Sp64" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "N-000123" +Na 77 "/FPGA_Sp66" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/DDR_Banks/M1_UDQS" +Na 78 "/FPGA_Sp69" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/DDR_Banks/M0_DQ13" +Na 79 "/FPGA_Sp71" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/DDR_Banks/M0_DQ12" +Na 80 "/FPGA_Sp73" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/DDR_Banks/M1_DQ12" +Na 81 "/FPGA_Sp74" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/DDR_Banks/M1_DQ13" +Na 82 "/FPGA_Sp77" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/DDR_Banks/M0_DQ15" +Na 83 "/FPGA_Sp9" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/DDR_Banks/M0_DQ14" +Na 84 "/Non_vol79" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/DDR_Banks/M1_DQ14" +Na 85 "3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/DDR_Banks/M1_DQ15" +Na 86 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "N-000068" +Na 87 "N-000048" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/ETH_MDIO" +Na 88 "N-000056" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/Ethernet_Phy/ETH_PLL1.8V" +Na 89 "N-000152" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "N-000391" +Na 90 "N-000153" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "N-000386" +Na 91 "N-000154" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/Ethernet_Phy/ETH_A3.3V" +Na 92 "N-000158" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "N-000384" +Na 93 "N-000159" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/Ethernet_Phy/ETH_LED0" +Na 94 "N-000160" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/Ethernet_Phy/ETH_LED1" +Na 95 "N-000396" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/Ethernet_Phy/ETH_A1.8V" +Na 96 "N-000398" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "N-000385" +Na 97 "N-000399" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "N-000392" +Na 98 "N-000400" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/Ethernet_Phy/ETH_1.8V" +Na 99 "N-000402" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/Non_volatile_memories/FRB_N" +Na 100 "N-000404" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "N-000046" +Na 101 "N-000405" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "N-000048" +Na 102 "N-000406" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "N-000409" +Na 103 "N-000420" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "N-000389" -St ~ -$EndEQUIPOT -$EQUIPOT -Na 105 "N-000393" -St ~ -$EndEQUIPOT -$EQUIPOT -Na 106 "N-000411" -St ~ -$EndEQUIPOT -$EQUIPOT -Na 107 "N-000388" -St ~ -$EndEQUIPOT -$EQUIPOT -Na 108 "N-000410" -St ~ -$EndEQUIPOT -$EQUIPOT -Na 109 "N-000412" +Na 104 "N-000426" St ~ $EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "/DDR_Ban11" +AddNet "/DDR_Ban12" +AddNet "/DDR_Ban27" +AddNet "/DDR_Ban28" +AddNet "/DDR_Ban31" +AddNet "/DDR_Ban34" +AddNet "/DDR_Ban36" +AddNet "/DDR_Ban38" +AddNet "/DDR_Ban43" +AddNet "/DDR_Ban44" +AddNet "/DDR_Ban47" +AddNet "/DDR_Ban48" +AddNet "/DDR_Ban57" +AddNet "/DDR_Ban62" +AddNet "/DDR_Ban63" +AddNet "/DDR_Ban65" +AddNet "/DDR_Ban67" +AddNet "/DDR_Ban68" +AddNet "/DDR_Ban70" +AddNet "/DDR_Ban72" +AddNet "/DDR_Ban75" +AddNet "/DDR_Ban76" +AddNet "/DDR_Ban78" +AddNet "/DDR_Ban8" +AddNet "/DDR_Banks/M0_A8" +AddNet "/DDR_Banks/M0_A9" +AddNet "/DDR_Banks/M1_A3" +AddNet "/DDR_Banks/M1_A5" +AddNet "/ETH_MDIO" +AddNet "/Etherne1" +AddNet "/Etherne2" +AddNet "/Etherne3" +AddNet "/Etherne4" +AddNet "/Etherne5" +AddNet "/Etherne6" +AddNet "/Etherne7" +AddNet "/FPGA_Sp10" +AddNet "/FPGA_Sp13" +AddNet "/FPGA_Sp14" +AddNet "/FPGA_Sp15" +AddNet "/FPGA_Sp16" +AddNet "/FPGA_Sp17" +AddNet "/FPGA_Sp18" +AddNet "/FPGA_Sp19" +AddNet "/FPGA_Sp20" +AddNet "/FPGA_Sp21" +AddNet "/FPGA_Sp22" +AddNet "/FPGA_Sp23" +AddNet "/FPGA_Sp24" +AddNet "/FPGA_Sp25" +AddNet "/FPGA_Sp26" +AddNet "/FPGA_Sp29" +AddNet "/FPGA_Sp30" +AddNet "/FPGA_Sp32" +AddNet "/FPGA_Sp33" +AddNet "/FPGA_Sp35" +AddNet "/FPGA_Sp37" +AddNet "/FPGA_Sp39" +AddNet "/FPGA_Sp40" +AddNet "/FPGA_Sp41" +AddNet "/FPGA_Sp42" +AddNet "/FPGA_Sp45" +AddNet "/FPGA_Sp46" +AddNet "/FPGA_Sp49" +AddNet "/FPGA_Sp50" +AddNet "/FPGA_Sp51" +AddNet "/FPGA_Sp52" +AddNet "/FPGA_Sp53" +AddNet "/FPGA_Sp54" +AddNet "/FPGA_Sp55" +AddNet "/FPGA_Sp56" +AddNet "/FPGA_Sp58" +AddNet "/FPGA_Sp59" +AddNet "/FPGA_Sp60" +AddNet "/FPGA_Sp61" +AddNet "/FPGA_Sp64" +AddNet "/FPGA_Sp66" +AddNet "/FPGA_Sp69" +AddNet "/FPGA_Sp71" +AddNet "/FPGA_Sp73" +AddNet "/FPGA_Sp74" +AddNet "/FPGA_Sp77" +AddNet "/FPGA_Sp9" +AddNet "/Non_vol79" +AddNet "3.3V" +AddNet "GND" +AddNet "N-000048" +AddNet "N-000056" +AddNet "N-000152" +AddNet "N-000153" +AddNet "N-000154" +AddNet "N-000158" +AddNet "N-000159" +AddNet "N-000160" +AddNet "N-000396" +AddNet "N-000398" +AddNet "N-000399" +AddNet "N-000400" +AddNet "N-000402" +AddNet "N-000404" +AddNet "N-000405" +AddNet "N-000406" +AddNet "N-000420" +AddNet "N-000426" +$EndNCLASS $MODULE FGG484bga-p10 Po 56450 33930 0 15 4C4325AE 4C431E53 ~~ Li FGG484bga-p10 @@ -517,7 +619,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -4133 -4133 $EndPAD $PAD @@ -545,7 +647,7 @@ $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/FPGA_Spartan6/ETH_INT" +Ne 36 "/Etherne7" Po -2558 -4133 $EndPAD $PAD @@ -664,7 +766,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 4133 -4133 $EndPAD $PAD @@ -692,14 +794,14 @@ $PAD Sh "B4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "N-000122" +Ne 90 "N-000153" Po -2952 -3739 $EndPAD $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -2558 -3739 $EndPAD $PAD @@ -713,7 +815,7 @@ $PAD Sh "B7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "N-000122" +Ne 90 "N-000153" Po -1771 -3739 $EndPAD $PAD @@ -727,7 +829,7 @@ $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -983 -3739 $EndPAD $PAD @@ -741,7 +843,7 @@ $PAD Sh "B11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "N-000122" +Ne 90 "N-000153" Po -196 -3739 $EndPAD $PAD @@ -755,7 +857,7 @@ $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 590 -3739 $EndPAD $PAD @@ -769,7 +871,7 @@ $PAD Sh "B15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "N-000122" +Ne 90 "N-000153" Po 1377 -3739 $EndPAD $PAD @@ -783,7 +885,7 @@ $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 2165 -3739 $EndPAD $PAD @@ -797,7 +899,7 @@ $PAD Sh "B19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "N-000122" +Ne 90 "N-000153" Po 2952 -3739 $EndPAD $PAD @@ -825,14 +927,14 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/DDR_Banks/M0_A11" +Ne 24 "/DDR_Ban8" Po -4133 -3346 $EndPAD $PAD Sh "C2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -3739 -3346 $EndPAD $PAD @@ -958,35 +1060,35 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M1_A8" +Ne 83 "/FPGA_Sp9" Po 3346 -3346 $EndPAD $PAD Sh "C21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "N-000121" +Ne 91 "N-000154" Po 3739 -3346 $EndPAD $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M1_A9" +Ne 37 "/FPGA_Sp10" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A12" +Ne 1 "/DDR_Ban11" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_CKE" +Ne 2 "/DDR_Ban12" Po -3739 -2952 $EndPAD $PAD @@ -1000,7 +1102,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1084,7 +1186,7 @@ $PAD Sh "D16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po 1771 -2952 $EndPAD $PAD @@ -1098,7 +1200,7 @@ $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 2558 -2952 $EndPAD $PAD @@ -1119,35 +1221,35 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M1_CKE" +Ne 38 "/FPGA_Sp13" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M1_A12" +Ne 39 "/FPGA_Sp14" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_A9" +Ne 26 "/DDR_Banks/M0_A9" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_A8" +Ne 25 "/DDR_Banks/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1175,7 +1277,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -1771 -2558 $EndPAD $PAD @@ -1189,7 +1291,7 @@ $PAD Sh "E9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "N-000122" +Ne 90 "N-000153" Po -983 -2558 $EndPAD $PAD @@ -1203,7 +1305,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -196 -2558 $EndPAD $PAD @@ -1217,7 +1319,7 @@ $PAD Sh "E13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "N-000122" +Ne 90 "N-000153" Po 590 -2558 $EndPAD $PAD @@ -1231,7 +1333,7 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 1377 -2558 $EndPAD $PAD @@ -1245,7 +1347,7 @@ $PAD Sh "E17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "N-000122" +Ne 90 "N-000153" Po 2165 -2558 $EndPAD $PAD @@ -1259,28 +1361,28 @@ $PAD Sh "E19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "N-000121" +Ne 91 "N-000154" Po 2952 -2558 $EndPAD $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M1_A7" +Ne 40 "/FPGA_Sp15" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M1_A2" +Ne 41 "/FPGA_Sp16" Po 4133 -2558 $EndPAD $PAD @@ -1294,21 +1396,21 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_WE#" +Ne 42 "/FPGA_Sp17" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_A4" +Ne 43 "/FPGA_Sp18" Po -3346 -2165 $EndPAD $PAD Sh "F4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -2952 -2165 $EndPAD $PAD @@ -1322,7 +1424,7 @@ $PAD Sh "F6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -2165 -2165 $EndPAD $PAD @@ -1357,7 +1459,7 @@ $PAD Sh "F11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po -196 -2165 $EndPAD $PAD @@ -1413,28 +1515,28 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_A11" +Ne 44 "/FPGA_Sp19" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_A4" +Ne 45 "/FPGA_Sp20" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_A0" +Ne 46 "/FPGA_Sp21" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A1" +Ne 47 "/FPGA_Sp22" Po 4133 -2165 $EndPAD $PAD @@ -1448,7 +1550,7 @@ $PAD Sh "G2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -3739 -1771 $EndPAD $PAD @@ -1462,14 +1564,14 @@ $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M0_A10" +Ne 48 "/FPGA_Sp23" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -2558 -1771 $EndPAD $PAD @@ -1504,7 +1606,7 @@ $PAD Sh "G10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "N-000122" +Ne 90 "N-000153" Po -590 -1771 $EndPAD $PAD @@ -1518,7 +1620,7 @@ $PAD Sh "G12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po 196 -1771 $EndPAD $PAD @@ -1532,7 +1634,7 @@ $PAD Sh "G14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "N-000122" +Ne 90 "N-000153" Po 983 -1771 $EndPAD $PAD @@ -1560,28 +1662,28 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A10" +Ne 49 "/FPGA_Sp24" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_A3" +Ne 27 "/DDR_Banks/M1_A3" Po 3346 -1771 $EndPAD $PAD Sh "G21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "N-000121" +Ne 91 "N-000154" Po 3739 -1771 $EndPAD $PAD @@ -1595,49 +1697,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M0_A1" +Ne 50 "/FPGA_Sp25" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M0_A0" +Ne 51 "/FPGA_Sp26" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M0_CLK#" +Ne 3 "/DDR_Ban27" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M0_CLK" +Ne 4 "/DDR_Ban28" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M0_A2" +Ne 52 "/FPGA_Sp29" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M0_A7" +Ne 53 "/FPGA_Sp30" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -1771 -1377 $EndPAD $PAD @@ -1651,7 +1753,7 @@ $PAD Sh "H9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po -983 -1377 $EndPAD $PAD @@ -1693,7 +1795,7 @@ $PAD Sh "H15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po 1377 -1377 $EndPAD $PAD @@ -1721,63 +1823,63 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_WE#" +Ne 5 "/DDR_Ban31" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_CLK" +Ne 54 "/FPGA_Sp32" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_RAS#" +Ne 55 "/FPGA_Sp33" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_CAS#" +Ne 6 "/DDR_Ban34" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/DDR_Banks/M0_DQ5" +Ne 56 "/FPGA_Sp35" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M0_DQ4" +Ne 7 "/DDR_Ban36" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M0_A6" +Ne 57 "/FPGA_Sp37" Po -2952 -983 $EndPAD $PAD Sh "J5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -2558 -983 $EndPAD $PAD @@ -1798,56 +1900,56 @@ $PAD Sh "J8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po -1377 -983 $EndPAD $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -983 -983 $EndPAD $PAD Sh "J10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po -590 -983 $EndPAD $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -196 -983 $EndPAD $PAD Sh "J12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po 196 -983 $EndPAD $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 590 -983 $EndPAD $PAD Sh "J14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po 983 -983 $EndPAD $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 1377 -983 $EndPAD $PAD @@ -1868,77 +1970,77 @@ $PAD Sh "J18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "N-000121" +Ne 91 "N-000154" Po 2558 -983 $EndPAD $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/DDR_Banks/M1_CLK#" +Ne 8 "/DDR_Ban38" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/DDR_Banks/M1_DQ4" +Ne 0 "" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/DDR_Banks/M1_DQ5" +Ne 58 "/FPGA_Sp39" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/DDR_Banks/M0_DQ7" +Ne 59 "/FPGA_Sp40" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/DDR_Banks/M0_DQ6" +Ne 60 "/FPGA_Sp41" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/DDR_Banks/M0_A5" +Ne 61 "/FPGA_Sp42" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/DDR_Banks/M0_CAS#" +Ne 9 "/DDR_Ban43" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/DDR_Banks/M0_RAS#" +Ne 10 "/DDR_Ban44" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/DDR_Banks/M0_A3" +Ne 62 "/FPGA_Sp45" Po -2165 -590 $EndPAD $PAD @@ -1959,49 +2061,49 @@ $PAD Sh "K9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po -983 -590 $EndPAD $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -590 -590 $EndPAD $PAD Sh "K11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po -196 -590 $EndPAD $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 196 -590 $EndPAD $PAD Sh "K13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po 590 -590 $EndPAD $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 983 -590 $EndPAD $PAD Sh "K15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po 1377 -590 $EndPAD $PAD @@ -2029,28 +2131,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/DDR_Banks/M1_A6" +Ne 63 "/FPGA_Sp46" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/DDR_Banks/M1_A5" +Ne 28 "/DDR_Banks/M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/DDR_Banks/M1_DQ6" +Ne 11 "/DDR_Ban47" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/DDR_Banks/M1_DQ7" +Ne 12 "/DDR_Ban48" Po 4133 -590 $EndPAD $PAD @@ -2064,28 +2166,28 @@ $PAD Sh "L2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -3739 -196 $EndPAD $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/DDR_Banks/M0_LDQS" +Ne 64 "/FPGA_Sp49" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/DDR_Banks/M0_LDM" +Ne 65 "/FPGA_Sp50" Po -2952 -196 $EndPAD $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -2558 -196 $EndPAD $PAD @@ -2099,56 +2201,56 @@ $PAD Sh "L7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -1771 -196 $EndPAD $PAD Sh "L8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po -1377 -196 $EndPAD $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -983 -196 $EndPAD $PAD Sh "L10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po -590 -196 $EndPAD $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -196 -196 $EndPAD $PAD Sh "L12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po 196 -196 $EndPAD $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 590 -196 $EndPAD $PAD Sh "L14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po 983 -196 $EndPAD $PAD @@ -2162,7 +2264,7 @@ $PAD Sh "L16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "N-000121" +Ne 91 "N-000154" Po 1771 -196 $EndPAD $PAD @@ -2176,28 +2278,28 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/DDR_Banks/M1_LDM" +Ne 66 "/FPGA_Sp51" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/DDR_Banks/M1_LDQS" +Ne 67 "/FPGA_Sp52" Po 3346 -196 $EndPAD $PAD Sh "L21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "N-000121" +Ne 91 "N-000154" Po 3739 -196 $EndPAD $PAD @@ -2211,21 +2313,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/DDR_Banks/M0_DQ3" +Ne 68 "/FPGA_Sp53" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/DDR_Banks/M0_DQ2" +Ne 69 "/FPGA_Sp54" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/DDR_Banks/M0_UDM" +Ne 70 "/FPGA_Sp55" Po -3346 196 $EndPAD $PAD @@ -2267,49 +2369,49 @@ $PAD Sh "M9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po -983 196 $EndPAD $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -590 196 $EndPAD $PAD Sh "M11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po -196 196 $EndPAD $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 196 196 $EndPAD $PAD Sh "M13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po 590 196 $EndPAD $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 983 196 $EndPAD $PAD Sh "M15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po 1377 196 $EndPAD $PAD @@ -2344,42 +2446,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/DDR_Banks/M1_UDM" +Ne 71 "/FPGA_Sp56" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/DDR_Banks/M1_DQ2" +Ne 0 "" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/DDR_Banks/M1_DQ3" +Ne 0 "" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/DDR_Banks/M0_DQ1" +Ne 13 "/DDR_Ban57" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/DDR_Banks/M0_DQ0" +Ne 72 "/FPGA_Sp58" Po -3346 590 $EndPAD $PAD @@ -2393,7 +2495,7 @@ $PAD Sh "N5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -2558 590 $EndPAD $PAD @@ -2414,49 +2516,49 @@ $PAD Sh "N8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po -1377 590 $EndPAD $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -983 590 $EndPAD $PAD Sh "N10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po -590 590 $EndPAD $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -196 590 $EndPAD $PAD Sh "N12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po 196 590 $EndPAD $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 590 590 $EndPAD $PAD Sh "N14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po 983 590 $EndPAD $PAD @@ -2477,14 +2579,14 @@ $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 2165 590 $EndPAD $PAD Sh "N18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "N-000121" +Ne 91 "N-000154" Po 2558 590 $EndPAD $PAD @@ -2498,35 +2600,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/DDR_Banks/M1_DQ0" +Ne 73 "/FPGA_Sp59" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/DDR_Banks/M1_DQ1" +Ne 74 "/FPGA_Sp60" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/DDR_Banks/M0_DQ9" +Ne 75 "/FPGA_Sp61" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/DDR_Banks/M0_DQ8" +Ne 14 "/DDR_Ban62" Po -3739 983 $EndPAD $PAD @@ -2575,42 +2677,42 @@ $PAD Sh "P9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po -983 983 $EndPAD $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -590 983 $EndPAD $PAD Sh "P11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po -196 983 $EndPAD $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 196 983 $EndPAD $PAD Sh "P13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po 590 983 $EndPAD $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 983 983 $EndPAD $PAD @@ -2659,35 +2761,35 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/DDR_Banks/M1_DQ8" +Ne 15 "/DDR_Ban63" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/DDR_Banks/M1_DQ9" +Ne 76 "/FPGA_Sp64" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/DDR_Banks/M0_DQ11" +Ne 16 "/DDR_Ban65" Po -4133 1377 $EndPAD $PAD Sh "R2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -3739 1377 $EndPAD $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/DDR_Banks/M0_DQ10" +Ne 77 "/FPGA_Sp66" Po -3346 1377 $EndPAD $PAD @@ -2701,14 +2803,14 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -2558 1377 $EndPAD $PAD Sh "R6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po -2165 1377 $EndPAD $PAD @@ -2736,7 +2838,7 @@ $PAD Sh "R10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po -590 1377 $EndPAD $PAD @@ -2750,7 +2852,7 @@ $PAD Sh "R12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po 196 1377 $EndPAD $PAD @@ -2764,7 +2866,7 @@ $PAD Sh "R14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "N-000118" +Ne 93 "N-000159" Po 983 1377 $EndPAD $PAD @@ -2792,7 +2894,7 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 2558 1377 $EndPAD $PAD @@ -2806,21 +2908,21 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/DDR_Banks/M1_DQ10" +Ne 17 "/DDR_Ban67" Po 3346 1377 $EndPAD $PAD Sh "R21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "N-000121" +Ne 91 "N-000154" Po 3739 1377 $EndPAD $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/DDR_Banks/M1_DQ11" +Ne 18 "/DDR_Ban68" Po 4133 1377 $EndPAD $PAD @@ -2834,7 +2936,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/DDR_Banks/M0_UDQS" +Ne 78 "/FPGA_Sp69" Po -3739 1771 $EndPAD $PAD @@ -2883,7 +2985,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po -983 1771 $EndPAD $PAD @@ -2911,7 +3013,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po 590 1771 $EndPAD $PAD @@ -2967,7 +3069,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/DDR_Banks/M1_UDQS" +Ne 19 "/DDR_Ban70" Po 3739 1771 $EndPAD $PAD @@ -2981,21 +3083,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/DDR_Banks/M0_DQ13" +Ne 79 "/FPGA_Sp71" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/DDR_Banks/M0_DQ12" +Ne 20 "/DDR_Ban72" Po -3346 2165 $EndPAD $PAD @@ -3009,7 +3111,7 @@ $PAD Sh "U5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -2558 2165 $EndPAD $PAD @@ -3023,7 +3125,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -1771 2165 $EndPAD $PAD @@ -3051,7 +3153,7 @@ $PAD Sh "U11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po -196 2165 $EndPAD $PAD @@ -3100,7 +3202,7 @@ $PAD Sh "U18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "N-000121" +Ne 91 "N-000154" Po 2558 2165 $EndPAD $PAD @@ -3114,35 +3216,35 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/DDR_Banks/M1_DQ12" +Ne 80 "/FPGA_Sp73" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/DDR_Banks/M1_DQ13" +Ne 81 "/FPGA_Sp74" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/DDR_Banks/M0_DQ15" +Ne 21 "/DDR_Ban75" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/DDR_Banks/M0_DQ14" +Ne 22 "/DDR_Ban76" Po -3739 2558 $EndPAD $PAD @@ -3156,7 +3258,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -2952 2558 $EndPAD $PAD @@ -3170,7 +3272,7 @@ $PAD Sh "V6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000119" +Ne 94 "N-000160" Po -2165 2558 $EndPAD $PAD @@ -3184,7 +3286,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po -1377 2558 $EndPAD $PAD @@ -3198,7 +3300,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -590 2558 $EndPAD $PAD @@ -3212,7 +3314,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po 196 2558 $EndPAD $PAD @@ -3226,7 +3328,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 983 2558 $EndPAD $PAD @@ -3240,7 +3342,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po 1771 2558 $EndPAD $PAD @@ -3275,14 +3377,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/DDR_Banks/M1_DQ14" +Ne 82 "/FPGA_Sp77" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/DDR_Banks/M1_DQ15" +Ne 23 "/DDR_Ban78" Po 4133 2558 $EndPAD $PAD @@ -3296,7 +3398,7 @@ $PAD Sh "W2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "N-000120" +Ne 92 "N-000158" Po -3739 2952 $EndPAD $PAD @@ -3317,7 +3419,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po -2558 2952 $EndPAD $PAD @@ -3331,7 +3433,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -1771 2952 $EndPAD $PAD @@ -3394,7 +3496,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 1771 2952 $EndPAD $PAD @@ -3415,7 +3517,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 2952 2952 $EndPAD $PAD @@ -3429,7 +3531,7 @@ $PAD Sh "W21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "N-000121" +Ne 91 "N-000154" Po 3739 2952 $EndPAD $PAD @@ -3611,7 +3713,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po -3346 3739 $EndPAD $PAD @@ -3625,7 +3727,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -2558 3739 $EndPAD $PAD @@ -3639,7 +3741,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po -1771 3739 $EndPAD $PAD @@ -3653,7 +3755,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -983 3739 $EndPAD $PAD @@ -3667,7 +3769,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po -196 3739 $EndPAD $PAD @@ -3681,7 +3783,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 590 3739 $EndPAD $PAD @@ -3695,7 +3797,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po 1377 3739 $EndPAD $PAD @@ -3709,7 +3811,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 2165 3739 $EndPAD $PAD @@ -3723,7 +3825,7 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "N-000123" +Ne 89 "N-000152" Po 2952 3739 $EndPAD $PAD @@ -3751,7 +3853,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -4133 4133 $EndPAD $PAD @@ -3898,7 +4000,7 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 @@ -3920,7 +4022,7 @@ $PAD Sh "12" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -1613 1082 $EndPAD $PAD @@ -3948,14 +4050,14 @@ $PAD Sh "8" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -1613 295 $EndPAD $PAD Sh "7" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000068" +Ne 85 "3.3V" Po -1613 98 $EndPAD $PAD @@ -3997,7 +4099,7 @@ $PAD Sh "1" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/ETH_MDIO" +Ne 29 "/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD @@ -4011,7 +4113,7 @@ $PAD Sh "47" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 33 "/Etherne4" Po -885 -1613 $EndPAD $PAD @@ -4032,7 +4134,7 @@ $PAD Sh "44" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -295 -1613 $EndPAD $PAD @@ -4053,56 +4155,56 @@ $PAD Sh "41" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000391" +Ne 96 "N-000398" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000386" +Ne 102 "N-000406" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/Ethernet_Phy/ETH_A3.3V" +Ne 32 "/Etherne3" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000384" +Ne 99 "N-000402" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/FPGA_Spartan6/ETH_INT" +Ne 36 "/Etherne7" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/Ethernet_Phy/ETH_LED0" +Ne 34 "/Etherne5" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/Ethernet_Phy/ETH_LED1" +Ne 35 "/Etherne6" Po 1613 688 $EndPAD $PAD @@ -4130,21 +4232,21 @@ $PAD Sh "31" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/Ethernet_Phy/ETH_A1.8V" +Ne 31 "/Etherne2" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "N-000385" +Ne 101 "N-000405" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "N-000392" +Ne 97 "N-000399" Po 1613 -491 $EndPAD $PAD @@ -4158,21 +4260,21 @@ $PAD Sh "35" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 1613 -1082 $EndPAD $PAD Sh "13" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/Ethernet_Phy/ETH_1.8V" +Ne 30 "/Etherne1" Po -1082 1613 $EndPAD $PAD @@ -4242,14 +4344,14 @@ $PAD Sh "23" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 885 1613 $EndPAD $PAD Sh "24" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000068" +Ne 85 "3.3V" Po 1082 1613 $EndPAD $EndMODULE LQFP48 @@ -4513,14 +4615,14 @@ $PAD Sh "6" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/Non_volatile_memories/FRB_N" +Ne 84 "/Non_vol79" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/Non_volatile_memories/FRB_N" +Ne 84 "/Non_vol79" Po -1090 3850 $EndPAD $PAD @@ -4555,14 +4657,14 @@ $PAD Sh "12" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000068" +Ne 85 "3.3V" Po -100 3850 $EndPAD $PAD Sh "13" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 100 3850 $EndPAD $PAD @@ -4604,7 +4706,7 @@ $PAD Sh "19" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000068" +Ne 85 "3.3V" Po 1280 3850 $EndPAD $PAD @@ -4723,14 +4825,14 @@ $PAD Sh "36" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 100 -3850 $EndPAD $PAD Sh "37" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000068" +Ne 85 "3.3V" Po -100 -3850 $EndPAD $PAD @@ -4811,1772 +4913,6 @@ Ne 0 "" Po -2270 -3850 $EndPAD $EndMODULE NAND-48TSOP -$MODULE 60fbga_ddr -Po 47940 33390 1800 15 4C58C755 4C58C847 ~~ -Li 60fbga_ddr -Sc 4C58C847 -AR /4C421DD3/4C58C847 -Op 0 0 0 -At SMD -T0 0 -150 200 200 1800 40 N V 25 N"U2" -T1 0 150 200 200 1800 40 N I 25 N"MT46V32M16FN" -DC -1771 -2283 -1771 -2362 39 21 -DS -1968 2460 -1968 -2460 39 21 -DS -1968 -2460 1968 -2460 39 21 -DS 1968 -2460 1968 2460 39 21 -DS 1968 2460 -1968 2460 39 21 -$PAD -Sh "A1" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -1259 -2165 -$EndPAD -$PAD -Sh "A9" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 101 "N-000046" -Po 1259 -2165 -$EndPAD -$PAD -Sh "B1" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 84 "/DDR_Banks/M0_DQ14" -Po -1259 -1771 -$EndPAD -$PAD -Sh "B9" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 64 "/DDR_Banks/M0_DQ1" -Po 1259 -1771 -$EndPAD -$PAD -Sh "C1" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 80 "/DDR_Banks/M0_DQ12" -Po -1259 -1377 -$EndPAD -$PAD -Sh "C9" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 58 "/DDR_Banks/M0_DQ3" -Po 1259 -1377 -$EndPAD -$PAD -Sh "D1" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 73 "/DDR_Banks/M0_DQ10" -Po -1259 -983 -$EndPAD -$PAD -Sh "D9" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 37 "/DDR_Banks/M0_DQ5" -Po 1259 -983 -$EndPAD -$PAD -Sh "E1" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 69 "/DDR_Banks/M0_DQ8" -Po -1259 -590 -$EndPAD -$PAD -Sh "E9" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 44 "/DDR_Banks/M0_DQ7" -Po 1259 -590 -$EndPAD -$PAD -Sh "F1" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -1259 -196 -$EndPAD -$PAD -Sh "F9" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 1259 -196 -$EndPAD -$PAD -Sh "A2" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 83 "/DDR_Banks/M0_DQ15" -Po -944 -2165 -$EndPAD -$PAD -Sh "A3" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -629 -2165 -$EndPAD -$PAD -Sh "A7" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 101 "N-000046" -Po 629 -2165 -$EndPAD -$PAD -Sh "A8" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 65 "/DDR_Banks/M0_DQ0" -Po 944 -2165 -$EndPAD -$PAD -Sh "B2" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 101 "N-000046" -Po -944 -1771 -$EndPAD -$PAD -Sh "B3" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 79 "/DDR_Banks/M0_DQ13" -Po -629 -1771 -$EndPAD -$PAD -Sh "B7" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 59 "/DDR_Banks/M0_DQ2" -Po 629 -1771 -$EndPAD -$PAD -Sh "B8" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po 944 -1771 -$EndPAD -$PAD -Sh "C2" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -944 -1377 -$EndPAD -$PAD -Sh "C3" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 72 "/DDR_Banks/M0_DQ11" -Po -629 -1377 -$EndPAD -$PAD -Sh "C7" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 38 "/DDR_Banks/M0_DQ4" -Po 629 -1377 -$EndPAD -$PAD -Sh "C8" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 101 "N-000046" -Po 944 -1377 -$EndPAD -$PAD -Sh "D2" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 101 "N-000046" -Po -944 -983 -$EndPAD -$PAD -Sh "D3" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 68 "/DDR_Banks/M0_DQ9" -Po -629 -983 -$EndPAD -$PAD -Sh "D7" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 45 "/DDR_Banks/M0_DQ6" -Po 629 -983 -$EndPAD -$PAD -Sh "D8" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po 944 -983 -$EndPAD -$PAD -Sh "E2" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -944 -590 -$EndPAD -$PAD -Sh "E3" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 76 "/DDR_Banks/M0_UDQS" -Po -629 -590 -$EndPAD -$PAD -Sh "E7" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 54 "/DDR_Banks/M0_LDQS" -Po 629 -590 -$EndPAD -$PAD -Sh "E8" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 101 "N-000046" -Po 944 -590 -$EndPAD -$PAD -Sh "F2" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -944 -196 -$EndPAD -$PAD -Sh "F3" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 60 "/DDR_Banks/M0_UDM" -Po -629 -196 -$EndPAD -$PAD -Sh "F7" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 55 "/DDR_Banks/M0_LDM" -Po 629 -196 -$EndPAD -$PAD -Sh "F8" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 101 "N-000046" -Po 944 -196 -$EndPAD -$PAD -Sh "G2" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 30 "/DDR_Banks/M0_CLK" -Po -944 196 -$EndPAD -$PAD -Sh "G3" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 29 "/DDR_Banks/M0_CLK#" -Po -629 196 -$EndPAD -$PAD -Sh "G7" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_WE#" -Po 629 196 -$EndPAD -$PAD -Sh "G8" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 47 "/DDR_Banks/M0_CAS#" -Po 944 196 -$EndPAD -$PAD -Sh "H2" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A12" -Po -944 590 -$EndPAD -$PAD -Sh "H3" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_CKE" -Po -629 590 -$EndPAD -$PAD -Sh "H7" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 48 "/DDR_Banks/M0_RAS#" -Po 629 590 -$EndPAD -$PAD -Sh "H8" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 944 590 -$EndPAD -$PAD -Sh "J2" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 4 "/DDR_Banks/M0_A11" -Po -944 983 -$EndPAD -$PAD -Sh "J3" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_A9" -Po -629 983 -$EndPAD -$PAD -Sh "J7" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 629 983 -$EndPAD -$PAD -Sh "J8" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 944 983 -$EndPAD -$PAD -Sh "K2" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_A8" -Po -944 1377 -$EndPAD -$PAD -Sh "K3" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 32 "/DDR_Banks/M0_A7" -Po -629 1377 -$EndPAD -$PAD -Sh "K7" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 28 "/DDR_Banks/M0_A0" -Po 629 1377 -$EndPAD -$PAD -Sh "K8" O 157 157 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 24 "/DDR_Banks/M0_A10" -Po 944 1377 -$EndPAD -$PAD -Sh "L2" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 39 "/DDR_Banks/M0_A6" -Po -944 1771 -$EndPAD -$PAD -Sh "L3" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 46 "/DDR_Banks/M0_A5" -Po -629 1771 -$EndPAD -$PAD -Sh "L7" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 31 "/DDR_Banks/M0_A2" -Po 629 1771 -$EndPAD -$PAD -Sh "L8" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 27 "/DDR_Banks/M0_A1" -Po 944 1771 -$EndPAD -$PAD -Sh "M2" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_A4" -Po -944 2165 -$EndPAD -$PAD -Sh "M3" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -629 2165 -$EndPAD -$PAD -Sh "M7" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 101 "N-000046" -Po 629 2165 -$EndPAD -$PAD -Sh "M8" O 157 158 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 49 "/DDR_Banks/M0_A3" -Po 944 2165 -$EndPAD -$EndMODULE 60fbga_ddr -$MODULE 60fbga_ddr -Po 63529 32225 0 15 4C58C755 4C58CA3A ~~ -Li 60fbga_ddr -Sc 4C58CA3A -AR /4C421DD3/4C58CA3A -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"U3" -T1 0 150 200 200 0 40 N I 25 N"MT46V32M16FN" -DC -1771 -2283 -1771 -2362 39 21 -DS -1968 2460 -1968 -2460 39 21 -DS -1968 -2460 1968 -2460 39 21 -DS 1968 -2460 1968 2460 39 21 -DS 1968 2460 -1968 2460 39 21 -$PAD -Sh "A1" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -1259 -2165 -$EndPAD -$PAD -Sh "A9" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 102 "N-000048" -Po 1259 -2165 -$EndPAD -$PAD -Sh "B1" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 85 "/DDR_Banks/M1_DQ14" -Po -1259 -1771 -$EndPAD -$PAD -Sh "B9" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 67 "/DDR_Banks/M1_DQ1" -Po 1259 -1771 -$EndPAD -$PAD -Sh "C1" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 81 "/DDR_Banks/M1_DQ12" -Po -1259 -1377 -$EndPAD -$PAD -Sh "C9" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 63 "/DDR_Banks/M1_DQ3" -Po 1259 -1377 -$EndPAD -$PAD -Sh "D1" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 74 "/DDR_Banks/M1_DQ10" -Po -1259 -983 -$EndPAD -$PAD -Sh "D9" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 43 "/DDR_Banks/M1_DQ5" -Po 1259 -983 -$EndPAD -$PAD -Sh "E1" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 70 "/DDR_Banks/M1_DQ8" -Po -1259 -590 -$EndPAD -$PAD -Sh "E9" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 53 "/DDR_Banks/M1_DQ7" -Po 1259 -590 -$EndPAD -$PAD -Sh "F1" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -1259 -196 -$EndPAD -$PAD -Sh "F9" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 1259 -196 -$EndPAD -$PAD -Sh "A2" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 86 "/DDR_Banks/M1_DQ15" -Po -944 -2165 -$EndPAD -$PAD -Sh "A3" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -629 -2165 -$EndPAD -$PAD -Sh "A7" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 102 "N-000048" -Po 629 -2165 -$EndPAD -$PAD -Sh "A8" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 66 "/DDR_Banks/M1_DQ0" -Po 944 -2165 -$EndPAD -$PAD -Sh "B2" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 102 "N-000048" -Po -944 -1771 -$EndPAD -$PAD -Sh "B3" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 82 "/DDR_Banks/M1_DQ13" -Po -629 -1771 -$EndPAD -$PAD -Sh "B7" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 62 "/DDR_Banks/M1_DQ2" -Po 629 -1771 -$EndPAD -$PAD -Sh "B8" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po 944 -1771 -$EndPAD -$PAD -Sh "C2" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -944 -1377 -$EndPAD -$PAD -Sh "C3" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 75 "/DDR_Banks/M1_DQ11" -Po -629 -1377 -$EndPAD -$PAD -Sh "C7" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 42 "/DDR_Banks/M1_DQ4" -Po 629 -1377 -$EndPAD -$PAD -Sh "C8" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 102 "N-000048" -Po 944 -1377 -$EndPAD -$PAD -Sh "D2" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 102 "N-000048" -Po -944 -983 -$EndPAD -$PAD -Sh "D3" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 71 "/DDR_Banks/M1_DQ9" -Po -629 -983 -$EndPAD -$PAD -Sh "D7" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 52 "/DDR_Banks/M1_DQ6" -Po 629 -983 -$EndPAD -$PAD -Sh "D8" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po 944 -983 -$EndPAD -$PAD -Sh "E2" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -944 -590 -$EndPAD -$PAD -Sh "E3" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 78 "/DDR_Banks/M1_UDQS" -Po -629 -590 -$EndPAD -$PAD -Sh "E7" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 57 "/DDR_Banks/M1_LDQS" -Po 629 -590 -$EndPAD -$PAD -Sh "E8" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 102 "N-000048" -Po 944 -590 -$EndPAD -$PAD -Sh "F2" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -944 -196 -$EndPAD -$PAD -Sh "F3" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 61 "/DDR_Banks/M1_UDM" -Po -629 -196 -$EndPAD -$PAD -Sh "F7" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 56 "/DDR_Banks/M1_LDM" -Po 629 -196 -$EndPAD -$PAD -Sh "F8" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 102 "N-000048" -Po 944 -196 -$EndPAD -$PAD -Sh "G2" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_CLK" -Po -944 196 -$EndPAD -$PAD -Sh "G3" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 41 "/DDR_Banks/M1_CLK#" -Po -629 196 -$EndPAD -$PAD -Sh "G7" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_WE#" -Po 629 196 -$EndPAD -$PAD -Sh "G8" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_CAS#" -Po 944 196 -$EndPAD -$PAD -Sh "H2" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 13 "/DDR_Banks/M1_A12" -Po -944 590 -$EndPAD -$PAD -Sh "H3" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 12 "/DDR_Banks/M1_CKE" -Po -629 590 -$EndPAD -$PAD -Sh "H7" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_RAS#" -Po 629 590 -$EndPAD -$PAD -Sh "H8" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 944 590 -$EndPAD -$PAD -Sh "J2" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_A11" -Po -944 983 -$EndPAD -$PAD -Sh "J3" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 8 "/DDR_Banks/M1_A9" -Po -629 983 -$EndPAD -$PAD -Sh "J7" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 629 983 -$EndPAD -$PAD -Sh "J8" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 944 983 -$EndPAD -$PAD -Sh "K2" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 6 "/DDR_Banks/M1_A8" -Po -944 1377 -$EndPAD -$PAD -Sh "K3" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 16 "/DDR_Banks/M1_A7" -Po -629 1377 -$EndPAD -$PAD -Sh "K7" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_A0" -Po 629 1377 -$EndPAD -$PAD -Sh "K8" O 157 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A10" -Po 944 1377 -$EndPAD -$PAD -Sh "L2" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 50 "/DDR_Banks/M1_A6" -Po -944 1771 -$EndPAD -$PAD -Sh "L3" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 51 "/DDR_Banks/M1_A5" -Po -629 1771 -$EndPAD -$PAD -Sh "L7" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 17 "/DDR_Banks/M1_A2" -Po 629 1771 -$EndPAD -$PAD -Sh "L8" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A1" -Po 944 1771 -$EndPAD -$PAD -Sh "M2" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_A4" -Po -944 2165 -$EndPAD -$PAD -Sh "M3" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po -629 2165 -$EndPAD -$PAD -Sh "M7" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 102 "N-000048" -Po 629 2165 -$EndPAD -$PAD -Sh "M8" O 157 158 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_A3" -Po 944 2165 -$EndPAD -$EndMODULE 60fbga_ddr -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5F2CA3 ~~ -Li 0402 -Sc 4C5F2CA3 -AR /4C5F1EDC/4C5F2CA3 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"V?" -T1 0 150 200 200 0 40 N I 25 N"V0402MHS03" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 103 "N-000409" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5F2CA3 ~~ -Li 0402 -Sc 4C5F2CA3 -AR /4C5F1EDC/4C5F2CA3 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"V?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D719D ~~ -Li 0402 -Sc 4C5D719D -AR /4C4320F3/4C5D719D -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"R?" -T1 0 150 200 200 0 40 N I 25 N"220" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 104 "N-000389" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 94 "/Ethernet_Phy/ETH_LED0" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7F39 ~~ -Li 0402 -Sc 4C5D7F39 -AR /4C4320F3/4C5D7F39 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"R?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7ECF ~~ -Li 0402 -Sc 4C5D7ECF -AR /4C4320F3/4C5D7ECF -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"R?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7DC4 ~~ -Li 0402 -Sc 4C5D7DC4 -AR /4C4320F3/4C5D7DC4 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"R?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7AFE ~~ -Li 0402 -Sc 4C5D7AFE -AR /4C4320F3/4C5D7AFE -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"R?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7AFC ~~ -Li 0402 -Sc 4C5D7AFC -AR /4C4320F3/4C5D7AFC -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"R?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7AF9 ~~ -Li 0402 -Sc 4C5D7AF9 -AR /4C4320F3/4C5D7AF9 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"R?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7AF7 ~~ -Li 0402 -Sc 4C5D7AF7 -AR /4C4320F3/4C5D7AF7 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"R?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D71DB ~~ -Li 0402 -Sc 4C5D71DB -AR /4C4320F3/4C5D71DB -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"R?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D719D ~~ -Li 0402 -Sc 4C5D719D -AR /4C4320F3/4C5D719D -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"R?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7FB7 ~~ -Li 0402 -Sc 4C5D7FB7 -AR /4C4320F3/4C5D7FB7 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"L?" -T1 0 150 200 200 0 40 N I 25 N"FB" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 87 "N-000068" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 92 "/Ethernet_Phy/ETH_A3.3V" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D80F3 ~~ -Li 0402 -Sc 4C5D80F3 -AR /4C4320F3/4C5D80F3 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"L?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7FB7 ~~ -Li 0402 -Sc 4C5D7FB7 -AR /4C4320F3/4C5D7FB7 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"L?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7DCB ~~ -Li 0402 -Sc 4C5D7DCB -AR /4C4320F3/4C5D7DCB -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"47nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 105 "N-000393" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 1 "GND" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5F2039 ~~ -Li 0402 -Sc 4C5F2039 -AR /4C5F1EDC/4C5F2039 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5F2037 ~~ -Li 0402 -Sc 4C5F2037 -AR /4C5F1EDC/4C5F2037 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5F2033 ~~ -Li 0402 -Sc 4C5F2033 -AR /4C5F1EDC/4C5F2033 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D8114 ~~ -Li 0402 -Sc 4C5D8114 -AR /4C4320F3/4C5D8114 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D8104 ~~ -Li 0402 -Sc 4C5D8104 -AR /4C4320F3/4C5D8104 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D80F0 ~~ -Li 0402 -Sc 4C5D80F0 -AR /4C4320F3/4C5D80F0 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D80ED ~~ -Li 0402 -Sc 4C5D80ED -AR /4C4320F3/4C5D80ED -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7FA7 ~~ -Li 0402 -Sc 4C5D7FA7 -AR /4C4320F3/4C5D7FA7 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7FA5 ~~ -Li 0402 -Sc 4C5D7FA5 -AR /4C4320F3/4C5D7FA5 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7FA3 ~~ -Li 0402 -Sc 4C5D7FA3 -AR /4C4320F3/4C5D7FA3 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7FA1 ~~ -Li 0402 -Sc 4C5D7FA1 -AR /4C4320F3/4C5D7FA1 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7F9F ~~ -Li 0402 -Sc 4C5D7F9F -AR /4C4320F3/4C5D7F9F -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7E43 ~~ -Li 0402 -Sc 4C5D7E43 -AR /4C4320F3/4C5D7E43 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7E41 ~~ -Li 0402 -Sc 4C5D7E41 -AR /4C4320F3/4C5D7E41 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 0 0 0 15 4C5FF890 4C5D7DCB ~~ -Li 0402 -Sc 4C5D7DCB -AR /4C4320F3/4C5D7DCB -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"C?" -T1 0 150 200 200 0 40 N I 25 N"Val*" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 -$PAD -Sh "1" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 1210 -Po 36900 35050 900 15 4C5FF890 4C5F2B55 ~~ -Li 1210 -Sc 4C5F2B55 -AR /4C5F1EDC/4C5F2B55 -Op 0 0 0 -At SMD -T0 0 -150 200 200 900 40 N V 25 N"F?" -T1 0 150 200 200 900 40 N I 25 N"MICROSMD075F" -DS -798 542 -798 -542 50 21 -DS -798 -542 798 -542 50 21 -DS 798 -542 798 542 50 21 -DS 798 542 -798 542 50 21 -$PAD -Sh "1" R 355 984 0 0 900 -Dr 0 0 0 -At SMD N 00888000 -Ne 106 "N-000411" -Po -570 0 -$EndPAD -$PAD -Sh "2" R 355 984 0 0 900 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 570 0 -$EndPAD -$EndMODULE 1210 $MODULE MICROSD-500901 Po 57990 45510 0 15 4C5F34DA 4B76F5E2 ~~ Li MICROSD-500901 @@ -6654,28 +4990,28 @@ $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 2707 -1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -2707 -1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po -2707 2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 2707 2244 $EndPAD $EndMODULE MICROSD-500901 @@ -6695,190 +5031,115 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 105 "N-000393" +Ne 98 "N-000400" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 105 "N-000393" +Ne 98 "N-000400" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 105 "N-000393" +Ne 98 "N-000400" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 105 "N-000393" +Ne 98 "N-000400" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 90 "N-000391" +Ne 96 "N-000398" Po -1750 -2500 $EndPAD $PAD Sh "3" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 87 "N-000068" +Ne 85 "3.3V" Po -750 -2500 $EndPAD $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 1 "GND" +Ne 86 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 98 "N-000392" +Ne 97 "N-000399" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 91 "N-000386" +Ne 102 "N-000406" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 1 "GND" +Ne 86 "GND" Po -250 -3500 $EndPAD $PAD Sh "6" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 87 "N-000068" +Ne 85 "3.3V" Po 750 -3500 $EndPAD $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 97 "N-000385" +Ne 101 "N-000405" Po 1750 -3500 $EndPAD $PAD Sh "9" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 87 "N-000068" +Ne 85 "3.3V" Po -2150 -5400 $EndPAD $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 104 "N-000389" +Ne 95 "N-000396" Po -1150 -5400 $EndPAD $PAD Sh "11" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 87 "N-000068" +Ne 85 "3.3V" Po 1150 -5400 $EndPAD $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 107 "N-000388" +Ne 100 "N-000404" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 -$MODULE USB-48204 -Po 33090 37720 2700 15 4C5F28A8 4C5F23DD ~~ -Li USB-48204 -Sc 4C5F23DD -AR /4C5F1EDC/4C5F23DD -Op 0 0 0 -T0 120 -3162 157 157 2700 20 N V 21 N"J?" -T1 0 118 118 118 900 20 N I 21 N"USB-48204-0001" -DS -1499 5299 -1704 5299 60 21 -DS -1704 5299 -1704 5178 60 21 -DS -1704 5178 -1502 5178 60 21 -DS 1500 5298 1708 5298 60 21 -DS 1708 5298 1707 5180 60 21 -DS 1707 5180 1499 5181 60 21 -DS -1500 -3000 -1500 5300 60 21 -DS -1500 -3000 1500 -3000 60 21 -DS 1500 -3000 1500 5300 60 21 -DS -1500 5300 1500 5300 60 21 -$PAD -Sh "1" R 470 470 0 0 2700 -Dr 360 0 0 -At STD N 0CC0FFFF -Ne 106 "N-000411" -Po 0 -2362 -$EndPAD -$PAD -Sh "2" C 470 470 0 0 2700 -Dr 360 0 0 -At STD N 0CC0FFFF -Ne 103 "N-000409" -Po 0 -1575 -$EndPAD -$PAD -Sh "3" C 470 470 0 0 2700 -Dr 360 0 0 -At STD N 0CC0FFFF -Ne 108 "N-000410" -Po 0 -787 -$EndPAD -$PAD -Sh "3" C 470 470 0 0 2700 -Dr 360 0 0 -At STD N 0CC0FFFF -Ne 108 "N-000410" -Po 0 0 -$EndPAD -$PAD -Sh "S1" C 670 670 0 0 2700 -Dr 532 0 0 -At STD N 0CC0FFFF -Ne 109 "N-000412" -Po 1077 287 -$EndPAD -$PAD -Sh "S2" C 670 670 0 0 2700 -Dr 532 0 0 -At STD N 0CC0FFFF -Ne 109 "N-000412" -Po -1077 287 -$EndPAD -$PAD -Sh "S3" C 670 670 0 0 2700 -Dr 532 0 0 -At STD N 0CC0FFFF -Ne 109 "N-000412" -Po 1077 -2468 -$EndPAD -$PAD -Sh "S4" C 670 670 0 0 2700 -Dr 532 0 0 -At STD N 0CC0FFFF -Ne 109 "N-000412" -Po -1077 -2468 -$EndPAD -$EndMODULE USB-48204 $MODULE TSSOP-14 Po 39240 37670 900 15 4C60642A 4C5F2025 ~~ Li TSSOP-14 @@ -6904,7 +5165,7 @@ $PAD Sh "1" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000068" +Ne 85 "3.3V" Po -767 1112 $EndPAD $PAD @@ -6946,14 +5207,14 @@ $PAD Sh "7" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 767 1112 $EndPAD $PAD Sh "8" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 86 "GND" Po 767 -1112 $EndPAD $PAD @@ -6967,21 +5228,21 @@ $PAD Sh "10" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "N-000409" +Ne 103 "N-000420" Po 255 -1112 $EndPAD $PAD Sh "11" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000410" +Ne 104 "N-000426" Po 0 -1112 $EndPAD $PAD Sh "12" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000068" +Ne 85 "3.3V" Po -255 -1112 $EndPAD $PAD @@ -6995,10 +5256,964 @@ $PAD Sh "14" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000068" +Ne 85 "3.3V" Po -767 -1112 $EndPAD $EndMODULE TSSOP-14 +$MODULE TSOP-66 +Po 63780 34055 900 15 4C6098A7 4C60B7B8 ~~ +Li TSOP-66 +Sc 4C60B7B8 +AR /4C421DD3/4C609C8E +Op 0 0 0 +At SMD +T0 0 -150 200 200 900 40 N V 25 N"U3" +T1 0 150 200 200 900 40 N I 25 N"MT46V32M16TG" +DC -4094 1881 -4094 1822 39 21 +DS 4350 -1968 4350 1968 39 21 +DS 4350 1968 -4350 1968 39 21 +DS -4350 1968 -4350 -1968 39 21 +DS -4350 -1968 4350 -1968 39 21 +$PAD +Sh "1" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000048" +Po -4094 2176 +$EndPAD +$PAD +Sh "2" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 73 "/FPGA_Sp59" +Po -3838 2176 +$EndPAD +$PAD +Sh "3" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000048" +Po -3582 2176 +$EndPAD +$PAD +Sh "4" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 74 "/FPGA_Sp60" +Po -3326 2176 +$EndPAD +$PAD +Sh "5" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3070 2176 +$EndPAD +$PAD +Sh "6" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -2814 2176 +$EndPAD +$PAD +Sh "7" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2558 2176 +$EndPAD +$PAD +Sh "8" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2303 2176 +$EndPAD +$PAD +Sh "9" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000048" +Po -2047 2176 +$EndPAD +$PAD +Sh "10" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 58 "/FPGA_Sp39" +Po -1791 2176 +$EndPAD +$PAD +Sh "11" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 11 "/DDR_Ban47" +Po -1535 2176 +$EndPAD +$PAD +Sh "12" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -1279 2176 +$EndPAD +$PAD +Sh "13" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 12 "/DDR_Ban48" +Po -1023 2176 +$EndPAD +$PAD +Sh "14" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -767 2176 +$EndPAD +$PAD +Sh "15" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000048" +Po -511 2176 +$EndPAD +$PAD +Sh "16" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 67 "/FPGA_Sp52" +Po -255 2176 +$EndPAD +$PAD +Sh "17" R 136 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 2176 +$EndPAD +$PAD +Sh "18" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000048" +Po 255 2176 +$EndPAD +$PAD +Sh "19" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 511 2176 +$EndPAD +$PAD +Sh "20" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 66 "/FPGA_Sp51" +Po 767 2176 +$EndPAD +$PAD +Sh "21" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 5 "/DDR_Ban31" +Po 1023 2176 +$EndPAD +$PAD +Sh "22" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "/DDR_Ban34" +Po 1279 2176 +$EndPAD +$PAD +Sh "23" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 55 "/FPGA_Sp33" +Po 1535 2176 +$EndPAD +$PAD +Sh "24" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1791 2176 +$EndPAD +$PAD +Sh "25" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2047 2176 +$EndPAD +$PAD +Sh "26" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2302 2176 +$EndPAD +$PAD +Sh "27" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 2176 +$EndPAD +$PAD +Sh "28" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 49 "/FPGA_Sp24" +Po 2814 2176 +$EndPAD +$PAD +Sh "29" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 46 "/FPGA_Sp21" +Po 3070 2176 +$EndPAD +$PAD +Sh "30" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 47 "/FPGA_Sp22" +Po 3326 2176 +$EndPAD +$PAD +Sh "31" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 41 "/FPGA_Sp16" +Po 3582 2176 +$EndPAD +$PAD +Sh "32" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 27 "/DDR_Banks/M1_A3" +Po 3838 2176 +$EndPAD +$PAD +Sh "33" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000048" +Po 4094 2176 +$EndPAD +$PAD +Sh "34" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po 4094 -2176 +$EndPAD +$PAD +Sh "35" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 45 "/FPGA_Sp20" +Po 3838 -2176 +$EndPAD +$PAD +Sh "36" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 28 "/DDR_Banks/M1_A5" +Po 3582 -2176 +$EndPAD +$PAD +Sh "37" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 63 "/FPGA_Sp46" +Po 3326 -2176 +$EndPAD +$PAD +Sh "38" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 40 "/FPGA_Sp15" +Po 3070 -2176 +$EndPAD +$PAD +Sh "39" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 83 "/FPGA_Sp9" +Po 2814 -2176 +$EndPAD +$PAD +Sh "40" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 37 "/FPGA_Sp10" +Po 2558 -2176 +$EndPAD +$PAD +Sh "41" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 44 "/FPGA_Sp19" +Po 2303 -2176 +$EndPAD +$PAD +Sh "42" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 39 "/FPGA_Sp14" +Po 2047 -2176 +$EndPAD +$PAD +Sh "43" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1791 -2176 +$EndPAD +$PAD +Sh "44" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 8 "/DDR_Ban38" +Po 1535 -2176 +$EndPAD +$PAD +Sh "45" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 38 "/FPGA_Sp13" +Po 1279 -2176 +$EndPAD +$PAD +Sh "46" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 54 "/FPGA_Sp32" +Po 1023 -2176 +$EndPAD +$PAD +Sh "47" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 71 "/FPGA_Sp56" +Po 767 -2176 +$EndPAD +$PAD +Sh "48" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po 511 -2176 +$EndPAD +$PAD +Sh "49" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 255 -2176 +$EndPAD +$PAD +Sh "50" R 136 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 -2176 +$EndPAD +$PAD +Sh "51" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 19 "/DDR_Ban70" +Po -255 -2176 +$EndPAD +$PAD +Sh "52" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -511 -2176 +$EndPAD +$PAD +Sh "53" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -767 -2176 +$EndPAD +$PAD +Sh "54" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 15 "/DDR_Ban63" +Po -1023 -2176 +$EndPAD +$PAD +Sh "55" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000048" +Po -1279 -2176 +$EndPAD +$PAD +Sh "56" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 76 "/FPGA_Sp64" +Po -1535 -2176 +$EndPAD +$PAD +Sh "57" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 17 "/DDR_Ban67" +Po -1791 -2176 +$EndPAD +$PAD +Sh "58" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -2047 -2176 +$EndPAD +$PAD +Sh "59" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 18 "/DDR_Ban68" +Po -2303 -2176 +$EndPAD +$PAD +Sh "60" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 80 "/FPGA_Sp73" +Po -2558 -2176 +$EndPAD +$PAD +Sh "61" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000048" +Po -2814 -2176 +$EndPAD +$PAD +Sh "62" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 81 "/FPGA_Sp74" +Po -3070 -2176 +$EndPAD +$PAD +Sh "63" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 82 "/FPGA_Sp77" +Po -3326 -2176 +$EndPAD +$PAD +Sh "64" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -3582 -2176 +$EndPAD +$PAD +Sh "65" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 23 "/DDR_Ban78" +Po -3838 -2176 +$EndPAD +$PAD +Sh "66" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -4094 -2176 +$EndPAD +$EndMODULE TSOP-66 +$MODULE TSOP-66 +Po 49016 34055 900 15 4C6098A7 4C60B7BA ~~ +Li TSOP-66 +Sc 4C60B7BA +AR /4C421DD3/4C609B99 +Op 0 0 0 +At SMD +T0 0 -150 200 200 900 40 N V 25 N"U2" +T1 0 150 200 200 900 40 N I 25 N"MT46V32M16TG" +DC -4094 1881 -4094 1822 39 21 +DS 4350 -1968 4350 1968 39 21 +DS 4350 1968 -4350 1968 39 21 +DS -4350 1968 -4350 -1968 39 21 +DS -4350 -1968 4350 -1968 39 21 +$PAD +Sh "1" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "N-000056" +Po -4094 2176 +$EndPAD +$PAD +Sh "2" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 72 "/FPGA_Sp58" +Po -3838 2176 +$EndPAD +$PAD +Sh "3" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "N-000056" +Po -3582 2176 +$EndPAD +$PAD +Sh "4" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/DDR_Ban57" +Po -3326 2176 +$EndPAD +$PAD +Sh "5" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 69 "/FPGA_Sp54" +Po -3070 2176 +$EndPAD +$PAD +Sh "6" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -2814 2176 +$EndPAD +$PAD +Sh "7" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 68 "/FPGA_Sp53" +Po -2558 2176 +$EndPAD +$PAD +Sh "8" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "/DDR_Ban36" +Po -2303 2176 +$EndPAD +$PAD +Sh "9" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "N-000056" +Po -2047 2176 +$EndPAD +$PAD +Sh "10" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 56 "/FPGA_Sp35" +Po -1791 2176 +$EndPAD +$PAD +Sh "11" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 60 "/FPGA_Sp41" +Po -1535 2176 +$EndPAD +$PAD +Sh "12" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -1279 2176 +$EndPAD +$PAD +Sh "13" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 59 "/FPGA_Sp40" +Po -1023 2176 +$EndPAD +$PAD +Sh "14" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -767 2176 +$EndPAD +$PAD +Sh "15" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "N-000056" +Po -511 2176 +$EndPAD +$PAD +Sh "16" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 64 "/FPGA_Sp49" +Po -255 2176 +$EndPAD +$PAD +Sh "17" R 136 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 2176 +$EndPAD +$PAD +Sh "18" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "N-000056" +Po 255 2176 +$EndPAD +$PAD +Sh "19" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 511 2176 +$EndPAD +$PAD +Sh "20" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "/FPGA_Sp50" +Po 767 2176 +$EndPAD +$PAD +Sh "21" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 42 "/FPGA_Sp17" +Po 1023 2176 +$EndPAD +$PAD +Sh "22" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 9 "/DDR_Ban43" +Po 1279 2176 +$EndPAD +$PAD +Sh "23" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "/DDR_Ban44" +Po 1535 2176 +$EndPAD +$PAD +Sh "24" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1791 2176 +$EndPAD +$PAD +Sh "25" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2047 2176 +$EndPAD +$PAD +Sh "26" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2302 2176 +$EndPAD +$PAD +Sh "27" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 2176 +$EndPAD +$PAD +Sh "28" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 48 "/FPGA_Sp23" +Po 2814 2176 +$EndPAD +$PAD +Sh "29" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 51 "/FPGA_Sp26" +Po 3070 2176 +$EndPAD +$PAD +Sh "30" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 50 "/FPGA_Sp25" +Po 3326 2176 +$EndPAD +$PAD +Sh "31" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 52 "/FPGA_Sp29" +Po 3582 2176 +$EndPAD +$PAD +Sh "32" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 62 "/FPGA_Sp45" +Po 3838 2176 +$EndPAD +$PAD +Sh "33" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "N-000056" +Po 4094 2176 +$EndPAD +$PAD +Sh "34" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po 4094 -2176 +$EndPAD +$PAD +Sh "35" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 43 "/FPGA_Sp18" +Po 3838 -2176 +$EndPAD +$PAD +Sh "36" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 61 "/FPGA_Sp42" +Po 3582 -2176 +$EndPAD +$PAD +Sh "37" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 57 "/FPGA_Sp37" +Po 3326 -2176 +$EndPAD +$PAD +Sh "38" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 53 "/FPGA_Sp30" +Po 3070 -2176 +$EndPAD +$PAD +Sh "39" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 25 "/DDR_Banks/M0_A8" +Po 2814 -2176 +$EndPAD +$PAD +Sh "40" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 26 "/DDR_Banks/M0_A9" +Po 2558 -2176 +$EndPAD +$PAD +Sh "41" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 24 "/DDR_Ban8" +Po 2303 -2176 +$EndPAD +$PAD +Sh "42" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "/DDR_Ban11" +Po 2047 -2176 +$EndPAD +$PAD +Sh "43" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1791 -2176 +$EndPAD +$PAD +Sh "44" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "/DDR_Ban27" +Po 1535 -2176 +$EndPAD +$PAD +Sh "45" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 2 "/DDR_Ban12" +Po 1279 -2176 +$EndPAD +$PAD +Sh "46" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "/DDR_Ban28" +Po 1023 -2176 +$EndPAD +$PAD +Sh "47" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 70 "/FPGA_Sp55" +Po 767 -2176 +$EndPAD +$PAD +Sh "48" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po 511 -2176 +$EndPAD +$PAD +Sh "49" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 255 -2176 +$EndPAD +$PAD +Sh "50" R 136 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 -2176 +$EndPAD +$PAD +Sh "51" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 78 "/FPGA_Sp69" +Po -255 -2176 +$EndPAD +$PAD +Sh "52" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -511 -2176 +$EndPAD +$PAD +Sh "53" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -767 -2176 +$EndPAD +$PAD +Sh "54" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/DDR_Ban62" +Po -1023 -2176 +$EndPAD +$PAD +Sh "55" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "N-000056" +Po -1279 -2176 +$EndPAD +$PAD +Sh "56" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 75 "/FPGA_Sp61" +Po -1535 -2176 +$EndPAD +$PAD +Sh "57" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 77 "/FPGA_Sp66" +Po -1791 -2176 +$EndPAD +$PAD +Sh "58" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -2047 -2176 +$EndPAD +$PAD +Sh "59" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 16 "/DDR_Ban65" +Po -2303 -2176 +$EndPAD +$PAD +Sh "60" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 20 "/DDR_Ban72" +Po -2558 -2176 +$EndPAD +$PAD +Sh "61" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "N-000056" +Po -2814 -2176 +$EndPAD +$PAD +Sh "62" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 79 "/FPGA_Sp71" +Po -3070 -2176 +$EndPAD +$PAD +Sh "63" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 22 "/DDR_Ban76" +Po -3326 -2176 +$EndPAD +$PAD +Sh "64" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -3582 -2176 +$EndPAD +$PAD +Sh "65" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 21 "/DDR_Ban75" +Po -3838 -2176 +$EndPAD +$PAD +Sh "66" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "GND" +Po -4094 -2176 +$EndPAD +$EndMODULE TSOP-66 $TRACK $EndTRACK $ZONE diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp index badce76..2ba6b17 100644 --- a/kicad/xue-rnc/xue-rnc.cmp +++ b/kicad/xue-rnc/xue-rnc.cmp @@ -1,122 +1,122 @@ -Cmp-Mod V01 Created by CVpcb (20090216-final) date = Mon 09 Aug 2010 03:24:50 PM COT - -BeginCmp -TimeStamp = /4C4320F3/4C5D7DCB; -Reference = C?; -ValeurCmp = 47nF; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7E41; -Reference = C?; -ValeurCmp = 100nF; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7E43; -Reference = C?; -ValeurCmp = 100nF; -IdModule = 0402; -EndCmp +Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Mon 09 Aug 2010 09:21:21 PM COT BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; -Reference = C?; +Reference = C1; ValeurCmp = 1uF; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7FA1; -Reference = C?; -ValeurCmp = 100nF; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7FA3; -Reference = C?; -ValeurCmp = 100nF; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7FA5; -Reference = C?; -ValeurCmp = 1uF; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7FA7; -Reference = C?; -ValeurCmp = 100nF; -IdModule = 0402; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D80ED; -Reference = C?; +Reference = C2; ValeurCmp = C; -IdModule = 0402; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7FA1; +Reference = C3; +ValeurCmp = 100nF; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D80F0; -Reference = C?; +Reference = C4; ValeurCmp = C; -IdModule = 0402; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7FA3; +Reference = C5; +ValeurCmp = 100nF; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D8104; -Reference = C?; +Reference = C6; ValeurCmp = C; -IdModule = 0402; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7FA5; +Reference = C7; +ValeurCmp = 1uF; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7FA7; +Reference = C8; +ValeurCmp = 100nF; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D8114; -Reference = C?; +Reference = C9; ValeurCmp = C; -IdModule = 0402; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7E41; +Reference = C10; +ValeurCmp = 100nF; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7E43; +Reference = C11; +ValeurCmp = 100nF; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7DCB; +Reference = C12; +ValeurCmp = 47nF; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C5F1EDC/4C5F2033; -Reference = C?; +Reference = C13; ValeurCmp = 1uF; -IdModule = 0402; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C5F1EDC/4C5F2037; -Reference = C?; +Reference = C14; ValeurCmp = 1uF; -IdModule = 0402; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C5F1EDC/4C5F2039; -Reference = C?; +Reference = C15; ValeurCmp = 470nF; -IdModule = 0402; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C5F1EDC/4C5F2D1E; -Reference = C?; +Reference = C16; ValeurCmp = 4.7nF; -IdModule = 0402; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C5F1EDC/4C5F2B55; -Reference = F?; +Reference = F1; ValeurCmp = MICROSMD075F; -IdModule = 1210; +IdModule = ; EndCmp BeginCmp @@ -135,100 +135,100 @@ EndCmp BeginCmp TimeStamp = /4C5F1EDC/4C5F23DD; -Reference = J?; +Reference = J5; ValeurCmp = USB-48204-0001; -IdModule = USB-48204; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7FB7; -Reference = L?; -ValeurCmp = FB; -IdModule = 0402; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D80F3; -Reference = L?; +Reference = L1; ValeurCmp = INDUCTOR; -IdModule = 0402; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7FB7; +Reference = L2; +ValeurCmp = FB; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D810A; -Reference = L?; +Reference = L3; ValeurCmp = INDUCTOR; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D719D; -Reference = R?; -ValeurCmp = 220; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D71DB; -Reference = R?; -ValeurCmp = 220; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7AF7; -Reference = R?; -ValeurCmp = 49.9; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7AF9; -Reference = R?; -ValeurCmp = 49.9; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7AFC; -Reference = R?; -ValeurCmp = 49.9; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7AFE; -Reference = R?; -ValeurCmp = 49.9; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7DC4; -Reference = R?; -ValeurCmp = 1M; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C4320F3/4C5D7ECF; -Reference = R?; -ValeurCmp = 6.65K; -IdModule = 0402; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7F39; -Reference = R?; +Reference = R1; ValeurCmp = 4.7K; -IdModule = 0402; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7ECF; +Reference = R2; +ValeurCmp = 6.65K; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7AFE; +Reference = R3; +ValeurCmp = 49.9; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7AFC; +Reference = R4; +ValeurCmp = 49.9; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7AF7; +Reference = R5; +ValeurCmp = 49.9; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7AF9; +Reference = R6; +ValeurCmp = 49.9; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D719D; +Reference = R7; +ValeurCmp = 220; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D71DB; +Reference = R8; +ValeurCmp = 220; +IdModule = ; +EndCmp + +BeginCmp +TimeStamp = /4C4320F3/4C5D7DC4; +Reference = R9; +ValeurCmp = 1M; +IdModule = ; EndCmp BeginCmp TimeStamp = /4C5F1EDC/4C5F2D27; -Reference = R?; +Reference = R10; ValeurCmp = 1M; -IdModule = 0402; +IdModule = ; EndCmp BeginCmp @@ -239,17 +239,17 @@ IdModule = FGG484bga-p10; EndCmp BeginCmp -TimeStamp = /4C421DD3/4C58C847; +TimeStamp = /4C421DD3/4C609B99; Reference = U2; -ValeurCmp = MT46V32M16FN; -IdModule = 60fbga_ddr; +ValeurCmp = MT46V32M16TG; +IdModule = TSOP-66; EndCmp BeginCmp -TimeStamp = /4C421DD3/4C58CA3A; +TimeStamp = /4C421DD3/4C609C8E; Reference = U3; -ValeurCmp = MT46V32M16FN; -IdModule = 60fbga_ddr; +ValeurCmp = MT46V32M16TG; +IdModule = TSOP-66; EndCmp BeginCmp @@ -274,17 +274,17 @@ IdModule = TSSOP-14; EndCmp BeginCmp -TimeStamp = /4C5F1EDC/4C5F2CA3; -Reference = V?; +TimeStamp = /4C5F1EDC/4C5F2CA7; +Reference = V1; ValeurCmp = V0402MHS03; -IdModule = 0402; +IdModule = ; EndCmp BeginCmp -TimeStamp = /4C5F1EDC/4C5F2CA7; -Reference = V?; +TimeStamp = /4C5F1EDC/4C5F2CA3; +Reference = V2; ValeurCmp = V0402MHS03; -IdModule = 0402; +IdModule = ; EndCmp EndListe diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 8a039c6..a7a6324 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,1588 +1,1045 @@ -# EESchema Netlist Version 1.1 created Mon 09 Aug 2010 03:31:28 PM COT +# EESchema Netlist Version 1.1 created Mon 09 Aug 2010 09:21:21 PM COT ( - ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} - ( H9 N-000119 ) - ( U11 N-000119 ) - ( F11 N-000119 ) - ( R6 N-000119 ) - ( M15 N-000119 ) - ( V6 N-000119 ) - ( G12 N-000119 ) - ( H15 N-000119 ) - ( D16 N-000119 ) - ( K15 N-000119 ) - ( R12 N-000119 ) - ( N8 N-000119 ) - ( R10 N-000119 ) - ( L8 N-000119 ) - ( N10 N-000118 ) - ( P11 N-000118 ) - ( P13 N-000118 ) - ( P9 N-000118 ) - ( R14 N-000118 ) - ( N12 N-000118 ) - ( J10 N-000118 ) - ( J12 N-000118 ) - ( J14 N-000118 ) - ( J8 N-000118 ) - ( K11 N-000118 ) - ( K13 N-000118 ) - ( K9 N-000118 ) - ( L10 N-000118 ) - ( L12 N-000118 ) - ( L14 N-000118 ) - ( M11 N-000118 ) - ( M13 N-000118 ) - ( M9 N-000118 ) - ( N14 N-000118 ) - ( G13 ? ) - ( G8 ? ) - ( G9 ? ) - ( H10 ? ) - ( H11 ? ) - ( H12 ? ) - ( H13 ? ) - ( H14 ? ) - ( P16 ? ) - ( D13 ? ) - ( AA1 ? ) - ( N15 ? ) - ( G15 ? ) - ( E18 ? ) - ( A19 ? ) - ( C18 ? ) - ( G11 ? ) - ( F9 ? ) - ( F8 ? ) - ( F15 ? ) - ( F14 ? ) - ( F13 ? ) - ( F12 ? ) - ( F10 ? ) - ( E8 ? ) - ( E14 ? ) - ( E12 ? ) - ( E10 ? ) - ( D12 ? ) - ( P15 ? ) - ( R17 ? ) - ( Y22 ? ) - ( P10 GND ) - ( V10 GND ) - ( M10 GND ) - ( K10 GND ) - ( L13 GND ) - ( A1 GND ) - ( N13 GND ) - ( A22 GND ) - ( R5 GND ) - ( AA13 GND ) - ( W19 GND ) - ( AA17 GND ) - ( K14 GND ) - ( AA5 GND ) - ( L5 GND ) - ( AA9 GND ) - ( M14 GND ) - ( AB1 GND ) - ( N2 GND ) - ( AB22 GND ) - ( P14 GND ) - ( B13 GND ) - ( U21 GND ) - ( B17 GND ) - ( V4 GND ) - ( B5 GND ) - ( J9 GND ) - ( B9 GND ) - ( K12 GND ) - ( D18 GND ) - ( L11 GND ) - ( D4 GND ) - ( L18 GND ) - ( E11 GND ) - ( L9 GND ) - ( E15 GND ) - ( M12 GND ) - ( E2 GND ) - ( N11 GND ) - ( E21 GND ) - ( N17 GND ) - ( E7 GND ) - ( N21 GND ) - ( G18 GND ) - ( P12 GND ) - ( G5 GND ) - ( R18 GND ) - ( H7 GND ) - ( U2 GND ) - ( J11 GND ) - ( U7 GND ) - ( J13 GND ) - ( V14 GND ) - ( J15 GND ) - ( W16 GND ) - ( J2 GND ) - ( W7 GND ) - ( J21 GND ) - ( N9 GND ) - ( AA15 N-000123 ) - ( V16 N-000123 ) - ( T13 N-000123 ) - ( V8 N-000123 ) - ( V12 N-000123 ) - ( AA3 N-000123 ) - ( T9 N-000123 ) - ( AA19 N-000123 ) - ( AA11 N-000123 ) - ( W5 N-000123 ) - ( AA7 N-000123 ) - ( AA12 ? ) - ( AB12 ? ) - ( Y11 ? ) - ( AB11 ? ) - ( R11 ? ) - ( T11 ? ) + ( /4C4320F3/4C5D7F9F $noname$ C1 1uF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D80ED $noname$ C2 C + ( 1 /Etherne1 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FA1 $noname$ C3 100nF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D80F0 $noname$ C4 C + ( 1 N-000417 ) + ( 2 N-000416 ) + ) + ( /4C4320F3/4C5D7FA3 $noname$ C5 100nF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D8104 $noname$ C6 C + ( 1 /Etherne2 ) + ( 2 N-000416 ) + ) + ( /4C4320F3/4C5D7FA5 $noname$ C7 1uF + ( 1 /Etherne3 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FA7 $noname$ C8 100nF + ( 1 /Etherne3 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D8114 $noname$ C9 C + ( 1 /Etherne4 ) + ( 2 N-000416 ) + ) + ( /4C4320F3/4C5D7E41 $noname$ C10 100nF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7E43 $noname$ C11 100nF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7DCB $noname$ C12 47nF + ( 1 N-000400 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2033 $noname$ C13 1uF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2037 $noname$ C14 1uF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2039 $noname$ C15 470nF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2D1E $noname$ C16 4.7nF + ( 1 N-000428 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2B55 $noname$ F1 MICROSMD075F + ( 1 N-000427 ) + ( 2 ? ) + ) + ( /4C4227FE/4B76F5E2 MICROSD-500901 J1 MICROSD + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 ? ) + ( 7 ? ) + ( 8 ? ) + ( CASE GND ) + ( CD ? ) + ( COM GND ) + ) + ( /4C4320F3/4C5D6F5A SD-48025 J4 RJ45-48025 + ( 1 N-000398 ) + ( 2 N-000406 ) + ( 3 3.3V ) + ( 4 GND ) + ( 5 GND ) + ( 6 3.3V ) + ( 7 N-000399 ) + ( 8 N-000405 ) + ( 9 3.3V ) + ( 10 N-000396 ) + ( 11 3.3V ) + ( 12 N-000404 ) + ( 13 N-000400 ) + ( 14 N-000400 ) + ) + ( /4C5F1EDC/4C5F23DD $noname$ J5 USB-48204-0001 + ( 1 N-000427 ) + ( 2 N-000420 ) + ( 3 N-000426 ) + ( 4 GND ) + ( S1 N-000428 ) + ( S2 N-000428 ) + ( S3 N-000428 ) + ( S4 N-000428 ) + ) + ( /4C4320F3/4C5D80F3 $noname$ L1 INDUCTOR + ( 1 N-000417 ) + ( 2 /Etherne2 ) + ) + ( /4C4320F3/4C5D7FB7 $noname$ L2 FB + ( 1 3.3V ) + ( 2 /Etherne3 ) + ) + ( /4C4320F3/4C5D810A $noname$ L3 INDUCTOR + ( 1 /Etherne2 ) + ( 2 /Etherne4 ) + ) + ( /4C4320F3/4C5D7F39 $noname$ R1 4.7K + ( 1 /ETH_MDIO ) + ( 2 3.3V ) + ) + ( /4C4320F3/4C5D7ECF $noname$ R2 6.65K + ( 1 N-000402 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7AFE $noname$ R3 49.9 + ( 1 3.3V ) + ( 2 N-000398 ) + ) + ( /4C4320F3/4C5D7AFC $noname$ R4 49.9 + ( 1 3.3V ) + ( 2 N-000406 ) + ) + ( /4C4320F3/4C5D7AF7 $noname$ R5 49.9 + ( 1 3.3V ) + ( 2 N-000399 ) + ) + ( /4C4320F3/4C5D7AF9 $noname$ R6 49.9 + ( 1 3.3V ) + ( 2 N-000405 ) + ) + ( /4C4320F3/4C5D719D $noname$ R7 220 + ( 1 N-000396 ) + ( 2 /Etherne5 ) + ) + ( /4C4320F3/4C5D71DB $noname$ R8 220 + ( 1 N-000404 ) + ( 2 /Etherne6 ) + ) + ( /4C4320F3/4C5D7DC4 $noname$ R9 1M + ( 1 N-000400 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2D27 $noname$ R10 1M + ( 1 N-000428 ) + ( 2 GND ) + ) + ( /4C431A63/4C431E53 FGG484bga-p10 U1 XC6SLX45FGG484 + ( A1 GND ) + ( A2 ? ) + ( A4 ? ) + ( A5 /Etherne7 ) + ( A6 ? ) + ( A7 ? ) + ( A8 ? ) + ( A9 ? ) + ( A10 ? ) + ( A11 ? ) + ( A12 ? ) + ( A13 ? ) + ( A14 ? ) + ( A15 ? ) + ( A16 ? ) + ( A17 ? ) + ( A18 ? ) + ( A19 ? ) + ( A20 ? ) + ( A21 ? ) + ( A22 GND ) + ( AA1 ? ) + ( AA2 ? ) + ( AA3 N-000152 ) + ( AA4 ? ) + ( AA5 GND ) + ( AA6 ? ) + ( AA7 N-000152 ) + ( AA8 ? ) + ( AA9 GND ) ( AA10 ? ) - ( AB10 ? ) - ( V11 ? ) - ( W11 ? ) - ( Y9 ? ) - ( AB9 ? ) - ( W10 ? ) - ( Y10 ? ) - ( AA8 ? ) - ( AB8 ? ) - ( W8 ? ) - ( V7 ? ) - ( W9 ? ) - ( Y8 ? ) - ( Y7 ? ) - ( AB7 ? ) - ( AA6 ? ) - ( AB6 ? ) - ( U9 ? ) - ( V9 ? ) - ( T8 ? ) - ( U8 ? ) - ( T10 ? ) - ( U10 ? ) - ( W6 ? ) - ( Y6 ? ) - ( Y5 ? ) - ( AB5 ? ) - ( AA4 ? ) - ( AB4 ? ) - ( Y3 ? ) - ( AB3 ? ) - ( R9 ? ) - ( R8 ? ) - ( T7 ? ) - ( R7 ? ) - ( W4 ? ) - ( Y4 ? ) - ( U6 ? ) - ( V5 ? ) - ( AA2 ? ) - ( AB2 ? ) - ( T6 ? ) - ( T5 ? ) - ( AB13 ? ) - ( Y13 ? ) - ( Y12 ? ) - ( W12 ? ) - ( R13 ? ) - ( T14 ? ) - ( U12 ? ) - ( T12 ? ) - ( AB15 ? ) - ( Y15 ? ) - ( Y14 ? ) - ( W14 ? ) - ( AB16 ? ) - ( AA16 ? ) - ( W13 ? ) - ( V13 ? ) - ( W15 ? ) - ( Y16 ? ) - ( AB14 ? ) + ( AA11 N-000152 ) + ( AA12 ? ) + ( AA13 GND ) ( AA14 ? ) - ( AB17 ? ) - ( Y17 ? ) - ( AB18 ? ) + ( AA15 N-000152 ) + ( AA16 ? ) + ( AA17 GND ) ( AA18 ? ) - ( V15 ? ) - ( U15 ? ) - ( U13 ? ) - ( U14 ? ) - ( W17 ? ) - ( V17 ? ) - ( R15 ? ) - ( R16 ? ) - ( V18 ? ) - ( V19 ? ) - ( U16 ? ) - ( U17 ? ) - ( T15 ? ) - ( T16 ? ) - ( Y18 ? ) - ( W18 ? ) - ( AB19 ? ) - ( Y19 ? ) - ( T17 ? ) - ( T18 ? ) - ( AB20 ? ) + ( AA19 N-000152 ) ( AA20 ? ) - ( AB21 ? ) ( AA21 ? ) ( AA22 ? ) - ( W2 N-000120 ) - ( L2 N-000120 ) - ( L7 N-000120 ) - ( C2 N-000120 ) - ( N5 N-000120 ) - ( R2 N-000120 ) - ( U5 N-000120 ) - ( G2 N-000120 ) - ( F4 N-000120 ) - ( F6 N-000120 ) - ( J5 N-000120 ) - ( M3 /DDR_Banks/M0_UDM ) - ( L4 /DDR_Banks/M0_LDM ) - ( K5 /DDR_Banks/M0_RAS# ) - ( K4 /DDR_Banks/M0_CAS# ) - ( K3 /DDR_Banks/M0_A5 ) - ( J4 /DDR_Banks/M0_A6 ) - ( K6 /DDR_Banks/M0_A3 ) - ( J6 ? ) - ( H4 /DDR_Banks/M0_CLK ) - ( H3 /DDR_Banks/M0_CLK# ) - ( H2 /DDR_Banks/M0_A0 ) - ( H1 /DDR_Banks/M0_A1 ) - ( G3 ? ) - ( G1 ? ) - ( H6 /DDR_Banks/M0_A7 ) - ( H5 /DDR_Banks/M0_A2 ) - ( F2 /DDR_Banks/M0_WE# ) - ( F1 ? ) - ( G4 /DDR_Banks/M0_A10 ) - ( F3 /DDR_Banks/M0_A4 ) - ( E3 /DDR_Banks/M0_A8 ) - ( E1 /DDR_Banks/M0_A9 ) - ( D2 /DDR_Banks/M0_CKE ) - ( D1 /DDR_Banks/M0_A12 ) - ( C3 ? ) - ( C1 /DDR_Banks/M0_A11 ) - ( G6 ? ) - ( F5 ? ) - ( K7 ? ) - ( K8 ? ) - ( D5 ? ) - ( E4 ? ) - ( J7 ? ) - ( H8 ? ) - ( B2 ? ) - ( B1 ? ) - ( G7 ? ) - ( F7 ? ) - ( D3 ? ) - ( C4 ? ) - ( E5 ? ) - ( E6 ? ) - ( A2 ? ) - ( B3 ? ) - ( J1 /DDR_Banks/M0_DQ5 ) - ( J3 /DDR_Banks/M0_DQ4 ) - ( K1 /DDR_Banks/M0_DQ7 ) - ( K2 /DDR_Banks/M0_DQ6 ) - ( L1 ? ) - ( L3 /DDR_Banks/M0_LDQS ) - ( M1 /DDR_Banks/M0_DQ3 ) - ( M2 /DDR_Banks/M0_DQ2 ) - ( N1 /DDR_Banks/M0_DQ1 ) - ( N3 /DDR_Banks/M0_DQ0 ) - ( P1 /DDR_Banks/M0_DQ9 ) - ( P2 /DDR_Banks/M0_DQ8 ) - ( R1 /DDR_Banks/M0_DQ11 ) - ( R3 /DDR_Banks/M0_DQ10 ) - ( T1 ? ) - ( T2 /DDR_Banks/M0_UDQS ) - ( U1 /DDR_Banks/M0_DQ13 ) - ( U3 /DDR_Banks/M0_DQ12 ) - ( V1 /DDR_Banks/M0_DQ15 ) - ( V2 /DDR_Banks/M0_DQ14 ) - ( M4 ? ) - ( M5 ? ) - ( N4 ? ) - ( P3 ? ) - ( L6 ? ) - ( M6 ? ) - ( P4 ? ) - ( R4 ? ) - ( M8 ? ) - ( M7 ? ) - ( N7 ? ) - ( N6 ? ) - ( V3 ? ) - ( U4 ? ) - ( T3 ? ) - ( T4 ? ) - ( P5 ? ) - ( P6 ? ) - ( P7 ? ) - ( P8 ? ) - ( W1 ? ) - ( W3 ? ) - ( Y1 ? ) - ( W21 N-000121 ) - ( C21 N-000121 ) - ( G21 N-000121 ) - ( J18 N-000121 ) - ( L16 N-000121 ) - ( L21 N-000121 ) - ( N18 N-000121 ) - ( R21 N-000121 ) - ( U18 N-000121 ) - ( E19 N-000121 ) - ( L19 /DDR_Banks/M1_LDM ) - ( J20 /DDR_Banks/M1_DQ4 ) - ( J22 /DDR_Banks/M1_DQ5 ) - ( K21 /DDR_Banks/M1_DQ6 ) - ( K22 /DDR_Banks/M1_DQ7 ) - ( L20 /DDR_Banks/M1_LDQS ) - ( L22 ? ) - ( M21 /DDR_Banks/M1_DQ2 ) - ( M22 /DDR_Banks/M1_DQ3 ) - ( N20 /DDR_Banks/M1_DQ0 ) - ( N22 /DDR_Banks/M1_DQ1 ) - ( P21 /DDR_Banks/M1_DQ8 ) - ( P22 /DDR_Banks/M1_DQ9 ) - ( R20 /DDR_Banks/M1_DQ10 ) - ( R22 /DDR_Banks/M1_DQ11 ) - ( T21 /DDR_Banks/M1_UDQS ) - ( T22 ? ) - ( U20 /DDR_Banks/M1_DQ12 ) - ( U22 /DDR_Banks/M1_DQ13 ) - ( V21 /DDR_Banks/M1_DQ14 ) - ( V22 /DDR_Banks/M1_DQ15 ) - ( M19 ? ) - ( N19 ? ) - ( M16 ? ) - ( L15 ? ) - ( P19 ? ) - ( P20 ? ) - ( W20 ? ) - ( W22 ? ) - ( L17 ? ) - ( K18 ? ) - ( U19 ? ) - ( V20 ? ) - ( M17 ? ) - ( M18 ? ) - ( P17 ? ) - ( N16 ? ) - ( P18 ? ) - ( R19 ? ) - ( T19 ? ) - ( T20 ? ) - ( M20 /DDR_Banks/M1_UDM ) - ( H22 /DDR_Banks/M1_CAS# ) - ( H21 /DDR_Banks/M1_RAS# ) - ( K19 /DDR_Banks/M1_A6 ) - ( K20 /DDR_Banks/M1_A5 ) - ( G22 ? ) - ( G20 /DDR_Banks/M1_A3 ) - ( J19 /DDR_Banks/M1_CLK# ) - ( H20 /DDR_Banks/M1_CLK ) - ( F22 /DDR_Banks/M1_A1 ) - ( F21 /DDR_Banks/M1_A0 ) - ( K17 ? ) - ( J17 ? ) - ( E22 /DDR_Banks/M1_A2 ) - ( E20 /DDR_Banks/M1_A7 ) - ( H18 ? ) - ( H19 /DDR_Banks/M1_WE# ) - ( F20 /DDR_Banks/M1_A4 ) - ( G19 /DDR_Banks/M1_A10 ) - ( C22 /DDR_Banks/M1_A9 ) - ( C20 /DDR_Banks/M1_A8 ) - ( D22 /DDR_Banks/M1_A12 ) - ( D21 /DDR_Banks/M1_CKE ) - ( F19 /DDR_Banks/M1_A11 ) - ( F18 ? ) - ( D20 ? ) - ( D19 ? ) - ( H17 ? ) - ( H16 ? ) - ( J16 ? ) - ( K16 ? ) - ( A21 ? ) - ( A20 ? ) - ( B22 ? ) - ( B21 ? ) - ( F17 ? ) - ( F16 ? ) - ( G17 ? ) - ( G16 ? ) - ( B20 ? ) - ( B4 N-000122 ) - ( B7 N-000122 ) - ( E13 N-000122 ) - ( E17 N-000122 ) - ( G10 N-000122 ) - ( G14 N-000122 ) - ( B11 N-000122 ) - ( B15 N-000122 ) - ( B19 N-000122 ) - ( E9 N-000122 ) - ( A11 ? ) - ( D11 ? ) - ( C12 ? ) - ( B12 ? ) - ( A12 ? ) - ( C13 ? ) - ( A13 ? ) - ( D14 ? ) - ( C14 ? ) - ( B14 ? ) - ( A14 ? ) - ( C15 ? ) - ( A15 ? ) - ( D15 ? ) - ( C16 ? ) - ( B16 ? ) - ( A16 ? ) - ( C17 ? ) - ( A17 ? ) - ( B18 ? ) - ( A18 ? ) - ( E16 ? ) - ( D17 ? ) - ( C11 ? ) - ( A10 ? ) - ( B10 ? ) - ( C10 ? ) - ( D10 ? ) - ( D8 ? ) - ( D7 ? ) - ( A9 ? ) - ( C9 ? ) - ( C8 ? ) - ( D9 ? ) - ( A8 ? ) - ( B8 ? ) - ( A7 ? ) - ( C7 ? ) - ( A6 ? ) - ( B6 ? ) - ( C6 ? ) - ( D6 ? ) - ( A5 /FPGA_Spartan6/ETH_INT ) - ( C5 ? ) - ( A4 ? ) + ( AB1 GND ) + ( AB2 ? ) + ( AB3 ? ) + ( AB4 ? ) + ( AB5 ? ) + ( AB6 ? ) + ( AB7 ? ) + ( AB8 ? ) + ( AB9 ? ) + ( AB10 ? ) + ( AB11 ? ) + ( AB12 ? ) + ( AB13 ? ) + ( AB14 ? ) + ( AB15 ? ) + ( AB16 ? ) + ( AB17 ? ) + ( AB18 ? ) + ( AB19 ? ) + ( AB20 ? ) + ( AB21 ? ) + ( AB22 GND ) + ( B1 ? ) + ( B2 ? ) + ( B3 ? ) + ( B4 N-000153 ) + ( B5 GND ) + ( B6 ? ) + ( B7 N-000153 ) + ( B8 ? ) + ( B9 GND ) + ( B10 ? ) + ( B11 N-000153 ) + ( B12 ? ) + ( B13 GND ) + ( B14 ? ) + ( B15 N-000153 ) + ( B16 ? ) + ( B17 GND ) + ( B18 ? ) + ( B19 N-000153 ) + ( B20 ? ) + ( B21 ? ) + ( B22 ? ) + ( C1 /DDR_Ban8 ) + ( C2 N-000158 ) + ( C3 ? ) + ( C4 ? ) + ( C5 ? ) + ( C6 ? ) + ( C7 ? ) + ( C8 ? ) + ( C9 ? ) + ( C10 ? ) + ( C11 ? ) + ( C12 ? ) + ( C13 ? ) + ( C14 ? ) + ( C15 ? ) + ( C16 ? ) + ( C17 ? ) + ( C18 ? ) + ( C20 /FPGA_Sp9 ) + ( C21 N-000154 ) + ( C22 /FPGA_Sp10 ) + ( D1 /DDR_Ban11 ) + ( D2 /DDR_Ban12 ) + ( D3 ? ) + ( D4 GND ) + ( D5 ? ) + ( D6 ? ) + ( D7 ? ) + ( D8 ? ) + ( D9 ? ) + ( D10 ? ) + ( D11 ? ) + ( D12 ? ) + ( D13 ? ) + ( D14 ? ) + ( D15 ? ) + ( D16 N-000160 ) + ( D17 ? ) + ( D18 GND ) + ( D19 ? ) + ( D20 ? ) + ( D21 /FPGA_Sp13 ) + ( D22 /FPGA_Sp14 ) + ( E1 /DDR_Banks/M0_A9 ) + ( E2 GND ) + ( E3 /DDR_Banks/M0_A8 ) + ( E4 ? ) + ( E5 ? ) + ( E6 ? ) + ( E7 GND ) + ( E8 ? ) + ( E9 N-000153 ) + ( E10 ? ) + ( E11 GND ) + ( E12 ? ) + ( E13 N-000153 ) + ( E14 ? ) + ( E15 GND ) + ( E16 ? ) + ( E17 N-000153 ) + ( E18 ? ) + ( E19 N-000154 ) + ( E20 /FPGA_Sp15 ) + ( E21 GND ) + ( E22 /FPGA_Sp16 ) + ( F1 ? ) + ( F2 /FPGA_Sp17 ) + ( F3 /FPGA_Sp18 ) + ( F4 N-000158 ) + ( F5 ? ) + ( F6 N-000158 ) + ( F7 ? ) + ( F8 ? ) + ( F9 ? ) + ( F10 ? ) + ( F11 N-000160 ) + ( F12 ? ) + ( F13 ? ) + ( F14 ? ) + ( F15 ? ) + ( F16 ? ) + ( F17 ? ) + ( F18 ? ) + ( F19 /FPGA_Sp19 ) + ( F20 /FPGA_Sp20 ) + ( F21 /FPGA_Sp21 ) + ( F22 /FPGA_Sp22 ) + ( G1 ? ) + ( G2 N-000158 ) + ( G3 ? ) + ( G4 /FPGA_Sp23 ) + ( G5 GND ) + ( G6 ? ) + ( G7 ? ) + ( G8 ? ) + ( G9 ? ) + ( G10 N-000153 ) + ( G11 ? ) + ( G12 N-000160 ) + ( G13 ? ) + ( G14 N-000153 ) + ( G15 ? ) + ( G16 ? ) + ( G17 ? ) + ( G18 GND ) + ( G19 /FPGA_Sp24 ) + ( G20 /DDR_Banks/M1_A3 ) + ( G21 N-000154 ) + ( G22 ? ) + ( H1 /FPGA_Sp25 ) + ( H2 /FPGA_Sp26 ) + ( H3 /DDR_Ban27 ) + ( H4 /DDR_Ban28 ) + ( H5 /FPGA_Sp29 ) + ( H6 /FPGA_Sp30 ) + ( H7 GND ) + ( H8 ? ) + ( H9 N-000160 ) + ( H10 ? ) + ( H11 ? ) + ( H12 ? ) + ( H13 ? ) + ( H14 ? ) + ( H15 N-000160 ) + ( H16 ? ) + ( H17 ? ) + ( H18 ? ) + ( H19 /DDR_Ban31 ) + ( H20 /FPGA_Sp32 ) + ( H21 /FPGA_Sp33 ) + ( H22 /DDR_Ban34 ) + ( J1 /FPGA_Sp35 ) + ( J2 GND ) + ( J3 /DDR_Ban36 ) + ( J4 /FPGA_Sp37 ) + ( J5 N-000158 ) + ( J6 ? ) + ( J7 ? ) + ( J8 N-000159 ) + ( J9 GND ) + ( J10 N-000159 ) + ( J11 GND ) + ( J12 N-000159 ) + ( J13 GND ) + ( J14 N-000159 ) + ( J15 GND ) + ( J16 ? ) + ( J17 ? ) + ( J18 N-000154 ) + ( J19 /DDR_Ban38 ) + ( J20 ? ) + ( J21 GND ) + ( J22 /FPGA_Sp39 ) + ( K1 /FPGA_Sp40 ) + ( K2 /FPGA_Sp41 ) + ( K3 /FPGA_Sp42 ) + ( K4 /DDR_Ban43 ) + ( K5 /DDR_Ban44 ) + ( K6 /FPGA_Sp45 ) + ( K7 ? ) + ( K8 ? ) + ( K9 N-000159 ) + ( K10 GND ) + ( K11 N-000159 ) + ( K12 GND ) + ( K13 N-000159 ) + ( K14 GND ) + ( K15 N-000160 ) + ( K16 ? ) + ( K17 ? ) + ( K18 ? ) + ( K19 /FPGA_Sp46 ) + ( K20 /DDR_Banks/M1_A5 ) + ( K21 /DDR_Ban47 ) + ( K22 /DDR_Ban48 ) + ( L1 ? ) + ( L2 N-000158 ) + ( L3 /FPGA_Sp49 ) + ( L4 /FPGA_Sp50 ) + ( L5 GND ) + ( L6 ? ) + ( L7 N-000158 ) + ( L8 N-000160 ) + ( L9 GND ) + ( L10 N-000159 ) + ( L11 GND ) + ( L12 N-000159 ) + ( L13 GND ) + ( L14 N-000159 ) + ( L15 ? ) + ( L16 N-000154 ) + ( L17 ? ) + ( L18 GND ) + ( L19 /FPGA_Sp51 ) + ( L20 /FPGA_Sp52 ) + ( L21 N-000154 ) + ( L22 ? ) + ( M1 /FPGA_Sp53 ) + ( M2 /FPGA_Sp54 ) + ( M3 /FPGA_Sp55 ) + ( M4 ? ) + ( M5 ? ) + ( M6 ? ) + ( M7 ? ) + ( M8 ? ) + ( M9 N-000159 ) + ( M10 GND ) + ( M11 N-000159 ) + ( M12 GND ) + ( M13 N-000159 ) + ( M14 GND ) + ( M15 N-000160 ) + ( M16 ? ) + ( M17 ? ) + ( M18 ? ) + ( M19 ? ) + ( M20 /FPGA_Sp56 ) + ( M21 ? ) + ( M22 ? ) + ( N1 /DDR_Ban57 ) + ( N2 GND ) + ( N3 /FPGA_Sp58 ) + ( N4 ? ) + ( N5 N-000158 ) + ( N6 ? ) + ( N7 ? ) + ( N8 N-000160 ) + ( N9 GND ) + ( N10 N-000159 ) + ( N11 GND ) + ( N12 N-000159 ) + ( N13 GND ) + ( N14 N-000159 ) + ( N15 ? ) + ( N16 ? ) + ( N17 GND ) + ( N18 N-000154 ) + ( N19 ? ) + ( N20 /FPGA_Sp59 ) + ( N21 GND ) + ( N22 /FPGA_Sp60 ) + ( P1 /FPGA_Sp61 ) + ( P2 /DDR_Ban62 ) + ( P3 ? ) + ( P4 ? ) + ( P5 ? ) + ( P6 ? ) + ( P7 ? ) + ( P8 ? ) + ( P9 N-000159 ) + ( P10 GND ) + ( P11 N-000159 ) + ( P12 GND ) + ( P13 N-000159 ) + ( P14 GND ) + ( P15 ? ) + ( P16 ? ) + ( P17 ? ) + ( P18 ? ) + ( P19 ? ) + ( P20 ? ) + ( P21 /DDR_Ban63 ) + ( P22 /FPGA_Sp64 ) + ( R1 /DDR_Ban65 ) + ( R2 N-000158 ) + ( R3 /FPGA_Sp66 ) + ( R4 ? ) + ( R5 GND ) + ( R6 N-000160 ) + ( R7 ? ) + ( R8 ? ) + ( R9 ? ) + ( R10 N-000160 ) + ( R11 ? ) + ( R12 N-000160 ) + ( R13 ? ) + ( R14 N-000159 ) + ( R15 ? ) + ( R16 ? ) + ( R17 ? ) + ( R18 GND ) + ( R19 ? ) + ( R20 /DDR_Ban67 ) + ( R21 N-000154 ) + ( R22 /DDR_Ban68 ) + ( T1 ? ) + ( T2 /FPGA_Sp69 ) + ( T3 ? ) + ( T4 ? ) + ( T5 ? ) + ( T6 ? ) + ( T7 ? ) + ( T8 ? ) + ( T9 N-000152 ) + ( T10 ? ) + ( T11 ? ) + ( T12 ? ) + ( T13 N-000152 ) + ( T14 ? ) + ( T15 ? ) + ( T16 ? ) + ( T17 ? ) + ( T18 ? ) + ( T19 ? ) + ( T20 ? ) + ( T21 /DDR_Ban70 ) + ( T22 ? ) + ( U1 /FPGA_Sp71 ) + ( U2 GND ) + ( U3 /DDR_Ban72 ) + ( U4 ? ) + ( U5 N-000158 ) + ( U6 ? ) + ( U7 GND ) + ( U8 ? ) + ( U9 ? ) + ( U10 ? ) + ( U11 N-000160 ) + ( U12 ? ) + ( U13 ? ) + ( U14 ? ) + ( U15 ? ) + ( U16 ? ) + ( U17 ? ) + ( U18 N-000154 ) + ( U19 ? ) + ( U20 /FPGA_Sp73 ) + ( U21 GND ) + ( U22 /FPGA_Sp74 ) + ( V1 /DDR_Ban75 ) + ( V2 /DDR_Ban76 ) + ( V3 ? ) + ( V4 GND ) + ( V5 ? ) + ( V6 N-000160 ) + ( V7 ? ) + ( V8 N-000152 ) + ( V9 ? ) + ( V10 GND ) + ( V11 ? ) + ( V12 N-000152 ) + ( V13 ? ) + ( V14 GND ) + ( V15 ? ) + ( V16 N-000152 ) + ( V17 ? ) + ( V18 ? ) + ( V19 ? ) + ( V20 ? ) + ( V21 /FPGA_Sp77 ) + ( V22 /DDR_Ban78 ) + ( W1 ? ) + ( W2 N-000158 ) + ( W3 ? ) + ( W4 ? ) + ( W5 N-000152 ) + ( W6 ? ) + ( W7 GND ) + ( W8 ? ) + ( W9 ? ) + ( W10 ? ) + ( W11 ? ) + ( W12 ? ) + ( W13 ? ) + ( W14 ? ) + ( W15 ? ) + ( W16 GND ) + ( W17 ? ) + ( W18 ? ) + ( W19 GND ) + ( W20 ? ) + ( W21 N-000154 ) + ( W22 ? ) + ( Y1 ? ) + ( Y3 ? ) + ( Y4 ? ) + ( Y5 ? ) + ( Y6 ? ) + ( Y7 ? ) + ( Y8 ? ) + ( Y9 ? ) + ( Y10 ? ) + ( Y11 ? ) + ( Y12 ? ) + ( Y13 ? ) + ( Y14 ? ) + ( Y15 ? ) + ( Y16 ? ) + ( Y17 ? ) + ( Y18 ? ) + ( Y19 ? ) + ( Y22 ? ) ) - ( /4C5F1EDC/4C5F2D27 $noname R? 1M {Lib=R} - ( 1 N-000412 ) - ( 2 GND ) + ( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG + ( 1 N-000056 ) + ( 2 /FPGA_Sp58 ) + ( 3 N-000056 ) + ( 4 /DDR_Ban57 ) + ( 5 /FPGA_Sp54 ) + ( 6 GND ) + ( 7 /FPGA_Sp53 ) + ( 8 /DDR_Ban36 ) + ( 9 N-000056 ) + ( 10 /FPGA_Sp35 ) + ( 11 /FPGA_Sp41 ) + ( 12 GND ) + ( 13 /FPGA_Sp40 ) + ( 14 ? ) + ( 15 N-000056 ) + ( 16 /FPGA_Sp49 ) + ( 17 ? ) + ( 18 N-000056 ) + ( 19 ? ) + ( 20 /FPGA_Sp50 ) + ( 21 /FPGA_Sp17 ) + ( 22 /DDR_Ban43 ) + ( 23 /DDR_Ban44 ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 /FPGA_Sp23 ) + ( 29 /FPGA_Sp26 ) + ( 30 /FPGA_Sp25 ) + ( 31 /FPGA_Sp29 ) + ( 32 /FPGA_Sp45 ) + ( 33 N-000056 ) + ( 34 GND ) + ( 35 /FPGA_Sp18 ) + ( 36 /FPGA_Sp42 ) + ( 37 /FPGA_Sp37 ) + ( 38 /FPGA_Sp30 ) + ( 39 /DDR_Banks/M0_A8 ) + ( 40 /DDR_Banks/M0_A9 ) + ( 41 /DDR_Ban8 ) + ( 42 /DDR_Ban11 ) + ( 43 ? ) + ( 44 /DDR_Ban27 ) + ( 45 /DDR_Ban12 ) + ( 46 /DDR_Ban28 ) + ( 47 /FPGA_Sp55 ) + ( 48 GND ) + ( 49 ? ) + ( 50 ? ) + ( 51 /FPGA_Sp69 ) + ( 52 GND ) + ( 53 ? ) + ( 54 /DDR_Ban62 ) + ( 55 N-000056 ) + ( 56 /FPGA_Sp61 ) + ( 57 /FPGA_Sp66 ) + ( 58 GND ) + ( 59 /DDR_Ban65 ) + ( 60 /DDR_Ban72 ) + ( 61 N-000056 ) + ( 62 /FPGA_Sp71 ) + ( 63 /DDR_Ban76 ) + ( 64 GND ) + ( 65 /DDR_Ban75 ) + ( 66 GND ) ) - ( /4C5F1EDC/4C5F2D1E $noname C? 4.7nF {Lib=C} - ( 1 N-000412 ) - ( 2 GND ) + ( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG + ( 1 N-000048 ) + ( 2 /FPGA_Sp59 ) + ( 3 N-000048 ) + ( 4 /FPGA_Sp60 ) + ( 5 ? ) + ( 6 GND ) + ( 7 ? ) + ( 8 ? ) + ( 9 N-000048 ) + ( 10 /FPGA_Sp39 ) + ( 11 /DDR_Ban47 ) + ( 12 GND ) + ( 13 /DDR_Ban48 ) + ( 14 ? ) + ( 15 N-000048 ) + ( 16 /FPGA_Sp52 ) + ( 17 ? ) + ( 18 N-000048 ) + ( 19 ? ) + ( 20 /FPGA_Sp51 ) + ( 21 /DDR_Ban31 ) + ( 22 /DDR_Ban34 ) + ( 23 /FPGA_Sp33 ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 /FPGA_Sp24 ) + ( 29 /FPGA_Sp21 ) + ( 30 /FPGA_Sp22 ) + ( 31 /FPGA_Sp16 ) + ( 32 /DDR_Banks/M1_A3 ) + ( 33 N-000048 ) + ( 34 GND ) + ( 35 /FPGA_Sp20 ) + ( 36 /DDR_Banks/M1_A5 ) + ( 37 /FPGA_Sp46 ) + ( 38 /FPGA_Sp15 ) + ( 39 /FPGA_Sp9 ) + ( 40 /FPGA_Sp10 ) + ( 41 /FPGA_Sp19 ) + ( 42 /FPGA_Sp14 ) + ( 43 ? ) + ( 44 /DDR_Ban38 ) + ( 45 /FPGA_Sp13 ) + ( 46 /FPGA_Sp32 ) + ( 47 /FPGA_Sp56 ) + ( 48 GND ) + ( 49 ? ) + ( 50 ? ) + ( 51 /DDR_Ban70 ) + ( 52 GND ) + ( 53 ? ) + ( 54 /DDR_Ban63 ) + ( 55 N-000048 ) + ( 56 /FPGA_Sp64 ) + ( 57 /DDR_Ban67 ) + ( 58 GND ) + ( 59 /DDR_Ban68 ) + ( 60 /FPGA_Sp73 ) + ( 61 N-000048 ) + ( 62 /FPGA_Sp74 ) + ( 63 /FPGA_Sp77 ) + ( 64 GND ) + ( 65 /DDR_Ban78 ) + ( 66 GND ) ) - ( /4C5F1EDC/4C5F2CA7 $noname V? V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000410 ) - ( 2 GND ) + ( /4C4320F3/4C432132 LQFP48 U4 K8001 + ( 1 /ETH_MDIO ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 ? ) + ( 7 3.3V ) + ( 8 GND ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 GND ) + ( 13 /Etherne1 ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ( 17 ? ) + ( 18 ? ) + ( 19 ? ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 GND ) + ( 24 3.3V ) + ( 25 /Etherne7 ) + ( 26 /Etherne5 ) + ( 27 /Etherne6 ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 /Etherne2 ) + ( 32 N-000405 ) + ( 33 N-000399 ) + ( 34 ? ) + ( 35 GND ) + ( 36 GND ) + ( 37 N-000402 ) + ( 38 /Etherne3 ) + ( 39 GND ) + ( 40 N-000406 ) + ( 41 N-000398 ) + ( 42 ? ) + ( 43 ? ) + ( 44 GND ) + ( 45 ? ) + ( 46 ? ) + ( 47 /Etherne4 ) + ( 48 ? ) ) - ( /4C5F1EDC/4C5F2CA3 $noname V? V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000409 ) - ( 2 GND ) + ( /4C4227FE/4B76F108 NAND-48TSOP U5 NAND + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 /Non_vol79 ) + ( 7 /Non_vol79 ) + ( 8 ? ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 3.3V ) + ( 13 GND ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ( 17 ? ) + ( 18 ? ) + ( 19 3.3V ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 ? ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 ? ) + ( 32 ? ) + ( 33 ? ) + ( 34 ? ) + ( 35 ? ) + ( 36 GND ) + ( 37 3.3V ) + ( 38 ? ) + ( 39 ? ) + ( 40 ? ) + ( 41 ? ) + ( 42 ? ) + ( 43 ? ) + ( 44 ? ) + ( 45 ? ) + ( 46 ? ) + ( 47 ? ) + ( 48 ? ) ) - ( /4C5F1EDC/4C5F2B55 $noname F? MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000411 ) - ( 2 ? ) + ( /4C5F1EDC/4C5F2025 TSSOP-14 U6 MIC2550AYTS + ( 1 3.3V ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 7 GND ) + ( 8 GND ) + ( 9 ? ) + ( 10 N-000420 ) + ( 11 N-000426 ) + ( 12 3.3V ) + ( 14 3.3V ) ) - ( /4C5F1EDC/4C5F23DD $noname J? USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000412 ) - ( S2 N-000412 ) - ( S3 N-000412 ) - ( S4 N-000412 ) - ( 1 N-000411 ) - ( 2 N-000409 ) - ( 3 N-000410 ) - ( 4 GND ) + ( /4C5F1EDC/4C5F2CA7 $noname$ V1 V0402MHS03 + ( 1 N-000426 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2039 $noname C? 470nF {Lib=C} - ( 1 N-000068 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2037 $noname C? 1uF {Lib=C} - ( 1 N-000068 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2033 $noname C? 1uF {Lib=C} - ( 1 N-000068 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} - ( 1 N-000068 ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 7 GND ) - ( 8 GND ) - ( 9 ? ) - ( 10 N-000409 ) - ( 11 N-000410 ) - ( 12 N-000068 ) - ( 14 N-000068 ) - ) - ( /4C4320F3/4C5D8114 $noname C? C {Lib=C} - ( 1 /Ethernet_Phy/ETH_PLL1.8V ) - ( 2 N-000395 ) - ) - ( /4C4320F3/4C5D810A $noname L? INDUCTOR {Lib=INDUCTOR} - ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 /Ethernet_Phy/ETH_PLL1.8V ) - ) - ( /4C4320F3/4C5D8104 $noname C? C {Lib=C} - ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 N-000395 ) - ) - ( /4C4320F3/4C5D80F3 $noname L? INDUCTOR {Lib=INDUCTOR} - ( 1 N-000394 ) - ( 2 /Ethernet_Phy/ETH_A1.8V ) - ) - ( /4C4320F3/4C5D80F0 $noname C? C {Lib=C} - ( 1 N-000394 ) - ( 2 N-000395 ) - ) - ( /4C4320F3/4C5D80ED $noname C? C {Lib=C} - ( 1 /Ethernet_Phy/ETH_1.8V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FB7 $noname L? FB {Lib=INDUCTOR} - ( 1 N-000068 ) - ( 2 /Ethernet_Phy/ETH_A3.3V ) - ) - ( /4C4320F3/4C5D7FA7 $noname C? 100nF {Lib=C} - ( 1 /Ethernet_Phy/ETH_A3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA5 $noname C? 1uF {Lib=C} - ( 1 /Ethernet_Phy/ETH_A3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA3 $noname C? 100nF {Lib=C} - ( 1 N-000068 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA1 $noname C? 100nF {Lib=C} - ( 1 N-000068 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7F9F $noname C? 1uF {Lib=C} - ( 1 N-000068 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7F39 $noname R? 4.7K {Lib=R} - ( 1 /ETH_MDIO ) - ( 2 N-000068 ) - ) - ( /4C4320F3/4C5D7ECF $noname R? 6.65K {Lib=R} - ( 1 N-000384 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E43 $noname C? 100nF {Lib=C} - ( 1 N-000068 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E41 $noname C? 100nF {Lib=C} - ( 1 N-000068 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7DCB $noname C? 47nF {Lib=C} - ( 1 N-000393 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7DC4 $noname R? 1M {Lib=R} - ( 1 N-000393 ) - ( 2 GND ) - ) - ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /ETH_MDIO ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) - ( 7 N-000068 ) - ( 8 GND ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 GND ) - ( 13 /Ethernet_Phy/ETH_1.8V ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ( 17 ? ) - ( 18 ? ) - ( 19 ? ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 GND ) - ( 24 N-000068 ) - ( 25 /FPGA_Spartan6/ETH_INT ) - ( 26 /Ethernet_Phy/ETH_LED0 ) - ( 27 /Ethernet_Phy/ETH_LED1 ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000385 ) - ( 33 N-000392 ) - ( 34 ? ) - ( 35 GND ) - ( 36 GND ) - ( 37 N-000384 ) - ( 38 /Ethernet_Phy/ETH_A3.3V ) - ( 39 GND ) - ( 40 N-000386 ) - ( 41 N-000391 ) - ( 42 ? ) - ( 43 ? ) - ( 44 GND ) - ( 45 ? ) - ( 46 ? ) - ( 47 /Ethernet_Phy/ETH_PLL1.8V ) - ( 48 ? ) - ) - ( /4C4320F3/4C5D7AFE $noname R? 49.9 {Lib=R} - ( 1 N-000068 ) - ( 2 N-000391 ) - ) - ( /4C4320F3/4C5D7AFC $noname R? 49.9 {Lib=R} - ( 1 N-000068 ) - ( 2 N-000386 ) - ) - ( /4C4320F3/4C5D7AF9 $noname R? 49.9 {Lib=R} - ( 1 N-000068 ) - ( 2 N-000385 ) - ) - ( /4C4320F3/4C5D7AF7 $noname R? 49.9 {Lib=R} - ( 1 N-000068 ) - ( 2 N-000392 ) - ) - ( /4C4320F3/4C5D71DB $noname R? 220 {Lib=R} - ( 1 N-000388 ) - ( 2 /Ethernet_Phy/ETH_LED1 ) - ) - ( /4C4320F3/4C5D719D $noname R? 220 {Lib=R} - ( 1 N-000389 ) - ( 2 /Ethernet_Phy/ETH_LED0 ) - ) - ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000391 ) - ( 2 N-000386 ) - ( 3 N-000068 ) - ( 4 GND ) - ( 5 GND ) - ( 6 N-000068 ) - ( 7 N-000392 ) - ( 8 N-000385 ) - ( 9 N-000068 ) - ( 10 N-000389 ) - ( 11 N-000068 ) - ( 12 N-000388 ) - ( 13 N-000393 ) - ( 14 N-000393 ) - ) - ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} - ( CASE GND ) - ( CD ? ) - ( COM GND ) - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) - ( 7 ? ) - ( 8 ? ) - ) - ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 /Non_volatile_memories/FRB_N ) - ( 7 /Non_volatile_memories/FRB_N ) - ( 8 ? ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 N-000068 ) - ( 13 GND ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ( 17 ? ) - ( 18 ? ) - ( 19 N-000068 ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 ? ) - ( 24 ? ) - ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 ? ) - ( 32 ? ) - ( 33 ? ) - ( 34 ? ) - ( 35 ? ) - ( 36 GND ) - ( 37 N-000068 ) - ( 38 ? ) - ( 39 ? ) - ( 40 ? ) - ( 41 ? ) - ( 42 ? ) - ( 43 ? ) - ( 44 ? ) - ( 45 ? ) - ( 46 ? ) - ( 47 ? ) - ( 48 ? ) - ) - ( /4C421DD3/4C58CA3A 60fbga_ddr U3 MT46V32M16FN {Lib=MT46V32M16FN} - ( A7 N-000048 ) - ( F8 N-000048 ) - ( M7 N-000048 ) - ( A9 N-000048 ) - ( B2 N-000048 ) - ( C8 N-000048 ) - ( D2 N-000048 ) - ( E8 N-000048 ) - ( B7 /DDR_Banks/M1_DQ2 ) - ( C9 /DDR_Banks/M1_DQ3 ) - ( C7 /DDR_Banks/M1_DQ4 ) - ( D9 /DDR_Banks/M1_DQ5 ) - ( D7 /DDR_Banks/M1_DQ6 ) - ( E9 /DDR_Banks/M1_DQ7 ) - ( E1 /DDR_Banks/M1_DQ8 ) - ( D3 /DDR_Banks/M1_DQ9 ) - ( D1 /DDR_Banks/M1_DQ10 ) - ( C3 /DDR_Banks/M1_DQ11 ) - ( C1 /DDR_Banks/M1_DQ12 ) - ( B3 /DDR_Banks/M1_DQ13 ) - ( B1 /DDR_Banks/M1_DQ14 ) - ( A2 /DDR_Banks/M1_DQ15 ) - ( F7 /DDR_Banks/M1_LDM ) - ( E7 /DDR_Banks/M1_LDQS ) - ( F9 ? ) - ( H7 /DDR_Banks/M1_RAS# ) - ( F3 /DDR_Banks/M1_UDM ) - ( E3 /DDR_Banks/M1_UDQS ) - ( F1 ? ) - ( G7 /DDR_Banks/M1_WE# ) - ( B9 /DDR_Banks/M1_DQ1 ) - ( A8 /DDR_Banks/M1_DQ0 ) - ( H8 ? ) - ( G3 /DDR_Banks/M1_CLK# ) - ( G2 /DDR_Banks/M1_CLK ) - ( H3 /DDR_Banks/M1_CKE ) - ( G8 /DDR_Banks/M1_CAS# ) - ( J7 ? ) - ( J8 ? ) - ( H2 /DDR_Banks/M1_A12 ) - ( J2 /DDR_Banks/M1_A11 ) - ( K8 /DDR_Banks/M1_A10 ) - ( J3 /DDR_Banks/M1_A9 ) - ( K2 /DDR_Banks/M1_A8 ) - ( K3 /DDR_Banks/M1_A7 ) - ( L2 /DDR_Banks/M1_A6 ) - ( L3 /DDR_Banks/M1_A5 ) - ( M2 /DDR_Banks/M1_A4 ) - ( M8 /DDR_Banks/M1_A3 ) - ( L7 /DDR_Banks/M1_A2 ) - ( L8 /DDR_Banks/M1_A1 ) - ( K7 /DDR_Banks/M1_A0 ) - ( A3 GND ) - ( F2 GND ) - ( M3 GND ) - ( A1 GND ) - ( B8 GND ) - ( C2 GND ) - ( D8 GND ) - ( E2 GND ) - ) - ( /4C421DD3/4C58C847 60fbga_ddr U2 MT46V32M16FN {Lib=MT46V32M16FN} - ( A7 N-000046 ) - ( F8 N-000046 ) - ( M7 N-000046 ) - ( A9 N-000046 ) - ( B2 N-000046 ) - ( C8 N-000046 ) - ( D2 N-000046 ) - ( E8 N-000046 ) - ( B7 /DDR_Banks/M0_DQ2 ) - ( C9 /DDR_Banks/M0_DQ3 ) - ( C7 /DDR_Banks/M0_DQ4 ) - ( D9 /DDR_Banks/M0_DQ5 ) - ( D7 /DDR_Banks/M0_DQ6 ) - ( E9 /DDR_Banks/M0_DQ7 ) - ( E1 /DDR_Banks/M0_DQ8 ) - ( D3 /DDR_Banks/M0_DQ9 ) - ( D1 /DDR_Banks/M0_DQ10 ) - ( C3 /DDR_Banks/M0_DQ11 ) - ( C1 /DDR_Banks/M0_DQ12 ) - ( B3 /DDR_Banks/M0_DQ13 ) - ( B1 /DDR_Banks/M0_DQ14 ) - ( A2 /DDR_Banks/M0_DQ15 ) - ( F7 /DDR_Banks/M0_LDM ) - ( E7 /DDR_Banks/M0_LDQS ) - ( F9 ? ) - ( H7 /DDR_Banks/M0_RAS# ) - ( F3 /DDR_Banks/M0_UDM ) - ( E3 /DDR_Banks/M0_UDQS ) - ( F1 ? ) - ( G7 /DDR_Banks/M0_WE# ) - ( B9 /DDR_Banks/M0_DQ1 ) - ( A8 /DDR_Banks/M0_DQ0 ) - ( H8 ? ) - ( G3 /DDR_Banks/M0_CLK# ) - ( G2 /DDR_Banks/M0_CLK ) - ( H3 /DDR_Banks/M0_CKE ) - ( G8 /DDR_Banks/M0_CAS# ) - ( J7 ? ) - ( J8 ? ) - ( H2 /DDR_Banks/M0_A12 ) - ( J2 /DDR_Banks/M0_A11 ) - ( K8 /DDR_Banks/M0_A10 ) - ( J3 /DDR_Banks/M0_A9 ) - ( K2 /DDR_Banks/M0_A8 ) - ( K3 /DDR_Banks/M0_A7 ) - ( L2 /DDR_Banks/M0_A6 ) - ( L3 /DDR_Banks/M0_A5 ) - ( M2 /DDR_Banks/M0_A4 ) - ( M8 /DDR_Banks/M0_A3 ) - ( L7 /DDR_Banks/M0_A2 ) - ( L8 /DDR_Banks/M0_A1 ) - ( K7 /DDR_Banks/M0_A0 ) - ( A3 GND ) - ( F2 GND ) - ( M3 GND ) - ( A1 GND ) - ( B8 GND ) - ( C2 GND ) - ( D8 GND ) - ( E2 GND ) + ( /4C5F1EDC/4C5F2CA3 $noname$ V2 V0402MHS03 + ( 1 N-000420 ) + ( 2 GND ) ) ) * { Allowed footprints by component: -$component R? +$component C1 + SM* + C? + C1-1 +$endlist +$component C2 + SM* + C? + C1-1 +$endlist +$component C3 + SM* + C? + C1-1 +$endlist +$component C4 + SM* + C? + C1-1 +$endlist +$component C5 + SM* + C? + C1-1 +$endlist +$component C6 + SM* + C? + C1-1 +$endlist +$component C7 + SM* + C? + C1-1 +$endlist +$component C8 + SM* + C? + C1-1 +$endlist +$component C9 + SM* + C? + C1-1 +$endlist +$component C10 + SM* + C? + C1-1 +$endlist +$component C11 + SM* + C? + C1-1 +$endlist +$component C12 + SM* + C? + C1-1 +$endlist +$component C13 + SM* + C? + C1-1 +$endlist +$component C14 + SM* + C? + C1-1 +$endlist +$component C15 + SM* + C? + C1-1 +$endlist +$component C16 + SM* + C? + C1-1 +$endlist +$component R1 R? SM0603 SM0805 + R?-* $endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component R? +$component R2 R? SM0603 SM0805 + R?-* $endlist -$component R? +$component R3 R? SM0603 SM0805 + R?-* $endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component C? - SM* - C? - C1-1 -$endlist -$component R? +$component R4 R? SM0603 SM0805 + R?-* $endlist -$component R? +$component R5 R? SM0603 SM0805 + R?-* $endlist -$component R? +$component R6 R? SM0603 SM0805 + R?-* $endlist -$component R? +$component R7 R? SM0603 SM0805 + R?-* $endlist -$component R? +$component R8 R? SM0603 SM0805 + R?-* $endlist -$component R? +$component R9 R? SM0603 SM0805 + R?-* $endlist -$component R? +$component R10 R? SM0603 SM0805 + R?-* $endlist $endfootprintlist } -{ Pin List by Nets -Net 9 "/ETH_MDIO" "ETH_MDIO" - R? 1 - U4 1 -Net 13 "/DDR Banks/M1_LDM" "M1_LDM" - U3 F7 - U1 L19 -Net 14 "/DDR Banks/M1_CKE" "M1_CKE" - U3 H3 - U1 D21 -Net 15 "/DDR Banks/M1_CAS#" "M1_CAS#" - U3 G8 - U1 H22 -Net 16 "/DDR Banks/M0_CKE" "M0_CKE" - U2 H3 - U1 D2 -Net 17 "/DDR Banks/M0_WE#" "M0_WE#" - U2 G7 - U1 F2 -Net 18 "/DDR Banks/M0_CAS#" "M0_CAS#" - U2 G8 - U1 K4 -Net 19 "/DDR Banks/M0_UDM" "M0_UDM" - U2 F3 - U1 M3 -Net 20 "/DDR Banks/M0_UDQS" "M0_UDQS" - U2 E3 - U1 T2 -Net 21 "/DDR Banks/M1_CLK#" "M1_CLK#" - U3 G3 - U1 J19 -Net 22 "/DDR Banks/M0_CLK#" "M0_CLK#" - U2 G3 - U1 H3 -Net 23 "/DDR Banks/M0_CLK" "M0_CLK" - U2 G2 - U1 H4 -Net 24 "/DDR Banks/M1_CLK" "M1_CLK" - U3 G2 - U1 H20 -Net 25 "/DDR Banks/M0_LDM" "M0_LDM" - U2 F7 - U1 L4 -Net 26 "/DDR Banks/M0_LDQS" "M0_LDQS" - U2 E7 - U1 L3 -Net 27 "/DDR Banks/M0_RAS#" "M0_RAS#" - U2 H7 - U1 K5 -Net 29 "/DDR Banks/M1_RAS#" "M1_RAS#" - U3 H7 - U1 H21 -Net 30 "/DDR Banks/M1_WE#" "M1_WE#" - U3 G7 - U1 H19 -Net 31 "/DDR Banks/M1_UDM" "M1_UDM" - U3 F3 - U1 M20 -Net 32 "/DDR Banks/M1_LDQS" "M1_LDQS" - U3 E7 - U1 L20 -Net 33 "/DDR Banks/M1_UDQS" "M1_UDQS" - U3 E3 - U1 T21 -Net 34 "/FPGA Spartan6/ETH_INT" "ETH_INT" - U1 A5 - U4 25 -Net 45 "GND" "GND" - U3 A3 - U3 F2 - U3 M3 - U3 A1 - U3 B8 - U3 C2 - U3 D8 - U3 E2 - U2 A3 - U2 F2 - U2 M3 - U2 A1 - U2 B8 - U2 C2 - U2 D8 - U2 E2 - J1 CASE - J1 CASE - J1 CASE - J1 COM - U5 36 - U5 13 - U1 P10 - U1 V10 - U1 M10 - U1 K10 - U1 L13 - U1 A1 - U1 N13 - U1 A22 - U1 R5 - U1 AA13 - U1 W19 - U1 AA17 - U1 K14 - U1 AA5 - U1 L5 - U1 AA9 - U1 M14 - U1 AB1 - U1 N2 - U1 AB22 - U1 P14 - U1 B13 - U1 U21 - U1 B17 - U1 V4 - U1 B5 - U1 J9 - U1 B9 - U1 K12 - U1 D18 - U1 L11 - U1 D4 - U1 L18 - U1 E11 - U1 L9 - U1 E15 - U1 M12 - U1 E2 - U1 N11 - U1 E21 - U1 N17 - U1 E7 - U1 N21 - U1 G18 - U1 P12 - U1 G5 - U1 R18 - U1 H7 - U1 U2 - U1 J11 - U1 U7 - U1 J13 - U1 V14 - U1 J15 - U1 W16 - U1 J2 - U1 W7 - U1 J21 - U1 N9 - C? 2 - C? 2 - C? 2 - C? 2 - C? 2 - C? 2 - R? 2 - C? 2 - C? 2 - C? 2 - R? 2 - U4 8 - U4 12 - U4 23 - U4 35 - U4 36 - U4 39 - U4 44 - J4 5 - J4 4 - R? 2 - C? 2 - V? 2 - V? 2 - J? 4 - C? 2 - C? 2 - C? 2 - U6 8 - U6 7 -Net 46 "" "" - U2 A7 - U2 F8 - U2 M7 - U2 A9 - U2 B2 - U2 C8 - U2 D2 - U2 E8 -Net 48 "" "" - U3 A7 - U3 F8 - U3 M7 - U3 A9 - U3 B2 - U3 C8 - U3 D2 - U3 E8 -Net 68 "" "" - U5 37 - U5 19 - U5 12 - L? 1 - C? 1 - C? 1 - C? 1 - R? 2 - C? 1 - C? 1 - U4 7 - U4 24 - R? 1 - R? 1 - R? 1 - R? 1 - J4 11 - J4 9 - J4 6 - J4 3 - C? 1 - C? 1 - C? 1 - U6 14 - U6 12 - U6 1 -Net 71 "/Non volatile memories/FRB_N" "FRB_N" - U5 7 - U5 6 -Net 118 "" "" - U1 N10 - U1 P11 - U1 P13 - U1 P9 - U1 R14 - U1 N12 - U1 J10 - U1 J12 - U1 J14 - U1 J8 - U1 K11 - U1 K13 - U1 K9 - U1 L10 - U1 L12 - U1 L14 - U1 M11 - U1 M13 - U1 M9 - U1 N14 -Net 119 "" "" - U1 H9 - U1 U11 - U1 F11 - U1 R6 - U1 M15 - U1 V6 - U1 G12 - U1 H15 - U1 D16 - U1 K15 - U1 R12 - U1 N8 - U1 R10 - U1 L8 -Net 120 "" "" - U1 W2 - U1 L2 - U1 L7 - U1 C2 - U1 N5 - U1 R2 - U1 U5 - U1 G2 - U1 F4 - U1 F6 - U1 J5 -Net 121 "" "" - U1 W21 - U1 C21 - U1 G21 - U1 J18 - U1 L16 - U1 L21 - U1 N18 - U1 R21 - U1 U18 - U1 E19 -Net 122 "" "" - U1 B4 - U1 B7 - U1 E13 - U1 E17 - U1 G10 - U1 G14 - U1 B11 - U1 B15 - U1 B19 - U1 E9 -Net 123 "" "" - U1 AA15 - U1 V16 - U1 T13 - U1 V8 - U1 V12 - U1 AA3 - U1 T9 - U1 AA19 - U1 AA11 - U1 W5 - U1 AA7 -Net 382 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - L? 1 - C? 1 - L? 2 - U4 31 -Net 383 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - L? 2 - C? 1 - C? 1 - U4 38 -Net 384 "" "" - R? 1 - U4 37 -Net 385 "" "" - U4 32 - R? 2 - J4 8 -Net 386 "" "" - U4 40 - R? 2 - J4 2 -Net 387 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - U4 27 - R? 2 -Net 388 "" "" - R? 1 - J4 12 -Net 389 "" "" - R? 1 - J4 10 -Net 390 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - U4 26 - R? 2 -Net 391 "" "" - U4 41 - R? 2 - J4 1 -Net 392 "" "" - U4 33 - R? 2 - J4 7 -Net 393 "" "" - C? 1 - R? 1 - J4 13 - J4 14 -Net 394 "" "" - L? 1 - C? 1 -Net 395 "" "" - C? 2 - C? 2 - C? 2 -Net 396 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" - C? 1 - U4 13 -Net 397 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - C? 1 - L? 2 - U4 47 -Net 409 "" "" - V? 1 - V? 1 - J? 2 - U6 10 -Net 410 "" "" - V? 1 - V? 1 - J? 3 - U6 11 -Net 411 "" "" - F? 1 - J? 1 -Net 412 "" "" - R? 1 - C? 1 - J? S1 - J? S2 - J? S3 - J? S4 -Net 423 "/DDR Banks/M0_A0" "M0_A0" - U2 K7 - U1 H2 -Net 424 "/DDR Banks/M0_A1" "M0_A1" - U2 L8 - U1 H1 -Net 425 "/DDR Banks/M0_A2" "M0_A2" - U2 L7 - U1 H5 -Net 426 "/DDR Banks/M0_A3" "M0_A3" - U2 M8 - U1 K6 -Net 427 "/DDR Banks/M0_A4" "M0_A4" - U2 M2 - U1 F3 -Net 428 "/DDR Banks/M0_A5" "M0_A5" - U2 L3 - U1 K3 -Net 429 "/DDR Banks/M0_A6" "M0_A6" - U2 L2 - U1 J4 -Net 430 "/DDR Banks/M0_A7" "M0_A7" - U2 K3 - U1 H6 -Net 431 "/DDR Banks/M0_A8" "M0_A8" - U2 K2 - U1 E3 -Net 432 "/DDR Banks/M0_A9" "M0_A9" - U2 J3 - U1 E1 -Net 433 "/DDR Banks/M0_A10" "M0_A10" - U2 K8 - U1 G4 -Net 434 "/DDR Banks/M0_A11" "M0_A11" - U2 J2 - U1 C1 -Net 435 "/DDR Banks/M0_A12" "M0_A12" - U2 H2 - U1 D1 -Net 436 "/DDR Banks/M1_A0" "M1_A0" - U3 K7 - U1 F21 -Net 437 "/DDR Banks/M1_A1" "M1_A1" - U3 L8 - U1 F22 -Net 438 "/DDR Banks/M1_A2" "M1_A2" - U3 L7 - U1 E22 -Net 439 "/DDR Banks/M1_A3" "M1_A3" - U3 M8 - U1 G20 -Net 440 "/DDR Banks/M1_A4" "M1_A4" - U3 M2 - U1 F20 -Net 441 "/DDR Banks/M1_A5" "M1_A5" - U3 L3 - U1 K20 -Net 442 "/DDR Banks/M1_A6" "M1_A6" - U3 L2 - U1 K19 -Net 443 "/DDR Banks/M1_A7" "M1_A7" - U3 K3 - U1 E20 -Net 444 "/DDR Banks/M1_A8" "M1_A8" - U3 K2 - U1 C20 -Net 445 "/DDR Banks/M1_A9" "M1_A9" - U3 J3 - U1 C22 -Net 446 "/DDR Banks/M1_A10" "M1_A10" - U3 K8 - U1 G19 -Net 447 "/DDR Banks/M1_A11" "M1_A11" - U3 J2 - U1 F19 -Net 448 "/DDR Banks/M1_A12" "M1_A12" - U3 H2 - U1 D22 -Net 449 "/DDR Banks/M0_DQ0" "M0_DQ0" - U2 A8 - U1 N3 -Net 450 "/DDR Banks/M0_DQ1" "M0_DQ1" - U2 B9 - U1 N1 -Net 451 "/DDR Banks/M0_DQ2" "M0_DQ2" - U2 B7 - U1 M2 -Net 452 "/DDR Banks/M0_DQ3" "M0_DQ3" - U2 C9 - U1 M1 -Net 453 "/DDR Banks/M0_DQ4" "M0_DQ4" - U2 C7 - U1 J3 -Net 454 "/DDR Banks/M0_DQ5" "M0_DQ5" - U2 D9 - U1 J1 -Net 455 "/DDR Banks/M0_DQ6" "M0_DQ6" - U2 D7 - U1 K2 -Net 456 "/DDR Banks/M0_DQ7" "M0_DQ7" - U2 E9 - U1 K1 -Net 457 "/DDR Banks/M0_DQ8" "M0_DQ8" - U2 E1 - U1 P2 -Net 458 "/DDR Banks/M0_DQ9" "M0_DQ9" - U2 D3 - U1 P1 -Net 459 "/DDR Banks/M0_DQ10" "M0_DQ10" - U2 D1 - U1 R3 -Net 460 "/DDR Banks/M0_DQ11" "M0_DQ11" - U2 C3 - U1 R1 -Net 461 "/DDR Banks/M0_DQ12" "M0_DQ12" - U2 C1 - U1 U3 -Net 462 "/DDR Banks/M0_DQ13" "M0_DQ13" - U2 B3 - U1 U1 -Net 463 "/DDR Banks/M0_DQ14" "M0_DQ14" - U2 B1 - U1 V2 -Net 464 "/DDR Banks/M0_DQ15" "M0_DQ15" - U2 A2 - U1 V1 -Net 465 "/DDR Banks/M1_DQ0" "M1_DQ0" - U3 A8 - U1 N20 -Net 466 "/DDR Banks/M1_DQ1" "M1_DQ1" - U3 B9 - U1 N22 -Net 467 "/DDR Banks/M1_DQ2" "M1_DQ2" - U3 B7 - U1 M21 -Net 468 "/DDR Banks/M1_DQ3" "M1_DQ3" - U3 C9 - U1 M22 -Net 469 "/DDR Banks/M1_DQ4" "M1_DQ4" - U3 C7 - U1 J20 -Net 470 "/DDR Banks/M1_DQ5" "M1_DQ5" - U3 D9 - U1 J22 -Net 471 "/DDR Banks/M1_DQ6" "M1_DQ6" - U3 D7 - U1 K21 -Net 472 "/DDR Banks/M1_DQ7" "M1_DQ7" - U3 E9 - U1 K22 -Net 473 "/DDR Banks/M1_DQ8" "M1_DQ8" - U3 E1 - U1 P21 -Net 474 "/DDR Banks/M1_DQ9" "M1_DQ9" - U3 D3 - U1 P22 -Net 475 "/DDR Banks/M1_DQ10" "M1_DQ10" - U3 D1 - U1 R20 -Net 476 "/DDR Banks/M1_DQ11" "M1_DQ11" - U3 C3 - U1 R22 -Net 477 "/DDR Banks/M1_DQ12" "M1_DQ12" - U3 C1 - U1 U20 -Net 478 "/DDR Banks/M1_DQ13" "M1_DQ13" - U3 B3 - U1 U22 -Net 479 "/DDR Banks/M1_DQ14" "M1_DQ14" - U3 B1 - U1 V21 -Net 480 "/DDR Banks/M1_DQ15" "M1_DQ15" - U3 A2 - U1 V22 -} -#End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 408784f..e834e20 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,73 +1,8 @@ -update=Mon 09 Aug 2010 07:12:06 PM COT +update=Mon 09 Aug 2010 09:19:33 PM COT version=1 -last_client=kicad +last_client=pcbnew [common] NetDir= -[cvpcb] -version=1 -NetIExt=net -[cvpcb/libraries] -EquName1=devcms -[pcbnew] -version=1 -PadDrlX=320 -PadDimH=600 -PadDimV=600 -ViaDiam=350 -ViaDril=250 -ViaAltD=250 -MViaDia=200 -MViaDrl=50 -Isol=100 -Countlayer=4 -Lpiste=80 -RouteTo=15 -RouteBo=0 -TypeVia=3 -Segm45=1 -Racc45=1 -SgPcb45=1 -TxtPcbV=800 -TxtPcbH=600 -TxtModV=600 -TxtModH=600 -TxtModW=120 -HPGLnum=1 -HPGdiam=15 -HPGLSpd=20 -HPGLrec=2 -HPGLorg=0 -VEgarde=100 -DrawLar=150 -EdgeLar=150 -TxtLar=120 -MSegLar=150 -WpenSer=10 -[pcbnew/libraries] -LibDir= -LibName1=../modules/stdpass -LibName2=../modules/SD-48025 -LibName3=../modules/USB-48204 -LibName4=../modules/TSSOP-14 -LibName5=../modules/SMB-0402 -LibName6=../modules/SD-48025 -LibName7=../modules/MICROSD-500901 -LibName8=sockets -LibName9=connect -LibName10=discret -LibName11=pin_array -LibName12=divers -LibName13=libcms -LibName14=display -LibName15=valves -LibName16=led -LibName17=dip_sockets -LibName18=../modules/90vfbga_mobile_ddr -LibName19=../modules/FGG484bga-p10 -LibName20=../modules/LQFP48 -LibName21=../modules/48TSOP-NAND -LibName22=../modules/micro-sd -LibName23=../modules/60fbga_ddr [eeschema] version=1 LibDir= @@ -147,3 +82,52 @@ LibName41=valves version=1 RootSch= BoardNm= +[cvpcb] +version=1 +NetIExt=net +[cvpcb/libraries] +EquName1=devcms +[pcbnew] +version=1 +PadDrlX=320 +PadDimH=600 +PadDimV=600 +BoardThickness=630 +SgPcb45=1 +TxtPcbV=800 +TxtPcbH=600 +TxtModV=600 +TxtModH=600 +TxtModW=120 +VEgarde=100 +DrawLar=150 +EdgeLar=150 +TxtLar=120 +MSegLar=150 +LastNetListRead=xue-rnc.net +[pcbnew/libraries] +LibDir= +LibName1=../modules/stdpass +LibName2=../modules/SD-48025 +LibName3=../modules/USB-48204 +LibName4=../modules/TSSOP-14 +LibName5=../modules/SMB-0402 +LibName6=../modules/SD-48025 +LibName7=../modules/MICROSD-500901 +LibName8=sockets +LibName9=connect +LibName10=discret +LibName11=pin_array +LibName12=divers +LibName13=libcms +LibName14=display +LibName15=valves +LibName16=led +LibName17=dip_sockets +LibName18=../modules/90vfbga_mobile_ddr +LibName19=../modules/FGG484bga-p10 +LibName20=../modules/LQFP48 +LibName21=../modules/48TSOP-NAND +LibName22=../modules/micro-sd +LibName23=../modules/60fbga_ddr +LibName24=/home/afc/devel/Qi/xue/kicad/modules/66-tsop diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 5b0d937..c17edd5 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 08:20:32 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:20:06 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001