From 11bf380cc6e5c967b7e028d53cd7ec01aa9104c2 Mon Sep 17 00:00:00 2001 From: Juan64Bits Date: Tue, 10 Aug 2010 21:25:32 -0500 Subject: [PATCH] Fixing USB connections --- kicad/xue-rnc/DRAM.sch | 102 +- kicad/xue-rnc/FPGA.sch | 188 +-- kicad/xue-rnc/NV_MEMORIES.sch | 58 +- kicad/xue-rnc/USB.sch | 48 +- kicad/xue-rnc/eth_phy.sch | 62 +- kicad/xue-rnc/xue-rnc.brd | 1829 ++++++++++------------ kicad/xue-rnc/xue-rnc.cache.dcm | 2 +- kicad/xue-rnc/xue-rnc.cache.lib | 193 ++- kicad/xue-rnc/xue-rnc.net | 2610 ++++++++++++++++--------------- kicad/xue-rnc/xue-rnc.sch | 87 +- 10 files changed, 2425 insertions(+), 2754 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 50323fa..f121f31 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,47 +1,5 @@ -EESchema Schematic File Version 2 date Tue 10 Aug 2010 06:50:48 PM COT -LIBS:power -LIBS:v0402mhs03 -LIBS:usb-48204-0001 -LIBS:microsmd075f -LIBS:mic2550ayts -LIBS:rj45-48025 -LIBS:xue-nv -LIBS:xc6slx75fgg484 -LIBS:xc6slx45fgg484 -LIBS:micron_mobile_ddr -LIBS:micron_ddr_512Mb -LIBS:k8001 -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:pasives-connectors -LIBS:xue-rnc-cache +EESchema Schematic File Version 2 date Tue 10 Aug 2010 09:23:11 PM COT +LIBS:power,../library/v0402mhs03,../library/usb-48204-0001,../library/microsmd075f,../library/mic2550ayts,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,../library/pasives-connectors,./xue-rnc.cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 @@ -500,37 +458,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR06 +L GND #PWR012 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR06" H 6900 6200 30 0001 C CNN +F 0 "#PWR012" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR07 +L +2.5V #PWR013 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR07" H 6900 5750 20 0001 C CNN +F 0 "#PWR013" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR08 +L +2.5V #PWR014 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR08" H 1700 5750 20 0001 C CNN +F 0 "#PWR014" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR09 +L GND #PWR015 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR09" H 1700 6200 30 0001 C CNN +F 0 "#PWR015" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -546,19 +504,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR010 +L +2.5V #PWR016 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR010" H 3050 1700 20 0001 C CNN +F 0 "#PWR016" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR011 +L +2.5V #PWR017 U 1 1 4C61CFC6 P 8300 1750 -F 0 "#PWR011" H 8300 1700 20 0001 C CNN +F 0 "#PWR017" H 8300 1700 20 0001 C CNN F 1 "+2.5V" H 8300 1850 30 0000 C CNN 1 8300 1750 1 0 0 -1 @@ -624,37 +582,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR012 +L +2.5V #PWR018 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR012" H 8300 5700 20 0001 C CNN +F 0 "#PWR018" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR013 +L GND #PWR019 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR013" H 8300 6350 30 0001 C CNN +F 0 "#PWR019" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR014 +L GND #PWR020 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR014" H 3050 6350 30 0001 C CNN +F 0 "#PWR020" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR015 +L +2.5V #PWR021 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR015" H 3050 5700 20 0001 C CNN +F 0 "#PWR021" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -740,19 +698,19 @@ F 2 "0402" H 9850 1850 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR016 +L +2.5V #PWR022 U 1 1 4C61CE2F P 9850 1000 -F 0 "#PWR016" H 9850 950 20 0001 C CNN +F 0 "#PWR022" H 9850 950 20 0001 C CNN F 1 "+2.5V" H 9850 1100 30 0000 C CNN 1 9850 1000 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR017 +L +2.5V #PWR023 U 1 1 4C61CDF1 P 4550 900 -F 0 "#PWR017" H 4550 850 20 0001 C CNN +F 0 "#PWR023" H 4550 850 20 0001 C CNN F 1 "+2.5V" H 4550 1000 30 0000 C CNN 1 4550 900 1 0 0 -1 @@ -844,10 +802,10 @@ $EndComp Text HLabel 4950 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR018 +L GND #PWR024 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR018" H 3000 5200 30 0001 C CNN +F 0 "#PWR024" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1141,10 +1099,10 @@ Entry Wire Line Entry Wire Line 9950 3650 10050 3750 $Comp -L GND #PWR019 +L GND #PWR025 U 1 1 4C437C3F P 8250 5200 -F 0 "#PWR019" H 8250 5200 30 0001 C CNN +F 0 "#PWR025" H 8250 5200 30 0001 C CNN F 1 "GND" H 8250 5130 30 0001 C CNN 1 8250 5200 1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index ce315e7..35c7898 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,51 +1,9 @@ -EESchema Schematic File Version 2 date Tue 10 Aug 2010 06:50:48 PM COT -LIBS:power -LIBS:v0402mhs03 -LIBS:usb-48204-0001 -LIBS:microsmd075f -LIBS:mic2550ayts -LIBS:rj45-48025 -LIBS:xue-nv -LIBS:xc6slx75fgg484 -LIBS:xc6slx45fgg484 -LIBS:micron_mobile_ddr -LIBS:micron_ddr_512Mb -LIBS:k8001 -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:pasives-connectors -LIBS:xue-rnc-cache +EESchema Schematic File Version 2 date Tue 10 Aug 2010 09:23:11 PM COT +LIBS:power,../library/v0402mhs03,../library/usb-48204-0001,../library/microsmd075f,../library/mic2550ayts,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,../library/pasives-connectors,./xue-rnc.cache EELAYER 24 0 EELAYER END $Descr A2 23400 16535 -Sheet 2 6 +Sheet 3 6 Title "" Date "10 aug 2010" Rev "" @@ -55,6 +13,8 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Wire Line + 14200 10750 14150 10750 Connection ~ 15850 8300 Wire Wire Line 15850 8200 15850 8300 @@ -81,23 +41,23 @@ Wire Wire Line Wire Wire Line 1450 5700 1600 5700 Wire Wire Line - 14150 10650 14200 10650 -Wire Wire Line - 14200 10450 12900 10450 + 14150 10450 14200 10450 Wire Wire Line 14200 10250 12900 10250 Wire Wire Line - 14150 10050 14200 10050 + 14200 10050 12900 10050 Wire Wire Line 14150 9850 14200 9850 Wire Wire Line - 14200 9650 12900 9650 + 14150 9650 14200 9650 Wire Wire Line 14200 9450 12900 9450 Wire Wire Line - 14150 9250 14200 9250 + 14200 9250 12900 9250 Wire Wire Line 14150 9050 14200 9050 +Wire Wire Line + 14150 8850 14200 8850 Wire Wire Line 17600 9150 17700 9150 Wire Wire Line @@ -105,11 +65,11 @@ Wire Wire Line Wire Wire Line 17700 8750 17600 8750 Wire Bus Line - 12800 10400 12800 10000 + 12800 10200 12800 9800 Wire Bus Line - 12800 10000 12700 10000 + 12800 9800 12700 9800 Wire Bus Line - 12700 9200 12800 9200 + 12700 9000 12800 9000 Wire Wire Line 18300 4350 18750 4350 Wire Wire Line @@ -802,31 +762,31 @@ Wire Wire Line Wire Wire Line 18300 3950 18750 3950 Wire Bus Line - 12800 9200 12800 9600 + 12800 9000 12800 9400 Wire Wire Line 17600 8850 17700 8850 Wire Wire Line 17600 9050 17700 9050 +Wire Wire Line + 14150 8750 14200 8750 Wire Wire Line 14150 8950 14200 8950 Wire Wire Line - 14150 9150 14200 9150 + 14200 9150 12900 9150 Wire Wire Line 14200 9350 12900 9350 Wire Wire Line - 14200 9550 12900 9550 + 14150 9550 14200 9550 Wire Wire Line 14150 9750 14200 9750 Wire Wire Line - 14150 9950 14200 9950 + 14200 9950 12900 9950 Wire Wire Line 14200 10150 12900 10150 Wire Wire Line - 14200 10350 12900 10350 + 14150 10350 14200 10350 Wire Wire Line 14150 10550 14200 10550 -Wire Wire Line - 14150 10750 14200 10750 Wire Wire Line 1600 5700 1600 5950 Wire Bus Line @@ -845,47 +805,53 @@ Wire Bus Line 18300 9350 18300 9650 Wire Wire Line 12550 12900 12550 13050 +Wire Wire Line + 14200 10650 14150 10650 +Text HLabel 14150 10750 0 60 BiDi ~ 0 +ETH_COL +Text HLabel 14150 10650 0 60 BiDi ~ 0 +ETH_CRS $Comp -L +3.3V #PWR? +L +3.3V #PWR01 U 1 1 4C61E5B3 P 15850 8200 -F 0 "#PWR?" H 15850 8160 30 0001 C CNN +F 0 "#PWR01" H 15850 8160 30 0001 C CNN F 1 "+3.3V" H 15850 8310 30 0000 C CNN 1 15850 8200 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR? +L +1.2V #PWR02 U 1 1 4C61E58C P 14050 12900 -F 0 "#PWR?" H 14050 13040 20 0001 C CNN +F 0 "#PWR02" H 14050 13040 20 0001 C CNN F 1 "+1.2V" H 14050 13010 30 0000 C CNN 1 14050 12900 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR? +L +2.5V #PWR03 U 1 1 4C61E577 P 12550 12900 -F 0 "#PWR?" H 12550 12850 20 0001 C CNN +F 0 "#PWR03" H 12550 12850 20 0001 C CNN F 1 "+2.5V" H 12550 13000 30 0000 C CNN 1 12550 12900 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR? +L +2.5V #PWR04 U 1 1 4C61E523 P 16000 600 -F 0 "#PWR?" H 16000 550 20 0001 C CNN +F 0 "#PWR04" H 16000 550 20 0001 C CNN F 1 "+2.5V" H 16000 700 30 0000 C CNN 1 16000 600 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR? +L +2.5V #PWR05 U 1 1 4C61E51F P 5300 650 -F 0 "#PWR?" H 5300 600 20 0001 C CNN +F 0 "#PWR05" H 5300 600 20 0001 C CNN F 1 "+2.5V" H 5300 750 30 0000 C CNN 1 5300 650 1 0 0 -1 @@ -931,19 +897,19 @@ M0_BA[0..1] Text HLabel 12400 4850 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR01 +L GND #PWR06 U 1 1 4C60C24F P 12550 5100 -F 0 "#PWR01" H 12550 5100 30 0001 C CNN +F 0 "#PWR06" H 12550 5100 30 0001 C CNN F 1 "GND" H 12550 5030 30 0001 C CNN 1 12550 5100 -1 0 0 -1 $EndComp $Comp -L GND #PWR02 +L GND #PWR07 U 1 1 4C60C21D P 1600 5950 -F 0 "#PWR02" H 1600 5950 30 0001 C CNN +F 0 "#PWR07" H 1600 5950 30 0001 C CNN F 1 "GND" H 1600 5880 30 0001 C CNN 1 1600 5950 -1 0 0 -1 @@ -958,61 +924,61 @@ Text HLabel 17700 8850 2 60 BiDi ~ 0 USBA_OE_N Text HLabel 17700 8750 2 60 BiDi ~ 0 USBA_SPD -Text HLabel 14150 10750 0 60 BiDi ~ 0 -ETH_CLK -Text HLabel 14150 10650 0 60 BiDi ~ 0 -ETH_RXC Text HLabel 14150 10550 0 60 BiDi ~ 0 +ETH_CLK +Text HLabel 14150 10450 0 60 BiDi ~ 0 +ETH_RXC +Text HLabel 14150 10350 0 60 BiDi ~ 0 ETH_TXC -Text Label 13300 10450 2 40 ~ 0 -ETH_TXD3 -Text Label 13300 10350 2 40 ~ 0 -ETH_TXD2 Text Label 13300 10250 2 40 ~ 0 -ETH_TXD1 +ETH_TXD3 Text Label 13300 10150 2 40 ~ 0 +ETH_TXD2 +Text Label 13300 10050 2 40 ~ 0 +ETH_TXD1 +Text Label 13300 9950 2 40 ~ 0 ETH_TXD0 -Text HLabel 12700 10000 0 60 Output ~ 0 +Text HLabel 12700 9800 0 60 Output ~ 0 ETH_TXD[0..3] -Entry Wire Line - 12800 10350 12900 10450 -Entry Wire Line - 12800 10250 12900 10350 Entry Wire Line 12800 10150 12900 10250 Entry Wire Line 12800 10050 12900 10150 -Text HLabel 14150 10050 0 60 BiDi ~ 0 -ETH_TXEN -Text HLabel 14150 9950 0 60 BiDi ~ 0 -ETH_TXER +Entry Wire Line + 12800 9950 12900 10050 +Entry Wire Line + 12800 9850 12900 9950 Text HLabel 14150 9850 0 60 BiDi ~ 0 -ETH_RXER +ETH_TXEN Text HLabel 14150 9750 0 60 BiDi ~ 0 +ETH_TXER +Text HLabel 14150 9650 0 60 BiDi ~ 0 +ETH_RXER +Text HLabel 14150 9550 0 60 BiDi ~ 0 ETH_RXDV -Text Label 13300 9650 2 40 ~ 0 -ETH_RXD0 -Text Label 13300 9550 2 40 ~ 0 -ETH_RXD1 Text Label 13300 9450 2 40 ~ 0 -ETH_RXD2 +ETH_RXD0 Text Label 13300 9350 2 40 ~ 0 +ETH_RXD1 +Text Label 13300 9250 2 40 ~ 0 +ETH_RXD2 +Text Label 13300 9150 2 40 ~ 0 ETH_RXD3 -Entry Wire Line - 12800 9550 12900 9650 -Entry Wire Line - 12800 9450 12900 9550 Entry Wire Line 12800 9350 12900 9450 Entry Wire Line 12800 9250 12900 9350 -Text HLabel 12700 9200 0 60 Input ~ 0 +Entry Wire Line + 12800 9150 12900 9250 +Entry Wire Line + 12800 9050 12900 9150 +Text HLabel 12700 9000 0 60 Input ~ 0 ETH_RXD[0..3] -Text HLabel 14150 9250 0 60 BiDi ~ 0 -ETH_RESET_N -Text HLabel 14150 9150 0 60 BiDi ~ 0 -ETH_MDIO Text HLabel 14150 9050 0 60 BiDi ~ 0 +ETH_RESET_N +Text HLabel 14150 8950 0 60 BiDi ~ 0 +ETH_MDIO +Text HLabel 14150 8850 0 60 BiDi ~ 0 ETH_MDC Text Label 18400 4250 0 60 ~ 0 M1_DQ0 @@ -1408,7 +1374,7 @@ Text Label 13500 4050 0 60 ~ 0 M1_A0 Text HLabel 11300 900 0 60 Output ~ 0 M1_A[0..12] -Text HLabel 14150 8950 0 60 BiDi ~ 0 +Text HLabel 14150 8750 0 60 BiDi ~ 0 ETH_INT Text HLabel 13550 4250 0 60 Output ~ 0 M1_CLK @@ -1419,10 +1385,10 @@ M0_CLK Text HLabel 7750 4700 2 60 Output ~ 0 M0_CLK# $Comp -L GND #PWR03 +L GND #PWR08 U 1 1 4C439B7E P 13950 15700 -F 0 "#PWR03" H 13950 15700 30 0001 C CNN +F 0 "#PWR08" H 13950 15700 30 0001 C CNN F 1 "GND" H 13950 15630 30 0001 C CNN 1 13950 15700 -1 0 0 -1 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 702d183..ef09c04 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,47 +1,5 @@ -EESchema Schematic File Version 2 date Tue 10 Aug 2010 06:50:48 PM COT -LIBS:power -LIBS:v0402mhs03 -LIBS:usb-48204-0001 -LIBS:microsmd075f -LIBS:mic2550ayts -LIBS:rj45-48025 -LIBS:xue-nv -LIBS:xc6slx75fgg484 -LIBS:xc6slx45fgg484 -LIBS:micron_mobile_ddr -LIBS:micron_ddr_512Mb -LIBS:k8001 -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:pasives-connectors -LIBS:xue-rnc-cache +EESchema Schematic File Version 2 date Tue 10 Aug 2010 09:23:11 PM COT +LIBS:power,../library/v0402mhs03,../library/usb-48204-0001,../library/microsmd075f,../library/mic2550ayts,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,../library/pasives-connectors,./xue-rnc.cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 @@ -231,10 +189,10 @@ SD_DAT3 Text Label 2800 5850 0 30 ~ 0 SD_CMD $Comp -L GND #PWR? +L GND #PWR09 U 1 1 4C61D875 P 3050 6150 -F 0 "#PWR?" H 3050 6150 30 0001 C CNN +F 0 "#PWR09" H 3050 6150 30 0001 C CNN F 1 "GND" H 3050 6080 30 0001 C CNN 1 3050 6150 1 0 0 -1 @@ -246,19 +204,19 @@ SD_DAT0 Text Label 2800 5600 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR04 +L GND #PWR010 U 1 1 4C438ADC P 4400 5950 -F 0 "#PWR04" H 4400 5950 30 0001 C CNN +F 0 "#PWR010" H 4400 5950 30 0001 C CNN F 1 "GND" H 4400 5880 30 0001 C CNN 1 4400 5950 1 0 0 -1 $EndComp $Comp -L GND #PWR05 +L GND #PWR011 U 1 1 4C438AD5 P 3950 6300 -F 0 "#PWR05" H 3950 6300 30 0001 C CNN +F 0 "#PWR011" H 3950 6300 30 0001 C CNN F 1 "GND" H 3950 6230 30 0001 C CNN 1 3950 6300 1 0 0 -1 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 62f2d71..bb35997 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,51 +1,9 @@ -EESchema Schematic File Version 2 date Tue 10 Aug 2010 06:50:48 PM COT -LIBS:power -LIBS:v0402mhs03 -LIBS:usb-48204-0001 -LIBS:microsmd075f -LIBS:mic2550ayts -LIBS:rj45-48025 -LIBS:xue-nv -LIBS:xc6slx75fgg484 -LIBS:xc6slx45fgg484 -LIBS:micron_mobile_ddr -LIBS:micron_ddr_512Mb -LIBS:k8001 -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:pasives-connectors -LIBS:xue-rnc-cache +EESchema Schematic File Version 2 date Tue 10 Aug 2010 09:23:11 PM COT +LIBS:power,../library/v0402mhs03,../library/usb-48204-0001,../library/microsmd075f,../library/mic2550ayts,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,../library/pasives-connectors,./xue-rnc.cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 3 6 +Sheet 2 6 Title "" Date "10 aug 2010" Rev "" diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index e0516a2..b196aa8 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,47 +1,5 @@ -EESchema Schematic File Version 2 date Tue 10 Aug 2010 06:50:48 PM COT -LIBS:power -LIBS:v0402mhs03 -LIBS:usb-48204-0001 -LIBS:microsmd075f -LIBS:mic2550ayts -LIBS:rj45-48025 -LIBS:xue-nv -LIBS:xc6slx75fgg484 -LIBS:xc6slx45fgg484 -LIBS:micron_mobile_ddr -LIBS:micron_ddr_512Mb -LIBS:k8001 -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:pasives-connectors -LIBS:xue-rnc-cache +EESchema Schematic File Version 2 date Tue 10 Aug 2010 09:23:11 PM COT +LIBS:power,../library/v0402mhs03,../library/usb-48204-0001,../library/microsmd075f,../library/mic2550ayts,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,../library/pasives-connectors,./xue-rnc.cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 @@ -55,8 +13,10 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Text Notes 8000 7300 0 60 ~ 0 -Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com +Wire Wire Line + 3700 4550 3800 4550 +Wire Wire Line + 3800 4350 3700 4350 Wire Wire Line 5700 4550 5600 4550 Wire Wire Line @@ -172,8 +132,6 @@ Wire Wire Line 9400 4650 5600 4650 Wire Wire Line 3800 5750 3700 5750 -Wire Wire Line - 3700 4350 3800 4350 Wire Bus Line 6650 6450 6500 6450 Wire Wire Line @@ -225,10 +183,6 @@ Wire Bus Line 6500 6450 6500 6150 Wire Wire Line 3800 5050 3750 5050 -Wire Wire Line - 3800 4550 3700 4550 -Wire Wire Line - 3700 4450 3800 4450 Wire Wire Line 3700 5650 3800 5650 Wire Wire Line @@ -351,6 +305,10 @@ Wire Wire Line 4400 3950 4400 3400 Wire Wire Line 4700 3950 4700 3400 +Wire Wire Line + 3700 4450 3800 4450 +Text Notes 8000 7300 0 60 ~ 0 +Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com NoConn ~ 5600 4450 NoConn ~ 5600 5550 Text Label 4700 3400 3 40 ~ 0 diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index cc2f92b..ebf478b 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,26 +1,22 @@ -PCBNEW-BOARD Version 1 date Tue 10 Aug 2010 06:08:15 PM COT - -# Created by Pcbnew(2010-07-27 BZR 2423)-unstable +PCBNEW-BOARD Version 1 date Tue 10 Aug 2010 09:13:52 PM COT $GENERAL LayerCount 4 Ly 1FFF8007 -EnabledLayers 1FFF8007 -Links 412 -NoConn 412 -Di 41329 -2756 85664 44681 +Links 420 +NoConn 420 +Di 41429 -2230 85564 44550 Ndraw 0 Ntrack 0 Nzone 0 -BoardThickness 630 Nmodule 63 -Nnets 142 +Nnets 144 $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "10 aug 2010" +Date "11 aug 2010" Rev "" Comp "" Comment1 "" @@ -38,20 +34,20 @@ Layer[1] Inner2 signal Layer[2] Inner3 signal Layer[15] Front signal TrackWidth 80 +TrackWidthHistory 80 +TrackWidthHistory 170 TrackClearence 100 ZoneClearence 200 -TrackMinWidth 80 DrawSegmWidth 150 EdgeSegmWidth 150 ViaSize 350 ViaDrill 250 -ViaMinSize 350 -ViaMinDrill 200 +ViaAltDrill 250 +ViaSizeHistory 350 +ViaSizeHistory 450 MicroViaSize 200 MicroViaDrill 50 MicroViasAllowed 0 -MicroViaMinSize 200 -MicroViaMinDrill 50 TextPcbWidth 120 TextPcbSize 600 800 EdgeModWidth 150 @@ -59,7 +55,6 @@ TextModSize 600 600 TextModWidth 120 PadSize 600 600 PadDrill 320 -Pad2MaskClearance 100 AuxiliaryAxisOrg 0 0 $EndSETUP @@ -68,721 +63,577 @@ Na 0 "" St ~ $EndEQUIPOT $EQUIPOT -Na 1 "+2.5V" +Na 1 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 2 "/DDR_Banks/M0_A12" +Na 2 "/FPGA_Spartan6/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 3 "/DDR_Banks/M0_A5" +Na 3 "/FPGA_Spartan6/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 4 "/DDR_Banks/M0_A9" +Na 4 "/FPGA_Spartan6/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/DDR_Banks/M0_CKE" +Na 5 "/FPGA_Spartan6/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_CLK" +Na 6 "/FPGA_Spartan6/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_CLK#" +Na 7 "/FPGA_Spartan6/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_DQ12" +Na 8 "/Non_volatile_memories/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_DQ13" +Na 9 "/Non_volatile_memories/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_DQ15" +Na 10 "/FPGA_Spartan6/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_DQ2" +Na 11 "/FPGA_Spartan6/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_DQ3" +Na 12 "+3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_UDQS" +Na 13 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M1_A0" +Na 14 "/FPGA_Spartan6/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M1_A11" +Na 15 "/FPGA_Spartan6/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M1_A7" +Na 16 "/Non_volatile_memories/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M1_A9" +Na 17 "/FPGA_Spartan6/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M1_BA0" +Na 18 "/DDR_Banks/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M1_CAS#" +Na 19 "+2.5V" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M1_CLK#" +Na 20 "/FPGA_Spartan6/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M1_DQ0" +Na 21 "/FPGA_Spartan6/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M1_DQ1" +Na 22 "/FPGA_Spartan6/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_DQ12" +Na 23 "/FPGA_Spartan6/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_DQ2" +Na 24 "/FPGA_Spartan6/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_DQ7" +Na 25 "/Non_volatile_memories/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_DQ8" +Na 26 "/Non_volatile_memories/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_UDM" +Na 27 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_UDQS" +Na 28 "/DDR_Banks/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_WE#" +Na 29 "/DDR_Banks/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/Ethernet_Phy/ETH_1.8V" +Na 30 "/DDR_Banks/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/Ethernet_Phy/ETH_A1.8V" +Na 31 "/FPGA_Spartan6/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/Ethernet_Phy/ETH_A3.3V" +Na 32 "/FPGA_Spartan6/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/Ethernet_Phy/ETH_INT" +Na 33 "/FPGA_Spartan6/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/Ethernet_Phy/ETH_LED0" +Na 34 "/FPGA_Spartan6/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/Ethernet_Phy/ETH_LED1" +Na 35 "/FPGA_Spartan6/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/Ethernet_Phy/ETH_MDC" +Na 36 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/Ethernet_Phy/ETH_MDIO" +Na 37 "/FPGA_Spartan6/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/Ethernet_Phy/ETH_PLL1.8V" +Na 38 "/DDR_Banks/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/Ethernet_Phy/ETH_RXC" +Na 39 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Ethernet_Phy/ETH_RXD1" +Na 40 "/DDR_Banks/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_RXD3" +Na 41 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_RXDV" +Na 42 "/FPGA_Spartan6/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_TXC" +Na 43 "/DDR_Banks/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_TXD1" +Na 44 "/DDR_Banks/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_TXD2" +Na 45 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_TXEN" +Na 46 "/DDR_Banks/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_TXER" +Na 47 "/DDR_Banks/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/FPGA_Spartan6/ETH_CLK" +Na 48 "/DDR_Banks/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/FPGA_Spartan6/ETH_RESET_N" +Na 49 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/FPGA_Spartan6/ETH_RXD0" +Na 50 "/DDR_Banks/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/FPGA_Spartan6/ETH_RXD2" +Na 51 "/DDR_Banks/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Spartan6/ETH_RXER" +Na 52 "/DDR_Banks/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Spartan6/ETH_TXD0" +Na 53 "/DDR_Banks/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Spartan6/ETH_TXD3" +Na 54 "/DDR_Banks/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Spartan6/M0_A0" +Na 55 "/DDR_Banks/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/M0_A1" +Na 56 "/DDR_Banks/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/M0_A10" +Na 57 "/DDR_Banks/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/M0_A11" +Na 58 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/M0_A2" +Na 59 "/DDR_Banks/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/M0_A3" +Na 60 "/DDR_Banks/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/M0_A4" +Na 61 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/M0_A6" +Na 62 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/M0_A7" +Na 63 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/M0_A8" +Na 64 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/M0_BA0" +Na 65 "/DDR_Banks/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/M0_BA1" +Na 66 "/DDR_Banks/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/M0_CAS#" +Na 67 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/M0_DQ0" +Na 68 "/DDR_Banks/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_DQ1" +Na 69 "+1.2V" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_DQ10" +Na 70 "/DDR_Banks/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_DQ11" +Na 71 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_DQ14" +Na 72 "/DDR_Banks/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_DQ4" +Na 73 "/DDR_Banks/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_DQ5" +Na 74 "/DDR_Banks/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_DQ6" +Na 75 "/DDR_Banks/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_DQ7" +Na 76 "/DDR_Banks/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_DQ8" +Na 77 "/DDR_Banks/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_DQ9" +Na 78 "/DDR_Banks/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_LDM" +Na 79 "/DDR_Banks/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_LDQS" +Na 80 "/DDR_Banks/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_RAS#" +Na 81 "/DDR_Banks/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_UDM" +Na 82 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_WE#" +Na 83 "/DDR_Banks/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M1_A1" +Na 84 "/DDR_Banks/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M1_A10" +Na 85 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M1_A12" +Na 86 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M1_A2" +Na 87 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M1_A3" +Na 88 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M1_A4" +Na 89 "/DDR_Banks/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M1_A5" +Na 90 "/DDR_Banks/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M1_A6" +Na 91 "/DDR_Banks/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M1_A8" +Na 92 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M1_BA1" +Na 93 "/DDR_Banks/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_CKE" +Na 94 "/DDR_Banks/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_CLK" +Na 95 "/DDR_Banks/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_DQ10" +Na 96 "/DDR_Banks/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_DQ11" +Na 97 "/DDR_Banks/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_DQ13" +Na 98 "/DDR_Banks/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_DQ14" +Na 99 "/DDR_Banks/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_DQ15" +Na 100 "/DDR_Banks/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_DQ3" +Na 101 "/DDR_Banks/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_DQ4" +Na 102 "/DDR_Banks/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_DQ5" +Na 103 "/DDR_Banks/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_DQ6" +Na 104 "/DDR_Banks/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ9" +Na 105 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_LDM" +Na 106 "/DDR_Banks/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_LDQS" +Na 107 "/DDR_Banks/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_RAS#" +Na 108 "N-000101" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/SD_CLK" +Na 109 "/DDR_Banks/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/SD_CMD" +Na 110 "/DDR_Banks/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/SD_DAT3" +Na 111 "/DDR_Banks/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/Non_volatile_memories/FRB_N" +Na 112 "/DDR_Banks/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/Non_volatile_memories/SD_DAT0" +Na 113 "/DDR_Banks/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/Non_volatile_memories/SD_DAT1" +Na 114 "/DDR_Banks/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/Non_volatile_memories/SD_DAT2" +Na 115 "/DDR_Banks/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "3.3V" +Na 116 "/DDR_Banks/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "GND" +Na 117 "/DDR_Banks/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "N-000043" +Na 118 "N-000069" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "N-000044" +Na 119 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "N-000045" +Na 120 "N-000345" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "N-000047" +Na 121 "N-000340" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "N-000098" +Na 122 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "N-000099" +Na 123 "N-000338" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "N-000100" +Na 124 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "N-000101" +Na 125 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "N-000102" +Na 126 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "N-000103" +Na 127 "N-000339" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "N-000341" +Na 128 "N-000346" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "N-000350" +Na 129 "/Ethernet_Phy/ETH_1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "N-000351" +Na 130 "/Non_volatile_memories/FRB_N" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "N-000352" +Na 131 "N-000347" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "N-000354" +Na 132 "N-000343" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "N-000355" +Na 133 "N-000342" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "N-000356" +Na 134 "N-000360" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "N-000358" +Na 135 "N-000361" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "N-000359" +Na 136 "N-000047" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "N-000360" +Na 137 "N-000046" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "N-000361" +Na 138 "N-000363" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "N-000362" +Na 139 "N-000349" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "N-000367" +Na 140 "N-000348" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "N-000368" +Na 141 "N-000362" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 142 "N-000045" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 143 "N-000048" St ~ $EndEQUIPOT -$NCLASS -Name "Default" -Desc "This is the default net class." -Clearance 100 -TrackWidth 80 -ViaDia 350 -ViaDrill 250 -uViaDia 200 -uViaDrill 50 -AddNet "" -AddNet "+2.5V" -AddNet "/DDR_Banks/M0_A12" -AddNet "/DDR_Banks/M0_A5" -AddNet "/DDR_Banks/M0_A9" -AddNet "/DDR_Banks/M0_CKE" -AddNet "/DDR_Banks/M0_CLK" -AddNet "/DDR_Banks/M0_CLK#" -AddNet "/DDR_Banks/M0_DQ12" -AddNet "/DDR_Banks/M0_DQ13" -AddNet "/DDR_Banks/M0_DQ15" -AddNet "/DDR_Banks/M0_DQ2" -AddNet "/DDR_Banks/M0_DQ3" -AddNet "/DDR_Banks/M0_UDQS" -AddNet "/DDR_Banks/M1_A0" -AddNet "/DDR_Banks/M1_A11" -AddNet "/DDR_Banks/M1_A7" -AddNet "/DDR_Banks/M1_A9" -AddNet "/DDR_Banks/M1_BA0" -AddNet "/DDR_Banks/M1_CAS#" -AddNet "/DDR_Banks/M1_CLK#" -AddNet "/DDR_Banks/M1_DQ0" -AddNet "/DDR_Banks/M1_DQ1" -AddNet "/DDR_Banks/M1_DQ12" -AddNet "/DDR_Banks/M1_DQ2" -AddNet "/DDR_Banks/M1_DQ7" -AddNet "/DDR_Banks/M1_DQ8" -AddNet "/DDR_Banks/M1_UDM" -AddNet "/DDR_Banks/M1_UDQS" -AddNet "/DDR_Banks/M1_WE#" -AddNet "/Ethernet_Phy/ETH_1.8V" -AddNet "/Ethernet_Phy/ETH_A1.8V" -AddNet "/Ethernet_Phy/ETH_A3.3V" -AddNet "/Ethernet_Phy/ETH_INT" -AddNet "/Ethernet_Phy/ETH_LED0" -AddNet "/Ethernet_Phy/ETH_LED1" -AddNet "/Ethernet_Phy/ETH_MDC" -AddNet "/Ethernet_Phy/ETH_MDIO" -AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/ETH_RXC" -AddNet "/Ethernet_Phy/ETH_RXD1" -AddNet "/Ethernet_Phy/ETH_RXD3" -AddNet "/Ethernet_Phy/ETH_RXDV" -AddNet "/Ethernet_Phy/ETH_TXC" -AddNet "/Ethernet_Phy/ETH_TXD1" -AddNet "/Ethernet_Phy/ETH_TXD2" -AddNet "/Ethernet_Phy/ETH_TXEN" -AddNet "/Ethernet_Phy/ETH_TXER" -AddNet "/FPGA_Spartan6/ETH_CLK" -AddNet "/FPGA_Spartan6/ETH_RESET_N" -AddNet "/FPGA_Spartan6/ETH_RXD0" -AddNet "/FPGA_Spartan6/ETH_RXD2" -AddNet "/FPGA_Spartan6/ETH_RXER" -AddNet "/FPGA_Spartan6/ETH_TXD0" -AddNet "/FPGA_Spartan6/ETH_TXD3" -AddNet "/FPGA_Spartan6/M0_A0" -AddNet "/FPGA_Spartan6/M0_A1" -AddNet "/FPGA_Spartan6/M0_A10" -AddNet "/FPGA_Spartan6/M0_A11" -AddNet "/FPGA_Spartan6/M0_A2" -AddNet "/FPGA_Spartan6/M0_A3" -AddNet "/FPGA_Spartan6/M0_A4" -AddNet "/FPGA_Spartan6/M0_A6" -AddNet "/FPGA_Spartan6/M0_A7" -AddNet "/FPGA_Spartan6/M0_A8" -AddNet "/FPGA_Spartan6/M0_BA0" -AddNet "/FPGA_Spartan6/M0_BA1" -AddNet "/FPGA_Spartan6/M0_CAS#" -AddNet "/FPGA_Spartan6/M0_DQ0" -AddNet "/FPGA_Spartan6/M0_DQ1" -AddNet "/FPGA_Spartan6/M0_DQ10" -AddNet "/FPGA_Spartan6/M0_DQ11" -AddNet "/FPGA_Spartan6/M0_DQ14" -AddNet "/FPGA_Spartan6/M0_DQ4" -AddNet "/FPGA_Spartan6/M0_DQ5" -AddNet "/FPGA_Spartan6/M0_DQ6" -AddNet "/FPGA_Spartan6/M0_DQ7" -AddNet "/FPGA_Spartan6/M0_DQ8" -AddNet "/FPGA_Spartan6/M0_DQ9" -AddNet "/FPGA_Spartan6/M0_LDM" -AddNet "/FPGA_Spartan6/M0_LDQS" -AddNet "/FPGA_Spartan6/M0_RAS#" -AddNet "/FPGA_Spartan6/M0_UDM" -AddNet "/FPGA_Spartan6/M0_WE#" -AddNet "/FPGA_Spartan6/M1_A1" -AddNet "/FPGA_Spartan6/M1_A10" -AddNet "/FPGA_Spartan6/M1_A12" -AddNet "/FPGA_Spartan6/M1_A2" -AddNet "/FPGA_Spartan6/M1_A3" -AddNet "/FPGA_Spartan6/M1_A4" -AddNet "/FPGA_Spartan6/M1_A5" -AddNet "/FPGA_Spartan6/M1_A6" -AddNet "/FPGA_Spartan6/M1_A8" -AddNet "/FPGA_Spartan6/M1_BA1" -AddNet "/FPGA_Spartan6/M1_CKE" -AddNet "/FPGA_Spartan6/M1_CLK" -AddNet "/FPGA_Spartan6/M1_DQ10" -AddNet "/FPGA_Spartan6/M1_DQ11" -AddNet "/FPGA_Spartan6/M1_DQ13" -AddNet "/FPGA_Spartan6/M1_DQ14" -AddNet "/FPGA_Spartan6/M1_DQ15" -AddNet "/FPGA_Spartan6/M1_DQ3" -AddNet "/FPGA_Spartan6/M1_DQ4" -AddNet "/FPGA_Spartan6/M1_DQ5" -AddNet "/FPGA_Spartan6/M1_DQ6" -AddNet "/FPGA_Spartan6/M1_DQ9" -AddNet "/FPGA_Spartan6/M1_LDM" -AddNet "/FPGA_Spartan6/M1_LDQS" -AddNet "/FPGA_Spartan6/M1_RAS#" -AddNet "/FPGA_Spartan6/SD_CLK" -AddNet "/FPGA_Spartan6/SD_CMD" -AddNet "/FPGA_Spartan6/SD_DAT3" -AddNet "/Non_volatile_memories/FRB_N" -AddNet "/Non_volatile_memories/SD_DAT0" -AddNet "/Non_volatile_memories/SD_DAT1" -AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "3.3V" -AddNet "GND" -AddNet "N-000043" -AddNet "N-000044" -AddNet "N-000045" -AddNet "N-000047" -AddNet "N-000098" -AddNet "N-000099" -AddNet "N-000100" -AddNet "N-000101" -AddNet "N-000102" -AddNet "N-000103" -AddNet "N-000341" -AddNet "N-000350" -AddNet "N-000351" -AddNet "N-000352" -AddNet "N-000354" -AddNet "N-000355" -AddNet "N-000356" -AddNet "N-000358" -AddNet "N-000359" -AddNet "N-000360" -AddNet "N-000361" -AddNet "N-000362" -AddNet "N-000367" -AddNet "N-000368" -$EndNCLASS $MODULE FGG484bga-p10 Po 56450 33930 0 15 4C4325AE 4C431E53 ~~ Li FGG484bga-p10 @@ -804,7 +655,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -4133 -4133 $EndPAD $PAD @@ -832,42 +683,42 @@ $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/Ethernet_Phy/ETH_INT" +Ne 2 "/FPGA_Spartan6/ETH_INT" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_RXD3" +Ne 3 "/FPGA_Spartan6/ETH_RXD3" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_RXD1" +Ne 4 "/FPGA_Spartan6/ETH_RXD1" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_RXDV" +Ne 5 "/FPGA_Spartan6/ETH_RXDV" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_TXD0" +Ne 6 "/FPGA_Spartan6/ETH_TXD0" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/FPGA_Spartan6/ETH_CLK" +Ne 7 "/FPGA_Spartan6/ETH_CLK" Po -590 -4133 $EndPAD $PAD @@ -902,28 +753,28 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/SD_DAT3" +Ne 8 "/Non_volatile_memories/SD_DAT3" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/SD_CLK" +Ne 9 "/Non_volatile_memories/SD_CLK" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 10 "/FPGA_Spartan6/USBA_VM" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 11 "/FPGA_Spartan6/USBA_RCV" Po 2558 -4133 $EndPAD $PAD @@ -951,7 +802,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 4133 -4133 $EndPAD $PAD @@ -979,56 +830,56 @@ $PAD Sh "B4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000100" +Ne 12 "+3.3V" Po -2952 -3739 $EndPAD $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2558 -3739 $EndPAD $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/FPGA_Spartan6/ETH_RESET_N" +Ne 13 "/FPGA_Spartan6/ETH_RESET_N" Po -2165 -3739 $EndPAD $PAD Sh "B7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000100" +Ne 12 "+3.3V" Po -1771 -3739 $EndPAD $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Spartan6/ETH_RXD0" +Ne 14 "/FPGA_Spartan6/ETH_RXD0" Po -1377 -3739 $EndPAD $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -983 -3739 $EndPAD $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_RXC" +Ne 15 "/FPGA_Spartan6/ETH_RXC" Po -590 -3739 $EndPAD $PAD Sh "B11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000100" +Ne 12 "+3.3V" Po -196 -3739 $EndPAD $PAD @@ -1042,7 +893,7 @@ $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 590 -3739 $EndPAD $PAD @@ -1056,35 +907,35 @@ $PAD Sh "B15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000100" +Ne 12 "+3.3V" Po 1377 -3739 $EndPAD $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/Non_volatile_memories/SD_DAT0" +Ne 16 "/Non_volatile_memories/SD_DAT0" Po 1771 -3739 $EndPAD $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 2165 -3739 $EndPAD $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 17 "/FPGA_Spartan6/USBA_VP" Po 2558 -3739 $EndPAD $PAD Sh "B19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000100" +Ne 12 "+3.3V" Po 2952 -3739 $EndPAD $PAD @@ -1112,14 +963,14 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/M0_A11" +Ne 18 "/DDR_Banks/M0_A11" Po -4133 -3346 $EndPAD $PAD Sh "C2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -3739 -3346 $EndPAD $PAD @@ -1147,35 +998,35 @@ $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_MDIO" +Ne 20 "/FPGA_Spartan6/ETH_MDIO" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/ETH_RXD2" +Ne 21 "/FPGA_Spartan6/ETH_RXD2" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_TXER" +Ne 22 "/FPGA_Spartan6/ETH_TXER" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_TXEN" +Ne 23 "/FPGA_Spartan6/ETH_TXEN" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_TXC" +Ne 24 "/FPGA_Spartan6/ETH_TXC" Po -590 -3346 $EndPAD $PAD @@ -1217,14 +1068,14 @@ $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/Non_volatile_memories/SD_DAT1" +Ne 25 "/Non_volatile_memories/SD_DAT1" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/SD_CMD" +Ne 26 "/Non_volatile_memories/SD_CMD" Po 2165 -3346 $EndPAD $PAD @@ -1245,35 +1096,35 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A8" +Ne 27 "/DDR_Banks/M1_A8" Po 3346 -3346 $EndPAD $PAD Sh "C21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000099" +Ne 19 "+2.5V" Po 3739 -3346 $EndPAD $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M1_A9" +Ne 28 "/DDR_Banks/M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/DDR_Banks/M0_A12" +Ne 29 "/DDR_Banks/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_CKE" +Ne 30 "/DDR_Banks/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1287,7 +1138,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1301,35 +1152,35 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_MDC" +Ne 31 "/FPGA_Spartan6/ETH_MDC" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_TXD1" +Ne 32 "/FPGA_Spartan6/ETH_TXD1" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_TXD2" +Ne 33 "/FPGA_Spartan6/ETH_TXD2" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_RXER" +Ne 34 "/FPGA_Spartan6/ETH_RXER" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_TXD3" +Ne 35 "/FPGA_Spartan6/ETH_TXD3" Po -590 -2952 $EndPAD $PAD @@ -1364,28 +1215,28 @@ $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/Non_volatile_memories/SD_DAT2" +Ne 36 "/Non_volatile_memories/SD_DAT2" Po 1377 -2952 $EndPAD $PAD Sh "D16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po 1771 -2952 $EndPAD $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 37 "/FPGA_Spartan6/USBA_SPD" Po 2165 -2952 $EndPAD $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 2558 -2952 $EndPAD $PAD @@ -1406,35 +1257,35 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_CKE" +Ne 38 "/DDR_Banks/M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M1_A12" +Ne 39 "/DDR_Banks/M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/DDR_Banks/M0_A9" +Ne 40 "/DDR_Banks/M0_A9" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A8" +Ne 41 "/DDR_Banks/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1462,7 +1313,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -1771 -2558 $EndPAD $PAD @@ -1476,7 +1327,7 @@ $PAD Sh "E9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000100" +Ne 12 "+3.3V" Po -983 -2558 $EndPAD $PAD @@ -1504,7 +1355,7 @@ $PAD Sh "E13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000100" +Ne 12 "+3.3V" Po 590 -2558 $EndPAD $PAD @@ -1518,21 +1369,21 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 1377 -2558 $EndPAD $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 42 "/FPGA_Spartan6/USBA_OE_N" Po 1771 -2558 $EndPAD $PAD Sh "E17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000100" +Ne 12 "+3.3V" Po 2165 -2558 $EndPAD $PAD @@ -1546,28 +1397,28 @@ $PAD Sh "E19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000099" +Ne 19 "+2.5V" Po 2952 -2558 $EndPAD $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M1_A7" +Ne 43 "/DDR_Banks/M1_A7" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M1_A2" +Ne 44 "/DDR_Banks/M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -1581,21 +1432,21 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_WE#" +Ne 45 "/DDR_Banks/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/M0_A4" +Ne 46 "/DDR_Banks/M0_A4" Po -3346 -2165 $EndPAD $PAD Sh "F4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -2952 -2165 $EndPAD $PAD @@ -1609,7 +1460,7 @@ $PAD Sh "F6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -2165 -2165 $EndPAD $PAD @@ -1644,7 +1495,7 @@ $PAD Sh "F11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po -196 -2165 $EndPAD $PAD @@ -1700,63 +1551,63 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M1_A11" +Ne 47 "/DDR_Banks/M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A4" +Ne 48 "/DDR_Banks/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M1_A0" +Ne 49 "/DDR_Banks/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M1_A1" +Ne 50 "/DDR_Banks/M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_BA1" +Ne 51 "/DDR_Banks/M0_BA1" Po -4133 -1771 $EndPAD $PAD Sh "G2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -3739 -1771 $EndPAD $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_BA0" +Ne 52 "/DDR_Banks/M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/M0_A10" +Ne 53 "/DDR_Banks/M0_A10" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2558 -1771 $EndPAD $PAD @@ -1791,7 +1642,7 @@ $PAD Sh "G10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000100" +Ne 12 "+3.3V" Po -590 -1771 $EndPAD $PAD @@ -1805,7 +1656,7 @@ $PAD Sh "G12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po 196 -1771 $EndPAD $PAD @@ -1819,7 +1670,7 @@ $PAD Sh "G14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "N-000100" +Ne 12 "+3.3V" Po 983 -1771 $EndPAD $PAD @@ -1847,28 +1698,28 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M1_A10" +Ne 54 "/DDR_Banks/M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M1_A3" +Ne 55 "/DDR_Banks/M1_A3" Po 3346 -1771 $EndPAD $PAD Sh "G21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000099" +Ne 19 "+2.5V" Po 3739 -1771 $EndPAD $PAD @@ -1882,49 +1733,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/M0_A1" +Ne 56 "/DDR_Banks/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/M0_A0" +Ne 57 "/DDR_Banks/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_CLK#" +Ne 58 "/DDR_Banks/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_CLK" +Ne 59 "/DDR_Banks/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/M0_A2" +Ne 60 "/DDR_Banks/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M0_A7" +Ne 61 "/DDR_Banks/M0_A7" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -1771 -1377 $EndPAD $PAD @@ -1938,7 +1789,7 @@ $PAD Sh "H9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po -983 -1377 $EndPAD $PAD @@ -1980,7 +1831,7 @@ $PAD Sh "H15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po 1377 -1377 $EndPAD $PAD @@ -2008,63 +1859,63 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_WE#" +Ne 62 "/DDR_Banks/M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_CLK" +Ne 63 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_RAS#" +Ne 64 "/DDR_Banks/M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M1_CAS#" +Ne 65 "/DDR_Banks/M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_DQ5" +Ne 66 "/DDR_Banks/M0_DQ5" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_DQ4" +Ne 67 "/DDR_Banks/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/M0_A6" +Ne 68 "/DDR_Banks/M0_A6" Po -2952 -983 $EndPAD $PAD Sh "J5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -2558 -983 $EndPAD $PAD @@ -2085,56 +1936,56 @@ $PAD Sh "J8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po -1377 -983 $EndPAD $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -983 -983 $EndPAD $PAD Sh "J10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po -590 -983 $EndPAD $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -196 -983 $EndPAD $PAD Sh "J12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po 196 -983 $EndPAD $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 590 -983 $EndPAD $PAD Sh "J14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po 983 -983 $EndPAD $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 1377 -983 $EndPAD $PAD @@ -2148,84 +1999,84 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M1_BA0" +Ne 70 "/DDR_Banks/M1_BA0" Po 2165 -983 $EndPAD $PAD Sh "J18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000099" +Ne 19 "+2.5V" Po 2558 -983 $EndPAD $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_CLK#" +Ne 71 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ4" +Ne 72 "/DDR_Banks/M1_DQ4" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ5" +Ne 73 "/DDR_Banks/M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ7" +Ne 74 "/DDR_Banks/M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_DQ6" +Ne 75 "/DDR_Banks/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/DDR_Banks/M0_A5" +Ne 76 "/DDR_Banks/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_CAS#" +Ne 77 "/DDR_Banks/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_RAS#" +Ne 78 "/DDR_Banks/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/M0_A3" +Ne 79 "/DDR_Banks/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2246,21 +2097,21 @@ $PAD Sh "K9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po -983 -590 $EndPAD $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -590 -590 $EndPAD $PAD Sh "K11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po -196 -590 $EndPAD $PAD @@ -2274,21 +2125,21 @@ $PAD Sh "K13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po 590 -590 $EndPAD $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 983 -590 $EndPAD $PAD Sh "K15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po 1377 -590 $EndPAD $PAD @@ -2302,7 +2153,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_BA1" +Ne 80 "/DDR_Banks/M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2316,28 +2167,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A6" +Ne 81 "/DDR_Banks/M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A5" +Ne 82 "/DDR_Banks/M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ6" +Ne 83 "/DDR_Banks/M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_DQ7" +Ne 84 "/DDR_Banks/M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2351,28 +2202,28 @@ $PAD Sh "L2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -3739 -196 $EndPAD $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_LDQS" +Ne 85 "/DDR_Banks/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_LDM" +Ne 86 "/DDR_Banks/M0_LDM" Po -2952 -196 $EndPAD $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2558 -196 $EndPAD $PAD @@ -2386,56 +2237,56 @@ $PAD Sh "L7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -1771 -196 $EndPAD $PAD Sh "L8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po -1377 -196 $EndPAD $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -983 -196 $EndPAD $PAD Sh "L10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po -590 -196 $EndPAD $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -196 -196 $EndPAD $PAD Sh "L12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po 196 -196 $EndPAD $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 590 -196 $EndPAD $PAD Sh "L14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po 983 -196 $EndPAD $PAD @@ -2449,7 +2300,7 @@ $PAD Sh "L16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000099" +Ne 19 "+2.5V" Po 1771 -196 $EndPAD $PAD @@ -2463,28 +2314,28 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_LDM" +Ne 87 "/DDR_Banks/M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_LDQS" +Ne 88 "/DDR_Banks/M1_LDQS" Po 3346 -196 $EndPAD $PAD Sh "L21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000099" +Ne 19 "+2.5V" Po 3739 -196 $EndPAD $PAD @@ -2498,21 +2349,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_DQ3" +Ne 89 "/DDR_Banks/M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_DQ2" +Ne 90 "/DDR_Banks/M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_UDM" +Ne 91 "/DDR_Banks/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2554,49 +2405,49 @@ $PAD Sh "M9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po -983 196 $EndPAD $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -590 196 $EndPAD $PAD Sh "M11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po -196 196 $EndPAD $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 196 196 $EndPAD $PAD Sh "M13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po 590 196 $EndPAD $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 983 196 $EndPAD $PAD Sh "M15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po 1377 196 $EndPAD $PAD @@ -2631,42 +2482,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_UDM" +Ne 92 "/DDR_Banks/M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_DQ2" +Ne 93 "/DDR_Banks/M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ3" +Ne 94 "/DDR_Banks/M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_DQ1" +Ne 95 "/DDR_Banks/M0_DQ1" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_DQ0" +Ne 96 "/DDR_Banks/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -2680,7 +2531,7 @@ $PAD Sh "N5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -2558 590 $EndPAD $PAD @@ -2701,49 +2552,49 @@ $PAD Sh "N8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po -1377 590 $EndPAD $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -983 590 $EndPAD $PAD Sh "N10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po -590 590 $EndPAD $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -196 590 $EndPAD $PAD Sh "N12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po 196 590 $EndPAD $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 590 590 $EndPAD $PAD Sh "N14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po 983 590 $EndPAD $PAD @@ -2764,14 +2615,14 @@ $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 2165 590 $EndPAD $PAD Sh "N18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000099" +Ne 19 "+2.5V" Po 2558 590 $EndPAD $PAD @@ -2785,35 +2636,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_DQ0" +Ne 97 "/DDR_Banks/M1_DQ0" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_DQ1" +Ne 98 "/DDR_Banks/M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ9" +Ne 99 "/DDR_Banks/M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ8" +Ne 100 "/DDR_Banks/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -2862,42 +2713,42 @@ $PAD Sh "P9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po -983 983 $EndPAD $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -590 983 $EndPAD $PAD Sh "P11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po -196 983 $EndPAD $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 196 983 $EndPAD $PAD Sh "P13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po 590 983 $EndPAD $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 983 983 $EndPAD $PAD @@ -2946,35 +2797,35 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_DQ8" +Ne 101 "/DDR_Banks/M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ9" +Ne 102 "/DDR_Banks/M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_DQ11" +Ne 103 "/DDR_Banks/M0_DQ11" Po -4133 1377 $EndPAD $PAD Sh "R2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -3739 1377 $EndPAD $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_DQ10" +Ne 104 "/DDR_Banks/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -2988,14 +2839,14 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2558 1377 $EndPAD $PAD Sh "R6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po -2165 1377 $EndPAD $PAD @@ -3023,7 +2874,7 @@ $PAD Sh "R10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po -590 1377 $EndPAD $PAD @@ -3037,7 +2888,7 @@ $PAD Sh "R12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po 196 1377 $EndPAD $PAD @@ -3051,7 +2902,7 @@ $PAD Sh "R14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "N-000102" +Ne 69 "+1.2V" Po 983 1377 $EndPAD $PAD @@ -3079,7 +2930,7 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 2558 1377 $EndPAD $PAD @@ -3093,21 +2944,21 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_DQ10" +Ne 105 "/DDR_Banks/M1_DQ10" Po 3346 1377 $EndPAD $PAD Sh "R21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000099" +Ne 19 "+2.5V" Po 3739 1377 $EndPAD $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_DQ11" +Ne 106 "/DDR_Banks/M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3121,7 +2972,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_UDQS" +Ne 107 "/DDR_Banks/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3170,7 +3021,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po -983 1771 $EndPAD $PAD @@ -3198,7 +3049,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po 590 1771 $EndPAD $PAD @@ -3254,7 +3105,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_UDQS" +Ne 109 "/DDR_Banks/M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3268,21 +3119,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_DQ13" +Ne 110 "/DDR_Banks/M0_DQ13" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_DQ12" +Ne 111 "/DDR_Banks/M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3296,7 +3147,7 @@ $PAD Sh "U5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -2558 2165 $EndPAD $PAD @@ -3310,7 +3161,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -1771 2165 $EndPAD $PAD @@ -3338,7 +3189,7 @@ $PAD Sh "U11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po -196 2165 $EndPAD $PAD @@ -3387,7 +3238,7 @@ $PAD Sh "U18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000099" +Ne 19 "+2.5V" Po 2558 2165 $EndPAD $PAD @@ -3401,35 +3252,35 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_DQ12" +Ne 112 "/DDR_Banks/M1_DQ12" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_DQ13" +Ne 113 "/DDR_Banks/M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_DQ15" +Ne 114 "/DDR_Banks/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_DQ14" +Ne 115 "/DDR_Banks/M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3443,7 +3294,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2952 2558 $EndPAD $PAD @@ -3457,7 +3308,7 @@ $PAD Sh "V6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000103" +Ne 19 "+2.5V" Po -2165 2558 $EndPAD $PAD @@ -3471,7 +3322,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po -1377 2558 $EndPAD $PAD @@ -3485,7 +3336,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -590 2558 $EndPAD $PAD @@ -3499,7 +3350,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po 196 2558 $EndPAD $PAD @@ -3513,7 +3364,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 983 2558 $EndPAD $PAD @@ -3527,7 +3378,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po 1771 2558 $EndPAD $PAD @@ -3562,14 +3413,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_DQ14" +Ne 116 "/DDR_Banks/M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_DQ15" +Ne 117 "/DDR_Banks/M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -3583,7 +3434,7 @@ $PAD Sh "W2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "N-000098" +Ne 19 "+2.5V" Po -3739 2952 $EndPAD $PAD @@ -3604,7 +3455,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po -2558 2952 $EndPAD $PAD @@ -3618,7 +3469,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -1771 2952 $EndPAD $PAD @@ -3681,7 +3532,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 1771 2952 $EndPAD $PAD @@ -3702,7 +3553,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 2952 2952 $EndPAD $PAD @@ -3716,7 +3567,7 @@ $PAD Sh "W21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000099" +Ne 19 "+2.5V" Po 3739 2952 $EndPAD $PAD @@ -3898,7 +3749,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po -3346 3739 $EndPAD $PAD @@ -3912,7 +3763,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2558 3739 $EndPAD $PAD @@ -3926,7 +3777,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po -1771 3739 $EndPAD $PAD @@ -3940,7 +3791,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -983 3739 $EndPAD $PAD @@ -3954,7 +3805,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po -196 3739 $EndPAD $PAD @@ -3968,7 +3819,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 590 3739 $EndPAD $PAD @@ -3982,7 +3833,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po 1377 3739 $EndPAD $PAD @@ -3996,7 +3847,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 2165 3739 $EndPAD $PAD @@ -4010,7 +3861,7 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "N-000101" +Ne 108 "N-000101" Po 2952 3739 $EndPAD $PAD @@ -4038,7 +3889,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -4133 4133 $EndPAD $PAD @@ -4185,14 +4036,14 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 $MODULE LQFP48 -Po 53590 25490 900 15 4C433D64 4C61D678 ~~ +Po 53620 25730 900 15 4C433D64 4C432132 ~~ Li LQFP48 -Sc 4C61D678 +Sc 4C432132 AR /4C4320F3/4C432132 Op 0 0 0 At SMD @@ -4207,105 +4058,105 @@ $PAD Sh "12" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -1613 1082 $EndPAD $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_RXER" +Ne 34 "/FPGA_Spartan6/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_RXC" +Ne 15 "/FPGA_Spartan6/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_RXDV" +Ne 5 "/FPGA_Spartan6/ETH_RXDV" Po -1613 491 $EndPAD $PAD Sh "8" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -1613 295 $EndPAD $PAD Sh "7" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -1613 98 $EndPAD $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Spartan6/ETH_RXD0" +Ne 14 "/FPGA_Spartan6/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_RXD1" +Ne 4 "/FPGA_Spartan6/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/ETH_RXD2" +Ne 21 "/FPGA_Spartan6/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_RXD3" +Ne 3 "/FPGA_Spartan6/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_MDC" +Ne 31 "/FPGA_Spartan6/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_MDIO" +Ne 20 "/FPGA_Spartan6/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/FPGA_Spartan6/ETH_RESET_N" +Ne 13 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 119 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/FPGA_Spartan6/ETH_CLK" +Ne 7 "/FPGA_Spartan6/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -4319,7 +4170,7 @@ $PAD Sh "44" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -295 -1613 $EndPAD $PAD @@ -4340,56 +4191,56 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "N-000350" +Ne 120 "N-000345" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 136 "N-000359" +Ne 121 "N-000340" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Ethernet_Phy/ETH_A3.3V" +Ne 122 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000354" +Ne 123 "N-000338" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/Ethernet_Phy/ETH_INT" +Ne 2 "/FPGA_Spartan6/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Ethernet_Phy/ETH_LED0" +Ne 124 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_LED1" +Ne 125 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4417,21 +4268,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A1.8V" +Ne 126 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 135 "N-000358" +Ne 127 "N-000339" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "N-000341" +Ne 128 "N-000346" Po 1613 -491 $EndPAD $PAD @@ -4445,70 +4296,70 @@ $PAD Sh "35" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 1613 -1082 $EndPAD $PAD Sh "13" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/Ethernet_Phy/ETH_1.8V" +Ne 129 "/Ethernet_Phy/ETH_1.8V" Po -1082 1613 $EndPAD $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_TXER" +Ne 22 "/FPGA_Spartan6/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_TXC" +Ne 24 "/FPGA_Spartan6/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_TXEN" +Ne 23 "/FPGA_Spartan6/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_TXD0" +Ne 6 "/FPGA_Spartan6/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_TXD1" +Ne 32 "/FPGA_Spartan6/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_TXD2" +Ne 33 "/FPGA_Spartan6/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_TXD3" +Ne 35 "/FPGA_Spartan6/ETH_TXD3" Po 295 1613 $EndPAD $PAD @@ -4529,14 +4380,14 @@ $PAD Sh "23" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 885 1613 $EndPAD $PAD Sh "24" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po 1082 1613 $EndPAD $EndMODULE LQFP48 @@ -4800,14 +4651,14 @@ $PAD Sh "6" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/Non_volatile_memories/FRB_N" +Ne 130 "/Non_volatile_memories/FRB_N" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/Non_volatile_memories/FRB_N" +Ne 130 "/Non_volatile_memories/FRB_N" Po -1090 3850 $EndPAD $PAD @@ -4842,14 +4693,14 @@ $PAD Sh "12" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -100 3850 $EndPAD $PAD Sh "13" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 100 3850 $EndPAD $PAD @@ -4891,7 +4742,7 @@ $PAD Sh "19" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po 1280 3850 $EndPAD $PAD @@ -5010,14 +4861,14 @@ $PAD Sh "36" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 100 -3850 $EndPAD $PAD Sh "37" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -100 -3850 $EndPAD $PAD @@ -5119,21 +4970,21 @@ $PAD Sh "1" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 115 "/Non_volatile_memories/SD_DAT2" +Ne 36 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 111 "/FPGA_Spartan6/SD_DAT3" +Ne 8 "/Non_volatile_memories/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 110 "/FPGA_Spartan6/SD_CMD" +Ne 26 "/Non_volatile_memories/SD_CMD" Po -433 0 $EndPAD $PAD @@ -5147,56 +4998,56 @@ $PAD Sh "5" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 109 "/FPGA_Spartan6/SD_CLK" +Ne 9 "/Non_volatile_memories/SD_CLK" Po 433 0 $EndPAD $PAD Sh "6" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 866 0 $EndPAD $PAD Sh "7" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 113 "/Non_volatile_memories/SD_DAT0" +Ne 16 "/Non_volatile_memories/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 114 "/Non_volatile_memories/SD_DAT1" +Ne 25 "/Non_volatile_memories/SD_DAT1" Po 1732 0 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 2707 -1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2707 -1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2707 2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 2707 2244 $EndPAD $EndMODULE MICROSD-500901 @@ -5216,117 +5067,117 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 133 "N-000355" +Ne 131 "N-000347" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 133 "N-000355" +Ne 131 "N-000347" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 133 "N-000355" +Ne 131 "N-000347" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 133 "N-000355" +Ne 131 "N-000347" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 129 "N-000350" +Ne 120 "N-000345" Po -1750 -2500 $EndPAD $PAD Sh "3" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 116 "3.3V" +Ne 118 "N-000069" Po -750 -2500 $EndPAD $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 117 "GND" +Ne 1 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 128 "N-000341" +Ne 128 "N-000346" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 136 "N-000359" +Ne 121 "N-000340" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 117 "GND" +Ne 1 "GND" Po -250 -3500 $EndPAD $PAD Sh "6" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 116 "3.3V" +Ne 118 "N-000069" Po 750 -3500 $EndPAD $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 135 "N-000358" +Ne 127 "N-000339" Po 1750 -3500 $EndPAD $PAD Sh "9" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 116 "3.3V" +Ne 118 "N-000069" Po -2150 -5400 $EndPAD $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 130 "N-000351" +Ne 132 "N-000343" Po -1150 -5400 $EndPAD $PAD Sh "11" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 116 "3.3V" +Ne 118 "N-000069" Po 1150 -5400 $EndPAD $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 131 "N-000352" +Ne 133 "N-000342" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 $MODULE TSSOP-14 -Po 60260 18330 2700 15 4C60642A 4C5F2025 ~~ +Po 59770 18070 2700 15 4C60642A 4C5F2025 ~~ Li TSSOP-14 Sc 4C5F2025 AR /4C5F1EDC/4C5F2025 @@ -5350,35 +5201,35 @@ $PAD Sh "1" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -767 1112 $EndPAD $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 37 "/FPGA_Spartan6/USBA_SPD" Po -511 1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 11 "/FPGA_Spartan6/USBA_RCV" Po -255 1112 $EndPAD $PAD Sh "4" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 17 "/FPGA_Spartan6/USBA_VP" Po 0 1112 $EndPAD $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 10 "/FPGA_Spartan6/USBA_VM" Po 255 1112 $EndPAD $PAD @@ -5392,42 +5243,42 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 767 1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 767 -1112 $EndPAD $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 42 "/FPGA_Spartan6/USBA_OE_N" Po 511 -1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 141 "N-000368" +Ne 134 "N-000360" Po 255 -1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 139 "N-000362" +Ne 135 "N-000361" Po 0 -1112 $EndPAD $PAD Sh "12" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -255 -1112 $EndPAD $PAD @@ -5441,14 +5292,14 @@ $PAD Sh "14" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -767 -1112 $EndPAD $EndMODULE TSSOP-14 $MODULE TSOP-66 -Po 63780 34055 900 15 4C6098A7 4C60B7B8 ~~ +Po 63780 34055 900 15 4C6098A7 4C609C8E ~~ Li TSOP-66 -Sc 4C60B7B8 +Sc 4C609C8E AR /4C421DD3/4C609C8E Op 0 0 0 At SMD @@ -5463,91 +5314,91 @@ $PAD Sh "1" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -4094 2176 $EndPAD $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_DQ0" +Ne 97 "/DDR_Banks/M1_DQ0" Po -3838 2176 $EndPAD $PAD Sh "3" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -3582 2176 $EndPAD $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_DQ1" +Ne 98 "/DDR_Banks/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_DQ2" +Ne 93 "/DDR_Banks/M1_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ3" +Ne 94 "/DDR_Banks/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ4" +Ne 72 "/DDR_Banks/M1_DQ4" Po -2303 2176 $EndPAD $PAD Sh "9" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -2047 2176 $EndPAD $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ5" +Ne 73 "/DDR_Banks/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ6" +Ne 83 "/DDR_Banks/M1_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_DQ7" +Ne 84 "/DDR_Banks/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5561,14 +5412,14 @@ $PAD Sh "15" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -511 2176 $EndPAD $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_LDQS" +Ne 88 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -5582,7 +5433,7 @@ $PAD Sh "18" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po 255 2176 $EndPAD $PAD @@ -5596,35 +5447,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_LDM" +Ne 87 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_WE#" +Ne 62 "/DDR_Banks/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M1_CAS#" +Ne 65 "/DDR_Banks/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_RAS#" +Ne 64 "/DDR_Banks/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 1791 2176 $EndPAD $PAD @@ -5638,119 +5489,119 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M1_BA0" +Ne 70 "/DDR_Banks/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_BA1" +Ne 80 "/DDR_Banks/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M1_A10" +Ne 54 "/DDR_Banks/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M1_A0" +Ne 49 "/DDR_Banks/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M1_A1" +Ne 50 "/DDR_Banks/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M1_A2" +Ne 44 "/DDR_Banks/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M1_A3" +Ne 55 "/DDR_Banks/M1_A3" Po 3838 2176 $EndPAD $PAD Sh "33" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po 4094 2176 $EndPAD $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A4" +Ne 48 "/DDR_Banks/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A5" +Ne 82 "/DDR_Banks/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A6" +Ne 81 "/DDR_Banks/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M1_A7" +Ne 43 "/DDR_Banks/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A8" +Ne 27 "/DDR_Banks/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M1_A9" +Ne 28 "/DDR_Banks/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M1_A11" +Ne 47 "/DDR_Banks/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M1_A12" +Ne 39 "/DDR_Banks/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -5764,42 +5615,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_CLK#" +Ne 71 "/DDR_Banks/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_CKE" +Ne 38 "/DDR_Banks/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_CLK" +Ne 63 "/DDR_Banks/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_UDM" +Ne 92 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "N-000044" +Ne 136 "N-000047" Po 255 -2176 $EndPAD $PAD @@ -5813,14 +5664,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_UDQS" +Ne 109 "/DDR_Banks/M1_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -511 -2176 $EndPAD $PAD @@ -5834,98 +5685,98 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_DQ8" +Ne 101 "/DDR_Banks/M1_DQ8" Po -1023 -2176 $EndPAD $PAD Sh "55" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -1279 -2176 $EndPAD $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ9" +Ne 102 "/DDR_Banks/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_DQ10" +Ne 105 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_DQ11" +Ne 106 "/DDR_Banks/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_DQ12" +Ne 112 "/DDR_Banks/M1_DQ12" Po -2558 -2176 $EndPAD $PAD Sh "61" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -2814 -2176 $EndPAD $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_DQ13" +Ne 113 "/DDR_Banks/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_DQ14" +Ne 116 "/DDR_Banks/M1_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_DQ15" +Ne 117 "/DDR_Banks/M1_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 $MODULE TSOP-66 -Po 49016 34055 900 15 4C6098A7 4C60B7BA ~~ +Po 49016 34055 900 15 4C6098A7 4C609B99 ~~ Li TSOP-66 -Sc 4C60B7BA +Sc 4C609B99 AR /4C421DD3/4C609B99 Op 0 0 0 At SMD @@ -5940,91 +5791,91 @@ $PAD Sh "1" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -4094 2176 $EndPAD $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_DQ0" +Ne 96 "/DDR_Banks/M0_DQ0" Po -3838 2176 $EndPAD $PAD Sh "3" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -3582 2176 $EndPAD $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_DQ1" +Ne 95 "/DDR_Banks/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_DQ2" +Ne 90 "/DDR_Banks/M0_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_DQ3" +Ne 89 "/DDR_Banks/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_DQ4" +Ne 67 "/DDR_Banks/M0_DQ4" Po -2303 2176 $EndPAD $PAD Sh "9" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -2047 2176 $EndPAD $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_DQ5" +Ne 66 "/DDR_Banks/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_DQ6" +Ne 75 "/DDR_Banks/M0_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ7" +Ne 74 "/DDR_Banks/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -6038,14 +5889,14 @@ $PAD Sh "15" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -511 2176 $EndPAD $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_LDQS" +Ne 85 "/DDR_Banks/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -6059,7 +5910,7 @@ $PAD Sh "18" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po 255 2176 $EndPAD $PAD @@ -6073,35 +5924,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_LDM" +Ne 86 "/DDR_Banks/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_WE#" +Ne 45 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_CAS#" +Ne 77 "/DDR_Banks/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_RAS#" +Ne 78 "/DDR_Banks/M0_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 1791 2176 $EndPAD $PAD @@ -6115,119 +5966,119 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_BA0" +Ne 52 "/DDR_Banks/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_BA1" +Ne 51 "/DDR_Banks/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/M0_A10" +Ne 53 "/DDR_Banks/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/M0_A0" +Ne 57 "/DDR_Banks/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/M0_A1" +Ne 56 "/DDR_Banks/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/M0_A2" +Ne 60 "/DDR_Banks/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/M0_A3" +Ne 79 "/DDR_Banks/M0_A3" Po 3838 2176 $EndPAD $PAD Sh "33" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po 4094 2176 $EndPAD $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/M0_A4" +Ne 46 "/DDR_Banks/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/DDR_Banks/M0_A5" +Ne 76 "/DDR_Banks/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/M0_A6" +Ne 68 "/DDR_Banks/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M0_A7" +Ne 61 "/DDR_Banks/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A8" +Ne 41 "/DDR_Banks/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/DDR_Banks/M0_A9" +Ne 40 "/DDR_Banks/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/M0_A11" +Ne 18 "/DDR_Banks/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/DDR_Banks/M0_A12" +Ne 29 "/DDR_Banks/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6241,42 +6092,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_CLK#" +Ne 58 "/DDR_Banks/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_CKE" +Ne 30 "/DDR_Banks/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_CLK" +Ne 59 "/DDR_Banks/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_UDM" +Ne 91 "/DDR_Banks/M0_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "N-000045" +Ne 137 "N-000046" Po 255 -2176 $EndPAD $PAD @@ -6290,14 +6141,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_UDQS" +Ne 107 "/DDR_Banks/M0_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -511 -2176 $EndPAD $PAD @@ -6311,98 +6162,98 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ8" +Ne 100 "/DDR_Banks/M0_DQ8" Po -1023 -2176 $EndPAD $PAD Sh "55" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -1279 -2176 $EndPAD $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ9" +Ne 99 "/DDR_Banks/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_DQ10" +Ne 104 "/DDR_Banks/M0_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_DQ11" +Ne 103 "/DDR_Banks/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_DQ12" +Ne 111 "/DDR_Banks/M0_DQ12" Po -2558 -2176 $EndPAD $PAD Sh "61" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -2814 -2176 $EndPAD $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_DQ13" +Ne 110 "/DDR_Banks/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_DQ14" +Ne 115 "/DDR_Banks/M0_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_DQ15" +Ne 114 "/DDR_Banks/M0_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 $MODULE 0402 -Po 65839 23126 1800 15 4C5FF890 4C60BE78 ~~ +Po 65839 23126 1800 15 4C5FF890 4C5F2D27 ~~ Li 0402 -Sc 4C60BE78 +Sc 4C5F2D27 AR /4C5F1EDC/4C5F2D27 Op 0 0 0 At SMD @@ -6416,21 +6267,21 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000367" +Ne 138 "N-000363" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 56000 26000 0 15 4C5FF890 4C60BE7A ~~ +Po 56000 26000 0 15 4C5FF890 4C5D7DC4 ~~ Li 0402 -Sc 4C60BE7A +Sc 4C5D7DC4 AR /4C4320F3/4C5D7DC4 Op 0 0 0 At SMD @@ -6444,21 +6295,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "N-000355" +Ne 131 "N-000347" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 53543 22244 0 15 4C5FF890 4C60BE7C ~~ +Po 53543 22244 0 15 4C5FF890 4C5D71DB ~~ Li 0402 -Sc 4C60BE7C +Sc 4C5D71DB AR /4C4320F3/4C5D71DB Op 0 0 0 At SMD @@ -6472,21 +6323,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "N-000352" +Ne 133 "N-000342" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_LED1" +Ne 125 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 54921 22047 0 15 4C5FF890 4C60BE7E ~~ +Po 54921 22047 0 15 4C5FF890 4C5D719D ~~ Li 0402 -Sc 4C60BE7E +Sc 4C5D719D AR /4C4320F3/4C5D719D Op 0 0 0 At SMD @@ -6500,21 +6351,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "N-000351" +Ne 132 "N-000343" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Ethernet_Phy/ETH_LED0" +Ne 124 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 49016 27362 0 15 4C5FF890 4C60BE80 ~~ +Po 49016 27362 0 15 4C5FF890 4C5D7AF9 ~~ Li 0402 -Sc 4C60BE80 +Sc 4C5D7AF9 AR /4C4320F3/4C5D7AF9 Op 0 0 0 At SMD @@ -6528,21 +6379,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "N-000358" +Ne 127 "N-000339" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51000 25000 0 15 4C5FF890 4C60BE82 ~~ +Po 51000 25000 0 15 4C5FF890 4C5D7AF7 ~~ Li 0402 -Sc 4C60BE82 +Sc 4C5D7AF7 AR /4C4320F3/4C5D7AF7 Op 0 0 0 At SMD @@ -6556,21 +6407,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "N-000341" +Ne 128 "N-000346" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 48622 25197 0 15 4C5FF890 4C60BE84 ~~ +Po 48622 25197 0 15 4C5FF890 4C5D7AFC ~~ Li 0402 -Sc 4C60BE84 +Sc 4C5D7AFC AR /4C4320F3/4C5D7AFC Op 0 0 0 At SMD @@ -6584,21 +6435,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "N-000359" +Ne 121 "N-000340" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 41929 18504 0 15 4C5FF890 4C60BE86 ~~ +Po 41929 18504 0 15 4C5FF890 4C5D7AFE ~~ Li 0402 -Sc 4C60BE86 +Sc 4C5D7AFE AR /4C4320F3/4C5D7AFE Op 0 0 0 At SMD @@ -6612,21 +6463,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "N-000350" +Ne 120 "N-000345" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 52559 22835 0 15 4C5FF890 4C60BE88 ~~ +Po 52559 22835 0 15 4C5FF890 4C5D7ECF ~~ Li 0402 -Sc 4C60BE88 +Sc 4C5D7ECF AR /4C4320F3/4C5D7ECF Op 0 0 0 At SMD @@ -6640,21 +6491,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000354" +Ne 123 "N-000338" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51575 22835 0 15 4C5FF890 4C60BE8A ~~ +Po 51575 22835 0 15 4C5FF890 4C5D7F39 ~~ Li 0402 -Sc 4C60BE8A +Sc 4C5D7F39 AR /4C4320F3/4C5D7F39 Op 0 0 0 At SMD @@ -6668,21 +6519,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_MDIO" +Ne 20 "/FPGA_Spartan6/ETH_MDIO" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 66232 24701 1800 15 4C5FF890 4C60BE8C ~~ +Po 66232 24701 1800 15 4C5FF890 4C5F2D1E ~~ Li 0402 -Sc 4C60BE8C +Sc 4C5F2D1E AR /4C5F1EDC/4C5F2D1E Op 0 0 0 At SMD @@ -6696,21 +6547,21 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000367" +Ne 138 "N-000363" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 50787 26969 0 15 4C5FF890 4C60BE8E ~~ +Po 50787 26969 0 15 4C5FF890 4C5D7DCB ~~ Li 0402 -Sc 4C60BE8E +Sc 4C5D7DCB AR /4C4320F3/4C5D7DCB Op 0 0 0 At SMD @@ -6724,21 +6575,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "N-000355" +Ne 131 "N-000347" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 55709 23425 0 15 4C5FF890 4C60BE90 ~~ +Po 55709 23425 0 15 4C5FF890 4C5D7E43 ~~ Li 0402 -Sc 4C60BE90 +Sc 4C5D7E43 AR /4C4320F3/4C5D7E43 Op 0 0 0 At SMD @@ -6752,21 +6603,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 56000 27000 0 15 4C5FF890 4C60BE92 ~~ +Po 56000 27000 0 15 4C5FF890 4C5D7E41 ~~ Li 0402 -Sc 4C60BE92 +Sc 4C5D7E41 AR /4C4320F3/4C5D7E41 Op 0 0 0 At SMD @@ -6780,21 +6631,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 56000 24500 0 15 4C5FF890 4C60BE94 ~~ +Po 56000 24500 0 15 4C5FF890 4C5D8114 ~~ Li 0402 -Sc 4C60BE94 +Sc 4C5D8114 AR /4C4320F3/4C5D8114 Op 0 0 0 At SMD @@ -6808,21 +6659,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 119 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000360" +Ne 139 "N-000349" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 56000 24000 0 15 4C5FF890 4C60BE96 ~~ +Po 56000 24000 0 15 4C5FF890 4C5D7FA7 ~~ Li 0402 -Sc 4C60BE96 +Sc 4C5D7FA7 AR /4C4320F3/4C5D7FA7 Op 0 0 0 At SMD @@ -6836,21 +6687,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Ethernet_Phy/ETH_A3.3V" +Ne 122 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 48425 23622 0 15 4C5FF890 4C60BE98 ~~ +Po 48425 23622 0 15 4C5FF890 4C5D8104 ~~ Li 0402 -Sc 4C60BE98 +Sc 4C5D8104 AR /4C4320F3/4C5D8104 Op 0 0 0 At SMD @@ -6864,21 +6715,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A1.8V" +Ne 126 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000360" +Ne 139 "N-000349" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 56890 22835 0 15 4C5FF890 4C60BE9A ~~ +Po 56890 22835 0 15 4C5FF890 4C5D7FA3 ~~ Li 0402 -Sc 4C60BE9A +Sc 4C5D7FA3 AR /4C4320F3/4C5D7FA3 Op 0 0 0 At SMD @@ -6892,21 +6743,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51000 22000 1800 15 4C5FF890 4C60BE9C ~~ +Po 51000 22000 1800 15 4C5FF890 4C5D80F0 ~~ Li 0402 -Sc 4C60BE9C +Sc 4C5D80F0 AR /4C4320F3/4C5D80F0 Op 0 0 0 At SMD @@ -6920,21 +6771,21 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 134 "N-000356" +Ne 140 "N-000348" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000360" +Ne 139 "N-000349" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 50000 24016 0 15 4C5FF890 4C60BE9E ~~ +Po 50000 24016 0 15 4C5FF890 4C5D7FA1 ~~ Li 0402 -Sc 4C60BE9E +Sc 4C5D7FA1 AR /4C4320F3/4C5D7FA1 Op 0 0 0 At SMD @@ -6948,21 +6799,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51772 27756 0 15 4C5FF890 4C60BEA0 ~~ +Po 51772 27756 0 15 4C5FF890 4C5D80ED ~~ Li 0402 -Sc 4C60BEA0 +Sc 4C5D80ED AR /4C4320F3/4C5D80ED Op 0 0 0 At SMD @@ -6976,21 +6827,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/Ethernet_Phy/ETH_1.8V" +Ne 129 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0603 -Po 60327 21354 1800 15 4C5FF890 4C60BEA1 ~~ +Po 60327 21354 1800 15 4C5FF890 4C5F2CA3 ~~ Li 0603 -Sc 4C60BEA1 +Sc 4C5F2CA3 AR /4C5F1EDC/4C5F2CA3 Op 0 0 0 At SMD @@ -7004,21 +6855,21 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 141 "N-000368" +Ne 134 "N-000360" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 58555 12496 1800 15 4C5FF890 4C60BEA3 ~~ +Po 58555 12496 1800 15 4C5FF890 4C5F2CA7 ~~ Li 0603 -Sc 4C60BEA3 +Sc 4C5F2CA7 AR /4C5F1EDC/4C5F2CA7 Op 0 0 0 At SMD @@ -7032,21 +6883,21 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 139 "N-000362" +Ne 135 "N-000361" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 50000 22500 0 15 4C5FF890 4C60BEA5 ~~ +Po 50000 22500 0 15 4C5FF890 4C5D810A ~~ Li 0603 -Sc 4C60BEA5 +Sc 4C5D810A AR /4C4320F3/4C5D810A Op 0 0 0 At SMD @@ -7060,21 +6911,21 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A1.8V" +Ne 126 "/Ethernet_Phy/ETH_A1.8V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 119 "/Ethernet_Phy/ETH_PLL1.8V" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 50000 22000 0 15 4C5FF890 4C60BEA7 ~~ +Po 50000 22000 0 15 4C5FF890 4C5D7FB7 ~~ Li 0603 -Sc 4C60BEA7 +Sc 4C5D7FB7 AR /4C4320F3/4C5D7FB7 Op 0 0 0 At SMD @@ -7088,21 +6939,21 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Ethernet_Phy/ETH_A3.3V" +Ne 122 "/Ethernet_Phy/ETH_A3.3V" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 56087 25394 0 15 4C5FF890 4C60BEA9 ~~ +Po 56087 25394 0 15 4C5FF890 4C5D80F3 ~~ Li 0603 -Sc 4C60BEA9 +Sc 4C5D80F3 AR /4C4320F3/4C5D80F3 Op 0 0 0 At SMD @@ -7116,21 +6967,21 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "N-000356" +Ne 140 "N-000348" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A1.8V" +Ne 126 "/Ethernet_Phy/ETH_A1.8V" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 64067 24504 1800 15 4C5FF890 4C60BEAB ~~ +Po 64067 24504 1800 15 4C5FF890 4C5F2039 ~~ Li 0603 -Sc 4C60BEAB +Sc 4C5F2039 AR /4C5F1EDC/4C5F2039 Op 0 0 0 At SMD @@ -7144,21 +6995,21 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 64067 25488 1800 15 4C5FF890 4C60BEAD ~~ +Po 64067 25488 1800 15 4C5FF890 4C5F2037 ~~ Li 0603 -Sc 4C60BEAD +Sc 4C5F2037 AR /4C5F1EDC/4C5F2037 Op 0 0 0 At SMD @@ -7172,21 +7023,21 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 64067 23126 1800 15 4C5FF890 4C60BEAF ~~ +Po 64067 23126 1800 15 4C5FF890 4C5F2033 ~~ Li 0603 -Sc 4C60BEAF +Sc 4C5F2033 AR /4C5F1EDC/4C5F2033 Op 0 0 0 At SMD @@ -7200,21 +7051,21 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 63083 18402 1800 15 4C5FF890 4C60BEB1 ~~ +Po 63083 18402 1800 15 4C5FF890 4C5D7FA5 ~~ Li 0603 -Sc 4C60BEB1 +Sc 4C5D7FA5 AR /4C4320F3/4C5D7FA5 Op 0 0 0 At SMD @@ -7228,21 +7079,21 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Ethernet_Phy/ETH_A3.3V" +Ne 122 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 50197 25787 0 15 4C5FF890 4C60BEB3 ~~ +Po 50197 25787 0 15 4C5FF890 4C5D7F9F ~~ Li 0603 -Sc 4C60BEB3 +Sc 4C5D7F9F AR /4C4320F3/4C5D7F9F Op 0 0 0 At SMD @@ -7256,21 +7107,21 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "3.3V" +Ne 118 "N-000069" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 1210 -Po 72138 25291 1800 15 4C5FF890 4C60C35F ~~ +Po 72138 25291 1800 15 4C5FF890 4C5F2B55 ~~ Li 1210 -Sc 4C60C35F +Sc 4C5F2B55 AR /4C5F1EDC/4C5F2B55 Op 0 0 0 At SMD @@ -7284,7 +7135,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 138 "N-000361" +Ne 141 "N-000362" Po -570 0 $EndPAD $PAD @@ -7296,9 +7147,9 @@ Po 570 0 $EndPAD $EndMODULE 1210 $MODULE USB-48204 -Po 64067 13496 1800 15 4C5F28A8 4C60C360 ~~ +Po 64067 13496 1800 15 4C5F28A8 4C5F23DD ~~ Li USB-48204 -Sc 4C60C360 +Sc 4C5F23DD AR /4C5F1EDC/4C5F23DD Op 0 0 0 T0 120 -3162 157 157 1800 20 N V 21 N"J5" @@ -7317,63 +7168,63 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 138 "N-000361" +Ne 141 "N-000362" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 141 "N-000368" +Ne 134 "N-000360" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 139 "N-000362" +Ne 135 "N-000361" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 139 "N-000362" +Ne 135 "N-000361" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 140 "N-000367" +Ne 138 "N-000363" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 140 "N-000367" +Ne 138 "N-000363" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 140 "N-000367" +Ne 138 "N-000363" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 140 "N-000367" +Ne 138 "N-000363" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 $MODULE 0402 -Po 45000 29500 0 15 4C5FF890 4C61CD11 ~~ +Po 45000 29500 0 15 4C5FF890 4C61CC73 ~~ Li 0402 -Sc 4C61CD11 +Sc 4C61CC73 AR /4C421DD3/4C61CC73 Op 0 0 0 At SMD @@ -7387,21 +7238,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "N-000045" +Ne 137 "N-000046" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46000 29000 0 15 4C5FF890 4C61CD13 ~~ +Po 46000 29000 0 15 4C5FF890 4C61CC96 ~~ Li 0402 -Sc 4C61CD13 +Sc 4C61CC96 AR /4C421DD3/4C61CC96 Op 0 0 0 At SMD @@ -7415,21 +7266,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "N-000045" +Ne 137 "N-000046" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "N-000047" +Ne 142 "N-000045" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 63000 28500 0 15 4C5FF890 4C61CD15 ~~ +Po 63000 28500 0 15 4C5FF890 4C61CCE2 ~~ Li 0402 -Sc 4C61CD15 +Sc 4C61CCE2 AR /4C421DD3/4C61CCE2 Op 0 0 0 At SMD @@ -7443,21 +7294,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "N-000044" +Ne 136 "N-000047" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000043" +Ne 143 "N-000048" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 64000 28500 0 15 4C5FF890 4C61CD17 ~~ +Po 64000 28500 0 15 4C5FF890 4C61CCE3 ~~ Li 0402 -Sc 4C61CD17 +Sc 4C61CCE3 AR /4C421DD3/4C61CCE3 Op 0 0 0 At SMD @@ -7471,21 +7322,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "N-000044" +Ne 136 "N-000047" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 45000 34500 0 15 4C5FF890 4C61D013 ~~ +Po 45000 34500 0 15 4C5FF890 4C61CD4A ~~ Li 0402 -Sc 4C61D013 +Sc 4C61CD4A AR /4C421DD3/4C61CD4A Op 0 0 0 At SMD @@ -7499,21 +7350,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "N-000045" +Ne 137 "N-000046" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 45000 33500 0 15 4C5FF890 4C61D015 ~~ +Po 45000 33500 0 15 4C5FF890 4C61CDB5 ~~ Li 0402 -Sc 4C61D015 +Sc 4C61CDB5 AR /4C421DD3/4C61CDB5 Op 0 0 0 At SMD @@ -7527,21 +7378,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "N-000045" +Ne 137 "N-000046" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "N-000047" +Ne 142 "N-000045" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 65000 29000 0 15 4C5FF890 4C61D017 ~~ +Po 65000 29000 0 15 4C5FF890 4C61CE31 ~~ Li 0402 -Sc 4C61D017 +Sc 4C61CE31 AR /4C421DD3/4C61CE31 Op 0 0 0 At SMD @@ -7555,21 +7406,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "N-000044" +Ne 136 "N-000047" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 45500 37000 0 15 4C5FF890 4C61D019 ~~ +Po 45500 37000 0 15 4C5FF890 4C61CEB9 ~~ Li 0402 -Sc 4C61D019 +Sc 4C61CEB9 AR /4C421DD3/4C61CEB9 Op 0 0 0 At SMD @@ -7583,21 +7434,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46000 35000 0 15 4C5FF890 4C61D01B ~~ +Po 46000 35000 0 15 4C5FF890 4C61CEF7 ~~ Li 0402 -Sc 4C61D01B +Sc 4C61CEF7 AR /4C421DD3/4C61CEF7 Op 0 0 0 At SMD @@ -7611,21 +7462,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46000 30000 0 15 4C5FF890 4C61D01D ~~ +Po 46000 30000 0 15 4C5FF890 4C61CF16 ~~ Li 0402 -Sc 4C61D01D +Sc 4C61CF16 AR /4C421DD3/4C61CF16 Op 0 0 0 At SMD @@ -7639,21 +7490,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46000 32000 0 15 4C5FF890 4C61D01F ~~ +Po 46000 32000 0 15 4C5FF890 4C61CF17 ~~ Li 0402 -Sc 4C61D01F +Sc 4C61CF17 AR /4C421DD3/4C61CF17 Op 0 0 0 At SMD @@ -7667,21 +7518,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46000 33000 0 15 4C5FF890 4C61D021 ~~ +Po 46000 33000 0 15 4C5FF890 4C61CF27 ~~ Li 0402 -Sc 4C61D021 +Sc 4C61CF27 AR /4C421DD3/4C61CF27 Op 0 0 0 At SMD @@ -7695,21 +7546,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67000 36500 0 15 4C5FF890 4C61D023 ~~ +Po 67000 36500 0 15 4C5FF890 4C61CFA1 ~~ Li 0402 -Sc 4C61D023 +Sc 4C61CFA1 AR /4C421DD3/4C61CFA1 Op 0 0 0 At SMD @@ -7723,21 +7574,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67500 34000 0 15 4C5FF890 4C61D025 ~~ +Po 67500 34000 0 15 4C5FF890 4C61CFA2 ~~ Li 0402 -Sc 4C61D025 +Sc 4C61CFA2 AR /4C421DD3/4C61CFA2 Op 0 0 0 At SMD @@ -7751,21 +7602,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67500 35000 0 15 4C5FF890 4C61D027 ~~ +Po 67500 35000 0 15 4C5FF890 4C61CFA3 ~~ Li 0402 -Sc 4C61D027 +Sc 4C61CFA3 AR /4C421DD3/4C61CFA3 Op 0 0 0 At SMD @@ -7779,21 +7630,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67000 35500 0 15 4C5FF890 4C61D029 ~~ +Po 67000 35500 0 15 4C5FF890 4C61CFA4 ~~ Li 0402 -Sc 4C61D029 +Sc 4C61CFA4 AR /4C421DD3/4C61CFA4 Op 0 0 0 At SMD @@ -7807,21 +7658,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67500 32500 0 15 4C5FF890 4C61D02B ~~ +Po 67500 32500 0 15 4C5FF890 4C61CFA5 ~~ Li 0402 -Sc 4C61D02B +Sc 4C61CFA5 AR /4C421DD3/4C61CFA5 Op 0 0 0 At SMD @@ -7835,21 +7686,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0603 -Po 46000 31000 0 15 4C5FF890 4C61D02C ~~ +Po 46000 31000 0 15 4C5FF890 4C61CF2F ~~ Li 0603 -Sc 4C61D02C +Sc 4C61CF2F AR /4C421DD3/4C61CF2F Op 0 0 0 At SMD @@ -7863,21 +7714,21 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 66000 27500 0 15 4C5FF890 4C61D02E ~~ +Po 66000 27500 0 15 4C5FF890 4C61CFA0 ~~ Li 0603 -Sc 4C61D02E +Sc 4C61CFA0 AR /4C421DD3/4C61CFA0 Op 0 0 0 At SMD @@ -7891,21 +7742,21 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0402 -Po 63000 29000 0 15 4C5FF890 4C61D035 ~~ +Po 63000 29000 0 15 4C5FF890 4C61CE30 ~~ Li 0402 -Sc 4C61D035 +Sc 4C61CE30 AR /4C421DD3/4C61CE30 Op 0 0 0 At SMD @@ -7919,21 +7770,21 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "N-000044" +Ne 136 "N-000047" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000043" +Ne 143 "N-000048" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 1206 -Po 49500 39000 0 15 4C5FF890 4C61D1B6 ~~ +Po 49500 39000 0 15 4C5FF890 4C61D151 ~~ Li 1206 -Sc 4C61D1B6 +Sc 4C61D151 AR /4C421DD3/4C61D151 Op 0 0 0 At SMD @@ -7947,21 +7798,21 @@ $PAD Sh "1" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 64000 39000 0 15 4C5FF890 4C61D46D ~~ +Po 64000 39000 0 15 4C5FF890 4C61D1D4 ~~ Li 1206 -Sc 4C61D46D +Sc 4C61D1D4 AR /4C421DD3/4C61D1D4 Op 0 0 0 At SMD @@ -7975,14 +7826,14 @@ $PAD Sh "1" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "+2.5V" +Ne 19 "+2.5V" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "GND" +Ne 1 "GND" Po 570 0 $EndPAD $EndMODULE 1206 diff --git a/kicad/xue-rnc/xue-rnc.cache.dcm b/kicad/xue-rnc/xue-rnc.cache.dcm index 532a09b..98ba4c4 100644 --- a/kicad/xue-rnc/xue-rnc.cache.dcm +++ b/kicad/xue-rnc/xue-rnc.cache.dcm @@ -1,4 +1,4 @@ -EESchema-DOCLIB Version 2.0 Mon 09 Aug 2010 07:11:00 PM COT +EESchema-DOCLIB Version 2.0 Tue 10 Aug 2010 09:23:11 PM COT # $CMP C D Condensateur non polarise diff --git a/kicad/xue-rnc/xue-rnc.cache.lib b/kicad/xue-rnc/xue-rnc.cache.lib index 0ceefc3..3097eca 100644 --- a/kicad/xue-rnc/xue-rnc.cache.lib +++ b/kicad/xue-rnc/xue-rnc.cache.lib @@ -1,6 +1,44 @@ -EESchema-LIBRARY Version Mon 09 Aug 2010 07:11:00 PM COT +EESchema-LIBRARY Version Tue 10 Aug 2010 09:23:11 PM COT # # +# +1.2V +# +DEF +1.2V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 140 20 H I C CNN +F1 "+1.2V" 0 110 30 H V C CNN +DRAW +P 3 0 0 0 0 0 0 40 0 40 N +C 0 60 20 0 1 0 N +X +1.2V 1 0 0 0 U 20 20 0 0 W N +ENDDRAW +ENDDEF +# +# +2.5V +# +DEF +2.5V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -50 20 H I C CNN +F1 "+2.5V" 0 100 30 H V C CNN +ALIAS +2,5V +DRAW +P 3 0 1 0 0 0 0 40 0 40 N +C 0 60 20 0 1 0 N +X +2.5V 1 0 0 0 U 20 30 0 0 W N +ENDDRAW +ENDDEF +# +# +3.3V +# +DEF +3.3V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -40 30 H I C CNN +F1 "+3.3V" 0 110 30 H V C CNN +ALIAS +3,3V +DRAW +P 3 0 1 0 0 0 0 40 0 40 N +C 0 60 20 0 1 0 N +X +3.3V 1 0 0 0 U 30 30 0 0 W N +ENDDRAW +ENDDEF +# # C # DEF C C 0 10 N Y 1 F N @@ -19,6 +57,25 @@ X ~ 2 0 -200 170 U 40 40 1 1 P ENDDRAW ENDDEF # +# Cap +# +DEF Cap C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "Cap" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +S -50 -25 -50 -25 0 1 0 N +S -50 -25 50 -25 0 1 20 N +S -50 25 50 25 0 1 20 N +X ~ 1 0 100 65 D 40 40 1 1 P +X ~ 2 0 -100 65 U 40 40 1 1 P +ENDDRAW +ENDDEF +# # GND # DEF ~GND #PWR 0 0 Y Y 1 F P @@ -221,73 +278,79 @@ X ~ 2 -300 0 150 R 30 30 1 1 B ENDDRAW ENDDEF # -# MT46V32M16FN +# MT46V32M16TG # -DEF MT46V32M16FN U 0 40 Y Y 1 F N +DEF MT46V32M16TG U 0 40 Y Y 1 F N F0 "U" 0 100 70 H V C CNN -F1 "MT46V32M16FN" 0 -100 70 H V C CNN +F1 "MT46V32M16TG" 0 -100 70 H V C CNN DRAW -S -700 -1200 700 1200 1 1 0 f -X VDD A7 -400 1500 300 D 60 60 1 1 P -X VDD F8 -300 1500 300 D 60 60 1 1 P -X VDD M7 -200 1500 300 D 60 60 1 1 P -X VDDQ A9 -100 1500 300 D 60 60 1 1 P -X VDDQ B2 0 1500 300 D 60 60 1 1 P -X VDDQ C8 100 1500 300 D 60 60 1 1 P -X VDDQ D2 200 1500 300 D 60 60 1 1 P -X VDDQ E8 300 1500 300 D 60 60 1 1 P -X DQ2 B7 1000 -1100 300 L 60 60 1 1 P -X DQ3 C9 1000 -1000 300 L 60 60 1 1 P -X DQ4 C7 1000 -900 300 L 60 60 1 1 P -X DQ5 D9 1000 -800 300 L 60 60 1 1 P -X DQ6 D7 1000 -700 300 L 60 60 1 1 P -X DQ7 E9 1000 -600 300 L 60 60 1 1 P -X DQ8 E1 1000 -500 300 L 60 60 1 1 P -X DQ9 D3 1000 -400 300 L 60 60 1 1 P -X DQ10 D1 1000 -300 300 L 60 60 1 1 P -X DQ11 C3 1000 -200 300 L 60 60 1 1 P -X DQ12 C1 1000 -100 300 L 60 60 1 1 P -X DQ13 B3 1000 0 300 L 60 60 1 1 P -X DQ14 B1 1000 100 300 L 60 60 1 1 P -X DQ15 A2 1000 200 300 L 60 60 1 1 P -X LDM F7 1000 300 300 L 60 60 1 1 P -X LDQS E7 1000 400 300 L 60 60 1 1 P -X NC F9 1000 500 300 L 60 60 1 1 P -X RAS_ H7 1000 600 300 L 60 60 1 1 P -X UDM F3 1000 700 300 L 60 60 1 1 P -X UDQS E3 1000 800 300 L 60 60 1 1 P -X VREF F1 1000 900 300 L 60 60 1 1 P -X WE_ G7 1000 1000 300 L 60 60 1 1 P -X DQ1 B9 -1000 -1000 300 R 60 60 1 1 P -X DQ0 A8 -1000 -900 300 R 60 60 1 1 P -X CS_ H8 -1000 -800 300 R 60 60 1 1 P -X CLK_ G3 -1000 -700 300 R 60 60 1 1 P -X CLK G2 -1000 -600 300 R 60 60 1 1 P -X CKE H3 -1000 -500 300 R 60 60 1 1 P -X CAS_ G8 -1000 -400 300 R 60 60 1 1 P -X BA1 J7 -1000 -300 300 R 60 60 1 1 P -X BA0 J8 -1000 -200 300 R 60 60 1 1 P -X A12 H2 -1000 -100 300 R 60 60 1 1 P -X A11 J2 -1000 0 300 R 60 60 1 1 P -X A10 K8 -1000 100 300 R 60 60 1 1 P -X A9 J3 -1000 200 300 R 60 60 1 1 P -X A8 K2 -1000 300 300 R 60 60 1 1 P -X A7 K3 -1000 400 300 R 60 60 1 1 P -X A6 L2 -1000 500 300 R 60 60 1 1 P -X A5 L3 -1000 600 300 R 60 60 1 1 P -X A4 M2 -1000 700 300 R 60 60 1 1 P -X A3 M8 -1000 800 300 R 60 60 1 1 P -X A2 L7 -1000 900 300 R 60 60 1 1 P -X A1 L8 -1000 1000 300 R 60 60 1 1 P -X A0 K7 -1000 1100 300 R 60 60 1 1 P -X VSS A3 -400 -1500 300 U 60 60 1 1 P -X VSS F2 -300 -1500 300 U 60 60 1 1 P -X VSS M3 -200 -1500 300 U 60 60 1 1 P -X VSSQ A1 -100 -1500 300 U 60 60 1 1 P -X VSSQ B8 0 -1500 300 U 60 60 1 1 P -X VSSQ C2 100 -1500 300 U 60 60 1 1 P -X VSSQ D8 200 -1500 300 U 60 60 1 1 P -X VSSQ E2 300 -1500 300 U 60 60 1 1 P +S -800 -1300 800 1300 1 1 0 f +X VDD 1 -400 1600 300 D 60 60 1 1 P +X VDD 18 -300 1600 300 D 60 60 1 1 P +X VDD 33 -200 1600 300 D 60 60 1 1 P +X VDDQ 3 -100 1600 300 D 60 60 1 1 P +X VDDQ 9 0 1600 300 D 60 60 1 1 P +X VDDQ 15 100 1600 300 D 60 60 1 1 P +X VDDQ 55 200 1600 300 D 60 60 1 1 P +X VDDQ 61 300 1600 300 D 60 60 1 1 P +X DQ5 10 1100 -1200 300 L 60 60 1 1 P +X DQ6 11 1100 -1100 300 L 60 60 1 1 P +X DQ7 13 1100 -1000 300 L 60 60 1 1 P +X DQ8 54 1100 -900 300 L 60 60 1 1 P +X DQ9 56 1100 -800 300 L 60 60 1 1 P +X DQ10 57 1100 -700 300 L 60 60 1 1 P +X DQ11 59 1100 -600 300 L 60 60 1 1 P +X DQ12 60 1100 -500 300 L 60 60 1 1 P +X DQ13 62 1100 -400 300 L 60 60 1 1 P +X DQ14 63 1100 -300 300 L 60 60 1 1 P +X DQ15 65 1100 -200 300 L 60 60 1 1 P +X LDM 20 1100 -100 300 L 60 60 1 1 P +X LDQS 16 1100 0 300 L 60 60 1 1 P +X NC 14 1100 100 300 L 60 60 1 1 P +X NC 17 1100 200 300 L 60 60 1 1 P +X NC 19 1100 300 300 L 60 60 1 1 P +X NC 25 1100 400 300 L 60 60 1 1 P +X NC 43 1100 500 300 L 60 60 1 1 P +X NC 50 1100 600 300 L 60 60 1 1 P +X NC 53 1100 700 300 L 60 60 1 1 P +X RAS# 23 1100 800 300 L 60 60 1 1 I I +X UDM 47 1100 900 300 L 60 60 1 1 P +X UDQS 51 1100 1000 300 L 60 60 1 1 P +X VREF 49 1100 1100 300 L 60 60 1 1 P +X WE# 21 1100 1200 300 L 60 60 1 1 I I +X DQ4 8 -1100 -1200 300 R 60 60 1 1 P +X DQ3 7 -1100 -1100 300 R 60 60 1 1 P +X DQ2 5 -1100 -1000 300 R 60 60 1 1 P +X DQ1 4 -1100 -900 300 R 60 60 1 1 P +X DQ0 2 -1100 -800 300 R 60 60 1 1 P +X CS# 24 -1100 -700 300 R 60 60 1 1 I I +X CKE 44 -1100 -600 300 R 60 60 1 1 P +X CK# 46 -1100 -500 300 R 60 60 1 1 I I +X CK 45 -1100 -400 300 R 60 60 1 1 P +X CAS# 22 -1100 -300 300 R 60 60 1 1 I I +X BA1 27 -1100 -200 300 R 60 60 1 1 P +X BA0 26 -1100 -100 300 R 60 60 1 1 P +X A12 42 -1100 0 300 R 60 60 1 1 P +X A11 41 -1100 100 300 R 60 60 1 1 P +X A10_AP 28 -1100 200 300 R 60 60 1 1 P +X A9 40 -1100 300 300 R 60 60 1 1 P +X A8 39 -1100 400 300 R 60 60 1 1 P +X A7 38 -1100 500 300 R 60 60 1 1 P +X A6 37 -1100 600 300 R 60 60 1 1 P +X A5 36 -1100 700 300 R 60 60 1 1 P +X A4 35 -1100 800 300 R 60 60 1 1 P +X A3 32 -1100 900 300 R 60 60 1 1 P +X A2 31 -1100 1000 300 R 60 60 1 1 P +X A1 30 -1100 1100 300 R 60 60 1 1 P +X A0 29 -1100 1200 300 R 60 60 1 1 P +X VSS 34 -400 -1600 300 U 60 60 1 1 P +X VSS 48 -300 -1600 300 U 60 60 1 1 P +X VSS 66 -200 -1600 300 U 60 60 1 1 P +X VSSQ 6 -100 -1600 300 U 60 60 1 1 P +X VSSQ 12 0 -1600 300 U 60 60 1 1 P +X VSSQ 52 100 -1600 300 U 60 60 1 1 P +X VSSQ 58 200 -1600 300 U 60 60 1 1 P +X VSSQ 64 300 -1600 300 U 60 60 1 1 P ENDDRAW ENDDEF # diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 4c4c197..c9dadbc 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,545 +1,545 @@ -# EESchema Netlist Version 1.1 created Tue 10 Aug 2010 06:06:19 PM COT +# EESchema Netlist Version 1.1 created Tue 10 Aug 2010 09:23:17 PM COT ( + ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} + ( 1 N-000361 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} + ( 1 N-000361 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000359 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000358 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} + ( 1 N-000360 ) + ( 2 ? ) + ) + ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} + ( S1 N-000361 ) + ( S2 N-000361 ) + ( S3 N-000361 ) + ( S4 N-000361 ) + ( 1 N-000360 ) + ( 2 N-000358 ) + ( 3 N-000359 ) + ( 4 GND ) + ) + ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} + ( 1 N-000069 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} + ( 1 N-000069 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} + ( 1 N-000069 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} + ( 1 N-000069 ) + ( 2 /FPGA_Spartan6/USBA_SPD ) + ( 3 /FPGA_Spartan6/USBA_RCV ) + ( 4 /FPGA_Spartan6/USBA_VP ) + ( 5 /FPGA_Spartan6/USBA_VM ) + ( 7 GND ) + ( 8 GND ) + ( 9 /FPGA_Spartan6/USBA_OE_N ) + ( 10 N-000358 ) + ( 11 N-000359 ) + ( 12 N-000069 ) + ( 14 N-000069 ) + ) ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} - ( P7 ? ) - ( N7 ? ) - ( M7 ? ) - ( L7 N-000098 ) + ( H9 +2.5V ) + ( U11 +2.5V ) + ( F11 +2.5V ) + ( R6 +2.5V ) + ( M15 +2.5V ) + ( V6 +2.5V ) + ( G12 +2.5V ) + ( H15 +2.5V ) + ( D16 +2.5V ) + ( K15 +2.5V ) + ( R12 +2.5V ) + ( N8 +2.5V ) + ( R10 +2.5V ) + ( L8 +2.5V ) + ( N10 +1.2V ) + ( P11 +1.2V ) + ( P13 +1.2V ) + ( P9 +1.2V ) + ( R14 +1.2V ) + ( N12 +1.2V ) + ( J10 +1.2V ) + ( J12 +1.2V ) + ( J14 +1.2V ) + ( J8 +1.2V ) + ( K11 +1.2V ) + ( K13 +1.2V ) + ( K9 +1.2V ) + ( L10 +1.2V ) + ( L12 +1.2V ) + ( L14 +1.2V ) + ( M11 +1.2V ) + ( M13 +1.2V ) + ( M9 +1.2V ) + ( N14 +1.2V ) + ( G13 ? ) + ( G8 ? ) + ( G9 ? ) + ( H10 ? ) + ( H11 ? ) + ( H12 ? ) + ( H13 ? ) + ( H14 ? ) + ( P16 ? ) + ( D13 ? ) + ( AA1 ? ) + ( N15 ? ) + ( G15 ? ) + ( E18 ? ) + ( A19 ? ) + ( C18 ? ) + ( G11 ? ) + ( F9 ? ) + ( F8 ? ) + ( F15 ? ) + ( F14 ? ) + ( F13 ? ) + ( F12 ? ) + ( F10 ? ) + ( E8 ? ) + ( E14 ? ) + ( E12 ? ) + ( E10 ? ) + ( D12 ? ) + ( P15 ? ) + ( R17 ? ) + ( Y22 ? ) + ( P10 GND ) + ( V10 GND ) + ( M10 GND ) + ( K10 GND ) + ( L13 GND ) + ( A1 GND ) + ( N13 GND ) + ( A22 GND ) + ( R5 GND ) + ( AA13 GND ) + ( W19 GND ) + ( AA17 GND ) + ( K14 GND ) + ( AA5 GND ) + ( L5 GND ) + ( AA9 GND ) + ( M14 GND ) + ( AB1 GND ) + ( N2 GND ) + ( AB22 GND ) + ( P14 GND ) + ( B13 GND ) + ( U21 GND ) + ( B17 GND ) + ( V4 GND ) + ( B5 GND ) + ( J9 GND ) + ( B9 GND ) + ( K12 ? ) + ( D18 GND ) + ( L11 GND ) + ( D4 GND ) + ( L18 GND ) + ( E11 ? ) + ( L9 GND ) + ( E15 GND ) + ( M12 GND ) + ( E2 GND ) + ( N11 GND ) + ( E21 GND ) + ( N17 GND ) + ( E7 GND ) + ( N21 GND ) + ( G18 GND ) + ( P12 GND ) + ( G5 GND ) + ( R18 GND ) + ( H7 GND ) + ( U2 GND ) + ( J11 GND ) + ( U7 GND ) + ( J13 GND ) + ( V14 GND ) + ( J15 GND ) + ( W16 GND ) + ( J2 GND ) + ( W7 GND ) + ( J21 GND ) + ( N9 GND ) + ( AA15 N-000101 ) + ( V16 N-000101 ) + ( T13 N-000101 ) + ( V8 N-000101 ) + ( V12 N-000101 ) + ( AA3 N-000101 ) + ( T9 N-000101 ) + ( AA19 N-000101 ) + ( AA11 N-000101 ) + ( W5 N-000101 ) + ( AA7 N-000101 ) + ( AA12 ? ) + ( AB12 ? ) + ( Y11 ? ) + ( AB11 ? ) + ( R11 ? ) + ( T11 ? ) + ( AA10 ? ) + ( AB10 ? ) + ( V11 ? ) + ( W11 ? ) + ( Y9 ? ) + ( AB9 ? ) + ( W10 ? ) + ( Y10 ? ) + ( AA8 ? ) + ( AB8 ? ) + ( W8 ? ) + ( V7 ? ) + ( W9 ? ) + ( Y8 ? ) + ( Y7 ? ) + ( AB7 ? ) + ( AA6 ? ) + ( AB6 ? ) + ( U9 ? ) + ( V9 ? ) + ( T8 ? ) + ( U8 ? ) + ( T10 ? ) + ( U10 ? ) + ( W6 ? ) + ( Y6 ? ) + ( Y5 ? ) + ( AB5 ? ) + ( AA4 ? ) + ( AB4 ? ) + ( Y3 ? ) + ( AB3 ? ) + ( R9 ? ) + ( R8 ? ) + ( T7 ? ) + ( R7 ? ) + ( W4 ? ) + ( Y4 ? ) + ( U6 ? ) + ( V5 ? ) + ( AA2 ? ) + ( AB2 ? ) + ( T6 ? ) + ( T5 ? ) + ( AB13 ? ) + ( Y13 ? ) + ( Y12 ? ) + ( W12 ? ) + ( R13 ? ) + ( T14 ? ) + ( U12 ? ) + ( T12 ? ) + ( AB15 ? ) + ( Y15 ? ) + ( Y14 ? ) + ( W14 ? ) + ( AB16 ? ) + ( AA16 ? ) + ( W13 ? ) + ( V13 ? ) + ( W15 ? ) + ( Y16 ? ) + ( AB14 ? ) + ( AA14 ? ) + ( AB17 ? ) + ( Y17 ? ) + ( AB18 ? ) + ( AA18 ? ) + ( V15 ? ) + ( U15 ? ) + ( U13 ? ) + ( U14 ? ) + ( W17 ? ) + ( V17 ? ) + ( R15 ? ) + ( R16 ? ) + ( V18 ? ) + ( V19 ? ) + ( U16 ? ) + ( U17 ? ) + ( T15 ? ) + ( T16 ? ) + ( Y18 ? ) + ( W18 ? ) + ( AB19 ? ) + ( Y19 ? ) + ( T17 ? ) + ( T18 ? ) + ( AB20 ? ) + ( AA20 ? ) + ( AB21 ? ) + ( AA21 ? ) + ( AA22 ? ) + ( W2 +2.5V ) + ( L2 +2.5V ) + ( L7 +2.5V ) + ( C2 +2.5V ) + ( N5 +2.5V ) + ( R2 +2.5V ) + ( U5 +2.5V ) + ( G2 +2.5V ) + ( F4 +2.5V ) + ( F6 +2.5V ) + ( J5 +2.5V ) + ( M3 /DDR_Banks/M0_UDM ) + ( L4 /DDR_Banks/M0_LDM ) + ( K5 /DDR_Banks/M0_RAS# ) + ( K4 /DDR_Banks/M0_CAS# ) + ( K3 /DDR_Banks/M0_A5 ) + ( J4 /DDR_Banks/M0_A6 ) + ( K6 /DDR_Banks/M0_A3 ) + ( J6 ? ) + ( H4 /DDR_Banks/M0_CLK ) + ( H3 /DDR_Banks/M0_CLK# ) + ( H2 /DDR_Banks/M0_A0 ) + ( H1 /DDR_Banks/M0_A1 ) + ( G3 /DDR_Banks/M0_BA0 ) + ( G1 /DDR_Banks/M0_BA1 ) + ( H6 /DDR_Banks/M0_A7 ) + ( H5 /DDR_Banks/M0_A2 ) + ( F2 /DDR_Banks/M0_WE# ) + ( F1 ? ) + ( G4 /DDR_Banks/M0_A10 ) + ( F3 /DDR_Banks/M0_A4 ) + ( E3 /DDR_Banks/M0_A8 ) + ( E1 /DDR_Banks/M0_A9 ) + ( D2 /DDR_Banks/M0_CKE ) + ( D1 /DDR_Banks/M0_A12 ) + ( C3 ? ) + ( C1 /DDR_Banks/M0_A11 ) + ( G6 ? ) + ( F5 ? ) ( K7 ? ) + ( K8 ? ) + ( D5 ? ) + ( E4 ? ) ( J7 ? ) + ( H8 ? ) + ( B2 ? ) + ( B1 ? ) ( G7 ? ) ( F7 ? ) - ( P6 ? ) - ( N6 ? ) - ( M6 ? ) - ( L6 ? ) - ( K6 /FPGA_Spartan6/M0_A3 ) - ( J6 ? ) - ( H6 /FPGA_Spartan6/M0_A7 ) - ( G6 ? ) - ( F6 N-000098 ) - ( E6 ? ) - ( U5 N-000098 ) - ( P5 ? ) - ( N5 N-000098 ) - ( M5 ? ) - ( K5 /FPGA_Spartan6/M0_RAS# ) - ( J5 N-000098 ) - ( H5 /FPGA_Spartan6/M0_A2 ) - ( F5 ? ) - ( E5 ? ) - ( D5 ? ) - ( U4 ? ) - ( H21 /FPGA_Spartan6/M1_RAS# ) - ( G21 N-000099 ) - ( F21 /DDR_Banks/M1_A0 ) - ( D21 /FPGA_Spartan6/M1_CKE ) - ( C21 N-000099 ) - ( B21 ? ) - ( A21 ? ) - ( W20 ? ) - ( V20 ? ) - ( U20 /DDR_Banks/M1_DQ12 ) - ( T20 ? ) - ( R20 /FPGA_Spartan6/M1_DQ10 ) - ( P20 ? ) - ( N20 /DDR_Banks/M1_DQ0 ) - ( M20 /DDR_Banks/M1_UDM ) - ( L20 /FPGA_Spartan6/M1_LDQS ) - ( K20 /FPGA_Spartan6/M1_A5 ) - ( J20 /FPGA_Spartan6/M1_DQ4 ) - ( H20 /FPGA_Spartan6/M1_CLK ) - ( G20 /FPGA_Spartan6/M1_A3 ) - ( F20 /FPGA_Spartan6/M1_A4 ) - ( E20 /DDR_Banks/M1_A7 ) - ( D20 ? ) - ( C20 /FPGA_Spartan6/M1_A8 ) - ( B20 ? ) - ( A20 ? ) - ( P8 ? ) - ( M8 ? ) - ( K8 ? ) - ( H8 ? ) - ( B3 ? ) - ( W2 N-000098 ) - ( V2 /FPGA_Spartan6/M0_DQ14 ) - ( T2 /DDR_Banks/M0_UDQS ) - ( R2 N-000098 ) - ( P2 /FPGA_Spartan6/M0_DQ8 ) - ( M2 /DDR_Banks/M0_DQ2 ) - ( L2 N-000098 ) - ( K2 /FPGA_Spartan6/M0_DQ6 ) - ( H2 /FPGA_Spartan6/M0_A0 ) - ( G2 N-000098 ) - ( F2 /FPGA_Spartan6/M0_WE# ) - ( D2 /DDR_Banks/M0_CKE ) - ( C2 N-000098 ) - ( B2 ? ) - ( A2 ? ) - ( Y1 ? ) - ( W1 ? ) - ( V1 /DDR_Banks/M0_DQ15 ) - ( U1 /DDR_Banks/M0_DQ13 ) - ( T1 ? ) - ( R1 /FPGA_Spartan6/M0_DQ11 ) - ( P1 /FPGA_Spartan6/M0_DQ9 ) - ( N1 /FPGA_Spartan6/M0_DQ1 ) - ( M1 /DDR_Banks/M0_DQ3 ) - ( L1 ? ) - ( K1 /FPGA_Spartan6/M0_DQ7 ) - ( J1 /FPGA_Spartan6/M0_DQ5 ) - ( H1 /FPGA_Spartan6/M0_A1 ) - ( G1 /FPGA_Spartan6/M0_BA1 ) - ( T4 ? ) - ( R4 ? ) - ( P4 ? ) - ( N4 ? ) - ( M4 ? ) - ( L4 /FPGA_Spartan6/M0_LDM ) - ( K4 /FPGA_Spartan6/M0_CAS# ) - ( J4 /FPGA_Spartan6/M0_A6 ) - ( H4 /DDR_Banks/M0_CLK ) - ( G4 /FPGA_Spartan6/M0_A10 ) - ( F4 N-000098 ) - ( E4 ? ) - ( C4 ? ) - ( W3 ? ) - ( V3 ? ) - ( U3 /DDR_Banks/M0_DQ12 ) - ( T3 ? ) - ( R3 /FPGA_Spartan6/M0_DQ10 ) - ( P3 ? ) - ( N3 /FPGA_Spartan6/M0_DQ0 ) - ( M3 /FPGA_Spartan6/M0_UDM ) - ( L3 /FPGA_Spartan6/M0_LDQS ) - ( K3 /DDR_Banks/M0_A5 ) - ( J3 /FPGA_Spartan6/M0_DQ4 ) - ( H3 /DDR_Banks/M0_CLK# ) - ( G3 /FPGA_Spartan6/M0_BA0 ) - ( F3 /FPGA_Spartan6/M0_A4 ) - ( E3 /FPGA_Spartan6/M0_A8 ) ( D3 ? ) - ( C3 ? ) - ( G10 N-000100 ) - ( D10 /FPGA_Spartan6/ETH_TXD3 ) - ( C10 /Ethernet_Phy/ETH_TXC ) - ( B10 /Ethernet_Phy/ETH_RXC ) - ( A10 /FPGA_Spartan6/ETH_CLK ) - ( E9 N-000100 ) - ( D9 /FPGA_Spartan6/ETH_RXER ) - ( C9 /Ethernet_Phy/ETH_TXEN ) - ( A9 /FPGA_Spartan6/ETH_TXD0 ) - ( D8 /Ethernet_Phy/ETH_TXD2 ) - ( C8 /Ethernet_Phy/ETH_TXER ) - ( B8 /FPGA_Spartan6/ETH_RXD0 ) - ( A8 /Ethernet_Phy/ETH_RXDV ) - ( D7 /Ethernet_Phy/ETH_TXD1 ) - ( C7 /FPGA_Spartan6/ETH_RXD2 ) - ( B7 N-000100 ) - ( A7 /Ethernet_Phy/ETH_RXD1 ) - ( D6 /Ethernet_Phy/ETH_MDC ) - ( C6 /Ethernet_Phy/ETH_MDIO ) - ( B6 /FPGA_Spartan6/ETH_RESET_N ) - ( A6 /Ethernet_Phy/ETH_RXD3 ) - ( C5 ? ) - ( A5 /Ethernet_Phy/ETH_INT ) - ( B4 N-000100 ) - ( A4 ? ) - ( U19 ? ) - ( T19 ? ) - ( R19 ? ) - ( P19 ? ) + ( C4 ? ) + ( E5 ? ) + ( E6 ? ) + ( A2 ? ) + ( B3 ? ) + ( J1 /DDR_Banks/M0_DQ5 ) + ( J3 /DDR_Banks/M0_DQ4 ) + ( K1 /DDR_Banks/M0_DQ7 ) + ( K2 /DDR_Banks/M0_DQ6 ) + ( L1 ? ) + ( L3 /DDR_Banks/M0_LDQS ) + ( M1 /DDR_Banks/M0_DQ3 ) + ( M2 /DDR_Banks/M0_DQ2 ) + ( N1 /DDR_Banks/M0_DQ1 ) + ( N3 /DDR_Banks/M0_DQ0 ) + ( P1 /DDR_Banks/M0_DQ9 ) + ( P2 /DDR_Banks/M0_DQ8 ) + ( R1 /DDR_Banks/M0_DQ11 ) + ( R3 /DDR_Banks/M0_DQ10 ) + ( T1 ? ) + ( T2 /DDR_Banks/M0_UDQS ) + ( U1 /DDR_Banks/M0_DQ13 ) + ( U3 /DDR_Banks/M0_DQ12 ) + ( V1 /DDR_Banks/M0_DQ15 ) + ( V2 /DDR_Banks/M0_DQ14 ) + ( M4 ? ) + ( M5 ? ) + ( N4 ? ) + ( P3 ? ) + ( L6 ? ) + ( M6 ? ) + ( P4 ? ) + ( R4 ? ) + ( M8 ? ) + ( M7 ? ) + ( N7 ? ) + ( N6 ? ) + ( V3 ? ) + ( U4 ? ) + ( T3 ? ) + ( T4 ? ) + ( P5 ? ) + ( P6 ? ) + ( P7 ? ) + ( P8 ? ) + ( W1 ? ) + ( W3 ? ) + ( Y1 ? ) + ( W21 +2.5V ) + ( C21 +2.5V ) + ( G21 +2.5V ) + ( J18 +2.5V ) + ( L16 +2.5V ) + ( L21 +2.5V ) + ( N18 +2.5V ) + ( R21 +2.5V ) + ( U18 +2.5V ) + ( E19 +2.5V ) + ( L19 /DDR_Banks/M1_LDM ) + ( J20 /DDR_Banks/M1_DQ4 ) + ( J22 /DDR_Banks/M1_DQ5 ) + ( K21 /DDR_Banks/M1_DQ6 ) + ( K22 /DDR_Banks/M1_DQ7 ) + ( L20 /DDR_Banks/M1_LDQS ) + ( L22 ? ) + ( M21 /DDR_Banks/M1_DQ2 ) + ( M22 /DDR_Banks/M1_DQ3 ) + ( N20 /DDR_Banks/M1_DQ0 ) + ( N22 /DDR_Banks/M1_DQ1 ) + ( P21 /DDR_Banks/M1_DQ8 ) + ( P22 /DDR_Banks/M1_DQ9 ) + ( R20 /DDR_Banks/M1_DQ10 ) + ( R22 /DDR_Banks/M1_DQ11 ) + ( T21 /DDR_Banks/M1_UDQS ) + ( T22 ? ) + ( U20 /DDR_Banks/M1_DQ12 ) + ( U22 /DDR_Banks/M1_DQ13 ) + ( V21 /DDR_Banks/M1_DQ14 ) + ( V22 /DDR_Banks/M1_DQ15 ) + ( M19 ? ) ( N19 ? ) - ( B19 N-000100 ) - ( B18 ? ) - ( A18 ? ) - ( E17 N-000100 ) - ( D17 ? ) - ( C17 /FPGA_Spartan6/SD_CMD ) - ( A17 ? ) - ( E16 ? ) - ( C16 /Non_volatile_memories/SD_DAT1 ) - ( B16 /Non_volatile_memories/SD_DAT0 ) - ( A16 /FPGA_Spartan6/SD_CLK ) - ( D15 /Non_volatile_memories/SD_DAT2 ) - ( C15 ? ) - ( B15 N-000100 ) - ( A15 /FPGA_Spartan6/SD_DAT3 ) - ( G14 N-000100 ) + ( M16 ? ) + ( L15 ? ) + ( P19 ? ) + ( P20 ? ) + ( W20 ? ) + ( W22 ? ) + ( L17 ? ) + ( K18 ? ) + ( U19 ? ) + ( V20 ? ) + ( M17 ? ) + ( M18 ? ) + ( P17 ? ) + ( N16 ? ) + ( P18 ? ) + ( R19 ? ) + ( T19 ? ) + ( T20 ? ) + ( M20 /DDR_Banks/M1_UDM ) + ( H22 /DDR_Banks/M1_CAS# ) + ( H21 /DDR_Banks/M1_RAS# ) + ( K19 /DDR_Banks/M1_A6 ) + ( K20 /DDR_Banks/M1_A5 ) + ( G22 ? ) + ( G20 /DDR_Banks/M1_A3 ) + ( J19 /DDR_Banks/M1_CLK# ) + ( H20 /DDR_Banks/M1_CLK ) + ( F22 /DDR_Banks/M1_A1 ) + ( F21 /DDR_Banks/M1_A0 ) + ( K17 /DDR_Banks/M1_BA1 ) + ( J17 /DDR_Banks/M1_BA0 ) + ( E22 /DDR_Banks/M1_A2 ) + ( E20 /DDR_Banks/M1_A7 ) + ( H18 ? ) + ( H19 /DDR_Banks/M1_WE# ) + ( F20 /DDR_Banks/M1_A4 ) + ( G19 /DDR_Banks/M1_A10 ) + ( C22 /DDR_Banks/M1_A9 ) + ( C20 /DDR_Banks/M1_A8 ) + ( D22 /DDR_Banks/M1_A12 ) + ( D21 /DDR_Banks/M1_CKE ) + ( F19 /DDR_Banks/M1_A11 ) + ( F18 ? ) + ( D20 ? ) + ( D19 ? ) + ( H17 ? ) + ( H16 ? ) + ( J16 ? ) + ( K16 ? ) + ( A21 ? ) + ( A20 ? ) + ( B22 ? ) + ( B21 ? ) + ( F17 ? ) + ( F16 ? ) + ( G17 ? ) + ( G16 ? ) + ( B20 ? ) + ( B4 +3.3V ) + ( B7 +3.3V ) + ( E13 +3.3V ) + ( E17 +3.3V ) + ( G10 +3.3V ) + ( G14 +3.3V ) + ( B11 +3.3V ) + ( B15 +3.3V ) + ( B19 +3.3V ) + ( E9 +3.3V ) + ( A11 ? ) + ( D11 ? ) + ( C12 ? ) + ( B12 ? ) + ( A12 ? ) + ( C13 ? ) + ( A13 ? ) ( D14 ? ) ( C14 ? ) ( B14 ? ) ( A14 ? ) - ( E13 N-000100 ) - ( C13 ? ) - ( A13 ? ) - ( C12 ? ) - ( B12 ? ) - ( A12 ? ) - ( D11 ? ) + ( C15 ? ) + ( A15 /Non_volatile_memories/SD_DAT3 ) + ( D15 /Non_volatile_memories/SD_DAT2 ) + ( C16 /Non_volatile_memories/SD_DAT1 ) + ( B16 /Non_volatile_memories/SD_DAT0 ) + ( A16 /Non_volatile_memories/SD_CLK ) + ( C17 /Non_volatile_memories/SD_CMD ) + ( A17 /FPGA_Spartan6/USBA_VM ) + ( B18 /FPGA_Spartan6/USBA_VP ) + ( A18 /FPGA_Spartan6/USBA_RCV ) + ( E16 /FPGA_Spartan6/USBA_OE_N ) + ( D17 /FPGA_Spartan6/USBA_SPD ) ( C11 ? ) - ( B11 N-000100 ) - ( A11 ? ) - ( H16 ? ) - ( G16 ? ) - ( F16 ? ) - ( L15 ? ) - ( W22 ? ) - ( V22 /FPGA_Spartan6/M1_DQ15 ) - ( U22 /FPGA_Spartan6/M1_DQ13 ) - ( T22 ? ) - ( R22 /FPGA_Spartan6/M1_DQ11 ) - ( P22 /FPGA_Spartan6/M1_DQ9 ) - ( N22 /DDR_Banks/M1_DQ1 ) - ( M22 /FPGA_Spartan6/M1_DQ3 ) - ( L22 ? ) - ( K22 /DDR_Banks/M1_DQ7 ) - ( J22 /FPGA_Spartan6/M1_DQ5 ) - ( H22 /DDR_Banks/M1_CAS# ) - ( G22 ? ) - ( F22 /FPGA_Spartan6/M1_A1 ) - ( E22 /FPGA_Spartan6/M1_A2 ) - ( D22 /FPGA_Spartan6/M1_A12 ) - ( C22 /DDR_Banks/M1_A9 ) - ( B22 ? ) - ( W21 N-000099 ) - ( V21 /FPGA_Spartan6/M1_DQ14 ) - ( T21 /DDR_Banks/M1_UDQS ) - ( R21 N-000099 ) - ( P21 /DDR_Banks/M1_DQ8 ) - ( M21 /DDR_Banks/M1_DQ2 ) - ( L21 N-000099 ) - ( K21 /FPGA_Spartan6/M1_DQ6 ) - ( M19 ? ) - ( L19 /FPGA_Spartan6/M1_LDM ) - ( K19 /FPGA_Spartan6/M1_A6 ) - ( J19 /DDR_Banks/M1_CLK# ) - ( H19 /DDR_Banks/M1_WE# ) - ( G19 /FPGA_Spartan6/M1_A10 ) - ( F19 /DDR_Banks/M1_A11 ) - ( E19 N-000099 ) - ( D19 ? ) - ( U18 N-000099 ) - ( P18 ? ) - ( N18 N-000099 ) - ( M18 ? ) - ( K18 ? ) - ( J18 N-000099 ) - ( H18 ? ) - ( F18 ? ) - ( P17 ? ) - ( M17 ? ) - ( L17 ? ) - ( K17 /FPGA_Spartan6/M1_BA1 ) - ( J17 /DDR_Banks/M1_BA0 ) - ( H17 ? ) - ( G17 ? ) - ( F17 ? ) - ( N16 ? ) - ( M16 ? ) - ( L16 N-000099 ) - ( K16 ? ) - ( J16 ? ) - ( J14 N-000102 ) - ( H14 ? ) - ( F14 ? ) - ( E14 ? ) - ( P13 N-000102 ) - ( N13 GND ) - ( M13 N-000102 ) - ( L13 GND ) - ( K13 N-000102 ) - ( J13 GND ) - ( H13 ? ) - ( G13 ? ) - ( F13 ? ) - ( D13 ? ) - ( B13 GND ) - ( Y22 ? ) - ( A22 GND ) - ( R12 N-000103 ) - ( P12 GND ) - ( N12 N-000102 ) - ( M12 GND ) - ( L12 N-000102 ) - ( K12 ? ) - ( J12 N-000102 ) - ( H12 ? ) - ( G12 N-000103 ) - ( F12 ? ) - ( E12 ? ) - ( D12 ? ) - ( AB1 GND ) - ( A19 ? ) - ( R18 GND ) - ( L18 GND ) - ( G18 GND ) - ( E18 ? ) - ( D18 GND ) - ( C18 ? ) - ( R17 ? ) - ( N17 GND ) - ( B17 GND ) - ( W16 GND ) - ( P16 ? ) - ( D16 N-000103 ) - ( AA5 GND ) - ( P15 ? ) - ( N15 ? ) - ( M15 N-000103 ) - ( K15 N-000103 ) - ( J15 GND ) - ( H15 N-000103 ) - ( G15 ? ) - ( F15 ? ) - ( E15 GND ) - ( V14 GND ) - ( R14 N-000102 ) - ( P14 GND ) - ( N14 N-000102 ) - ( M14 GND ) - ( L14 N-000102 ) - ( K14 GND ) - ( L9 GND ) - ( K9 N-000102 ) - ( J9 GND ) - ( H9 N-000103 ) - ( G9 ? ) - ( F9 ? ) - ( B9 GND ) - ( N8 N-000103 ) - ( L8 N-000103 ) - ( J8 N-000102 ) - ( G8 ? ) - ( F8 ? ) - ( E8 ? ) - ( W7 GND ) - ( U7 GND ) - ( H7 GND ) - ( E7 GND ) - ( V6 N-000103 ) - ( R6 N-000103 ) - ( R5 GND ) - ( L5 GND ) - ( G5 GND ) - ( B5 GND ) - ( V4 GND ) - ( D4 GND ) - ( U2 GND ) - ( N2 GND ) - ( J2 GND ) - ( E2 GND ) - ( A1 GND ) - ( AA1 ? ) - ( U21 GND ) - ( N21 GND ) - ( J21 GND ) - ( E21 GND ) - ( U11 N-000103 ) - ( P11 N-000102 ) - ( N11 GND ) - ( M11 N-000102 ) - ( L11 GND ) - ( K11 N-000102 ) - ( J11 GND ) - ( H11 ? ) - ( G11 ? ) - ( F11 N-000103 ) - ( E11 ? ) - ( V10 GND ) - ( R10 N-000103 ) - ( P10 GND ) - ( N10 N-000102 ) - ( M10 GND ) - ( L10 N-000102 ) - ( K10 GND ) - ( J10 N-000102 ) - ( H10 ? ) - ( F10 ? ) - ( E10 ? ) - ( P9 N-000102 ) - ( N9 GND ) - ( M9 N-000102 ) - ( V19 ? ) - ( AB8 ? ) - ( AA8 ? ) - ( Y18 ? ) - ( W18 ? ) - ( V18 ? ) - ( T18 ? ) - ( AB7 ? ) - ( AA7 N-000101 ) - ( Y17 ? ) - ( W17 ? ) - ( V17 ? ) - ( U17 ? ) - ( T17 ? ) - ( AB6 ? ) - ( AA6 ? ) - ( Y16 ? ) - ( V16 N-000101 ) - ( U16 ? ) - ( T16 ? ) - ( R16 ? ) - ( AB5 ? ) - ( Y15 ? ) - ( W15 ? ) - ( V15 ? ) - ( U15 ? ) - ( T15 ? ) - ( R15 ? ) - ( AB4 ? ) - ( AA4 ? ) - ( F1 ? ) - ( E1 /DDR_Banks/M0_A9 ) - ( D1 /DDR_Banks/M0_A12 ) - ( C1 /FPGA_Spartan6/M0_A11 ) - ( B1 ? ) - ( AB19 ? ) - ( AA19 N-000101 ) - ( AB18 ? ) - ( AA18 ? ) - ( AB17 ? ) - ( AB16 ? ) - ( AA16 ? ) - ( AB15 ? ) - ( AA15 N-000101 ) - ( AB14 ? ) - ( AA14 ? ) - ( AB13 ? ) - ( AA22 ? ) - ( AB12 ? ) - ( AA12 ? ) - ( AB21 ? ) - ( AA21 ? ) - ( AB11 ? ) - ( AA11 N-000101 ) - ( AB20 ? ) - ( AA20 ? ) - ( AB10 ? ) - ( AA10 ? ) - ( AB9 ? ) - ( Y19 ? ) - ( V9 ? ) - ( U9 ? ) - ( T9 N-000101 ) - ( R9 ? ) - ( Y8 ? ) - ( W8 ? ) - ( V8 N-000101 ) - ( U8 ? ) - ( T8 ? ) - ( R8 ? ) - ( Y7 ? ) - ( V7 ? ) - ( T7 ? ) - ( R7 ? ) - ( Y6 ? ) - ( W6 ? ) - ( U6 ? ) - ( T6 ? ) - ( Y5 ? ) - ( W5 N-000101 ) - ( V5 ? ) - ( T5 ? ) - ( Y4 ? ) - ( W4 ? ) - ( Y3 ? ) - ( AA17 GND ) - ( AA13 GND ) - ( AB22 GND ) - ( AA9 GND ) - ( W19 GND ) - ( Y14 ? ) - ( W14 ? ) - ( U14 ? ) - ( T14 ? ) - ( AB3 ? ) - ( AA3 N-000101 ) - ( Y13 ? ) - ( W13 ? ) - ( V13 ? ) - ( U13 ? ) - ( T13 N-000101 ) - ( R13 ? ) - ( AB2 ? ) - ( AA2 ? ) - ( Y12 ? ) - ( W12 ? ) - ( V12 N-000101 ) - ( U12 ? ) - ( T12 ? ) - ( Y11 ? ) - ( W11 ? ) - ( V11 ? ) - ( T11 ? ) - ( R11 ? ) - ( Y10 ? ) - ( W10 ? ) - ( U10 ? ) - ( T10 ? ) - ( Y9 ? ) - ( W9 ? ) - ) - ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000367 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000367 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000362 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000368 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000361 ) - ( 2 ? ) - ) - ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000367 ) - ( S2 N-000367 ) - ( S3 N-000367 ) - ( S4 N-000367 ) - ( 1 N-000361 ) - ( 2 N-000368 ) - ( 3 N-000362 ) - ( 4 GND ) - ) - ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} - ( 1 3.3V ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 7 GND ) - ( 8 GND ) - ( 9 ? ) - ( 10 N-000368 ) - ( 11 N-000362 ) - ( 12 3.3V ) - ( 14 3.3V ) + ( A10 /FPGA_Spartan6/ETH_COL ) + ( B10 /FPGA_Spartan6/ETH_CRS ) + ( C10 /FPGA_Spartan6/ETH_CLK ) + ( D10 /FPGA_Spartan6/ETH_RXC ) + ( D8 /FPGA_Spartan6/ETH_TXC ) + ( D7 /FPGA_Spartan6/ETH_TXD3 ) + ( A9 /FPGA_Spartan6/ETH_TXD2 ) + ( C9 /FPGA_Spartan6/ETH_TXD1 ) + ( C8 /FPGA_Spartan6/ETH_TXD0 ) + ( D9 /FPGA_Spartan6/ETH_TXEN ) + ( A8 /FPGA_Spartan6/ETH_TXER ) + ( B8 /FPGA_Spartan6/ETH_RXER ) + ( A7 /FPGA_Spartan6/ETH_RXDV ) + ( C7 /FPGA_Spartan6/ETH_RXD0 ) + ( A6 /FPGA_Spartan6/ETH_RXD1 ) + ( B6 /FPGA_Spartan6/ETH_RXD2 ) + ( C6 /FPGA_Spartan6/ETH_RXD3 ) + ( D6 /FPGA_Spartan6/ETH_RESET_N ) + ( A5 /FPGA_Spartan6/ETH_MDIO ) + ( C5 /FPGA_Spartan6/ETH_MDC ) + ( A4 /FPGA_Spartan6/ETH_INT ) ) ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} ( 1 /Ethernet_Phy/ETH_PLL1.8V ) - ( 2 N-000360 ) + ( 2 N-000347 ) ) ( /4C4320F3/4C5D810A $noname L3 INDUCTOR {Lib=INDUCTOR} ( 1 /Ethernet_Phy/ETH_A1.8V ) @@ -547,22 +547,22 @@ ) ( /4C4320F3/4C5D8104 $noname C6 C {Lib=C} ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 N-000360 ) + ( 2 N-000347 ) ) ( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR} - ( 1 N-000356 ) + ( 1 N-000346 ) ( 2 /Ethernet_Phy/ETH_A1.8V ) ) ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} - ( 1 N-000356 ) - ( 2 N-000360 ) + ( 1 N-000346 ) + ( 2 N-000347 ) ) ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} ( 1 /Ethernet_Phy/ETH_1.8V ) ( 2 GND ) ) ( /4C4320F3/4C5D7FB7 $noname L2 FB {Lib=INDUCTOR} - ( 1 3.3V ) + ( 1 N-000069 ) ( 2 /Ethernet_Phy/ETH_A3.3V ) ) ( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C} @@ -574,83 +574,83 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C} - ( 1 3.3V ) + ( 1 N-000069 ) ( 2 GND ) ) ( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C} - ( 1 3.3V ) + ( 1 N-000069 ) ( 2 GND ) ) ( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C} - ( 1 3.3V ) + ( 1 N-000069 ) ( 2 GND ) ) ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} - ( 1 /Ethernet_Phy/ETH_MDIO ) - ( 2 3.3V ) + ( 1 /FPGA_Spartan6/ETH_MDIO ) + ( 2 N-000069 ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000354 ) + ( 1 N-000336 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} - ( 1 3.3V ) + ( 1 N-000069 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C} - ( 1 3.3V ) + ( 1 N-000069 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000355 ) + ( 1 N-000345 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000355 ) + ( 1 N-000345 ) ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /Ethernet_Phy/ETH_MDIO ) - ( 2 /Ethernet_Phy/ETH_MDC ) - ( 3 /Ethernet_Phy/ETH_RXD3 ) + ( 1 /FPGA_Spartan6/ETH_MDIO ) + ( 2 /FPGA_Spartan6/ETH_MDC ) + ( 3 /FPGA_Spartan6/ETH_RXD3 ) ( 4 /FPGA_Spartan6/ETH_RXD2 ) - ( 5 /Ethernet_Phy/ETH_RXD1 ) + ( 5 /FPGA_Spartan6/ETH_RXD1 ) ( 6 /FPGA_Spartan6/ETH_RXD0 ) - ( 7 3.3V ) + ( 7 N-000069 ) ( 8 GND ) - ( 9 /Ethernet_Phy/ETH_RXDV ) - ( 10 /Ethernet_Phy/ETH_RXC ) + ( 9 /FPGA_Spartan6/ETH_RXDV ) + ( 10 /FPGA_Spartan6/ETH_RXC ) ( 11 /FPGA_Spartan6/ETH_RXER ) ( 12 GND ) ( 13 /Ethernet_Phy/ETH_1.8V ) - ( 14 /Ethernet_Phy/ETH_TXER ) - ( 15 /Ethernet_Phy/ETH_TXC ) - ( 16 /Ethernet_Phy/ETH_TXEN ) + ( 14 /FPGA_Spartan6/ETH_TXER ) + ( 15 /FPGA_Spartan6/ETH_TXC ) + ( 16 /FPGA_Spartan6/ETH_TXEN ) ( 17 /FPGA_Spartan6/ETH_TXD0 ) - ( 18 /Ethernet_Phy/ETH_TXD1 ) - ( 19 /Ethernet_Phy/ETH_TXD2 ) + ( 18 /FPGA_Spartan6/ETH_TXD1 ) + ( 19 /FPGA_Spartan6/ETH_TXD2 ) ( 20 /FPGA_Spartan6/ETH_TXD3 ) - ( 21 ? ) - ( 22 ? ) + ( 21 /FPGA_Spartan6/ETH_COL ) + ( 22 /FPGA_Spartan6/ETH_CRS ) ( 23 GND ) - ( 24 3.3V ) - ( 25 /Ethernet_Phy/ETH_INT ) + ( 24 N-000069 ) + ( 25 /FPGA_Spartan6/ETH_INT ) ( 26 /Ethernet_Phy/ETH_LED0 ) ( 27 /Ethernet_Phy/ETH_LED1 ) ( 28 ? ) ( 29 ? ) ( 30 ? ) ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000358 ) - ( 33 N-000341 ) + ( 32 N-000337 ) + ( 33 N-000344 ) ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000354 ) + ( 37 N-000336 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) - ( 40 N-000359 ) - ( 41 N-000350 ) + ( 40 N-000338 ) + ( 41 N-000343 ) ( 42 ? ) ( 43 ? ) ( 44 GND ) @@ -660,54 +660,54 @@ ( 48 /FPGA_Spartan6/ETH_RESET_N ) ) ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000350 ) + ( 1 N-000069 ) + ( 2 N-000343 ) ) ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000359 ) + ( 1 N-000069 ) + ( 2 N-000338 ) ) ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000358 ) + ( 1 N-000069 ) + ( 2 N-000337 ) ) ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000341 ) + ( 1 N-000069 ) + ( 2 N-000344 ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000352 ) + ( 1 N-000340 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000351 ) + ( 1 N-000341 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000350 ) - ( 2 N-000359 ) - ( 3 3.3V ) + ( 1 N-000343 ) + ( 2 N-000338 ) + ( 3 N-000069 ) ( 4 GND ) ( 5 GND ) - ( 6 3.3V ) - ( 7 N-000341 ) - ( 8 N-000358 ) - ( 9 3.3V ) - ( 10 N-000351 ) - ( 11 3.3V ) - ( 12 N-000352 ) - ( 13 N-000355 ) - ( 14 N-000355 ) + ( 6 N-000069 ) + ( 7 N-000344 ) + ( 8 N-000337 ) + ( 9 N-000069 ) + ( 10 N-000341 ) + ( 11 N-000069 ) + ( 12 N-000340 ) + ( 13 N-000345 ) + ( 14 N-000345 ) ) ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} ( CASE GND ) - ( COM GND ) ( CD ? ) + ( COM GND ) ( 1 /Non_volatile_memories/SD_DAT2 ) - ( 2 /FPGA_Spartan6/SD_DAT3 ) - ( 3 /FPGA_Spartan6/SD_CMD ) + ( 2 /Non_volatile_memories/SD_DAT3 ) + ( 3 /Non_volatile_memories/SD_CMD ) ( 4 ? ) - ( 5 /FPGA_Spartan6/SD_CLK ) + ( 5 /Non_volatile_memories/SD_CLK ) ( 6 GND ) ( 7 /Non_volatile_memories/SD_DAT0 ) ( 8 /Non_volatile_memories/SD_DAT1 ) @@ -724,14 +724,14 @@ ( 9 ? ) ( 10 ? ) ( 11 ? ) - ( 12 3.3V ) + ( 12 N-000069 ) ( 13 GND ) ( 14 ? ) ( 15 ? ) ( 16 ? ) ( 17 ? ) ( 18 ? ) - ( 19 3.3V ) + ( 19 N-000069 ) ( 20 ? ) ( 21 ? ) ( 22 ? ) @@ -749,7 +749,7 @@ ( 34 ? ) ( 35 ? ) ( 36 GND ) - ( 37 3.3V ) + ( 37 N-000069 ) ( 38 ? ) ( 39 ? ) ( 40 ? ) @@ -820,35 +820,35 @@ ) ( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R} ( 1 +2.5V ) - ( 2 N-000044 ) + ( 2 N-000047 ) ) ( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R} - ( 1 N-000044 ) - ( 2 N-000043 ) + ( 1 N-000047 ) + ( 2 N-000048 ) ) ( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R} - ( 1 N-000045 ) - ( 2 N-000047 ) + ( 1 N-000046 ) + ( 2 N-000045 ) ) ( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R} ( 1 +2.5V ) - ( 2 N-000045 ) + ( 2 N-000046 ) ) ( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP} ( 1 +2.5V ) - ( 2 N-000044 ) + ( 2 N-000047 ) ) ( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP} - ( 1 N-000044 ) - ( 2 N-000043 ) + ( 1 N-000047 ) + ( 2 N-000048 ) ) ( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP} - ( 1 N-000045 ) - ( 2 N-000047 ) + ( 1 N-000046 ) + ( 2 N-000045 ) ) ( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP} ( 1 +2.5V ) - ( 2 N-000045 ) + ( 2 N-000046 ) ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) @@ -857,131 +857,131 @@ ( 4 /DDR_Banks/M1_DQ1 ) ( 5 /DDR_Banks/M1_DQ2 ) ( 6 GND ) - ( 7 /FPGA_Spartan6/M1_DQ3 ) - ( 8 /FPGA_Spartan6/M1_DQ4 ) + ( 7 /DDR_Banks/M1_DQ3 ) + ( 8 /DDR_Banks/M1_DQ4 ) ( 9 +2.5V ) - ( 10 /FPGA_Spartan6/M1_DQ5 ) - ( 11 /FPGA_Spartan6/M1_DQ6 ) + ( 10 /DDR_Banks/M1_DQ5 ) + ( 11 /DDR_Banks/M1_DQ6 ) ( 12 GND ) ( 13 /DDR_Banks/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /FPGA_Spartan6/M1_LDQS ) + ( 16 /DDR_Banks/M1_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Spartan6/M1_LDM ) + ( 20 /DDR_Banks/M1_LDM ) ( 21 /DDR_Banks/M1_WE# ) ( 22 /DDR_Banks/M1_CAS# ) - ( 23 /FPGA_Spartan6/M1_RAS# ) + ( 23 /DDR_Banks/M1_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /DDR_Banks/M1_BA0 ) - ( 27 /FPGA_Spartan6/M1_BA1 ) - ( 28 /FPGA_Spartan6/M1_A10 ) + ( 27 /DDR_Banks/M1_BA1 ) + ( 28 /DDR_Banks/M1_A10 ) ( 29 /DDR_Banks/M1_A0 ) - ( 30 /FPGA_Spartan6/M1_A1 ) - ( 31 /FPGA_Spartan6/M1_A2 ) - ( 32 /FPGA_Spartan6/M1_A3 ) + ( 30 /DDR_Banks/M1_A1 ) + ( 31 /DDR_Banks/M1_A2 ) + ( 32 /DDR_Banks/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /FPGA_Spartan6/M1_A4 ) - ( 36 /FPGA_Spartan6/M1_A5 ) - ( 37 /FPGA_Spartan6/M1_A6 ) + ( 35 /DDR_Banks/M1_A4 ) + ( 36 /DDR_Banks/M1_A5 ) + ( 37 /DDR_Banks/M1_A6 ) ( 38 /DDR_Banks/M1_A7 ) - ( 39 /FPGA_Spartan6/M1_A8 ) + ( 39 /DDR_Banks/M1_A8 ) ( 40 /DDR_Banks/M1_A9 ) ( 41 /DDR_Banks/M1_A11 ) - ( 42 /FPGA_Spartan6/M1_A12 ) + ( 42 /DDR_Banks/M1_A12 ) ( 43 ? ) ( 44 /DDR_Banks/M1_CLK# ) - ( 45 /FPGA_Spartan6/M1_CKE ) - ( 46 /FPGA_Spartan6/M1_CLK ) + ( 45 /DDR_Banks/M1_CKE ) + ( 46 /DDR_Banks/M1_CLK ) ( 47 /DDR_Banks/M1_UDM ) ( 48 GND ) - ( 49 N-000044 ) + ( 49 N-000047 ) ( 50 ? ) ( 51 /DDR_Banks/M1_UDQS ) ( 52 GND ) ( 53 ? ) ( 54 /DDR_Banks/M1_DQ8 ) ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M1_DQ9 ) - ( 57 /FPGA_Spartan6/M1_DQ10 ) + ( 56 /DDR_Banks/M1_DQ9 ) + ( 57 /DDR_Banks/M1_DQ10 ) ( 58 GND ) - ( 59 /FPGA_Spartan6/M1_DQ11 ) + ( 59 /DDR_Banks/M1_DQ11 ) ( 60 /DDR_Banks/M1_DQ12 ) ( 61 +2.5V ) - ( 62 /FPGA_Spartan6/M1_DQ13 ) - ( 63 /FPGA_Spartan6/M1_DQ14 ) + ( 62 /DDR_Banks/M1_DQ13 ) + ( 63 /DDR_Banks/M1_DQ14 ) ( 64 GND ) - ( 65 /FPGA_Spartan6/M1_DQ15 ) + ( 65 /DDR_Banks/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /FPGA_Spartan6/M0_DQ0 ) + ( 2 /DDR_Banks/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M0_DQ1 ) + ( 4 /DDR_Banks/M0_DQ1 ) ( 5 /DDR_Banks/M0_DQ2 ) ( 6 GND ) ( 7 /DDR_Banks/M0_DQ3 ) - ( 8 /FPGA_Spartan6/M0_DQ4 ) + ( 8 /DDR_Banks/M0_DQ4 ) ( 9 +2.5V ) - ( 10 /FPGA_Spartan6/M0_DQ5 ) - ( 11 /FPGA_Spartan6/M0_DQ6 ) + ( 10 /DDR_Banks/M0_DQ5 ) + ( 11 /DDR_Banks/M0_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Spartan6/M0_DQ7 ) + ( 13 /DDR_Banks/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /FPGA_Spartan6/M0_LDQS ) + ( 16 /DDR_Banks/M0_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Spartan6/M0_LDM ) - ( 21 /FPGA_Spartan6/M0_WE# ) - ( 22 /FPGA_Spartan6/M0_CAS# ) - ( 23 /FPGA_Spartan6/M0_RAS# ) + ( 20 /DDR_Banks/M0_LDM ) + ( 21 /DDR_Banks/M0_WE# ) + ( 22 /DDR_Banks/M0_CAS# ) + ( 23 /DDR_Banks/M0_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 /FPGA_Spartan6/M0_BA0 ) - ( 27 /FPGA_Spartan6/M0_BA1 ) - ( 28 /FPGA_Spartan6/M0_A10 ) - ( 29 /FPGA_Spartan6/M0_A0 ) - ( 30 /FPGA_Spartan6/M0_A1 ) - ( 31 /FPGA_Spartan6/M0_A2 ) - ( 32 /FPGA_Spartan6/M0_A3 ) + ( 26 /DDR_Banks/M0_BA0 ) + ( 27 /DDR_Banks/M0_BA1 ) + ( 28 /DDR_Banks/M0_A10 ) + ( 29 /DDR_Banks/M0_A0 ) + ( 30 /DDR_Banks/M0_A1 ) + ( 31 /DDR_Banks/M0_A2 ) + ( 32 /DDR_Banks/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /FPGA_Spartan6/M0_A4 ) + ( 35 /DDR_Banks/M0_A4 ) ( 36 /DDR_Banks/M0_A5 ) - ( 37 /FPGA_Spartan6/M0_A6 ) - ( 38 /FPGA_Spartan6/M0_A7 ) - ( 39 /FPGA_Spartan6/M0_A8 ) + ( 37 /DDR_Banks/M0_A6 ) + ( 38 /DDR_Banks/M0_A7 ) + ( 39 /DDR_Banks/M0_A8 ) ( 40 /DDR_Banks/M0_A9 ) - ( 41 /FPGA_Spartan6/M0_A11 ) + ( 41 /DDR_Banks/M0_A11 ) ( 42 /DDR_Banks/M0_A12 ) ( 43 ? ) ( 44 /DDR_Banks/M0_CLK# ) ( 45 /DDR_Banks/M0_CKE ) ( 46 /DDR_Banks/M0_CLK ) - ( 47 /FPGA_Spartan6/M0_UDM ) + ( 47 /DDR_Banks/M0_UDM ) ( 48 GND ) - ( 49 N-000045 ) + ( 49 N-000046 ) ( 50 ? ) ( 51 /DDR_Banks/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /FPGA_Spartan6/M0_DQ8 ) + ( 54 /DDR_Banks/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M0_DQ9 ) - ( 57 /FPGA_Spartan6/M0_DQ10 ) + ( 56 /DDR_Banks/M0_DQ9 ) + ( 57 /DDR_Banks/M0_DQ10 ) ( 58 GND ) - ( 59 /FPGA_Spartan6/M0_DQ11 ) + ( 59 /DDR_Banks/M0_DQ11 ) ( 60 /DDR_Banks/M0_DQ12 ) ( 61 +2.5V ) ( 62 /DDR_Banks/M0_DQ13 ) - ( 63 /FPGA_Spartan6/M0_DQ14 ) + ( 63 /DDR_Banks/M0_DQ14 ) ( 64 GND ) ( 65 /DDR_Banks/M0_DQ15 ) ( 66 GND ) @@ -993,7 +993,6 @@ $component R10 R? SM0603 SM0805 - R?-* $endlist $component C16 SM* @@ -1064,13 +1063,11 @@ $component R1 R? SM0603 SM0805 - R?-* $endlist $component R2 R? SM0603 SM0805 - R?-* $endlist $component C11 SM* @@ -1091,43 +1088,36 @@ $component R9 R? SM0603 SM0805 - R?-* $endlist $component R3 R? SM0603 SM0805 - R?-* $endlist $component R4 R? SM0603 SM0805 - R?-* $endlist $component R6 R? SM0603 SM0805 - R?-* $endlist $component R5 R? SM0603 SM0805 - R?-* $endlist $component R8 R? SM0603 SM0805 - R?-* $endlist $component R7 R? SM0603 SM0805 - R?-* $endlist $component C34 SM* @@ -1203,25 +1193,21 @@ $component R13 R? SM0603 SM0805 - R?-* $endlist $component R14 R? SM0603 SM0805 - R?-* $endlist $component R12 R? SM0603 SM0805 - R?-* $endlist $component R11 R? SM0603 SM0805 - R?-* $endlist $component C19 SM* @@ -1246,699 +1232,717 @@ $endlist $endfootprintlist } { Pin List by Nets -Net 1 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" - U4 46 +Net 2 "/FPGA Spartan6/ETH_COL" "ETH_COL" U1 A10 -Net 2 "/Ethernet Phy/ETH_TXER" "ETH_TXER" - U4 14 - U1 C8 -Net 3 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" - U4 16 - U1 C9 -Net 4 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" - U1 K4 - U2 22 -Net 5 "/DDR Banks/M1_WE#" "M1_WE#" - U1 H19 - U3 21 -Net 6 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" - U3 23 - U1 H21 -Net 7 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" - U2 23 - U1 K5 -Net 8 "/FPGA Spartan6/M0_WE#" "M0_WE#" - U2 21 - U1 F2 -Net 12 "/FPGA Spartan6/SD_CMD" "SD_CMD" - U1 C17 - J1 3 -Net 13 "/FPGA Spartan6/SD_CLK" "SD_CLK" - U1 A16 + U4 21 +Net 3 "/Non volatile memories/SD_CLK" "SD_CLK" J1 5 -Net 14 "/Ethernet Phy/ETH_INT" "ETH_INT" - U4 25 - U1 A5 -Net 15 "/Ethernet Phy/ETH_TXC" "ETH_TXC" - U1 C10 - U4 15 -Net 16 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" - U4 11 - U1 D9 -Net 17 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" + U1 A16 +Net 4 "/FPGA Spartan6/USBA_VM" "USBA_VM" + U1 A17 + U6 5 +Net 5 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" + U1 A18 + U6 3 +Net 6 "/FPGA Spartan6/USBA_SPD" "USBA_SPD" + U1 D17 + U6 2 +Net 7 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" U1 A8 - U4 9 -Net 18 "/Ethernet Phy/ETH_MDC" "ETH_MDC" - U1 D6 - U4 2 -Net 19 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" - U4 1 + U4 14 +Net 8 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" + U1 B8 + U4 11 +Net 9 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" + U1 A5 R1 1 - U1 C6 -Net 22 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" - U4 48 - U1 B6 -Net 23 "/Ethernet Phy/ETH_RXC" "ETH_RXC" + U4 1 +Net 10 "/FPGA Spartan6/ETH_RXC" "ETH_RXC" + U1 D10 U4 10 - U1 B10 -Net 27 "/DDR Banks/M1_UDM" "M1_UDM" - U1 M20 - U3 47 -Net 28 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" - U3 16 - U1 L20 -Net 29 "/FPGA Spartan6/M1_LDM" "M1_LDM" - U1 L19 - U3 20 -Net 30 "/DDR Banks/M1_UDQS" "M1_UDQS" - U3 51 - U1 T21 -Net 31 "/DDR Banks/M0_UDQS" "M0_UDQS" - U2 51 - U1 T2 -Net 32 "/FPGA Spartan6/M0_LDM" "M0_LDM" - U1 L4 - U2 20 -Net 33 "/DDR Banks/M1_CAS#" "M1_CAS#" - U3 22 - U1 H22 -Net 34 "/FPGA Spartan6/M1_CKE" "M1_CKE" - U3 45 - U1 D21 -Net 35 "GND" "GND" - U3 64 - U3 34 - U3 24 - U4 12 - U4 23 - U3 52 - U3 58 - C13 2 - U4 44 - U4 35 - U4 36 - C14 2 - C15 2 - U4 39 - U2 64 - U2 34 - U2 24 - U2 58 - U2 48 - U2 66 - U2 6 - U3 48 - U3 66 - U3 6 - V1 2 - U3 12 - C16 2 - R10 2 - V2 2 - J4 5 - J4 4 - U1 N13 - U1 L13 - U1 J13 - U1 W7 - U1 U7 - U1 H7 - U1 E7 - U1 L9 - U1 N9 - U6 8 - U1 A22 - U1 B13 - U1 J9 - U1 B9 - U1 B17 - U1 N17 - U1 AA17 - U1 AA13 - U1 AB22 - U1 AA9 - U1 W19 - U1 R18 - U1 L18 - U1 G18 - U1 D18 - U1 K10 - U1 M10 - U1 P10 - U1 V10 - U1 J2 - U1 E2 - U1 A1 - U1 W16 - U1 AA5 - U1 J15 - U1 E15 - U1 V14 - U5 13 - U1 AB1 - U5 36 - U1 P14 - U2 52 - U2 12 - J1 6 - U1 R5 - U1 L5 - J1 COM - J1 CASE - J1 CASE - J1 CASE - U1 G5 - U1 B5 - U1 V4 - U1 D4 - U1 U2 - U1 N2 - U6 7 - U1 M12 - U1 P12 - U1 U21 - U1 N21 - U1 J21 - U1 E21 - U1 N11 - U1 L11 - U1 J11 - U1 M14 - U1 K14 - J5 4 - C2 2 +Net 11 "GND" "GND" C34 2 - C1 2 - C3 2 - C5 2 - C7 2 - C8 2 - C23 2 + C33 2 + C28 2 C29 2 - C22 2 C31 2 C30 2 C32 2 C27 2 - C28 2 - C10 2 - R2 2 - C11 2 + C21 2 C26 2 C24 2 C25 2 + C23 2 + C22 2 + U3 24 + U3 34 + U3 48 + U3 66 + U3 6 + U3 12 + U3 52 + U3 58 + U3 64 + U2 24 + U2 34 + U2 48 + U2 66 + U2 6 + U2 12 + U2 52 + U2 58 + U2 64 + J1 CASE + J1 CASE + J1 CASE + J1 6 + J1 COM + U5 36 + U5 13 + U1 P10 + U1 V10 + U1 M10 + U1 K10 + U1 L13 + U1 A1 + U1 N13 + U1 A22 + U1 R5 + U1 AA13 + U1 W19 + U1 AA17 + U1 K14 + U1 AA5 + U1 L5 + U1 AA9 + U1 M14 + U1 AB1 + U1 N2 + U1 AB22 + U1 P14 + U1 B13 + U1 U21 + U1 B17 + U1 V4 + U1 B5 + U1 J9 + U1 B9 + U1 D18 + U1 L11 + U1 D4 + U1 L18 + U1 L9 + U1 E15 + U1 M12 + U1 E2 + U1 N11 + U1 E21 + U1 N17 + U1 E7 + U1 N21 + U1 G18 + U1 P12 + U1 G5 + U1 R18 + U1 H7 + U1 U2 + U1 J11 + U1 U7 + U1 J13 + U1 V14 + U1 J15 + U1 W16 + U1 J2 + U1 W7 + U1 J21 + U1 N9 + C2 2 + C8 2 + C7 2 + C5 2 + C3 2 + C1 2 + R2 2 + C11 2 + C10 2 C12 2 R9 2 U4 8 - C33 2 - C21 2 -Net 36 "/DDR Banks/M0_CKE" "M0_CKE" - U1 D2 + U4 12 + U4 23 + U4 35 + U4 36 + U4 39 + U4 44 + J4 5 + J4 4 + R10 2 + C16 2 + V1 2 + V2 2 + J5 4 + C15 2 + C14 2 + C13 2 + U6 8 + U6 7 +Net 12 "/DDR Banks/M1_LDM" "M1_LDM" + U3 20 + U1 L19 +Net 13 "/DDR Banks/M1_CKE" "M1_CKE" + U3 45 + U1 D21 +Net 14 "/DDR Banks/M1_CAS#" "M1_CAS#" + U3 22 + U1 H22 +Net 15 "/DDR Banks/M0_CKE" "M0_CKE" U2 45 -Net 37 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" - U2 16 - U1 L3 -Net 38 "/FPGA Spartan6/M0_UDM" "M0_UDM" + U1 D2 +Net 16 "/DDR Banks/M0_WE#" "M0_WE#" + U2 21 + U1 F2 +Net 17 "/DDR Banks/M0_CAS#" "M0_CAS#" + U2 22 + U1 K4 +Net 18 "/DDR Banks/M0_UDM" "M0_UDM" U2 47 U1 M3 -Net 39 "/DDR Banks/M0_CLK#" "M0_CLK#" - U1 H3 - U2 44 -Net 40 "/DDR Banks/M0_CLK" "M0_CLK" - U2 46 - U1 H4 -Net 41 "/DDR Banks/M1_CLK#" "M1_CLK#" +Net 19 "/DDR Banks/M0_UDQS" "M0_UDQS" + U2 51 + U1 T2 +Net 20 "/DDR Banks/M1_CLK#" "M1_CLK#" U3 44 U1 J19 -Net 42 "/FPGA Spartan6/M1_CLK" "M1_CLK" +Net 21 "/DDR Banks/M0_CLK#" "M0_CLK#" + U2 44 + U1 H3 +Net 22 "/DDR Banks/M0_CLK" "M0_CLK" + U2 46 + U1 H4 +Net 23 "/DDR Banks/M1_CLK" "M1_CLK" U3 46 U1 H20 -Net 43 "" "" - R14 2 - C20 2 -Net 44 "" "" - U3 49 - R14 1 - R13 2 - C19 2 - C20 1 +Net 24 "/DDR Banks/M0_LDM" "M0_LDM" + U2 20 + U1 L4 +Net 25 "/DDR Banks/M0_LDQS" "M0_LDQS" + U2 16 + U1 L3 +Net 26 "/DDR Banks/M0_RAS#" "M0_RAS#" + U2 23 + U1 K5 +Net 27 "/DDR Banks/M1_RAS#" "M1_RAS#" + U3 23 + U1 H21 +Net 28 "/DDR Banks/M1_WE#" "M1_WE#" + U3 21 + U1 H19 +Net 29 "/DDR Banks/M1_UDM" "M1_UDM" + U3 47 + U1 M20 +Net 30 "/DDR Banks/M1_LDQS" "M1_LDQS" + U3 16 + U1 L20 +Net 31 "/DDR Banks/M1_UDQS" "M1_UDQS" + U3 51 + U1 T21 +Net 32 "/FPGA Spartan6/ETH_INT" "ETH_INT" + U1 A4 + U4 25 +Net 33 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" + U1 D6 + U4 48 +Net 34 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" + U1 C5 + U4 2 +Net 35 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" + U1 A7 + U4 9 +Net 36 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" + U1 D8 + U4 15 +Net 37 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" + U1 D9 + U4 16 +Net 38 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" + U1 C10 + U4 46 +Net 39 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" + U1 E16 + U6 9 +Net 40 "/FPGA Spartan6/USBA_VP" "USBA_VP" + U1 B18 + U6 4 +Net 41 "/Non volatile memories/SD_CMD" "SD_CMD" + J1 3 + U1 C17 +Net 42 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" + U1 B10 + U4 22 +Net 44 "+2.5V" "+2.5V" + C34 1 + C33 1 + C28 1 + C29 1 + C31 1 + C30 1 + C32 1 + C27 1 + C21 1 + C26 1 + C24 1 + C25 1 + C23 1 + C22 1 + R13 1 + R11 1 + C19 1 + C17 1 + U3 1 + U3 18 + U3 33 + U3 3 + U3 9 + U3 15 + U3 55 + U3 61 + U2 1 + U2 18 + U2 33 + U2 3 + U2 9 + U2 15 + U2 55 + U2 61 + U1 H9 + U1 U11 + U1 F11 + U1 R6 + U1 M15 + U1 V6 + U1 G12 + U1 H15 + U1 D16 + U1 K15 + U1 R12 + U1 N8 + U1 R10 + U1 L8 + U1 W2 + U1 L2 + U1 L7 + U1 C2 + U1 N5 + U1 R2 + U1 U5 + U1 G2 + U1 F4 + U1 F6 + U1 J5 + U1 W21 + U1 C21 + U1 G21 + U1 J18 + U1 L16 + U1 L21 + U1 N18 + U1 R21 + U1 U18 + U1 E19 Net 45 "" "" - R11 2 + R12 2 + C18 2 +Net 46 "" "" R12 1 + R11 2 C18 1 C17 2 U2 49 -Net 46 "+2.5V" "+2.5V" - C33 1 - C21 1 - C22 1 - C23 1 - C25 1 - C24 1 - C26 1 - C34 1 - C28 1 - C29 1 - C27 1 - C32 1 - C30 1 - C31 1 - R13 1 - U2 9 - U2 3 - U3 61 - U2 1 - R11 1 - C19 1 - U2 33 - C17 1 - U3 18 - U3 33 - U2 55 - U2 15 - U3 9 - U3 15 - U2 18 - U3 55 - U3 3 - U3 1 - U2 61 Net 47 "" "" - C18 2 - R12 2 -Net 95 "/Non volatile memories/FRB_N" "FRB_N" + R13 2 + R14 1 + C19 2 + C20 1 + U3 49 +Net 48 "" "" + R14 2 + C20 2 +Net 64 "/Non volatile memories/FRB_N" "FRB_N" U5 7 U5 6 -Net 97 "3.3V" "3.3V" - J4 3 - J4 6 - J4 9 - J4 11 - U4 7 - U6 1 - C5 1 - C1 1 - C3 1 - U6 12 - U6 14 - U4 24 - R5 1 - R6 1 - R4 1 - R3 1 - C13 1 - L2 1 - C14 1 +Net 69 "" "" U5 37 U5 19 - C10 1 U5 12 - C15 1 - C11 1 + L2 1 + C5 1 + C3 1 + C1 1 R1 2 -Net 98 "" "" - U1 R2 - U1 W2 - U1 J5 - U1 F4 - U1 L2 - U1 F6 - U1 U5 - U1 C2 - U1 L7 - U1 G2 - U1 N5 -Net 99 "" "" - U1 C21 - U1 G21 - U1 L16 - U1 R21 - U1 W21 - U1 L21 - U1 E19 - U1 J18 - U1 U18 - U1 N18 -Net 100 "" "" + C11 1 + C10 1 + U4 7 + U4 24 + R3 1 + R4 1 + R6 1 + R5 1 + J4 11 + J4 9 + J4 6 + J4 3 + C15 1 + C14 1 + C13 1 + U6 14 + U6 12 + U6 1 +Net 99 "+1.2V" "+1.2V" + U1 N10 + U1 P11 + U1 P13 + U1 P9 + U1 R14 + U1 N12 + U1 J10 + U1 J12 + U1 J14 + U1 J8 + U1 K11 + U1 K13 + U1 K9 + U1 L10 + U1 L12 + U1 L14 + U1 M11 + U1 M13 + U1 M9 + U1 N14 +Net 100 "+3.3V" "+3.3V" + U1 B4 + U1 B7 + U1 E13 + U1 E17 + U1 G10 U1 G14 + U1 B11 U1 B15 U1 B19 U1 E9 - U1 G10 - U1 B11 - U1 B4 - U1 B7 - U1 E17 - U1 E13 Net 101 "" "" - U1 AA11 - U1 AA7 - U1 V16 U1 AA15 - U1 AA3 - U1 V12 - U1 AA19 - U1 W5 + U1 V16 U1 T13 U1 V8 + U1 V12 + U1 AA3 U1 T9 -Net 102 "" "" - U1 J8 - U1 K9 - U1 K13 - U1 N12 - U1 L12 - U1 J12 - U1 M13 - U1 P13 - U1 P11 - U1 J14 - U1 L14 - U1 K11 - U1 N10 - U1 L10 - U1 J10 - U1 P9 - U1 M9 - U1 M11 - U1 N14 - U1 R14 -Net 103 "" "" - U1 R10 - U1 U11 - U1 R12 - U1 R6 - U1 F11 - U1 H9 - U1 G12 - U1 V6 - U1 N8 - U1 L8 - U1 M15 - U1 K15 - U1 H15 - U1 D16 -Net 340 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - U4 47 - L3 2 - C9 1 -Net 341 "" "" - J4 7 - U4 33 - R5 2 -Net 342 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - U4 27 - R8 2 -Net 345 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" - U4 13 - C2 1 -Net 349 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - R7 2 - U4 26 -Net 350 "" "" - J4 1 - U4 41 - R3 2 -Net 351 "" "" - J4 10 - R7 1 -Net 352 "" "" - J4 12 - R8 1 -Net 353 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - L1 2 - C6 1 + U1 AA19 + U1 AA11 + U1 W5 + U1 AA7 +Net 334 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" L3 1 + C6 1 + L1 2 U4 31 -Net 354 "" "" - U4 37 - R2 1 -Net 355 "" "" - J4 13 - J4 14 - C12 1 - R9 1 -Net 356 "" "" - L1 1 - C4 1 -Net 357 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - U4 38 +Net 335 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" L2 2 C8 1 C7 1 -Net 358 "" "" - R6 2 + U4 38 +Net 336 "" "" + R2 1 + U4 37 +Net 337 "" "" U4 32 + R6 2 J4 8 -Net 359 "" "" - J4 2 +Net 338 "" "" U4 40 R4 2 -Net 360 "" "" + J4 2 +Net 339 "/Ethernet Phy/ETH_LED1" "ETH_LED1" + U4 27 + R8 2 +Net 340 "" "" + R8 1 + J4 12 +Net 341 "" "" + R7 1 + J4 10 +Net 342 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + U4 26 + R7 2 +Net 343 "" "" + U4 41 + R3 2 + J4 1 +Net 344 "" "" + U4 33 + R5 2 + J4 7 +Net 345 "" "" + C12 1 + R9 1 + J4 13 + J4 14 +Net 346 "" "" + L1 1 + C4 1 +Net 347 "" "" C9 2 C6 2 C4 2 -Net 361 "" "" - F1 1 - J5 1 -Net 362 "" "" - J5 3 - V1 1 - U6 11 - V1 1 -Net 367 "" "" - R10 1 - C16 1 - J5 S4 - J5 S3 - J5 S2 - J5 S1 -Net 368 "" "" - U6 10 +Net 348 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" + C2 1 + U4 13 +Net 349 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + C9 1 + L3 2 + U4 47 +Net 358 "" "" V2 1 V2 1 J5 2 -Net 378 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" - J1 2 - U1 A15 -Net 379 "/Non volatile memories/SD_DAT2" "SD_DAT2" - J1 1 - U1 D15 -Net 380 "/Non volatile memories/SD_DAT1" "SD_DAT1" - U1 C16 - J1 8 -Net 381 "/Non volatile memories/SD_DAT0" "SD_DAT0" - U1 B16 - J1 7 -Net 382 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" - U1 D10 - U4 20 -Net 383 "/FPGA Spartan6/M1_BA1" "M1_BA1" - U3 27 - U1 K17 -Net 384 "/DDR Banks/M1_BA0" "M1_BA0" - U3 26 - U1 J17 -Net 385 "/FPGA Spartan6/M0_BA1" "M0_BA1" - U2 27 - U1 G1 -Net 386 "/FPGA Spartan6/M0_BA0" "M0_BA0" - U1 G3 - U2 26 -Net 396 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" - U1 A6 - U4 3 -Net 397 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" - U1 C7 - U4 4 -Net 398 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" - U1 A7 - U4 5 -Net 399 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" - U1 B8 - U4 6 -Net 400 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" - U1 D8 - U4 19 -Net 401 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" - U1 D7 - U4 18 -Net 402 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" - U1 A9 - U4 17 -Net 403 "/DDR Banks/M1_A9" "M1_A9" - U1 C22 - U3 40 -Net 404 "/FPGA Spartan6/M1_A8" "M1_A8" - U1 C20 - U3 39 -Net 405 "/DDR Banks/M1_A7" "M1_A7" - U3 38 - U1 E20 -Net 406 "/FPGA Spartan6/M1_A6" "M1_A6" - U3 37 - U1 K19 -Net 407 "/FPGA Spartan6/M1_A5" "M1_A5" - U3 36 - U1 K20 -Net 408 "/FPGA Spartan6/M1_A4" "M1_A4" - U1 F20 - U3 35 -Net 409 "/FPGA Spartan6/M1_A3" "M1_A3" - U1 G20 - U3 32 -Net 410 "/FPGA Spartan6/M1_A2" "M1_A2" - U3 31 - U1 E22 -Net 411 "/FPGA Spartan6/M1_A1" "M1_A1" - U3 30 - U1 F22 -Net 412 "/DDR Banks/M1_A0" "M1_A0" - U1 F21 - U3 29 -Net 413 "/DDR Banks/M0_A12" "M0_A12" - U1 D1 - U2 42 -Net 414 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" - U1 V22 - U3 65 -Net 415 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" - U1 V21 - U3 63 -Net 416 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" - U3 62 - U1 U22 -Net 417 "/DDR Banks/M1_DQ12" "M1_DQ12" - U3 60 - U1 U20 -Net 418 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" - U3 59 - U1 R22 -Net 419 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" - U1 R20 - U3 57 -Net 420 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" - U1 P22 - U3 56 -Net 421 "/DDR Banks/M1_DQ8" "M1_DQ8" - U3 54 - U1 P21 -Net 422 "/DDR Banks/M1_DQ7" "M1_DQ7" - U3 13 - U1 K22 -Net 423 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" - U1 K21 - U3 11 -Net 424 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" - U1 J22 - U3 10 -Net 425 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" - U3 8 - U1 J20 -Net 426 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" - U1 M22 - U3 7 -Net 427 "/DDR Banks/M1_DQ2" "M1_DQ2" - U1 M21 - U3 5 -Net 428 "/DDR Banks/M1_DQ1" "M1_DQ1" - U1 N22 - U3 4 -Net 429 "/DDR Banks/M1_DQ0" "M1_DQ0" - U3 2 - U1 N20 -Net 430 "/FPGA Spartan6/M1_A12" "M1_A12" - U3 42 - U1 D22 -Net 431 "/DDR Banks/M1_A11" "M1_A11" - U1 F19 - U3 41 -Net 432 "/FPGA Spartan6/M1_A10" "M1_A10" - U3 28 - U1 G19 -Net 433 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" - U1 R3 - U2 57 -Net 434 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" - U1 P1 - U2 56 -Net 435 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" - U2 54 - U1 P2 -Net 436 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" - U1 K1 - U2 13 -Net 437 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" - U1 K2 - U2 11 -Net 438 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" - U2 10 - U1 J1 -Net 439 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" - U1 J3 - U2 8 -Net 440 "/DDR Banks/M0_DQ3" "M0_DQ3" - U1 M1 - U2 7 -Net 441 "/DDR Banks/M0_DQ2" "M0_DQ2" - U1 M2 - U2 5 -Net 442 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" - U2 4 - U1 N1 -Net 443 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" - U1 N3 - U2 2 -Net 444 "/FPGA Spartan6/M0_A11" "M0_A11" - U2 41 - U1 C1 -Net 445 "/FPGA Spartan6/M0_A10" "M0_A10" - U2 28 - U1 G4 -Net 446 "/DDR Banks/M0_A9" "M0_A9" - U2 40 - U1 E1 -Net 447 "/FPGA Spartan6/M0_A8" "M0_A8" - U2 39 - U1 E3 -Net 448 "/FPGA Spartan6/M0_A7" "M0_A7" - U1 H6 - U2 38 -Net 449 "/FPGA Spartan6/M0_A6" "M0_A6" - U1 J4 - U2 37 -Net 450 "/DDR Banks/M0_A5" "M0_A5" - U2 36 - U1 K3 -Net 451 "/FPGA Spartan6/M0_A4" "M0_A4" - U1 F3 - U2 35 -Net 452 "/FPGA Spartan6/M0_A3" "M0_A3" - U2 32 - U1 K6 -Net 453 "/FPGA Spartan6/M0_A2" "M0_A2" - U1 H5 - U2 31 -Net 454 "/FPGA Spartan6/M0_A1" "M0_A1" - U2 30 - U1 H1 -Net 455 "/FPGA Spartan6/M0_A0" "M0_A0" + U6 10 +Net 359 "" "" + V1 1 + V1 1 + J5 3 + U6 11 +Net 360 "" "" + F1 1 + J5 1 +Net 361 "" "" + R10 1 + C16 1 + J5 S1 + J5 S2 + J5 S3 + J5 S4 +Net 362 "/DDR Banks/M0_A0" "M0_A0" U2 29 U1 H2 -Net 456 "/DDR Banks/M0_DQ15" "M0_DQ15" - U1 V1 - U2 65 -Net 457 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" - U1 V2 - U2 63 -Net 458 "/DDR Banks/M0_DQ13" "M0_DQ13" - U1 U1 - U2 62 -Net 459 "/DDR Banks/M0_DQ12" "M0_DQ12" - U1 U3 - U2 60 -Net 460 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" +Net 363 "/DDR Banks/M0_A1" "M0_A1" + U2 30 + U1 H1 +Net 364 "/DDR Banks/M0_A2" "M0_A2" + U2 31 + U1 H5 +Net 365 "/DDR Banks/M0_A3" "M0_A3" + U2 32 + U1 K6 +Net 366 "/DDR Banks/M0_A4" "M0_A4" + U2 35 + U1 F3 +Net 367 "/DDR Banks/M0_A5" "M0_A5" + U2 36 + U1 K3 +Net 368 "/DDR Banks/M0_A6" "M0_A6" + U2 37 + U1 J4 +Net 369 "/DDR Banks/M0_A7" "M0_A7" + U2 38 + U1 H6 +Net 370 "/DDR Banks/M0_A8" "M0_A8" + U2 39 + U1 E3 +Net 371 "/DDR Banks/M0_A9" "M0_A9" + U2 40 + U1 E1 +Net 372 "/DDR Banks/M0_A10" "M0_A10" + U2 28 + U1 G4 +Net 373 "/DDR Banks/M0_A11" "M0_A11" + U2 41 + U1 C1 +Net 374 "/DDR Banks/M0_A12" "M0_A12" + U2 42 + U1 D1 +Net 375 "/DDR Banks/M1_A0" "M1_A0" + U3 29 + U1 F21 +Net 376 "/DDR Banks/M1_A1" "M1_A1" + U3 30 + U1 F22 +Net 377 "/DDR Banks/M1_A2" "M1_A2" + U3 31 + U1 E22 +Net 378 "/DDR Banks/M1_A3" "M1_A3" + U3 32 + U1 G20 +Net 379 "/DDR Banks/M1_A4" "M1_A4" + U3 35 + U1 F20 +Net 380 "/DDR Banks/M1_A5" "M1_A5" + U3 36 + U1 K20 +Net 381 "/DDR Banks/M1_A6" "M1_A6" + U3 37 + U1 K19 +Net 382 "/DDR Banks/M1_A7" "M1_A7" + U3 38 + U1 E20 +Net 383 "/DDR Banks/M1_A8" "M1_A8" + U3 39 + U1 C20 +Net 384 "/DDR Banks/M1_A9" "M1_A9" + U3 40 + U1 C22 +Net 385 "/DDR Banks/M1_A10" "M1_A10" + U3 28 + U1 G19 +Net 386 "/DDR Banks/M1_A11" "M1_A11" + U3 41 + U1 F19 +Net 387 "/DDR Banks/M1_A12" "M1_A12" + U3 42 + U1 D22 +Net 388 "/DDR Banks/M0_DQ0" "M0_DQ0" + U2 2 + U1 N3 +Net 389 "/DDR Banks/M0_DQ1" "M0_DQ1" + U2 4 + U1 N1 +Net 390 "/DDR Banks/M0_DQ2" "M0_DQ2" + U2 5 + U1 M2 +Net 391 "/DDR Banks/M0_DQ3" "M0_DQ3" + U2 7 + U1 M1 +Net 392 "/DDR Banks/M0_DQ4" "M0_DQ4" + U2 8 + U1 J3 +Net 393 "/DDR Banks/M0_DQ5" "M0_DQ5" + U2 10 + U1 J1 +Net 394 "/DDR Banks/M0_DQ6" "M0_DQ6" + U2 11 + U1 K2 +Net 395 "/DDR Banks/M0_DQ7" "M0_DQ7" + U2 13 + U1 K1 +Net 396 "/DDR Banks/M0_DQ8" "M0_DQ8" + U2 54 + U1 P2 +Net 397 "/DDR Banks/M0_DQ9" "M0_DQ9" + U2 56 + U1 P1 +Net 398 "/DDR Banks/M0_DQ10" "M0_DQ10" + U2 57 + U1 R3 +Net 399 "/DDR Banks/M0_DQ11" "M0_DQ11" U2 59 U1 R1 +Net 400 "/DDR Banks/M0_DQ12" "M0_DQ12" + U2 60 + U1 U3 +Net 401 "/DDR Banks/M0_DQ13" "M0_DQ13" + U2 62 + U1 U1 +Net 402 "/DDR Banks/M0_DQ14" "M0_DQ14" + U2 63 + U1 V2 +Net 403 "/DDR Banks/M0_DQ15" "M0_DQ15" + U2 65 + U1 V1 +Net 404 "/DDR Banks/M1_DQ0" "M1_DQ0" + U3 2 + U1 N20 +Net 405 "/DDR Banks/M1_DQ1" "M1_DQ1" + U3 4 + U1 N22 +Net 406 "/DDR Banks/M1_DQ2" "M1_DQ2" + U3 5 + U1 M21 +Net 407 "/DDR Banks/M1_DQ3" "M1_DQ3" + U3 7 + U1 M22 +Net 408 "/DDR Banks/M1_DQ4" "M1_DQ4" + U3 8 + U1 J20 +Net 409 "/DDR Banks/M1_DQ5" "M1_DQ5" + U3 10 + U1 J22 +Net 410 "/DDR Banks/M1_DQ6" "M1_DQ6" + U3 11 + U1 K21 +Net 411 "/DDR Banks/M1_DQ7" "M1_DQ7" + U3 13 + U1 K22 +Net 412 "/DDR Banks/M1_DQ8" "M1_DQ8" + U3 54 + U1 P21 +Net 413 "/DDR Banks/M1_DQ9" "M1_DQ9" + U3 56 + U1 P22 +Net 414 "/DDR Banks/M1_DQ10" "M1_DQ10" + U3 57 + U1 R20 +Net 415 "/DDR Banks/M1_DQ11" "M1_DQ11" + U3 59 + U1 R22 +Net 416 "/DDR Banks/M1_DQ12" "M1_DQ12" + U3 60 + U1 U20 +Net 417 "/DDR Banks/M1_DQ13" "M1_DQ13" + U3 62 + U1 U22 +Net 418 "/DDR Banks/M1_DQ14" "M1_DQ14" + U3 63 + U1 V21 +Net 419 "/DDR Banks/M1_DQ15" "M1_DQ15" + U3 65 + U1 V22 +Net 420 "/DDR Banks/M1_BA0" "M1_BA0" + U3 26 + U1 J17 +Net 421 "/DDR Banks/M1_BA1" "M1_BA1" + U3 27 + U1 K17 +Net 422 "/DDR Banks/M0_BA0" "M0_BA0" + U2 26 + U1 G3 +Net 423 "/DDR Banks/M0_BA1" "M0_BA1" + U2 27 + U1 G1 +Net 424 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" + U1 C8 + U4 17 +Net 425 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" + U1 C9 + U4 18 +Net 426 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" + U1 A9 + U4 19 +Net 427 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" + U1 D7 + U4 20 +Net 428 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" + U1 C7 + U4 6 +Net 429 "/FPGA Spartan6/ETH_RXD1" "ETH_RXD1" + U1 A6 + U4 5 +Net 430 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" + U1 B6 + U4 4 +Net 431 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" + U1 C6 + U4 3 +Net 432 "/Non volatile memories/SD_DAT0" "SD_DAT0" + J1 7 + U1 B16 +Net 433 "/Non volatile memories/SD_DAT1" "SD_DAT1" + J1 8 + U1 C16 +Net 434 "/Non volatile memories/SD_DAT2" "SD_DAT2" + J1 1 + U1 D15 +Net 435 "/Non volatile memories/SD_DAT3" "SD_DAT3" + J1 2 + U1 A15 } #End diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 0d5f22c..8cb538b 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,47 +1,5 @@ -EESchema Schematic File Version 2 date Tue 10 Aug 2010 06:50:48 PM COT -LIBS:power -LIBS:v0402mhs03 -LIBS:usb-48204-0001 -LIBS:microsmd075f -LIBS:mic2550ayts -LIBS:rj45-48025 -LIBS:xue-nv -LIBS:xc6slx75fgg484 -LIBS:xc6slx45fgg484 -LIBS:micron_mobile_ddr -LIBS:micron_ddr_512Mb -LIBS:k8001 -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:pasives-connectors -LIBS:xue-rnc-cache +EESchema Schematic File Version 2 date Tue 10 Aug 2010 09:23:11 PM COT +LIBS:power,../library/v0402mhs03,../library/usb-48204-0001,../library/microsmd075f,../library/mic2550ayts,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,../library/pasives-connectors,./xue-rnc.cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 @@ -55,8 +13,8 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Text Notes 12850 10750 0 60 ~ 0 -Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com +Wire Wire Line + 10600 6800 9300 6800 Wire Bus Line 9300 3100 10650 3100 Wire Wire Line @@ -73,8 +31,6 @@ Wire Wire Line 9300 7400 10600 7400 Wire Wire Line 10600 6900 9300 6900 -Wire Wire Line - 9300 6700 10600 6700 Wire Wire Line 9300 6500 10600 6500 Wire Bus Line @@ -139,8 +95,6 @@ Wire Wire Line 9300 6350 10600 6350 Wire Wire Line 9300 6600 10600 6600 -Wire Wire Line - 9300 6800 10600 6800 Wire Wire Line 9300 7000 10600 7000 Wire Wire Line @@ -161,6 +115,21 @@ Wire Bus Line 10600 7200 9300 7200 Wire Wire Line 9300 3000 10650 3000 +Wire Wire Line + 10600 6700 9300 6700 +$Sheet +S 10650 4800 1150 750 +U 4C5F1EDC +F0 "USB" 60 +F1 "USB.sch" 60 +F2 "USBA_SPD" B L 10650 5000 60 +F3 "USBA_OE_N" B L 10650 5100 60 +F4 "USBA_RCV" B L 10650 5200 60 +F5 "USBA_VP" B L 10650 5300 60 +F6 "USBA_VM" B L 10650 5400 60 +$EndSheet +Text Notes 12850 10750 0 60 ~ 0 +Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com $Sheet S 5950 2700 3350 5800 U 4C431A63 @@ -215,22 +184,8 @@ F47 "ETH_INT" B R 9300 6350 60 F48 "SD_CLK" B R 9300 2900 60 F49 "SD_CMD" B R 9300 3000 60 F50 "SD_DAT[0..3]" B R 9300 3100 60 -$EndSheet -Text HLabel 10650 5400 2 60 BiDi ~ 0 -USBA_VM -Text HLabel 10650 5300 2 60 BiDi ~ 0 -USBA_VP -Text HLabel 10650 5200 2 60 BiDi ~ 0 -USBA_RCV -Text HLabel 10650 5100 2 60 BiDi ~ 0 -USBA_OE_N -Text HLabel 10650 5000 2 60 BiDi ~ 0 -USBA_SPD -$Sheet -S 10650 4900 1150 650 -U 4C5F1EDC -F0 "USB" 60 -F1 "USB.sch" 60 +F51 "ETH_CRS" I R 9300 6700 60 +F52 "ETH_COL" I R 9300 6800 60 $EndSheet $Sheet S 10600 6250 1300 1800