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Code

only one wire connected

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This commit is contained in:
Andres Calderon 2010-07-28 06:48:02 -05:00
parent 939c04d645
commit 1580e66a1e
9 changed files with 629 additions and 589 deletions
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2
kicad/xue-rnc/DRAM.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 27 Jul 2010 08:07:47 PM COT EESchema Schematic File Version 2 date Wed 28 Jul 2010 06:08:38 AM COT
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors

14
kicad/xue-rnc/FPGA.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 27 Jul 2010 08:07:47 PM COT EESchema Schematic File Version 2 date Wed 28 Jul 2010 06:08:38 AM COT
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
@ -47,10 +47,6 @@ Wire Wire Line
10650 4400 10350 4400 10650 4400 10350 4400
Wire Wire Line Wire Wire Line
10650 4300 10350 4300 10650 4300 10350 4300
Text HLabel 10350 4300 0 60 Output ~ 0
M1_CLK
Text HLabel 10350 4400 0 60 Output ~ 0
M1_CLK#
Wire Wire Line Wire Wire Line
7400 4700 7700 4700 7400 4700 7700 4700
Connection ~ 7900 6300 Connection ~ 7900 6300
@ -460,6 +456,14 @@ Wire Wire Line
Connection ~ 8000 6300 Connection ~ 8000 6300
Wire Wire Line Wire Wire Line
7400 4800 7700 4800 7400 4800 7700 4800
Wire Wire Line
12050 6950 12200 6950
Text HLabel 12050 6950 0 60 Input ~ 0
ETH_INT
Text HLabel 10350 4300 0 60 Output ~ 0
M1_CLK
Text HLabel 10350 4400 0 60 Output ~ 0
M1_CLK#
Text HLabel 7700 4800 2 60 Output ~ 0 Text HLabel 7700 4800 2 60 Output ~ 0
M0_CLK M0_CLK
Text HLabel 7700 4700 2 60 Output ~ 0 Text HLabel 7700 4700 2 60 Output ~ 0

2
kicad/xue-rnc/NV_MEMORIES.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 27 Jul 2010 08:07:47 PM COT EESchema Schematic File Version 2 date Wed 28 Jul 2010 06:08:38 AM COT
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors

2
kicad/xue-rnc/eth_phy.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 27 Jul 2010 08:07:47 PM COT EESchema Schematic File Version 2 date Wed 28 Jul 2010 06:08:38 AM COT
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors

2
kicad/xue-rnc/xue-rnc-cache.lib
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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Tue 27 Jul 2010 08:07:47 PM COT EESchema-LIBRARY Version 2.3 Date: Wed 28 Jul 2010 06:08:38 AM COT
# #
# GND # GND
# #

517
kicad/xue-rnc/xue-rnc.brd
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File diff suppressed because it is too large Load Diff

612
kicad/xue-rnc/xue-rnc.net
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File diff suppressed because it is too large Load Diff

2
kicad/xue-rnc/xue-rnc.pro
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@ -1,4 +1,4 @@
update=Tue 27 Jul 2010 08:03:37 PM COT update=Wed 28 Jul 2010 06:43:00 AM COT
version=1 version=1
last_client=pcbnew last_client=pcbnew
[general] [general]

65
kicad/xue-rnc/xue-rnc.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Tue 27 Jul 2010 08:10:40 PM COT EESchema Schematic File Version 2 date Wed 28 Jul 2010 06:08:38 AM COT
LIBS:power LIBS:power
LIBS:device LIBS:device
LIBS:transistors LIBS:transistors
@ -44,44 +44,46 @@ Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
Wire Wire Line Wire Wire Line
2750 2100 4000 2100 7800 4550 7350 4550
Wire Wire Line
4000 4200 2750 4200
Wire Bus Line
4000 1200 4000 1150
Wire Bus Line
4000 1150 2750 1150
Wire Bus Line
2750 3250 4000 3250
Wire Bus Line
4000 3250 4000 3300
Wire Wire Line
2750 4100 4000 4100
Wire Wire Line Wire Wire Line
4000 2000 2750 2000 4000 2000 2750 2000
Wire Wire Line
2750 4100 4000 4100
Wire Bus Line
4000 3300 4000 3250
Wire Bus Line
4000 3250 2750 3250
Wire Bus Line
2750 1150 4000 1150
Wire Bus Line
4000 1150 4000 1200
Wire Wire Line
4000 4200 2750 4200
Wire Wire Line
2750 2100 4000 2100
$Sheet $Sheet
S 8650 3550 1450 2200 S 7800 4450 1450 2200
U 4C4320F3 U 4C4320F3
F0 "Ethernet Phy" 60 F0 "Ethernet Phy" 60
F1 "eth_phy.sch" 60 F1 "eth_phy.sch" 60
F2 "ETH_RXC" O L 8650 3700 60 F2 "ETH_RXC" O L 7800 4700 60
F3 "ETH_RST_N" I L 8650 3800 60 F3 "ETH_RST_N" I L 7800 4800 60
F4 "ETH_CRS" O L 8650 3900 60 F4 "ETH_CRS" O L 7800 4900 60
F5 "ETH_COL" O L 8650 4000 60 F5 "ETH_COL" O L 7800 5000 60
F6 "ETH_INT" O L 8650 4100 60 F6 "ETH_INT" O L 7800 4550 60
F7 "ETH_MDIO" B L 8650 4200 60 F7 "ETH_MDIO" B L 7800 5100 60
F8 "ETH_MDC" I L 8650 4300 60 F8 "ETH_MDC" I L 7800 5200 60
F9 "ETH_RXD[0..3]" O L 8650 4500 60 F9 "ETH_RXD[0..3]" O L 7800 5400 60
F10 "ETH_RXDV" O L 8650 4600 60 F10 "ETH_RXDV" O L 7800 5500 60
F11 "ETH_RXER" O L 8650 4700 60 F11 "ETH_RXER" O L 7800 5600 60
F12 "ETH_TXC" B L 8650 4800 60 F12 "ETH_TXC" B L 7800 5700 60
F13 "ETH_TXD[0..3]" I L 8650 4900 60 F13 "ETH_TXD[0..3]" I L 7800 5800 60
F14 "ETH_TXEN" I L 8650 5000 60 F14 "ETH_TXEN" I L 7800 5900 60
F15 "ETH_TXER" I L 8650 5100 60 F15 "ETH_TXER" I L 7800 6000 60
F16 "ETH_CLK" I L 8650 5200 60 F16 "ETH_CLK" I L 7800 6100 60
$EndSheet $EndSheet
$Sheet $Sheet
S 4000 900 3500 4000 S 4000 900 3350 5800
U 4C431A63 U 4C431A63
F0 "FPGA Spartan6" 60 F0 "FPGA Spartan6" 60
F1 "FPGA.sch" 60 F1 "FPGA.sch" 60
@ -89,6 +91,7 @@ F2 "M1_CLK" O L 4000 2000 60
F3 "M1_CLK#" O L 4000 2100 60 F3 "M1_CLK#" O L 4000 2100 60
F4 "M0_CLK" O L 4000 4100 60 F4 "M0_CLK" O L 4000 4100 60
F5 "M0_CLK#" O L 4000 4200 60 F5 "M0_CLK#" O L 4000 4200 60
F6 "ETH_INT" I R 7350 4550 60
$EndSheet $EndSheet
$Sheet $Sheet
S 8700 900 1150 1850 S 8700 900 1150 1850