diff --git a/kicad/modules/MICROSD-500901.mdc b/kicad/modules/MICROSD-500901.mdc
new file mode 100644
index 0000000..8b5064c
--- /dev/null
+++ b/kicad/modules/MICROSD-500901.mdc
@@ -0,0 +1,3 @@
+PCBNEW-LibDoc----V1  27/9/2008-16:35:21
+#
+$EndLIBDOC
diff --git a/kicad/modules/TSSOP-14.mdc b/kicad/modules/TSSOP-14.mdc
new file mode 100644
index 0000000..8b5064c
--- /dev/null
+++ b/kicad/modules/TSSOP-14.mdc
@@ -0,0 +1,3 @@
+PCBNEW-LibDoc----V1  27/9/2008-16:35:21
+#
+$EndLIBDOC
diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch
index c5d0d43..a8f5939 100644
--- a/kicad/xue-rnc/DRAM.sch
+++ b/kicad/xue-rnc/DRAM.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:20:06 PM COT
+EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:53:48 PM COT
 LIBS:power
 LIBS:v0402mhs03
 LIBS:usb-48204-0001
@@ -389,10 +389,10 @@ $EndComp
 Text HLabel 4950 5700 2    60   BiDi ~ 0
 M0_DQ[0..15]
 $Comp
-L GND #PWR1
+L GND #PWR04
 U 1 1 4C58A712
 P 3000 5200
-F 0 "#PWR1" H 3000 5200 30  0001 C CNN
+F 0 "#PWR04" H 3000 5200 30  0001 C CNN
 F 1 "GND" H 3000 5130 30  0001 C CNN
 	1    3000 5200
 	1    0    0    -1  
@@ -686,10 +686,10 @@ Entry Wire Line
 Entry Wire Line
 	9950 3650 10050 3750
 $Comp
-L GND #PWR2
+L GND #PWR05
 U 1 1 4C437C3F
 P 8250 5200
-F 0 "#PWR2" H 8250 5200 30  0001 C CNN
+F 0 "#PWR05" H 8250 5200 30  0001 C CNN
 F 1 "GND" H 8250 5130 30  0001 C CNN
 	1    8250 5200
 	1    0    0    -1  
diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch
index 197a862..84b90e3 100644
--- a/kicad/xue-rnc/FPGA.sch
+++ b/kicad/xue-rnc/FPGA.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:20:06 PM COT
+EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:53:48 PM COT
 LIBS:power
 LIBS:v0402mhs03
 LIBS:usb-48204-0001
@@ -1280,10 +1280,10 @@ M0_CLK
 Text HLabel 7750 4700 2    60   Output ~ 0
 M0_CLK#
 $Comp
-L GND #PWR5
+L GND #PWR01
 U 1 1 4C439B7E
 P 13450 15700
-F 0 "#PWR5" H 13450 15700 30  0001 C CNN
+F 0 "#PWR01" H 13450 15700 30  0001 C CNN
 F 1 "GND" H 13450 15630 30  0001 C CNN
 	1    13450 15700
 	1    0    0    -1  
diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch
index f143890..6c684e1 100644
--- a/kicad/xue-rnc/NV_MEMORIES.sch
+++ b/kicad/xue-rnc/NV_MEMORIES.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:20:06 PM COT
+EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:53:48 PM COT
 LIBS:power
 LIBS:v0402mhs03
 LIBS:usb-48204-0001
@@ -172,19 +172,19 @@ Wire Wire Line
 	4400 5750 4400 5950
 Connection ~ 4400 5850
 $Comp
-L GND #PWR4
+L GND #PWR02
 U 1 1 4C438ADC
 P 4400 5950
-F 0 "#PWR4" H 4400 5950 30  0001 C CNN
+F 0 "#PWR02" H 4400 5950 30  0001 C CNN
 F 1 "GND" H 4400 5880 30  0001 C CNN
 	1    4400 5950
 	1    0    0    -1  
 $EndComp
 $Comp
-L GND #PWR3
+L GND #PWR03
 U 1 1 4C438AD5
 P 3950 6300
-F 0 "#PWR3" H 3950 6300 30  0001 C CNN
+F 0 "#PWR03" H 3950 6300 30  0001 C CNN
 F 1 "GND" H 3950 6230 30  0001 C CNN
 	1    3950 6300
 	1    0    0    -1  
diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch
index 3cf166e..906ebbd 100644
--- a/kicad/xue-rnc/USB.sch
+++ b/kicad/xue-rnc/USB.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:20:06 PM COT
+EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:53:48 PM COT
 LIBS:power
 LIBS:v0402mhs03
 LIBS:usb-48204-0001
diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch
index 79a3239..734ed1b 100644
--- a/kicad/xue-rnc/eth_phy.sch
+++ b/kicad/xue-rnc/eth_phy.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:20:06 PM COT
+EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:53:48 PM COT
 LIBS:power
 LIBS:v0402mhs03
 LIBS:usb-48204-0001
diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib
index 32605ee..b82181b 100644
--- a/kicad/xue-rnc/xue-rnc-cache.lib
+++ b/kicad/xue-rnc/xue-rnc-cache.lib
@@ -1,4 +1,4 @@
-EESchema-LIBRARY Version 2.3  Date: Mon 09 Aug 2010 09:20:06 PM COT
+EESchema-LIBRARY Version 2.3  Date: Mon 09 Aug 2010 09:53:48 PM COT
 #
 # C
 #
diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd
index eefbf42..b740fa3 100644
--- a/kicad/xue-rnc/xue-rnc.brd
+++ b/kicad/xue-rnc/xue-rnc.brd
@@ -1,4 +1,4 @@
-PCBNEW-BOARD Version 1 date Mon 09 Aug 2010 09:26:54 PM COT
+PCBNEW-BOARD Version 1 date Mon 09 Aug 2010 09:50:49 PM COT
 
 # Created by Pcbnew(2010-07-15 BZR 2414)-unstable
 
@@ -6,15 +6,15 @@ $GENERAL
 LayerCount 4
 Ly 1FFF8007
 EnabledLayers 1FFF8007
-Links 270
-NoConn 270
-Di 37146 11079 66209 48914
+Links 329
+NoConn 329
+Di -1231 -600 66209 48914
 Ndraw 0
 Ntrack 0
 Nzone 0
 BoardThickness 630
-Nmodule 8
-Nnets 105
+Nmodule 39
+Nnets 108
 $EndGENERAL
 
 $SHEETDESCR
@@ -72,67 +72,67 @@ Na 1 "/DDR_Ban11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 2 "/DDR_Ban12"
+Na 2 "/DDR_Ban15"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 3 "/DDR_Ban27"
+Na 3 "/DDR_Ban16"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 4 "/DDR_Ban28"
+Na 4 "/DDR_Ban22"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 5 "/DDR_Ban31"
+Na 5 "/DDR_Ban23"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 6 "/DDR_Ban34"
+Na 6 "/DDR_Ban25"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 7 "/DDR_Ban36"
+Na 7 "/DDR_Ban26"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 8 "/DDR_Ban38"
+Na 8 "/DDR_Ban30"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 9 "/DDR_Ban43"
+Na 9 "/DDR_Ban34"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 10 "/DDR_Ban44"
+Na 10 "/DDR_Ban35"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 11 "/DDR_Ban47"
+Na 11 "/DDR_Ban42"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 12 "/DDR_Ban48"
+Na 12 "/DDR_Ban44"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 13 "/DDR_Ban57"
+Na 13 "/DDR_Ban45"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 14 "/DDR_Ban62"
+Na 14 "/DDR_Ban46"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 15 "/DDR_Ban63"
+Na 15 "/DDR_Ban49"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 16 "/DDR_Ban65"
+Na 16 "/DDR_Ban51"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 17 "/DDR_Ban67"
+Na 17 "/DDR_Ban64"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -140,159 +140,159 @@ Na 18 "/DDR_Ban68"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 19 "/DDR_Ban70"
+Na 19 "/DDR_Ban71"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 20 "/DDR_Ban72"
+Na 20 "/DDR_Banks/M0_A0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 21 "/DDR_Ban75"
+Na 21 "/DDR_Banks/M0_A4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 22 "/DDR_Ban76"
+Na 22 "/DDR_Banks/M0_A7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 23 "/DDR_Ban78"
+Na 23 "/DDR_Banks/M0_A8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 24 "/DDR_Ban8"
+Na 24 "/DDR_Banks/M1_A0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 25 "/DDR_Banks/M0_A8"
+Na 25 "/DDR_Banks/M1_A1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 26 "/DDR_Banks/M0_A9"
+Na 26 "/DDR_Banks/M1_A2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 27 "/DDR_Banks/M1_A3"
+Na 27 "/DDR_Banks/M1_A5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 28 "/DDR_Banks/M1_A5"
+Na 28 "/DDR_Banks/M1_A6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 29 "/ETH_MDIO"
+Na 29 "/DDR_Banks/M1_A7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 30 "/Etherne1"
+Na 30 "/DDR_Banks/M1_A9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 31 "/Etherne2"
+Na 31 "/ETH_MDIO"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 32 "/Etherne3"
+Na 32 "/Etherne1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 33 "/Etherne4"
+Na 33 "/Etherne2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 34 "/Etherne5"
+Na 34 "/Etherne3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 35 "/Etherne6"
+Na 35 "/Etherne4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 36 "/Etherne7"
+Na 36 "/Etherne5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 37 "/FPGA_Sp10"
+Na 37 "/Etherne6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 38 "/FPGA_Sp13"
+Na 38 "/Etherne7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 39 "/FPGA_Sp14"
+Na 39 "/FPGA_Sp10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 40 "/FPGA_Sp15"
+Na 40 "/FPGA_Sp12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 41 "/FPGA_Sp16"
+Na 41 "/FPGA_Sp13"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 42 "/FPGA_Sp17"
+Na 42 "/FPGA_Sp14"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 43 "/FPGA_Sp18"
+Na 43 "/FPGA_Sp17"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 44 "/FPGA_Sp19"
+Na 44 "/FPGA_Sp18"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 45 "/FPGA_Sp20"
+Na 45 "/FPGA_Sp19"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 46 "/FPGA_Sp21"
+Na 46 "/FPGA_Sp20"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 47 "/FPGA_Sp22"
+Na 47 "/FPGA_Sp21"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 48 "/FPGA_Sp23"
+Na 48 "/FPGA_Sp24"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 49 "/FPGA_Sp24"
+Na 49 "/FPGA_Sp27"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 50 "/FPGA_Sp25"
+Na 50 "/FPGA_Sp28"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 51 "/FPGA_Sp26"
+Na 51 "/FPGA_Sp29"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 52 "/FPGA_Sp29"
+Na 52 "/FPGA_Sp31"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 53 "/FPGA_Sp30"
+Na 53 "/FPGA_Sp32"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 54 "/FPGA_Sp32"
+Na 54 "/FPGA_Sp33"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 55 "/FPGA_Sp33"
+Na 55 "/FPGA_Sp36"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 56 "/FPGA_Sp35"
+Na 56 "/FPGA_Sp37"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 57 "/FPGA_Sp37"
+Na 57 "/FPGA_Sp38"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -308,91 +308,91 @@ Na 60 "/FPGA_Sp41"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 61 "/FPGA_Sp42"
+Na 61 "/FPGA_Sp43"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 62 "/FPGA_Sp45"
+Na 62 "/FPGA_Sp47"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 63 "/FPGA_Sp46"
+Na 63 "/FPGA_Sp48"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 64 "/FPGA_Sp49"
+Na 64 "/FPGA_Sp50"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 65 "/FPGA_Sp50"
+Na 65 "/FPGA_Sp52"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 66 "/FPGA_Sp51"
+Na 66 "/FPGA_Sp53"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 67 "/FPGA_Sp52"
+Na 67 "/FPGA_Sp54"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 68 "/FPGA_Sp53"
+Na 68 "/FPGA_Sp55"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 69 "/FPGA_Sp54"
+Na 69 "/FPGA_Sp56"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 70 "/FPGA_Sp55"
+Na 70 "/FPGA_Sp57"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 71 "/FPGA_Sp56"
+Na 71 "/FPGA_Sp58"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 72 "/FPGA_Sp58"
+Na 72 "/FPGA_Sp59"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 73 "/FPGA_Sp59"
+Na 73 "/FPGA_Sp60"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 74 "/FPGA_Sp60"
+Na 74 "/FPGA_Sp61"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 75 "/FPGA_Sp61"
+Na 75 "/FPGA_Sp62"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 76 "/FPGA_Sp64"
+Na 76 "/FPGA_Sp63"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 77 "/FPGA_Sp66"
+Na 77 "/FPGA_Sp65"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 78 "/FPGA_Sp69"
+Na 78 "/FPGA_Sp66"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 79 "/FPGA_Sp71"
+Na 79 "/FPGA_Sp67"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 80 "/FPGA_Sp73"
+Na 80 "/FPGA_Sp69"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 81 "/FPGA_Sp74"
+Na 81 "/FPGA_Sp70"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 82 "/FPGA_Sp77"
+Na 82 "/FPGA_Sp8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -400,7 +400,7 @@ Na 83 "/FPGA_Sp9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 84 "/Non_vol79"
+Na 84 "/Non_vol72"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -476,11 +476,23 @@ Na 102 "N-000406"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 103 "N-000420"
+Na 103 "N-000416"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 104 "N-000426"
+Na 104 "N-000417"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 105 "N-000420"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 106 "N-000426"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 107 "N-000428"
 St ~
 $EndEQUIPOT
 $NCLASS
@@ -494,33 +506,35 @@ uViaDia 200
 uViaDrill 50
 AddNet ""
 AddNet "/DDR_Ban11"
-AddNet "/DDR_Ban12"
-AddNet "/DDR_Ban27"
-AddNet "/DDR_Ban28"
-AddNet "/DDR_Ban31"
+AddNet "/DDR_Ban15"
+AddNet "/DDR_Ban16"
+AddNet "/DDR_Ban22"
+AddNet "/DDR_Ban23"
+AddNet "/DDR_Ban25"
+AddNet "/DDR_Ban26"
+AddNet "/DDR_Ban30"
 AddNet "/DDR_Ban34"
-AddNet "/DDR_Ban36"
-AddNet "/DDR_Ban38"
-AddNet "/DDR_Ban43"
+AddNet "/DDR_Ban35"
+AddNet "/DDR_Ban42"
 AddNet "/DDR_Ban44"
-AddNet "/DDR_Ban47"
-AddNet "/DDR_Ban48"
-AddNet "/DDR_Ban57"
-AddNet "/DDR_Ban62"
-AddNet "/DDR_Ban63"
-AddNet "/DDR_Ban65"
-AddNet "/DDR_Ban67"
+AddNet "/DDR_Ban45"
+AddNet "/DDR_Ban46"
+AddNet "/DDR_Ban49"
+AddNet "/DDR_Ban51"
+AddNet "/DDR_Ban64"
 AddNet "/DDR_Ban68"
-AddNet "/DDR_Ban70"
-AddNet "/DDR_Ban72"
-AddNet "/DDR_Ban75"
-AddNet "/DDR_Ban76"
-AddNet "/DDR_Ban78"
-AddNet "/DDR_Ban8"
+AddNet "/DDR_Ban71"
+AddNet "/DDR_Banks/M0_A0"
+AddNet "/DDR_Banks/M0_A4"
+AddNet "/DDR_Banks/M0_A7"
 AddNet "/DDR_Banks/M0_A8"
-AddNet "/DDR_Banks/M0_A9"
-AddNet "/DDR_Banks/M1_A3"
+AddNet "/DDR_Banks/M1_A0"
+AddNet "/DDR_Banks/M1_A1"
+AddNet "/DDR_Banks/M1_A2"
 AddNet "/DDR_Banks/M1_A5"
+AddNet "/DDR_Banks/M1_A6"
+AddNet "/DDR_Banks/M1_A7"
+AddNet "/DDR_Banks/M1_A9"
 AddNet "/ETH_MDIO"
 AddNet "/Etherne1"
 AddNet "/Etherne2"
@@ -530,53 +544,51 @@ AddNet "/Etherne5"
 AddNet "/Etherne6"
 AddNet "/Etherne7"
 AddNet "/FPGA_Sp10"
+AddNet "/FPGA_Sp12"
 AddNet "/FPGA_Sp13"
 AddNet "/FPGA_Sp14"
-AddNet "/FPGA_Sp15"
-AddNet "/FPGA_Sp16"
 AddNet "/FPGA_Sp17"
 AddNet "/FPGA_Sp18"
 AddNet "/FPGA_Sp19"
 AddNet "/FPGA_Sp20"
 AddNet "/FPGA_Sp21"
-AddNet "/FPGA_Sp22"
-AddNet "/FPGA_Sp23"
 AddNet "/FPGA_Sp24"
-AddNet "/FPGA_Sp25"
-AddNet "/FPGA_Sp26"
+AddNet "/FPGA_Sp27"
+AddNet "/FPGA_Sp28"
 AddNet "/FPGA_Sp29"
-AddNet "/FPGA_Sp30"
+AddNet "/FPGA_Sp31"
 AddNet "/FPGA_Sp32"
 AddNet "/FPGA_Sp33"
-AddNet "/FPGA_Sp35"
+AddNet "/FPGA_Sp36"
 AddNet "/FPGA_Sp37"
+AddNet "/FPGA_Sp38"
 AddNet "/FPGA_Sp39"
 AddNet "/FPGA_Sp40"
 AddNet "/FPGA_Sp41"
-AddNet "/FPGA_Sp42"
-AddNet "/FPGA_Sp45"
-AddNet "/FPGA_Sp46"
-AddNet "/FPGA_Sp49"
+AddNet "/FPGA_Sp43"
+AddNet "/FPGA_Sp47"
+AddNet "/FPGA_Sp48"
 AddNet "/FPGA_Sp50"
-AddNet "/FPGA_Sp51"
 AddNet "/FPGA_Sp52"
 AddNet "/FPGA_Sp53"
 AddNet "/FPGA_Sp54"
 AddNet "/FPGA_Sp55"
 AddNet "/FPGA_Sp56"
+AddNet "/FPGA_Sp57"
 AddNet "/FPGA_Sp58"
 AddNet "/FPGA_Sp59"
 AddNet "/FPGA_Sp60"
 AddNet "/FPGA_Sp61"
-AddNet "/FPGA_Sp64"
+AddNet "/FPGA_Sp62"
+AddNet "/FPGA_Sp63"
+AddNet "/FPGA_Sp65"
 AddNet "/FPGA_Sp66"
+AddNet "/FPGA_Sp67"
 AddNet "/FPGA_Sp69"
-AddNet "/FPGA_Sp71"
-AddNet "/FPGA_Sp73"
-AddNet "/FPGA_Sp74"
-AddNet "/FPGA_Sp77"
+AddNet "/FPGA_Sp70"
+AddNet "/FPGA_Sp8"
 AddNet "/FPGA_Sp9"
-AddNet "/Non_vol79"
+AddNet "/Non_vol72"
 AddNet "3.3V"
 AddNet "GND"
 AddNet "N-000048"
@@ -595,8 +607,11 @@ AddNet "N-000402"
 AddNet "N-000404"
 AddNet "N-000405"
 AddNet "N-000406"
+AddNet "N-000416"
+AddNet "N-000417"
 AddNet "N-000420"
 AddNet "N-000426"
+AddNet "N-000428"
 $EndNCLASS
 $MODULE FGG484bga-p10
 Po 56450 33930 0 15 4C4325AE 4C431E53 ~~
@@ -647,7 +662,7 @@ $PAD
 Sh "A5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 36 "/Etherne7"
+Ne 38 "/Etherne7"
 Po -2558 -4133
 $EndPAD
 $PAD
@@ -927,7 +942,7 @@ $PAD
 Sh "C1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 24 "/DDR_Ban8"
+Ne 82 "/FPGA_Sp8"
 Po -4133 -3346
 $EndPAD
 $PAD
@@ -1074,21 +1089,21 @@ $PAD
 Sh "C22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 37 "/FPGA_Sp10"
+Ne 30 "/DDR_Banks/M1_A9"
 Po 4133 -3346
 $EndPAD
 $PAD
 Sh "D1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 1 "/DDR_Ban11"
+Ne 39 "/FPGA_Sp10"
 Po -4133 -2952
 $EndPAD
 $PAD
 Sh "D2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 2 "/DDR_Ban12"
+Ne 1 "/DDR_Ban11"
 Po -3739 -2952
 $EndPAD
 $PAD
@@ -1221,21 +1236,21 @@ $PAD
 Sh "D21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 38 "/FPGA_Sp13"
+Ne 40 "/FPGA_Sp12"
 Po 3739 -2952
 $EndPAD
 $PAD
 Sh "D22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 39 "/FPGA_Sp14"
+Ne 41 "/FPGA_Sp13"
 Po 4133 -2952
 $EndPAD
 $PAD
 Sh "E1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 26 "/DDR_Banks/M0_A9"
+Ne 42 "/FPGA_Sp14"
 Po -4133 -2558
 $EndPAD
 $PAD
@@ -1249,7 +1264,7 @@ $PAD
 Sh "E3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 25 "/DDR_Banks/M0_A8"
+Ne 23 "/DDR_Banks/M0_A8"
 Po -3346 -2558
 $EndPAD
 $PAD
@@ -1368,7 +1383,7 @@ $PAD
 Sh "E20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 40 "/FPGA_Sp15"
+Ne 29 "/DDR_Banks/M1_A7"
 Po 3346 -2558
 $EndPAD
 $PAD
@@ -1382,7 +1397,7 @@ $PAD
 Sh "E22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 41 "/FPGA_Sp16"
+Ne 26 "/DDR_Banks/M1_A2"
 Po 4133 -2558
 $EndPAD
 $PAD
@@ -1396,14 +1411,14 @@ $PAD
 Sh "F2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 42 "/FPGA_Sp17"
+Ne 2 "/DDR_Ban15"
 Po -3739 -2165
 $EndPAD
 $PAD
 Sh "F3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 43 "/FPGA_Sp18"
+Ne 21 "/DDR_Banks/M0_A4"
 Po -3346 -2165
 $EndPAD
 $PAD
@@ -1515,28 +1530,28 @@ $PAD
 Sh "F19" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 44 "/FPGA_Sp19"
+Ne 3 "/DDR_Ban16"
 Po 2952 -2165
 $EndPAD
 $PAD
 Sh "F20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 45 "/FPGA_Sp20"
+Ne 43 "/FPGA_Sp17"
 Po 3346 -2165
 $EndPAD
 $PAD
 Sh "F21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 46 "/FPGA_Sp21"
+Ne 24 "/DDR_Banks/M1_A0"
 Po 3739 -2165
 $EndPAD
 $PAD
 Sh "F22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 47 "/FPGA_Sp22"
+Ne 25 "/DDR_Banks/M1_A1"
 Po 4133 -2165
 $EndPAD
 $PAD
@@ -1564,7 +1579,7 @@ $PAD
 Sh "G4" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 48 "/FPGA_Sp23"
+Ne 44 "/FPGA_Sp18"
 Po -2952 -1771
 $EndPAD
 $PAD
@@ -1669,14 +1684,14 @@ $PAD
 Sh "G19" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 49 "/FPGA_Sp24"
+Ne 45 "/FPGA_Sp19"
 Po 2952 -1771
 $EndPAD
 $PAD
 Sh "G20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 27 "/DDR_Banks/M1_A3"
+Ne 46 "/FPGA_Sp20"
 Po 3346 -1771
 $EndPAD
 $PAD
@@ -1697,42 +1712,42 @@ $PAD
 Sh "H1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "/FPGA_Sp25"
+Ne 47 "/FPGA_Sp21"
 Po -4133 -1377
 $EndPAD
 $PAD
 Sh "H2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "/FPGA_Sp26"
+Ne 20 "/DDR_Banks/M0_A0"
 Po -3739 -1377
 $EndPAD
 $PAD
 Sh "H3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 3 "/DDR_Ban27"
+Ne 4 "/DDR_Ban22"
 Po -3346 -1377
 $EndPAD
 $PAD
 Sh "H4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 4 "/DDR_Ban28"
+Ne 5 "/DDR_Ban23"
 Po -2952 -1377
 $EndPAD
 $PAD
 Sh "H5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "/FPGA_Sp29"
+Ne 48 "/FPGA_Sp24"
 Po -2558 -1377
 $EndPAD
 $PAD
 Sh "H6" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "/FPGA_Sp30"
+Ne 22 "/DDR_Banks/M0_A7"
 Po -2165 -1377
 $EndPAD
 $PAD
@@ -1823,35 +1838,35 @@ $PAD
 Sh "H19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 5 "/DDR_Ban31"
+Ne 6 "/DDR_Ban25"
 Po 2952 -1377
 $EndPAD
 $PAD
 Sh "H20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "/FPGA_Sp32"
+Ne 7 "/DDR_Ban26"
 Po 3346 -1377
 $EndPAD
 $PAD
 Sh "H21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "/FPGA_Sp33"
+Ne 49 "/FPGA_Sp27"
 Po 3739 -1377
 $EndPAD
 $PAD
 Sh "H22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 6 "/DDR_Ban34"
+Ne 50 "/FPGA_Sp28"
 Po 4133 -1377
 $EndPAD
 $PAD
 Sh "J1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "/FPGA_Sp35"
+Ne 51 "/FPGA_Sp29"
 Po -4133 -983
 $EndPAD
 $PAD
@@ -1865,14 +1880,14 @@ $PAD
 Sh "J3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 7 "/DDR_Ban36"
+Ne 8 "/DDR_Ban30"
 Po -3346 -983
 $EndPAD
 $PAD
 Sh "J4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "/FPGA_Sp37"
+Ne 52 "/FPGA_Sp31"
 Po -2952 -983
 $EndPAD
 $PAD
@@ -1977,7 +1992,7 @@ $PAD
 Sh "J19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 8 "/DDR_Ban38"
+Ne 53 "/FPGA_Sp32"
 Po 2952 -983
 $EndPAD
 $PAD
@@ -1998,49 +2013,49 @@ $PAD
 Sh "J22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "/FPGA_Sp39"
+Ne 54 "/FPGA_Sp33"
 Po 4133 -983
 $EndPAD
 $PAD
 Sh "K1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "/FPGA_Sp40"
+Ne 9 "/DDR_Ban34"
 Po -4133 -590
 $EndPAD
 $PAD
 Sh "K2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 60 "/FPGA_Sp41"
+Ne 10 "/DDR_Ban35"
 Po -3739 -590
 $EndPAD
 $PAD
 Sh "K3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 61 "/FPGA_Sp42"
+Ne 55 "/FPGA_Sp36"
 Po -3346 -590
 $EndPAD
 $PAD
 Sh "K4" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 9 "/DDR_Ban43"
+Ne 56 "/FPGA_Sp37"
 Po -2952 -590
 $EndPAD
 $PAD
 Sh "K5" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 10 "/DDR_Ban44"
+Ne 57 "/FPGA_Sp38"
 Po -2558 -590
 $EndPAD
 $PAD
 Sh "K6" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 62 "/FPGA_Sp45"
+Ne 58 "/FPGA_Sp39"
 Po -2165 -590
 $EndPAD
 $PAD
@@ -2131,28 +2146,28 @@ $PAD
 Sh "K19" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 63 "/FPGA_Sp46"
+Ne 28 "/DDR_Banks/M1_A6"
 Po 2952 -590
 $EndPAD
 $PAD
 Sh "K20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 28 "/DDR_Banks/M1_A5"
+Ne 27 "/DDR_Banks/M1_A5"
 Po 3346 -590
 $EndPAD
 $PAD
 Sh "K21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 11 "/DDR_Ban47"
+Ne 59 "/FPGA_Sp40"
 Po 3739 -590
 $EndPAD
 $PAD
 Sh "K22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 12 "/DDR_Ban48"
+Ne 60 "/FPGA_Sp41"
 Po 4133 -590
 $EndPAD
 $PAD
@@ -2173,14 +2188,14 @@ $PAD
 Sh "L3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 64 "/FPGA_Sp49"
+Ne 11 "/DDR_Ban42"
 Po -3346 -196
 $EndPAD
 $PAD
 Sh "L4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 65 "/FPGA_Sp50"
+Ne 61 "/FPGA_Sp43"
 Po -2952 -196
 $EndPAD
 $PAD
@@ -2285,14 +2300,14 @@ $PAD
 Sh "L19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 66 "/FPGA_Sp51"
+Ne 12 "/DDR_Ban44"
 Po 2952 -196
 $EndPAD
 $PAD
 Sh "L20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 67 "/FPGA_Sp52"
+Ne 13 "/DDR_Ban45"
 Po 3346 -196
 $EndPAD
 $PAD
@@ -2313,21 +2328,21 @@ $PAD
 Sh "M1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 68 "/FPGA_Sp53"
+Ne 14 "/DDR_Ban46"
 Po -4133 196
 $EndPAD
 $PAD
 Sh "M2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 69 "/FPGA_Sp54"
+Ne 62 "/FPGA_Sp47"
 Po -3739 196
 $EndPAD
 $PAD
 Sh "M3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 70 "/FPGA_Sp55"
+Ne 63 "/FPGA_Sp48"
 Po -3346 196
 $EndPAD
 $PAD
@@ -2446,7 +2461,7 @@ $PAD
 Sh "M20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 71 "/FPGA_Sp56"
+Ne 15 "/DDR_Ban49"
 Po 3346 196
 $EndPAD
 $PAD
@@ -2467,7 +2482,7 @@ $PAD
 Sh "N1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 13 "/DDR_Ban57"
+Ne 64 "/FPGA_Sp50"
 Po -4133 590
 $EndPAD
 $PAD
@@ -2481,7 +2496,7 @@ $PAD
 Sh "N3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 72 "/FPGA_Sp58"
+Ne 16 "/DDR_Ban51"
 Po -3346 590
 $EndPAD
 $PAD
@@ -2600,7 +2615,7 @@ $PAD
 Sh "N20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 73 "/FPGA_Sp59"
+Ne 65 "/FPGA_Sp52"
 Po 3346 590
 $EndPAD
 $PAD
@@ -2614,21 +2629,21 @@ $PAD
 Sh "N22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 74 "/FPGA_Sp60"
+Ne 66 "/FPGA_Sp53"
 Po 4133 590
 $EndPAD
 $PAD
 Sh "P1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 75 "/FPGA_Sp61"
+Ne 67 "/FPGA_Sp54"
 Po -4133 983
 $EndPAD
 $PAD
 Sh "P2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 14 "/DDR_Ban62"
+Ne 68 "/FPGA_Sp55"
 Po -3739 983
 $EndPAD
 $PAD
@@ -2761,21 +2776,21 @@ $PAD
 Sh "P21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 15 "/DDR_Ban63"
+Ne 69 "/FPGA_Sp56"
 Po 3739 983
 $EndPAD
 $PAD
 Sh "P22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 76 "/FPGA_Sp64"
+Ne 70 "/FPGA_Sp57"
 Po 4133 983
 $EndPAD
 $PAD
 Sh "R1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 16 "/DDR_Ban65"
+Ne 71 "/FPGA_Sp58"
 Po -4133 1377
 $EndPAD
 $PAD
@@ -2789,7 +2804,7 @@ $PAD
 Sh "R3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 77 "/FPGA_Sp66"
+Ne 72 "/FPGA_Sp59"
 Po -3346 1377
 $EndPAD
 $PAD
@@ -2908,7 +2923,7 @@ $PAD
 Sh "R20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 17 "/DDR_Ban67"
+Ne 73 "/FPGA_Sp60"
 Po 3346 1377
 $EndPAD
 $PAD
@@ -2922,7 +2937,7 @@ $PAD
 Sh "R22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 18 "/DDR_Ban68"
+Ne 74 "/FPGA_Sp61"
 Po 4133 1377
 $EndPAD
 $PAD
@@ -2936,7 +2951,7 @@ $PAD
 Sh "T2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 78 "/FPGA_Sp69"
+Ne 75 "/FPGA_Sp62"
 Po -3739 1771
 $EndPAD
 $PAD
@@ -3069,7 +3084,7 @@ $PAD
 Sh "T21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 19 "/DDR_Ban70"
+Ne 76 "/FPGA_Sp63"
 Po 3739 1771
 $EndPAD
 $PAD
@@ -3083,7 +3098,7 @@ $PAD
 Sh "U1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 79 "/FPGA_Sp71"
+Ne 17 "/DDR_Ban64"
 Po -4133 2165
 $EndPAD
 $PAD
@@ -3097,7 +3112,7 @@ $PAD
 Sh "U3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 20 "/DDR_Ban72"
+Ne 77 "/FPGA_Sp65"
 Po -3346 2165
 $EndPAD
 $PAD
@@ -3216,7 +3231,7 @@ $PAD
 Sh "U20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 80 "/FPGA_Sp73"
+Ne 78 "/FPGA_Sp66"
 Po 3346 2165
 $EndPAD
 $PAD
@@ -3230,21 +3245,21 @@ $PAD
 Sh "U22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 81 "/FPGA_Sp74"
+Ne 79 "/FPGA_Sp67"
 Po 4133 2165
 $EndPAD
 $PAD
 Sh "V1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 21 "/DDR_Ban75"
+Ne 18 "/DDR_Ban68"
 Po -4133 2558
 $EndPAD
 $PAD
 Sh "V2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 22 "/DDR_Ban76"
+Ne 80 "/FPGA_Sp69"
 Po -3739 2558
 $EndPAD
 $PAD
@@ -3377,14 +3392,14 @@ $PAD
 Sh "V21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 82 "/FPGA_Sp77"
+Ne 81 "/FPGA_Sp70"
 Po 3739 2558
 $EndPAD
 $PAD
 Sh "V22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 23 "/DDR_Ban78"
+Ne 19 "/DDR_Ban71"
 Po 4133 2558
 $EndPAD
 $PAD
@@ -4099,7 +4114,7 @@ $PAD
 Sh "1" R 315 98 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 29 "/ETH_MDIO"
+Ne 31 "/ETH_MDIO"
 Po -1613 -1082
 $EndPAD
 $PAD
@@ -4113,7 +4128,7 @@ $PAD
 Sh "47" R 99 315 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 33 "/Etherne4"
+Ne 35 "/Etherne4"
 Po -885 -1613
 $EndPAD
 $PAD
@@ -4176,7 +4191,7 @@ $PAD
 Sh "38" R 99 315 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 32 "/Etherne3"
+Ne 34 "/Etherne3"
 Po 885 -1613
 $EndPAD
 $PAD
@@ -4190,21 +4205,21 @@ $PAD
 Sh "25" R 315 98 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 36 "/Etherne7"
+Ne 38 "/Etherne7"
 Po 1613 1082
 $EndPAD
 $PAD
 Sh "26" R 315 99 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 34 "/Etherne5"
+Ne 36 "/Etherne5"
 Po 1613 885
 $EndPAD
 $PAD
 Sh "27" R 315 99 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 35 "/Etherne6"
+Ne 37 "/Etherne6"
 Po 1613 688
 $EndPAD
 $PAD
@@ -4232,7 +4247,7 @@ $PAD
 Sh "31" R 315 98 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 31 "/Etherne2"
+Ne 33 "/Etherne2"
 Po 1613 -98
 $EndPAD
 $PAD
@@ -4274,7 +4289,7 @@ $PAD
 Sh "13" R 98 315 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 30 "/Etherne1"
+Ne 32 "/Etherne1"
 Po -1082 1613
 $EndPAD
 $PAD
@@ -4615,14 +4630,14 @@ $PAD
 Sh "6" R 100 600 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 84 "/Non_vol79"
+Ne 84 "/Non_vol72"
 Po -1280 3850
 $EndPAD
 $PAD
 Sh "7" R 100 600 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 84 "/Non_vol79"
+Ne 84 "/Non_vol72"
 Po -1090 3850
 $EndPAD
 $PAD
@@ -5228,14 +5243,14 @@ $PAD
 Sh "10" R 137 570 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 103 "N-000420"
+Ne 105 "N-000420"
 Po 255 -1112
 $EndPAD
 $PAD
 Sh "11" R 137 570 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 104 "N-000426"
+Ne 106 "N-000426"
 Po 0 -1112
 $EndPAD
 $PAD
@@ -5285,7 +5300,7 @@ $PAD
 Sh "2" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 73 "/FPGA_Sp59"
+Ne 65 "/FPGA_Sp52"
 Po -3838 2176
 $EndPAD
 $PAD
@@ -5299,7 +5314,7 @@ $PAD
 Sh "4" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 74 "/FPGA_Sp60"
+Ne 66 "/FPGA_Sp53"
 Po -3326 2176
 $EndPAD
 $PAD
@@ -5341,14 +5356,14 @@ $PAD
 Sh "10" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "/FPGA_Sp39"
+Ne 54 "/FPGA_Sp33"
 Po -1791 2176
 $EndPAD
 $PAD
 Sh "11" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 11 "/DDR_Ban47"
+Ne 59 "/FPGA_Sp40"
 Po -1535 2176
 $EndPAD
 $PAD
@@ -5362,7 +5377,7 @@ $PAD
 Sh "13" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 12 "/DDR_Ban48"
+Ne 60 "/FPGA_Sp41"
 Po -1023 2176
 $EndPAD
 $PAD
@@ -5383,7 +5398,7 @@ $PAD
 Sh "16" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 67 "/FPGA_Sp52"
+Ne 13 "/DDR_Ban45"
 Po -255 2176
 $EndPAD
 $PAD
@@ -5411,28 +5426,28 @@ $PAD
 Sh "20" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 66 "/FPGA_Sp51"
+Ne 12 "/DDR_Ban44"
 Po 767 2176
 $EndPAD
 $PAD
 Sh "21" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 5 "/DDR_Ban31"
+Ne 6 "/DDR_Ban25"
 Po 1023 2176
 $EndPAD
 $PAD
 Sh "22" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 6 "/DDR_Ban34"
+Ne 50 "/FPGA_Sp28"
 Po 1279 2176
 $EndPAD
 $PAD
 Sh "23" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "/FPGA_Sp33"
+Ne 49 "/FPGA_Sp27"
 Po 1535 2176
 $EndPAD
 $PAD
@@ -5467,35 +5482,35 @@ $PAD
 Sh "28" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 49 "/FPGA_Sp24"
+Ne 45 "/FPGA_Sp19"
 Po 2814 2176
 $EndPAD
 $PAD
 Sh "29" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 46 "/FPGA_Sp21"
+Ne 24 "/DDR_Banks/M1_A0"
 Po 3070 2176
 $EndPAD
 $PAD
 Sh "30" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 47 "/FPGA_Sp22"
+Ne 25 "/DDR_Banks/M1_A1"
 Po 3326 2176
 $EndPAD
 $PAD
 Sh "31" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 41 "/FPGA_Sp16"
+Ne 26 "/DDR_Banks/M1_A2"
 Po 3582 2176
 $EndPAD
 $PAD
 Sh "32" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 27 "/DDR_Banks/M1_A3"
+Ne 46 "/FPGA_Sp20"
 Po 3838 2176
 $EndPAD
 $PAD
@@ -5516,28 +5531,28 @@ $PAD
 Sh "35" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 45 "/FPGA_Sp20"
+Ne 43 "/FPGA_Sp17"
 Po 3838 -2176
 $EndPAD
 $PAD
 Sh "36" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 28 "/DDR_Banks/M1_A5"
+Ne 27 "/DDR_Banks/M1_A5"
 Po 3582 -2176
 $EndPAD
 $PAD
 Sh "37" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 63 "/FPGA_Sp46"
+Ne 28 "/DDR_Banks/M1_A6"
 Po 3326 -2176
 $EndPAD
 $PAD
 Sh "38" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 40 "/FPGA_Sp15"
+Ne 29 "/DDR_Banks/M1_A7"
 Po 3070 -2176
 $EndPAD
 $PAD
@@ -5551,21 +5566,21 @@ $PAD
 Sh "40" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 37 "/FPGA_Sp10"
+Ne 30 "/DDR_Banks/M1_A9"
 Po 2558 -2176
 $EndPAD
 $PAD
 Sh "41" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 44 "/FPGA_Sp19"
+Ne 3 "/DDR_Ban16"
 Po 2303 -2176
 $EndPAD
 $PAD
 Sh "42" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 39 "/FPGA_Sp14"
+Ne 41 "/FPGA_Sp13"
 Po 2047 -2176
 $EndPAD
 $PAD
@@ -5579,28 +5594,28 @@ $PAD
 Sh "44" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 8 "/DDR_Ban38"
+Ne 53 "/FPGA_Sp32"
 Po 1535 -2176
 $EndPAD
 $PAD
 Sh "45" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 38 "/FPGA_Sp13"
+Ne 40 "/FPGA_Sp12"
 Po 1279 -2176
 $EndPAD
 $PAD
 Sh "46" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "/FPGA_Sp32"
+Ne 7 "/DDR_Ban26"
 Po 1023 -2176
 $EndPAD
 $PAD
 Sh "47" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 71 "/FPGA_Sp56"
+Ne 15 "/DDR_Ban49"
 Po 767 -2176
 $EndPAD
 $PAD
@@ -5628,7 +5643,7 @@ $PAD
 Sh "51" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 19 "/DDR_Ban70"
+Ne 76 "/FPGA_Sp63"
 Po -255 -2176
 $EndPAD
 $PAD
@@ -5649,7 +5664,7 @@ $PAD
 Sh "54" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 15 "/DDR_Ban63"
+Ne 69 "/FPGA_Sp56"
 Po -1023 -2176
 $EndPAD
 $PAD
@@ -5663,14 +5678,14 @@ $PAD
 Sh "56" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 76 "/FPGA_Sp64"
+Ne 70 "/FPGA_Sp57"
 Po -1535 -2176
 $EndPAD
 $PAD
 Sh "57" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 17 "/DDR_Ban67"
+Ne 73 "/FPGA_Sp60"
 Po -1791 -2176
 $EndPAD
 $PAD
@@ -5684,14 +5699,14 @@ $PAD
 Sh "59" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 18 "/DDR_Ban68"
+Ne 74 "/FPGA_Sp61"
 Po -2303 -2176
 $EndPAD
 $PAD
 Sh "60" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 80 "/FPGA_Sp73"
+Ne 78 "/FPGA_Sp66"
 Po -2558 -2176
 $EndPAD
 $PAD
@@ -5705,14 +5720,14 @@ $PAD
 Sh "62" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 81 "/FPGA_Sp74"
+Ne 79 "/FPGA_Sp67"
 Po -3070 -2176
 $EndPAD
 $PAD
 Sh "63" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 82 "/FPGA_Sp77"
+Ne 81 "/FPGA_Sp70"
 Po -3326 -2176
 $EndPAD
 $PAD
@@ -5726,7 +5741,7 @@ $PAD
 Sh "65" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 23 "/DDR_Ban78"
+Ne 19 "/DDR_Ban71"
 Po -3838 -2176
 $EndPAD
 $PAD
@@ -5762,7 +5777,7 @@ $PAD
 Sh "2" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 72 "/FPGA_Sp58"
+Ne 16 "/DDR_Ban51"
 Po -3838 2176
 $EndPAD
 $PAD
@@ -5776,14 +5791,14 @@ $PAD
 Sh "4" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 13 "/DDR_Ban57"
+Ne 64 "/FPGA_Sp50"
 Po -3326 2176
 $EndPAD
 $PAD
 Sh "5" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 69 "/FPGA_Sp54"
+Ne 62 "/FPGA_Sp47"
 Po -3070 2176
 $EndPAD
 $PAD
@@ -5797,14 +5812,14 @@ $PAD
 Sh "7" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 68 "/FPGA_Sp53"
+Ne 14 "/DDR_Ban46"
 Po -2558 2176
 $EndPAD
 $PAD
 Sh "8" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 7 "/DDR_Ban36"
+Ne 8 "/DDR_Ban30"
 Po -2303 2176
 $EndPAD
 $PAD
@@ -5818,14 +5833,14 @@ $PAD
 Sh "10" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "/FPGA_Sp35"
+Ne 51 "/FPGA_Sp29"
 Po -1791 2176
 $EndPAD
 $PAD
 Sh "11" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 60 "/FPGA_Sp41"
+Ne 10 "/DDR_Ban35"
 Po -1535 2176
 $EndPAD
 $PAD
@@ -5839,7 +5854,7 @@ $PAD
 Sh "13" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "/FPGA_Sp40"
+Ne 9 "/DDR_Ban34"
 Po -1023 2176
 $EndPAD
 $PAD
@@ -5860,7 +5875,7 @@ $PAD
 Sh "16" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 64 "/FPGA_Sp49"
+Ne 11 "/DDR_Ban42"
 Po -255 2176
 $EndPAD
 $PAD
@@ -5888,28 +5903,28 @@ $PAD
 Sh "20" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 65 "/FPGA_Sp50"
+Ne 61 "/FPGA_Sp43"
 Po 767 2176
 $EndPAD
 $PAD
 Sh "21" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 42 "/FPGA_Sp17"
+Ne 2 "/DDR_Ban15"
 Po 1023 2176
 $EndPAD
 $PAD
 Sh "22" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 9 "/DDR_Ban43"
+Ne 56 "/FPGA_Sp37"
 Po 1279 2176
 $EndPAD
 $PAD
 Sh "23" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 10 "/DDR_Ban44"
+Ne 57 "/FPGA_Sp38"
 Po 1535 2176
 $EndPAD
 $PAD
@@ -5944,35 +5959,35 @@ $PAD
 Sh "28" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 48 "/FPGA_Sp23"
+Ne 44 "/FPGA_Sp18"
 Po 2814 2176
 $EndPAD
 $PAD
 Sh "29" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "/FPGA_Sp26"
+Ne 20 "/DDR_Banks/M0_A0"
 Po 3070 2176
 $EndPAD
 $PAD
 Sh "30" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "/FPGA_Sp25"
+Ne 47 "/FPGA_Sp21"
 Po 3326 2176
 $EndPAD
 $PAD
 Sh "31" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "/FPGA_Sp29"
+Ne 48 "/FPGA_Sp24"
 Po 3582 2176
 $EndPAD
 $PAD
 Sh "32" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 62 "/FPGA_Sp45"
+Ne 58 "/FPGA_Sp39"
 Po 3838 2176
 $EndPAD
 $PAD
@@ -5993,56 +6008,56 @@ $PAD
 Sh "35" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 43 "/FPGA_Sp18"
+Ne 21 "/DDR_Banks/M0_A4"
 Po 3838 -2176
 $EndPAD
 $PAD
 Sh "36" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 61 "/FPGA_Sp42"
+Ne 55 "/FPGA_Sp36"
 Po 3582 -2176
 $EndPAD
 $PAD
 Sh "37" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "/FPGA_Sp37"
+Ne 52 "/FPGA_Sp31"
 Po 3326 -2176
 $EndPAD
 $PAD
 Sh "38" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "/FPGA_Sp30"
+Ne 22 "/DDR_Banks/M0_A7"
 Po 3070 -2176
 $EndPAD
 $PAD
 Sh "39" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 25 "/DDR_Banks/M0_A8"
+Ne 23 "/DDR_Banks/M0_A8"
 Po 2814 -2176
 $EndPAD
 $PAD
 Sh "40" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 26 "/DDR_Banks/M0_A9"
+Ne 42 "/FPGA_Sp14"
 Po 2558 -2176
 $EndPAD
 $PAD
 Sh "41" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 24 "/DDR_Ban8"
+Ne 82 "/FPGA_Sp8"
 Po 2303 -2176
 $EndPAD
 $PAD
 Sh "42" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 1 "/DDR_Ban11"
+Ne 39 "/FPGA_Sp10"
 Po 2047 -2176
 $EndPAD
 $PAD
@@ -6056,28 +6071,28 @@ $PAD
 Sh "44" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 3 "/DDR_Ban27"
+Ne 4 "/DDR_Ban22"
 Po 1535 -2176
 $EndPAD
 $PAD
 Sh "45" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 2 "/DDR_Ban12"
+Ne 1 "/DDR_Ban11"
 Po 1279 -2176
 $EndPAD
 $PAD
 Sh "46" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 4 "/DDR_Ban28"
+Ne 5 "/DDR_Ban23"
 Po 1023 -2176
 $EndPAD
 $PAD
 Sh "47" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 70 "/FPGA_Sp55"
+Ne 63 "/FPGA_Sp48"
 Po 767 -2176
 $EndPAD
 $PAD
@@ -6105,7 +6120,7 @@ $PAD
 Sh "51" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 78 "/FPGA_Sp69"
+Ne 75 "/FPGA_Sp62"
 Po -255 -2176
 $EndPAD
 $PAD
@@ -6126,7 +6141,7 @@ $PAD
 Sh "54" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 14 "/DDR_Ban62"
+Ne 68 "/FPGA_Sp55"
 Po -1023 -2176
 $EndPAD
 $PAD
@@ -6140,14 +6155,14 @@ $PAD
 Sh "56" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 75 "/FPGA_Sp61"
+Ne 67 "/FPGA_Sp54"
 Po -1535 -2176
 $EndPAD
 $PAD
 Sh "57" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 77 "/FPGA_Sp66"
+Ne 72 "/FPGA_Sp59"
 Po -1791 -2176
 $EndPAD
 $PAD
@@ -6161,14 +6176,14 @@ $PAD
 Sh "59" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 16 "/DDR_Ban65"
+Ne 71 "/FPGA_Sp58"
 Po -2303 -2176
 $EndPAD
 $PAD
 Sh "60" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 20 "/DDR_Ban72"
+Ne 77 "/FPGA_Sp65"
 Po -2558 -2176
 $EndPAD
 $PAD
@@ -6182,14 +6197,14 @@ $PAD
 Sh "62" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 79 "/FPGA_Sp71"
+Ne 17 "/DDR_Ban64"
 Po -3070 -2176
 $EndPAD
 $PAD
 Sh "63" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 22 "/DDR_Ban76"
+Ne 80 "/FPGA_Sp69"
 Po -3326 -2176
 $EndPAD
 $PAD
@@ -6203,7 +6218,7 @@ $PAD
 Sh "65" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 21 "/DDR_Ban75"
+Ne 18 "/DDR_Ban68"
 Po -3838 -2176
 $EndPAD
 $PAD
@@ -6214,6 +6229,874 @@ Ne 86 "GND"
 Po -4094 -2176
 $EndPAD
 $EndMODULE  TSOP-66
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE78 ~~
+Li 0402
+Sc 4C60BE78
+AR /4C5F1EDC/4C5F2D27
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"R10"
+T1 0 150 200 200 0 40 N I 25 N"1M"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 107 "N-000428"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE7A ~~
+Li 0402
+Sc 4C60BE7A
+AR /4C4320F3/4C5D7DC4
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"R9"
+T1 0 150 200 200 0 40 N I 25 N"1M"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 98 "N-000400"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE7C ~~
+Li 0402
+Sc 4C60BE7C
+AR /4C4320F3/4C5D71DB
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"R8"
+T1 0 150 200 200 0 40 N I 25 N"220"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 100 "N-000404"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 37 "/Etherne6"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE7E ~~
+Li 0402
+Sc 4C60BE7E
+AR /4C4320F3/4C5D719D
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"R7"
+T1 0 150 200 200 0 40 N I 25 N"220"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 95 "N-000396"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 36 "/Etherne5"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE80 ~~
+Li 0402
+Sc 4C60BE80
+AR /4C4320F3/4C5D7AF9
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"R6"
+T1 0 150 200 200 0 40 N I 25 N"49.9"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 101 "N-000405"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE82 ~~
+Li 0402
+Sc 4C60BE82
+AR /4C4320F3/4C5D7AF7
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"R5"
+T1 0 150 200 200 0 40 N I 25 N"49.9"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 97 "N-000399"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE84 ~~
+Li 0402
+Sc 4C60BE84
+AR /4C4320F3/4C5D7AFC
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"R4"
+T1 0 150 200 200 0 40 N I 25 N"49.9"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 102 "N-000406"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE86 ~~
+Li 0402
+Sc 4C60BE86
+AR /4C4320F3/4C5D7AFE
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"R3"
+T1 0 150 200 200 0 40 N I 25 N"49.9"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 96 "N-000398"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE88 ~~
+Li 0402
+Sc 4C60BE88
+AR /4C4320F3/4C5D7ECF
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"R2"
+T1 0 150 200 200 0 40 N I 25 N"6.65K"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 99 "N-000402"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE8A ~~
+Li 0402
+Sc 4C60BE8A
+AR /4C4320F3/4C5D7F39
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"R1"
+T1 0 150 200 200 0 40 N I 25 N"4.7K"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 31 "/ETH_MDIO"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE8C ~~
+Li 0402
+Sc 4C60BE8C
+AR /4C5F1EDC/4C5F2D1E
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C16"
+T1 0 150 200 200 0 40 N I 25 N"4.7nF"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 107 "N-000428"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE8E ~~
+Li 0402
+Sc 4C60BE8E
+AR /4C4320F3/4C5D7DCB
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C12"
+T1 0 150 200 200 0 40 N I 25 N"47nF"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 98 "N-000400"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE90 ~~
+Li 0402
+Sc 4C60BE90
+AR /4C4320F3/4C5D7E43
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C11"
+T1 0 150 200 200 0 40 N I 25 N"100nF"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE92 ~~
+Li 0402
+Sc 4C60BE92
+AR /4C4320F3/4C5D7E41
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C10"
+T1 0 150 200 200 0 40 N I 25 N"100nF"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE94 ~~
+Li 0402
+Sc 4C60BE94
+AR /4C4320F3/4C5D8114
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C9"
+T1 0 150 200 200 0 40 N I 25 N"C"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 35 "/Etherne4"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 103 "N-000416"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE96 ~~
+Li 0402
+Sc 4C60BE96
+AR /4C4320F3/4C5D7FA7
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C8"
+T1 0 150 200 200 0 40 N I 25 N"100nF"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 34 "/Etherne3"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE98 ~~
+Li 0402
+Sc 4C60BE98
+AR /4C4320F3/4C5D8104
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C6"
+T1 0 150 200 200 0 40 N I 25 N"C"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 33 "/Etherne2"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 103 "N-000416"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE9A ~~
+Li 0402
+Sc 4C60BE9A
+AR /4C4320F3/4C5D7FA3
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C5"
+T1 0 150 200 200 0 40 N I 25 N"100nF"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE9C ~~
+Li 0402
+Sc 4C60BE9C
+AR /4C4320F3/4C5D80F0
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C4"
+T1 0 150 200 200 0 40 N I 25 N"C"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 104 "N-000417"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 103 "N-000416"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BE9E ~~
+Li 0402
+Sc 4C60BE9E
+AR /4C4320F3/4C5D7FA1
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C3"
+T1 0 150 200 200 0 40 N I 25 N"100nF"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 0 0 0 15 4C5FF890 4C60BEA0 ~~
+Li 0402
+Sc 4C60BEA0
+AR /4C4320F3/4C5D80ED
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C2"
+T1 0 150 200 200 0 40 N I 25 N"C"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 32 "/Etherne1"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0603
+Po 0 0 0 15 4C5FF890 4C60BEA1 ~~
+Li 0603
+Sc 4C60BEA1
+AR /4C5F1EDC/4C5F2CA3
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"V2"
+T1 0 150 200 200 0 40 N I 25 N"V0402MHS03"
+DS -443 227 -443 -227 50 21
+DS -443 -227 443 -227 50 21
+DS 443 -227 443 227 50 21
+DS 443 227 -443 227 50 21
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 105 "N-000420"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
+$MODULE 0603
+Po 0 0 0 15 4C5FF890 4C60BEA3 ~~
+Li 0603
+Sc 4C60BEA3
+AR /4C5F1EDC/4C5F2CA7
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"V1"
+T1 0 150 200 200 0 40 N I 25 N"V0402MHS03"
+DS -443 227 -443 -227 50 21
+DS -443 -227 443 -227 50 21
+DS 443 -227 443 227 50 21
+DS 443 227 -443 227 50 21
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 106 "N-000426"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
+$MODULE 0603
+Po 0 0 0 15 4C5FF890 4C60BEA5 ~~
+Li 0603
+Sc 4C60BEA5
+AR /4C4320F3/4C5D810A
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"L3"
+T1 0 150 200 200 0 40 N I 25 N"INDUCTOR"
+DS -443 227 -443 -227 50 21
+DS -443 -227 443 -227 50 21
+DS 443 -227 443 227 50 21
+DS 443 227 -443 227 50 21
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 33 "/Etherne2"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 35 "/Etherne4"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
+$MODULE 0603
+Po 0 0 0 15 4C5FF890 4C60BEA7 ~~
+Li 0603
+Sc 4C60BEA7
+AR /4C4320F3/4C5D7FB7
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"L2"
+T1 0 150 200 200 0 40 N I 25 N"FB"
+DS -443 227 -443 -227 50 21
+DS -443 -227 443 -227 50 21
+DS 443 -227 443 227 50 21
+DS 443 227 -443 227 50 21
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 34 "/Etherne3"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
+$MODULE 0603
+Po 0 0 0 15 4C5FF890 4C60BEA9 ~~
+Li 0603
+Sc 4C60BEA9
+AR /4C4320F3/4C5D80F3
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"L1"
+T1 0 150 200 200 0 40 N I 25 N"INDUCTOR"
+DS -443 227 -443 -227 50 21
+DS -443 -227 443 -227 50 21
+DS 443 -227 443 227 50 21
+DS 443 227 -443 227 50 21
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 104 "N-000417"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 33 "/Etherne2"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
+$MODULE 0603
+Po 0 0 0 15 4C5FF890 4C60BEAB ~~
+Li 0603
+Sc 4C60BEAB
+AR /4C5F1EDC/4C5F2039
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C15"
+T1 0 150 200 200 0 40 N I 25 N"470nF"
+DS -443 227 -443 -227 50 21
+DS -443 -227 443 -227 50 21
+DS 443 -227 443 227 50 21
+DS 443 227 -443 227 50 21
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
+$MODULE 0603
+Po 0 0 0 15 4C5FF890 4C60BEAD ~~
+Li 0603
+Sc 4C60BEAD
+AR /4C5F1EDC/4C5F2037
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C14"
+T1 0 150 200 200 0 40 N I 25 N"1uF"
+DS -443 227 -443 -227 50 21
+DS -443 -227 443 -227 50 21
+DS 443 -227 443 227 50 21
+DS 443 227 -443 227 50 21
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
+$MODULE 0603
+Po 0 0 0 15 4C5FF890 4C60BEAF ~~
+Li 0603
+Sc 4C60BEAF
+AR /4C5F1EDC/4C5F2033
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C13"
+T1 0 150 200 200 0 40 N I 25 N"1uF"
+DS -443 227 -443 -227 50 21
+DS -443 -227 443 -227 50 21
+DS 443 -227 443 227 50 21
+DS 443 227 -443 227 50 21
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
+$MODULE 0603
+Po 0 0 0 15 4C5FF890 4C60BEB1 ~~
+Li 0603
+Sc 4C60BEB1
+AR /4C4320F3/4C5D7FA5
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C7"
+T1 0 150 200 200 0 40 N I 25 N"1uF"
+DS -443 227 -443 -227 50 21
+DS -443 -227 443 -227 50 21
+DS 443 -227 443 227 50 21
+DS 443 227 -443 227 50 21
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 34 "/Etherne3"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
+$MODULE 0603
+Po 5906 3150 0 15 4C5FF890 4C60BEB3 ~~
+Li 0603
+Sc 4C60BEB3
+AR /4C4320F3/4C5D7F9F
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C1"
+T1 0 150 200 200 0 40 N I 25 N"1uF"
+DS -443 227 -443 -227 50 21
+DS -443 -227 443 -227 50 21
+DS 443 -227 443 227 50 21
+DS 443 227 -443 227 50 21
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 85 "3.3V"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 86 "GND"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
 $TRACK
 $EndTRACK
 $ZONE
diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp
index 2ba6b17..c41bb32 100644
--- a/kicad/xue-rnc/xue-rnc.cmp
+++ b/kicad/xue-rnc/xue-rnc.cmp
@@ -1,122 +1,122 @@
-Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Mon 09 Aug 2010 09:21:21 PM COT
+Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Mon 09 Aug 2010 09:53:42 PM COT
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7F9F;
 Reference = C1;
 ValeurCmp = 1uF;
-IdModule  = ;
+IdModule  = 0603;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D80ED;
 Reference = C2;
 ValeurCmp = C;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7FA1;
 Reference = C3;
 ValeurCmp = 100nF;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D80F0;
 Reference = C4;
 ValeurCmp = C;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7FA3;
 Reference = C5;
 ValeurCmp = 100nF;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D8104;
 Reference = C6;
 ValeurCmp = C;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7FA5;
 Reference = C7;
 ValeurCmp = 1uF;
-IdModule  = ;
+IdModule  = 0603;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7FA7;
 Reference = C8;
 ValeurCmp = 100nF;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D8114;
 Reference = C9;
 ValeurCmp = C;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7E41;
 Reference = C10;
 ValeurCmp = 100nF;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7E43;
 Reference = C11;
 ValeurCmp = 100nF;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7DCB;
 Reference = C12;
 ValeurCmp = 47nF;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2033;
 Reference = C13;
 ValeurCmp = 1uF;
-IdModule  = ;
+IdModule  = 0603;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2037;
 Reference = C14;
 ValeurCmp = 1uF;
-IdModule  = ;
+IdModule  = 0603;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2039;
 Reference = C15;
 ValeurCmp = 470nF;
-IdModule  = ;
+IdModule  = 0603;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2D1E;
 Reference = C16;
 ValeurCmp = 4.7nF;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2B55;
 Reference = F1;
 ValeurCmp = MICROSMD075F;
-IdModule  = ;
+IdModule  = 1210;
 EndCmp
 
 BeginCmp
@@ -137,98 +137,98 @@ BeginCmp
 TimeStamp = /4C5F1EDC/4C5F23DD;
 Reference = J5;
 ValeurCmp = USB-48204-0001;
-IdModule  = ;
+IdModule  = USB-48204;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D80F3;
 Reference = L1;
 ValeurCmp = INDUCTOR;
-IdModule  = ;
+IdModule  = 0603;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7FB7;
 Reference = L2;
 ValeurCmp = FB;
-IdModule  = ;
+IdModule  = 0603;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D810A;
 Reference = L3;
 ValeurCmp = INDUCTOR;
-IdModule  = ;
+IdModule  = 0603;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7F39;
 Reference = R1;
 ValeurCmp = 4.7K;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7ECF;
 Reference = R2;
 ValeurCmp = 6.65K;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7AFE;
 Reference = R3;
 ValeurCmp = 49.9;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7AFC;
 Reference = R4;
 ValeurCmp = 49.9;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7AF7;
 Reference = R5;
 ValeurCmp = 49.9;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7AF9;
 Reference = R6;
 ValeurCmp = 49.9;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D719D;
 Reference = R7;
 ValeurCmp = 220;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D71DB;
 Reference = R8;
 ValeurCmp = 220;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7DC4;
 Reference = R9;
 ValeurCmp = 1M;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2D27;
 Reference = R10;
 ValeurCmp = 1M;
-IdModule  = ;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
@@ -277,14 +277,14 @@ BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2CA7;
 Reference = V1;
 ValeurCmp = V0402MHS03;
-IdModule  = ;
+IdModule  = 0603;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2CA3;
 Reference = V2;
 ValeurCmp = V0402MHS03;
-IdModule  = ;
+IdModule  = 0603;
 EndCmp
 
 EndListe
diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net
index a7a6324..ecd03b5 100644
--- a/kicad/xue-rnc/xue-rnc.net
+++ b/kicad/xue-rnc/xue-rnc.net
@@ -1,70 +1,70 @@
-# EESchema Netlist Version 1.1 created  Mon 09 Aug 2010 09:21:21 PM COT
+# EESchema Netlist Version 1.1 created  Mon 09 Aug 2010 09:53:42 PM COT
 (
- ( /4C4320F3/4C5D7F9F $noname$ C1 1uF
+ ( /4C4320F3/4C5D7F9F 0603 C1 1uF
   ( 1 3.3V )
   ( 2 GND )
  )
- ( /4C4320F3/4C5D80ED $noname$ C2 C
+ ( /4C4320F3/4C5D80ED 0402 C2 C
   ( 1 /Etherne1 )
   ( 2 GND )
  )
- ( /4C4320F3/4C5D7FA1 $noname$ C3 100nF
+ ( /4C4320F3/4C5D7FA1 0402 C3 100nF
   ( 1 3.3V )
   ( 2 GND )
  )
- ( /4C4320F3/4C5D80F0 $noname$ C4 C
+ ( /4C4320F3/4C5D80F0 0402 C4 C
   ( 1 N-000417 )
   ( 2 N-000416 )
  )
- ( /4C4320F3/4C5D7FA3 $noname$ C5 100nF
+ ( /4C4320F3/4C5D7FA3 0402 C5 100nF
   ( 1 3.3V )
   ( 2 GND )
  )
- ( /4C4320F3/4C5D8104 $noname$ C6 C
+ ( /4C4320F3/4C5D8104 0402 C6 C
   ( 1 /Etherne2 )
   ( 2 N-000416 )
  )
- ( /4C4320F3/4C5D7FA5 $noname$ C7 1uF
+ ( /4C4320F3/4C5D7FA5 0603 C7 1uF
   ( 1 /Etherne3 )
   ( 2 GND )
  )
- ( /4C4320F3/4C5D7FA7 $noname$ C8 100nF
+ ( /4C4320F3/4C5D7FA7 0402 C8 100nF
   ( 1 /Etherne3 )
   ( 2 GND )
  )
- ( /4C4320F3/4C5D8114 $noname$ C9 C
+ ( /4C4320F3/4C5D8114 0402 C9 C
   ( 1 /Etherne4 )
   ( 2 N-000416 )
  )
- ( /4C4320F3/4C5D7E41 $noname$ C10 100nF
+ ( /4C4320F3/4C5D7E41 0402 C10 100nF
   ( 1 3.3V )
   ( 2 GND )
  )
- ( /4C4320F3/4C5D7E43 $noname$ C11 100nF
+ ( /4C4320F3/4C5D7E43 0402 C11 100nF
   ( 1 3.3V )
   ( 2 GND )
  )
- ( /4C4320F3/4C5D7DCB $noname$ C12 47nF
+ ( /4C4320F3/4C5D7DCB 0402 C12 47nF
   ( 1 N-000400 )
   ( 2 GND )
  )
- ( /4C5F1EDC/4C5F2033 $noname$ C13 1uF
+ ( /4C5F1EDC/4C5F2033 0603 C13 1uF
   ( 1 3.3V )
   ( 2 GND )
  )
- ( /4C5F1EDC/4C5F2037 $noname$ C14 1uF
+ ( /4C5F1EDC/4C5F2037 0603 C14 1uF
   ( 1 3.3V )
   ( 2 GND )
  )
- ( /4C5F1EDC/4C5F2039 $noname$ C15 470nF
+ ( /4C5F1EDC/4C5F2039 0603 C15 470nF
   ( 1 3.3V )
   ( 2 GND )
  )
- ( /4C5F1EDC/4C5F2D1E $noname$ C16 4.7nF
+ ( /4C5F1EDC/4C5F2D1E 0402 C16 4.7nF
   ( 1 N-000428 )
   ( 2 GND )
  )
- ( /4C5F1EDC/4C5F2B55 $noname$ F1 MICROSMD075F
+ ( /4C5F1EDC/4C5F2B55 1210 F1 MICROSMD075F
   ( 1 N-000427 )
   ( 2 ? )
  )
@@ -97,7 +97,7 @@
   ( 13 N-000400 )
   ( 14 N-000400 )
  )
- ( /4C5F1EDC/4C5F23DD $noname$ J5 USB-48204-0001
+ ( /4C5F1EDC/4C5F23DD USB-48204 J5 USB-48204-0001
   ( 1 N-000427 )
   ( 2 N-000420 )
   ( 3 N-000426 )
@@ -107,55 +107,55 @@
   ( S3 N-000428 )
   ( S4 N-000428 )
  )
- ( /4C4320F3/4C5D80F3 $noname$ L1 INDUCTOR
+ ( /4C4320F3/4C5D80F3 0603 L1 INDUCTOR
   ( 1 N-000417 )
   ( 2 /Etherne2 )
  )
- ( /4C4320F3/4C5D7FB7 $noname$ L2 FB
+ ( /4C4320F3/4C5D7FB7 0603 L2 FB
   ( 1 3.3V )
   ( 2 /Etherne3 )
  )
- ( /4C4320F3/4C5D810A $noname$ L3 INDUCTOR
+ ( /4C4320F3/4C5D810A 0603 L3 INDUCTOR
   ( 1 /Etherne2 )
   ( 2 /Etherne4 )
  )
- ( /4C4320F3/4C5D7F39 $noname$ R1 4.7K
+ ( /4C4320F3/4C5D7F39 0402 R1 4.7K
   ( 1 /ETH_MDIO )
   ( 2 3.3V )
  )
- ( /4C4320F3/4C5D7ECF $noname$ R2 6.65K
+ ( /4C4320F3/4C5D7ECF 0402 R2 6.65K
   ( 1 N-000402 )
   ( 2 GND )
  )
- ( /4C4320F3/4C5D7AFE $noname$ R3 49.9
+ ( /4C4320F3/4C5D7AFE 0402 R3 49.9
   ( 1 3.3V )
   ( 2 N-000398 )
  )
- ( /4C4320F3/4C5D7AFC $noname$ R4 49.9
+ ( /4C4320F3/4C5D7AFC 0402 R4 49.9
   ( 1 3.3V )
   ( 2 N-000406 )
  )
- ( /4C4320F3/4C5D7AF7 $noname$ R5 49.9
+ ( /4C4320F3/4C5D7AF7 0402 R5 49.9
   ( 1 3.3V )
   ( 2 N-000399 )
  )
- ( /4C4320F3/4C5D7AF9 $noname$ R6 49.9
+ ( /4C4320F3/4C5D7AF9 0402 R6 49.9
   ( 1 3.3V )
   ( 2 N-000405 )
  )
- ( /4C4320F3/4C5D719D $noname$ R7 220
+ ( /4C4320F3/4C5D719D 0402 R7 220
   ( 1 N-000396 )
   ( 2 /Etherne5 )
  )
- ( /4C4320F3/4C5D71DB $noname$ R8 220
+ ( /4C4320F3/4C5D71DB 0402 R8 220
   ( 1 N-000404 )
   ( 2 /Etherne6 )
  )
- ( /4C4320F3/4C5D7DC4 $noname$ R9 1M
+ ( /4C4320F3/4C5D7DC4 0402 R9 1M
   ( 1 N-000400 )
   ( 2 GND )
  )
- ( /4C5F1EDC/4C5F2D27 $noname$ R10 1M
+ ( /4C5F1EDC/4C5F2D27 0402 R10 1M
   ( 1 N-000428 )
   ( 2 GND )
  )
@@ -247,7 +247,7 @@
   ( B20 ? )
   ( B21 ? )
   ( B22 ? )
-  ( C1 /DDR_Ban8 )
+  ( C1 /FPGA_Sp8 )
   ( C2 N-000158 )
   ( C3 ? )
   ( C4 ? )
@@ -267,9 +267,9 @@
   ( C18 ? )
   ( C20 /FPGA_Sp9 )
   ( C21 N-000154 )
-  ( C22 /FPGA_Sp10 )
-  ( D1 /DDR_Ban11 )
-  ( D2 /DDR_Ban12 )
+  ( C22 /DDR_Banks/M1_A9 )
+  ( D1 /FPGA_Sp10 )
+  ( D2 /DDR_Ban11 )
   ( D3 ? )
   ( D4 GND )
   ( D5 ? )
@@ -288,9 +288,9 @@
   ( D18 GND )
   ( D19 ? )
   ( D20 ? )
-  ( D21 /FPGA_Sp13 )
-  ( D22 /FPGA_Sp14 )
-  ( E1 /DDR_Banks/M0_A9 )
+  ( D21 /FPGA_Sp12 )
+  ( D22 /FPGA_Sp13 )
+  ( E1 /FPGA_Sp14 )
   ( E2 GND )
   ( E3 /DDR_Banks/M0_A8 )
   ( E4 ? )
@@ -309,12 +309,12 @@
   ( E17 N-000153 )
   ( E18 ? )
   ( E19 N-000154 )
-  ( E20 /FPGA_Sp15 )
+  ( E20 /DDR_Banks/M1_A7 )
   ( E21 GND )
-  ( E22 /FPGA_Sp16 )
+  ( E22 /DDR_Banks/M1_A2 )
   ( F1 ? )
-  ( F2 /FPGA_Sp17 )
-  ( F3 /FPGA_Sp18 )
+  ( F2 /DDR_Ban15 )
+  ( F3 /DDR_Banks/M0_A4 )
   ( F4 N-000158 )
   ( F5 ? )
   ( F6 N-000158 )
@@ -330,14 +330,14 @@
   ( F16 ? )
   ( F17 ? )
   ( F18 ? )
-  ( F19 /FPGA_Sp19 )
-  ( F20 /FPGA_Sp20 )
-  ( F21 /FPGA_Sp21 )
-  ( F22 /FPGA_Sp22 )
+  ( F19 /DDR_Ban16 )
+  ( F20 /FPGA_Sp17 )
+  ( F21 /DDR_Banks/M1_A0 )
+  ( F22 /DDR_Banks/M1_A1 )
   ( G1 ? )
   ( G2 N-000158 )
   ( G3 ? )
-  ( G4 /FPGA_Sp23 )
+  ( G4 /FPGA_Sp18 )
   ( G5 GND )
   ( G6 ? )
   ( G7 ? )
@@ -352,16 +352,16 @@
   ( G16 ? )
   ( G17 ? )
   ( G18 GND )
-  ( G19 /FPGA_Sp24 )
-  ( G20 /DDR_Banks/M1_A3 )
+  ( G19 /FPGA_Sp19 )
+  ( G20 /FPGA_Sp20 )
   ( G21 N-000154 )
   ( G22 ? )
-  ( H1 /FPGA_Sp25 )
-  ( H2 /FPGA_Sp26 )
-  ( H3 /DDR_Ban27 )
-  ( H4 /DDR_Ban28 )
-  ( H5 /FPGA_Sp29 )
-  ( H6 /FPGA_Sp30 )
+  ( H1 /FPGA_Sp21 )
+  ( H2 /DDR_Banks/M0_A0 )
+  ( H3 /DDR_Ban22 )
+  ( H4 /DDR_Ban23 )
+  ( H5 /FPGA_Sp24 )
+  ( H6 /DDR_Banks/M0_A7 )
   ( H7 GND )
   ( H8 ? )
   ( H9 N-000160 )
@@ -374,14 +374,14 @@
   ( H16 ? )
   ( H17 ? )
   ( H18 ? )
-  ( H19 /DDR_Ban31 )
-  ( H20 /FPGA_Sp32 )
-  ( H21 /FPGA_Sp33 )
-  ( H22 /DDR_Ban34 )
-  ( J1 /FPGA_Sp35 )
+  ( H19 /DDR_Ban25 )
+  ( H20 /DDR_Ban26 )
+  ( H21 /FPGA_Sp27 )
+  ( H22 /FPGA_Sp28 )
+  ( J1 /FPGA_Sp29 )
   ( J2 GND )
-  ( J3 /DDR_Ban36 )
-  ( J4 /FPGA_Sp37 )
+  ( J3 /DDR_Ban30 )
+  ( J4 /FPGA_Sp31 )
   ( J5 N-000158 )
   ( J6 ? )
   ( J7 ? )
@@ -396,16 +396,16 @@
   ( J16 ? )
   ( J17 ? )
   ( J18 N-000154 )
-  ( J19 /DDR_Ban38 )
+  ( J19 /FPGA_Sp32 )
   ( J20 ? )
   ( J21 GND )
-  ( J22 /FPGA_Sp39 )
-  ( K1 /FPGA_Sp40 )
-  ( K2 /FPGA_Sp41 )
-  ( K3 /FPGA_Sp42 )
-  ( K4 /DDR_Ban43 )
-  ( K5 /DDR_Ban44 )
-  ( K6 /FPGA_Sp45 )
+  ( J22 /FPGA_Sp33 )
+  ( K1 /DDR_Ban34 )
+  ( K2 /DDR_Ban35 )
+  ( K3 /FPGA_Sp36 )
+  ( K4 /FPGA_Sp37 )
+  ( K5 /FPGA_Sp38 )
+  ( K6 /FPGA_Sp39 )
   ( K7 ? )
   ( K8 ? )
   ( K9 N-000159 )
@@ -418,14 +418,14 @@
   ( K16 ? )
   ( K17 ? )
   ( K18 ? )
-  ( K19 /FPGA_Sp46 )
+  ( K19 /DDR_Banks/M1_A6 )
   ( K20 /DDR_Banks/M1_A5 )
-  ( K21 /DDR_Ban47 )
-  ( K22 /DDR_Ban48 )
+  ( K21 /FPGA_Sp40 )
+  ( K22 /FPGA_Sp41 )
   ( L1 ? )
   ( L2 N-000158 )
-  ( L3 /FPGA_Sp49 )
-  ( L4 /FPGA_Sp50 )
+  ( L3 /DDR_Ban42 )
+  ( L4 /FPGA_Sp43 )
   ( L5 GND )
   ( L6 ? )
   ( L7 N-000158 )
@@ -440,13 +440,13 @@
   ( L16 N-000154 )
   ( L17 ? )
   ( L18 GND )
-  ( L19 /FPGA_Sp51 )
-  ( L20 /FPGA_Sp52 )
+  ( L19 /DDR_Ban44 )
+  ( L20 /DDR_Ban45 )
   ( L21 N-000154 )
   ( L22 ? )
-  ( M1 /FPGA_Sp53 )
-  ( M2 /FPGA_Sp54 )
-  ( M3 /FPGA_Sp55 )
+  ( M1 /DDR_Ban46 )
+  ( M2 /FPGA_Sp47 )
+  ( M3 /FPGA_Sp48 )
   ( M4 ? )
   ( M5 ? )
   ( M6 ? )
@@ -463,12 +463,12 @@
   ( M17 ? )
   ( M18 ? )
   ( M19 ? )
-  ( M20 /FPGA_Sp56 )
+  ( M20 /DDR_Ban49 )
   ( M21 ? )
   ( M22 ? )
-  ( N1 /DDR_Ban57 )
+  ( N1 /FPGA_Sp50 )
   ( N2 GND )
-  ( N3 /FPGA_Sp58 )
+  ( N3 /DDR_Ban51 )
   ( N4 ? )
   ( N5 N-000158 )
   ( N6 ? )
@@ -485,11 +485,11 @@
   ( N17 GND )
   ( N18 N-000154 )
   ( N19 ? )
-  ( N20 /FPGA_Sp59 )
+  ( N20 /FPGA_Sp52 )
   ( N21 GND )
-  ( N22 /FPGA_Sp60 )
-  ( P1 /FPGA_Sp61 )
-  ( P2 /DDR_Ban62 )
+  ( N22 /FPGA_Sp53 )
+  ( P1 /FPGA_Sp54 )
+  ( P2 /FPGA_Sp55 )
   ( P3 ? )
   ( P4 ? )
   ( P5 ? )
@@ -508,11 +508,11 @@
   ( P18 ? )
   ( P19 ? )
   ( P20 ? )
-  ( P21 /DDR_Ban63 )
-  ( P22 /FPGA_Sp64 )
-  ( R1 /DDR_Ban65 )
+  ( P21 /FPGA_Sp56 )
+  ( P22 /FPGA_Sp57 )
+  ( R1 /FPGA_Sp58 )
   ( R2 N-000158 )
-  ( R3 /FPGA_Sp66 )
+  ( R3 /FPGA_Sp59 )
   ( R4 ? )
   ( R5 GND )
   ( R6 N-000160 )
@@ -529,11 +529,11 @@
   ( R17 ? )
   ( R18 GND )
   ( R19 ? )
-  ( R20 /DDR_Ban67 )
+  ( R20 /FPGA_Sp60 )
   ( R21 N-000154 )
-  ( R22 /DDR_Ban68 )
+  ( R22 /FPGA_Sp61 )
   ( T1 ? )
-  ( T2 /FPGA_Sp69 )
+  ( T2 /FPGA_Sp62 )
   ( T3 ? )
   ( T4 ? )
   ( T5 ? )
@@ -552,11 +552,11 @@
   ( T18 ? )
   ( T19 ? )
   ( T20 ? )
-  ( T21 /DDR_Ban70 )
+  ( T21 /FPGA_Sp63 )
   ( T22 ? )
-  ( U1 /FPGA_Sp71 )
+  ( U1 /DDR_Ban64 )
   ( U2 GND )
-  ( U3 /DDR_Ban72 )
+  ( U3 /FPGA_Sp65 )
   ( U4 ? )
   ( U5 N-000158 )
   ( U6 ? )
@@ -573,11 +573,11 @@
   ( U17 ? )
   ( U18 N-000154 )
   ( U19 ? )
-  ( U20 /FPGA_Sp73 )
+  ( U20 /FPGA_Sp66 )
   ( U21 GND )
-  ( U22 /FPGA_Sp74 )
-  ( V1 /DDR_Ban75 )
-  ( V2 /DDR_Ban76 )
+  ( U22 /FPGA_Sp67 )
+  ( V1 /DDR_Ban68 )
+  ( V2 /FPGA_Sp69 )
   ( V3 ? )
   ( V4 GND )
   ( V5 ? )
@@ -596,8 +596,8 @@
   ( V18 ? )
   ( V19 ? )
   ( V20 ? )
-  ( V21 /FPGA_Sp77 )
-  ( V22 /DDR_Ban78 )
+  ( V21 /FPGA_Sp70 )
+  ( V22 /DDR_Ban71 )
   ( W1 ? )
   ( W2 N-000158 )
   ( W3 ? )
@@ -642,138 +642,138 @@
  )
  ( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG
   ( 1 N-000056 )
-  ( 2 /FPGA_Sp58 )
+  ( 2 /DDR_Ban51 )
   ( 3 N-000056 )
-  ( 4 /DDR_Ban57 )
-  ( 5 /FPGA_Sp54 )
+  ( 4 /FPGA_Sp50 )
+  ( 5 /FPGA_Sp47 )
   ( 6 GND )
-  ( 7 /FPGA_Sp53 )
-  ( 8 /DDR_Ban36 )
+  ( 7 /DDR_Ban46 )
+  ( 8 /DDR_Ban30 )
   ( 9 N-000056 )
-  ( 10 /FPGA_Sp35 )
-  ( 11 /FPGA_Sp41 )
+  ( 10 /FPGA_Sp29 )
+  ( 11 /DDR_Ban35 )
   ( 12 GND )
-  ( 13 /FPGA_Sp40 )
+  ( 13 /DDR_Ban34 )
   ( 14 ? )
   ( 15 N-000056 )
-  ( 16 /FPGA_Sp49 )
+  ( 16 /DDR_Ban42 )
   ( 17 ? )
   ( 18 N-000056 )
   ( 19 ? )
-  ( 20 /FPGA_Sp50 )
-  ( 21 /FPGA_Sp17 )
-  ( 22 /DDR_Ban43 )
-  ( 23 /DDR_Ban44 )
+  ( 20 /FPGA_Sp43 )
+  ( 21 /DDR_Ban15 )
+  ( 22 /FPGA_Sp37 )
+  ( 23 /FPGA_Sp38 )
   ( 24 ? )
   ( 25 ? )
   ( 26 ? )
   ( 27 ? )
-  ( 28 /FPGA_Sp23 )
-  ( 29 /FPGA_Sp26 )
-  ( 30 /FPGA_Sp25 )
-  ( 31 /FPGA_Sp29 )
-  ( 32 /FPGA_Sp45 )
+  ( 28 /FPGA_Sp18 )
+  ( 29 /DDR_Banks/M0_A0 )
+  ( 30 /FPGA_Sp21 )
+  ( 31 /FPGA_Sp24 )
+  ( 32 /FPGA_Sp39 )
   ( 33 N-000056 )
   ( 34 GND )
-  ( 35 /FPGA_Sp18 )
-  ( 36 /FPGA_Sp42 )
-  ( 37 /FPGA_Sp37 )
-  ( 38 /FPGA_Sp30 )
+  ( 35 /DDR_Banks/M0_A4 )
+  ( 36 /FPGA_Sp36 )
+  ( 37 /FPGA_Sp31 )
+  ( 38 /DDR_Banks/M0_A7 )
   ( 39 /DDR_Banks/M0_A8 )
-  ( 40 /DDR_Banks/M0_A9 )
-  ( 41 /DDR_Ban8 )
-  ( 42 /DDR_Ban11 )
+  ( 40 /FPGA_Sp14 )
+  ( 41 /FPGA_Sp8 )
+  ( 42 /FPGA_Sp10 )
   ( 43 ? )
-  ( 44 /DDR_Ban27 )
-  ( 45 /DDR_Ban12 )
-  ( 46 /DDR_Ban28 )
-  ( 47 /FPGA_Sp55 )
+  ( 44 /DDR_Ban22 )
+  ( 45 /DDR_Ban11 )
+  ( 46 /DDR_Ban23 )
+  ( 47 /FPGA_Sp48 )
   ( 48 GND )
   ( 49 ? )
   ( 50 ? )
-  ( 51 /FPGA_Sp69 )
+  ( 51 /FPGA_Sp62 )
   ( 52 GND )
   ( 53 ? )
-  ( 54 /DDR_Ban62 )
+  ( 54 /FPGA_Sp55 )
   ( 55 N-000056 )
-  ( 56 /FPGA_Sp61 )
-  ( 57 /FPGA_Sp66 )
+  ( 56 /FPGA_Sp54 )
+  ( 57 /FPGA_Sp59 )
   ( 58 GND )
-  ( 59 /DDR_Ban65 )
-  ( 60 /DDR_Ban72 )
+  ( 59 /FPGA_Sp58 )
+  ( 60 /FPGA_Sp65 )
   ( 61 N-000056 )
-  ( 62 /FPGA_Sp71 )
-  ( 63 /DDR_Ban76 )
+  ( 62 /DDR_Ban64 )
+  ( 63 /FPGA_Sp69 )
   ( 64 GND )
-  ( 65 /DDR_Ban75 )
+  ( 65 /DDR_Ban68 )
   ( 66 GND )
  )
  ( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG
   ( 1 N-000048 )
-  ( 2 /FPGA_Sp59 )
+  ( 2 /FPGA_Sp52 )
   ( 3 N-000048 )
-  ( 4 /FPGA_Sp60 )
+  ( 4 /FPGA_Sp53 )
   ( 5 ? )
   ( 6 GND )
   ( 7 ? )
   ( 8 ? )
   ( 9 N-000048 )
-  ( 10 /FPGA_Sp39 )
-  ( 11 /DDR_Ban47 )
+  ( 10 /FPGA_Sp33 )
+  ( 11 /FPGA_Sp40 )
   ( 12 GND )
-  ( 13 /DDR_Ban48 )
+  ( 13 /FPGA_Sp41 )
   ( 14 ? )
   ( 15 N-000048 )
-  ( 16 /FPGA_Sp52 )
+  ( 16 /DDR_Ban45 )
   ( 17 ? )
   ( 18 N-000048 )
   ( 19 ? )
-  ( 20 /FPGA_Sp51 )
-  ( 21 /DDR_Ban31 )
-  ( 22 /DDR_Ban34 )
-  ( 23 /FPGA_Sp33 )
+  ( 20 /DDR_Ban44 )
+  ( 21 /DDR_Ban25 )
+  ( 22 /FPGA_Sp28 )
+  ( 23 /FPGA_Sp27 )
   ( 24 ? )
   ( 25 ? )
   ( 26 ? )
   ( 27 ? )
-  ( 28 /FPGA_Sp24 )
-  ( 29 /FPGA_Sp21 )
-  ( 30 /FPGA_Sp22 )
-  ( 31 /FPGA_Sp16 )
-  ( 32 /DDR_Banks/M1_A3 )
+  ( 28 /FPGA_Sp19 )
+  ( 29 /DDR_Banks/M1_A0 )
+  ( 30 /DDR_Banks/M1_A1 )
+  ( 31 /DDR_Banks/M1_A2 )
+  ( 32 /FPGA_Sp20 )
   ( 33 N-000048 )
   ( 34 GND )
-  ( 35 /FPGA_Sp20 )
+  ( 35 /FPGA_Sp17 )
   ( 36 /DDR_Banks/M1_A5 )
-  ( 37 /FPGA_Sp46 )
-  ( 38 /FPGA_Sp15 )
+  ( 37 /DDR_Banks/M1_A6 )
+  ( 38 /DDR_Banks/M1_A7 )
   ( 39 /FPGA_Sp9 )
-  ( 40 /FPGA_Sp10 )
-  ( 41 /FPGA_Sp19 )
-  ( 42 /FPGA_Sp14 )
+  ( 40 /DDR_Banks/M1_A9 )
+  ( 41 /DDR_Ban16 )
+  ( 42 /FPGA_Sp13 )
   ( 43 ? )
-  ( 44 /DDR_Ban38 )
-  ( 45 /FPGA_Sp13 )
-  ( 46 /FPGA_Sp32 )
-  ( 47 /FPGA_Sp56 )
+  ( 44 /FPGA_Sp32 )
+  ( 45 /FPGA_Sp12 )
+  ( 46 /DDR_Ban26 )
+  ( 47 /DDR_Ban49 )
   ( 48 GND )
   ( 49 ? )
   ( 50 ? )
-  ( 51 /DDR_Ban70 )
+  ( 51 /FPGA_Sp63 )
   ( 52 GND )
   ( 53 ? )
-  ( 54 /DDR_Ban63 )
+  ( 54 /FPGA_Sp56 )
   ( 55 N-000048 )
-  ( 56 /FPGA_Sp64 )
-  ( 57 /DDR_Ban67 )
+  ( 56 /FPGA_Sp57 )
+  ( 57 /FPGA_Sp60 )
   ( 58 GND )
-  ( 59 /DDR_Ban68 )
-  ( 60 /FPGA_Sp73 )
+  ( 59 /FPGA_Sp61 )
+  ( 60 /FPGA_Sp66 )
   ( 61 N-000048 )
-  ( 62 /FPGA_Sp74 )
-  ( 63 /FPGA_Sp77 )
+  ( 62 /FPGA_Sp67 )
+  ( 63 /FPGA_Sp70 )
   ( 64 GND )
-  ( 65 /DDR_Ban78 )
+  ( 65 /DDR_Ban71 )
   ( 66 GND )
  )
  ( /4C4320F3/4C432132 LQFP48 U4 K8001
@@ -832,8 +832,8 @@
   ( 3 ? )
   ( 4 ? )
   ( 5 ? )
-  ( 6 /Non_vol79 )
-  ( 7 /Non_vol79 )
+  ( 6 /Non_vol72 )
+  ( 7 /Non_vol72 )
   ( 8 ? )
   ( 9 ? )
   ( 10 ? )
@@ -890,11 +890,11 @@
   ( 12 3.3V )
   ( 14 3.3V )
  )
- ( /4C5F1EDC/4C5F2CA7 $noname$ V1 V0402MHS03
+ ( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03
   ( 1 N-000426 )
   ( 2 GND )
  )
- ( /4C5F1EDC/4C5F2CA3 $noname$ V2 V0402MHS03
+ ( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03
   ( 1 N-000420 )
   ( 2 GND )
  )
diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro
index e834e20..20b006a 100644
--- a/kicad/xue-rnc/xue-rnc.pro
+++ b/kicad/xue-rnc/xue-rnc.pro
@@ -1,4 +1,4 @@
-update=Mon 09 Aug 2010 09:19:33 PM COT
+update=Mon 09 Aug 2010 09:51:02 PM COT
 version=1
 last_client=pcbnew
 [common]
@@ -130,4 +130,5 @@ LibName20=../modules/LQFP48
 LibName21=../modules/48TSOP-NAND
 LibName22=../modules/micro-sd
 LibName23=../modules/60fbga_ddr
-LibName24=/home/afc/devel/Qi/xue/kicad/modules/66-tsop
+LibName24=../modules/66-tsop
+LibName25=../modules/stdpass
diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch
index c17edd5..013b4fa 100644
--- a/kicad/xue-rnc/xue-rnc.sch
+++ b/kicad/xue-rnc/xue-rnc.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:20:06 PM COT
+EESchema Schematic File Version 2  date Mon 09 Aug 2010 09:53:48 PM COT
 LIBS:power
 LIBS:v0402mhs03
 LIBS:usb-48204-0001
@@ -248,17 +248,17 @@ F2 "ETH_RXC" O L 10600 6500 60
 F3 "ETH_RST_N" I L 10600 6600 60 
 F4 "ETH_CRS" O L 10600 6700 60 
 F5 "ETH_COL" O L 10600 6800 60 
-F6 "ETH_INT" O L 10600 6350 60 
-F7 "ETH_MDIO" B L 10600 6900 60 
-F8 "ETH_MDC" I L 10600 7000 60 
-F9 "ETH_RXD[0..3]" O L 10600 7200 60 
-F10 "ETH_RXDV" O L 10600 7300 60 
-F11 "ETH_RXER" O L 10600 7400 60 
-F12 "ETH_TXC" B L 10600 7500 60 
-F13 "ETH_TXD[0..3]" I L 10600 7600 60 
-F14 "ETH_TXEN" I L 10600 7700 60 
-F15 "ETH_TXER" I L 10600 7800 60 
-F16 "ETH_CLK" I L 10600 7900 60 
+F6 "ETH_MDIO" B L 10600 6900 60 
+F7 "ETH_MDC" I L 10600 7000 60 
+F8 "ETH_RXD[0..3]" O L 10600 7200 60 
+F9 "ETH_RXDV" O L 10600 7300 60 
+F10 "ETH_RXER" O L 10600 7400 60 
+F11 "ETH_TXC" B L 10600 7500 60 
+F12 "ETH_TXD[0..3]" I L 10600 7600 60 
+F13 "ETH_TXEN" I L 10600 7700 60 
+F14 "ETH_TXER" I L 10600 7800 60 
+F15 "ETH_CLK" I L 10600 7900 60 
+F16 "ETH_INT" O L 10600 6350 60 
 $EndSheet
 $Sheet
 S 10650 2700 1150 1850