diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 792ce57..f657bbd 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 20 Aug 2010 07:49:18 PM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,7 +49,7 @@ LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 6 7 +Sheet 7 7 Title "" Date "21 aug 2010" Rev "" @@ -59,6 +59,10 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Text Label 9750 1700 1 40 ~ 0 +M1_VREF +Text Label 4400 1750 1 40 ~ 0 +M0_VREF Entry Wire Line 4750 4650 4850 4750 Entry Wire Line diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 77c47ef..d7300f7 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 20 Aug 2010 07:49:18 PM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index d433235..cd9d6b5 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 20 Aug 2010 07:49:18 PM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index a4c4c04..e002c58 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 20 Aug 2010 07:49:18 PM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 65695f1..340d802 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 20 Aug 2010 07:49:18 PM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 118337d..27f3e70 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 20 Aug 2010 07:49:18 PM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 1c56fc3..c7c7f82 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Fri 20 Aug 2010 07:49:18 PM COT +EESchema-LIBRARY Version 2.3 Date: Sat 21 Aug 2010 07:16:33 AM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index db630a3..c88c5c9 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Fri 20 Aug 2010 08:06:18 PM COT +PCBNEW-BOARD Version 1 date Sat 21 Aug 2010 07:16:27 AM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -7,10 +7,10 @@ LayerCount 6 Ly 1FFF801F EnabledLayers 13FF801F Links 675 -NoConn 572 +NoConn 567 Di 45200 13470 70189 50668 Ndraw 7 -Ntrack 859 +Ntrack 884 Nzone 0 BoardThickness 630 Nmodule 161 @@ -94,7 +94,7 @@ Na 6 "/DDR_Banks/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_A3" +Na 7 "/DDR_Banks/M0_A2" St ~ $EndEQUIPOT $EQUIPOT @@ -102,31 +102,31 @@ Na 8 "/DDR_Banks/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_A8" +Na 9 "/DDR_Banks/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_BA0" +Na 10 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_CAS#" +Na 11 "/DDR_Banks/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_CLK" +Na 12 "/DDR_Banks/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_DQ15" +Na 13 "/DDR_Banks/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_DQ2" +Na 14 "/DDR_Banks/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_DQ3" +Na 15 "/DDR_Banks/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT @@ -134,35 +134,35 @@ Na 16 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_DQ8" +Na 17 "/DDR_Banks/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_RAS#" +Na 18 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_WE#" +Na 19 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M1_A11" +Na 20 "/DDR_Banks/M0_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M1_A12" +Na 21 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M1_A4" +Na 22 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_A5" +Na 23 "/DDR_Banks/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_A6" +Na 24 "/DDR_Banks/M1_A7" St ~ $EndEQUIPOT $EQUIPOT @@ -170,15 +170,15 @@ Na 25 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_BA0" +Na 26 "/DDR_Banks/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_BA1" +Na 27 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_CKE" +Na 28 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT @@ -186,55 +186,55 @@ Na 29 "/DDR_Banks/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_DQ0" +Na 30 "/DDR_Banks/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_DQ1" +Na 31 "/DDR_Banks/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_DQ13" +Na 32 "/DDR_Banks/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_DQ14" +Na 33 "/DDR_Banks/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_DQ2" +Na 34 "/DDR_Banks/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_DQ4" +Na 35 "/DDR_Banks/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/DDR_Banks/M1_DQ5" +Na 36 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/DDR_Banks/M1_DQ6" +Na 37 "/DDR_Banks/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M1_LDM" +Na 38 "/DDR_Banks/M1_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/DDR_Banks/M1_RAS#" +Na 39 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/DDR_Banks/M1_WE#" +Na 40 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_A1.8V" +Na 41 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_A3.3V" +Na 42 "/Ethernet_Phy/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT @@ -242,19 +242,19 @@ Na 43 "/Ethernet_Phy/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_INT" +Na 44 "/Ethernet_Phy/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_LED0" +Na 45 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_LED1" +Na 46 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_MDC" +Na 47 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT @@ -270,19 +270,19 @@ Na 50 "/Ethernet_Phy/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Ethernet_Phy/ETH_RXD1" +Na 51 "/Ethernet_Phy/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/Ethernet_Phy/ETH_RXD3" +Na 52 "/Ethernet_Phy/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/Ethernet_Phy/ETH_RXDV" +Na 53 "/Ethernet_Phy/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/Ethernet_Phy/ETH_TXC" +Na 54 "/Ethernet_Phy/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT @@ -294,195 +294,195 @@ Na 56 "/Ethernet_Phy/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/Ethernet_Phy/ETH_TXD3" +Na 57 "/Ethernet_Phy/MAG_RX+" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/Ethernet_Phy/ETH_TXER" +Na 58 "/Ethernet_Phy/MAG_RX-" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/Ethernet_Phy/MAG_RX+" +Na 59 "/Ethernet_Phy/MAG_SHIELD" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/Ethernet_Phy/MAG_RX-" +Na 60 "/Ethernet_Phy/MAG_TX+" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/Ethernet_Phy/MAG_SHIELD" +Na 61 "/Ethernet_Phy/MAG_TX-" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/Ethernet_Phy/MAG_TX+" +Na 62 "/FPGA_Spartan6/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/Ethernet_Phy/MAG_TX-" +Na 63 "/FPGA_Spartan6/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/ETH_CLK" +Na 64 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/ETH_CRS" +Na 65 "/FPGA_Spartan6/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/ETH_MDIO" +Na 66 "/FPGA_Spartan6/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/ETH_RESET_N" +Na 67 "/FPGA_Spartan6/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/ETH_RXD2" +Na 68 "/FPGA_Spartan6/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/ETH_RXER" +Na 69 "/FPGA_Spartan6/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/ETH_TXD0" +Na 70 "/FPGA_Spartan6/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/ETH_TXEN" +Na 71 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_A1" +Na 72 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_A10" +Na 73 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_A11" +Na 74 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_A12" +Na 75 "/FPGA_Spartan6/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_A2" +Na 76 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_A4" +Na 77 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_A6" +Na 78 "/FPGA_Spartan6/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_A7" +Na 79 "/FPGA_Spartan6/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_A9" +Na 80 "/FPGA_Spartan6/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_BA1" +Na 81 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_CKE" +Na 82 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_CLK#" +Na 83 "/FPGA_Spartan6/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_DQ0" +Na 84 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M0_DQ1" +Na 85 "/FPGA_Spartan6/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M0_DQ10" +Na 86 "/FPGA_Spartan6/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M0_DQ11" +Na 87 "/FPGA_Spartan6/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M0_DQ12" +Na 88 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M0_DQ13" +Na 89 "/FPGA_Spartan6/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M0_DQ14" +Na 90 "/FPGA_Spartan6/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M0_DQ5" +Na 91 "/FPGA_Spartan6/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M0_DQ6" +Na 92 "/FPGA_Spartan6/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M0_DQ7" +Na 93 "/FPGA_Spartan6/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M0_DQ9" +Na 94 "/FPGA_Spartan6/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M0_LDM" +Na 95 "/FPGA_Spartan6/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M0_LDQS" +Na 96 "/FPGA_Spartan6/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M0_UDM" +Na 97 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M0_UDQS" +Na 98 "/FPGA_Spartan6/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_A0" +Na 99 "/FPGA_Spartan6/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_A1" +Na 100 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_A10" +Na 101 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_A2" +Na 102 "/FPGA_Spartan6/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_A3" +Na 103 "/FPGA_Spartan6/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_A7" +Na 104 "/FPGA_Spartan6/M1_A6" St ~ $EndEQUIPOT $EQUIPOT @@ -490,507 +490,507 @@ Na 105 "/FPGA_Spartan6/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_CAS#" +Na 106 "/FPGA_Spartan6/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_CLK" +Na 107 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_CLK#" +Na 108 "/FPGA_Spartan6/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ10" +Na 109 "/FPGA_Spartan6/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_DQ11" +Na 110 "/FPGA_Spartan6/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_DQ12" +Na 111 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Spartan6/M1_DQ15" +Na 112 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_DQ3" +Na 113 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Spartan6/M1_DQ7" +Na 114 "/FPGA_Spartan6/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/M1_DQ8" +Na 115 "/FPGA_Spartan6/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/M1_DQ9" +Na 116 "/FPGA_Spartan6/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Spartan6/M1_LDQS" +Na 117 "/FPGA_Spartan6/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA_Spartan6/M1_UDM" +Na 118 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/M1_UDQS" +Na 119 "/FPGA_Spartan6/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Spartan6/NF_D2" +Na 120 "/FPGA_Spartan6/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Spartan6/NF_D3" +Na 121 "/FPGA_Spartan6/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Spartan6/NF_D5" +Na 122 "/FPGA_Spartan6/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Spartan6/NF_RE_N" +Na 123 "/FPGA_Spartan6/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Spartan6/NF_RNB" +Na 124 "/FPGA_Spartan6/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Spartan6/NF_WE_N" +Na 125 "/FPGA_Spartan6/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Spartan6/PROG_CCLK" +Na 126 "/FPGA_Spartan6/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Spartan6/PROG_CSO" +Na 127 "/FPGA_Spartan6/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Spartan6/PROG_MISO0" +Na 128 "/FPGA_Spartan6/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/FPGA_Spartan6/PROG_MISO1" +Na 129 "/FPGA_Spartan6/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/FPGA_Spartan6/PROG_MISO2" +Na 130 "/FPGA_Spartan6/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/FPGA_Spartan6/PROG_MISO3" +Na 131 "/FPGA_Spartan6/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/FPGA_Spartan6/R_M0_A0" +Na 132 "/FPGA_Spartan6/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/FPGA_Spartan6/R_M0_A1" +Na 133 "/FPGA_Spartan6/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/FPGA_Spartan6/R_M0_A10" +Na 134 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/FPGA_Spartan6/R_M0_A11" +Na 135 "/FPGA_Spartan6/R_M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/FPGA_Spartan6/R_M0_A12" +Na 136 "/FPGA_Spartan6/R_M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/FPGA_Spartan6/R_M0_A2" +Na 137 "/FPGA_Spartan6/R_M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/FPGA_Spartan6/R_M0_A3" +Na 138 "/FPGA_Spartan6/R_M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/FPGA_Spartan6/R_M0_A4" +Na 139 "/FPGA_Spartan6/R_M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/FPGA_Spartan6/R_M0_A5" +Na 140 "/FPGA_Spartan6/R_M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/FPGA_Spartan6/R_M0_A6" +Na 141 "/FPGA_Spartan6/R_M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/FPGA_Spartan6/R_M0_A7" +Na 142 "/FPGA_Spartan6/R_M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/FPGA_Spartan6/R_M0_A8" +Na 143 "/FPGA_Spartan6/R_M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/FPGA_Spartan6/R_M0_A9" +Na 144 "/FPGA_Spartan6/R_M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/FPGA_Spartan6/R_M0_BA0" +Na 145 "/FPGA_Spartan6/R_M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/FPGA_Spartan6/R_M0_BA1" +Na 146 "/FPGA_Spartan6/R_M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/FPGA_Spartan6/R_M0_CAS#" +Na 147 "/FPGA_Spartan6/R_M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/FPGA_Spartan6/R_M0_CKE" +Na 148 "/FPGA_Spartan6/R_M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/FPGA_Spartan6/R_M0_DQ0" +Na 149 "/FPGA_Spartan6/R_M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/FPGA_Spartan6/R_M0_DQ1" +Na 150 "/FPGA_Spartan6/R_M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/FPGA_Spartan6/R_M0_DQ10" +Na 151 "/FPGA_Spartan6/R_M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/FPGA_Spartan6/R_M0_DQ11" +Na 152 "/FPGA_Spartan6/R_M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/FPGA_Spartan6/R_M0_DQ12" +Na 153 "/FPGA_Spartan6/R_M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/FPGA_Spartan6/R_M0_DQ13" +Na 154 "/FPGA_Spartan6/R_M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/FPGA_Spartan6/R_M0_DQ14" +Na 155 "/FPGA_Spartan6/R_M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/FPGA_Spartan6/R_M0_DQ15" +Na 156 "/FPGA_Spartan6/R_M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/FPGA_Spartan6/R_M0_DQ2" +Na 157 "/FPGA_Spartan6/R_M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/FPGA_Spartan6/R_M0_DQ3" +Na 158 "/FPGA_Spartan6/R_M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/FPGA_Spartan6/R_M0_DQ4" +Na 159 "/FPGA_Spartan6/R_M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/FPGA_Spartan6/R_M0_DQ5" +Na 160 "/FPGA_Spartan6/R_M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/FPGA_Spartan6/R_M0_DQ6" +Na 161 "/FPGA_Spartan6/R_M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/FPGA_Spartan6/R_M0_DQ7" +Na 162 "/FPGA_Spartan6/R_M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/FPGA_Spartan6/R_M0_DQ8" +Na 163 "/FPGA_Spartan6/R_M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/FPGA_Spartan6/R_M0_DQ9" +Na 164 "/FPGA_Spartan6/R_M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/FPGA_Spartan6/R_M0_LDM" +Na 165 "/FPGA_Spartan6/R_M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/FPGA_Spartan6/R_M0_LDQS" +Na 166 "/FPGA_Spartan6/R_M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/FPGA_Spartan6/R_M0_RAS#" +Na 167 "/FPGA_Spartan6/R_M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/FPGA_Spartan6/R_M0_UDM" +Na 168 "/FPGA_Spartan6/R_M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/FPGA_Spartan6/R_M0_UDQS" +Na 169 "/FPGA_Spartan6/R_M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/FPGA_Spartan6/R_M0_WE#" +Na 170 "/FPGA_Spartan6/R_M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/FPGA_Spartan6/R_M1_A0" +Na 171 "/FPGA_Spartan6/R_M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/FPGA_Spartan6/R_M1_A1" +Na 172 "/FPGA_Spartan6/R_M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/FPGA_Spartan6/R_M1_A10" +Na 173 "/FPGA_Spartan6/R_M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/FPGA_Spartan6/R_M1_A11" +Na 174 "/FPGA_Spartan6/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/FPGA_Spartan6/R_M1_A12" +Na 175 "/FPGA_Spartan6/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/FPGA_Spartan6/R_M1_A2" +Na 176 "/FPGA_Spartan6/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/FPGA_Spartan6/R_M1_A3" +Na 177 "/FPGA_Spartan6/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/FPGA_Spartan6/R_M1_A5" +Na 178 "/FPGA_Spartan6/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/FPGA_Spartan6/R_M1_A6" +Na 179 "/FPGA_Spartan6/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 180 "/FPGA_Spartan6/R_M1_A7" +Na 180 "/FPGA_Spartan6/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/FPGA_Spartan6/R_M1_A8" +Na 181 "/FPGA_Spartan6/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/FPGA_Spartan6/R_M1_A9" +Na 182 "/FPGA_Spartan6/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/FPGA_Spartan6/R_M1_BA0" +Na 183 "/FPGA_Spartan6/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/FPGA_Spartan6/R_M1_BA1" +Na 184 "/FPGA_Spartan6/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "/FPGA_Spartan6/R_M1_CAS#" +Na 185 "/FPGA_Spartan6/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "/FPGA_Spartan6/R_M1_CKE" +Na 186 "/FPGA_Spartan6/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "/FPGA_Spartan6/R_M1_CS#" +Na 187 "/FPGA_Spartan6/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "/FPGA_Spartan6/R_M1_DQ0" +Na 188 "/FPGA_Spartan6/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "/FPGA_Spartan6/R_M1_DQ1" +Na 189 "/FPGA_Spartan6/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "/FPGA_Spartan6/R_M1_DQ10" +Na 190 "/FPGA_Spartan6/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "/FPGA_Spartan6/R_M1_DQ11" +Na 191 "/FPGA_Spartan6/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "/FPGA_Spartan6/R_M1_DQ12" +Na 192 "/FPGA_Spartan6/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "/FPGA_Spartan6/R_M1_DQ13" +Na 193 "/FPGA_Spartan6/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "/FPGA_Spartan6/R_M1_DQ14" +Na 194 "/FPGA_Spartan6/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "/FPGA_Spartan6/R_M1_DQ15" +Na 195 "/FPGA_Spartan6/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "/FPGA_Spartan6/R_M1_DQ2" +Na 196 "/FPGA_Spartan6/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "/FPGA_Spartan6/R_M1_DQ3" +Na 197 "/FPGA_Spartan6/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "/FPGA_Spartan6/R_M1_DQ4" +Na 198 "/FPGA_Spartan6/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "/FPGA_Spartan6/R_M1_DQ5" +Na 199 "/FPGA_Spartan6/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "/FPGA_Spartan6/R_M1_DQ6" +Na 200 "/FPGA_Spartan6/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 201 "/FPGA_Spartan6/R_M1_DQ7" +Na 201 "/FPGA_Spartan6/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 202 "/FPGA_Spartan6/R_M1_DQ8" +Na 202 "/FPGA_Spartan6/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 203 "/FPGA_Spartan6/R_M1_DQ9" +Na 203 "/FPGA_Spartan6/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 204 "/FPGA_Spartan6/R_M1_LDM" +Na 204 "/FPGA_Spartan6/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 205 "/FPGA_Spartan6/R_M1_LDQS" +Na 205 "/FPGA_Spartan6/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 206 "/FPGA_Spartan6/R_M1_RAS#" +Na 206 "/FPGA_Spartan6/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 207 "/FPGA_Spartan6/R_M1_UDM" +Na 207 "/FPGA_Spartan6/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 208 "/FPGA_Spartan6/R_M1_UDQS" +Na 208 "/FPGA_Spartan6/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 209 "/FPGA_Spartan6/R_M1_WE#" +Na 209 "/FPGA_Spartan6/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 210 "/FPGA_Spartan6/SD_CLK" +Na 210 "/FPGA_Spartan6/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 211 "/FPGA_Spartan6/SD_DAT3" +Na 211 "/FPGA_Spartan6/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 212 "/FPGA_Spartan6/USBA_OE_N" +Na 212 "/FPGA_Spartan6/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 213 "/FPGA_Spartan6/USBA_RCV" +Na 213 "/FPGA_Spartan6/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 214 "/Non_volatile_memories/NF_ALE" +Na 214 "/FPGA_Spartan6/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 215 "/Non_volatile_memories/NF_CLE" +Na 215 "/FPGA_Spartan6/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 216 "/Non_volatile_memories/NF_CS1_N" +Na 216 "/FPGA_Spartan6/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 217 "/Non_volatile_memories/NF_D0" +Na 217 "/FPGA_Spartan6/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 218 "/Non_volatile_memories/NF_D1" +Na 218 "/Non_volatile_memories/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 219 "/Non_volatile_memories/NF_D4" +Na 219 "/Non_volatile_memories/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 220 "/Non_volatile_memories/NF_D6" +Na 220 "/Non_volatile_memories/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 221 "/Non_volatile_memories/NF_D7" +Na 221 "/Non_volatile_memories/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 222 "/Non_volatile_memories/SD_CMD" +Na 222 "/Non_volatile_memories/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 223 "/Non_volatile_memories/SD_DAT0" +Na 223 "/Non_volatile_memories/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 224 "/Non_volatile_memories/SD_DAT1" +Na 224 "/Non_volatile_memories/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 225 "/Non_volatile_memories/SD_DAT2" +Na 225 "/Non_volatile_memories/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 226 "/USB/USBA_SPD" +Na 226 "/Non_volatile_memories/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 227 "/USB/USBA_VM" +Na 227 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 228 "/USB/USBA_VP" +Na 228 "/USB/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 229 "GND" +Na 229 "/USB/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 230 "N-000058" +Na 230 "/USB/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 231 "N-000059" +Na 231 "GND" St ~ $EndEQUIPOT $EQUIPOT @@ -1084,134 +1084,130 @@ uViaDia 197 uViaDrill 79 AddNet "" AddNet "/DDR_Banks/M0_A0" -AddNet "/DDR_Banks/M0_A3" +AddNet "/DDR_Banks/M0_A2" AddNet "/DDR_Banks/M0_A5" -AddNet "/DDR_Banks/M0_A8" +AddNet "/DDR_Banks/M0_A6" +AddNet "/DDR_Banks/M0_A7" +AddNet "/DDR_Banks/M0_A9" AddNet "/DDR_Banks/M0_BA0" +AddNet "/DDR_Banks/M0_BA1" AddNet "/DDR_Banks/M0_CAS#" -AddNet "/DDR_Banks/M0_CLK" -AddNet "/DDR_Banks/M0_DQ15" AddNet "/DDR_Banks/M0_DQ2" -AddNet "/DDR_Banks/M0_DQ3" AddNet "/DDR_Banks/M0_DQ4" -AddNet "/DDR_Banks/M0_DQ8" -AddNet "/DDR_Banks/M0_RAS#" +AddNet "/DDR_Banks/M0_DQ5" +AddNet "/DDR_Banks/M0_LDM" +AddNet "/DDR_Banks/M0_LDQS" AddNet "/DDR_Banks/M0_WE#" +AddNet "/DDR_Banks/M1_A0" AddNet "/DDR_Banks/M1_A11" -AddNet "/DDR_Banks/M1_A12" -AddNet "/DDR_Banks/M1_A4" -AddNet "/DDR_Banks/M1_A5" -AddNet "/DDR_Banks/M1_A6" +AddNet "/DDR_Banks/M1_A7" AddNet "/DDR_Banks/M1_A8" -AddNet "/DDR_Banks/M1_BA0" AddNet "/DDR_Banks/M1_BA1" -AddNet "/DDR_Banks/M1_CKE" AddNet "/DDR_Banks/M1_CS#" -AddNet "/DDR_Banks/M1_DQ0" AddNet "/DDR_Banks/M1_DQ1" -AddNet "/DDR_Banks/M1_DQ13" -AddNet "/DDR_Banks/M1_DQ14" -AddNet "/DDR_Banks/M1_DQ2" +AddNet "/DDR_Banks/M1_DQ11" +AddNet "/DDR_Banks/M1_DQ12" +AddNet "/DDR_Banks/M1_DQ15" AddNet "/DDR_Banks/M1_DQ4" -AddNet "/DDR_Banks/M1_DQ5" AddNet "/DDR_Banks/M1_DQ6" -AddNet "/DDR_Banks/M1_LDM" -AddNet "/DDR_Banks/M1_RAS#" +AddNet "/DDR_Banks/M1_UDM" +AddNet "/DDR_Banks/M1_UDQS" +AddNet "/Ethernet_Phy/ETH_CLK" AddNet "/Ethernet_Phy/ETH_COL" +AddNet "/Ethernet_Phy/ETH_CRS" AddNet "/Ethernet_Phy/ETH_INT" -AddNet "/Ethernet_Phy/ETH_MDC" AddNet "/Ethernet_Phy/ETH_RXC" AddNet "/Ethernet_Phy/ETH_RXD0" -AddNet "/Ethernet_Phy/ETH_RXD1" AddNet "/Ethernet_Phy/ETH_RXD3" AddNet "/Ethernet_Phy/ETH_RXDV" -AddNet "/Ethernet_Phy/ETH_TXC" +AddNet "/Ethernet_Phy/ETH_RXER" +AddNet "/Ethernet_Phy/ETH_TXD0" AddNet "/Ethernet_Phy/ETH_TXD1" AddNet "/Ethernet_Phy/ETH_TXD2" -AddNet "/Ethernet_Phy/ETH_TXD3" -AddNet "/Ethernet_Phy/ETH_TXER" -AddNet "/FPGA_Spartan6/ETH_CLK" -AddNet "/FPGA_Spartan6/ETH_CRS" +AddNet "/FPGA_Spartan6/ETH_MDC" AddNet "/FPGA_Spartan6/ETH_MDIO" AddNet "/FPGA_Spartan6/ETH_RESET_N" +AddNet "/FPGA_Spartan6/ETH_RXD1" AddNet "/FPGA_Spartan6/ETH_RXD2" -AddNet "/FPGA_Spartan6/ETH_RXER" -AddNet "/FPGA_Spartan6/ETH_TXD0" +AddNet "/FPGA_Spartan6/ETH_TXC" +AddNet "/FPGA_Spartan6/ETH_TXD3" AddNet "/FPGA_Spartan6/ETH_TXEN" +AddNet "/FPGA_Spartan6/ETH_TXER" AddNet "/FPGA_Spartan6/M0_A1" AddNet "/FPGA_Spartan6/M0_A11" AddNet "/FPGA_Spartan6/M0_A12" -AddNet "/FPGA_Spartan6/M0_A2" +AddNet "/FPGA_Spartan6/M0_A3" AddNet "/FPGA_Spartan6/M0_A4" -AddNet "/FPGA_Spartan6/M0_A6" -AddNet "/FPGA_Spartan6/M0_A7" -AddNet "/FPGA_Spartan6/M0_A9" -AddNet "/FPGA_Spartan6/M0_BA1" +AddNet "/FPGA_Spartan6/M0_A8" AddNet "/FPGA_Spartan6/M0_CKE" -AddNet "/FPGA_Spartan6/M0_CLK#" AddNet "/FPGA_Spartan6/M0_DQ0" AddNet "/FPGA_Spartan6/M0_DQ1" AddNet "/FPGA_Spartan6/M0_DQ11" AddNet "/FPGA_Spartan6/M0_DQ12" AddNet "/FPGA_Spartan6/M0_DQ14" +AddNet "/FPGA_Spartan6/M0_DQ15" +AddNet "/FPGA_Spartan6/M0_DQ3" AddNet "/FPGA_Spartan6/M0_DQ6" +AddNet "/FPGA_Spartan6/M0_DQ8" AddNet "/FPGA_Spartan6/M0_DQ9" -AddNet "/FPGA_Spartan6/M0_LDM" -AddNet "/FPGA_Spartan6/M0_LDQS" +AddNet "/FPGA_Spartan6/M0_RAS#" AddNet "/FPGA_Spartan6/M0_UDM" AddNet "/FPGA_Spartan6/M0_UDQS" -AddNet "/FPGA_Spartan6/M1_A0" AddNet "/FPGA_Spartan6/M1_A1" AddNet "/FPGA_Spartan6/M1_A10" +AddNet "/FPGA_Spartan6/M1_A12" AddNet "/FPGA_Spartan6/M1_A2" AddNet "/FPGA_Spartan6/M1_A3" +AddNet "/FPGA_Spartan6/M1_A4" +AddNet "/FPGA_Spartan6/M1_A5" +AddNet "/FPGA_Spartan6/M1_A6" AddNet "/FPGA_Spartan6/M1_A9" +AddNet "/FPGA_Spartan6/M1_BA0" AddNet "/FPGA_Spartan6/M1_CAS#" -AddNet "/FPGA_Spartan6/M1_CLK" -AddNet "/FPGA_Spartan6/M1_CLK#" +AddNet "/FPGA_Spartan6/M1_CKE" +AddNet "/FPGA_Spartan6/M1_DQ0" AddNet "/FPGA_Spartan6/M1_DQ10" -AddNet "/FPGA_Spartan6/M1_DQ11" -AddNet "/FPGA_Spartan6/M1_DQ12" -AddNet "/FPGA_Spartan6/M1_DQ15" +AddNet "/FPGA_Spartan6/M1_DQ13" +AddNet "/FPGA_Spartan6/M1_DQ14" +AddNet "/FPGA_Spartan6/M1_DQ2" AddNet "/FPGA_Spartan6/M1_DQ3" +AddNet "/FPGA_Spartan6/M1_DQ5" AddNet "/FPGA_Spartan6/M1_DQ7" AddNet "/FPGA_Spartan6/M1_DQ9" +AddNet "/FPGA_Spartan6/M1_LDM" AddNet "/FPGA_Spartan6/M1_LDQS" -AddNet "/FPGA_Spartan6/M1_UDM" -AddNet "/FPGA_Spartan6/M1_UDQS" +AddNet "/FPGA_Spartan6/M1_RAS#" +AddNet "/FPGA_Spartan6/NF_ALE" +AddNet "/FPGA_Spartan6/NF_CLE" AddNet "/FPGA_Spartan6/NF_D2" AddNet "/FPGA_Spartan6/NF_D3" -AddNet "/FPGA_Spartan6/NF_D5" -AddNet "/FPGA_Spartan6/NF_RE_N" +AddNet "/FPGA_Spartan6/NF_D4" +AddNet "/FPGA_Spartan6/NF_D7" AddNet "/FPGA_Spartan6/NF_RNB" -AddNet "/FPGA_Spartan6/NF_WE_N" AddNet "/FPGA_Spartan6/PROG_CCLK" AddNet "/FPGA_Spartan6/PROG_CSO" AddNet "/FPGA_Spartan6/PROG_MISO0" AddNet "/FPGA_Spartan6/PROG_MISO1" AddNet "/FPGA_Spartan6/PROG_MISO2" AddNet "/FPGA_Spartan6/PROG_MISO3" -AddNet "/FPGA_Spartan6/SD_CLK" +AddNet "/FPGA_Spartan6/SD_CMD" +AddNet "/FPGA_Spartan6/SD_DAT0" AddNet "/FPGA_Spartan6/SD_DAT3" AddNet "/FPGA_Spartan6/USBA_OE_N" -AddNet "/FPGA_Spartan6/USBA_RCV" -AddNet "/Non_volatile_memories/NF_ALE" -AddNet "/Non_volatile_memories/NF_CLE" +AddNet "/FPGA_Spartan6/USBA_VM" AddNet "/Non_volatile_memories/NF_CS1_N" AddNet "/Non_volatile_memories/NF_D0" AddNet "/Non_volatile_memories/NF_D1" -AddNet "/Non_volatile_memories/NF_D4" +AddNet "/Non_volatile_memories/NF_D5" AddNet "/Non_volatile_memories/NF_D6" -AddNet "/Non_volatile_memories/NF_D7" -AddNet "/Non_volatile_memories/SD_CMD" -AddNet "/Non_volatile_memories/SD_DAT0" +AddNet "/Non_volatile_memories/NF_RE_N" +AddNet "/Non_volatile_memories/NF_WE_N" +AddNet "/Non_volatile_memories/SD_CLK" AddNet "/Non_volatile_memories/SD_DAT1" AddNet "/Non_volatile_memories/SD_DAT2" +AddNet "/USB/USBA_RCV" AddNet "/USB/USBA_SPD" -AddNet "/USB/USBA_VM" AddNet "/USB/USBA_VP" -AddNet "N-000058" -AddNet "N-000059" AddNet "N-000395" AddNet "N-000397" AddNet "N-000398" @@ -1251,6 +1247,10 @@ ViaDia 157 ViaDrill 79 uViaDia 197 uViaDrill 79 +AddNet "/DDR_Banks/M1_CLK" +AddNet "/DDR_Banks/M1_CLK#" +AddNet "/FPGA_Spartan6/M0_CLK" +AddNet "/FPGA_Spartan6/M0_CLK#" $EndNCLASS $NCLASS Name "DATA/DDR" @@ -1265,9 +1265,7 @@ AddNet "/DDR_Banks/M1_WE#" AddNet "/FPGA_Spartan6/M0_A10" AddNet "/FPGA_Spartan6/M0_DQ10" AddNet "/FPGA_Spartan6/M0_DQ13" -AddNet "/FPGA_Spartan6/M0_DQ5" AddNet "/FPGA_Spartan6/M0_DQ7" -AddNet "/FPGA_Spartan6/M1_A7" AddNet "/FPGA_Spartan6/M1_DQ8" AddNet "/FPGA_Spartan6/R_M0_A0" AddNet "/FPGA_Spartan6/R_M0_A1" @@ -1392,6 +1390,8 @@ AddNet "+1.8V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" +AddNet "/DDR_Banks/M0_VREF" +AddNet "/DDR_Banks/M1_VREF" AddNet "GND" AddNet "VCCO2" $EndNCLASS @@ -1416,7 +1416,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -4133 -4133 $EndPAD $PAD @@ -1437,21 +1437,21 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_CLK" +Ne 42 "/Ethernet_Phy/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXD1" +Ne 65 "/FPGA_Spartan6/ETH_RXD1" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_RXDV" +Ne 52 "/Ethernet_Phy/ETH_RXDV" Po -2165 -4133 $EndPAD $PAD @@ -1465,42 +1465,42 @@ $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/Ethernet_Phy/ETH_TXD3" +Ne 68 "/FPGA_Spartan6/ETH_TXD3" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/ETH_TXD0" +Ne 54 "/Ethernet_Phy/ETH_TXD0" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_INT" +Ne 45 "/Ethernet_Phy/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/Non_volatile_memories/NF_D7" +Ne 127 "/FPGA_Spartan6/NF_D7" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/NF_D3" +Ne 125 "/FPGA_Spartan6/NF_D3" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 218 "/Non_volatile_memories/NF_D1" +Ne 220 "/Non_volatile_memories/NF_D1" Po 590 -4133 $EndPAD $PAD @@ -1514,28 +1514,28 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 214 "/Non_volatile_memories/NF_ALE" +Ne 122 "/FPGA_Spartan6/NF_ALE" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/NF_RNB" +Ne 128 "/FPGA_Spartan6/NF_RNB" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 225 "/Non_volatile_memories/SD_DAT2" +Ne 227 "/Non_volatile_memories/SD_DAT2" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 223 "/Non_volatile_memories/SD_DAT0" +Ne 214 "/FPGA_Spartan6/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -1563,7 +1563,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 4133 -4133 $EndPAD $PAD @@ -1598,7 +1598,7 @@ $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2558 -3739 $EndPAD $PAD @@ -1619,14 +1619,14 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/ETH_RXER" +Ne 53 "/Ethernet_Phy/ETH_RXER" Po -1377 -3739 $EndPAD $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -983 -3739 $EndPAD $PAD @@ -1647,14 +1647,14 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 219 "/Non_volatile_memories/NF_D4" +Ne 126 "/FPGA_Spartan6/NF_D4" Po 196 -3739 $EndPAD $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 590 -3739 $EndPAD $PAD @@ -1675,21 +1675,21 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/NF_RE_N" +Ne 223 "/Non_volatile_memories/NF_RE_N" Po 1771 -3739 $EndPAD $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 2165 -3739 $EndPAD $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 224 "/Non_volatile_memories/SD_DAT1" +Ne 226 "/Non_volatile_memories/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1724,7 +1724,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_Spartan6/R_M0_A11" +Ne 138 "/FPGA_Spartan6/R_M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1752,28 +1752,28 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_RXD3" +Ne 51 "/Ethernet_Phy/ETH_RXD3" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/ETH_RXD2" +Ne 66 "/FPGA_Spartan6/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/ETH_RESET_N" +Ne 64 "/FPGA_Spartan6/ETH_RESET_N" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXC" +Ne 67 "/FPGA_Spartan6/ETH_TXC" Po -1377 -3346 $EndPAD $PAD @@ -1787,7 +1787,7 @@ $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/ETH_CRS" +Ne 44 "/Ethernet_Phy/ETH_CRS" Po -590 -3346 $EndPAD $PAD @@ -1801,14 +1801,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_D5" +Ne 221 "/Non_volatile_memories/NF_D5" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/NF_D2" +Ne 124 "/FPGA_Spartan6/NF_D2" Po 590 -3346 $EndPAD $PAD @@ -1822,21 +1822,21 @@ $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/NF_WE_N" +Ne 224 "/Non_volatile_memories/NF_WE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 216 "/Non_volatile_memories/NF_CS1_N" +Ne 218 "/Non_volatile_memories/NF_CS1_N" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 211 "/FPGA_Spartan6/SD_DAT3" +Ne 215 "/FPGA_Spartan6/SD_DAT3" Po 2165 -3346 $EndPAD $PAD @@ -1857,7 +1857,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/FPGA_Spartan6/R_M1_A8" +Ne 184 "/FPGA_Spartan6/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1871,21 +1871,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/FPGA_Spartan6/R_M1_A9" +Ne 185 "/FPGA_Spartan6/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_Spartan6/R_M0_A12" +Ne 139 "/FPGA_Spartan6/R_M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA_Spartan6/R_M0_CKE" +Ne 151 "/FPGA_Spartan6/R_M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1899,7 +1899,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1913,28 +1913,28 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/ETH_MDIO" +Ne 63 "/FPGA_Spartan6/ETH_MDIO" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_MDC" +Ne 62 "/FPGA_Spartan6/ETH_MDC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/Ethernet_Phy/ETH_TXER" +Ne 70 "/FPGA_Spartan6/ETH_TXER" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/ETH_TXEN" +Ne 69 "/FPGA_Spartan6/ETH_TXEN" Po -983 -2952 $EndPAD $PAD @@ -1948,7 +1948,7 @@ $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 220 "/Non_volatile_memories/NF_D6" +Ne 222 "/Non_volatile_memories/NF_D6" Po -196 -2952 $EndPAD $PAD @@ -1969,14 +1969,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/Non_volatile_memories/NF_D0" +Ne 219 "/Non_volatile_memories/NF_D0" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 215 "/Non_volatile_memories/NF_CLE" +Ne 123 "/FPGA_Spartan6/NF_CLE" Po 1377 -2952 $EndPAD $PAD @@ -1990,14 +1990,14 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "/Non_volatile_memories/SD_CMD" +Ne 213 "/FPGA_Spartan6/SD_CMD" Po 2165 -2952 $EndPAD $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 2558 -2952 $EndPAD $PAD @@ -2018,35 +2018,35 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 186 "/FPGA_Spartan6/R_M1_CKE" +Ne 189 "/FPGA_Spartan6/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/FPGA_Spartan6/R_M1_A12" +Ne 178 "/FPGA_Spartan6/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/FPGA_Spartan6/R_M0_A9" +Ne 147 "/FPGA_Spartan6/R_M0_A9" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/FPGA_Spartan6/R_M0_A8" +Ne 146 "/FPGA_Spartan6/R_M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -2074,7 +2074,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -1771 -2558 $EndPAD $PAD @@ -2102,7 +2102,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -196 -2558 $EndPAD $PAD @@ -2130,14 +2130,14 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 1377 -2558 $EndPAD $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 210 "/FPGA_Spartan6/SD_CLK" +Ne 225 "/Non_volatile_memories/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -2165,21 +2165,21 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 180 "/FPGA_Spartan6/R_M1_A7" +Ne 183 "/FPGA_Spartan6/R_M1_A7" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/FPGA_Spartan6/R_M1_A2" +Ne 179 "/FPGA_Spartan6/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -2193,14 +2193,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/FPGA_Spartan6/R_M0_WE#" +Ne 173 "/FPGA_Spartan6/R_M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/FPGA_Spartan6/R_M0_A4" +Ne 142 "/FPGA_Spartan6/R_M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -2312,7 +2312,7 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/FPGA_Spartan6/R_M1_A11" +Ne 177 "/FPGA_Spartan6/R_M1_A11" Po 2952 -2165 $EndPAD $PAD @@ -2326,21 +2326,21 @@ $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/FPGA_Spartan6/R_M1_A0" +Ne 174 "/FPGA_Spartan6/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/FPGA_Spartan6/R_M1_A1" +Ne 175 "/FPGA_Spartan6/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA_Spartan6/R_M0_BA1" +Ne 149 "/FPGA_Spartan6/R_M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -2354,21 +2354,21 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA_Spartan6/R_M0_BA0" +Ne 148 "/FPGA_Spartan6/R_M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Spartan6/R_M0_A10" +Ne 137 "/FPGA_Spartan6/R_M0_A10" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2558 -1771 $EndPAD $PAD @@ -2459,21 +2459,21 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/FPGA_Spartan6/R_M1_A10" +Ne 176 "/FPGA_Spartan6/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/FPGA_Spartan6/R_M1_A3" +Ne 180 "/FPGA_Spartan6/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2494,49 +2494,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Spartan6/R_M0_A1" +Ne 136 "/FPGA_Spartan6/R_M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Spartan6/R_M0_A0" +Ne 135 "/FPGA_Spartan6/R_M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_CLK#" +Ne 80 "/FPGA_Spartan6/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_CLK" +Ne 79 "/FPGA_Spartan6/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA_Spartan6/R_M0_A2" +Ne 140 "/FPGA_Spartan6/R_M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/FPGA_Spartan6/R_M0_A7" +Ne 145 "/FPGA_Spartan6/R_M0_A7" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -1771 -1377 $EndPAD $PAD @@ -2599,7 +2599,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/FPGA_Spartan6/R_M1_CS#" +Ne 190 "/FPGA_Spartan6/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -2620,56 +2620,56 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 209 "/FPGA_Spartan6/R_M1_WE#" +Ne 212 "/FPGA_Spartan6/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_CLK" +Ne 27 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "/FPGA_Spartan6/R_M1_RAS#" +Ne 209 "/FPGA_Spartan6/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "/FPGA_Spartan6/R_M1_CAS#" +Ne 188 "/FPGA_Spartan6/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/FPGA_Spartan6/R_M0_DQ5" +Ne 163 "/FPGA_Spartan6/R_M0_DQ5" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/FPGA_Spartan6/R_M0_DQ4" +Ne 162 "/FPGA_Spartan6/R_M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/FPGA_Spartan6/R_M0_A6" +Ne 144 "/FPGA_Spartan6/R_M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2704,7 +2704,7 @@ $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -983 -983 $EndPAD $PAD @@ -2718,7 +2718,7 @@ $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -196 -983 $EndPAD $PAD @@ -2732,7 +2732,7 @@ $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 590 -983 $EndPAD $PAD @@ -2746,7 +2746,7 @@ $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 1377 -983 $EndPAD $PAD @@ -2760,7 +2760,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/FPGA_Spartan6/R_M1_BA0" +Ne 186 "/FPGA_Spartan6/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2774,70 +2774,70 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_CLK#" +Ne 28 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 198 "/FPGA_Spartan6/R_M1_DQ4" +Ne 201 "/FPGA_Spartan6/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 199 "/FPGA_Spartan6/R_M1_DQ5" +Ne 202 "/FPGA_Spartan6/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_Spartan6/R_M0_DQ7" +Ne 165 "/FPGA_Spartan6/R_M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_Spartan6/R_M0_DQ6" +Ne 164 "/FPGA_Spartan6/R_M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/FPGA_Spartan6/R_M0_A5" +Ne 143 "/FPGA_Spartan6/R_M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA_Spartan6/R_M0_CAS#" +Ne 150 "/FPGA_Spartan6/R_M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/FPGA_Spartan6/R_M0_RAS#" +Ne 170 "/FPGA_Spartan6/R_M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/FPGA_Spartan6/R_M0_A3" +Ne 141 "/FPGA_Spartan6/R_M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2865,7 +2865,7 @@ $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -590 -590 $EndPAD $PAD @@ -2879,7 +2879,7 @@ $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 196 -590 $EndPAD $PAD @@ -2893,7 +2893,7 @@ $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 983 -590 $EndPAD $PAD @@ -2914,7 +2914,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/FPGA_Spartan6/R_M1_BA1" +Ne 187 "/FPGA_Spartan6/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2928,28 +2928,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/FPGA_Spartan6/R_M1_A6" +Ne 182 "/FPGA_Spartan6/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/FPGA_Spartan6/R_M1_A5" +Ne 181 "/FPGA_Spartan6/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 200 "/FPGA_Spartan6/R_M1_DQ6" +Ne 203 "/FPGA_Spartan6/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "/FPGA_Spartan6/R_M1_DQ7" +Ne 204 "/FPGA_Spartan6/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2970,21 +2970,21 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/FPGA_Spartan6/R_M0_LDQS" +Ne 169 "/FPGA_Spartan6/R_M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/FPGA_Spartan6/R_M0_LDM" +Ne 168 "/FPGA_Spartan6/R_M0_LDM" Po -2952 -196 $EndPAD $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2558 -196 $EndPAD $PAD @@ -3012,7 +3012,7 @@ $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -983 -196 $EndPAD $PAD @@ -3026,7 +3026,7 @@ $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -196 -196 $EndPAD $PAD @@ -3040,7 +3040,7 @@ $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 590 -196 $EndPAD $PAD @@ -3075,21 +3075,21 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 204 "/FPGA_Spartan6/R_M1_LDM" +Ne 207 "/FPGA_Spartan6/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 205 "/FPGA_Spartan6/R_M1_LDQS" +Ne 208 "/FPGA_Spartan6/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -3110,21 +3110,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_Spartan6/R_M0_DQ3" +Ne 161 "/FPGA_Spartan6/R_M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_Spartan6/R_M0_DQ2" +Ne 160 "/FPGA_Spartan6/R_M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/FPGA_Spartan6/R_M0_UDM" +Ne 171 "/FPGA_Spartan6/R_M0_UDM" Po -3346 196 $EndPAD $PAD @@ -3173,7 +3173,7 @@ $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -590 196 $EndPAD $PAD @@ -3187,7 +3187,7 @@ $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 196 196 $EndPAD $PAD @@ -3201,7 +3201,7 @@ $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 983 196 $EndPAD $PAD @@ -3229,7 +3229,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 227 "/USB/USBA_VM" +Ne 217 "/FPGA_Spartan6/USBA_VM" Po 2558 196 $EndPAD $PAD @@ -3243,42 +3243,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 207 "/FPGA_Spartan6/R_M1_UDM" +Ne 210 "/FPGA_Spartan6/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 196 "/FPGA_Spartan6/R_M1_DQ2" +Ne 199 "/FPGA_Spartan6/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 197 "/FPGA_Spartan6/R_M1_DQ3" +Ne 200 "/FPGA_Spartan6/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/FPGA_Spartan6/R_M0_DQ1" +Ne 153 "/FPGA_Spartan6/R_M0_DQ1" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_Spartan6/R_M0_DQ0" +Ne 152 "/FPGA_Spartan6/R_M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -3320,7 +3320,7 @@ $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -983 590 $EndPAD $PAD @@ -3334,7 +3334,7 @@ $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -196 590 $EndPAD $PAD @@ -3348,7 +3348,7 @@ $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 590 590 $EndPAD $PAD @@ -3369,14 +3369,14 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 213 "/FPGA_Spartan6/USBA_RCV" +Ne 228 "/USB/USBA_RCV" Po 1771 590 $EndPAD $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 2165 590 $EndPAD $PAD @@ -3397,35 +3397,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/FPGA_Spartan6/R_M1_DQ0" +Ne 191 "/FPGA_Spartan6/R_M1_DQ0" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/FPGA_Spartan6/R_M1_DQ1" +Ne 192 "/FPGA_Spartan6/R_M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/FPGA_Spartan6/R_M0_DQ9" +Ne 167 "/FPGA_Spartan6/R_M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/FPGA_Spartan6/R_M0_DQ8" +Ne 166 "/FPGA_Spartan6/R_M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3481,7 +3481,7 @@ $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -590 983 $EndPAD $PAD @@ -3495,7 +3495,7 @@ $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 196 983 $EndPAD $PAD @@ -3509,7 +3509,7 @@ $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 983 983 $EndPAD $PAD @@ -3530,14 +3530,14 @@ $PAD Sh "P17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 228 "/USB/USBA_VP" +Ne 230 "/USB/USBA_VP" Po 2165 983 $EndPAD $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 212 "/FPGA_Spartan6/USBA_OE_N" +Ne 216 "/FPGA_Spartan6/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -3558,21 +3558,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 202 "/FPGA_Spartan6/R_M1_DQ8" +Ne 205 "/FPGA_Spartan6/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 203 "/FPGA_Spartan6/R_M1_DQ9" +Ne 206 "/FPGA_Spartan6/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/FPGA_Spartan6/R_M0_DQ11" +Ne 155 "/FPGA_Spartan6/R_M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3586,7 +3586,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/FPGA_Spartan6/R_M0_DQ10" +Ne 154 "/FPGA_Spartan6/R_M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3600,7 +3600,7 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2558 1377 $EndPAD $PAD @@ -3691,21 +3691,21 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 2558 1377 $EndPAD $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 226 "/USB/USBA_SPD" +Ne 229 "/USB/USBA_SPD" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/FPGA_Spartan6/R_M1_DQ10" +Ne 193 "/FPGA_Spartan6/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3719,7 +3719,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/FPGA_Spartan6/R_M1_DQ11" +Ne 194 "/FPGA_Spartan6/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3733,7 +3733,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/FPGA_Spartan6/R_M0_UDQS" +Ne 172 "/FPGA_Spartan6/R_M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3754,7 +3754,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/PROG_CSO" +Ne 130 "/FPGA_Spartan6/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -3866,7 +3866,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 208 "/FPGA_Spartan6/R_M1_UDQS" +Ne 211 "/FPGA_Spartan6/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3880,21 +3880,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_Spartan6/R_M0_DQ13" +Ne 157 "/FPGA_Spartan6/R_M0_DQ13" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_Spartan6/R_M0_DQ12" +Ne 156 "/FPGA_Spartan6/R_M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3922,7 +3922,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -1771 2165 $EndPAD $PAD @@ -3964,14 +3964,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/PROG_MISO3" +Ne 134 "/FPGA_Spartan6/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/PROG_MISO2" +Ne 133 "/FPGA_Spartan6/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -4013,35 +4013,35 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 192 "/FPGA_Spartan6/R_M1_DQ12" +Ne 195 "/FPGA_Spartan6/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 193 "/FPGA_Spartan6/R_M1_DQ13" +Ne 196 "/FPGA_Spartan6/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/FPGA_Spartan6/R_M0_DQ15" +Ne 159 "/FPGA_Spartan6/R_M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/FPGA_Spartan6/R_M0_DQ14" +Ne 158 "/FPGA_Spartan6/R_M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -4055,7 +4055,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2952 2558 $EndPAD $PAD @@ -4097,7 +4097,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -590 2558 $EndPAD $PAD @@ -4125,7 +4125,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 983 2558 $EndPAD $PAD @@ -4174,14 +4174,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 194 "/FPGA_Spartan6/R_M1_DQ14" +Ne 197 "/FPGA_Spartan6/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 195 "/FPGA_Spartan6/R_M1_DQ15" +Ne 198 "/FPGA_Spartan6/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -4230,7 +4230,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -1771 2952 $EndPAD $PAD @@ -4293,7 +4293,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 1771 2952 $EndPAD $PAD @@ -4314,7 +4314,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 2952 2952 $EndPAD $PAD @@ -4524,7 +4524,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2558 3739 $EndPAD $PAD @@ -4552,7 +4552,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -983 3739 $EndPAD $PAD @@ -4580,7 +4580,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 590 3739 $EndPAD $PAD @@ -4608,7 +4608,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 2165 3739 $EndPAD $PAD @@ -4629,14 +4629,14 @@ $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/PROG_MISO1" +Ne 132 "/FPGA_Spartan6/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/PROG_CCLK" +Ne 129 "/FPGA_Spartan6/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -4650,7 +4650,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -4133 4133 $EndPAD $PAD @@ -4783,7 +4783,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/PROG_MISO0" +Ne 131 "/FPGA_Spartan6/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -4797,7 +4797,7 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 @@ -4819,7 +4819,7 @@ $PAD Sh "PAD" R 904 628 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 0 0 $EndPAD $PAD @@ -4840,7 +4840,7 @@ $PAD Sh "2" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -196 491 $EndPAD $PAD @@ -4882,7 +4882,7 @@ $PAD Sh "5" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 393 491 $EndPAD $PAD @@ -4917,7 +4917,7 @@ $PAD Sh "2" R 157 236 0 0 1350 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4945,12 +4945,12 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 48094 33902 1800 0 4C5FF890 4C6B21D8 ~~ +Po 48327 34055 1800 0 4C5FF890 4C6B21D8 ~~ Li 0402 Sc 4C6B21D8 AR /4C431A63/4C6B216E @@ -4966,19 +4966,19 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/FPGA_Spartan6/R_M0_UDM" +Ne 171 "/FPGA_Spartan6/R_M0_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 97 "/FPGA_Spartan6/M0_UDM" +Ne 95 "/FPGA_Spartan6/M0_UDM" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 48098 34902 1800 0 4C5FF890 4C6B21D6 ~~ +Po 48327 35039 1800 0 4C5FF890 4C6B21D6 ~~ Li 0402 Sc 4C6B21D6 AR /4C431A63/4C6B216D @@ -4994,19 +4994,19 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/FPGA_Spartan6/R_M0_UDQS" +Ne 172 "/FPGA_Spartan6/R_M0_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 98 "/FPGA_Spartan6/M0_UDQS" +Ne 96 "/FPGA_Spartan6/M0_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 48091 33394 1800 0 4C5FF890 4C6B21D2 ~~ +Po 48327 33268 1800 0 4C5FF890 4C6B21D2 ~~ Li 0402 Sc 4C6B21D2 AR /4C431A63/4C6B216B @@ -5022,14 +5022,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 148 "/FPGA_Spartan6/R_M0_CKE" +Ne 151 "/FPGA_Spartan6/R_M0_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 82 "/FPGA_Spartan6/M0_CKE" +Ne 78 "/FPGA_Spartan6/M0_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5050,14 +5050,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 12 "/DDR_Banks/M0_CLK" +Ne 79 "/FPGA_Spartan6/M0_CLK" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 83 "/FPGA_Spartan6/M0_CLK#" +Ne 80 "/FPGA_Spartan6/M0_CLK#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5076,49 +5076,49 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 132 "/FPGA_Spartan6/R_M0_A0" +Ne 135 "/FPGA_Spartan6/R_M0_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 133 "/FPGA_Spartan6/R_M0_A1" +Ne 136 "/FPGA_Spartan6/R_M0_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 137 "/FPGA_Spartan6/R_M0_A2" +Ne 140 "/FPGA_Spartan6/R_M0_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 138 "/FPGA_Spartan6/R_M0_A3" +Ne 141 "/FPGA_Spartan6/R_M0_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 7 "/DDR_Banks/M0_A3" +Ne 75 "/FPGA_Spartan6/M0_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 76 "/FPGA_Spartan6/M0_A2" +Ne 7 "/DDR_Banks/M0_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 72 "/FPGA_Spartan6/M0_A1" +Ne 71 "/FPGA_Spartan6/M0_A1" Po -98 177 $EndPAD $PAD @@ -5144,56 +5144,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/FPGA_Spartan6/R_M0_RAS#" +Ne 170 "/FPGA_Spartan6/R_M0_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 145 "/FPGA_Spartan6/R_M0_BA0" +Ne 148 "/FPGA_Spartan6/R_M0_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 146 "/FPGA_Spartan6/R_M0_BA1" +Ne 149 "/FPGA_Spartan6/R_M0_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 134 "/FPGA_Spartan6/R_M0_A10" +Ne 137 "/FPGA_Spartan6/R_M0_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 73 "/FPGA_Spartan6/M0_A10" +Ne 72 "/FPGA_Spartan6/M0_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 81 "/FPGA_Spartan6/M0_BA1" +Ne 13 "/DDR_Banks/M0_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 10 "/DDR_Banks/M0_BA0" +Ne 12 "/DDR_Banks/M0_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Banks/M0_RAS#" +Ne 94 "/FPGA_Spartan6/M0_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5212,56 +5212,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/FPGA_Spartan6/R_M0_LDQS" +Ne 169 "/FPGA_Spartan6/R_M0_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/FPGA_Spartan6/R_M0_LDM" +Ne 168 "/FPGA_Spartan6/R_M0_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/FPGA_Spartan6/R_M0_WE#" +Ne 173 "/FPGA_Spartan6/R_M0_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 147 "/FPGA_Spartan6/R_M0_CAS#" +Ne 150 "/FPGA_Spartan6/R_M0_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 11 "/DDR_Banks/M0_CAS#" +Ne 14 "/DDR_Banks/M0_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 19 "/DDR_Banks/M0_WE#" +Ne 21 "/DDR_Banks/M0_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/FPGA_Spartan6/M0_LDM" +Ne 18 "/DDR_Banks/M0_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 96 "/FPGA_Spartan6/M0_LDQS" +Ne 19 "/DDR_Banks/M0_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5280,35 +5280,35 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/FPGA_Spartan6/R_M0_A7" +Ne 145 "/FPGA_Spartan6/R_M0_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 141 "/FPGA_Spartan6/R_M0_A6" +Ne 144 "/FPGA_Spartan6/R_M0_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 140 "/FPGA_Spartan6/R_M0_A5" +Ne 143 "/FPGA_Spartan6/R_M0_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 139 "/FPGA_Spartan6/R_M0_A4" +Ne 142 "/FPGA_Spartan6/R_M0_A4" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 77 "/FPGA_Spartan6/M0_A4" +Ne 76 "/FPGA_Spartan6/M0_A4" Po 295 177 $EndPAD $PAD @@ -5322,14 +5322,14 @@ $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 78 "/FPGA_Spartan6/M0_A6" +Ne 9 "/DDR_Banks/M0_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 79 "/FPGA_Spartan6/M0_A7" +Ne 10 "/DDR_Banks/M0_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5348,56 +5348,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 136 "/FPGA_Spartan6/R_M0_A12" +Ne 139 "/FPGA_Spartan6/R_M0_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 135 "/FPGA_Spartan6/R_M0_A11" +Ne 138 "/FPGA_Spartan6/R_M0_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/FPGA_Spartan6/R_M0_A9" +Ne 147 "/FPGA_Spartan6/R_M0_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/FPGA_Spartan6/R_M0_A8" +Ne 146 "/FPGA_Spartan6/R_M0_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 9 "/DDR_Banks/M0_A8" +Ne 77 "/FPGA_Spartan6/M0_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 80 "/FPGA_Spartan6/M0_A9" +Ne 11 "/DDR_Banks/M0_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 74 "/FPGA_Spartan6/M0_A11" +Ne 73 "/FPGA_Spartan6/M0_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 75 "/FPGA_Spartan6/M0_A12" +Ne 74 "/FPGA_Spartan6/M0_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5416,49 +5416,49 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/FPGA_Spartan6/R_M0_DQ4" +Ne 162 "/FPGA_Spartan6/R_M0_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/FPGA_Spartan6/R_M0_DQ5" +Ne 163 "/FPGA_Spartan6/R_M0_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/FPGA_Spartan6/R_M0_DQ6" +Ne 164 "/FPGA_Spartan6/R_M0_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/FPGA_Spartan6/R_M0_DQ7" +Ne 165 "/FPGA_Spartan6/R_M0_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 93 "/FPGA_Spartan6/M0_DQ7" +Ne 91 "/FPGA_Spartan6/M0_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 92 "/FPGA_Spartan6/M0_DQ6" +Ne 90 "/FPGA_Spartan6/M0_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 91 "/FPGA_Spartan6/M0_DQ5" +Ne 17 "/DDR_Banks/M0_DQ5" Po -98 177 $EndPAD $PAD @@ -5484,56 +5484,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/FPGA_Spartan6/R_M0_DQ0" +Ne 152 "/FPGA_Spartan6/R_M0_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/FPGA_Spartan6/R_M0_DQ1" +Ne 153 "/FPGA_Spartan6/R_M0_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/FPGA_Spartan6/R_M0_DQ2" +Ne 160 "/FPGA_Spartan6/R_M0_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/FPGA_Spartan6/R_M0_DQ3" +Ne 161 "/FPGA_Spartan6/R_M0_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 15 "/DDR_Banks/M0_DQ3" +Ne 89 "/FPGA_Spartan6/M0_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 14 "/DDR_Banks/M0_DQ2" +Ne 15 "/DDR_Banks/M0_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 85 "/FPGA_Spartan6/M0_DQ1" +Ne 82 "/FPGA_Spartan6/M0_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Spartan6/M0_DQ0" +Ne 81 "/FPGA_Spartan6/M0_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5552,56 +5552,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/FPGA_Spartan6/R_M0_DQ8" +Ne 166 "/FPGA_Spartan6/R_M0_DQ8" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/FPGA_Spartan6/R_M0_DQ9" +Ne 167 "/FPGA_Spartan6/R_M0_DQ9" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 151 "/FPGA_Spartan6/R_M0_DQ10" +Ne 154 "/FPGA_Spartan6/R_M0_DQ10" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 152 "/FPGA_Spartan6/R_M0_DQ11" +Ne 155 "/FPGA_Spartan6/R_M0_DQ11" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 87 "/FPGA_Spartan6/M0_DQ11" +Ne 84 "/FPGA_Spartan6/M0_DQ11" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 86 "/FPGA_Spartan6/M0_DQ10" +Ne 83 "/FPGA_Spartan6/M0_DQ10" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/FPGA_Spartan6/M0_DQ9" +Ne 93 "/FPGA_Spartan6/M0_DQ9" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 17 "/DDR_Banks/M0_DQ8" +Ne 92 "/FPGA_Spartan6/M0_DQ8" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5620,56 +5620,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/FPGA_Spartan6/R_M0_DQ12" +Ne 156 "/FPGA_Spartan6/R_M0_DQ12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 154 "/FPGA_Spartan6/R_M0_DQ13" +Ne 157 "/FPGA_Spartan6/R_M0_DQ13" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/FPGA_Spartan6/R_M0_DQ14" +Ne 158 "/FPGA_Spartan6/R_M0_DQ14" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/FPGA_Spartan6/R_M0_DQ15" +Ne 159 "/FPGA_Spartan6/R_M0_DQ15" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 13 "/DDR_Banks/M0_DQ15" +Ne 88 "/FPGA_Spartan6/M0_DQ15" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 90 "/FPGA_Spartan6/M0_DQ14" +Ne 87 "/FPGA_Spartan6/M0_DQ14" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 89 "/FPGA_Spartan6/M0_DQ13" +Ne 86 "/FPGA_Spartan6/M0_DQ13" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 88 "/FPGA_Spartan6/M0_DQ12" +Ne 85 "/FPGA_Spartan6/M0_DQ12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5691,28 +5691,28 @@ $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -235 -235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 235 -235 $EndPAD $PAD @@ -5824,7 +5824,7 @@ $PAD Sh "8" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 688 0 $EndPAD $PAD @@ -5873,14 +5873,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 208 "/FPGA_Spartan6/R_M1_UDQS" +Ne 211 "/FPGA_Spartan6/R_M1_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 119 "/FPGA_Spartan6/M1_UDQS" +Ne 37 "/DDR_Banks/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5901,7 +5901,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 187 "/FPGA_Spartan6/R_M1_CS#" +Ne 190 "/FPGA_Spartan6/R_M1_CS#" Po -176 0 $EndPAD $PAD @@ -5929,14 +5929,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 186 "/FPGA_Spartan6/R_M1_CKE" +Ne 189 "/FPGA_Spartan6/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M1_CKE" +Ne 108 "/FPGA_Spartan6/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5957,14 +5957,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 207 "/FPGA_Spartan6/R_M1_UDM" +Ne 210 "/FPGA_Spartan6/R_M1_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "/FPGA_Spartan6/M1_UDM" +Ne 36 "/DDR_Banks/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5983,56 +5983,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 195 "/FPGA_Spartan6/R_M1_DQ15" +Ne 198 "/FPGA_Spartan6/R_M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 194 "/FPGA_Spartan6/R_M1_DQ14" +Ne 197 "/FPGA_Spartan6/R_M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 193 "/FPGA_Spartan6/R_M1_DQ13" +Ne 196 "/FPGA_Spartan6/R_M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 192 "/FPGA_Spartan6/R_M1_DQ12" +Ne 195 "/FPGA_Spartan6/R_M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 111 "/FPGA_Spartan6/M1_DQ12" +Ne 32 "/DDR_Banks/M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Banks/M1_DQ13" +Ne 111 "/FPGA_Spartan6/M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_DQ14" +Ne 112 "/FPGA_Spartan6/M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 112 "/FPGA_Spartan6/M1_DQ15" +Ne 33 "/DDR_Banks/M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6051,56 +6051,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 191 "/FPGA_Spartan6/R_M1_DQ11" +Ne 194 "/FPGA_Spartan6/R_M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 190 "/FPGA_Spartan6/R_M1_DQ10" +Ne 193 "/FPGA_Spartan6/R_M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 203 "/FPGA_Spartan6/R_M1_DQ9" +Ne 206 "/FPGA_Spartan6/R_M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 202 "/FPGA_Spartan6/R_M1_DQ8" +Ne 205 "/FPGA_Spartan6/R_M1_DQ8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 115 "/FPGA_Spartan6/M1_DQ8" +Ne 117 "/FPGA_Spartan6/M1_DQ8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 116 "/FPGA_Spartan6/M1_DQ9" +Ne 118 "/FPGA_Spartan6/M1_DQ9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 109 "/FPGA_Spartan6/M1_DQ10" +Ne 110 "/FPGA_Spartan6/M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 110 "/FPGA_Spartan6/M1_DQ11" +Ne 31 "/DDR_Banks/M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6121,14 +6121,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 108 "/FPGA_Spartan6/M1_CLK#" +Ne 28 "/DDR_Banks/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/FPGA_Spartan6/M1_CLK" +Ne 27 "/DDR_Banks/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6147,28 +6147,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 175 "/FPGA_Spartan6/R_M1_A12" +Ne 178 "/FPGA_Spartan6/R_M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 174 "/FPGA_Spartan6/R_M1_A11" +Ne 177 "/FPGA_Spartan6/R_M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/FPGA_Spartan6/R_M1_A9" +Ne 185 "/FPGA_Spartan6/R_M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/FPGA_Spartan6/R_M1_A8" +Ne 184 "/FPGA_Spartan6/R_M1_A8" Po 295 -177 $EndPAD $PAD @@ -6189,14 +6189,14 @@ $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/DDR_Banks/M1_A11" +Ne 23 "/DDR_Banks/M1_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 21 "/DDR_Banks/M1_A12" +Ne 99 "/FPGA_Spartan6/M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6215,21 +6215,21 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 180 "/FPGA_Spartan6/R_M1_A7" +Ne 183 "/FPGA_Spartan6/R_M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 179 "/FPGA_Spartan6/R_M1_A6" +Ne 182 "/FPGA_Spartan6/R_M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 178 "/FPGA_Spartan6/R_M1_A5" +Ne 181 "/FPGA_Spartan6/R_M1_A5" Po 98 -177 $EndPAD $PAD @@ -6243,28 +6243,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 22 "/DDR_Banks/M1_A4" +Ne 102 "/FPGA_Spartan6/M1_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/DDR_Banks/M1_A5" +Ne 103 "/FPGA_Spartan6/M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Banks/M1_A6" +Ne 104 "/FPGA_Spartan6/M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/FPGA_Spartan6/M1_A7" +Ne 24 "/DDR_Banks/M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6283,56 +6283,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 188 "/FPGA_Spartan6/R_M1_DQ0" +Ne 191 "/FPGA_Spartan6/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 189 "/FPGA_Spartan6/R_M1_DQ1" +Ne 192 "/FPGA_Spartan6/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 196 "/FPGA_Spartan6/R_M1_DQ2" +Ne 199 "/FPGA_Spartan6/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 197 "/FPGA_Spartan6/R_M1_DQ3" +Ne 200 "/FPGA_Spartan6/R_M1_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 113 "/FPGA_Spartan6/M1_DQ3" +Ne 114 "/FPGA_Spartan6/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/DDR_Banks/M1_DQ2" +Ne 113 "/FPGA_Spartan6/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/DDR_Banks/M1_DQ1" +Ne 30 "/DDR_Banks/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Banks/M1_DQ0" +Ne 109 "/FPGA_Spartan6/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6351,56 +6351,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 205 "/FPGA_Spartan6/R_M1_LDQS" +Ne 208 "/FPGA_Spartan6/R_M1_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 204 "/FPGA_Spartan6/R_M1_LDM" +Ne 207 "/FPGA_Spartan6/R_M1_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 209 "/FPGA_Spartan6/R_M1_WE#" +Ne 212 "/FPGA_Spartan6/R_M1_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "/FPGA_Spartan6/R_M1_CAS#" +Ne 188 "/FPGA_Spartan6/R_M1_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 106 "/FPGA_Spartan6/M1_CAS#" +Ne 107 "/FPGA_Spartan6/M1_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/DDR_Banks/M1_WE#" +Ne 39 "/DDR_Banks/M1_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_LDM" +Ne 119 "/FPGA_Spartan6/M1_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 117 "/FPGA_Spartan6/M1_LDQS" +Ne 120 "/FPGA_Spartan6/M1_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6419,56 +6419,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 198 "/FPGA_Spartan6/R_M1_DQ4" +Ne 201 "/FPGA_Spartan6/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 199 "/FPGA_Spartan6/R_M1_DQ5" +Ne 202 "/FPGA_Spartan6/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 200 "/FPGA_Spartan6/R_M1_DQ6" +Ne 203 "/FPGA_Spartan6/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "/FPGA_Spartan6/R_M1_DQ7" +Ne 204 "/FPGA_Spartan6/R_M1_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 114 "/FPGA_Spartan6/M1_DQ7" +Ne 116 "/FPGA_Spartan6/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 37 "/DDR_Banks/M1_DQ6" +Ne 35 "/DDR_Banks/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 36 "/DDR_Banks/M1_DQ5" +Ne 115 "/FPGA_Spartan6/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/DDR_Banks/M1_DQ4" +Ne 34 "/DDR_Banks/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6487,56 +6487,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 206 "/FPGA_Spartan6/R_M1_RAS#" +Ne 209 "/FPGA_Spartan6/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/FPGA_Spartan6/R_M1_BA0" +Ne 186 "/FPGA_Spartan6/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/FPGA_Spartan6/R_M1_BA1" +Ne 187 "/FPGA_Spartan6/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 173 "/FPGA_Spartan6/R_M1_A10" +Ne 176 "/FPGA_Spartan6/R_M1_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 101 "/FPGA_Spartan6/M1_A10" +Ne 98 "/FPGA_Spartan6/M1_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Banks/M1_BA1" +Ne 26 "/DDR_Banks/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Banks/M1_BA0" +Ne 106 "/FPGA_Spartan6/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M1_RAS#" +Ne 121 "/FPGA_Spartan6/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6555,56 +6555,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/FPGA_Spartan6/R_M1_A0" +Ne 174 "/FPGA_Spartan6/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 172 "/FPGA_Spartan6/R_M1_A1" +Ne 175 "/FPGA_Spartan6/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 176 "/FPGA_Spartan6/R_M1_A2" +Ne 179 "/FPGA_Spartan6/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 177 "/FPGA_Spartan6/R_M1_A3" +Ne 180 "/FPGA_Spartan6/R_M1_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/FPGA_Spartan6/M1_A3" +Ne 101 "/FPGA_Spartan6/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 102 "/FPGA_Spartan6/M1_A2" +Ne 100 "/FPGA_Spartan6/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 100 "/FPGA_Spartan6/M1_A1" +Ne 97 "/FPGA_Spartan6/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 99 "/FPGA_Spartan6/M1_A0" +Ne 22 "/DDR_Banks/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6625,7 +6625,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -176 0 $EndPAD $PAD @@ -6653,7 +6653,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_A1.8V" +Ne 40 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD @@ -6688,7 +6688,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_A1.8V" +Ne 40 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6716,7 +6716,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/Ethernet_Phy/ETH_A3.3V" +Ne 41 "/Ethernet_Phy/ETH_A3.3V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6744,7 +6744,7 @@ $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -6772,7 +6772,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6800,7 +6800,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6828,7 +6828,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6856,7 +6856,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6890,49 +6890,49 @@ $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/PROG_CSO" +Ne 130 "/FPGA_Spartan6/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/PROG_MISO3" +Ne 134 "/FPGA_Spartan6/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/PROG_CCLK" +Ne 129 "/FPGA_Spartan6/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/PROG_MISO0" +Ne 131 "/FPGA_Spartan6/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/PROG_MISO1" +Ne 132 "/FPGA_Spartan6/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/PROG_MISO2" +Ne 133 "/FPGA_Spartan6/PROG_MISO2" Po 250 1050 $EndPAD $PAD Sh "4" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 750 1050 $EndPAD $SHAPE3D @@ -6966,7 +6966,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -6994,7 +6994,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7022,7 +7022,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7050,7 +7050,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7078,7 +7078,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7106,7 +7106,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7134,7 +7134,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7162,7 +7162,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7190,7 +7190,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7218,7 +7218,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7246,7 +7246,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7274,7 +7274,7 @@ $PAD Sh "2" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7302,7 +7302,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7330,7 +7330,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7358,7 +7358,7 @@ $PAD Sh "2" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7386,7 +7386,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7414,7 +7414,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7442,7 +7442,7 @@ $PAD Sh "2" R 157 236 0 0 2250 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7470,7 +7470,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7498,7 +7498,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7526,7 +7526,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7554,7 +7554,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7582,7 +7582,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7610,7 +7610,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7638,7 +7638,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7666,7 +7666,7 @@ $PAD Sh "2" R 157 236 0 0 1350 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7694,7 +7694,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7722,7 +7722,7 @@ $PAD Sh "2" R 157 236 0 0 450 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7750,7 +7750,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7778,7 +7778,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7806,7 +7806,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7834,7 +7834,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7905,14 +7905,14 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 767 -1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 767 1112 $EndPAD $PAD @@ -8010,7 +8010,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -8038,7 +8038,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -8066,7 +8066,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8094,7 +8094,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8122,7 +8122,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8150,7 +8150,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8178,7 +8178,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8206,7 +8206,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8290,7 +8290,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8311,14 +8311,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 230 "N-000058" +Ne 38 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8346,7 +8346,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8374,7 +8374,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8402,7 +8402,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8430,7 +8430,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8458,7 +8458,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8486,7 +8486,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8514,40 +8514,40 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 47126 35524 0 0 4C5FF890 4C61CF27 ~~ +Po 47126 35524 1800 0 4C5FF890 4C61CF27 ~~ Li 0402 Sc 4C61CF27 AR /4C421DD3/4C61CF27 Op 0 0 0 At SMD -T0 0 150 200 200 0 40 M V 20 N"C26" -T1 0 -150 200 200 0 40 M I 20 N"10nF" +T0 0 150 200 200 1800 40 M V 20 N"C26" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 Ne 3 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46260 37402 0 0 4C5FF890 4C61CF17 ~~ +Po 47500 37000 0 0 4C5FF890 4C61CF17 ~~ Li 0402 Sc 4C61CF17 AR /4C421DD3/4C61CF17 @@ -8570,7 +8570,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8598,7 +8598,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8626,7 +8626,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8654,7 +8654,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8682,12 +8682,12 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 230 "N-000058" +Ne 38 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46200 34200 0 0 4C5FF890 4C61CDB5 ~~ +Po 47441 34646 0 0 4C5FF890 4C61CDB5 ~~ Li 0402 Sc 4C61CDB5 AR /4C421DD3/4C61CDB5 @@ -8703,19 +8703,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "N-000059" +Ne 20 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46200 33000 1800 0 4C5FF890 4C61CD4A ~~ +Po 47441 33169 1800 0 4C5FF890 4C61CD4A ~~ Li 0402 Sc 4C61CD4A AR /4C421DD3/4C61CD4A @@ -8738,7 +8738,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "N-000059" +Ne 20 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8766,7 +8766,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 230 "N-000058" +Ne 38 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8787,19 +8787,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 230 "N-000058" +Ne 38 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46200 33800 0 0 4C5FF890 4C61CC96 ~~ +Po 47441 34154 0 0 4C5FF890 4C61CC96 ~~ Li 0402 Sc 4C61CC96 AR /4C421DD3/4C61CC96 @@ -8815,19 +8815,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "N-000059" +Ne 20 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46200 33400 1800 0 4C5FF890 4C61CC73 ~~ +Po 47441 33661 1800 0 4C5FF890 4C61CC73 ~~ Li 0402 Sc 4C61CC73 AR /4C421DD3/4C61CC73 @@ -8850,7 +8850,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "N-000059" +Ne 20 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8981,7 +8981,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9002,14 +9002,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_A3.3V" +Ne 41 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9037,7 +9037,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9065,7 +9065,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9093,7 +9093,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9121,7 +9121,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9149,7 +9149,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9177,7 +9177,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9205,7 +9205,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9233,7 +9233,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9261,7 +9261,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9282,14 +9282,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_A1.8V" +Ne 40 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9310,14 +9310,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/Ethernet_Phy/ETH_A3.3V" +Ne 41 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9345,7 +9345,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9373,7 +9373,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9401,7 +9401,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9422,14 +9422,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 61 "/Ethernet_Phy/MAG_SHIELD" +Ne 59 "/Ethernet_Phy/MAG_SHIELD" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9457,7 +9457,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9478,7 +9478,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 66 "/FPGA_Spartan6/ETH_MDIO" +Ne 63 "/FPGA_Spartan6/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -9513,7 +9513,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9541,7 +9541,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 62 "/Ethernet_Phy/MAG_TX+" +Ne 60 "/Ethernet_Phy/MAG_TX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9569,7 +9569,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 63 "/Ethernet_Phy/MAG_TX-" +Ne 61 "/Ethernet_Phy/MAG_TX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9597,7 +9597,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 59 "/Ethernet_Phy/MAG_RX+" +Ne 57 "/Ethernet_Phy/MAG_RX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9625,7 +9625,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 60 "/Ethernet_Phy/MAG_RX-" +Ne 58 "/Ethernet_Phy/MAG_RX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9653,7 +9653,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 45 "/Ethernet_Phy/ETH_LED0" +Ne 46 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9681,7 +9681,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/Ethernet_Phy/ETH_LED1" +Ne 47 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9702,14 +9702,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 61 "/Ethernet_Phy/MAG_SHIELD" +Ne 59 "/Ethernet_Phy/MAG_SHIELD" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9737,7 +9737,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9766,7 +9766,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ0" +Ne 81 "/FPGA_Spartan6/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -9780,28 +9780,28 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ1" +Ne 82 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ2" +Ne 15 "/DDR_Banks/M0_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ3" +Ne 89 "/FPGA_Spartan6/M0_DQ3" Po -2558 2176 $EndPAD $PAD @@ -9822,28 +9822,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M0_DQ5" +Ne 17 "/DDR_Banks/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M0_DQ6" +Ne 90 "/FPGA_Spartan6/M0_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M0_DQ7" +Ne 91 "/FPGA_Spartan6/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -9864,7 +9864,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M0_LDQS" +Ne 19 "/DDR_Banks/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -9892,35 +9892,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M0_LDM" +Ne 18 "/DDR_Banks/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_WE#" +Ne 21 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_CAS#" +Ne 14 "/DDR_Banks/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_RAS#" +Ne 94 "/FPGA_Spartan6/M0_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 1791 2176 $EndPAD $PAD @@ -9934,21 +9934,21 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_BA0" +Ne 12 "/DDR_Banks/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_BA1" +Ne 13 "/DDR_Banks/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_A10" +Ne 72 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD @@ -9962,21 +9962,21 @@ $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_A1" +Ne 71 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_A2" +Ne 7 "/DDR_Banks/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A3" +Ne 75 "/FPGA_Spartan6/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -9990,14 +9990,14 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_A4" +Ne 76 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD @@ -10011,42 +10011,42 @@ $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_A6" +Ne 9 "/DDR_Banks/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_A7" +Ne 10 "/DDR_Banks/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A8" +Ne 77 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_A9" +Ne 11 "/DDR_Banks/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_A11" +Ne 73 "/FPGA_Spartan6/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_A12" +Ne 74 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -10060,42 +10060,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_CLK#" +Ne 80 "/FPGA_Spartan6/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_CKE" +Ne 78 "/FPGA_Spartan6/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_CLK" +Ne 79 "/FPGA_Spartan6/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M0_UDM" +Ne 95 "/FPGA_Spartan6/M0_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "N-000059" +Ne 20 "/DDR_Banks/M0_VREF" Po 255 -2176 $EndPAD $PAD @@ -10109,14 +10109,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M0_UDQS" +Ne 96 "/FPGA_Spartan6/M0_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -511 -2176 $EndPAD $PAD @@ -10130,7 +10130,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ8" +Ne 92 "/FPGA_Spartan6/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10144,35 +10144,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M0_DQ9" +Ne 93 "/FPGA_Spartan6/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ10" +Ne 83 "/FPGA_Spartan6/M0_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_DQ11" +Ne 84 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_DQ12" +Ne 85 "/FPGA_Spartan6/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10186,35 +10186,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M0_DQ13" +Ne 86 "/FPGA_Spartan6/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M0_DQ14" +Ne 87 "/FPGA_Spartan6/M0_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ15" +Ne 88 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -10243,7 +10243,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ0" +Ne 109 "/FPGA_Spartan6/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -10257,35 +10257,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ1" +Ne 30 "/DDR_Banks/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_DQ2" +Ne 113 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_DQ3" +Ne 114 "/FPGA_Spartan6/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_DQ4" +Ne 34 "/DDR_Banks/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -10299,28 +10299,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_DQ5" +Ne 115 "/FPGA_Spartan6/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/DDR_Banks/M1_DQ6" +Ne 35 "/DDR_Banks/M1_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/M1_DQ7" +Ne 116 "/FPGA_Spartan6/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -10341,7 +10341,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/M1_LDQS" +Ne 120 "/FPGA_Spartan6/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -10369,28 +10369,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_LDM" +Ne 119 "/FPGA_Spartan6/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/DDR_Banks/M1_WE#" +Ne 39 "/DDR_Banks/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_CAS#" +Ne 107 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M1_RAS#" +Ne 121 "/FPGA_Spartan6/M1_RAS#" Po 1535 2176 $EndPAD $PAD @@ -10411,49 +10411,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_BA0" +Ne 106 "/FPGA_Spartan6/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_BA1" +Ne 26 "/DDR_Banks/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_A10" +Ne 98 "/FPGA_Spartan6/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_A0" +Ne 22 "/DDR_Banks/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_A1" +Ne 97 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_A2" +Ne 100 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_A3" +Ne 101 "/FPGA_Spartan6/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -10467,35 +10467,35 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_A4" +Ne 102 "/FPGA_Spartan6/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A5" +Ne 103 "/FPGA_Spartan6/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A6" +Ne 104 "/FPGA_Spartan6/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_A7" +Ne 24 "/DDR_Banks/M1_A7" Po 3070 -2176 $EndPAD $PAD @@ -10516,14 +10516,14 @@ $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_A11" +Ne 23 "/DDR_Banks/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_A12" +Ne 99 "/FPGA_Spartan6/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -10537,42 +10537,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_CLK#" +Ne 28 "/DDR_Banks/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_CKE" +Ne 108 "/FPGA_Spartan6/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_CLK" +Ne 27 "/DDR_Banks/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/M1_UDM" +Ne 36 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 230 "N-000058" +Ne 38 "/DDR_Banks/M1_VREF" Po 255 -2176 $EndPAD $PAD @@ -10586,14 +10586,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/M1_UDQS" +Ne 37 "/DDR_Banks/M1_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -511 -2176 $EndPAD $PAD @@ -10607,7 +10607,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/M1_DQ8" +Ne 117 "/FPGA_Spartan6/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10621,35 +10621,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/M1_DQ9" +Ne 118 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ10" +Ne 110 "/FPGA_Spartan6/M1_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ11" +Ne 31 "/DDR_Banks/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_DQ12" +Ne 32 "/DDR_Banks/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10663,35 +10663,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_DQ13" +Ne 111 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_DQ14" +Ne 112 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_DQ15" +Ne 33 "/DDR_Banks/M1_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -10727,28 +10727,28 @@ $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 226 "/USB/USBA_SPD" +Ne 229 "/USB/USBA_SPD" Po -511 -1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 213 "/FPGA_Spartan6/USBA_RCV" +Ne 228 "/USB/USBA_RCV" Po -255 -1112 $EndPAD $PAD Sh "4" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 228 "/USB/USBA_VP" +Ne 230 "/USB/USBA_VP" Po 0 -1112 $EndPAD $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 227 "/USB/USBA_VM" +Ne 217 "/FPGA_Spartan6/USBA_VM" Po 255 -1112 $EndPAD $PAD @@ -10762,21 +10762,21 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 767 -1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 767 1112 $EndPAD $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 212 "/FPGA_Spartan6/USBA_OE_N" +Ne 216 "/FPGA_Spartan6/USBA_OE_N" Po 511 1112 $EndPAD $PAD @@ -10831,35 +10831,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 61 "/Ethernet_Phy/MAG_SHIELD" +Ne 59 "/Ethernet_Phy/MAG_SHIELD" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 61 "/Ethernet_Phy/MAG_SHIELD" +Ne 59 "/Ethernet_Phy/MAG_SHIELD" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 61 "/Ethernet_Phy/MAG_SHIELD" +Ne 59 "/Ethernet_Phy/MAG_SHIELD" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 61 "/Ethernet_Phy/MAG_SHIELD" +Ne 59 "/Ethernet_Phy/MAG_SHIELD" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 62 "/Ethernet_Phy/MAG_TX+" +Ne 60 "/Ethernet_Phy/MAG_TX+" Po -1750 -2500 $EndPAD $PAD @@ -10873,28 +10873,28 @@ $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 229 "GND" +Ne 231 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 59 "/Ethernet_Phy/MAG_RX+" +Ne 57 "/Ethernet_Phy/MAG_RX+" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 63 "/Ethernet_Phy/MAG_TX-" +Ne 61 "/Ethernet_Phy/MAG_TX-" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 229 "GND" +Ne 231 "GND" Po -250 -3500 $EndPAD $PAD @@ -10908,7 +10908,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 60 "/Ethernet_Phy/MAG_RX-" +Ne 58 "/Ethernet_Phy/MAG_RX-" Po 1750 -3500 $EndPAD $PAD @@ -10961,21 +10961,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 225 "/Non_volatile_memories/SD_DAT2" +Ne 227 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 211 "/FPGA_Spartan6/SD_DAT3" +Ne 215 "/FPGA_Spartan6/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 222 "/Non_volatile_memories/SD_CMD" +Ne 213 "/FPGA_Spartan6/SD_CMD" Po -433 0 $EndPAD $PAD @@ -10989,56 +10989,56 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 210 "/FPGA_Spartan6/SD_CLK" +Ne 225 "/Non_volatile_memories/SD_CLK" Po 433 0 $EndPAD $PAD Sh "6" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 866 0 $EndPAD $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 223 "/Non_volatile_memories/SD_DAT0" +Ne 214 "/FPGA_Spartan6/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 224 "/Non_volatile_memories/SD_DAT1" +Ne 226 "/Non_volatile_memories/SD_DAT1" Po 1732 0 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po -2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po -2707 -2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 229 "GND" +Ne 231 "GND" Po 2707 -2244 $EndPAD $EndMODULE MICROSD-500901 @@ -11302,28 +11302,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/NF_RNB" +Ne 128 "/FPGA_Spartan6/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/NF_RNB" +Ne 128 "/FPGA_Spartan6/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/NF_RE_N" +Ne 223 "/Non_volatile_memories/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 216 "/Non_volatile_memories/NF_CS1_N" +Ne 218 "/Non_volatile_memories/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -11351,7 +11351,7 @@ $PAD Sh "13" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 100 3850 $EndPAD $PAD @@ -11372,21 +11372,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 215 "/Non_volatile_memories/NF_CLE" +Ne 123 "/FPGA_Spartan6/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 214 "/Non_volatile_memories/NF_ALE" +Ne 122 "/FPGA_Spartan6/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/NF_WE_N" +Ne 224 "/Non_volatile_memories/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -11463,28 +11463,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/Non_volatile_memories/NF_D0" +Ne 219 "/Non_volatile_memories/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 218 "/Non_volatile_memories/NF_D1" +Ne 220 "/Non_volatile_memories/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/NF_D2" +Ne 124 "/FPGA_Spartan6/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/NF_D3" +Ne 125 "/FPGA_Spartan6/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -11512,7 +11512,7 @@ $PAD Sh "36" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 100 -3850 $EndPAD $PAD @@ -11547,28 +11547,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 219 "/Non_volatile_memories/NF_D4" +Ne 126 "/FPGA_Spartan6/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_D5" +Ne 221 "/Non_volatile_memories/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 220 "/Non_volatile_memories/NF_D6" +Ne 222 "/Non_volatile_memories/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/Non_volatile_memories/NF_D7" +Ne 127 "/FPGA_Spartan6/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -11618,14 +11618,14 @@ $PAD Sh "12" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -1613 1082 $EndPAD $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/ETH_RXER" +Ne 53 "/Ethernet_Phy/ETH_RXER" Po -1613 885 $EndPAD $PAD @@ -11639,14 +11639,14 @@ $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_RXDV" +Ne 52 "/Ethernet_Phy/ETH_RXDV" Po -1613 491 $EndPAD $PAD Sh "8" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -1613 295 $EndPAD $PAD @@ -11667,42 +11667,42 @@ $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXD1" +Ne 65 "/FPGA_Spartan6/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/ETH_RXD2" +Ne 66 "/FPGA_Spartan6/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_RXD3" +Ne 51 "/Ethernet_Phy/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_MDC" +Ne 62 "/FPGA_Spartan6/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/ETH_MDIO" +Ne 63 "/FPGA_Spartan6/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/ETH_RESET_N" +Ne 64 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD @@ -11716,7 +11716,7 @@ $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_CLK" +Ne 42 "/Ethernet_Phy/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -11730,7 +11730,7 @@ $PAD Sh "44" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po -295 -1613 $EndPAD $PAD @@ -11751,28 +11751,28 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/Ethernet_Phy/MAG_TX+" +Ne 60 "/Ethernet_Phy/MAG_TX+" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/Ethernet_Phy/MAG_TX-" +Ne 61 "/Ethernet_Phy/MAG_TX-" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_A3.3V" +Ne 41 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD @@ -11786,21 +11786,21 @@ $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_INT" +Ne 45 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_LED0" +Ne 46 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_LED1" +Ne 47 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -11828,21 +11828,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_A1.8V" +Ne 40 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/Ethernet_Phy/MAG_RX-" +Ne 58 "/Ethernet_Phy/MAG_RX-" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/Ethernet_Phy/MAG_RX+" +Ne 57 "/Ethernet_Phy/MAG_RX+" Po 1613 -491 $EndPAD $PAD @@ -11856,14 +11856,14 @@ $PAD Sh "35" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 1613 -1082 $EndPAD $PAD @@ -11877,28 +11877,28 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/Ethernet_Phy/ETH_TXER" +Ne 70 "/FPGA_Spartan6/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXC" +Ne 67 "/FPGA_Spartan6/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/ETH_TXEN" +Ne 69 "/FPGA_Spartan6/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/ETH_TXD0" +Ne 54 "/Ethernet_Phy/ETH_TXD0" Po -295 1613 $EndPAD $PAD @@ -11919,7 +11919,7 @@ $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/Ethernet_Phy/ETH_TXD3" +Ne 68 "/FPGA_Spartan6/ETH_TXD3" Po 295 1613 $EndPAD $PAD @@ -11933,14 +11933,14 @@ $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/ETH_CRS" +Ne 44 "/Ethernet_Phy/ETH_CRS" Po 688 1613 $EndPAD $PAD Sh "23" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 885 1613 $EndPAD $PAD @@ -11975,7 +11975,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -12018,7 +12018,7 @@ $PAD Sh "2" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 0 500 $EndPAD $PAD @@ -12074,7 +12074,7 @@ $PAD Sh "2" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 0 500 $EndPAD $PAD @@ -12143,7 +12143,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12199,7 +12199,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12227,7 +12227,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12283,7 +12283,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12339,7 +12339,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -12367,7 +12367,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -12395,7 +12395,7 @@ $PAD Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -12423,7 +12423,7 @@ $PAD Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 229 "GND" +Ne 231 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -12598,15 +12598,17 @@ Po 3 50693 31575 50693 31575 157 -1 De 15 1 6 0 0 Po 0 50694 31576 50693 31575 39 -1 De 15 0 6 0 0 -Po 0 50995 30808 50048 30808 39 -1 +Po 0 50995 31064 50688 31064 39 -1 De 15 0 7 0 800 -Po 0 49909 30945 49768 30945 39 -1 +Po 0 50189 31142 49768 31142 39 -1 De 0 0 7 0 400 -Po 0 50047 30807 49909 30945 39 -1 +Po 0 50264 31067 50189 31142 39 -1 De 0 0 7 0 0 -Po 3 50047 30807 50047 30807 157 -1 +Po 0 50685 31067 50264 31067 39 -1 +De 0 0 7 0 0 +Po 3 50685 31067 50685 31067 157 -1 De 15 1 7 0 0 -Po 0 50048 30808 50047 30807 39 -1 +Po 0 50688 31064 50685 31067 39 -1 De 15 0 7 0 0 Po 0 47937 31338 47294 31338 39 -1 De 0 0 8 0 800 @@ -12618,114 +12620,74 @@ Po 3 47110 31154 47110 31154 157 -1 De 15 1 8 0 0 Po 0 47294 31338 47110 31154 39 -1 De 0 0 8 0 0 -Po 0 47941 32527 47256 32527 39 -1 +Po 0 47937 31142 47417 31142 39 -1 De 0 0 9 0 800 -Po 0 46883 31832 46643 31832 39 -1 +Po 0 47239 31320 46643 31320 39 -1 De 15 0 9 0 400 -Po 0 46980 31929 46883 31832 39 -1 +Po 0 47417 31142 47239 31320 39 -1 De 15 0 9 0 0 -Po 3 46980 31929 46980 31929 157 -1 +Po 3 47417 31142 47417 31142 157 -1 De 15 1 9 0 0 -Po 0 46980 32251 46980 31929 39 -1 -De 0 0 9 0 0 -Po 0 47256 32527 46980 32251 39 -1 -De 0 0 9 0 0 -Po 0 50995 32344 50017 32344 39 -1 -De 15 0 10 0 800 -Po 0 49988 32315 49775 32315 39 -1 -De 0 0 10 0 400 -Po 0 50016 32343 49988 32315 39 -1 -De 0 0 10 0 0 -Po 3 50016 32343 50016 32343 157 -1 -De 15 1 10 0 0 -Po 0 50017 32344 50016 32343 39 -1 +Po 0 47937 30945 47646 30945 39 -1 +De 0 0 10 0 800 +Po 0 47417 31576 46643 31576 39 -1 +De 15 0 10 0 400 +Po 0 47575 31418 47417 31576 39 -1 De 15 0 10 0 0 -Po 0 50995 33367 50298 33367 39 -1 -De 15 0 11 0 800 -Po 0 50039 33626 49795 33626 39 -1 -De 0 0 11 0 400 -Po 0 50055 33610 50039 33626 39 -1 -De 0 0 11 0 0 -Po 3 50055 33610 50055 33610 157 -1 -De 15 1 11 0 0 -Po 0 50298 33367 50055 33610 39 -1 +Po 0 47575 31016 47575 31418 39 -1 +De 15 0 10 0 0 +Po 0 47646 30945 47575 31016 39 -1 +De 15 0 10 0 0 +Po 3 47646 30945 47646 30945 157 -1 +De 15 1 10 0 0 +Po 0 47941 32330 47353 32330 39 -1 +De 0 0 11 0 800 +Po 0 47111 32088 46643 32088 39 -1 +De 15 0 11 0 400 +Po 0 47165 32142 47111 32088 39 -1 De 15 0 11 0 0 -Po 0 51858 33439 52896 33439 39 -1 -De 3 0 12 0 0 -Po 0 51677 33439 51858 33439 39 -1 -De 3 0 12 0 0 -Po 3 53126 33209 53126 33209 157 -1 -De 15 1 12 0 0 -Po 0 53126 33209 53317 33018 39 -1 -De 15 0 12 0 0 -Po 0 53317 33018 53317 33001 39 -1 -De 15 0 12 0 400 -Po 0 52896 33439 53126 33209 39 -1 -De 3 0 12 0 0 -Po 0 51551 33439 51568 33439 39 -1 -De 3 0 12 0 0 -Po 0 51568 33439 51618 33489 39 -1 -De 3 0 12 0 0 -Po 0 51677 33439 51668 33439 39 -1 -De 3 0 12 0 0 -Po 0 51668 33439 51618 33489 39 -1 -De 3 0 12 0 0 -Po 0 51618 33439 51618 33489 39 -1 -De 3 0 12 0 0 -Po 0 51618 33489 51618 33543 39 -1 -De 3 0 12 0 0 -Po 0 51568 33593 51370 33593 39 -1 -De 0 0 12 0 400 -Po 0 51598 33563 51568 33593 39 -1 -De 0 0 12 0 0 -Po 3 51598 33563 51598 33563 157 -1 -De 15 1 12 0 0 -Po 0 51618 33543 51598 33563 39 -1 -De 3 0 12 0 0 -Po 0 46643 33623 46922 33623 39 -1 +Po 3 47165 32142 47165 32142 157 -1 +De 15 1 11 0 0 +Po 0 47353 32330 47165 32142 39 -1 +De 0 0 11 0 0 +Po 0 50995 32344 50017 32344 39 -1 De 15 0 12 0 800 -Po 0 47112 33439 51551 33439 39 -1 -De 3 0 12 0 0 -Po 0 51551 33439 51618 33439 39 -1 -De 3 0 12 0 0 -Po 0 51618 33439 51677 33439 39 -1 -De 3 0 12 0 0 -Po 0 46925 33626 47112 33439 39 -1 -De 3 0 12 0 0 -Po 3 46925 33626 46925 33626 157 -1 -De 15 1 12 0 0 -Po 0 46922 33623 46925 33626 39 -1 -De 15 0 12 0 0 -Po 0 51370 33567 51370 33593 39 -1 +Po 0 49988 32315 49775 32315 39 -1 De 0 0 12 0 400 -Po 0 47362 38082 47260 38082 39 -1 -De 0 0 13 0 800 -Po 0 46858 38484 46643 38484 39 -1 -De 15 0 13 0 400 -Po 0 46972 38370 46858 38484 39 -1 -De 15 0 13 0 0 -Po 3 46972 38370 46972 38370 157 -1 -De 15 1 13 0 0 -Po 0 47260 38082 46972 38370 39 -1 +Po 0 50016 32343 49988 32315 39 -1 +De 0 0 12 0 0 +Po 3 50016 32343 50016 32343 157 -1 +De 15 1 12 0 0 +Po 0 50017 32344 50016 32343 39 -1 +De 15 0 12 0 0 +Po 0 50995 32088 50706 32088 39 -1 +De 15 0 13 0 800 +Po 0 50657 32119 49775 32119 39 -1 +De 0 0 13 0 400 +Po 0 50697 32079 50657 32119 39 -1 De 0 0 13 0 0 -Po 0 49838 37693 50661 37693 39 -1 -De 0 0 14 0 800 -Po 0 50684 37716 50995 37716 39 -1 -De 15 0 14 0 400 -Po 0 50661 37693 50684 37716 39 -1 -De 15 0 14 0 0 -Po 3 50661 37693 50661 37693 157 -1 +Po 3 50697 32079 50697 32079 157 -1 +De 15 1 13 0 0 +Po 0 50706 32088 50697 32079 39 -1 +De 15 0 13 0 0 +Po 0 50995 33367 50298 33367 39 -1 +De 15 0 14 0 800 +Po 0 50039 33626 49795 33626 39 -1 +De 0 0 14 0 400 +Po 0 50055 33610 50039 33626 39 -1 +De 0 0 14 0 0 +Po 3 50055 33610 50055 33610 157 -1 De 15 1 14 0 0 -Po 0 50995 37204 50320 37204 39 -1 -De 15 0 15 0 800 -Po 0 50028 37496 49838 37496 39 -1 -De 0 0 15 0 400 -Po 0 50059 37465 50028 37496 39 -1 -De 0 0 15 0 0 -Po 3 50059 37465 50059 37465 157 -1 -De 15 1 15 0 0 -Po 0 50320 37204 50059 37465 39 -1 +Po 0 50298 33367 50055 33610 39 -1 +De 15 0 14 0 0 +Po 0 49838 37693 50661 37693 39 -1 +De 0 0 15 0 800 +Po 0 50684 37716 50995 37716 39 -1 +De 15 0 15 0 400 +Po 0 50661 37693 50684 37716 39 -1 De 15 0 15 0 0 +Po 3 50661 37693 50661 37693 157 -1 +De 15 1 15 0 0 Po 0 49846 36535 49976 36535 39 -1 De 0 0 16 0 800 Po 0 50709 36949 50995 36949 39 -1 @@ -12738,60 +12700,110 @@ Po 0 50370 36929 50689 36929 39 -1 De 0 0 16 0 0 Po 0 49976 36535 50370 36929 39 -1 De 0 0 16 0 0 -Po 0 46643 35669 46826 35669 39 -1 -De 15 0 17 0 800 -Po 0 47157 36000 47351 36000 39 -1 -De 0 0 17 0 400 -Po 0 47035 35878 47157 36000 39 -1 -De 0 0 17 0 0 -Po 3 47035 35878 47035 35878 157 -1 -De 15 1 17 0 0 -Po 0 46826 35669 47035 35878 39 -1 +Po 0 49846 36338 50056 36338 39 -1 +De 0 0 17 0 800 +Po 0 50161 36437 50995 36437 39 -1 +De 15 0 17 0 400 +Po 0 50059 36335 50161 36437 39 -1 De 15 0 17 0 0 -Po 0 49775 32512 49858 32512 39 -1 -De 0 0 18 0 800 -Po 0 50457 33111 50995 33111 39 -1 -De 15 0 18 0 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-Po 0 52131 32607 51949 32425 39 -1 -De 15 0 146 0 0 -Po 0 51949 32425 51465 32425 39 -1 -De 15 0 146 0 0 -Po 0 50294 32283 50192 32181 39 -1 -De 3 0 146 0 0 -Po 0 50192 32181 49075 32181 39 -1 -De 3 0 146 0 0 -Po 0 49075 32181 49067 32173 39 -1 -De 3 0 146 0 0 -Po 0 49067 32173 49063 32173 39 -1 -De 3 0 146 0 0 -Po 3 49063 32173 49063 32173 157 -1 -De 15 1 146 0 0 -Po 0 49063 32173 49117 32119 39 -1 -De 0 0 146 0 0 -Po 0 49421 32119 49117 32119 39 -1 De 0 0 146 0 800 -Po 0 52131 32607 52136 32607 39 -1 +Po 0 52922 31820 52923 31820 39 -1 De 15 0 146 0 400 -Po 0 51414 32425 51465 32425 39 -1 +Po 0 52720 31618 52922 31820 39 -1 De 15 0 146 0 0 -Po 0 51272 32283 51414 32425 39 -1 -De 15 0 146 0 0 -Po 3 51272 32283 51272 32283 157 -1 +Po 3 52720 31618 52720 31618 157 -1 De 15 1 146 0 0 -Po 0 51791 33776 52928 33776 39 -1 -De 3 0 147 0 0 -Po 0 51791 33776 49189 33776 39 -1 -De 3 0 147 0 0 -Po 0 49189 33776 49181 33768 39 -1 -De 3 0 147 0 0 -Po 0 49441 33626 49039 33626 39 -1 +Po 0 52503 31835 52720 31618 39 -1 +De 0 0 146 0 0 +Po 0 52279 31835 52503 31835 39 -1 +De 0 0 146 0 0 +Po 0 51405 32709 52279 31835 39 -1 +De 0 0 146 0 0 +Po 0 50958 32709 51405 32709 39 -1 +De 0 0 146 0 0 +Po 0 50801 32866 50958 32709 39 -1 +De 0 0 146 0 0 +Po 0 50496 32866 50801 32866 39 -1 +De 0 0 146 0 0 +Po 0 50265 33097 50496 32866 39 -1 +De 0 0 146 0 0 +Po 0 48908 33097 50265 33097 39 -1 +De 0 0 146 0 0 +Po 0 48669 32858 48908 33097 39 -1 +De 0 0 146 0 0 +Po 0 48669 32625 48669 32858 39 -1 +De 0 0 146 0 0 +Po 0 48571 32527 48669 32625 39 -1 +De 0 0 146 0 0 +Po 0 48295 32330 48665 32330 39 -1 De 0 0 147 0 800 -Po 0 53288 33788 53317 33788 39 -1 +Po 0 52136 31774 52136 31820 39 -1 De 15 0 147 0 400 -Po 0 53102 33602 53288 33788 39 -1 +Po 0 52323 31587 52136 31774 39 -1 De 15 0 147 0 0 -Po 3 53102 33602 53102 33602 157 -1 +Po 3 52323 31587 52323 31587 157 -1 De 15 1 147 0 0 -Po 0 49035 33622 49181 33768 39 -1 -De 3 0 147 0 0 -Po 3 49035 33622 49035 33622 157 -1 -De 15 1 147 0 0 -Po 0 49039 33626 49035 33622 39 -1 +Po 0 51882 32028 52323 31587 39 -1 De 0 0 147 0 0 +Po 0 51882 32067 51882 32028 39 -1 +De 0 0 147 0 0 +Po 0 51339 32610 51882 32067 39 -1 +De 0 0 147 0 0 +Po 0 50902 32610 51339 32610 39 -1 +De 0 0 147 0 0 +Po 0 50752 32760 50902 32610 39 -1 +De 0 0 147 0 0 +Po 0 50445 32760 50752 32760 39 -1 +De 0 0 147 0 0 +Po 0 50209 32996 50445 32760 39 -1 +De 0 0 147 0 0 +Po 0 48969 32996 50209 32996 39 -1 +De 0 0 147 0 0 +Po 0 48776 32803 48969 32996 39 -1 +De 0 0 147 0 0 +Po 0 48776 32441 48776 32803 39 -1 +De 0 0 147 0 0 +Po 0 48665 32330 48776 32441 39 -1 +De 0 0 147 0 0 +Po 0 52923 32607 52923 32576 39 -1 +De 15 0 148 0 800 +Po 0 49138 32315 49421 32315 39 -1 +De 0 0 148 0 400 +Po 0 49059 32394 49138 32315 39 -1 +De 0 0 148 0 0 +Po 3 49059 32394 49059 32394 157 -1 +De 15 1 148 0 0 +Po 0 49433 32394 49059 32394 39 -1 +De 3 0 148 0 0 +Po 0 49559 32520 49433 32394 39 -1 +De 3 0 148 0 0 +Po 0 50197 32520 49559 32520 39 -1 +De 3 0 148 0 0 +Po 3 50197 32520 50197 32520 157 -1 +De 15 1 148 0 0 +Po 0 50567 32520 50197 32520 39 -1 +De 0 0 148 0 0 +Po 0 51036 32051 50567 32520 39 -1 +De 0 0 148 0 0 +Po 0 51323 32051 51036 32051 39 -1 +De 0 0 148 0 0 +Po 0 51331 32059 51323 32051 39 -1 +De 0 0 148 0 0 +Po 3 51331 32059 51331 32059 157 -1 +De 15 1 148 0 0 +Po 0 51575 32303 51331 32059 39 -1 +De 15 0 148 0 0 +Po 0 51996 32303 51575 32303 39 -1 +De 15 0 148 0 0 +Po 0 52102 32409 51996 32303 39 -1 +De 15 0 148 0 0 +Po 0 52756 32409 52102 32409 39 -1 +De 15 0 148 0 0 +Po 0 52923 32576 52756 32409 39 -1 +De 15 0 148 0 0 +Po 0 50294 32283 51272 32283 39 -1 +De 3 0 149 0 0 +Po 0 52131 32607 51949 32425 39 -1 +De 15 0 149 0 0 +Po 0 51949 32425 51465 32425 39 -1 +De 15 0 149 0 0 +Po 0 50294 32283 50192 32181 39 -1 +De 3 0 149 0 0 +Po 0 50192 32181 49075 32181 39 -1 +De 3 0 149 0 0 +Po 0 49075 32181 49067 32173 39 -1 +De 3 0 149 0 0 +Po 0 49067 32173 49063 32173 39 -1 +De 3 0 149 0 0 +Po 3 49063 32173 49063 32173 157 -1 +De 15 1 149 0 0 +Po 0 49063 32173 49117 32119 39 -1 +De 0 0 149 0 0 +Po 0 49421 32119 49117 32119 39 -1 +De 0 0 149 0 800 +Po 0 52131 32607 52136 32607 39 -1 +De 15 0 149 0 400 +Po 0 51414 32425 51465 32425 39 -1 +De 15 0 149 0 0 +Po 0 51272 32283 51414 32425 39 -1 +De 15 0 149 0 0 +Po 3 51272 32283 51272 32283 157 -1 +De 15 1 149 0 0 +Po 0 51791 33776 52928 33776 39 -1 +De 3 0 150 0 0 +Po 0 51791 33776 49189 33776 39 -1 +De 3 0 150 0 0 +Po 0 49189 33776 49181 33768 39 -1 +De 3 0 150 0 0 +Po 0 49441 33626 49039 33626 39 -1 +De 0 0 150 0 800 +Po 0 53288 33788 53317 33788 39 -1 +De 15 0 150 0 400 +Po 0 53102 33602 53288 33788 39 -1 +De 15 0 150 0 0 +Po 3 53102 33602 53102 33602 157 -1 +De 15 1 150 0 0 +Po 0 49035 33622 49181 33768 39 -1 +De 3 0 150 0 0 +Po 3 49035 33622 49035 33622 157 -1 +De 15 1 150 0 0 +Po 0 49039 33626 49035 33622 39 -1 +De 0 0 150 0 0 Po 0 52928 33776 53102 33602 39 -1 -De 3 0 147 0 0 +De 3 0 150 0 0 Po 0 51926 34106 52035 34106 39 -1 -De 3 0 165 0 0 +De 3 0 168 0 0 Po 3 53122 33992 53122 33992 157 -1 -De 15 1 165 0 0 +De 15 1 168 0 0 Po 0 53122 33992 53312 34182 39 -1 -De 15 0 165 0 0 +De 15 0 168 0 0 Po 0 53317 34182 53312 34182 39 -1 -De 15 0 165 0 800 +De 15 0 168 0 800 Po 0 49025 34019 49024 34020 39 -1 -De 0 0 165 0 0 +De 0 0 168 0 0 Po 3 49024 34020 49024 34020 157 -1 -De 15 1 165 0 0 +De 15 1 168 0 0 Po 0 49024 34020 49110 34106 39 -1 -De 3 0 165 0 0 +De 3 0 168 0 0 Po 0 49110 34106 51926 34106 39 -1 -De 3 0 165 0 0 +De 3 0 168 0 0 Po 0 49025 34019 49441 34019 39 -1 -De 0 0 165 0 400 +De 0 0 168 0 400 Po 0 52937 34177 53122 33992 39 -1 -De 3 0 165 0 0 +De 3 0 168 0 0 Po 0 52106 34177 52937 34177 39 -1 -De 3 0 165 0 0 +De 3 0 168 0 0 Po 0 52035 34106 52106 34177 39 -1 -De 3 0 165 0 0 +De 3 0 168 0 0 Po 0 49441 34216 49099 34216 39 -1 -De 0 0 166 0 800 +De 0 0 169 0 800 Po 0 52892 34182 52923 34182 39 -1 -De 15 0 166 0 400 +De 15 0 169 0 400 Po 0 52724 34350 52892 34182 39 -1 -De 15 0 166 0 0 +De 15 0 169 0 0 Po 3 52724 34350 52724 34350 157 -1 -De 15 1 166 0 0 +De 15 1 169 0 0 Po 0 52713 34339 52724 34350 39 -1 -De 3 0 166 0 0 +De 3 0 169 0 0 Po 0 49102 34339 52713 34339 39 -1 -De 3 0 166 0 0 +De 3 0 169 0 0 Po 0 49039 34276 49102 34339 39 -1 -De 3 0 166 0 0 +De 3 0 169 0 0 Po 3 49039 34276 49039 34276 157 -1 -De 15 1 166 0 0 +De 15 1 169 0 0 Po 0 49099 34216 49039 34276 39 -1 -De 0 0 166 0 0 +De 0 0 169 0 0 Po 0 49421 32512 49177 32512 39 -1 -De 0 0 167 0 800 -Po 3 53512 33591 53512 33591 157 -1 -De 15 1 167 0 0 -Po 0 53512 33591 53709 33788 39 -1 -De 15 0 167 0 0 -Po 0 53709 33788 53711 33788 39 -1 -De 15 0 167 0 400 -Po 0 53307 33386 53512 33591 39 -1 -De 0 0 167 0 0 -Po 0 52536 33386 53307 33386 39 -1 -De 0 0 167 0 0 -Po 0 52323 33173 52536 33386 39 -1 -De 0 0 167 0 0 -Po 0 51846 33173 52323 33173 39 -1 -De 0 0 167 0 0 -Po 3 51846 33173 51846 33173 157 -1 -De 15 1 167 0 0 -Po 0 51747 33173 51846 33173 39 -1 -De 3 0 167 0 0 -Po 0 51487 32913 51747 33173 39 -1 -De 3 0 167 0 0 -Po 0 50000 32913 51487 32913 39 -1 -De 3 0 167 0 0 -Po 0 49815 32728 50000 32913 39 -1 -De 3 0 167 0 0 -Po 0 49141 32728 49815 32728 39 -1 -De 3 0 167 0 0 -Po 0 49051 32638 49141 32728 39 -1 -De 3 0 167 0 0 -Po 3 49051 32638 49051 32638 157 -1 -De 15 1 167 0 0 -Po 0 49177 32512 49051 32638 39 -1 -De 0 0 167 0 0 -Po 0 52327 32433 52330 32433 39 -1 -De 0 0 170 0 0 -Po 0 48937 33823 48854 33740 39 -1 -De 0 0 170 0 0 -Po 0 48854 33740 48854 33563 39 -1 -De 0 0 170 0 0 -Po 0 48854 33563 48976 33441 39 -1 -De 0 0 170 0 0 -Po 0 48976 33441 50527 33441 39 -1 -De 0 0 170 0 0 -Po 0 50527 33441 50941 33027 39 -1 -De 0 0 170 0 0 -Po 0 50941 33027 51733 33027 39 -1 -De 0 0 170 0 0 -Po 0 51733 33027 52327 32433 39 -1 -De 0 0 170 0 0 -Po 0 49441 33823 48937 33823 39 -1 De 0 0 170 0 800 -Po 0 52550 32213 52530 32213 39 -1 -De 15 0 170 0 400 -Po 0 52732 32031 52550 32213 39 -1 -De 15 0 170 0 0 -Po 3 52732 32031 52732 32031 157 -1 +Po 3 53512 33591 53512 33591 157 -1 De 15 1 170 0 0 -Po 0 52330 32433 52732 32031 39 -1 -De 0 0 170 0 0 -Po 0 52516 32213 52530 32213 39 -1 +Po 0 53512 33591 53709 33788 39 -1 +De 15 0 170 0 0 +Po 0 53709 33788 53711 33788 39 -1 De 15 0 170 0 400 +Po 0 53307 33386 53512 33591 39 -1 +De 0 0 170 0 0 +Po 0 52536 33386 53307 33386 39 -1 +De 0 0 170 0 0 +Po 0 52323 33173 52536 33386 39 -1 +De 0 0 170 0 0 +Po 0 51846 33173 52323 33173 39 -1 +De 0 0 170 0 0 +Po 3 51846 33173 51846 33173 157 -1 +De 15 1 170 0 0 +Po 0 51747 33173 51846 33173 39 -1 +De 3 0 170 0 0 +Po 0 51487 32913 51747 33173 39 -1 +De 3 0 170 0 0 +Po 0 50000 32913 51487 32913 39 -1 +De 3 0 170 0 0 +Po 0 49815 32728 50000 32913 39 -1 +De 3 0 170 0 0 +Po 0 49141 32728 49815 32728 39 -1 +De 3 0 170 0 0 +Po 0 49051 32638 49141 32728 39 -1 +De 3 0 170 0 0 +Po 3 49051 32638 49051 32638 157 -1 +De 15 1 170 0 0 +Po 0 49177 32512 49051 32638 39 -1 +De 0 0 170 0 0 +Po 0 52327 32433 52330 32433 39 -1 +De 0 0 173 0 0 +Po 0 48937 33823 48854 33740 39 -1 +De 0 0 173 0 0 +Po 0 48854 33740 48854 33563 39 -1 +De 0 0 173 0 0 +Po 0 48854 33563 48976 33441 39 -1 +De 0 0 173 0 0 +Po 0 48976 33441 50527 33441 39 -1 +De 0 0 173 0 0 +Po 0 50527 33441 50941 33027 39 -1 +De 0 0 173 0 0 +Po 0 50941 33027 51733 33027 39 -1 +De 0 0 173 0 0 +Po 0 51733 33027 52327 32433 39 -1 +De 0 0 173 0 0 +Po 0 49441 33823 48937 33823 39 -1 +De 0 0 173 0 800 +Po 0 52550 32213 52530 32213 39 -1 +De 15 0 173 0 400 +Po 0 52732 32031 52550 32213 39 -1 +De 15 0 173 0 0 +Po 3 52732 32031 52732 32031 157 -1 +De 15 1 173 0 0 +Po 0 52330 32433 52732 32031 39 -1 +De 0 0 173 0 0 +Po 0 52516 32213 52530 32213 39 -1 +De 15 0 173 0 400 +Po 0 46643 35157 46870 35157 79 -1 +De 15 0 231 0 800 +Po 3 46870 35157 46870 35157 157 -1 +De 15 1 231 0 0 Po 0 48499 27453 48499 27229 79 -1 -De 0 0 229 0 800 +De 0 0 231 0 800 Po 3 48494 27224 48494 27224 157 -1 -De 15 1 229 0 0 +De 15 1 231 0 0 Po 0 48499 27229 48494 27224 79 -1 -De 0 0 229 0 0 +De 0 0 231 0 0 Po 0 47062 26567 46734 26567 79 -1 -De 15 0 229 0 800 +De 15 0 231 0 800 Po 3 46732 26565 46732 26565 157 -1 -De 15 1 229 0 0 +De 15 1 231 0 0 Po 0 46734 26567 46732 26565 79 -1 -De 15 0 229 0 0 +De 15 0 231 0 0 Po 0 47062 25584 46676 25584 79 -1 -De 15 0 229 0 800 +De 15 0 231 0 800 Po 3 46673 25591 46673 25591 157 -1 -De 15 1 229 0 0 +De 15 1 231 0 0 Po 0 46673 25587 46673 25591 79 -1 -De 15 0 229 0 0 +De 15 0 231 0 0 Po 0 46676 25584 46673 25587 79 -1 -De 15 0 229 0 0 +De 15 0 231 0 0 Po 0 50580 19154 50827 19154 79 -1 -De 0 0 229 0 800 +De 0 0 231 0 800 Po 3 50827 19154 50827 19154 157 -1 -De 15 1 229 0 0 +De 15 1 231 0 0 Po 0 50580 19154 50580 18711 79 -1 -De 0 0 229 0 800 +De 0 0 231 0 800 Po 0 50580 18711 50570 18701 79 -1 -De 0 0 229 0 400 +De 0 0 231 0 400 Po 0 49757 27885 49910 27885 79 -1 -De 15 0 229 0 800 +De 15 0 231 0 800 Po 0 49911 27884 49902 27884 79 -1 -De 0 0 229 0 0 +De 0 0 231 0 0 Po 3 49911 27884 49911 27884 157 -1 -De 15 1 229 0 0 +De 15 1 231 0 0 Po 0 49910 27885 49911 27884 79 -1 -De 15 0 229 0 0 +De 15 0 231 0 0 Po 0 48970 27885 48970 28156 79 -1 -De 15 0 229 0 800 +De 15 0 231 0 800 Po 0 48957 28169 48957 28189 79 -1 -De 0 0 229 0 0 +De 0 0 231 0 0 Po 0 48967 28159 48957 28169 79 -1 -De 0 0 229 0 0 +De 0 0 231 0 0 Po 3 48967 28159 48967 28159 157 -1 -De 15 1 229 0 0 +De 15 1 231 0 0 Po 0 48970 28156 48967 28159 79 -1 -De 15 0 229 0 0 +De 15 0 231 0 0 Po 0 47062 25190 47050 25190 39 -1 De 15 0 233 0 800 Po 0 46743 24883 46654 24883 39 -1 diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 0f24d37..e186d03 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,4 +1,4 @@ -# EESchema Netlist Version 1.1 created Fri 20 Aug 2010 07:49:29 PM COT +# EESchema Netlist Version 1.1 created Sat 21 Aug 2010 06:47:10 AM COT ( ( /4C69ED5F/4C6D2FD7 0805 C82 4.7uF {Lib=CAP} ( 1 N-000434 ) @@ -138,11 +138,11 @@ ( CD ? ) ( 1 /Non_volatile_memories/SD_DAT2 ) ( 2 /FPGA_Spartan6/SD_DAT3 ) - ( 3 /Non_volatile_memories/SD_CMD ) + ( 3 /FPGA_Spartan6/SD_CMD ) ( 4 +3.3V ) - ( 5 /FPGA_Spartan6/SD_CLK ) + ( 5 /Non_volatile_memories/SD_CLK ) ( 6 GND ) - ( 7 /Non_volatile_memories/SD_DAT0 ) + ( 7 /FPGA_Spartan6/SD_DAT0 ) ( 8 /Non_volatile_memories/SD_DAT1 ) ) ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} @@ -153,7 +153,7 @@ ( 5 ? ) ( 6 /FPGA_Spartan6/NF_RNB ) ( 7 /FPGA_Spartan6/NF_RNB ) - ( 8 /FPGA_Spartan6/NF_RE_N ) + ( 8 /Non_volatile_memories/NF_RE_N ) ( 9 /Non_volatile_memories/NF_CS1_N ) ( 10 ? ) ( 11 ? ) @@ -161,9 +161,9 @@ ( 13 GND ) ( 14 ? ) ( 15 ? ) - ( 16 /Non_volatile_memories/NF_CLE ) - ( 17 /Non_volatile_memories/NF_ALE ) - ( 18 /FPGA_Spartan6/NF_WE_N ) + ( 16 /FPGA_Spartan6/NF_CLE ) + ( 17 /FPGA_Spartan6/NF_ALE ) + ( 18 /Non_volatile_memories/NF_WE_N ) ( 19 +3.3V ) ( 20 ? ) ( 21 ? ) @@ -186,10 +186,10 @@ ( 38 ? ) ( 39 ? ) ( 40 ? ) - ( 41 /Non_volatile_memories/NF_D4 ) - ( 42 /FPGA_Spartan6/NF_D5 ) + ( 41 /FPGA_Spartan6/NF_D4 ) + ( 42 /Non_volatile_memories/NF_D5 ) ( 43 /Non_volatile_memories/NF_D6 ) - ( 44 /Non_volatile_memories/NF_D7 ) + ( 44 /FPGA_Spartan6/NF_D7 ) ( 45 ? ) ( 46 ? ) ( 47 ? ) @@ -302,9 +302,9 @@ ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) ( 2 /USB/USBA_SPD ) - ( 3 /FPGA_Spartan6/USBA_RCV ) + ( 3 /USB/USBA_RCV ) ( 4 /USB/USBA_VP ) - ( 5 /USB/USBA_VM ) + ( 5 /FPGA_Spartan6/USBA_VM ) ( 7 GND ) ( 8 GND ) ( 9 /FPGA_Spartan6/USBA_OE_N ) @@ -334,7 +334,7 @@ ( 2 /FPGA_Spartan6/M0_CKE ) ) ( /4C431A63/4C6B1B90 0402 R21 120 {Lib=R} - ( 1 /DDR_Banks/M0_CLK ) + ( 1 /FPGA_Spartan6/M0_CLK ) ( 2 /FPGA_Spartan6/M0_CLK# ) ) ( /4C431A63/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4} @@ -342,8 +342,8 @@ ( 2 /FPGA_Spartan6/R_M0_A1 ) ( 3 /FPGA_Spartan6/R_M0_A2 ) ( 4 /FPGA_Spartan6/R_M0_A3 ) - ( 5 /DDR_Banks/M0_A3 ) - ( 6 /FPGA_Spartan6/M0_A2 ) + ( 5 /FPGA_Spartan6/M0_A3 ) + ( 6 /DDR_Banks/M0_A2 ) ( 7 /FPGA_Spartan6/M0_A1 ) ( 8 /DDR_Banks/M0_A0 ) ) @@ -353,9 +353,9 @@ ( 3 /FPGA_Spartan6/R_M0_BA1 ) ( 4 /FPGA_Spartan6/R_M0_A10 ) ( 5 /FPGA_Spartan6/M0_A10 ) - ( 6 /FPGA_Spartan6/M0_BA1 ) + ( 6 /DDR_Banks/M0_BA1 ) ( 7 /DDR_Banks/M0_BA0 ) - ( 8 /DDR_Banks/M0_RAS# ) + ( 8 /FPGA_Spartan6/M0_RAS# ) ) ( /4C431A63/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_LDQS ) @@ -364,8 +364,8 @@ ( 4 /FPGA_Spartan6/R_M0_CAS# ) ( 5 /DDR_Banks/M0_CAS# ) ( 6 /DDR_Banks/M0_WE# ) - ( 7 /FPGA_Spartan6/M0_LDM ) - ( 8 /FPGA_Spartan6/M0_LDQS ) + ( 7 /DDR_Banks/M0_LDM ) + ( 8 /DDR_Banks/M0_LDQS ) ) ( /4C431A63/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_A7 ) @@ -374,16 +374,16 @@ ( 4 /FPGA_Spartan6/R_M0_A4 ) ( 5 /FPGA_Spartan6/M0_A4 ) ( 6 /DDR_Banks/M0_A5 ) - ( 7 /FPGA_Spartan6/M0_A6 ) - ( 8 /FPGA_Spartan6/M0_A7 ) + ( 7 /DDR_Banks/M0_A6 ) + ( 8 /DDR_Banks/M0_A7 ) ) ( /4C431A63/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_A12 ) ( 2 /FPGA_Spartan6/R_M0_A11 ) ( 3 /FPGA_Spartan6/R_M0_A9 ) ( 4 /FPGA_Spartan6/R_M0_A8 ) - ( 5 /DDR_Banks/M0_A8 ) - ( 6 /FPGA_Spartan6/M0_A9 ) + ( 5 /FPGA_Spartan6/M0_A8 ) + ( 6 /DDR_Banks/M0_A9 ) ( 7 /FPGA_Spartan6/M0_A11 ) ( 8 /FPGA_Spartan6/M0_A12 ) ) @@ -394,7 +394,7 @@ ( 4 /FPGA_Spartan6/R_M0_DQ7 ) ( 5 /FPGA_Spartan6/M0_DQ7 ) ( 6 /FPGA_Spartan6/M0_DQ6 ) - ( 7 /FPGA_Spartan6/M0_DQ5 ) + ( 7 /DDR_Banks/M0_DQ5 ) ( 8 /DDR_Banks/M0_DQ4 ) ) ( /4C431A63/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4} @@ -402,7 +402,7 @@ ( 2 /FPGA_Spartan6/R_M0_DQ1 ) ( 3 /FPGA_Spartan6/R_M0_DQ2 ) ( 4 /FPGA_Spartan6/R_M0_DQ3 ) - ( 5 /DDR_Banks/M0_DQ3 ) + ( 5 /FPGA_Spartan6/M0_DQ3 ) ( 6 /DDR_Banks/M0_DQ2 ) ( 7 /FPGA_Spartan6/M0_DQ1 ) ( 8 /FPGA_Spartan6/M0_DQ0 ) @@ -415,21 +415,21 @@ ( 5 /FPGA_Spartan6/M0_DQ11 ) ( 6 /FPGA_Spartan6/M0_DQ10 ) ( 7 /FPGA_Spartan6/M0_DQ9 ) - ( 8 /DDR_Banks/M0_DQ8 ) + ( 8 /FPGA_Spartan6/M0_DQ8 ) ) ( /4C431A63/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_DQ12 ) ( 2 /FPGA_Spartan6/R_M0_DQ13 ) ( 3 /FPGA_Spartan6/R_M0_DQ14 ) ( 4 /FPGA_Spartan6/R_M0_DQ15 ) - ( 5 /DDR_Banks/M0_DQ15 ) + ( 5 /FPGA_Spartan6/M0_DQ15 ) ( 6 /FPGA_Spartan6/M0_DQ14 ) ( 7 /FPGA_Spartan6/M0_DQ13 ) ( 8 /FPGA_Spartan6/M0_DQ12 ) ) ( /4C431A63/4C69E7DD 0402 R19 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_UDQS ) - ( 2 /FPGA_Spartan6/M1_UDQS ) + ( 2 /DDR_Banks/M1_UDQS ) ) ( /4C431A63/4C69E92D 0402 R20 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CS# ) @@ -437,11 +437,11 @@ ) ( /4C431A63/4C69E7F8 0402 R17 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CKE ) - ( 2 /DDR_Banks/M1_CKE ) + ( 2 /FPGA_Spartan6/M1_CKE ) ) ( /4C431A63/4C69E7C2 0402 R18 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_UDM ) - ( 2 /FPGA_Spartan6/M1_UDM ) + ( 2 /DDR_Banks/M1_UDM ) ) ( /4C431A63/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ11 ) @@ -451,21 +451,21 @@ ( 5 /FPGA_Spartan6/M1_DQ8 ) ( 6 /FPGA_Spartan6/M1_DQ9 ) ( 7 /FPGA_Spartan6/M1_DQ10 ) - ( 8 /FPGA_Spartan6/M1_DQ11 ) + ( 8 /DDR_Banks/M1_DQ11 ) ) ( /4C431A63/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ15 ) ( 2 /FPGA_Spartan6/R_M1_DQ14 ) ( 3 /FPGA_Spartan6/R_M1_DQ13 ) ( 4 /FPGA_Spartan6/R_M1_DQ12 ) - ( 5 /FPGA_Spartan6/M1_DQ12 ) - ( 6 /DDR_Banks/M1_DQ13 ) - ( 7 /DDR_Banks/M1_DQ14 ) - ( 8 /FPGA_Spartan6/M1_DQ15 ) + ( 5 /DDR_Banks/M1_DQ12 ) + ( 6 /FPGA_Spartan6/M1_DQ13 ) + ( 7 /FPGA_Spartan6/M1_DQ14 ) + ( 8 /DDR_Banks/M1_DQ15 ) ) ( /4C431A63/4C69DF7A 0402 R16 120 {Lib=R} - ( 1 /FPGA_Spartan6/M1_CLK# ) - ( 2 /FPGA_Spartan6/M1_CLK ) + ( 1 /DDR_Banks/M1_CLK# ) + ( 2 /DDR_Banks/M1_CLK ) ) ( /4C431A63/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A12 ) @@ -475,17 +475,17 @@ ( 5 /DDR_Banks/M1_A8 ) ( 6 /FPGA_Spartan6/M1_A9 ) ( 7 /DDR_Banks/M1_A11 ) - ( 8 /DDR_Banks/M1_A12 ) + ( 8 /FPGA_Spartan6/M1_A12 ) ) ( /4C431A63/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A7 ) ( 2 /FPGA_Spartan6/R_M1_A6 ) ( 3 /FPGA_Spartan6/R_M1_A5 ) ( 4 ? ) - ( 5 /DDR_Banks/M1_A4 ) - ( 6 /DDR_Banks/M1_A5 ) - ( 7 /DDR_Banks/M1_A6 ) - ( 8 /FPGA_Spartan6/M1_A7 ) + ( 5 /FPGA_Spartan6/M1_A4 ) + ( 6 /FPGA_Spartan6/M1_A5 ) + ( 7 /FPGA_Spartan6/M1_A6 ) + ( 8 /DDR_Banks/M1_A7 ) ) ( /4C431A63/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ0 ) @@ -493,9 +493,9 @@ ( 3 /FPGA_Spartan6/R_M1_DQ2 ) ( 4 /FPGA_Spartan6/R_M1_DQ3 ) ( 5 /FPGA_Spartan6/M1_DQ3 ) - ( 6 /DDR_Banks/M1_DQ2 ) + ( 6 /FPGA_Spartan6/M1_DQ2 ) ( 7 /DDR_Banks/M1_DQ1 ) - ( 8 /DDR_Banks/M1_DQ0 ) + ( 8 /FPGA_Spartan6/M1_DQ0 ) ) ( /4C431A63/4C69D3A4 $noname RP3 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_LDQS ) @@ -504,7 +504,7 @@ ( 4 /FPGA_Spartan6/R_M1_CAS# ) ( 5 /FPGA_Spartan6/M1_CAS# ) ( 6 /DDR_Banks/M1_WE# ) - ( 7 /DDR_Banks/M1_LDM ) + ( 7 /FPGA_Spartan6/M1_LDM ) ( 8 /FPGA_Spartan6/M1_LDQS ) ) ( /4C431A63/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4} @@ -514,7 +514,7 @@ ( 4 /FPGA_Spartan6/R_M1_DQ7 ) ( 5 /FPGA_Spartan6/M1_DQ7 ) ( 6 /DDR_Banks/M1_DQ6 ) - ( 7 /DDR_Banks/M1_DQ5 ) + ( 7 /FPGA_Spartan6/M1_DQ5 ) ( 8 /DDR_Banks/M1_DQ4 ) ) ( /4C431A63/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4} @@ -524,8 +524,8 @@ ( 4 /FPGA_Spartan6/R_M1_A10 ) ( 5 /FPGA_Spartan6/M1_A10 ) ( 6 /DDR_Banks/M1_BA1 ) - ( 7 /DDR_Banks/M1_BA0 ) - ( 8 /DDR_Banks/M1_RAS# ) + ( 7 /FPGA_Spartan6/M1_BA0 ) + ( 8 /FPGA_Spartan6/M1_RAS# ) ) ( /4C431A63/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A0 ) @@ -535,7 +535,7 @@ ( 5 /FPGA_Spartan6/M1_A3 ) ( 6 /FPGA_Spartan6/M1_A2 ) ( 7 /FPGA_Spartan6/M1_A1 ) - ( 8 /FPGA_Spartan6/M1_A0 ) + ( 8 /DDR_Banks/M1_A0 ) ) ( /4C431A63/4C656D9D $noname C66 470nF {Lib=C} ( 1 +2.5V ) @@ -711,7 +711,7 @@ ( L20 /FPGA_Spartan6/R_M1_LDQS ) ( K20 /FPGA_Spartan6/R_M1_A5 ) ( J20 /FPGA_Spartan6/R_M1_DQ4 ) - ( H20 /FPGA_Spartan6/M1_CLK ) + ( H20 /DDR_Banks/M1_CLK ) ( G20 /FPGA_Spartan6/R_M1_A3 ) ( F20 ? ) ( E20 /FPGA_Spartan6/R_M1_A7 ) @@ -760,7 +760,7 @@ ( L4 /FPGA_Spartan6/R_M0_LDM ) ( K4 /FPGA_Spartan6/R_M0_CAS# ) ( J4 /FPGA_Spartan6/R_M0_A6 ) - ( H4 /DDR_Banks/M0_CLK ) + ( H4 /FPGA_Spartan6/M0_CLK ) ( G4 /FPGA_Spartan6/R_M0_A10 ) ( F4 +2.5V ) ( E4 ? ) @@ -785,18 +785,18 @@ ( B3 ? ) ( G10 +3.3V ) ( D10 /Ethernet_Phy/ETH_TXD1 ) - ( C10 /FPGA_Spartan6/ETH_CRS ) + ( C10 /Ethernet_Phy/ETH_CRS ) ( B10 /Ethernet_Phy/ETH_COL ) ( A10 /Ethernet_Phy/ETH_INT ) ( E9 +3.3V ) ( D9 /FPGA_Spartan6/ETH_TXEN ) ( C9 /Ethernet_Phy/ETH_TXD2 ) - ( A9 /FPGA_Spartan6/ETH_TXD0 ) - ( D8 /Ethernet_Phy/ETH_TXER ) - ( C8 /Ethernet_Phy/ETH_TXC ) - ( B8 /FPGA_Spartan6/ETH_RXER ) - ( A8 /Ethernet_Phy/ETH_TXD3 ) - ( D7 /Ethernet_Phy/ETH_MDC ) + ( A9 /Ethernet_Phy/ETH_TXD0 ) + ( D8 /FPGA_Spartan6/ETH_TXER ) + ( C8 /FPGA_Spartan6/ETH_TXC ) + ( B8 /Ethernet_Phy/ETH_RXER ) + ( A8 /FPGA_Spartan6/ETH_TXD3 ) + ( D7 /FPGA_Spartan6/ETH_MDC ) ( C7 /FPGA_Spartan6/ETH_RESET_N ) ( B7 +3.3V ) ( A7 /Ethernet_Phy/ETH_RXC ) @@ -805,9 +805,9 @@ ( B6 /Ethernet_Phy/ETH_RXD0 ) ( A6 /Ethernet_Phy/ETH_RXDV ) ( C5 /Ethernet_Phy/ETH_RXD3 ) - ( A5 /Ethernet_Phy/ETH_RXD1 ) + ( A5 /FPGA_Spartan6/ETH_RXD1 ) ( B4 +3.3V ) - ( A4 /FPGA_Spartan6/ETH_CLK ) + ( A4 /Ethernet_Phy/ETH_CLK ) ( A3 ? ) ( U19 ? ) ( T19 ? ) @@ -815,19 +815,19 @@ ( P19 ? ) ( B19 +3.3V ) ( B18 /Non_volatile_memories/SD_DAT1 ) - ( A18 /Non_volatile_memories/SD_DAT0 ) + ( A18 /FPGA_Spartan6/SD_DAT0 ) ( E17 +3.3V ) - ( D17 /Non_volatile_memories/SD_CMD ) + ( D17 /FPGA_Spartan6/SD_CMD ) ( C17 /FPGA_Spartan6/SD_DAT3 ) ( A17 /Non_volatile_memories/SD_DAT2 ) - ( E16 /FPGA_Spartan6/SD_CLK ) + ( E16 /Non_volatile_memories/SD_CLK ) ( C16 /Non_volatile_memories/NF_CS1_N ) - ( B16 /FPGA_Spartan6/NF_RE_N ) + ( B16 /Non_volatile_memories/NF_RE_N ) ( A16 /FPGA_Spartan6/NF_RNB ) - ( D15 /Non_volatile_memories/NF_CLE ) - ( C15 /FPGA_Spartan6/NF_WE_N ) + ( D15 /FPGA_Spartan6/NF_CLE ) + ( C15 /Non_volatile_memories/NF_WE_N ) ( B15 +3.3V ) - ( A15 /Non_volatile_memories/NF_ALE ) + ( A15 /FPGA_Spartan6/NF_ALE ) ( G14 +3.3V ) ( D14 /Non_volatile_memories/NF_D0 ) ( C14 ? ) @@ -836,13 +836,13 @@ ( E13 +3.3V ) ( C13 /FPGA_Spartan6/NF_D2 ) ( A13 /Non_volatile_memories/NF_D1 ) - ( C12 /FPGA_Spartan6/NF_D5 ) - ( B12 /Non_volatile_memories/NF_D4 ) + ( C12 /Non_volatile_memories/NF_D5 ) + ( B12 /FPGA_Spartan6/NF_D4 ) ( A12 /FPGA_Spartan6/NF_D3 ) ( D11 /Non_volatile_memories/NF_D6 ) ( C11 ? ) ( B11 +3.3V ) - ( A11 /Non_volatile_memories/NF_D7 ) + ( A11 /FPGA_Spartan6/NF_D7 ) ( J16 ? ) ( H16 /FPGA_Spartan6/R_M1_CS# ) ( G16 ? ) @@ -877,7 +877,7 @@ ( M19 ? ) ( L19 /FPGA_Spartan6/R_M1_LDM ) ( K19 /FPGA_Spartan6/R_M1_A6 ) - ( J19 /FPGA_Spartan6/M1_CLK# ) + ( J19 /DDR_Banks/M1_CLK# ) ( H19 /FPGA_Spartan6/R_M1_WE# ) ( G19 /FPGA_Spartan6/R_M1_A10 ) ( F19 /FPGA_Spartan6/R_M1_A11 ) @@ -887,7 +887,7 @@ ( U18 +2.5V ) ( P18 /FPGA_Spartan6/USBA_OE_N ) ( N18 +2.5V ) - ( M18 /USB/USBA_VM ) + ( M18 /FPGA_Spartan6/USBA_VM ) ( K18 ? ) ( J18 +2.5V ) ( H18 ? ) @@ -900,7 +900,7 @@ ( H17 ? ) ( G17 ? ) ( F17 ? ) - ( N16 /FPGA_Spartan6/USBA_RCV ) + ( N16 /USB/USBA_RCV ) ( M16 ? ) ( L16 +2.5V ) ( K16 ? ) @@ -1221,27 +1221,27 @@ ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} ( 1 /FPGA_Spartan6/ETH_MDIO ) - ( 2 /Ethernet_Phy/ETH_MDC ) + ( 2 /FPGA_Spartan6/ETH_MDC ) ( 3 /Ethernet_Phy/ETH_RXD3 ) ( 4 /FPGA_Spartan6/ETH_RXD2 ) - ( 5 /Ethernet_Phy/ETH_RXD1 ) + ( 5 /FPGA_Spartan6/ETH_RXD1 ) ( 6 /Ethernet_Phy/ETH_RXD0 ) ( 7 +3.3V ) ( 8 GND ) ( 9 /Ethernet_Phy/ETH_RXDV ) ( 10 /Ethernet_Phy/ETH_RXC ) - ( 11 /FPGA_Spartan6/ETH_RXER ) + ( 11 /Ethernet_Phy/ETH_RXER ) ( 12 GND ) ( 13 +1.8V ) - ( 14 /Ethernet_Phy/ETH_TXER ) - ( 15 /Ethernet_Phy/ETH_TXC ) + ( 14 /FPGA_Spartan6/ETH_TXER ) + ( 15 /FPGA_Spartan6/ETH_TXC ) ( 16 /FPGA_Spartan6/ETH_TXEN ) - ( 17 /FPGA_Spartan6/ETH_TXD0 ) + ( 17 /Ethernet_Phy/ETH_TXD0 ) ( 18 /Ethernet_Phy/ETH_TXD1 ) ( 19 /Ethernet_Phy/ETH_TXD2 ) - ( 20 /Ethernet_Phy/ETH_TXD3 ) + ( 20 /FPGA_Spartan6/ETH_TXD3 ) ( 21 /Ethernet_Phy/ETH_COL ) - ( 22 /FPGA_Spartan6/ETH_CRS ) + ( 22 /Ethernet_Phy/ETH_CRS ) ( 23 GND ) ( 24 +3.3V ) ( 25 /Ethernet_Phy/ETH_INT ) @@ -1265,7 +1265,7 @@ ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 /FPGA_Spartan6/ETH_CLK ) + ( 46 /Ethernet_Phy/ETH_CLK ) ( 47 /Ethernet_Phy/ETH_PLL1.8V ) ( 48 /FPGA_Spartan6/ETH_RESET_N ) ) @@ -1311,15 +1311,15 @@ ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /DDR_Banks/M1_DQ0 ) + ( 2 /FPGA_Spartan6/M1_DQ0 ) ( 3 +2.5V ) ( 4 /DDR_Banks/M1_DQ1 ) - ( 5 /DDR_Banks/M1_DQ2 ) + ( 5 /FPGA_Spartan6/M1_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M1_DQ3 ) ( 8 /DDR_Banks/M1_DQ4 ) ( 9 +2.5V ) - ( 10 /DDR_Banks/M1_DQ5 ) + ( 10 /FPGA_Spartan6/M1_DQ5 ) ( 11 /DDR_Banks/M1_DQ6 ) ( 12 GND ) ( 13 /FPGA_Spartan6/M1_DQ7 ) @@ -1329,38 +1329,38 @@ ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /DDR_Banks/M1_LDM ) + ( 20 /FPGA_Spartan6/M1_LDM ) ( 21 /DDR_Banks/M1_WE# ) ( 22 /FPGA_Spartan6/M1_CAS# ) - ( 23 /DDR_Banks/M1_RAS# ) + ( 23 /FPGA_Spartan6/M1_RAS# ) ( 24 /DDR_Banks/M1_CS# ) ( 25 ? ) - ( 26 /DDR_Banks/M1_BA0 ) + ( 26 /FPGA_Spartan6/M1_BA0 ) ( 27 /DDR_Banks/M1_BA1 ) ( 28 /FPGA_Spartan6/M1_A10 ) - ( 29 /FPGA_Spartan6/M1_A0 ) + ( 29 /DDR_Banks/M1_A0 ) ( 30 /FPGA_Spartan6/M1_A1 ) ( 31 /FPGA_Spartan6/M1_A2 ) ( 32 /FPGA_Spartan6/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /DDR_Banks/M1_A4 ) - ( 36 /DDR_Banks/M1_A5 ) - ( 37 /DDR_Banks/M1_A6 ) - ( 38 /FPGA_Spartan6/M1_A7 ) + ( 35 /FPGA_Spartan6/M1_A4 ) + ( 36 /FPGA_Spartan6/M1_A5 ) + ( 37 /FPGA_Spartan6/M1_A6 ) + ( 38 /DDR_Banks/M1_A7 ) ( 39 /DDR_Banks/M1_A8 ) ( 40 /FPGA_Spartan6/M1_A9 ) ( 41 /DDR_Banks/M1_A11 ) - ( 42 /DDR_Banks/M1_A12 ) + ( 42 /FPGA_Spartan6/M1_A12 ) ( 43 ? ) - ( 44 /FPGA_Spartan6/M1_CLK# ) - ( 45 /DDR_Banks/M1_CKE ) - ( 46 /FPGA_Spartan6/M1_CLK ) - ( 47 /FPGA_Spartan6/M1_UDM ) + ( 44 /DDR_Banks/M1_CLK# ) + ( 45 /FPGA_Spartan6/M1_CKE ) + ( 46 /DDR_Banks/M1_CLK ) + ( 47 /DDR_Banks/M1_UDM ) ( 48 GND ) - ( 49 N-000058 ) + ( 49 /DDR_Banks/M1_VREF ) ( 50 ? ) - ( 51 /FPGA_Spartan6/M1_UDQS ) + ( 51 /DDR_Banks/M1_UDQS ) ( 52 GND ) ( 53 ? ) ( 54 /FPGA_Spartan6/M1_DQ8 ) @@ -1368,13 +1368,13 @@ ( 56 /FPGA_Spartan6/M1_DQ9 ) ( 57 /FPGA_Spartan6/M1_DQ10 ) ( 58 GND ) - ( 59 /FPGA_Spartan6/M1_DQ11 ) - ( 60 /FPGA_Spartan6/M1_DQ12 ) + ( 59 /DDR_Banks/M1_DQ11 ) + ( 60 /DDR_Banks/M1_DQ12 ) ( 61 +2.5V ) - ( 62 /DDR_Banks/M1_DQ13 ) - ( 63 /DDR_Banks/M1_DQ14 ) + ( 62 /FPGA_Spartan6/M1_DQ13 ) + ( 63 /FPGA_Spartan6/M1_DQ14 ) ( 64 GND ) - ( 65 /FPGA_Spartan6/M1_DQ15 ) + ( 65 /DDR_Banks/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} @@ -1443,35 +1443,35 @@ ) ( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R} ( 1 +2.5V ) - ( 2 N-000058 ) + ( 2 /DDR_Banks/M1_VREF ) ) ( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R} - ( 1 N-000058 ) + ( 1 /DDR_Banks/M1_VREF ) ( 2 GND ) ) ( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R} - ( 1 N-000059 ) + ( 1 /DDR_Banks/M0_VREF ) ( 2 GND ) ) ( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R} ( 1 +2.5V ) - ( 2 N-000059 ) + ( 2 /DDR_Banks/M0_VREF ) ) ( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP} ( 1 +2.5V ) - ( 2 N-000058 ) + ( 2 /DDR_Banks/M1_VREF ) ) ( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP} - ( 1 N-000058 ) + ( 1 /DDR_Banks/M1_VREF ) ( 2 GND ) ) ( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP} - ( 1 N-000059 ) + ( 1 /DDR_Banks/M0_VREF ) ( 2 GND ) ) ( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP} ( 1 +2.5V ) - ( 2 N-000059 ) + ( 2 /DDR_Banks/M0_VREF ) ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) @@ -1480,54 +1480,54 @@ ( 4 /FPGA_Spartan6/M0_DQ1 ) ( 5 /DDR_Banks/M0_DQ2 ) ( 6 GND ) - ( 7 /DDR_Banks/M0_DQ3 ) + ( 7 /FPGA_Spartan6/M0_DQ3 ) ( 8 /DDR_Banks/M0_DQ4 ) ( 9 +2.5V ) - ( 10 /FPGA_Spartan6/M0_DQ5 ) + ( 10 /DDR_Banks/M0_DQ5 ) ( 11 /FPGA_Spartan6/M0_DQ6 ) ( 12 GND ) ( 13 /FPGA_Spartan6/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /FPGA_Spartan6/M0_LDQS ) + ( 16 /DDR_Banks/M0_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Spartan6/M0_LDM ) + ( 20 /DDR_Banks/M0_LDM ) ( 21 /DDR_Banks/M0_WE# ) ( 22 /DDR_Banks/M0_CAS# ) - ( 23 /DDR_Banks/M0_RAS# ) + ( 23 /FPGA_Spartan6/M0_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /DDR_Banks/M0_BA0 ) - ( 27 /FPGA_Spartan6/M0_BA1 ) + ( 27 /DDR_Banks/M0_BA1 ) ( 28 /FPGA_Spartan6/M0_A10 ) ( 29 /DDR_Banks/M0_A0 ) ( 30 /FPGA_Spartan6/M0_A1 ) - ( 31 /FPGA_Spartan6/M0_A2 ) - ( 32 /DDR_Banks/M0_A3 ) + ( 31 /DDR_Banks/M0_A2 ) + ( 32 /FPGA_Spartan6/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M0_A4 ) ( 36 /DDR_Banks/M0_A5 ) - ( 37 /FPGA_Spartan6/M0_A6 ) - ( 38 /FPGA_Spartan6/M0_A7 ) - ( 39 /DDR_Banks/M0_A8 ) - ( 40 /FPGA_Spartan6/M0_A9 ) + ( 37 /DDR_Banks/M0_A6 ) + ( 38 /DDR_Banks/M0_A7 ) + ( 39 /FPGA_Spartan6/M0_A8 ) + ( 40 /DDR_Banks/M0_A9 ) ( 41 /FPGA_Spartan6/M0_A11 ) ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) ( 44 /FPGA_Spartan6/M0_CLK# ) ( 45 /FPGA_Spartan6/M0_CKE ) - ( 46 /DDR_Banks/M0_CLK ) + ( 46 /FPGA_Spartan6/M0_CLK ) ( 47 /FPGA_Spartan6/M0_UDM ) ( 48 GND ) - ( 49 N-000059 ) + ( 49 /DDR_Banks/M0_VREF ) ( 50 ? ) ( 51 /FPGA_Spartan6/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M0_DQ8 ) + ( 54 /FPGA_Spartan6/M0_DQ8 ) ( 55 +2.5V ) ( 56 /FPGA_Spartan6/M0_DQ9 ) ( 57 /FPGA_Spartan6/M0_DQ10 ) @@ -1538,7 +1538,7 @@ ( 62 /FPGA_Spartan6/M0_DQ13 ) ( 63 /FPGA_Spartan6/M0_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M0_DQ15 ) + ( 65 /FPGA_Spartan6/M0_DQ15 ) ( 66 GND ) ) ) @@ -2141,315 +2141,315 @@ $endfootprintlist } { Pin List by Nets Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" - U1 T5 U8 1 -Net 2 "/FPGA Spartan6/NF_RE_N" "NF_RE_N" + U1 T5 +Net 2 "/Non volatile memories/NF_RE_N" "NF_RE_N" U1 B16 U5 8 Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" U1 C16 U5 9 -Net 4 "/Non volatile memories/NF_ALE" "NF_ALE" - U1 A15 +Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE" U5 17 -Net 5 "/Ethernet Phy/ETH_TXC" "ETH_TXC" - U4 15 + U1 A15 +Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" U1 C8 + U4 15 Net 6 "/Ethernet Phy/ETH_RXC" "ETH_RXC" U4 10 U1 A7 -Net 7 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" - U1 A4 +Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK" U4 46 + U1 A4 Net 8 "/USB/USBA_SPD" "USBA_SPD" U6 2 U1 R19 Net 9 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" U6 9 U1 P18 -Net 10 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" - U6 3 +Net 10 "/USB/USBA_RCV" "USBA_RCV" U1 N16 + U6 3 Net 11 "/USB/USBA_VP" "USBA_VP" - U6 4 U1 P17 -Net 12 "/USB/USBA_VM" "USBA_VM" + U6 4 +Net 12 "/FPGA Spartan6/USBA_VM" "USBA_VM" U6 5 U1 M18 Net 13 "/Ethernet Phy/ETH_COL" "ETH_COL" - U1 B10 U4 21 -Net 14 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" + U1 B10 +Net 14 "/Ethernet Phy/ETH_CRS" "ETH_CRS" U1 C10 U4 22 -Net 15 "/FPGA Spartan6/SD_CLK" "SD_CLK" +Net 15 "/Non volatile memories/SD_CLK" "SD_CLK" J1 5 U1 E16 Net 16 "/Ethernet Phy/ETH_INT" "ETH_INT" U1 A10 U4 25 -Net 17 "/Ethernet Phy/ETH_MDC" "ETH_MDC" - U4 2 +Net 17 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" U1 D7 + U4 2 Net 18 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" + U4 1 U1 D6 R1 1 - U4 1 Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" U1 C7 U4 48 Net 20 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" - U4 9 U1 A6 -Net 21 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" - U1 B8 + U4 9 +Net 21 "/Ethernet Phy/ETH_RXER" "ETH_RXER" U4 11 -Net 22 "/Ethernet Phy/ETH_TXER" "ETH_TXER" + U1 B8 +Net 22 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" U1 D8 U4 14 Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" U1 D9 U4 16 Net 24 "/DDR Banks/M1_CS#" "M1_CS#" - R20 2 U3 24 -Net 25 "/FPGA Spartan6/M1_UDM" "M1_UDM" + R20 2 +Net 25 "/DDR Banks/M1_UDM" "M1_UDM" R18 2 U3 47 Net 26 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" - RP3 8 U3 16 -Net 27 "/DDR Banks/M1_LDM" "M1_LDM" - RP3 7 + RP3 8 +Net 27 "/FPGA Spartan6/M1_LDM" "M1_LDM" U3 20 -Net 28 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" + RP3 7 +Net 28 "/DDR Banks/M1_UDQS" "M1_UDQS" U3 51 R19 2 Net 29 "/FPGA Spartan6/M0_UDQS" "M0_UDQS" - U2 51 R22 2 -Net 30 "/FPGA Spartan6/M0_LDM" "M0_LDM" + U2 51 +Net 30 "/DDR Banks/M0_LDM" "M0_LDM" U2 20 RP16 7 Net 31 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" RP3 5 U3 22 -Net 32 "/DDR Banks/M1_CKE" "M1_CKE" +Net 32 "/FPGA Spartan6/M1_CKE" "M1_CKE" U3 45 R17 2 -Net 33 "/FPGA Spartan6/M1_CLK" "M1_CLK" +Net 33 "/DDR Banks/M1_CLK" "M1_CLK" R16 2 - U3 46 U1 H20 -Net 34 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" - U1 J19 - R16 1 + U3 46 +Net 34 "/DDR Banks/M1_CLK#" "M1_CLK#" U3 44 + R16 1 + U1 J19 Net 35 "GND" "GND" - U1 L13 - U1 J13 - U4 8 - U1 E21 - U1 N21 - U1 K14 - R9 2 - C5 2 - C7 2 - C8 2 - C3 2 - U1 V14 - C34 2 - U1 E15 - C71 2 - U1 J21 - U1 P14 - U1 M14 - U1 N13 - U1 B13 - C27 2 - U1 A22 - U1 N9 - C32 2 - U1 K10 - U1 J9 - U1 B9 - U1 L9 - U1 U21 - U1 G18 - C22 2 - U1 L18 - C23 2 - U1 R18 - C25 2 - U1 W19 - C24 2 - U1 AA9 - C26 2 - U1 AB22 - C21 2 - U1 AA13 - U1 AA17 - C1 2 - C30 2 - U1 M10 - C31 2 - U1 P12 - U1 M12 - U1 K12 - U1 P10 - C29 2 - U1 V10 - C28 2 - U1 AB1 - U1 E11 - U1 W16 - U1 B17 - U1 N17 - U1 D18 - C33 2 - U5 36 - J1 CASE - J1 COM - J1 6 - C77 2 - C73 2 - C74 2 - C75 1 - U5 13 - U1 A1 - U1 E2 - U1 J2 - U1 N2 - U1 U2 - U1 D4 - U1 V4 - U1 B5 - U1 G5 - U1 L5 - U1 R5 - U1 E7 - U1 H7 - U1 U7 - U1 W7 C76 2 J1 CASE J1 CASE - U2 64 - C18 2 - C20 2 - R12 2 - R14 2 + U3 58 + C34 2 + C71 2 C70 2 - U1 J15 - U1 AA5 U2 34 U2 24 U2 52 U2 12 U2 66 + U2 64 + C18 2 + C20 2 + R12 2 + R14 2 + C22 2 + C32 2 + C30 2 + C31 2 + C29 2 + C28 2 + C33 2 + C23 2 + C25 2 + C24 2 + C26 2 + C21 2 + C27 2 C72 2 + C73 2 + C74 2 + C75 1 + U5 13 + U5 36 + J1 CASE + J1 COM + J1 6 U2 6 U8 4 - C16 2 - V1 2 - V2 2 - L7 2 - U3 52 - U3 58 - U3 48 - L5 2 - U3 66 - C15 2 - C14 2 - C13 2 - U6 7 - U6 8 - U3 64 - U3 34 - C81 2 - U9 8 - U9 PAD - U11 2 - U10 2 - U10 5 - U10 PAD - R25 2 - C80 2 - C78 2 - U12 2 - R27 2 - C85 2 - C82 2 - C84 2 - R15 2 - C38 2 - V3 2 - V4 2 - C37 2 - C36 2 - C64 2 - C35 2 - C61 2 - C58 2 - C55 2 C68 2 - J4 5 - J4 4 - U1 J11 - U4 36 - U4 35 - U4 44 - C54 2 - C69 2 + C55 2 + C58 2 + C61 2 + C64 2 C67 2 - C40 2 + C69 2 + C54 2 + C57 2 + C60 2 + C63 2 C43 2 - U4 23 - U4 39 - U4 12 + C52 2 + C46 2 + C49 2 + C51 2 + C53 2 + C41 2 + C44 2 + C47 2 + U10 5 + U10 2 C39 2 C42 2 C45 2 + U11 2 C48 2 - C50 2 - U3 6 - C47 2 - C44 2 - C41 2 - C12 2 - U2 48 - U2 58 - U1 N11 - C10 2 + C40 2 + U9 PAD + U9 8 + C81 2 C65 2 - C62 2 - U1 L11 - U3 12 - C59 2 - R10 2 + C80 2 + R25 2 + C50 2 C56 2 - C11 2 - R2 2 - U7 8 - U7 7 + C59 2 + C62 2 + C85 2 + R27 2 + U12 2 + C78 2 C66 2 - C63 2 - C2 2 - C60 2 - C57 2 - C4 2 - C6 2 + U1 W16 + U1 AA5 + U1 J15 + U1 E15 + U1 V14 + U1 P14 + U1 M14 + U1 K14 + U1 N13 + U1 L13 + C77 2 + U1 W7 + U1 U7 + U1 H7 + U1 E7 + U1 R5 + U1 L5 + U1 G5 + U1 B5 + U1 V4 + U1 D4 + U1 U2 + U1 N2 + U1 J2 + U1 E2 + U1 A1 + U1 B9 + U1 B13 + U1 A22 + U1 P12 + U1 M12 + U1 K12 + U10 PAD + U1 AB1 + U1 U21 + U1 N21 + U1 J21 + U1 E21 + U1 N11 + U1 L11 + U1 J13 + U1 AA17 + U1 AA13 + U1 AB22 + U1 AA9 + U1 W19 + U1 R18 + U1 L18 + U1 G18 + U1 D18 + U1 N17 + U1 B17 + U1 J11 + U1 E11 + U1 V10 + U1 P10 + U1 M10 + U1 K10 + U1 N9 + U1 L9 + U1 J9 + U3 12 + L5 2 + U3 52 + J4 4 + J4 5 + U3 34 + L7 2 + U3 64 + U7 8 + U4 35 + U4 36 + C16 2 + R10 2 + U3 66 + U3 48 + C13 2 + C14 2 + C10 2 C9 2 - C53 2 - C52 2 - C51 2 - C49 2 - C46 2 + C6 2 + C4 2 + C2 2 + U6 8 + U6 7 + C35 2 + C36 2 + C37 2 + V4 2 + V3 2 + C38 2 + R15 2 + U4 12 + U4 39 + U3 6 + U7 7 + U4 23 + U4 44 + C82 2 + R2 2 + C11 2 + C15 2 + V2 2 + V1 2 + U4 8 + C8 2 + C7 2 + U2 58 + U2 48 + C12 2 + R9 2 + C84 2 + C5 2 + C3 2 + C1 2 Net 36 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" U1 H3 - U2 44 R21 2 -Net 37 "/DDR Banks/M0_CLK" "M0_CLK" + U2 44 +Net 37 "/FPGA Spartan6/M0_CLK" "M0_CLK" R21 1 U2 46 U1 H4 @@ -2457,467 +2457,467 @@ Net 38 "/FPGA Spartan6/M0_CKE" "M0_CKE" R24 2 U2 45 Net 39 "/DDR Banks/M0_CAS#" "M0_CAS#" - U2 22 RP16 5 + U2 22 Net 40 "/DDR Banks/M1_WE#" "M1_WE#" RP3 6 U3 21 -Net 41 "/DDR Banks/M1_RAS#" "M1_RAS#" - U3 23 +Net 41 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" RP2 8 -Net 42 "/DDR Banks/M0_RAS#" "M0_RAS#" + U3 23 +Net 42 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" RP15 8 U2 23 Net 43 "/DDR Banks/M0_WE#" "M0_WE#" - U2 21 RP16 6 -Net 44 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" - U2 16 + U2 21 +Net 44 "/DDR Banks/M0_LDQS" "M0_LDQS" RP16 8 + U2 16 Net 45 "/FPGA Spartan6/M0_UDM" "M0_UDM" R23 2 U2 47 Net 46 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" - U8 6 U1 AA21 + U8 6 Net 47 "/FPGA Spartan6/NF_RNB" "NF_RNB" - U1 A16 - U5 6 U5 7 -Net 48 "/FPGA Spartan6/NF_WE_N" "NF_WE_N" - U1 C15 + U5 6 + U1 A16 +Net 48 "/Non volatile memories/NF_WE_N" "NF_WE_N" U5 18 -Net 49 "/Non volatile memories/NF_CLE" "NF_CLE" - U5 16 + U1 C15 +Net 49 "/FPGA Spartan6/NF_CLE" "NF_CLE" U1 D15 -Net 50 "/Non volatile memories/SD_CMD" "SD_CMD" + U5 16 +Net 50 "/FPGA Spartan6/SD_CMD" "SD_CMD" U1 D17 J1 3 -Net 56 "+2.5V" "+2.5V" - U1 R21 - U1 L21 - U1 G21 - U1 U11 - U1 N18 - U1 C21 - U6 1 - U1 U18 - U1 E19 - C43 1 - C40 1 - U1 W21 - U1 H9 - C27 1 - U1 W2 - C32 1 +Net 55 "+2.5V" "+2.5V" + C17 1 + U1 L2 U1 R2 - C30 1 - C31 1 - U1 R10 + U6 1 + U1 W2 C29 1 - C28 1 - U1 F11 - U1 G12 - U1 C2 - U1 R12 + C31 1 + U1 U18 + U1 N18 + U2 1 + U2 3 + U1 J18 + U1 L16 + U3 33 U1 L8 U1 N8 - C53 1 - C51 1 - C49 1 - C46 1 - C52 1 - C66 1 - C63 1 - U3 33 + U1 C21 + U1 H9 + U1 G21 U3 18 - U1 L7 - U3 55 - U3 1 - C65 1 - C62 1 - C59 1 - U3 61 - C56 1 - U7 1 - U3 9 - U3 3 - C60 1 - C57 1 - C54 1 - C37 1 - U3 15 - C68 1 - U2 3 - U2 1 - U1 L16 - U2 55 - U2 15 - C17 1 - C19 1 - R11 1 - R13 1 - U2 9 - C77 1 - U1 J18 - U1 R6 - U1 V6 - C15 1 + U1 L21 + U1 R21 + U1 R10 + U1 E19 + U1 U11 + C30 1 + C32 1 + C27 1 + U1 G12 U1 F6 - U1 U5 - U1 N5 - U1 J5 + U3 15 + U1 R12 C34 1 C71 1 - U1 H15 - U1 D16 - U1 L2 - U1 G2 - C33 1 + C70 1 + U2 33 C22 1 C23 1 C25 1 C24 1 C26 1 C21 1 - U2 18 - C70 1 - U1 K15 - U2 61 - U1 M15 U1 F4 - U2 33 -Net 58 "" "" - R14 1 - R13 2 - C19 2 - U3 49 - C20 1 -Net 59 "" "" - C17 2 - C18 1 - R12 1 + C33 1 + C43 1 + C40 1 + C63 1 + C60 1 + C57 1 + C54 1 + R13 1 + U2 9 + C68 1 + C65 1 + U2 61 + C62 1 + U2 18 + C59 1 + C56 1 + U2 55 + U2 15 + C28 1 + C15 1 + C19 1 + C53 1 + C51 1 + R11 1 + C49 1 + C46 1 + C52 1 + C37 1 + U1 G2 + U1 C2 + U1 U5 + C77 1 + U1 M15 + U1 D16 + C66 1 + U1 R6 + U1 V6 + U3 61 + U7 1 + U1 J5 + U1 N5 + U1 F11 + U1 W21 + U3 55 + U3 1 + U1 K15 + U1 H15 + U3 3 + U1 L7 + U3 9 +Net 58 "/DDR Banks/M0_VREF" "M0_VREF" U2 49 + C18 1 + C17 2 R11 2 + R12 1 +Net 59 "/DDR Banks/M1_VREF" "M1_VREF" + C20 1 + C19 2 + R13 2 + R14 1 + U3 49 Net 68 "VCCO2" "VCCO2" - U1 AA3 - U1 T13 - U1 V16 - U1 AA7 - U1 AA19 - U1 W5 U1 T9 - U1 V12 - U8 8 + U1 AA3 U1 V8 + U1 AA15 + U8 8 + U1 V16 + U1 T13 + U1 V12 + U1 AA19 C69 1 C67 1 C64 1 C61 1 C58 1 C55 1 - U1 AA15 + U1 AA7 + U1 W5 U1 AA11 Net 87 "+3.3V" "+3.3V" - U1 E9 - U1 G14 + U1 B15 U1 B4 U1 B7 - U1 E13 - U1 B11 - U1 G10 - U1 B19 U1 E17 - U1 B15 - R1 2 - C1 1 - C3 1 - C5 1 + U1 B19 + U1 E9 + U1 G10 + U1 B11 + U1 E13 + U1 G14 + J4 6 + J4 9 + J4 11 L2 1 U4 7 - C10 1 + C5 1 + C3 1 + C1 1 + R1 2 C11 1 - J4 11 - J4 9 - J4 6 - J4 3 - U4 24 - R5 1 - R6 1 - R4 1 - R3 1 - L8 1 - C81 1 - C79 1 - C80 1 + C10 1 + C75 2 + U5 12 + U5 37 + U5 19 + J1 4 + C72 1 + C73 1 + C74 1 R26 1 - C35 1 - C36 1 - U6 14 - U6 12 - U7 12 - U7 14 - C13 1 + C80 1 + C79 1 + C81 1 + L8 1 C14 1 + C13 1 + U7 14 + U7 12 + U6 12 + U6 14 + C36 1 + C35 1 + R3 1 + R4 1 + R6 1 + R5 1 + U4 24 + J4 3 C50 1 C47 1 C44 1 C41 1 - U5 19 - J1 4 - U5 37 - U5 12 - C75 2 - C74 1 - C73 1 - C72 1 -Net 100 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" - RP7 3 - U1 C22 -Net 102 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" - U1 E22 +Net 100 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" RP1 3 -Net 103 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" + U1 E22 +Net 101 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" RP1 2 U1 F22 +Net 103 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" + U1 C22 + RP7 3 Net 104 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" RP7 1 U1 D22 Net 105 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" - U1 K20 RP6 3 -Net 106 "/FPGA Spartan6/R_M0_A3" "R_M0_A3" - RP14 4 - U1 K6 -Net 107 "/FPGA Spartan6/R_M0_A9" "R_M0_A9" - RP18 3 - U1 E1 -Net 108 "/FPGA Spartan6/R_M0_A11" "R_M0_A11" - U1 C1 - RP18 2 -Net 109 "/FPGA Spartan6/R_M0_A1" "R_M0_A1" - U1 H1 - RP14 2 -Net 110 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1" - U1 G1 - RP15 3 -Net 111 "/FPGA Spartan6/R_M0_A2" "R_M0_A2" - U1 H5 - RP14 3 -Net 112 "/FPGA Spartan6/R_M0_A5" "R_M0_A5" - RP17 3 - U1 K3 -Net 113 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" - RP10 3 - U1 V2 -Net 114 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" - RP10 1 - U1 U3 -Net 115 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" - U1 P1 - RP11 2 -Net 116 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" - RP11 4 - U1 R1 -Net 117 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10" - RP11 3 - U1 R3 -Net 118 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" - RP13 2 - U1 N1 -Net 119 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" - U1 M1 - RP13 4 -Net 120 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" - RP12 1 - U1 J3 -Net 121 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" - RP12 3 - U1 K2 -Net 122 "/FPGA Spartan6/R_M0_A4" "R_M0_A4" + U1 K20 +Net 109 "/FPGA Spartan6/R_M0_A4" "R_M0_A4" RP17 4 U1 F3 -Net 166 "+1.2V" "+1.2V" - U1 N10 - R28 1 - L9 1 - C85 1 - U1 L10 - U1 J10 - C84 1 - U1 P9 - U1 M9 - U1 K9 - U1 K13 - U1 M13 - U1 P13 - C76 1 - U1 J14 - U1 L14 - U1 N14 - U1 R14 - C83 1 - C48 1 - C45 1 - C42 1 - C39 1 - U1 K11 - U1 M11 - U1 P11 +Net 110 "/FPGA Spartan6/R_M0_A3" "R_M0_A3" + U1 K6 + RP14 4 +Net 111 "/FPGA Spartan6/R_M0_A9" "R_M0_A9" + U1 E1 + RP18 3 +Net 112 "/FPGA Spartan6/R_M0_A11" "R_M0_A11" + U1 C1 + RP18 2 +Net 113 "/FPGA Spartan6/R_M0_A1" "R_M0_A1" + U1 H1 + RP14 2 +Net 114 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1" + RP15 3 + U1 G1 +Net 115 "/FPGA Spartan6/R_M0_A2" "R_M0_A2" + RP14 3 + U1 H5 +Net 116 "/FPGA Spartan6/R_M0_A5" "R_M0_A5" + U1 K3 + RP17 3 +Net 117 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" + RP10 3 + U1 V2 +Net 118 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" + U1 U3 + RP10 1 +Net 119 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" + U1 P1 + RP11 2 +Net 120 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" + RP11 4 + U1 R1 +Net 121 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10" + RP11 3 + U1 R3 +Net 122 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" + RP13 2 + U1 N1 +Net 123 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" + RP13 4 + U1 M1 +Net 124 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" + RP12 1 + U1 J3 +Net 168 "+1.2V" "+1.2V" U1 J12 U1 L12 + R28 1 + U1 M11 + U1 P11 + L9 1 + C85 1 + U1 K11 + U1 R14 + C39 1 + U1 J14 + C42 1 + C45 1 + U1 K13 + U1 M13 + U1 N14 + C76 1 + U1 P13 U1 N12 U1 J8 -Net 167 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" - U1 J17 + U1 K9 + C84 1 + C83 1 + U1 M9 + U1 P9 + U1 J10 + U1 L10 + C48 1 + U1 L14 + U1 N10 +Net 169 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" RP2 2 -Net 168 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" - U1 R20 - RP9 2 -Net 169 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" - U1 U20 - RP8 4 -Net 170 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" - RP5 3 - U1 M21 -Net 171 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" - RP5 1 - U1 N20 -Net 176 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" - RP3 2 - U1 L19 -Net 177 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" - U1 H19 - RP3 3 -Net 193 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" - RP8 1 - U1 V22 -Net 194 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" - RP8 3 - U1 U22 -Net 196 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" - RP9 1 - U1 R22 -Net 197 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" - RP9 3 - U1 P22 -Net 198 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" - U1 N22 - RP5 2 -Net 199 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" - U1 M22 - RP5 4 -Net 206 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" - U1 K19 - RP6 2 -Net 207 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" - RP2 4 - U1 G19 -Net 208 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" - RP7 2 - U1 F19 -Net 211 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" - RP3 1 - U1 L20 -Net 212 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" - U1 M20 - R18 1 -Net 241 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" - RP10 4 - U1 V1 -Net 242 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" - RP10 2 - U1 U1 -Net 245 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" - U1 K1 - RP12 4 -Net 246 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" - RP12 2 - U1 J1 -Net 248 "/FPGA Spartan6/R_M0_A12" "R_M0_A12" - RP18 1 - U1 D1 -Net 311 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" - U1 J20 - RP4 1 -Net 312 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" - U1 G20 - RP1 4 -Net 314 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" - U1 E20 - RP6 1 -Net 316 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" - U1 C20 - RP7 4 -Net 335 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" - U1 K22 - RP4 4 -Net 336 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" - RP4 2 - U1 J22 -Net 339 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" - U1 V21 - RP8 2 -Net 340 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" - U1 P21 - RP9 4 -Net 341 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" - RP4 3 - U1 K21 -Net 342 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" - RP1 1 - U1 F21 -Net 351 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" - U1 N3 - RP13 1 -Net 352 "/FPGA Spartan6/R_M0_LDQS" "R_M0_LDQS" - RP16 1 - U1 L3 -Net 353 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0" - RP15 2 - U1 G3 -Net 354 "/FPGA Spartan6/R_M0_A8" "R_M0_A8" - RP18 4 - U1 E3 -Net 359 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS" - U1 T2 - R22 1 -Net 360 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" - U1 P2 - RP11 1 -Net 361 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" - U1 M2 - RP13 3 -Net 362 "/FPGA Spartan6/R_M0_A0" "R_M0_A0" - U1 H2 - RP14 1 -Net 364 "/FPGA Spartan6/R_M0_A7" "R_M0_A7" - RP17 1 - U1 H6 -Net 378 "/FPGA Spartan6/R_M0_A6" "R_M0_A6" - RP17 2 - U1 J4 -Net 379 "/FPGA Spartan6/R_M0_A10" "R_M0_A10" - RP15 4 - U1 G4 -Net 383 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" - U1 T21 - R19 1 -Net 384 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" - R17 1 - U1 D21 -Net 385 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" - U1 H16 - R20 1 -Net 386 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" + U1 J17 +Net 170 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" + RP12 3 + U1 K2 +Net 171 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" U1 K17 RP2 3 -Net 387 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" - RP2 1 - U1 H21 -Net 388 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" +Net 172 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" + U1 R20 + RP9 2 +Net 173 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" + RP8 4 + U1 U20 +Net 174 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" + U1 M21 + RP5 3 +Net 175 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" + RP5 1 + U1 N20 +Net 180 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" + RP3 2 + U1 L19 +Net 181 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" + U1 H19 + RP3 3 +Net 197 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" + RP8 1 + U1 V22 +Net 198 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" + RP8 3 + U1 U22 +Net 200 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" + U1 R22 + RP9 1 +Net 207 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" + RP6 2 + U1 K19 +Net 208 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" + RP2 4 + U1 G19 +Net 209 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" + RP7 2 + U1 F19 +Net 212 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" + RP3 1 + U1 L20 +Net 213 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" + U1 M20 + R18 1 +Net 242 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" + RP10 4 + U1 V1 +Net 243 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" + RP10 2 + U1 U1 +Net 246 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" + RP12 4 + U1 K1 +Net 247 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" + RP12 2 + U1 J1 +Net 249 "/FPGA Spartan6/R_M0_A12" "R_M0_A12" + U1 D1 + RP18 1 +Net 310 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" + U1 J20 + RP4 1 +Net 311 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" + U1 G20 + RP1 4 +Net 313 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" + RP6 1 + U1 E20 +Net 315 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" + U1 C20 + RP7 4 +Net 330 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" + RP9 3 + U1 P22 +Net 331 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" + U1 N22 + RP5 2 +Net 332 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" + RP5 4 + U1 M22 +Net 334 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" + RP4 4 + U1 K22 +Net 335 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" + RP4 2 + U1 J22 +Net 338 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" + U1 V21 + RP8 2 +Net 339 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" + U1 P21 + RP9 4 +Net 340 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" + RP4 3 + U1 K21 +Net 341 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" + U1 F21 + RP1 1 +Net 352 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" + U1 N3 + RP13 1 +Net 353 "/FPGA Spartan6/R_M0_LDQS" "R_M0_LDQS" + U1 L3 + RP16 1 +Net 354 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0" + RP15 2 + U1 G3 +Net 355 "/FPGA Spartan6/R_M0_A8" "R_M0_A8" + U1 E3 + RP18 4 +Net 360 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS" + R22 1 + U1 T2 +Net 361 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" + U1 P2 + RP11 1 +Net 362 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" + RP13 3 + U1 M2 +Net 363 "/FPGA Spartan6/R_M0_A0" "R_M0_A0" + RP14 1 + U1 H2 +Net 368 "/FPGA Spartan6/R_M0_A7" "R_M0_A7" + U1 H6 + RP17 1 +Net 382 "/FPGA Spartan6/R_M0_A6" "R_M0_A6" + RP17 2 + U1 J4 +Net 383 "/FPGA Spartan6/R_M0_A10" "R_M0_A10" + RP15 4 + U1 G4 +Net 384 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" U1 H22 RP3 4 +Net 385 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" + R19 1 + U1 T21 +Net 386 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" + R17 1 + U1 D21 +Net 387 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" + R20 1 + U1 H16 +Net 388 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" + U1 H21 + RP2 1 Net 389 "/FPGA Spartan6/R_M0_RAS#" "R_M0_RAS#" U1 K5 RP15 1 @@ -2925,8 +2925,8 @@ Net 390 "/FPGA Spartan6/R_M0_CKE" "R_M0_CKE" U1 D2 R24 1 Net 391 "/FPGA Spartan6/R_M0_UDM" "R_M0_UDM" - R23 1 U1 M3 + R23 1 Net 392 "/FPGA Spartan6/R_M0_LDM" "R_M0_LDM" RP16 2 U1 L4 @@ -2934,14 +2934,14 @@ Net 393 "/FPGA Spartan6/R_M0_WE#" "R_M0_WE#" U1 F2 RP16 3 Net 394 "/FPGA Spartan6/R_M0_CAS#" "R_M0_CAS#" - U1 K4 RP16 4 + U1 K4 Net 395 "" "" J4 10 R7 1 Net 396 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - R7 2 U4 26 + R7 2 Net 397 "" "" R2 1 U4 37 @@ -2949,72 +2949,72 @@ Net 398 "" "" R8 1 J4 12 Net 399 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - R8 2 U4 27 -Net 405 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - L2 2 - C8 1 - C7 1 - U4 38 -Net 406 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD" + R8 2 +Net 405 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD" J4 13 J4 14 C12 1 R9 1 -Net 407 "/Ethernet Phy/MAG_RX-" "MAG_RX-" +Net 406 "/Ethernet Phy/MAG_TX-" "MAG_TX-" + J4 2 + U4 40 + R4 2 +Net 407 "/Ethernet Phy/MAG_TX+" "MAG_TX+" + J4 1 + U4 41 + R3 2 +Net 408 "/Ethernet Phy/MAG_RX+" "MAG_RX+" + J4 7 + R5 2 + U4 33 +Net 409 "/Ethernet Phy/MAG_RX-" "MAG_RX-" J4 8 - U4 32 R6 2 -Net 408 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - U4 47 + U4 32 +Net 410 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" C9 1 + U4 47 L3 2 -Net 409 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" +Net 411 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + U4 38 + C7 1 + C8 1 + L2 2 +Net 412 "+1.8V" "+1.8V" + L1 1 + C4 1 + C2 1 + U4 13 +Net 415 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" U4 31 L3 1 C6 1 L1 2 -Net 410 "+1.8V" "+1.8V" - C2 1 - C4 1 - L1 1 - U4 13 -Net 413 "/Ethernet Phy/MAG_TX-" "MAG_TX-" - U4 40 - R4 2 - J4 2 -Net 414 "/Ethernet Phy/MAG_TX+" "MAG_TX+" - J4 1 - R3 2 - U4 41 -Net 415 "/Ethernet Phy/MAG_RX+" "MAG_RX+" - J4 7 - R5 2 - U4 33 Net 422 "" "" F2 1 L6 1 Net 424 "" "" - C16 1 J5 S1 J5 S2 - J5 S3 - J5 S4 + C16 1 R10 1 + J5 S4 + J5 S3 Net 425 "" "" - J5 4 L5 1 + J5 4 Net 426 "" "" V2 1 + U6 10 V2 1 J5 2 - U6 10 Net 427 "" "" L4 2 J5 1 Net 428 "+5V" "+5V" - F1 2 F2 2 + F1 2 Net 429 "" "" L4 1 F1 1 @@ -3024,9 +3024,9 @@ Net 430 "" "" V1 1 V1 1 Net 431 "" "" - V4 1 - V4 1 U7 10 + V4 1 + V4 1 Net 432 "" "" V3 1 V3 1 @@ -3035,32 +3035,32 @@ Net 433 "" "" R15 1 C38 1 Net 434 "" "" + U12 4 C82 1 U12 1 - U12 4 Net 435 "" "" + C83 2 U12 5 R27 1 R28 2 - C83 2 Net 436 "" "" U11 4 U11 1 C78 1 Net 437 "" "" - C79 2 R25 1 - R26 2 + C79 2 U11 5 + R26 2 Net 447 "" "" - U11 3 L8 2 + U11 3 Net 466 "" "" - U12 3 L9 2 + U12 3 Net 467 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" - U8 7 U1 U13 + U8 7 Net 468 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" U8 3 U1 U14 @@ -3068,18 +3068,18 @@ Net 469 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" U1 AA20 U8 2 Net 470 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" - U8 5 U1 AB20 -Net 471 "/Non volatile memories/NF_D7" "NF_D7" + U8 5 +Net 471 "/FPGA Spartan6/NF_D7" "NF_D7" U5 44 U1 A11 Net 472 "/Non volatile memories/NF_D6" "NF_D6" - U1 D11 U5 43 -Net 473 "/FPGA Spartan6/NF_D5" "NF_D5" + U1 D11 +Net 473 "/Non volatile memories/NF_D5" "NF_D5" U5 42 U1 C12 -Net 474 "/Non volatile memories/NF_D4" "NF_D4" +Net 474 "/FPGA Spartan6/NF_D4" "NF_D4" U5 41 U1 B12 Net 475 "/FPGA Spartan6/NF_D3" "NF_D3" @@ -3089,65 +3089,65 @@ Net 476 "/FPGA Spartan6/NF_D2" "NF_D2" U5 31 U1 C13 Net 477 "/Non volatile memories/NF_D1" "NF_D1" - U5 30 U1 A13 + U5 30 Net 478 "/Non volatile memories/NF_D0" "NF_D0" - U1 D14 U5 29 -Net 479 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" - U1 A8 + U1 D14 +Net 479 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" U4 20 + U1 A8 Net 480 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" - U1 C9 U4 19 + U1 C9 Net 481 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" - U1 D10 U4 18 -Net 482 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" - U4 17 + U1 D10 +Net 482 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" U1 A9 + U4 17 Net 483 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" U4 3 U1 C5 Net 484 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" - U1 C6 U4 4 -Net 485 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" + U1 C6 +Net 485 "/FPGA Spartan6/ETH_RXD1" "ETH_RXD1" U4 5 U1 A5 Net 486 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" - U1 B6 U4 6 -Net 487 "/FPGA Spartan6/M0_BA1" "M0_BA1" + U1 B6 +Net 487 "/DDR Banks/M0_BA1" "M0_BA1" RP15 6 U2 27 Net 488 "/DDR Banks/M0_BA0" "M0_BA0" - U2 26 RP15 7 + U2 26 Net 489 "/DDR Banks/M1_BA1" "M1_BA1" - U3 27 RP2 6 -Net 490 "/DDR Banks/M1_BA0" "M1_BA0" - RP2 7 + U3 27 +Net 490 "/FPGA Spartan6/M1_BA0" "M1_BA0" U3 26 -Net 491 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" - U3 65 + RP2 7 +Net 491 "/DDR Banks/M1_DQ15" "M1_DQ15" RP8 8 -Net 492 "/DDR Banks/M1_DQ14" "M1_DQ14" + U3 65 +Net 492 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" RP8 7 U3 63 -Net 493 "/DDR Banks/M1_DQ13" "M1_DQ13" +Net 493 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" U3 62 RP8 6 -Net 494 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" - U3 60 +Net 494 "/DDR Banks/M1_DQ12" "M1_DQ12" RP8 5 -Net 495 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" + U3 60 +Net 495 "/DDR Banks/M1_DQ11" "M1_DQ11" RP9 8 U3 59 Net 496 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" - RP9 7 U3 57 + RP9 7 Net 497 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" U1 C17 J1 2 @@ -3155,86 +3155,86 @@ Net 498 "/Non volatile memories/SD_DAT2" "SD_DAT2" U1 A17 J1 1 Net 499 "/Non volatile memories/SD_DAT1" "SD_DAT1" - J1 8 U1 B18 -Net 500 "/Non volatile memories/SD_DAT0" "SD_DAT0" + J1 8 +Net 500 "/FPGA Spartan6/SD_DAT0" "SD_DAT0" J1 7 U1 A18 -Net 501 "/FPGA Spartan6/M1_A7" "M1_A7" - RP6 8 +Net 501 "/DDR Banks/M1_A7" "M1_A7" U3 38 -Net 502 "/DDR Banks/M1_A6" "M1_A6" + RP6 8 +Net 502 "/FPGA Spartan6/M1_A6" "M1_A6" U3 37 RP6 7 -Net 503 "/DDR Banks/M1_A5" "M1_A5" - RP6 6 +Net 503 "/FPGA Spartan6/M1_A5" "M1_A5" U3 36 -Net 504 "/DDR Banks/M1_A4" "M1_A4" + RP6 6 +Net 504 "/FPGA Spartan6/M1_A4" "M1_A4" U3 35 RP6 5 Net 505 "/FPGA Spartan6/M1_A3" "M1_A3" - RP1 5 U3 32 + RP1 5 Net 506 "/FPGA Spartan6/M1_A2" "M1_A2" - RP1 6 U3 31 + RP1 6 Net 507 "/FPGA Spartan6/M1_A1" "M1_A1" RP1 7 U3 30 -Net 508 "/FPGA Spartan6/M1_A0" "M1_A0" - U3 29 +Net 508 "/DDR Banks/M1_A0" "M1_A0" RP1 8 + U3 29 Net 509 "/FPGA Spartan6/M0_A12" "M0_A12" - RP18 8 U2 42 + RP18 8 Net 510 "/FPGA Spartan6/M0_A11" "M0_A11" U2 41 RP18 7 Net 511 "/FPGA Spartan6/M0_A10" "M0_A10" - RP15 5 U2 28 -Net 512 "/FPGA Spartan6/M0_A9" "M0_A9" - RP18 6 + RP15 5 +Net 512 "/DDR Banks/M0_A9" "M0_A9" U2 40 -Net 513 "/DDR Banks/M0_A8" "M0_A8" - U2 39 + RP18 6 +Net 513 "/FPGA Spartan6/M0_A8" "M0_A8" RP18 5 -Net 514 "/FPGA Spartan6/M0_A7" "M0_A7" - U2 38 + U2 39 +Net 514 "/DDR Banks/M0_A7" "M0_A7" RP17 8 + U2 38 Net 515 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" U3 56 RP9 6 Net 516 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" - U3 54 RP9 5 + U3 54 Net 517 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" - U3 13 RP4 5 + U3 13 Net 518 "/DDR Banks/M1_DQ6" "M1_DQ6" U3 11 RP4 6 -Net 519 "/DDR Banks/M1_DQ5" "M1_DQ5" - U3 10 +Net 519 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" RP4 7 + U3 10 Net 520 "/DDR Banks/M1_DQ4" "M1_DQ4" U3 8 RP4 8 Net 521 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" RP5 5 U3 7 -Net 522 "/DDR Banks/M1_DQ2" "M1_DQ2" - U3 5 +Net 522 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" RP5 6 + U3 5 Net 523 "/DDR Banks/M1_DQ1" "M1_DQ1" U3 4 RP5 7 -Net 524 "/DDR Banks/M1_DQ0" "M1_DQ0" - RP5 8 +Net 524 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" U3 2 -Net 525 "/DDR Banks/M1_A12" "M1_A12" - RP7 8 + RP5 8 +Net 525 "/FPGA Spartan6/M1_A12" "M1_A12" U3 42 + RP7 8 Net 526 "/DDR Banks/M1_A11" "M1_A11" RP7 7 U3 41 @@ -3242,53 +3242,53 @@ Net 527 "/FPGA Spartan6/M1_A10" "M1_A10" U3 28 RP2 5 Net 528 "/FPGA Spartan6/M1_A9" "M1_A9" - U3 40 RP7 6 + U3 40 Net 529 "/DDR Banks/M1_A8" "M1_A8" U3 39 RP7 5 -Net 530 "/DDR Banks/M0_DQ3" "M0_DQ3" +Net 530 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" U2 7 RP13 5 Net 531 "/DDR Banks/M0_DQ2" "M0_DQ2" U2 5 RP13 6 Net 532 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" - RP13 7 U2 4 + RP13 7 Net 533 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" RP13 8 U2 2 -Net 534 "/FPGA Spartan6/M0_A6" "M0_A6" +Net 534 "/DDR Banks/M0_A6" "M0_A6" RP17 7 U2 37 Net 535 "/DDR Banks/M0_A5" "M0_A5" - U2 36 RP17 6 + U2 36 Net 536 "/FPGA Spartan6/M0_A4" "M0_A4" RP17 5 U2 35 -Net 537 "/DDR Banks/M0_A3" "M0_A3" +Net 537 "/FPGA Spartan6/M0_A3" "M0_A3" U2 32 RP14 5 -Net 538 "/FPGA Spartan6/M0_A2" "M0_A2" - RP14 6 +Net 538 "/DDR Banks/M0_A2" "M0_A2" U2 31 + RP14 6 Net 539 "/FPGA Spartan6/M0_A1" "M0_A1" RP14 7 U2 30 Net 540 "/DDR Banks/M0_A0" "M0_A0" - U2 29 RP14 8 -Net 541 "/DDR Banks/M0_DQ15" "M0_DQ15" + U2 29 +Net 541 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" U2 65 RP10 5 Net 542 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" - U2 63 RP10 6 + U2 63 Net 543 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" - U2 62 RP10 7 + U2 62 Net 544 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" RP10 8 U2 60 @@ -3301,20 +3301,20 @@ Net 546 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" Net 547 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" U2 56 RP11 7 -Net 548 "/DDR Banks/M0_DQ8" "M0_DQ8" - U2 54 +Net 548 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" RP11 8 + U2 54 Net 549 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" - RP12 5 U2 13 + RP12 5 Net 550 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" - RP12 6 U2 11 -Net 551 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" - RP12 7 + RP12 6 +Net 551 "/DDR Banks/M0_DQ5" "M0_DQ5" U2 10 + RP12 7 Net 552 "/DDR Banks/M0_DQ4" "M0_DQ4" - U2 8 RP12 8 + U2 8 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 9811793..278c1b6 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Fri 20 Aug 2010 08:06:20 PM COT +update=Sat 21 Aug 2010 06:55:47 AM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 9413543..5e5cd36 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 20 Aug 2010 07:49:18 PM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03