From 29e7ceda7ccbe5fc20a262feae254b0c9fcd679f Mon Sep 17 00:00:00 2001
From: Wolfgang Spraul <wolfgang@sharism.cc>
Date: Sun, 19 Dec 2010 01:38:43 +0000
Subject: [PATCH] unzipped 2 files

---
 sim/verilog/micron/2048Mb_ddr2.zip            |  Bin 37247 -> 0 bytes
 sim/verilog/micron/mobile_ddr.zip             |  Bin 39500 -> 0 bytes
 sim/verilog/micron_2048Mb_ddr2/ddr2.v         | 2031 ++++++++++++++++
 sim/verilog/micron_2048Mb_ddr2/ddr2_mcp.v     |   94 +
 sim/verilog/micron_2048Mb_ddr2/ddr2_module.v  |  377 +++
 .../micron_2048Mb_ddr2/ddr2_parameters.vh     |  383 +++
 sim/verilog/micron_2048Mb_ddr2/readme.txt     |  190 ++
 sim/verilog/micron_2048Mb_ddr2/subtest.vh     |  225 ++
 sim/verilog/micron_2048Mb_ddr2/tb.do          |   31 +
 sim/verilog/micron_2048Mb_ddr2/tb.v           |  468 ++++
 .../1024Mb_mobile_ddr_parameters.vh           |  167 ++
 .../128Mb_mobile_ddr_parameters.vh            |  153 ++
 .../2048Mb_mobile_ddr_parameters.vh           |  179 ++
 .../256Mb_mobile_ddr_parameters.vh            |  134 ++
 .../512Mb_mobile_ddr_parameters.vh            |  162 ++
 sim/verilog/micron_mobile_ddr/mobile_ddr.v    | 2126 +++++++++++++++++
 .../micron_mobile_ddr/mobile_ddr_mcp.v        |   84 +
 sim/verilog/micron_mobile_ddr/readme.txt      |  167 ++
 sim/verilog/micron_mobile_ddr/subtest.vh      |   32 +
 sim/verilog/micron_mobile_ddr/tb.do           |   39 +
 sim/verilog/micron_mobile_ddr/tb.v            |  587 +++++
 21 files changed, 7629 insertions(+)
 delete mode 100644 sim/verilog/micron/2048Mb_ddr2.zip
 delete mode 100644 sim/verilog/micron/mobile_ddr.zip
 create mode 100644 sim/verilog/micron_2048Mb_ddr2/ddr2.v
 create mode 100644 sim/verilog/micron_2048Mb_ddr2/ddr2_mcp.v
 create mode 100644 sim/verilog/micron_2048Mb_ddr2/ddr2_module.v
 create mode 100644 sim/verilog/micron_2048Mb_ddr2/ddr2_parameters.vh
 create mode 100644 sim/verilog/micron_2048Mb_ddr2/readme.txt
 create mode 100644 sim/verilog/micron_2048Mb_ddr2/subtest.vh
 create mode 100644 sim/verilog/micron_2048Mb_ddr2/tb.do
 create mode 100644 sim/verilog/micron_2048Mb_ddr2/tb.v
 create mode 100644 sim/verilog/micron_mobile_ddr/1024Mb_mobile_ddr_parameters.vh
 create mode 100644 sim/verilog/micron_mobile_ddr/128Mb_mobile_ddr_parameters.vh
 create mode 100644 sim/verilog/micron_mobile_ddr/2048Mb_mobile_ddr_parameters.vh
 create mode 100644 sim/verilog/micron_mobile_ddr/256Mb_mobile_ddr_parameters.vh
 create mode 100644 sim/verilog/micron_mobile_ddr/512Mb_mobile_ddr_parameters.vh
 create mode 100644 sim/verilog/micron_mobile_ddr/mobile_ddr.v
 create mode 100644 sim/verilog/micron_mobile_ddr/mobile_ddr_mcp.v
 create mode 100644 sim/verilog/micron_mobile_ddr/readme.txt
 create mode 100644 sim/verilog/micron_mobile_ddr/subtest.vh
 create mode 100644 sim/verilog/micron_mobile_ddr/tb.do
 create mode 100644 sim/verilog/micron_mobile_ddr/tb.v

diff --git a/sim/verilog/micron/2048Mb_ddr2.zip b/sim/verilog/micron/2048Mb_ddr2.zip
deleted file mode 100644
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diff --git a/sim/verilog/micron_2048Mb_ddr2/ddr2.v b/sim/verilog/micron_2048Mb_ddr2/ddr2.v
new file mode 100644
index 0000000..481fadc
--- /dev/null
+++ b/sim/verilog/micron_2048Mb_ddr2/ddr2.v
@@ -0,0 +1,2031 @@
+/****************************************************************************************
+*
+*    File Name:  ddr2.v
+*      Version:  5.83
+*        Model:  BUS Functional
+*
+* Dependencies:  ddr2_parameters.vh
+*
+*  Description:  Micron SDRAM DDR2 (Double Data Rate 2)
+*
+*   Limitation:  - doesn't check for average refresh timings
+*                - positive ck and ck_n edges are used to form internal clock
+*                - positive dqs and dqs_n edges are used to latch data
+*                - test mode is not modeled
+*
+*         Note:  - Set simulator resolution to "ps" accuracy
+*                - Set Debug = 0 to disable $display messages
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+* Rev   Author   Date        Changes
+* ---------------------------------------------------------------------------------------
+* 1.00  JMK      07/29/03    Initial Release
+* 1.10  JMK      08/09/03    Timing Parameter updates to tIS, tIH, tDS, tDH
+* 2.20  JMK      08/07/03    General cleanup
+* 2.30  JMK      11/26/03    Added CL_MIN, CL_MAX, wl_min and wl_max parameters.
+*                            Added AL_MIN and AL_MAX parameters.
+*                            Removed support for OCD.
+* 2.40  JMK      01/15/04    Removed verilog 2001 constructs.
+* 2.50  JMK      01/29/04    Removed tRP checks during Precharge command.
+* 2.60  JMK      04/20/04    Fixed tWTR check.
+* 2.70  JMK      04/30/04    Added tRFC maximum check.
+*                            Combined Self Refresh and Power Down always blocks.
+*                            Added Reset Function (CKE LOW Anytime).
+* 2.80  JMK      08/19/04    Precharge is treated as NOP when bank is not active.  
+*                            Added checks for tRAS, tWR, tRTP to any bank during Pre-All.
+*                            tRFC maximum violation will only display one time.
+* 2.90  JMK      11/05/04    Fixed DQS checking during write.
+*                            Fixed false tRFC max assertion during power up and self ref.
+*                            Added warning for 200us CKE low time during initialization.
+*                            Added -3, -3E, and -37V speed grades to ddr2_parameters.v
+* 3.00  JMK      04/22/05    Removed ODT off requirement during power down.
+*                            Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.
+*                            Added ODT status messages.
+*                            Updated the initialization sequence.
+*                            Disable ODT and CLK pins during self refresh.
+*                            Disable cmd and addr pins during power down and self refresh.
+* 3.10  JMK      06/07/05    Disable trpa checking if the part does not have 8 banks.
+*                            Changed tAXPD message from error to a warning.
+*                            Added tDSS checking.
+*                            Removed tDQSL checking during tWPRE and tWPST.
+*                            Fixed a burst order error during writes.
+*                            Renamed parameters file with .vh extension.
+* 3.20  JMK      07/18/05    Removed 14 tCK requirement from LMR to READ.
+* 3.30  JMK      08/03/05    Added check for interrupting a burst with auto precharge.
+* 4.00  JMK      11/21/05    Parameter names all UPPERCASE, signal names all lowercase.
+*                            Clock jitter can be tolerated within specification range.
+*                            Clock frequency is sampled from the CK pin.
+*                            Scaleable up to 64 DQ and 16 DQS bits.
+*                            Read data can be randomly skewed using RANDOM_OUT_DELAY.
+*                            Parameterized read and write DQS, and read DQ.
+*                            Initialization can be bypassed using initialize task.
+* 4.10  JMK      11/30/05    Fixed compile errors when `MAX_MEM was defined.
+* 4.20  JMK      12/09/05    Fixed memory addressing error when `MAX_MEM was defined.
+* 4.30  JMK      02/15/06    Added dummy write to initialization sequence.
+*                            Removed tWPST maximum checking.
+*                            Rising dqs_n edge latches data when enabled in EMR.
+*                            Fixed a sign error in the tJIT(cc) calculation.
+* 4.40  JMK      02/16/06    Fixed dummy write when`MAX_MEM was defined.
+* 4.50  JMK      02/27/06    Fixed extra tDQSS assertions.
+*                            Fixed tRCD and tWTR checking.
+*                            Errors entering Power Down or Self Refresh will cause reset.
+*                            Ignore dqs_n when disabled in EMR.
+* 5.00  JMK      04/24/06    Test stimulus now included from external file (subtest.vh)
+*                            Fixed tRFC max assertion during self refresh.
+*                            Fixed tANPD checking during Power Down.
+*                            Removed dummy write from initialization sequence.
+* 5.01  JMK      04/28/06    Fixed Auto Precharge to Load Mode, Refresh and Self Refresh.
+*                            Removed Auto Precharge error message during Power Down Enter.
+* 5.10  JMK      07/26/06    Created internal clock using ck and ck_n.
+*                            RDQS can only be enabled in EMR for x8 configurations.
+*                            CAS latency is checked vs frequency when DLL locks.
+*                            tMOD changed from tCK units to ns units.
+*                            Added 50 Ohm setting for Rtt in EMR.
+*                            Improved checking of DQS during writes.
+* 5.20  JMK      10/02/06    Fixed DQS checking for interrupting write to write and x16.
+* 5.30  JMK      05/25/07    Fixed checking for 0-Z transition on write postamble.
+* 5.50  JMK      05/30/08    Renamed ddr2_dimm.v to ddr2_module.v and added SODIMM support.
+*                            Added a register delay to ddr2_module.v when RDIMM is defined.
+*                            Added multi-chip package model support in ddr2_mcp.v
+*                            Added High Temp Self Refresh rate setting in EMRS2[7]
+* 5.70  JMK      04/23/09    Updated tRPA definition
+*                            Increased internal width to 72 bit DQ bus
+* 5.80  SPH      08/12/09    Fixed tRAS maximum violation (only check if bank still open)
+* 5.81  SPH      12/08/09    Only check tIH for cmd_addr if CS# LOW
+* 5.82  SPH      04/08/10    Correct debug message for SRT in EMR2         
+* 5.83  SPH      04/29/10    Correct tDQSS check on valid DQS group
+****************************************************************************************/
+
+// DO NOT CHANGE THE TIMESCALE
+// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
+`timescale 1ps / 1ps
+
+module ddr2 (
+    ck,
+    ck_n,
+    cke,
+    cs_n,
+    ras_n,
+    cas_n,
+    we_n,
+    dm_rdqs,
+    ba,
+    addr,
+    dq,
+    dqs,
+    dqs_n,
+    rdqs_n,
+    odt
+);
+
+    `include "ddr2_parameters.vh"
+
+    // text macros
+    `define DQ_PER_DQS DQ_BITS/DQS_BITS
+    `define BANKS      (1<<BA_BITS)
+    `define MAX_BITS   (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
+    `define MAX_SIZE   (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
+    `define MEM_SIZE   (1<<MEM_BITS)
+    `define MAX_PIPE   2*(AL_MAX + CL_MAX)
+
+    // Declare Ports
+    input   ck;
+    input   ck_n;
+    input   cke;
+    input   cs_n;
+    input   ras_n;
+    input   cas_n;
+    input   we_n;
+    inout   [DM_BITS-1:0]   dm_rdqs;
+    input   [BA_BITS-1:0]   ba;
+    input   [ADDR_BITS-1:0] addr;
+    inout   [DQ_BITS-1:0]   dq;
+    inout   [DQS_BITS-1:0]  dqs;
+    inout   [DQS_BITS-1:0]  dqs_n;
+    output  [DQS_BITS-1:0]  rdqs_n;
+    input   odt;
+                            
+    // clock jitter
+    real    tck_avg;
+    time    tck_sample [TDLLK-1:0];
+    time    tch_sample [TDLLK-1:0];
+    time    tcl_sample [TDLLK-1:0];
+    time    tck_i;
+    time    tch_i;
+    time    tcl_i;
+    real    tch_avg;
+    real    tcl_avg;
+    time    tm_ck_pos;
+    time    tm_ck_neg;
+    real    tjit_per_rtime;
+    integer tjit_cc_time;
+    real    terr_nper_rtime;
+
+    // clock skew
+    real    out_delay;
+    integer dqsck [DQS_BITS-1:0];
+    integer dqsck_min;
+    integer dqsck_max;
+    integer dqsq_min;
+    integer dqsq_max;
+    integer seed;
+
+    // Mode Registers
+    reg     burst_order;
+    reg     [BL_BITS:0] burst_length;
+    integer cas_latency;
+    integer additive_latency;
+    reg     dll_reset;
+    reg     dll_locked;
+    reg     dll_en;
+    integer write_recovery;
+    reg     low_power;
+    reg     [1:0] odt_rtt;
+    reg     odt_en;
+    reg     [2:0] ocd;
+    reg     dqs_n_en;
+    reg     rdqs_en;
+    reg     out_en;
+    integer read_latency;
+    integer write_latency;
+
+    // cmd encoding
+    parameter
+        LOAD_MODE = 4'b0000,
+        REFRESH   = 4'b0001,
+        PRECHARGE = 4'b0010,
+        ACTIVATE  = 4'b0011,
+        WRITE     = 4'b0100,
+        READ      = 4'b0101,
+        NOP       = 4'b0111,
+        PWR_DOWN  = 4'b1000,
+        SELF_REF  = 4'b1001
+    ;
+
+    reg [8*9-1:0] cmd_string [9:0];
+    initial begin
+        cmd_string[LOAD_MODE] = "Load Mode";
+        cmd_string[REFRESH  ] = "Refresh  ";
+        cmd_string[PRECHARGE] = "Precharge";
+        cmd_string[ACTIVATE ] = "Activate ";
+        cmd_string[WRITE    ] = "Write    ";
+        cmd_string[READ     ] = "Read     ";
+        cmd_string[NOP      ] = "No Op    ";
+        cmd_string[PWR_DOWN ] = "Pwr Down ";
+        cmd_string[SELF_REF ] = "Self Ref ";
+    end
+
+    // command state
+    reg     [`BANKS-1:0] active_bank;
+    reg     [`BANKS-1:0] auto_precharge_bank;
+    reg     [`BANKS-1:0] write_precharge_bank;
+    reg     [`BANKS-1:0] read_precharge_bank;
+    reg     [ROW_BITS-1:0] active_row [`BANKS-1:0];
+    reg     in_power_down;
+    reg     in_self_refresh;
+    reg     [3:0] init_mode_reg;
+    reg     init_done;
+    integer init_step;
+    reg     er_trfc_max;
+    reg     odt_state;
+    reg     prev_odt;
+
+    // cmd timers/counters
+    integer ref_cntr;
+    integer ck_cntr;
+    integer ck_load_mode;
+    integer ck_write;
+    integer ck_read;
+    integer ck_write_ap;
+    integer ck_power_down;
+    integer ck_slow_exit_pd;
+    integer ck_self_refresh;
+    integer ck_cke;
+    integer ck_odt;
+    integer ck_dll_reset;
+    integer ck_bank_write     [`BANKS-1:0];
+    integer ck_bank_read      [`BANKS-1:0];
+    time    tm_refresh;
+    time    tm_precharge;
+    time    tm_precharge_all;
+    time    tm_activate;
+    time    tm_write_end;
+    time    tm_self_refresh;
+    time    tm_odt_en;
+    time    tm_bank_precharge [`BANKS-1:0];
+    time    tm_bank_activate  [`BANKS-1:0];
+    time    tm_bank_write_end [`BANKS-1:0];
+    time    tm_bank_read_end  [`BANKS-1:0];
+
+    // pipelines
+    reg     [`MAX_PIPE:0]   al_pipeline;
+    reg     [`MAX_PIPE:0]   wr_pipeline;
+    reg     [`MAX_PIPE:0]   rd_pipeline;
+    reg     [`MAX_PIPE:0]   odt_pipeline;
+    reg     [BA_BITS-1:0]   ba_pipeline  [`MAX_PIPE:0];
+    reg     [ROW_BITS-1:0]  row_pipeline [`MAX_PIPE:0];
+    reg     [COL_BITS-1:0]  col_pipeline [`MAX_PIPE:0];
+    reg     prev_cke;
+    
+    // data state
+    reg     [BL_MAX*DQ_BITS-1:0] memory_data;
+    reg     [BL_MAX*DQ_BITS-1:0] bit_mask;
+    reg     [BL_BITS-1:0]        burst_position;
+    reg     [BL_BITS:0]          burst_cntr;
+    reg     [DQ_BITS-1:0]        dq_temp;
+    reg     [35:0] check_write_postamble;
+    reg     [35:0] check_write_preamble;
+    reg     [35:0] check_write_dqs_high;
+    reg     [35:0] check_write_dqs_low;
+    reg     [17:0] check_dm_tdipw;
+    reg     [71:0] check_dq_tdipw;
+
+    // data timers/counters
+    time    tm_cke;
+    time    tm_odt;
+    time    tm_tdqss;
+    time    tm_dm        [17:0];
+    time    tm_dqs       [17:0];
+    time    tm_dqs_pos   [35:0];
+    time    tm_dqss_pos  [35:0];
+    time    tm_dqs_neg   [35:0];
+    time    tm_dq        [71:0];
+    time    tm_cmd_addr  [22:0];
+    reg [8*7-1:0] cmd_addr_string [22:0];
+    initial begin
+        cmd_addr_string[ 0] = "CS_N   ";
+        cmd_addr_string[ 1] = "RAS_N  ";
+        cmd_addr_string[ 2] = "CAS_N  ";
+        cmd_addr_string[ 3] = "WE_N   ";
+        cmd_addr_string[ 4] = "BA 0   ";
+        cmd_addr_string[ 5] = "BA 1   ";
+        cmd_addr_string[ 6] = "BA 2   ";
+        cmd_addr_string[ 7] = "ADDR  0";
+        cmd_addr_string[ 8] = "ADDR  1";
+        cmd_addr_string[ 9] = "ADDR  2";
+        cmd_addr_string[10] = "ADDR  3";
+        cmd_addr_string[11] = "ADDR  4";
+        cmd_addr_string[12] = "ADDR  5";
+        cmd_addr_string[13] = "ADDR  6";
+        cmd_addr_string[14] = "ADDR  7";
+        cmd_addr_string[15] = "ADDR  8";
+        cmd_addr_string[16] = "ADDR  9";
+        cmd_addr_string[17] = "ADDR 10";
+        cmd_addr_string[18] = "ADDR 11";
+        cmd_addr_string[19] = "ADDR 12";
+        cmd_addr_string[20] = "ADDR 13";
+        cmd_addr_string[21] = "ADDR 14";
+        cmd_addr_string[22] = "ADDR 15";
+    end
+
+    reg [8*5-1:0] dqs_string [1:0];
+    initial begin
+        dqs_string[0] = "DQS  ";
+        dqs_string[1] = "DQS_N";
+    end
+
+    // Memory Storage
+`ifdef MAX_MEM
+    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MAX_SIZE-1];
+`else
+    reg     [BL_MAX*DQ_BITS-1:0] memory  [0:`MEM_SIZE-1];
+    reg     [`MAX_BITS-1:0]      address [0:`MEM_SIZE-1];
+    reg     [MEM_BITS:0]         memory_index;
+    reg     [MEM_BITS:0]         memory_used;
+`endif
+
+    // receive
+    reg            ck_in;
+    reg            ck_n_in;
+    reg            cke_in;
+    reg            cs_n_in;
+    reg            ras_n_in;
+    reg            cas_n_in;
+    reg            we_n_in;
+    reg     [17:0] dm_in;
+    reg     [2:0]  ba_in;
+    reg     [15:0] addr_in;
+    reg     [71:0] dq_in;
+    reg     [35:0] dqs_in;
+    reg            odt_in;
+
+    reg     [17:0] dm_in_pos;
+    reg     [17:0] dm_in_neg;
+    reg     [71:0] dq_in_pos;
+    reg     [71:0] dq_in_neg;
+    reg            dq_in_valid;
+    reg            dqs_in_valid;
+    integer        wdqs_cntr;
+    integer        wdq_cntr;
+    integer        wdqs_pos_cntr [35:0];
+    reg            b2b_write;
+    reg     [35:0] prev_dqs_in;
+    reg            diff_ck;
+
+    always @(ck     ) ck_in     <= #BUS_DELAY ck;
+    always @(ck_n   ) ck_n_in   <= #BUS_DELAY ck_n;
+    always @(cke    ) cke_in    <= #BUS_DELAY cke;
+    always @(cs_n   ) cs_n_in   <= #BUS_DELAY cs_n;
+    always @(ras_n  ) ras_n_in  <= #BUS_DELAY ras_n;
+    always @(cas_n  ) cas_n_in  <= #BUS_DELAY cas_n;
+    always @(we_n   ) we_n_in   <= #BUS_DELAY we_n;
+    always @(dm_rdqs) dm_in     <= #BUS_DELAY dm_rdqs;
+    always @(ba     ) ba_in     <= #BUS_DELAY ba;
+    always @(addr   ) addr_in   <= #BUS_DELAY addr;
+    always @(dq     ) dq_in     <= #BUS_DELAY dq;
+    always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<18) | dqs;
+    always @(odt    ) odt_in    <= #BUS_DELAY odt;
+    // create internal clock
+    always @(posedge ck_in)   diff_ck <= ck_in;
+    always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
+
+    wire    [17:0] dqs_even = dqs_in[17:0];
+    wire    [17:0] dqs_odd  = dqs_n_en ? dqs_in[35:18] : ~dqs_in[17:0];
+    wire    [3:0]  cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP;  //deselect = nop 
+
+    // transmit
+    reg                    dqs_out_en;
+    reg     [DQS_BITS-1:0] dqs_out_en_dly;
+    reg                    dqs_out;
+    reg     [DQS_BITS-1:0] dqs_out_dly;
+    reg                    dq_out_en;
+    reg     [DQ_BITS-1:0]  dq_out_en_dly;
+    reg     [DQ_BITS-1:0]  dq_out;
+    reg     [DQ_BITS-1:0]  dq_out_dly;
+    integer                rdqsen_cntr;
+    integer                rdqs_cntr;
+    integer                rdqen_cntr;
+    integer                rdq_cntr;
+
+    bufif1 buf_dqs    [DQS_BITS-1:0] (dqs,     dqs_out_dly,  dqs_out_en_dly & {DQS_BITS{out_en}});
+    bufif1 buf_dm     [DM_BITS-1:0]  (dm_rdqs, dqs_out_dly,  dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});
+    bufif1 buf_dqs_n  [DQS_BITS-1:0] (dqs_n,   ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});
+    bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n,  ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});
+    bufif1 buf_dq     [DQ_BITS-1:0]  (dq,      dq_out_dly,   dq_out_en_dly  & {DQ_BITS {out_en}});
+
+    initial begin
+        if (BL_MAX < 2) 
+            $display("%m ERROR: BL_MAX parameter must be >= 2.  \nBL_MAX = %d", BL_MAX);
+        if ((1<<BO_BITS) > BL_MAX) 
+            $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
+        $timeformat (-12, 1, " ps", 1);
+        reset_task;
+        seed = RANDOM_SEED;
+        ck_cntr = 0;
+    end
+
+    // calculate the absolute value of a real number
+    function real abs_value;
+    input arg;
+    real arg;
+    begin
+        if (arg < 0.0)
+            abs_value = -1.0 * arg;
+        else
+            abs_value = arg;
+    end
+    endfunction
+
+`ifdef MAX_MEM
+`else
+    function get_index;
+        input [`MAX_BITS-1:0] addr;
+        begin : index
+            get_index = 0;
+            for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
+                if (address[memory_index] == addr) begin
+                    get_index = 1;
+                    disable index;
+                end
+            end
+        end
+    endfunction
+`endif
+
+    task memory_write;
+        input  [BA_BITS-1:0]  bank;
+        input  [ROW_BITS-1:0] row;
+        input  [COL_BITS-1:0] col;
+        input  [BL_MAX*DQ_BITS-1:0] data;
+        reg    [`MAX_BITS-1:0] addr;
+        begin
+            // chop off the lowest address bits
+            addr = {bank, row, col}/BL_MAX;
+`ifdef MAX_MEM
+            memory[addr] = data;
+`else
+            if (get_index(addr)) begin
+                address[memory_index] = addr;
+                memory[memory_index] = data;
+            end else if (memory_used == `MEM_SIZE) begin
+                $display ("%m: at time %t ERROR: Memory overflow.  Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
+                if (STOP_ON_ERROR) $stop(0);
+            end else begin
+                address[memory_used] = addr;
+                memory[memory_used] = data;
+                memory_used = memory_used + 1;
+            end
+`endif
+        end
+    endtask
+
+    task memory_read;
+        input  [BA_BITS-1:0]  bank;
+        input  [ROW_BITS-1:0] row;
+        input  [COL_BITS-1:0] col;
+        output [BL_MAX*DQ_BITS-1:0] data;
+        reg    [`MAX_BITS-1:0] addr;
+        begin
+            // chop off the lowest address bits
+            addr = {bank, row, col}/BL_MAX;
+`ifdef MAX_MEM
+            data = memory[addr];
+`else
+            if (get_index(addr)) begin
+                data = memory[memory_index];
+            end else begin
+                data = {BL_MAX*DQ_BITS{1'bx}};
+            end
+`endif
+        end
+    endtask
+
+    // Before this task runs, the model must be in a valid state for precharge power down.
+    // After this task runs, NOP commands must be issued until tRFC has been met
+    task initialize;
+        input [ADDR_BITS-1:0] mode_reg0;
+        input [ADDR_BITS-1:0] mode_reg1;
+        input [ADDR_BITS-1:0] mode_reg2;
+        input [ADDR_BITS-1:0] mode_reg3;
+        begin
+            if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
+            cmd_task(1,       NOP, 'bx, 'bx);
+            cmd_task(1, PRECHARGE, 'bx, 1<<AP);           // Precharege ALL
+            cmd_task(1, LOAD_MODE, 3, mode_reg3);
+            cmd_task(1, LOAD_MODE, 2, mode_reg2);
+            cmd_task(1, LOAD_MODE, 1, mode_reg1);
+            cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
+            cmd_task(1, PRECHARGE, 'bx, 1<<AP);           // Precharege ALL
+            cmd_task(1,   REFRESH, 'bx, 'bx);
+            cmd_task(1,   REFRESH, 'bx, 'bx);
+            cmd_task(1, LOAD_MODE, 0, mode_reg0);
+            cmd_task(1, LOAD_MODE, 1, mode_reg1 | 'h380); // OCD Default
+            cmd_task(1, LOAD_MODE, 1, mode_reg1);
+            cmd_task(0,       NOP, 'bx, 'bx);
+        end
+    endtask
+    
+    task reset_task;
+        integer i;
+        begin
+            // disable inputs
+            dq_in_valid          = 0;
+            dqs_in_valid        <= 0;
+            wdqs_cntr            = 0;
+            wdq_cntr             = 0;
+            for (i=0; i<36; i=i+1) begin
+                wdqs_pos_cntr[i]    <= 0;
+            end
+            b2b_write           <= 0;
+            // disable outputs
+            out_en               = 0;
+            dqs_n_en             = 0;
+            rdqs_en              = 0;
+            dq_out_en            = 0;
+            rdq_cntr             = 0;
+            dqs_out_en           = 0;
+            rdqs_cntr            = 0;
+            // disable ODT
+            odt_en               = 0;
+            odt_state            = 0;
+            // reset bank state
+            active_bank          = {`BANKS{1'b1}};
+            auto_precharge_bank  = 0;
+	        read_precharge_bank  = 0;
+	        write_precharge_bank = 0;
+            // require initialization sequence
+            init_done            = 0;
+            init_step            = 0;
+            init_mode_reg        = 0;
+            // reset DLL
+            dll_en               = 0;
+            dll_reset            = 0;
+            dll_locked           = 0;
+            ocd                  = 0;
+            // exit power down and self refresh
+            in_power_down        = 0;
+            in_self_refresh      = 0;
+            // clear pipelines
+            al_pipeline          = 0;
+            wr_pipeline          = 0;
+            rd_pipeline          = 0;
+            odt_pipeline         = 0;
+            // clear memory
+`ifdef MAX_MEM
+            for (i=0; i<=`MAX_SIZE; i=i+1) begin //erase memory ... one address at a time
+                memory[i] <= 'bx;
+            end
+`else
+            memory_used <= 0; //erase memory
+`endif
+            // clear maximum timing checks
+            tm_refresh <= 'bx;
+            for (i=0; i<`BANKS; i=i+1) begin
+                tm_bank_activate[i] <= 'bx;
+            end
+        end
+    endtask
+
+    task chk_err;
+        input samebank;
+        input [BA_BITS-1:0] bank;
+        input [3:0] fromcmd;
+        input [3:0] cmd;
+        reg err;
+    begin
+        // all matching case expressions will be evaluated
+        casex ({samebank, fromcmd, cmd})
+            {1'b0, LOAD_MODE, 4'b0xxx  } : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                       $display ("%m: at time %t ERROR:  tMRD violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, LOAD_MODE, 4'b100x  } : begin if (ck_cntr - ck_load_mode < TMRD)                                                                                 begin $display ("%m: at time %t INFO: Load Mode to Reset condition.", $time);                    init_done = 0; end end
+            {1'b0, REFRESH  , 4'b0xxx  } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                       $display ("%m: at time %t ERROR:  tRFC violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, REFRESH  , PWR_DOWN } : ; // 1 tCK
+            {1'b0, REFRESH  , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN)                                                                                 begin $display ("%m: at time %t INFO: Refresh to Reset condition", $time);                       init_done = 0; end end
+            {1'b0, PRECHARGE, 4'b000x  } : begin if ($time - tm_precharge_all < TRPA)                                                                                     $display ("%m: at time %t ERROR:  tRPA violation during %s", $time, cmd_string[cmd]);
+                                                 if ($time - tm_precharge < TRP)                                                                                          $display ("%m: at time %t ERROR:   tRP violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b1, PRECHARGE, PRECHARGE} : begin if (DEBUG && ($time - tm_precharge_all < TRPA))                                                                          $display ("%m: at time %t INFO: Precharge All interruption during %s", $time, cmd_string[cmd]);
+                                                 if (DEBUG && ($time - tm_bank_precharge[bank] < TRP))                                                                    $display ("%m: at time %t INFO: Precharge bank %d interruption during %s", $time, cmd_string[cmd], bank);  end
+            {1'b1, PRECHARGE, ACTIVATE } : begin if ($time - tm_precharge_all < TRPA)                                                                                     $display ("%m: at time %t ERROR:  tRPA violation during %s", $time, cmd_string[cmd]);
+                                                 if ($time - tm_bank_precharge[bank] < TRP)                                                                               $display ("%m: at time %t ERROR:   tRP violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, PRECHARGE, PWR_DOWN } : ; //1 tCK, can be concurrent with auto precharge
+            {1'b0, PRECHARGE, SELF_REF } : begin if (($time - tm_precharge_all < TRPA) || ($time - tm_precharge < TRP))                                             begin $display ("%m: at time %t INFO: Precharge to Reset condition", $time);                     init_done = 0; end end
+            {1'b0, ACTIVATE , REFRESH  } : begin if ($time - tm_activate < TRC)                                                                                           $display ("%m: at time %t ERROR:   tRC violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b1, ACTIVATE , PRECHARGE} : begin if (($time - tm_bank_activate[bank] > TRAS_MAX) && (active_bank[bank] === 1'b1))                                         $display ("%m: at time %t ERROR:  tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
+                                                 if ($time - tm_bank_activate[bank] < TRAS_MIN)                                                                           $display ("%m: at time %t ERROR:  tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
+            {1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD)                                                                                          $display ("%m: at time %t ERROR:  tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC)                                                                                $display ("%m: at time %t ERROR:   tRC violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b1, ACTIVATE , 4'b010x  } : ; // tRCD is checked outside this task
+            {1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK
+            {1'b1, WRITE    , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR))        $display ("%m: at time %t ERROR:   tWR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, WRITE    , WRITE    } : begin if (ck_cntr - ck_write < TCCD)                                                                                           $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, WRITE    , READ     } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency))           $display ("%m: at time %t ERROR:  tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, WRITE    , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && (
+                                                    |write_precharge_bank
+                                                 || (ck_cntr - ck_write_ap < 1)
+                                                 || (ck_cntr - ck_write < write_latency + burst_length/2 + 2) 
+                                                 || ($time - tm_write_end < TWTR)))                                                                                 begin $display ("%m: at time %t INFO: Write to Reset condition", $time);                         init_done = 0; end end
+            {1'b1, READ     , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP))       $display ("%m: at time %t ERROR:  tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, READ     , WRITE    } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency))                 $display ("%m: at time %t ERROR:  tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, READ     , READ     } : begin if (ck_cntr - ck_read < TCCD)                                                                                            $display ("%m: at time %t ERROR:  tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank);        end
+            {1'b0, READ     , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1))                           begin $display ("%m: at time %t INFO: Read to Reset condition", $time);                          init_done = 0; end end
+            {1'b0, PWR_DOWN , 4'b00xx  } : begin if (ck_cntr - ck_power_down < TXP)                                                                                       $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, PWR_DOWN , WRITE    } : begin if (ck_cntr - ck_power_down < TXP)                                                                                       $display ("%m: at time %t ERROR:   tXP violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, PWR_DOWN , READ     } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency)                                                               $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]);
+                                            else if (ck_cntr - ck_power_down < TXARD)                                                                                     $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, SELF_REF , 4'b00xx  } : begin if ($time - tm_self_refresh < TXSNR)                                                                                     $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, SELF_REF , WRITE    } : begin if ($time - tm_self_refresh < TXSNR)                                                                                     $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, SELF_REF , READ     } : begin if (ck_cntr - ck_self_refresh < TXSRD)                                                                                   $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]);                         end
+            {1'b0, 4'b100x  , 4'b100x  } : begin if (ck_cntr - ck_cke < TCKE)                                                                                       begin $display ("%m: at time %t ERROR:  tCKE violation on CKE", $time);                          init_done = 0; end end
+        endcase
+    end
+    endtask
+
+    task cmd_task;
+        input cke;
+        input [2:0] cmd;
+        input [BA_BITS-1:0] bank;
+        input [ADDR_BITS-1:0] addr;
+        reg [`BANKS:0] i;
+        integer j;
+        reg [`BANKS:0] tfaw_cntr;
+        reg [COL_BITS-1:0] col;
+        begin
+
+            // tRFC max check
+            if (!er_trfc_max && !in_self_refresh) begin
+                if ($time - tm_refresh > TRFC_MAX) begin
+                    $display ("%m: at time %t ERROR:  tRFC maximum violation during %s", $time, cmd_string[cmd]);
+                    er_trfc_max = 1;
+                end
+            end
+            if (cke) begin
+                if ((cmd < NOP) && ((cmd != PRECHARGE) || !addr[AP])) begin
+                    for (j=0; j<NOP; j=j+1) begin
+                        chk_err(1'b0, bank, j, cmd);
+                        chk_err(1'b1, bank, j, cmd);
+                    end
+                    chk_err(1'b0, bank, PWR_DOWN, cmd);
+                    chk_err(1'b0, bank, SELF_REF, cmd);
+                end
+
+                case (cmd)
+                    LOAD_MODE : begin
+                        if (|active_bank) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  All banks must be Precharged.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
+                            case (bank)
+                                0 : begin
+                                    // Burst Length
+                                    burst_length = 1<<addr[2:0];
+                                    if ((burst_length >= BL_MIN) && (burst_length <= BL_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
+                                    end
+                                    // Burst Order
+                                    burst_order = addr[3];
+                                    if (!burst_order) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
+                                    end else if (burst_order) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
+                                    end
+                                    // CAS Latency
+                                    cas_latency = addr[6:4];
+                                    read_latency = cas_latency + additive_latency;
+                                    write_latency = read_latency - 1;
+                                    if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
+                                    end
+                                    // Test Mode
+                                    if (!addr[7]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]);
+                                    end
+                                    // DLL Reset
+                                    dll_reset = addr[8];
+                                    if (!dll_reset) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
+                                    end else if (dll_reset) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
+                                        dll_locked = 0;
+                                        ck_dll_reset <= ck_cntr;
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
+                                    end
+                                    // Write Recovery
+                                    write_recovery  = addr[11:9] + 1;
+                                    if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
+                                    end
+                                    // Power Down Mode
+                                    low_power = addr[12];
+                                    if (!low_power) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank);
+                                    end else if (low_power) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
+                                    end
+                                end
+                                1 : begin
+                                    // DLL Enable
+                                    dll_en = !addr[0];
+                                    if (!dll_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (dll_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
+                                    end
+                                    // Output Drive Strength
+                                    if (!addr[1]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank);
+                                    end else if (addr[1]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]);
+                                    end
+                                    // ODT Rtt
+                                    odt_rtt = {addr[6], addr[2]};
+                                    if (odt_rtt == 2'b00) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
+                                        odt_en = 0;
+                                    end else if (odt_rtt == 2'b01) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank);
+                                        odt_en = 1;
+                                        tm_odt_en <= $time;
+                                    end else if (odt_rtt == 2'b10) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank);
+                                        odt_en = 1;
+                                        tm_odt_en <= $time;
+                                    end else if (odt_rtt == 2'b11) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank);
+                                        odt_en = 1;
+                                        tm_odt_en <= $time;
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt);
+                                        odt_en = 0;
+                                    end
+                                    // Additive Latency
+                                    additive_latency = addr[5:3];
+                                    read_latency = cas_latency + additive_latency;
+                                    write_latency = read_latency - 1;
+                                    if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
+                                    end
+                                    // OCD Program
+                                    ocd = addr[9:7];
+                                    if (ocd == 3'b000) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank);
+                                    end else if (ocd == 3'b111) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd);
+                                    end
+
+                                    // DQS_N Enable
+                                    dqs_n_en = !addr[10];
+                                    if (!dqs_n_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (dqs_n_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en);
+                                    end 
+                                    // RDQS Enable
+                                    rdqs_en = addr[11];
+                                    if (!rdqs_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (rdqs_en) begin
+`ifdef x8
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank);
+`else
+                                        $display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable.  RDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
+                                        rdqs_en = 0;
+`endif
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en);
+                                    end 
+                                    // Output Enable
+                                    out_en = !addr[12];
+                                    if (!out_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank);
+                                    end else if (out_en) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en);
+                                    end 
+                                end
+                                2 : begin
+                                    // High Temperature Self Refresh rate
+                                    if (!addr[7]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 1X (0C-85C)", $time, cmd_string[cmd], bank);
+                                    end else if (addr[7]) begin
+                                        if (DEBUG) $display ("%m: at time %t INFO: %s %d High Temperature Self Refresh rate = 2X (>85C)", $time, cmd_string[cmd], bank);
+                                    end else begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal High Temperature Self Refresh rate = %d", $time, cmd_string[cmd], bank, addr[7]);
+                                    end
+                                    if ((addr & ~(1<<7)) !== 0) begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
+                                    end
+                                end
+                                3 : begin
+                                    if (addr !== 0) begin
+                                        $display ("%m: at time %t ERROR: %s %d Illegal value.  Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
+                                    end
+                                end
+                            endcase
+                            init_mode_reg[bank] = 1;
+                            ck_load_mode <= ck_cntr;
+                        end
+                    end
+                    REFRESH : begin
+                        if (|active_bank) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  All banks must be Precharged.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
+                            er_trfc_max = 0;
+                            ref_cntr = ref_cntr + 1;
+                            tm_refresh <= $time;
+                        end
+                    end
+                    PRECHARGE : begin
+                        if (addr[AP]) begin
+                            // tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
+                            // the number of banks already open or closed.
+                            for (i=0; i<`BANKS; i=i+1) begin
+                                for (j=0; j<NOP; j=j+1) begin
+                                    chk_err(1'b0, i, j, cmd);
+                                    chk_err(1'b1, i, j, cmd);
+                                end
+                                chk_err(1'b0, i, PWR_DOWN, cmd);
+                                chk_err(1'b0, i, SELF_REF, cmd);
+                            end
+                            if (|auto_precharge_bank) begin
+                                $display ("%m: at time %t ERROR: %s All Failure.  Auto Precharge is scheduled.", $time, cmd_string[cmd]);
+                                if (STOP_ON_ERROR) $stop(0);
+                            end else begin
+                                if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
+                                active_bank = 0;
+                                tm_precharge_all <= $time;
+                            end
+                        end else begin
+                            // A PRECHARGE command is allowed if there is no open row in that bank (idle state) 
+                            // or if the previously open row is already in the process of precharging. 
+                            // However, the precharge period will be determined by the last PRECHARGE command issued to the bank.
+                            if (auto_precharge_bank[bank]) begin
+                                $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
+                                if (STOP_ON_ERROR) $stop(0);
+                            end else begin
+                                if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], bank);
+                                active_bank[bank] = 1'b0;
+                                tm_bank_precharge[bank] <= $time;
+                                tm_precharge <= $time;
+                            end
+                        end
+                    end
+                    ACTIVATE : begin
+                        if (`BANKS == 8) begin
+                            tfaw_cntr = 0;
+                            for (i=0; i<`BANKS; i=i+1) begin
+                                if ($time - tm_bank_activate[i] < TFAW) begin
+                                    tfaw_cntr = tfaw_cntr + 1;
+                                end
+                            end
+                            if (tfaw_cntr > 3) begin
+                                $display ("%m: at time %t ERROR:  tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
+                            end
+                        end
+
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (active_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (addr >= 1<<ROW_BITS) begin
+                                $display ("%m: at time %t WARNING: row = %h does not exist.  Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
+                            end
+                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
+                            active_bank[bank] = 1'b1;
+                            active_row[bank] = addr;
+                            tm_bank_activate[bank] <= $time;
+                            tm_activate <= $time;
+                        end
+                        
+                    end
+                    WRITE : begin
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (!active_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Activated.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (auto_precharge_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if ((ck_cntr - ck_write < burst_length/2) && (ck_cntr - ck_write)%2) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Illegal burst interruption.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (addr[AP]) begin
+                                auto_precharge_bank[bank] = 1'b1;
+                                write_precharge_bank[bank] = 1'b1;
+                            end
+                            col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
+                            if (col >= 1<<COL_BITS) begin
+                                $display ("%m: at time %t WARNING: col = %h does not exist.  Maximum col = %h", $time, col, (1<<COL_BITS)-1);
+                            end
+                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
+                            wr_pipeline[2*write_latency + 1]  = 1;
+                            ba_pipeline[2*write_latency + 1]  = bank;
+                            row_pipeline[2*write_latency + 1] = active_row[bank];
+                            col_pipeline[2*write_latency + 1] = col;
+                            ck_bank_write[bank] <= ck_cntr;
+                            ck_write <= ck_cntr;
+                        end
+                    end
+                    READ : begin
+                        if (!dll_locked)
+                            $display ("%m: at time %t WARNING: %s prior to DLL locked.  Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.", $time, cmd_string[cmd]);
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Initialization sequence is not complete.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (!active_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Bank %d must be Activated.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if (auto_precharge_bank[bank]) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else if ((ck_cntr - ck_read < burst_length/2) && (ck_cntr - ck_read)%2) begin
+                            $display ("%m: at time %t ERROR: %s Failure.  Illegal burst interruption.", $time, cmd_string[cmd]);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (addr[AP]) begin
+                                auto_precharge_bank[bank] = 1'b1;
+                                read_precharge_bank[bank] = 1'b1;
+                            end
+                            col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
+                            if (col >= 1<<COL_BITS) begin
+                                $display ("%m: at time %t WARNING: col = %h does not exist.  Maximum col = %h", $time, col, (1<<COL_BITS)-1);
+                            end
+                            if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
+                            rd_pipeline[2*read_latency - 1]  = 1;
+                            ba_pipeline[2*read_latency - 1]  = bank;
+                            row_pipeline[2*read_latency - 1] = active_row[bank];
+                            col_pipeline[2*read_latency - 1] = col;
+                            ck_bank_read[bank] <= ck_cntr;
+                            ck_read <= ck_cntr;
+                        end
+                    end
+                    NOP: begin
+                        if (in_power_down) begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
+                            in_power_down = 0;
+                            if (|active_bank & low_power) begin // slow exit active power down
+                                ck_slow_exit_pd <= ck_cntr;
+                            end
+                            ck_power_down <= ck_cntr;
+                        end
+                        if (in_self_refresh) begin
+                            if ($time - tm_cke < TISXR)
+                                $display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
+                            if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
+                            in_self_refresh = 0;
+                            ck_dll_reset <= ck_cntr;
+                            ck_self_refresh <= ck_cntr;
+                            tm_self_refresh <= $time;
+                            tm_refresh <= $time;
+                        end
+                    end
+                endcase
+                if ((prev_cke !== 1) && (cmd !== NOP)) begin
+                    $display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
+                end
+                if (!init_done) begin
+                    case (init_step)
+                        0 : begin
+                            if ($time < 200000000) 
+                                $display ("%m: at time %t WARNING: 200 us is required before CKE goes active.", $time);
+//                          if (cmd_chk + 200000000 > $time)
+//                              $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time);
+                            init_step = init_step + 1;
+                        end
+                        1 : if (dll_en)        init_step = init_step + 1;
+                        2 : begin
+                            if (&init_mode_reg && dll_reset) begin
+                                active_bank = {`BANKS{1'b1}};   // require Precharge All or bank Precharges
+                                ref_cntr = 0;                   // require refresh
+                                init_step = init_step + 1;
+                            end
+                        end
+                        3 : if (ref_cntr == 2) begin
+                            init_step = init_step + 1;
+                        end
+                        4 : if (!dll_reset)    init_step = init_step + 1;
+                        5 : if (ocd == 3'b111) init_step = init_step + 1;
+                        6 : begin
+                            if (ocd == 3'b000) begin
+                                if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
+                                init_done = 1;
+                            end
+                        end
+                    endcase
+                end
+            end else if (prev_cke) begin
+                if ((!init_done) && (init_step > 1)) begin
+                    $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
+                    if (STOP_ON_ERROR) $stop(0);
+                end
+                case (cmd)
+                    REFRESH : begin
+                        for (j=0; j<NOP; j=j+1) begin
+                            chk_err(1'b0, bank, j, SELF_REF);
+                        end
+                        chk_err(1'b0, bank, PWR_DOWN, SELF_REF);
+                        chk_err(1'b0, bank, SELF_REF, SELF_REF);
+                        if (|active_bank) begin
+                            $display ("%m: at time %t ERROR: Self Refresh Failure.  All banks must be Precharged.", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                            init_done = 0;
+                        end else if (odt_en && odt_state) begin
+                            $display ("%m: at time %t ERROR: ODT must be off prior to entering Self Refresh", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                            init_done = 0;
+                        end else if (!init_done) begin
+                            $display ("%m: at time %t ERROR: Self Refresh Failure.  Initialization sequence is not complete.", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
+                            in_self_refresh = 1;
+                            dll_locked = 0;
+                        end
+                    end
+                    NOP : begin
+                        // entering slow_exit or precharge power down and tANPD has not been satisfied
+                        if ((low_power || (active_bank == 0)) && (ck_cntr - ck_odt < TANPD))
+                            $display ("%m: at time %t WARNING: tANPD violation during %s.  Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
+                        for (j=0; j<NOP; j=j+1) begin
+                            chk_err(1'b0, bank, j, PWR_DOWN);
+                        end
+                        chk_err(1'b0, bank, PWR_DOWN, PWR_DOWN);
+                        chk_err(1'b0, bank, SELF_REF, PWR_DOWN);
+
+                        if (!init_done) begin
+                            $display ("%m: at time %t ERROR: Power Down Failure.  Initialization sequence is not complete.", $time);
+                            if (STOP_ON_ERROR) $stop(0);
+                        end else begin
+                            if (DEBUG) begin
+                                if (|active_bank) begin
+                                    $display ("%m: at time %t INFO: Active Power Down Enter", $time);
+                                end else begin
+                                    $display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
+                                end
+                            end
+                            in_power_down = 1;
+                        end
+                    end
+                    default : begin
+                        $display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
+                        init_done = 0;
+                    end
+                endcase
+                if (!init_done) begin
+                    if (DEBUG) $display ("%m: at time %t WARNING: Reset has occurred.  Device must be re-initialized.", $time);
+                    reset_task;
+                end
+            end
+            prev_cke  = cke;
+        end
+    endtask
+
+    task data_task;
+        reg [BA_BITS-1:0] bank;
+        reg [ROW_BITS-1:0] row;
+        reg [COL_BITS-1:0] col;
+        integer i;
+        integer j;
+        begin
+
+            if (diff_ck) begin
+                for (i=0; i<36; i=i+1) begin
+                    if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
+                        $display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    if (check_write_dqs_high[i])
+                        $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/18], i%18);
+                end
+                check_write_dqs_high <= 0;
+            end else begin
+                for (i=0; i<36; i=i+1) begin
+                    if (dll_locked && dq_in_valid && (i % 18 < DQS_BITS)) begin // Only check valid DQS group
+                        tm_tdqss = abs_value($itor(tm_ck_pos) - tm_dqss_pos[i]);
+                        //$display ("at time %t, tm_tdqss = %0d, tm_ck_pos = %0d, tm_dqss_pos [%0d] = %0d", $time, tm_tdqss, tm_ck_pos, i, tm_dqss_pos[i]);
+                        if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
+                            $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/18], i%18); 
+                    end
+                    if (check_write_dqs_low[i])
+                        $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/18], i%18);
+                end
+                check_write_preamble <= 0;
+                check_write_postamble <= 0;
+                check_write_dqs_low <= 0;
+            end
+
+            if (wr_pipeline[0] || rd_pipeline[0]) begin
+                bank = ba_pipeline[0];
+                row = row_pipeline[0];
+                col = col_pipeline[0];
+                burst_cntr = 0;
+                memory_read(bank, row, col, memory_data);
+            end
+
+            // burst counter
+            if (burst_cntr < burst_length) begin
+                burst_position = col ^ burst_cntr;
+                if (!burst_order) begin
+                    burst_position[BO_BITS-1:0] = col + burst_cntr;
+                end
+                burst_cntr = burst_cntr + 1;
+            end
+
+            // write dqs counter
+            if (wr_pipeline[WDQS_PRE + 1]) begin
+                wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1;
+            end
+            // write dqs
+            if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble
+                check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+            end
+            if (wdqs_cntr > 1) begin  // write data
+                if ((wdqs_cntr - WDQS_PST)%2) begin
+                    check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+                end else begin
+                    check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+                end
+            end
+            if (wdqs_cntr == WDQS_PST) begin // write postamble
+                check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<18) | {DQS_BITS{1'b1}};
+            end 
+            if (wdqs_cntr > 0) begin
+                wdqs_cntr = wdqs_cntr - 1;
+            end
+
+            // write dq
+            if (dq_in_valid) begin // write data
+                bit_mask = 0;
+                if (diff_ck) begin
+                    for (i=0; i<DM_BITS; i=i+1) begin
+                        bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
+                    end
+                    memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
+                end else begin
+                    for (i=0; i<DM_BITS; i=i+1) begin
+                        bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
+                    end
+                    memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
+                end
+                dq_temp = memory_data>>(burst_position*DQ_BITS);
+                if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
+                if (burst_cntr%BL_MIN == 0) begin
+                    memory_write(bank, row, col, memory_data);
+                end
+            end
+            if (wr_pipeline[1]) begin
+                wdq_cntr = burst_length;
+            end
+            if (wdq_cntr > 0) begin
+                wdq_cntr = wdq_cntr - 1;
+                dq_in_valid = 1'b1;
+            end else begin
+                dq_in_valid = 1'b0;
+                dqs_in_valid <= 1'b0;
+                for (i=0; i<36; i=i+1) begin
+                    wdqs_pos_cntr[i] <= 0;
+                end
+            end
+            if (wr_pipeline[0]) begin
+                b2b_write <= 1'b0;
+            end
+            if (wr_pipeline[2]) begin
+                if (dqs_in_valid) begin
+                    b2b_write <= 1'b1;
+                end
+                dqs_in_valid <= 1'b1;
+            end
+            // read dqs enable counter
+            if (rd_pipeline[RDQSEN_PRE]) begin
+                rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1;
+            end
+            if (rdqsen_cntr > 0) begin
+                rdqsen_cntr = rdqsen_cntr - 1;
+                dqs_out_en = 1'b1;
+            end else begin
+                dqs_out_en = 1'b0;
+            end
+            
+            // read dqs counter
+            if (rd_pipeline[RDQS_PRE]) begin
+                rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1;
+            end
+            // read dqs
+            if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble
+                dqs_out = 1'b0;
+            end else if (rdqs_cntr > RDQS_PST) begin // read data
+                dqs_out = rdqs_cntr - RDQS_PST;
+            end else if (rdqs_cntr > 0) begin // read postamble
+                dqs_out = 1'b0;
+            end else begin
+                dqs_out = 1'b1;
+            end
+            if (rdqs_cntr > 0) begin
+                rdqs_cntr = rdqs_cntr - 1;
+            end
+
+            // read dq enable counter
+            if (rd_pipeline[RDQEN_PRE]) begin
+                rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST;
+            end
+            if (rdqen_cntr > 0) begin
+                rdqen_cntr = rdqen_cntr - 1;
+                dq_out_en = 1'b1;
+            end else begin
+                dq_out_en = 1'b0;
+            end
+            // read dq
+            if (rd_pipeline[0]) begin
+                rdq_cntr = burst_length;
+            end
+            if (rdq_cntr > 0) begin // read data
+                dq_temp = memory_data>>(burst_position*DQ_BITS);
+                dq_out = dq_temp;
+                if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
+                rdq_cntr = rdq_cntr - 1;
+            end else begin
+                dq_out = {DQ_BITS{1'b1}};
+            end
+
+            // delay signals prior to output
+            if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin
+                for (i=0; i<DQS_BITS; i=i+1) begin
+                    // DQSCK requirements
+                    // 1.) less than tDQSCK
+                    // 2.) greater than -tDQSCK
+                    // 3.) cannot change more than tQHS + tDQSQ from previous DQS edge
+                    dqsck_max = TDQSCK;
+                    if (dqsck_max > dqsck[i] + TQHS + TDQSQ) begin
+                        dqsck_max = dqsck[i] + TQHS + TDQSQ;
+                    end
+                    dqsck_min = -1*TDQSCK;
+                    if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin
+                        dqsck_min = dqsck[i] - TQHS - TDQSQ;
+                    end
+
+                    // DQSQ requirements
+                    // 1.) less than tAC - DQSCK
+                    // 2.) less than tDQSQ
+                    // 3.) greater than -tAC
+                    // 4.) greater than tQH from previous DQS edge
+                    dqsq_min = -1*TAC;
+                    if (dqsq_min < dqsck[i] - TQHS) begin
+                        dqsq_min = dqsck[i] - TQHS;
+                    end
+                    if (dqsck_min == dqsck_max) begin
+                        dqsck[i] = dqsck_min;
+                    end else begin
+                        dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
+                    end
+                    dqsq_max = TAC;
+                    if (dqsq_max > TDQSQ + dqsck[i]) begin
+                        dqsq_max = TDQSQ + dqsck[i];
+                    end
+
+                    dqs_out_en_dly[i] <= #(tck_avg/2.0 + ($random % TAC)) dqs_out_en;
+                    dqs_out_dly[i]    <= #(tck_avg/2.0 + dqsck[i]) dqs_out;
+                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
+                        if (dq_out_en) begin // tLZ2
+                            dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, -2*TAC, dqsq_max)) dq_out_en;
+                        end else begin // tHZ
+                            dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + ($random % TAC)) dq_out_en;
+                        end
+                        if (dqsq_min == dqsq_max) begin
+                            dq_out_dly   [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
+                        end else begin
+                            dq_out_dly   [i*`DQ_PER_DQS + j] <= #(tck_avg/2.0 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
+                        end
+                    end
+                end
+            end else begin
+                out_delay = tck_avg/2.0;
+                dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
+                dqs_out_dly    <= #(out_delay) {DQS_BITS{dqs_out   }};
+                dq_out_en_dly  <= #(out_delay) {DQ_BITS {dq_out_en }};
+                dq_out_dly     <= #(out_delay) {DQ_BITS {dq_out    }};
+            end
+        end
+    endtask
+
+    always @(diff_ck) begin : main
+        integer i;
+
+        if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
+            $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
+        data_task;
+        if (diff_ck) begin
+            // check setup of command signals
+            if ($time > TIS) begin
+                if ($time - tm_cke < TIS) 
+                    $display ("%m: at time %t ERROR:   tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
+                if (cke_in) begin
+                    for (i=0; i<22; i=i+1) begin
+                        if ($time - tm_cmd_addr[i] < TIS) 
+                            $display ("%m: at time %t ERROR:   tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
+                    end
+                end
+            end
+
+            // update current state
+            if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin
+                // check CL value against the clock frequency
+                if (cas_latency*tck_avg < CL_TIME)
+                    $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
+                // check WR value against the clock frequency
+                if (write_recovery*tck_avg < TWR)
+                    $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
+                dll_locked = 1;
+            end
+            if (|auto_precharge_bank) begin
+                for (i=0; i<`BANKS; i=i+1) begin
+                    // Write with Auto Precharge Calculation
+                    // 1.  Meet minimum tRAS requirement
+                    // 2.  Write Latency PLUS BL/2 cycles PLUS WR after Write command
+                    if (write_precharge_bank[i]
+                        && ($time - tm_bank_activate[i] >= TRAS_MIN)
+                        && (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery)) begin
+
+                        if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
+                        write_precharge_bank[i] = 0;
+                        active_bank[i] = 0;
+                        auto_precharge_bank[i] = 0;
+                        ck_write_ap = ck_cntr;
+                        tm_bank_precharge[i] = $time;
+                        tm_precharge = $time;
+                    end
+                    // Read with Auto Precharge Calculation
+                    // 1.  Meet minimum tRAS requirement
+                    // 2.  Additive Latency plus BL/2 cycles after Read command
+                    // 3.  tRTP after the last 4-bit prefetch
+                    if (read_precharge_bank[i]
+                        && ($time - tm_bank_activate[i] >= TRAS_MIN) 
+                        && (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin
+
+                        read_precharge_bank[i] = 0;
+                        // In case the internal precharge is pushed out by tRTP, tRP starts at the point where
+                        // the internal precharge happens (not at the next rising clock edge after this event).
+                        if ($time - tm_bank_read_end[i] < TRTP) begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
+                            active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
+                            auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
+                            tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
+                            tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
+                            active_bank[i] = 0;
+                            auto_precharge_bank[i] = 0;
+                            tm_bank_precharge[i] = $time;
+                            tm_precharge = $time;
+                        end
+                    end
+                end
+            end
+
+            // respond to incoming command
+            if (cke_in ^ prev_cke) begin
+                ck_cke <= ck_cntr;
+            end
+
+            cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
+            if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
+                al_pipeline[2*additive_latency] = 1'b1;
+            end
+            if (al_pipeline[0]) begin
+                // check tRCD after additive latency
+                if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin
+                    if (rd_pipeline[2*cas_latency - 1]) begin
+                        $display ("%m: at time %t ERROR:  tRCD violation during %s", $time, cmd_string[READ]);
+                    end else begin
+                        $display ("%m: at time %t ERROR:  tRCD violation during %s", $time, cmd_string[WRITE]);
+                    end
+                end
+                // check tWTR after additive latency
+                if (rd_pipeline[2*cas_latency - 1]) begin
+                    if ($time - tm_write_end < TWTR)
+                        $display ("%m: at time %t ERROR:  tWTR violation during %s", $time, cmd_string[READ]);
+                end
+            end
+            if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin
+                tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time;
+            end
+            for (i=0; i<`BANKS; i=i+1) begin
+                if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
+                    tm_bank_write_end[i] <= $time;
+                    tm_write_end <= $time;
+                end
+            end
+
+            // clk pin is disabled during self refresh
+            if (!in_self_refresh) begin
+                tjit_cc_time = $time - tm_ck_pos - tck_i;
+                tck_i   = $time - tm_ck_pos;
+                tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
+                tck_avg = tck_avg + tck_i/$itor(TDLLK);
+                tck_sample[ck_cntr%TDLLK] = tck_i;
+                tjit_per_rtime = tck_i - tck_avg;
+
+                if (dll_locked) begin
+                    // check accumulated error
+                    terr_nper_rtime = 0;
+                    for (i=0; i<50; i=i+1) begin
+                        terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
+                        terr_nper_rtime = abs_value(terr_nper_rtime);
+                        case (i)
+                                  0 :;
+                                  1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
+                                  2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
+                                  3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
+                                  4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
+                          5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER);
+                            default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER);
+                        endcase
+                    end
+
+                    // check tCK min/max/jitter
+                    if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) 
+                        $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
+                    if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) 
+                        $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
+                    if (TCK_MIN - tck_avg >= 1.0)
+                        $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
+                    if (tck_avg - TCK_MAX >= 1.0) 
+                        $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
+                    if (tm_ck_pos + TCK_MIN - TJIT_PER > $time) 
+                        $display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time);
+                    if (tm_ck_pos + TCK_MAX + TJIT_PER < $time) 
+                        $display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER);
+
+                    // check tCL
+                    if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time) 
+                        $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time);
+                    if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time) 
+                        $display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY);
+                    if (tcl_avg < TCL_MIN*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg);
+                    if (tcl_avg > TCL_MAX*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg);
+                end
+
+                // calculate the tch avg jitter
+                tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
+                tch_avg = tch_avg + tch_i/$itor(TDLLK);
+                tch_sample[ck_cntr%TDLLK] = tch_i;
+
+                // update timers/counters
+                tcl_i <= $time - tm_ck_neg;
+            end
+
+            prev_odt <= odt_in;
+            // update timers/counters
+            ck_cntr <= ck_cntr + 1;
+            tm_ck_pos <= $time;
+        end else begin
+            // clk pin is disabled during self refresh
+            if (!in_self_refresh) begin
+                if (dll_locked) begin
+                    if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time) 
+                        $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time);
+                    if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time) 
+                        $display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY);
+                    if (tch_avg < TCH_MIN*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg);
+                    if (tch_avg > TCH_MAX*tck_avg) 
+                        $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg);
+                end
+
+                // calculate the tcl avg jitter
+                tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
+                tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
+                tcl_sample[ck_cntr%TDLLK] = tcl_i;
+
+                // update timers/counters
+                tch_i <= $time - tm_ck_pos;
+            end
+            tm_ck_neg <= $time;
+        end
+
+        // on die termination
+        if (odt_en) begin
+            // clk pin is disabled during self refresh
+            if (!in_self_refresh && diff_ck) begin
+                if ($time - tm_odt < TIS) begin
+                    $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
+                end
+                if (prev_odt ^ odt_in) begin
+                    if (!dll_locked)
+                        $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
+                    if (odt_in && ($time - tm_odt_en  < TMOD))
+                        $display ("%m: at time %t ERROR:  tMOD violation during ODT transition", $time);
+                    if ($time - tm_self_refresh < TXSNR)
+                        $display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time);
+                    if (in_self_refresh)
+                        $display ("%m: at time %t ERROR:  Illegal ODT transition during Self Refresh.", $time);
+
+                    // async ODT mode applies:
+                    // 1.) during active power down with slow exit
+                    // 2.) during precharge power down
+                    // 3.) if tANPD has not been satisfied
+                    // 4.) until tAXPD has been satisfied
+                    if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin
+                        if (ck_cntr - ck_slow_exit_pd < TAXPD)
+                            $display ("%m: at time %t WARNING: tAXPD violation during ODT transition.  Synchronous or asynchronous change in termination resistance is possible.", $time);
+                        if (odt_in) begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1);
+                            odt_state <= #(TAONPD) 1'b1;
+                        end else begin
+                            if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0);
+                            odt_state <= #(TAOFPD) 1'b0;
+                        end
+                    // sync ODT mode applies:
+                    // 1.) during normal operation
+                    // 2.) during active power down with fast exit
+                    end else begin
+                        if (odt_in) begin
+                            i = TAOND*2;
+                            odt_pipeline[i] = 1'b1;
+                        end else begin
+                            i = TAOFD*2;
+                            odt_pipeline[i] = 1'b1;
+                        end
+                    end
+                    ck_odt <= ck_cntr;
+                end
+            end
+            if (odt_pipeline[0]) begin
+                odt_state = ~odt_state;
+                if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state);
+            end
+        end
+
+        // shift pipelines
+        if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
+            al_pipeline = al_pipeline>>1;
+            wr_pipeline = wr_pipeline>>1;
+            rd_pipeline = rd_pipeline>>1;
+            for (i=0; i<`MAX_PIPE; i=i+1) begin
+                ba_pipeline[i] = ba_pipeline[i+1];
+                row_pipeline[i] = row_pipeline[i+1];
+                col_pipeline[i] = col_pipeline[i+1];
+            end
+        end
+        if (|odt_pipeline) begin
+            odt_pipeline = odt_pipeline>>1;
+        end
+    end
+
+    // receiver(s)
+    task dqs_even_receiver;
+        input [4:0] i;
+        reg [71:0] bit_mask;
+        begin
+            bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
+            if (dqs_even[i]) begin
+                if (rdqs_en) begin // rdqs disables dm
+                    dm_in_pos[i] = 1'b0;
+                end else begin
+                    dm_in_pos[i] = dm_in[i];
+                end
+                dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
+            end
+        end
+    endtask
+
+    always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
+    always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
+    always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
+    always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
+    always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
+    always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
+    always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
+    always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
+    always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
+    always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
+    always @(posedge dqs_even[10]) dqs_even_receiver(10);
+    always @(posedge dqs_even[11]) dqs_even_receiver(11);
+    always @(posedge dqs_even[12]) dqs_even_receiver(12);
+    always @(posedge dqs_even[13]) dqs_even_receiver(13);
+    always @(posedge dqs_even[14]) dqs_even_receiver(14);
+    always @(posedge dqs_even[15]) dqs_even_receiver(15);
+    always @(posedge dqs_even[16]) dqs_even_receiver(16);
+    always @(posedge dqs_even[17]) dqs_even_receiver(17);
+
+    task dqs_odd_receiver;
+        input [4:0] i;
+        reg [71:0] bit_mask;
+        begin
+            bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
+            if (dqs_odd[i]) begin
+                if (rdqs_en) begin // rdqs disables dm
+                    dm_in_neg[i] = 1'b0;
+                end else begin
+                    dm_in_neg[i] = dm_in[i];
+                end
+                dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
+            end
+        end
+    endtask
+
+    always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
+    always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
+    always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
+    always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
+    always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
+    always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
+    always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
+    always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
+    always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
+    always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
+    always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
+    always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
+    always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
+    always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
+    always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
+    always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
+    always @(posedge dqs_odd[16]) dqs_odd_receiver(16);
+    always @(posedge dqs_odd[17]) dqs_odd_receiver(17);
+ 
+    // Processes to check hold and pulse width of control signals
+    always @(cke_in) begin
+        if ($time > TIH) begin
+            if ($time - tm_ck_pos < TIH) 
+                $display ("%m: at time %t ERROR:  tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
+        end
+        if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg)))
+            $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time);
+        tm_cke = $time;
+    end
+    always @(odt_in) begin
+        if (odt_en && !in_self_refresh) begin
+            if ($time - tm_ck_pos < TIH) 
+                $display ("%m: at time %t ERROR:  tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
+            if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg)))
+                $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time);
+        end
+        tm_odt = $time;
+    end
+
+    task cmd_addr_timing_check;
+    input i;
+    reg [4:0] i;
+    begin
+        if (prev_cke) begin
+            if ((i == 0) && ($time - tm_ck_pos < TIH))                      // Always check tIH for CS#
+                $display ("%m: at time %t ERROR:  tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
+            if ((i > 0) && (cs_n_in == 1'b0) && ($time - tm_ck_pos < TIH))  // Only check tIH for cmd_addr if CS# low
+                $display ("%m: at time %t ERROR:  tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
+            if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg)))
+                $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time);
+        end
+        tm_cmd_addr[i] = $time;
+    end
+    endtask
+
+    always @(cs_n_in    ) cmd_addr_timing_check( 0);
+    always @(ras_n_in   ) cmd_addr_timing_check( 1);
+    always @(cas_n_in   ) cmd_addr_timing_check( 2);
+    always @(we_n_in    ) cmd_addr_timing_check( 3);
+    always @(ba_in  [ 0]) cmd_addr_timing_check( 4);
+    always @(ba_in  [ 1]) cmd_addr_timing_check( 5);
+    always @(ba_in  [ 2]) cmd_addr_timing_check( 6);
+    always @(addr_in[ 0]) cmd_addr_timing_check( 7);
+    always @(addr_in[ 1]) cmd_addr_timing_check( 8);
+    always @(addr_in[ 2]) cmd_addr_timing_check( 9);
+    always @(addr_in[ 3]) cmd_addr_timing_check(10);
+    always @(addr_in[ 4]) cmd_addr_timing_check(11);
+    always @(addr_in[ 5]) cmd_addr_timing_check(12);
+    always @(addr_in[ 6]) cmd_addr_timing_check(13);
+    always @(addr_in[ 7]) cmd_addr_timing_check(14);
+    always @(addr_in[ 8]) cmd_addr_timing_check(15);
+    always @(addr_in[ 9]) cmd_addr_timing_check(16);
+    always @(addr_in[10]) cmd_addr_timing_check(17);
+    always @(addr_in[11]) cmd_addr_timing_check(18);
+    always @(addr_in[12]) cmd_addr_timing_check(19);
+    always @(addr_in[13]) cmd_addr_timing_check(20);
+    always @(addr_in[14]) cmd_addr_timing_check(21);
+    always @(addr_in[15]) cmd_addr_timing_check(22);
+
+    // Processes to check setup and hold of data signals
+    task dm_timing_check;
+    input i;
+    reg [4:0] i;
+    begin
+        if (dqs_in_valid) begin
+            if ($time - tm_dqs[i] < TDH) 
+                $display ("%m: at time %t ERROR:   tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
+            if (check_dm_tdipw[i]) begin
+                if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg)))
+                    $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time);
+            end
+        end
+        check_dm_tdipw[i] <= 1'b0;
+        tm_dm[i] = $time;
+    end
+    endtask
+
+    always @(dm_in[ 0]) dm_timing_check( 0);
+    always @(dm_in[ 1]) dm_timing_check( 1);
+    always @(dm_in[ 2]) dm_timing_check( 2);
+    always @(dm_in[ 3]) dm_timing_check( 3);
+    always @(dm_in[ 4]) dm_timing_check( 4);
+    always @(dm_in[ 5]) dm_timing_check( 5);
+    always @(dm_in[ 6]) dm_timing_check( 6);
+    always @(dm_in[ 7]) dm_timing_check( 7);
+    always @(dm_in[ 8]) dm_timing_check( 8);
+    always @(dm_in[ 9]) dm_timing_check( 9);
+    always @(dm_in[10]) dm_timing_check(10);
+    always @(dm_in[11]) dm_timing_check(11);
+    always @(dm_in[12]) dm_timing_check(12);
+    always @(dm_in[13]) dm_timing_check(13);
+    always @(dm_in[14]) dm_timing_check(14);
+    always @(dm_in[15]) dm_timing_check(15);
+    always @(dm_in[16]) dm_timing_check(16);
+    always @(dm_in[17]) dm_timing_check(17);
+
+    task dq_timing_check;
+    input i;
+    reg [6:0] i;
+    begin
+        if (dqs_in_valid) begin
+            if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH) 
+                $display ("%m: at time %t ERROR:   tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
+            if (check_dq_tdipw[i]) begin
+                if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg)))
+                    $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time);
+            end
+        end
+        check_dq_tdipw[i] <= 1'b0;
+        tm_dq[i] = $time;
+    end 
+    endtask
+
+    always @(dq_in[ 0]) dq_timing_check( 0);
+    always @(dq_in[ 1]) dq_timing_check( 1);
+    always @(dq_in[ 2]) dq_timing_check( 2);
+    always @(dq_in[ 3]) dq_timing_check( 3);
+    always @(dq_in[ 4]) dq_timing_check( 4);
+    always @(dq_in[ 5]) dq_timing_check( 5);
+    always @(dq_in[ 6]) dq_timing_check( 6);
+    always @(dq_in[ 7]) dq_timing_check( 7);
+    always @(dq_in[ 8]) dq_timing_check( 8);
+    always @(dq_in[ 9]) dq_timing_check( 9);
+    always @(dq_in[10]) dq_timing_check(10);
+    always @(dq_in[11]) dq_timing_check(11);
+    always @(dq_in[12]) dq_timing_check(12);
+    always @(dq_in[13]) dq_timing_check(13);
+    always @(dq_in[14]) dq_timing_check(14);
+    always @(dq_in[15]) dq_timing_check(15);
+    always @(dq_in[16]) dq_timing_check(16);
+    always @(dq_in[17]) dq_timing_check(17);
+    always @(dq_in[18]) dq_timing_check(18);
+    always @(dq_in[19]) dq_timing_check(19);
+    always @(dq_in[20]) dq_timing_check(20);
+    always @(dq_in[21]) dq_timing_check(21);
+    always @(dq_in[22]) dq_timing_check(22);
+    always @(dq_in[23]) dq_timing_check(23);
+    always @(dq_in[24]) dq_timing_check(24);
+    always @(dq_in[25]) dq_timing_check(25);
+    always @(dq_in[26]) dq_timing_check(26);
+    always @(dq_in[27]) dq_timing_check(27);
+    always @(dq_in[28]) dq_timing_check(28);
+    always @(dq_in[29]) dq_timing_check(29);
+    always @(dq_in[30]) dq_timing_check(30);
+    always @(dq_in[31]) dq_timing_check(31);
+    always @(dq_in[32]) dq_timing_check(32);
+    always @(dq_in[33]) dq_timing_check(33);
+    always @(dq_in[34]) dq_timing_check(34);
+    always @(dq_in[35]) dq_timing_check(35);
+    always @(dq_in[36]) dq_timing_check(36);
+    always @(dq_in[37]) dq_timing_check(37);
+    always @(dq_in[38]) dq_timing_check(38);
+    always @(dq_in[39]) dq_timing_check(39);
+    always @(dq_in[40]) dq_timing_check(40);
+    always @(dq_in[41]) dq_timing_check(41);
+    always @(dq_in[42]) dq_timing_check(42);
+    always @(dq_in[43]) dq_timing_check(43);
+    always @(dq_in[44]) dq_timing_check(44);
+    always @(dq_in[45]) dq_timing_check(45);
+    always @(dq_in[46]) dq_timing_check(46);
+    always @(dq_in[47]) dq_timing_check(47);
+    always @(dq_in[48]) dq_timing_check(48);
+    always @(dq_in[49]) dq_timing_check(49);
+    always @(dq_in[50]) dq_timing_check(50);
+    always @(dq_in[51]) dq_timing_check(51);
+    always @(dq_in[52]) dq_timing_check(52);
+    always @(dq_in[53]) dq_timing_check(53);
+    always @(dq_in[54]) dq_timing_check(54);
+    always @(dq_in[55]) dq_timing_check(55);
+    always @(dq_in[56]) dq_timing_check(56);
+    always @(dq_in[57]) dq_timing_check(57);
+    always @(dq_in[58]) dq_timing_check(58);
+    always @(dq_in[59]) dq_timing_check(59);
+    always @(dq_in[60]) dq_timing_check(60);
+    always @(dq_in[61]) dq_timing_check(61);
+    always @(dq_in[62]) dq_timing_check(62);
+    always @(dq_in[63]) dq_timing_check(63);
+    always @(dq_in[64]) dq_timing_check(64);
+    always @(dq_in[65]) dq_timing_check(65);
+    always @(dq_in[66]) dq_timing_check(66);
+    always @(dq_in[67]) dq_timing_check(67);
+    always @(dq_in[68]) dq_timing_check(68);
+    always @(dq_in[69]) dq_timing_check(69);
+    always @(dq_in[70]) dq_timing_check(70);
+    always @(dq_in[71]) dq_timing_check(71);
+
+    task dqs_pos_timing_check;
+    input i;
+    reg [5:0] i;
+    reg [3:0] j;
+    begin
+        if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<18)) begin
+            if (dqs_in[i] ^ prev_dqs_in[i]) begin
+                if (dll_locked) begin
+                    if (check_write_preamble[i]) begin
+                        if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg))
+                            $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/18], i%18);
+                    end else if (check_write_postamble[i]) begin
+                        if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
+                            $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    end else begin
+                        if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
+                            $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    end
+                end
+                if ($time - tm_dm[i%18] < TDS) 
+                    $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i,  tm_dm[i%18] + TDS - $time);
+                if (!dq_out_en) begin
+                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
+                        if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) 
+                            $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
+                        check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
+                    end
+                end
+                if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin
+                    wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
+                end else begin
+                    wdqs_pos_cntr[i] <= 1;
+                end
+                check_dm_tdipw[i%18] <= 1'b1;
+                check_write_preamble[i] <= 1'b0;
+                check_write_postamble[i] <= 1'b0;
+                check_write_dqs_low[i] <= 1'b0;
+                tm_dqs[i%18] <= $time;
+            end else begin
+                $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
+            end
+        end
+        tm_dqss_pos[i] <= $time;
+        tm_dqs_pos[i] = $time;
+        prev_dqs_in[i] <= dqs_in[i];
+    end
+    endtask
+
+    always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
+    always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
+    always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
+    always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
+    always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
+    always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
+    always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
+    always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
+    always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
+    always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
+    always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
+    always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
+    always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
+    always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
+    always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
+    always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
+    always @(posedge dqs_in[16]) dqs_pos_timing_check(16);
+    always @(posedge dqs_in[17]) dqs_pos_timing_check(17);
+    always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
+    always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
+    always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
+    always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
+    always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
+    always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
+    always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
+    always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
+    always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
+    always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
+    always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
+    always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
+    always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
+    always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
+    always @(negedge dqs_in[32]) dqs_neg_timing_check(32);
+    always @(negedge dqs_in[33]) dqs_neg_timing_check(33);
+    always @(negedge dqs_in[34]) dqs_neg_timing_check(34);
+    always @(negedge dqs_in[35]) dqs_neg_timing_check(35);
+
+    task dqs_neg_timing_check;
+    input i;
+    reg [5:0] i;
+    reg [3:0] j;
+    begin
+        if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i] && (dqs_n_en || i < 18)) begin
+            if (dqs_in[i] ^ prev_dqs_in[i]) begin
+                if (dll_locked) begin
+                    if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
+                        $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/18], i%18);
+                    if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
+                        $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/18], i%18); 
+                end
+                if ($time - tm_dm[i%18] < TDS) 
+                    $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i,  tm_dm[i%18] + TDS - $time);
+                if (!dq_out_en) begin
+                    for (j=0; j<`DQ_PER_DQS; j=j+1) begin
+                        if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) 
+                            $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
+                        check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
+                    end
+                end
+                check_dm_tdipw[i%18] <= 1'b1;
+                check_write_dqs_high[i] <= 1'b0;
+                tm_dqs[i%18] <= $time;
+            end else begin
+                $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/18], i%18);
+            end
+        end
+        tm_dqs_neg[i] = $time;
+        prev_dqs_in[i] <= dqs_in[i];
+    end
+    endtask
+
+    always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
+    always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
+    always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
+    always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
+    always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
+    always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
+    always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
+    always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
+    always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
+    always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
+    always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
+    always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
+    always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
+    always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
+    always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
+    always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
+    always @(negedge dqs_in[16]) dqs_neg_timing_check(16);
+    always @(negedge dqs_in[17]) dqs_neg_timing_check(17);
+    always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
+    always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
+    always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
+    always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
+    always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
+    always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
+    always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
+    always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
+    always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
+    always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
+    always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
+    always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
+    always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
+    always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
+    always @(posedge dqs_in[32]) dqs_neg_timing_check(32);
+    always @(posedge dqs_in[33]) dqs_neg_timing_check(33);
+    always @(posedge dqs_in[34]) dqs_neg_timing_check(34);
+    always @(posedge dqs_in[35]) dqs_neg_timing_check(35);
+
+endmodule
diff --git a/sim/verilog/micron_2048Mb_ddr2/ddr2_mcp.v b/sim/verilog/micron_2048Mb_ddr2/ddr2_mcp.v
new file mode 100644
index 0000000..38e04bb
--- /dev/null
+++ b/sim/verilog/micron_2048Mb_ddr2/ddr2_mcp.v
@@ -0,0 +1,94 @@
+/****************************************************************************************
+*
+*    File Name:  ddr2_mcp.v
+*
+* Dependencies:  ddr2.v, ddr2_parameters.vh
+*
+*  Description:  Micron SDRAM DDR2 (Double Data Rate 2) multi-chip package model
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+ `timescale 1ps / 1ps
+
+module ddr2_mcp (
+    ck,
+    ck_n,
+    cke,
+    cs_n,
+    ras_n,
+    cas_n,
+    we_n,
+    dm_rdqs,
+    ba,
+    addr,
+    dq,
+    dqs,
+    dqs_n,
+    rdqs_n,
+    odt
+);
+
+    `include "ddr2_parameters.vh"
+
+    // Declare Ports
+    input   ck;
+    input   ck_n;
+    input   [CS_BITS-1:0]   cke;
+    input   [CS_BITS-1:0]   cs_n;
+    input   ras_n;
+    input   cas_n;
+    input   we_n;
+    inout   [DM_BITS-1:0]   dm_rdqs;
+    input   [BA_BITS-1:0]   ba;
+    input   [ADDR_BITS-1:0] addr;
+    inout   [DQ_BITS-1:0]   dq;
+    inout   [DQS_BITS-1:0]  dqs;
+    inout   [DQS_BITS-1:0]  dqs_n;
+    output  [DQS_BITS-1:0]  rdqs_n;
+    input   [CS_BITS-1:0]   odt;
+
+    wire [RANKS-1:0] cke_mcp = cke;
+    wire [RANKS-1:0] cs_n_mcp = cs_n;
+    wire [RANKS-1:0] odt_mcp = odt;
+
+    ddr2 rank [RANKS-1:0] (
+        ck, 
+        ck_n,
+        cke_mcp, 
+        cs_n_mcp,
+        ras_n, 
+        cas_n, 
+        we_n, 
+        dm_rdqs, 
+        ba, 
+        addr, 
+        dq, 
+        dqs,
+        dqs_n,
+        rdqs_n,
+        odt_mcp
+    );
+
+endmodule
diff --git a/sim/verilog/micron_2048Mb_ddr2/ddr2_module.v b/sim/verilog/micron_2048Mb_ddr2/ddr2_module.v
new file mode 100644
index 0000000..2fd45be
--- /dev/null
+++ b/sim/verilog/micron_2048Mb_ddr2/ddr2_module.v
@@ -0,0 +1,377 @@
+/****************************************************************************************
+*
+*    File Name:  ddr2_module.v
+*
+* Dependencies:  ddr2.v, ddr2.v, ddr2_parameters.vh
+*
+*  Description:  Micron SDRAM DDR2 (Double Data Rate 2) module model
+*
+*   Limitation:  - SPD (Serial Presence-Detect) is not modeled
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+* Rev   Author   Date        Changes
+* ---------------------------------------------------------------------------------------
+* 1.00  SPH      09/18/09    Fixed cb connection in ECC mode
+*                            Added invalid ECC mode error message in x16 configuration
+****************************************************************************************/
+ `timescale 1ps / 1ps
+
+module ddr2_module (
+`ifdef SODIMM
+`else
+    reset_n,
+    cb     ,
+`endif
+    ck     ,
+    ck_n   ,
+    cke    ,
+    s_n    ,
+    ras_n  ,
+    cas_n  ,
+    we_n   ,
+    ba     ,
+    addr   ,
+    odt    ,
+    dqs    ,
+    dqs_n  ,
+    dq     ,
+    scl    ,
+    sa     ,
+    sda
+);
+
+`include "ddr2_parameters.vh"
+
+    input            [1:0] cke    ;
+    input                  ras_n  ;
+    input                  cas_n  ;
+    input                  we_n   ;
+    input            [2:0] ba     ;
+    input           [15:0] addr   ;
+    input            [1:0] odt    ;
+    inout           [17:0] dqs    ;
+    inout           [17:0] dqs_n  ;
+    inout           [63:0] dq     ;
+    input                  scl    ; // no connect
+    inout                  sda    ; // no connect
+
+`ifdef QUAD_RANK
+    initial if (DEBUG) $display("%m: Quad Rank");
+`else `ifdef DUAL_RANK
+    initial if (DEBUG) $display("%m: Dual Rank");
+`else
+    initial if (DEBUG) $display("%m: Single Rank");
+`endif `endif
+
+`ifdef ECC
+    initial if (DEBUG) $display("%m: ECC");
+    `ifdef SODIMM
+    initial begin
+        $display("%m ERROR: ECC is not available on SODIMM configurations");
+        if (STOP_ON_ERROR) $stop(0);
+    end
+    `endif
+    `ifdef x16
+    initial begin
+        $display("%m ERROR: ECC is not available on x16 configurations");
+        if (STOP_ON_ERROR) $stop(0);
+    end
+    `endif
+`else
+    initial if (DEBUG) $display("%m: non ECC");
+`endif
+
+`ifdef RDIMM
+    initial if (DEBUG) $display("%m: RDIMM");
+    input                  reset_n;
+    input                  ck     ;
+    input                  ck_n   ;
+    input            [3:0] s_n    ;
+    inout            [7:0] cb     ;
+    input            [2:0] sa     ; // no connect
+
+    wire             [5:0] rck    = {6{ck}};
+    wire             [5:0] rck_n  = {6{ck_n}};
+    reg              [3:0] rs_n   ;
+    reg                    rras_n ;
+    reg                    rcas_n ;
+    reg                    rwe_n  ;
+    reg              [2:0] rba    ;
+    reg             [15:0] raddr  ;
+    reg              [3:0] rcke   ;
+    reg              [3:0] rodt   ;
+
+    always @(negedge reset_n or posedge ck) begin
+        if (!reset_n) begin
+            rs_n   <= #(500) 0;
+            rras_n <= #(500) 0;
+            rcas_n <= #(500) 0;
+            rwe_n  <= #(500) 0;
+            rba    <= #(500) 0;
+            raddr  <= #(500) 0;
+            rcke   <= #(500) 0;
+            rodt   <= #(500) 0;
+        end else begin
+            rs_n   <= #(500) s_n  ;
+            rras_n <= #(500) ras_n;
+            rcas_n <= #(500) cas_n;
+            rwe_n  <= #(500) we_n ;
+            rba    <= #(500) ba   ;
+            raddr  <= #(500) addr ;
+    `ifdef QUAD_RANK
+            rcke   <= #(500) {{2{cke[1]}}, {2{cke[0]}}};
+            rodt   <= #(500) {{2{odt[1]}}, {2{odt[0]}}};
+    `else
+            rcke   <= #(500) {2'b00, cke};
+            rodt   <= #(500) {2'b00, odt};
+    `endif
+
+        end
+    end
+`else
+    `ifdef SODIMM
+    initial if (DEBUG) $display("%m: SODIMM");
+    input            [1:0] ck     ;
+    input            [1:0] ck_n   ;
+    input            [1:0] s_n    ;
+    input            [1:0] sa     ; // no connect
+
+    wire             [7:0] cb;
+    wire             [5:0] rck    = {{3{ck[1]}}, {3{ck[0]}}};
+    wire             [5:0] rck_n  = {{3{ck_n[1]}}, {3{ck_n[0]}}};
+    `else
+    initial if (DEBUG) $display("%m: UDIMM");
+    input                  reset_n;
+    input            [2:0] ck     ;
+    input            [2:0] ck_n   ;
+    input            [1:0] s_n    ;
+    inout            [7:0] cb     ;
+    input            [2:0] sa     ; // no connect
+
+    wire             [5:0] rck    = {2{ck}};
+    wire             [5:0] rck_n  = {2{ck_n}};
+    `endif
+
+    wire             [2:0] rba    = ba   ;
+    wire            [15:0] raddr  = addr ;
+    wire                   rras_n = ras_n;
+    wire                   rcas_n = cas_n;
+    wire                   rwe_n  = we_n ;
+    `ifdef QUAD_RANK
+    wire             [3:0] rs_n   = {{2{s_n[1]}}, {2{s_n[0]}}};
+    wire             [3:0] rcke   = {{2{cke[1]}}, {2{cke[0]}}};
+    wire             [3:0] rodt   = {{2{odt[1]}}, {2{odt[0]}}};
+    `else
+    wire             [3:0] rs_n   = {2'b00, s_n};
+    wire             [3:0] rcke   = {2'b00, cke};
+    wire             [3:0] rodt   = {2'b00, odt};
+    `endif
+`endif
+    wire            [15:0] rcb    = {8'b0, cb};
+    wire                   zero   = 1'b0;
+    wire                   one    = 1'b1;
+
+  //ddr2       (ck    , ck_n    , cke    , cs_n   , ras_n , cas_n , we_n , dm_rdqs       , ba , addr                , dq        , dqs           , dqs_n     , rdqs_n   , odt    );
+`ifdef x4
+    initial if (DEBUG) $display("%m: Component Width = x4");
+    ddr2 U1R0  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[  0]      , dqs_n[  0],          , rodt[0]);
+    ddr2 U2R0  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[  1]      , dqs_n[  1],          , rodt[0]);
+    ddr2 U3R0  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[  2]      , dqs_n[  2],          , rodt[0]);
+    ddr2 U4R0  (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[  3]      , dqs_n[  3],          , rodt[0]);
+    ddr2 U6R0  (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[  4]      , dqs_n[  4],          , rodt[0]);
+    ddr2 U7R0  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[  5]      , dqs_n[  5],          , rodt[0]);
+    ddr2 U8R0  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[  6]      , dqs_n[  6],          , rodt[0]);
+    ddr2 U9R0  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[  7]      , dqs_n[  7],          , rodt[0]);
+    `ifdef ECC                 
+    ddr2 U5R0  (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], cb [ 3: 0], dqs[  8]      , dqs_n[  8],          , rodt[0]);
+    `endif
+    ddr2 U18R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[  9]      , dqs_n[  9],          , rodt[0]);
+    ddr2 U17R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10]      , dqs_n[ 10],          , rodt[0]);
+    ddr2 U16R0 (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11]      , dqs_n[ 11],          , rodt[0]);
+    ddr2 U15R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12]      , dqs_n[ 12],          , rodt[0]);
+    ddr2 U13R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13]      , dqs_n[ 13],          , rodt[0]);
+    ddr2 U12R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14]      , dqs_n[ 14],          , rodt[0]);
+    ddr2 U11R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15]      , dqs_n[ 15],          , rodt[0]);
+    ddr2 U10R0 (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16]      , dqs_n[ 16],          , rodt[0]);
+    `ifdef ECC                 
+    ddr2 U14R0 (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], cb [ 7: 4], dqs[ 17]      , dqs_n[ 17],          , rodt[0]);
+    `endif
+    `ifdef DUAL_RANK
+    ddr2 U1R1  (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[  0]      , dqs_n[  0],          , rodt[1]);
+    ddr2 U2R1  (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[  1]      , dqs_n[  1],          , rodt[1]);
+    ddr2 U3R1  (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[  2]      , dqs_n[  2],          , rodt[1]);
+    ddr2 U4R1  (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[  3]      , dqs_n[  3],          , rodt[1]);
+    ddr2 U6R1  (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[  4]      , dqs_n[  4],          , rodt[1]);
+    ddr2 U7R1  (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[  5]      , dqs_n[  5],          , rodt[1]);
+    ddr2 U8R1  (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[  6]      , dqs_n[  6],          , rodt[1]);
+    ddr2 U9R1  (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[  7]      , dqs_n[  7],          , rodt[1]);
+        `ifdef  ECC            
+    ddr2 U5R1  (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], cb [ 3: 0], dqs[  8]      , dqs_n[  8],          , rodt[1]);
+        `endif
+    ddr2 U18R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[  9]      , dqs_n[  9],          , rodt[1]);
+    ddr2 U17R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10]      , dqs_n[ 10],          , rodt[1]);
+    ddr2 U16R1 (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11]      , dqs_n[ 11],          , rodt[1]);
+    ddr2 U15R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12]      , dqs_n[ 12],          , rodt[1]);
+    ddr2 U13R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13]      , dqs_n[ 13],          , rodt[1]);
+    ddr2 U12R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14]      , dqs_n[ 14],          , rodt[1]);
+    ddr2 U11R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15]      , dqs_n[ 15],          , rodt[1]);
+    ddr2 U10R1 (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16]      , dqs_n[ 16],          , rodt[1]);
+        `ifdef ECC            
+    ddr2 U14R1 (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], cb [ 7: 4], dqs[ 17]      , dqs_n[ 17],          , rodt[1]);
+        `endif
+    `endif
+    `ifdef QUAD_RANK
+    ddr2 U1R2  (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[  0]      , dqs_n[  0],          , rodt[2]);
+    ddr2 U2R2  (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[  1]      , dqs_n[  1],          , rodt[2]);
+    ddr2 U3R2  (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[  2]      , dqs_n[  2],          , rodt[2]);
+    ddr2 U4R2  (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[  3]      , dqs_n[  3],          , rodt[2]);
+    ddr2 U6R2  (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[  4]      , dqs_n[  4],          , rodt[2]);
+    ddr2 U7R2  (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[  5]      , dqs_n[  5],          , rodt[2]);
+    ddr2 U8R2  (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[  6]      , dqs_n[  6],          , rodt[2]);
+    ddr2 U9R2  (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[  7]      , dqs_n[  7],          , rodt[2]);
+        `ifdef ECC                 
+    ddr2 U5R2  (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], cb [ 3: 0], dqs[  8]      , dqs_n[  8],          , rodt[2]);
+        `endif
+    ddr2 U18R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[  9]      , dqs_n[  9],          , rodt[2]);
+    ddr2 U17R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10]      , dqs_n[ 10],          , rodt[2]);
+    ddr2 U16R2 (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11]      , dqs_n[ 11],          , rodt[2]);
+    ddr2 U15R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12]      , dqs_n[ 12],          , rodt[2]);
+    ddr2 U13R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13]      , dqs_n[ 13],          , rodt[2]);
+    ddr2 U12R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14]      , dqs_n[ 14],          , rodt[2]);
+    ddr2 U11R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15]      , dqs_n[ 15],          , rodt[2]);
+    ddr2 U10R2 (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16]      , dqs_n[ 16],          , rodt[2]);
+        `ifdef ECC                 
+    ddr2 U14R2 (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], cb [ 7: 4], dqs[ 17]      , dqs_n[ 17],          , rodt[2]);
+        `endif
+    ddr2 U1R3  (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [ 3: 0], dqs[  0]      , dqs_n[  0],          , rodt[3]);
+    ddr2 U2R3  (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [11: 8], dqs[  1]      , dqs_n[  1],          , rodt[3]);
+    ddr2 U3R3  (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [19:16], dqs[  2]      , dqs_n[  2],          , rodt[3]);
+    ddr2 U4R3  (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [27:24], dqs[  3]      , dqs_n[  3],          , rodt[3]);
+    ddr2 U6R3  (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [35:32], dqs[  4]      , dqs_n[  4],          , rodt[3]);
+    ddr2 U7R3  (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [43:40], dqs[  5]      , dqs_n[  5],          , rodt[3]);
+    ddr2 U8R3  (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [51:48], dqs[  6]      , dqs_n[  6],          , rodt[3]);
+    ddr2 U9R3  (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [59:56], dqs[  7]      , dqs_n[  7],          , rodt[3]);
+        `ifdef  ECC            
+    ddr2 U5R3  (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], cb [ 3: 0], dqs[  8]      , dqs_n[  8],          , rodt[3]);
+        `endif
+    ddr2 U18R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [ 7: 4], dqs[  9]      , dqs_n[  9],          , rodt[3]);
+    ddr2 U17R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [15:12], dqs[ 10]      , dqs_n[ 10],          , rodt[3]);
+    ddr2 U16R3 (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [23:20], dqs[ 11]      , dqs_n[ 11],          , rodt[3]);
+    ddr2 U15R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [31:28], dqs[ 12]      , dqs_n[ 12],          , rodt[3]);
+    ddr2 U13R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [39:36], dqs[ 13]      , dqs_n[ 13],          , rodt[3]);
+    ddr2 U12R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [47:44], dqs[ 14]      , dqs_n[ 14],          , rodt[3]);
+    ddr2 U11R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [55:52], dqs[ 15]      , dqs_n[ 15],          , rodt[3]);
+    ddr2 U10R3 (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], dq [63:60], dqs[ 16]      , dqs_n[ 16],          , rodt[3]);
+        `ifdef ECC            
+    ddr2 U14R3 (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, zero          , rba, raddr[ADDR_BITS-1:0], cb [ 7: 4], dqs[ 17]      , dqs_n[ 17],          , rodt[3]);
+        `endif
+    `endif
+`else `ifdef x8
+    initial if (DEBUG) $display("%m: Component Width = x8");
+    ddr2 U1R0  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[ 9]       , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[  0]      , dqs_n[  0], dqs_n[ 9], rodt[0]);
+    ddr2 U2R0  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[10]       , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[  1]      , dqs_n[  1], dqs_n[10], rodt[0]);
+    ddr2 U3R0  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[11]       , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[  2]      , dqs_n[  2], dqs_n[11], rodt[0]);
+    ddr2 U4R0  (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[12]       , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[  3]      , dqs_n[  3], dqs_n[12], rodt[0]);
+    ddr2 U6R0  (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[13]       , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[  4]      , dqs_n[  4], dqs_n[13], rodt[0]);
+    ddr2 U7R0  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[14]       , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[  5]      , dqs_n[  5], dqs_n[14], rodt[0]);
+    ddr2 U8R0  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[15]       , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[  6]      , dqs_n[  6], dqs_n[15], rodt[0]);
+    ddr2 U9R0  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[16]       , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[  7]      , dqs_n[  7], dqs_n[16], rodt[0]);
+    `ifdef ECC                 
+    ddr2 U5R0  (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[17]       , rba, raddr[ADDR_BITS-1:0], cb [ 7: 0], dqs[  8]      , dqs_n[  8], dqs_n[17], rodt[0]);
+    `endif
+    `ifdef DUAL_RANK
+    ddr2 U1R1  (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[ 9]       , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[  0]      , dqs_n[  0], dqs_n[ 9], rodt[1]);
+    ddr2 U2R1  (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[10]       , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[  1]      , dqs_n[  1], dqs_n[10], rodt[1]);
+    ddr2 U3R1  (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[11]       , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[  2]      , dqs_n[  2], dqs_n[11], rodt[1]);
+    ddr2 U4R1  (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[12]       , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[  3]      , dqs_n[  3], dqs_n[12], rodt[1]);
+    ddr2 U6R1  (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[13]       , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[  4]      , dqs_n[  4], dqs_n[13], rodt[1]);
+    ddr2 U7R1  (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[14]       , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[  5]      , dqs_n[  5], dqs_n[14], rodt[1]);
+    ddr2 U8R1  (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[15]       , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[  6]      , dqs_n[  6], dqs_n[15], rodt[1]);
+    ddr2 U9R1  (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[16]       , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[  7]      , dqs_n[  7], dqs_n[16], rodt[1]);
+        `ifdef ECC            
+    ddr2 U5R1  (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[17]       , rba, raddr[ADDR_BITS-1:0], cb [ 7: 0], dqs[  8]      , dqs_n[  8], dqs_n[17], rodt[1]);
+        `endif
+    `endif
+    `ifdef QUAD_RANK
+    ddr2 U1R2  (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[ 9]       , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[  0]      , dqs_n[  0], dqs_n[ 9], rodt[2]);
+    ddr2 U2R2  (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[10]       , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[  1]      , dqs_n[  1], dqs_n[10], rodt[2]);
+    ddr2 U3R2  (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[11]       , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[  2]      , dqs_n[  2], dqs_n[11], rodt[2]);
+    ddr2 U4R2  (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[12]       , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[  3]      , dqs_n[  3], dqs_n[12], rodt[2]);
+    ddr2 U6R2  (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[13]       , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[  4]      , dqs_n[  4], dqs_n[13], rodt[2]);
+    ddr2 U7R2  (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[14]       , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[  5]      , dqs_n[  5], dqs_n[14], rodt[2]);
+    ddr2 U8R2  (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[15]       , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[  6]      , dqs_n[  6], dqs_n[15], rodt[2]);
+    ddr2 U9R2  (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[16]       , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[  7]      , dqs_n[  7], dqs_n[16], rodt[2]);
+        `ifdef ECC                 
+    ddr2 U5R2  (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[17]       , rba, raddr[ADDR_BITS-1:0], cb [ 7: 0], dqs[  8]      , dqs_n[  8], dqs_n[17], rodt[2]);
+        `endif
+    ddr2 U1R3  (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[ 9]       , rba, raddr[ADDR_BITS-1:0], dq [ 7: 0], dqs[  0]      , dqs_n[  0], dqs_n[ 9], rodt[3]);
+    ddr2 U2R3  (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[10]       , rba, raddr[ADDR_BITS-1:0], dq [15: 8], dqs[  1]      , dqs_n[  1], dqs_n[10], rodt[3]);
+    ddr2 U3R3  (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[11]       , rba, raddr[ADDR_BITS-1:0], dq [23:16], dqs[  2]      , dqs_n[  2], dqs_n[11], rodt[3]);
+    ddr2 U4R3  (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[12]       , rba, raddr[ADDR_BITS-1:0], dq [31:24], dqs[  3]      , dqs_n[  3], dqs_n[12], rodt[3]);
+    ddr2 U6R3  (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[13]       , rba, raddr[ADDR_BITS-1:0], dq [39:32], dqs[  4]      , dqs_n[  4], dqs_n[13], rodt[3]);
+    ddr2 U7R3  (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[14]       , rba, raddr[ADDR_BITS-1:0], dq [47:40], dqs[  5]      , dqs_n[  5], dqs_n[14], rodt[3]);
+    ddr2 U8R3  (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[15]       , rba, raddr[ADDR_BITS-1:0], dq [55:48], dqs[  6]      , dqs_n[  6], dqs_n[15], rodt[3]);
+    ddr2 U9R3  (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[16]       , rba, raddr[ADDR_BITS-1:0], dq [63:56], dqs[  7]      , dqs_n[  7], dqs_n[16], rodt[3]);
+        `ifdef ECC            
+    ddr2 U5R3  (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[17]       , rba, raddr[ADDR_BITS-1:0], cb [ 7: 0], dqs[  8]      , dqs_n[  8], dqs_n[17], rodt[3]);
+        `endif
+    `endif
+`else `ifdef x16
+    initial if (DEBUG) $display("%m: Component Width = x16");
+    ddr2 U1R0  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[10: 9]    , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0]      , dqs_n[1:0],          , rodt[0]);
+    ddr2 U2R0  (rck[1], rck_n[1], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[12:11]    , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2]      , dqs_n[3:2],          , rodt[0]);
+    ddr2 U4R0  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[14:13]    , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4]      , dqs_n[5:4],          , rodt[0]);
+    ddr2 U5R0  (rck[2], rck_n[2], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, dqs[16:15]    , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6]      , dqs_n[7:6],          , rodt[0]);
+    `ifdef ECC
+    ddr2 U3R0  (rck[0], rck_n[0], rcke[0], rs_n[0], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]},     , rodt[0]);
+    `endif
+    `ifdef DUAL_RANK
+    ddr2 U1R1  (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[10: 9]    , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0]      , dqs_n[1:0],          , rodt[1]);
+    ddr2 U2R1  (rck[4], rck_n[4], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[12:11]    , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2]      , dqs_n[3:2],          , rodt[1]);
+    ddr2 U4R1  (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[14:13]    , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4]      , dqs_n[5:4],          , rodt[1]);
+    ddr2 U5R1  (rck[5], rck_n[5], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, dqs[16:15]    , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6]      , dqs_n[7:6],          , rodt[1]);
+        `ifdef ECC
+    ddr2 U3R1  (rck[3], rck_n[3], rcke[1], rs_n[1], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]},     , rodt[1]);
+        `endif
+    `endif
+    `ifdef QUAD_RANK
+    ddr2 U1R2  (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[10: 9]    , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0]      , dqs_n[1:0],          , rodt[2]);
+    ddr2 U2R2  (rck[1], rck_n[1], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[12:11]    , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2]      , dqs_n[3:2],          , rodt[2]);
+    ddr2 U4R2  (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[14:13]    , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4]      , dqs_n[5:4],          , rodt[2]);
+    ddr2 U5R2  (rck[2], rck_n[2], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, dqs[16:15]    , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6]      , dqs_n[7:6],          , rodt[2]);
+        `ifdef ECC
+    ddr2 U3R2  (rck[0], rck_n[0], rcke[2], rs_n[2], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]},     , rodt[2]);
+        `endif
+    ddr2 U1R3  (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[10: 9]    , rba, raddr[ADDR_BITS-1:0], dq [15: 0], dqs[1:0]      , dqs_n[1:0],          , rodt[3]);
+    ddr2 U2R3  (rck[4], rck_n[4], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[12:11]    , rba, raddr[ADDR_BITS-1:0], dq [31:16], dqs[3:2]      , dqs_n[3:2],          , rodt[3]);
+    ddr2 U4R3  (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[14:13]    , rba, raddr[ADDR_BITS-1:0], dq [47:32], dqs[5:4]      , dqs_n[5:4],          , rodt[3]);
+    ddr2 U5R3  (rck[5], rck_n[5], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, dqs[16:15]    , rba, raddr[ADDR_BITS-1:0], dq [63:48], dqs[7:6]      , dqs_n[7:6],          , rodt[3]);
+        `ifdef ECC
+    ddr2 U3R3  (rck[3], rck_n[3], rcke[3], rs_n[3], rras_n, rcas_n, rwe_n, {one, dqs[17]}, rba, raddr[ADDR_BITS-1:0], rcb[15: 0], {zero, dqs[8]}, {one, dqs_n[8]},     , rodt[3]);
+        `endif
+    `endif
+`endif `endif `endif
+
+endmodule
diff --git a/sim/verilog/micron_2048Mb_ddr2/ddr2_parameters.vh b/sim/verilog/micron_2048Mb_ddr2/ddr2_parameters.vh
new file mode 100644
index 0000000..4e4d866
--- /dev/null
+++ b/sim/verilog/micron_2048Mb_ddr2/ddr2_parameters.vh
@@ -0,0 +1,383 @@
+/****************************************************************************************
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+
+    // Parameters current with 2Gb datasheet rev B
+
+    // Timing parameters based on Speed Grade
+
+                                          // SYMBOL UNITS DESCRIPTION
+                                          // ------ ----- -----------
+`ifdef sg187E
+    parameter TCK_MIN          =    1875; // tCK    ps    Minimum Clock Cycle Time
+    parameter TJIT_PER         =      90; // tJIT(per)  ps Period JItter
+    parameter TJIT_DUTY        =      75; // tJIT(duty) ps Half Period Jitter
+    parameter TJIT_CC          =     180; // tJIT(cc)   ps Cycle to Cycle jitter
+    parameter TERR_2PER        =     132; // tERR(nper) ps Accumulated Error (2-cycle)
+    parameter TERR_3PER        =     157; // tERR(nper) ps Accumulated Error (3-cycle)
+    parameter TERR_4PER        =     175; // tERR(nper) ps Accumulated Error (4-cycle)
+    parameter TERR_5PER        =     188; // tERR(nper) ps Accumulated Error (5-cycle)
+    parameter TERR_N1PER       =     250; // tERR(nper) ps Accumulated Error (6-10-cycle)
+    parameter TERR_N2PER       =     425; // tERR(nper) ps Accumulated Error (11-50-cycle)
+    parameter TQHS             =     250; // tQHS   ps    Data hold skew factor
+    parameter TAC              =     350; // tAC    ps    DQ output access time from CK/CK#
+    parameter TDS              =       0; // tDS    ps    DQ and DM input setup time relative to DQS
+    parameter TDH              =      75; // tDH    ps    DQ and DM input hold time relative to DQS
+    parameter TDQSCK           =     300; // tDQSCK ps    DQS output access time from CK/CK#
+    parameter TDQSQ            =     175; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter TIS              =     125; // tIS    ps    Input Setup Time
+    parameter TIH              =     200; // tIH    ps    Input Hold Time
+    parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+    parameter TRCD             =   13125; // tRCD   ps    Active to Read/Write command time
+    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+    parameter TRP              =   13125; // tRP    ps    Precharge command period
+    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+    parameter TXARDS           =      10; // tXARDS tCK   Exit low power active power down to a read command
+    parameter TXARD            =       3; // tXARD  tCK   Exit active power down to a read command
+    parameter TXP              =       3; // tXP    tCK   Exit power down to a non-read command
+    parameter TANPD            =       4; // tANPD  tCK   ODT to power-down entry latency
+    parameter TAXPD            =      11; // tAXPD  tCK   ODT power-down exit latency
+    parameter CL_TIME          =   13125; // CL     ps    Minimum CAS Latency
+`else `ifdef sg25E
+    parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+    parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+    parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+    parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+    parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+    parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+    parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+    parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+    parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+    parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+    parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+    parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+    parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+    parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+    parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter TIS              =     175; // tIS    ps    Input Setup Time
+    parameter TIH              =     250; // tIH    ps    Input Hold Time
+    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+    parameter TRCD             =   12500; // tRCD   ps    Active to Read/Write command time
+    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+    parameter TRP              =   12500; // tRP    ps    Precharge command period
+    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+    parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+    parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+    parameter CL_TIME          =   12500; // CL     ps    Minimum CAS Latency
+`else `ifdef sg25
+    parameter TCK_MIN          =    2500; // tCK    ps    Minimum Clock Cycle Time
+    parameter TJIT_PER         =     100; // tJIT(per)  ps Period JItter
+    parameter TJIT_DUTY        =     100; // tJIT(duty) ps Half Period Jitter
+    parameter TJIT_CC          =     200; // tJIT(cc)   ps Cycle to Cycle jitter
+    parameter TERR_2PER        =     150; // tERR(nper) ps Accumulated Error (2-cycle)
+    parameter TERR_3PER        =     175; // tERR(nper) ps Accumulated Error (3-cycle)
+    parameter TERR_4PER        =     200; // tERR(nper) ps Accumulated Error (4-cycle)
+    parameter TERR_5PER        =     200; // tERR(nper) ps Accumulated Error (5-cycle)
+    parameter TERR_N1PER       =     300; // tERR(nper) ps Accumulated Error (6-10-cycle)
+    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+    parameter TQHS             =     300; // tQHS   ps    Data hold skew factor
+    parameter TAC              =     400; // tAC    ps    DQ output access time from CK/CK#
+    parameter TDS              =      50; // tDS    ps    DQ and DM input setup time relative to DQS
+    parameter TDH              =     125; // tDH    ps    DQ and DM input hold time relative to DQS
+    parameter TDQSCK           =     350; // tDQSCK ps    DQS output access time from CK/CK#
+    parameter TDQSQ            =     200; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter TIS              =     175; // tIS    ps    Input Setup Time
+    parameter TIH              =     250; // tIH    ps    Input Hold Time
+    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+    parameter TRP              =   15000; // tRP    ps    Precharge command period
+    parameter TRPA             =   17500; // tRPA   ps    Precharge All period
+    parameter TXARDS           =       8; // tXARDS tCK   Exit low power active power down to a read command
+    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+    parameter TAXPD            =      10; // tAXPD  tCK   ODT power-down exit latency
+    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+`else `ifdef sg3E
+    parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+    parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+    parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+    parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+    parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+    parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+    parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+    parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter TIS              =     200; // tIS    ps    Input Setup Time
+    parameter TIH              =     275; // tIH    ps    Input Hold Time
+    parameter TRC              =   54000; // tRC    ps    Active to Active/Auto Refresh command time
+    parameter TRCD             =   12000; // tRCD   ps    Active to Read/Write command time
+    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+    parameter TRP              =   12000; // tRP    ps    Precharge command period
+    parameter TRPA             =   15000; // tRPA   ps    Precharge All period
+    parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+    parameter CL_TIME          =   12000; // CL     ps    Minimum CAS Latency
+`else `ifdef sg3
+    parameter TCK_MIN          =    3000; // tCK    ps    Minimum Clock Cycle Time
+    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+    parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+    parameter TQHS             =     340; // tQHS   ps    Data hold skew factor
+    parameter TAC              =     450; // tAC    ps    DQ output access time from CK/CK#
+    parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+    parameter TDH              =     175; // tDH    ps    DQ and DM input hold time relative to DQS
+    parameter TDQSCK           =     400; // tDQSCK ps    DQS output access time from CK/CK#
+    parameter TDQSQ            =     240; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter TIS              =     200; // tIS    ps    Input Setup Time
+    parameter TIH              =     275; // tIH    ps    Input Hold Time
+    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+    parameter TRP              =   15000; // tRP    ps    Precharge command period
+    parameter TRPA             =   18000; // tRPA   ps    Precharge All period
+    parameter TXARDS           =       7; // tXARDS tCK   Exit low power active power down to a read command
+    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+`else `ifdef sg37E
+    parameter TCK_MIN          =    3750; // tCK    ps    Minimum Clock Cycle Time
+    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+    parameter TJIT_DUTY        =     125; // tJIT(duty) ps Half Period Jitter
+    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+    parameter TQHS             =     400; // tQHS   ps    Data hold skew factor
+    parameter TAC              =     500; // tAC    ps    DQ output access time from CK/CK#
+    parameter TDS              =     100; // tDS    ps    DQ and DM input setup time relative to DQS
+    parameter TDH              =     225; // tDH    ps    DQ and DM input hold time relative to DQS
+    parameter TDQSCK           =     450; // tDQSCK ps    DQS output access time from CK/CK#
+    parameter TDQSQ            =     300; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter TIS              =     250; // tIS    ps    Input Setup Time
+    parameter TIH              =     375; // tIH    ps    Input Hold Time
+    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+    parameter TWTR             =    7500; // tWTR   ps    Write to Read command delay
+    parameter TRP              =   15000; // tRP    ps    Precharge command period
+    parameter TRPA             =   18750; // tRPA   ps    Precharge All period
+    parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+`else `define sg5E
+    parameter TCK_MIN          =    5000; // tCK    ps    Minimum Clock Cycle Time
+    parameter TJIT_PER         =     125; // tJIT(per)  ps Period JItter
+    parameter TJIT_DUTY        =     150; // tJIT(duty) ps Half Period Jitter
+    parameter TJIT_CC          =     250; // tJIT(cc)   ps Cycle to Cycle jitter
+    parameter TERR_2PER        =     175; // tERR(nper) ps Accumulated Error (2-cycle)
+    parameter TERR_3PER        =     225; // tERR(nper) ps Accumulated Error (3-cycle)
+    parameter TERR_4PER        =     250; // tERR(nper) ps Accumulated Error (4-cycle)
+    parameter TERR_5PER        =     250; // tERR(nper) ps Accumulated Error (5-cycle)
+    parameter TERR_N1PER       =     350; // tERR(nper) ps Accumulated Error (6-10-cycle)
+    parameter TERR_N2PER       =     450; // tERR(nper) ps Accumulated Error (11-50-cycle)
+    parameter TQHS             =     450; // tQHS   ps    Data hold skew factor
+    parameter TAC              =     600; // tAC    ps    DQ output access time from CK/CK#
+    parameter TDS              =     150; // tDS    ps    DQ and DM input setup time relative to DQS
+    parameter TDH              =     275; // tDH    ps    DQ and DM input hold time relative to DQS
+    parameter TDQSCK           =     500; // tDQSCK ps    DQS output access time from CK/CK#
+    parameter TDQSQ            =     350; // tDQSQ  ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter TIS              =     350; // tIS    ps    Input Setup Time
+    parameter TIH              =     475; // tIH    ps    Input Hold Time
+    parameter TRC              =   55000; // tRC    ps    Active to Active/Auto Refresh command time
+    parameter TRCD             =   15000; // tRCD   ps    Active to Read/Write command time
+    parameter TWTR             =   10000; // tWTR   ps    Write to Read command delay
+    parameter TRP              =   15000; // tRP    ps    Precharge command period
+    parameter TRPA             =   20000; // tRPA   ps    Precharge All period
+    parameter TXARDS           =       6; // tXARDS tCK   Exit low power active power down to a read command
+    parameter TXARD            =       2; // tXARD  tCK   Exit active power down to a read command
+    parameter TXP              =       2; // tXP    tCK   Exit power down to a non-read command
+    parameter TANPD            =       3; // tANPD  tCK   ODT to power-down entry latency
+    parameter TAXPD            =       8; // tAXPD  tCK   ODT power-down exit latency
+    parameter CL_TIME          =   15000; // CL     ps    Minimum CAS Latency
+`endif `endif `endif `endif `endif `endif
+
+`ifdef x16
+  `ifdef sg187E
+    parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+  `else `ifdef sg25E
+    parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+  `else `ifdef sg25 
+    parameter TFAW             =   45000; // tFAW  ps     Four Bank Activate window
+  `else // sg3E, sg3, sg37E, sg5E
+    parameter TFAW             =   50000; // tFAW  ps     Four Bank Activate window
+  `endif `endif `endif
+`else // x4, x8
+  `ifdef sg187E
+    parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+  `else `ifdef sg25E
+    parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+  `else `ifdef sg25 
+    parameter TFAW             =   35000; // tFAW  ps     Four Bank Activate window
+  `else // sg3E, sg3, sg37E, sg5E
+    parameter TFAW             =   37500; // tFAW  ps     Four Bank Activate window
+  `endif `endif `endif
+`endif
+
+    // Timing Parameters
+
+    // Mode Register
+    parameter AL_MIN           =       0; // AL     tCK   Minimum Additive Latency
+    parameter AL_MAX           =       6; // AL     tCK   Maximum Additive Latency
+    parameter CL_MIN           =       3; // CL     tCK   Minimum CAS Latency
+    parameter CL_MAX           =       7; // CL     tCK   Maximum CAS Latency
+    parameter WR_MIN           =       2; // WR     tCK   Minimum Write Recovery
+    parameter WR_MAX           =       8; // WR     tCK   Maximum Write Recovery
+    parameter BL_MIN           =       4; // BL     tCK   Minimum Burst Length
+    parameter BL_MAX           =       8; // BL     tCK   Minimum Burst Length
+    // Clock
+    parameter TCK_MAX          =    8000; // tCK    ps    Maximum Clock Cycle Time
+    parameter TCH_MIN          =    0.48; // tCH    tCK   Minimum Clock High-Level Pulse Width
+    parameter TCH_MAX          =    0.52; // tCH    tCK   Maximum Clock High-Level Pulse Width
+    parameter TCL_MIN          =    0.48; // tCL    tCK   Minimum Clock Low-Level Pulse Width
+    parameter TCL_MAX          =    0.52; // tCL    tCK   Maximum Clock Low-Level Pulse Width
+    // Data
+    parameter TLZ              =     TAC; // tLZ    ps    Data-out low-impedance window from CK/CK#
+    parameter THZ              =     TAC; // tHZ    ps    Data-out high impedance window from CK/CK#
+    parameter TDIPW            =    0.35; // tDIPW  tCK   DQ and DM input Pulse Width
+    // Data Strobe
+    parameter TDQSH            =    0.35; // tDQSH  tCK   DQS input High Pulse Width
+    parameter TDQSL            =    0.35; // tDQSL  tCK   DQS input Low Pulse Width
+    parameter TDSS             =    0.20; // tDSS   tCK   DQS falling edge to CLK rising (setup time)
+    parameter TDSH             =    0.20; // tDSH   tCK   DQS falling edge from CLK rising (hold time)
+    parameter TWPRE            =    0.35; // tWPRE  tCK   DQS Write Preamble
+    parameter TWPST            =    0.40; // tWPST  tCK   DQS Write Postamble
+    parameter TDQSS            =    0.25; // tDQSS  tCK   Rising clock edge to DQS/DQS# latching transition
+    // Command and Address
+    parameter TIPW             =     0.6; // tIPW   tCK   Control and Address input Pulse Width  
+    parameter TCCD             =       2; // tCCD   tCK   Cas to Cas command delay
+    parameter TRAS_MIN         =   40000; // tRAS   ps    Minimum Active to Precharge command time
+    parameter TRAS_MAX         =70000000; // tRAS   ps    Maximum Active to Precharge command time
+    parameter TRTP             =    7500; // tRTP   ps    Read to Precharge command delay
+    parameter TWR              =   15000; // tWR    ps    Write recovery time
+    parameter TMRD             =       2; // tMRD   tCK   Load Mode Register command cycle time
+    parameter TDLLK            =     200; // tDLLK  tCK   DLL locking time
+    // Refresh
+    parameter TRFC_MIN         =  197500; // tRFC   ps    Refresh to Refresh Command interval minimum value
+    parameter TRFC_MAX         =70000000; // tRFC   ps    Refresh to Refresh Command Interval maximum value
+    // Self Refresh
+    parameter TXSNR   = TRFC_MIN + 10000; // tXSNR  ps    Exit self refesh to a non-read command
+    parameter TXSRD            =     200; // tXSRD  tCK   Exit self refresh to a read command
+    parameter TISXR            =     TIS; // tISXR  ps    CKE setup time during self refresh exit.
+    // ODT
+    parameter TAOND            =       2; // tAOND  tCK   ODT turn-on delay
+    parameter TAOFD            =     2.5; // tAOFD  tCK   ODT turn-off delay
+    parameter TAONPD           =    2000; // tAONPD ps    ODT turn-on (precharge power-down mode)
+    parameter TAOFPD           =    2000; // tAOFPD ps    ODT turn-off (precharge power-down mode)
+    parameter TMOD             =   12000; // tMOD   ps    ODT enable in EMR to ODT pin transition
+    // Power Down
+    parameter TCKE             =       3; // tCKE   tCK   CKE minimum high or low pulse width
+
+    // Size Parameters based on Part Width
+
+`ifdef x4
+    parameter ADDR_BITS        =      15; // Address Bits
+    parameter ROW_BITS         =      15; // Number of Address bits
+    parameter COL_BITS         =      11; // Number of Column bits
+    parameter DM_BITS          =       1; // Number of Data Mask bits
+    parameter DQ_BITS          =       4; // Number of Data bits
+    parameter DQS_BITS         =       1; // Number of Dqs bits
+    parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+`else `ifdef x8
+    parameter ADDR_BITS        =      15; // Address Bits
+    parameter ROW_BITS         =      15; // Number of Address bits
+    parameter COL_BITS         =      10; // Number of Column bits
+    parameter DM_BITS          =       1; // Number of Data Mask bits
+    parameter DQ_BITS          =       8; // Number of Data bits
+    parameter DQS_BITS         =       1; // Number of Dqs bits
+    parameter TRRD             =    7500; // tRRD   Active bank a to Active bank b command time
+`else `define x16
+    parameter ADDR_BITS        =      14; // Address Bits
+    parameter ROW_BITS         =      14; // Number of Address bits
+    parameter COL_BITS         =      10; // Number of Column bits
+    parameter DM_BITS          =       2; // Number of Data Mask bits
+    parameter DQ_BITS          =      16; // Number of Data bits
+    parameter DQS_BITS         =       2; // Number of Dqs bits
+    parameter TRRD             =   10000; // tRRD   Active bank a to Active bank b command time
+`endif `endif
+
+`ifdef QUAD_RANK
+    `define DUAL_RANK // also define DUAL_RANK
+    parameter CS_BITS          =       4; // Number of Chip Select Bits
+    parameter RANKS            =       4; // Number of Chip Select Bits
+`else `ifdef DUAL_RANK
+    parameter CS_BITS          =       2; // Number of Chip Select Bits
+    parameter RANKS            =       2; // Number of Chip Select Bits
+`else
+    parameter CS_BITS          =       2; // Number of Chip Select Bits
+    parameter RANKS            =       1; // Number of Chip Select Bits
+`endif `endif
+
+    // Size Parameters
+    parameter BA_BITS          =       3; // Set this parmaeter to control how many Bank Address bits
+    parameter MEM_BITS         =      10; // Number of write data bursts can be stored in memory.  The default is 2^10=1024.
+    parameter AP               =      10; // the address bit that controls auto-precharge and precharge-all
+    parameter BL_BITS          =       3; // the number of bits required to count to MAX_BL
+    parameter BO_BITS          =       2; // the number of Burst Order Bits
+
+    // Simulation parameters
+    parameter STOP_ON_ERROR    =       1; // If set to 1, the model will halt on command sequence/major errors
+    parameter DEBUG            =       1; // Turn on Debug messages
+    parameter BUS_DELAY        =       0; // delay in nanoseconds
+    parameter RANDOM_OUT_DELAY =       0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
+    parameter RANDOM_SEED      = 711689044; //seed value for random generator.
+
+    parameter RDQSEN_PRE       =       2; // DQS driving time prior to first read strobe
+    parameter RDQSEN_PST       =       1; // DQS driving time after last read strobe
+    parameter RDQS_PRE         =       2; // DQS low time prior to first read strobe
+    parameter RDQS_PST         =       1; // DQS low time after last valid read strobe
+    parameter RDQEN_PRE        =       0; // DQ/DM driving time prior to first read data
+    parameter RDQEN_PST        =       0; // DQ/DM driving time after last read data
+    parameter WDQS_PRE         =       1; // DQS half clock periods prior to first write strobe
+    parameter WDQS_PST         =       1; // DQS half clock periods after last valid write strobe
diff --git a/sim/verilog/micron_2048Mb_ddr2/readme.txt b/sim/verilog/micron_2048Mb_ddr2/readme.txt
new file mode 100644
index 0000000..cc0507d
--- /dev/null
+++ b/sim/verilog/micron_2048Mb_ddr2/readme.txt
@@ -0,0 +1,190 @@
+Disclaimer of Warranty:
+-----------------------
+This software code and all associated documentation, comments or other 
+information (collectively "Software") is provided "AS IS" without 
+warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+DAMAGES. Because some jurisdictions prohibit the exclusion or 
+limitation of liability for consequential or incidental damages, the 
+above limitation may not apply to you.
+
+Copyright 2003 Micron Technology, Inc. All rights reserved.
+
+Getting Started:
+----------------
+Unzip the included files to a folder.
+Compile ddr2.v, ddr2_mcp.v, and tb.v using a verilog simulator.
+Simulate the top level test bench tb.
+Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
+
+File Descriptions:
+------------------
+ddr2.v              -ddr2 model
+ddr2_mcp.v          -structural wrapper for ddr2 - multi-chip package model
+ddr2_module.v       -structural wrapper for ddr2 - module model
+ddr2_parameters.vh  -file that contains all parameters used by the model
+readme.txt          -this file
+tb.v                -ddr2 model test bench
+subtest.vh          -example test included by the test bench.
+tb.do               -compiles and runs the ddr2 model and test bench
+
+Defining the Speed Grade:
+-------------------------
+The verilog compiler directive "`define" may be used to choose between 
+multiple speed grades supported by the ddr2 model.  Allowable speed 
+grades are listed in the ddr2_parameters.vh file and begin with the 
+letters "sg".  The speed grade is used to select a set of timing 
+parameters for the ddr2 model.  The following are examples of defining 
+the speed grade.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+sg5 ddr2.v
+    NC-Verilog  ncverilog +define+sg5 ddr2.v
+    VCS         vcs +define+sg5 ddr2.v
+
+Defining the Organization:
+--------------------------
+The verilog compiler directive "`define" may be used to choose between 
+multiple organizations supported by the ddr2 model.  Valid 
+organizations include "x4", "x8", and x16, and are listed in the 
+ddr2_parameters.vh file.  The organization is used to select the amount 
+of memory and the port sizes of the ddr2 model.  The following are
+examples of defining the organization.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+x8 ddr2.v
+    NC-Verilog  ncverilog +define+x8 ddr2.v
+    VCS         vcs +define+x8 ddr2.v
+
+All combinations of speed grade and organization are considered valid 
+by the ddr2 model even though a Micron part may not exist for every 
+combination.
+
+Allocating Memory:
+------------------
+An associative array has been implemented to reduce the amount of 
+static memory allocated by the ddr2 model.  Each entry in the 
+associative array is a burst length of eight in size.  The number of 
+entries in the associative array is controlled by the MEM_BITS 
+parameter, and is equal to 2^MEM_BITS.  For example, if the MEM_BITS 
+parameter is equal to 10, the associative array will be large enough 
+to store 1024 writes of burst length 8 to unique addresses.  The 
+following are examples of setting the MEM_BITS parameter to 8.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vsim -GMEM_BITS=8 ddr2
+    NC-Verilog  ncverilog +defparam+ddr2.MEM_BITS=8 ddr2.v
+    VCS         vcs -pvalue+MEM_BITS=8 ddr2.v
+
+It is possible to allocate memory for every address supported by the 
+ddr2 model by using the verilog compiler directive "`define MAX_MEM".
+This procedure will improve simulation performance at the expense of 
+system memory.  The following are examples of allocating memory for
+every address.
+
+    Simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+MAX_MEM ddr2.v
+    NC-Verilog  ncverilog +define+MAX_MEM ddr2.v
+    VCS         vcs +define+MAX_MEM ddr2.v
+
+
+**********************************************************************
+The following information is provided to assist the modeling engineer 
+in creating multi-chip package (mcp) models.  ddr2_mcp.v is a 
+structural wrapper that instantiates ddr2 models.  This wrapper can be 
+used to create single, dual, or quad rank mcp models.  From the 
+perspective of the model, the only item that needs to be defined is the 
+number of ranks.
+**********************************************************************
+
+Defining the Number of Ranks in a multi-chip package:
+----------------------------------------------------
+The verilog compiler directive "`define" may be used to choose between 
+single, dual, and quad rank mcp configurations.  The default is single 
+rank if nothing is defined.  Dual rank configuration can be selected by 
+defining "DUAL_RANK" when the ddr2_mcp is compiled.  Quad rank 
+configuration can be selected by defining "QUAD_RANK" when the ddr2_mcp 
+is compiled.  The following are examples of defining a dual rank mcp 
+configuration.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+DUAL_RANK ddr2.v ddr2_mcp.v
+    NC-Verilog  ncverilog +define+DUAL_RANK ddr2.v ddr2_mcp.v
+    VCS         vcs +define+DUAL_RANK ddr2.v ddr2_mcp.v
+
+
+**********************************************************************
+The following information is provided to assist the modeling engineer 
+in creating DIMM models.  ddr2_module.v is a structural wrapper that 
+instantiates ddr2 models.  This wrapper can be used to create UDIMM, 
+RDIMM or SODIMM models.  Other form factors are not supported 
+(MiniDIMM, VLP DIMM, etc.).  From the perspective of the model, the 
+items that need to be defined are the number of ranks, the module 
+type, and the presence of ECC.  All combinations of ranks, module 
+type, and ECC are considered valid by the ddr2_module model even 
+though a Micron part may not exist for every combination.
+**********************************************************************
+
+Defining the Number of Ranks on a module:
+----------------------------------------
+The verilog compiler directive "`define" may be used to choose between 
+single, dual, and quad rank module configurations.  The default is single 
+rank if nothing is defined.  Dual rank configuration can be selected by 
+defining "DUAL_RANK" when the ddr2_module is compiled.  Quad rank 
+configuration can be selected by defining "QUAD_RANK" when the ddr2_module 
+is compiled.  The following are examples of defining a dual rank module 
+configuration.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+DUAL_RANK ddr2.v ddr2_module.v
+    NC-Verilog  ncverilog +define+DUAL_RANK ddr2.v ddr2_module.v
+    VCS         vcs +define+DUAL_RANK ddr2.v ddr2_module.v
+
+Defining the Module Type:
+-----------------------------------
+The verilog compiler directive "`define" may be used to choose between 
+UDIMM, RDIMM, and SODIMM module configurations.  The default is 
+unregistered (UDIMM) if nothing is defined.  SODIMM configuration can be 
+selected by defining "SODIMM" when the ddr2_module is compiled.  Registered 
+configuration can be selected by defining "RDIMM" when the ddr2_module is 
+compiled.  The following are examples of defining a registered module 
+configuration.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+RDIMM ddr2.v ddr2_module.v
+    NC-Verilog  ncverilog +define+RDIMM ddr2.v ddr2_module.v
+    VCS         vcs +define+RDIMM ddr2.v ddr2_module.v
+
+Defining the ECC for a module:
+-----------------------------
+The verilog compiler directive "`define" may be used to choose between 
+ECC and nonECC module configurations.  The default is nonECC if nothing 
+is defined.  ECC configuration can be selected by defining "ECC" when 
+the ddr2_module is compiled.  The following are examples of defining an
+ECC module configuration.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+ECC ddr2.v ddr2_module.v
+    NC-Verilog  ncverilog +define+ECC ddr2.v ddr2_module.v
+    VCS         vcs +define+ECC ddr2.v ddr2_module.v
diff --git a/sim/verilog/micron_2048Mb_ddr2/subtest.vh b/sim/verilog/micron_2048Mb_ddr2/subtest.vh
new file mode 100644
index 0000000..ec1e8f3
--- /dev/null
+++ b/sim/verilog/micron_2048Mb_ddr2/subtest.vh
@@ -0,0 +1,225 @@
+/****************************************************************************************
+*
+*    File Name:  subtest.vh
+*
+*  Description:  Micron SDRAM DDR2 (Double Data Rate 2)
+*                This file is included by tb.v
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+
+    initial begin : test
+        cke     <=  1'b0;
+        cs_n    <=  1'b1;
+        ras_n   <=  1'b1;
+        cas_n   <=  1'b1;
+        we_n    <=  1'b1;
+        ba      <=  {BA_BITS{1'bz}};
+        a       <=  {ADDR_BITS{1'bz}};
+        odt     <=  1'b0;
+        dq_en   <=  1'b0;
+        dqs_en  <=  1'b0;
+
+        cke     <=  1'b1;
+
+        // POWERUP SECTION 
+        power_up;
+
+        // INITIALIZE SECTION
+        precharge       (0, 1);                         // Precharge all banks
+        nop             (trp);
+        
+        load_mode       (2, 0);                         // Extended Mode Register (2)
+        nop             (tmrd-1);
+        
+        load_mode       (3, 0);                         // Extended Mode Register (3)
+        nop             (tmrd-1);
+        
+        load_mode       (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with DLL Enable
+        nop             (tmrd-1);
+        
+        load_mode       (0, 13'b0_000_1_0_000_0_011 | (twr-1)<<9 | taa<<4); // Mode Register without DLL Reset (bl=8)
+        nop             (tmrd-1);
+        
+        precharge       (0, 1);                         // Precharge all banks
+        nop             (trp);
+        
+        refresh;
+        nop             (trfc-1);
+
+        refresh;
+        nop             (trfc-1);
+        
+        load_mode       (0, 13'b0_000_0_0_000_0_011 | (twr-1)<<9 | taa<<4); // Mode Register without DLL Reset (bl=8)
+        nop             (tmrd-1);
+
+        load_mode       (1, 13'b0_0_0_111_0_000_1_0_0); // Extended Mode Register with OCD Default
+        nop             (tmrd-1);
+        
+        load_mode       (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with OCD Exit
+        nop             (tmrd-1);
+        
+        // DLL RESET ENABLE - you will need 200 TCK before any read command.
+        nop             (200);
+
+        // WRITE SECTION
+        activate        (0, 0);                       // Activate Bank 0, Row 0
+        nop             (trcd-1);
+        write           (0, 4, 0, 0, 'h3210);         // Write  Bank 0, Col 0
+        nop             (tccd-1);
+        write           (0, 0, 1, 0, 'h0123);         // Write  Bank 0, Col 0
+
+        activate        (1, 0);                       // Activate Bank 1, Row 0
+        nop             (trcd-1);
+        write           (1, 0, 1, 0, 'h4567);         // Write  Bank 1, Col 0
+
+        activate        (2, 0);                       // Activate Bank 2, Row 0
+        nop             (trcd-1);
+        write           (2, 0, 1, 0, 'h89AB);         // Write  Bank 2, Col 0
+
+        activate        (3, 0);                       // Activate Bank 3, Row 0
+        nop             (trcd-1);
+        write           (3, 0, 1, 0, 'hCDEF);         // Write  Bank 3, Col 0
+
+        nop             (cl - 1 + bl/2 + twtr-1);
+
+        nop             (tras);
+
+        // READ SECTION
+        activate        (0, 0);                       // Activate Bank 0, Row 0
+        nop             (trrd-1);
+        activate        (1, 0);                       // Activate Bank 1, Row 0
+        nop             (trrd-1);
+        activate        (2, 0);                       // Activate Bank 2, Row 0
+        nop             (trrd-1);
+        activate        (3, 0);                       // Activate Bank 3, Row 0
+        read            (0, 0, 1);                    // Read   Bank 0, Col 0
+        nop             (bl/2);
+        read            (1, 1, 1);                    // Read   Bank 1, Col 1
+        nop             (bl/2);
+        read            (2, 2, 1);                    // Read   Bank 2, Col 2
+        nop             (bl/2);
+        read            (3, 3, 1);                    // Read   Bank 3, Col 3
+        nop             (rl + bl/2);
+
+        activate        (0, 0);                       // Activate Bank 0, Row 0
+        nop             (trrd-1);
+        activate        (1, 0);                       // Activate Bank 1, Row 0
+        nop             (trcd-1);
+        $display ("%m at time %t: Figure 22: Consecutive READ Bursts", $time);
+        read            (0, 0, 0);                    // Read   Bank 0, Col 0
+        nop             (bl/2-1);
+        read            (0, 4, 0);                    // Read   Bank 0, Col 4
+        nop             (rl + bl/2);
+
+        $display ("%m at time %t: Figure 23: Nonconsecutive READ Bursts", $time);
+        read            (0, 0, 0);                    // Read   Bank 0, Col 0
+        nop             (bl/2);
+        read            (0, 4, 0);                    // Read   Bank 0, Col 4
+        nop             (rl + bl/2);
+
+        $display ("%m at time %t: Figure 24: READ Interrupted by READ", $time);
+        read            (0, 0, 0);                    // Read   Bank 0, Col 0
+        nop             (tccd-1);
+        read            (1, 0, 0);                    // Read   Bank 0, Col 0
+        nop             (rl + bl/2);
+
+        $display ("%m at time %t: Figure 25 & 26: READ to PRECHARGE", $time);
+        read            (0, 0, 0);                    // Read   Bank 0, Col 0
+        nop             (al + bl/2 + trtp - 2);
+        precharge       (0, 0);                       // Precharge Bank 0
+        nop             (trp-1);
+
+        activate        (0, 0);                       // Activate Bank 0, Row 0
+        nop             (trcd-1);
+        $display ("%m at time %t: Figure 27: READ to WRITE", $time);
+        read            (0, 0, 0);                    // Read   Bank 0, Col 0
+        nop             (rl + bl/2 - wl);
+        write           (0, 0, 1, 0, 'h0123);         // Write  Bank 0, Col 0
+        nop             (wl + bl/2 + twr + trp-1);
+
+        activate        (0, 0);                       // Activate Bank 0, Row 0
+        nop             (trcd-1);
+        $display ("%m at time %t: Figure 36: Nonconsecutive WRITE to WRITE", $time);
+        write           (0, 0, 0, 0, 'h0123);         // Write  Bank 0, Col 0
+        nop             (bl/2);
+        write           (0, 4, 0, 0, 'h0123);         // Write  Bank 0, Col 0
+        nop             (wl + bl/2);
+
+        $display ("%m at time %t: Figure 37: Random WRITE Cycles", $time);
+        write           (0, 0, 0, 0, 'h0123);         // Write  Bank 0, Col 0
+        nop             (bl/2-1);
+        write           (0, 4, 0, 0, 'h0123);         // Write  Bank 0, Col 0
+        nop             (wl + bl/2);
+
+        $display ("%m at time %t: Figure 37: Figure 38: WRITE Interrupted by WRITE", $time);
+        write           (0, 0, 0, 0, 'h0123);         // Write  Bank 0, Col 0
+        nop             (tccd-1);
+        write           (1, 4, 0, 0, 'h0123);         // Write  Bank 0, Col 0
+        nop             (wl + bl/2);
+
+        $display ("%m at time %t: Figure 39: WRITE to READ", $time);
+        write           (0, 0, 0, 0, 'h0123);         // Write  Bank 0, Col 0
+        nop             (wl + bl/2 + twtr-1);
+        read_verify     (0, 0, 0, 0, 'h0123);         // Read   Bank 0, Col 0
+        nop             (rl + bl/2);
+
+        $display ("%m at time %t: Figure 40: WRITE to PRECHARGE", $time);
+        write           (0, 0, 0, 0, 'h0123);         // Write  Bank 0, Col 0
+        nop             (wl + bl/2 + twr-1);
+        precharge       (0, 1);                       // Precharge all banks
+        nop             (trp-1);
+
+        // odt Section
+        $display ("%m at time %t: Figure 60: odt Timing for Active or Fast-Exit Power-Down Mode", $time);
+        odt             = 1'b1;
+        nop             (1);
+        odt             = 1'b0;
+        nop             (tanpd);
+
+        $display ("%m at time %t: Figure 61: odt timing for Slow-Exit or Precharge Power-Down Modes", $time);
+        cke             = 1'b0;
+        @(negedge ck);
+        odt             = 1'b1;
+        @(negedge ck);
+        odt             = 1'b0;
+        repeat(tanpd)@(negedge ck);
+        nop             (taxpd);
+
+        $display ("%m at time %t: Figure 62 & 63: odt Transition Timings when Entering Power-Down Mode", $time);
+        odt             = 1'b1;
+        nop             (tanpd);
+        power_down      (tcke);
+
+        // Self Refresh Section
+        nop             (taxpd);
+        odt             = 1'b0;
+        nop             (3); // taofd
+        self_refresh    (tcke);
+        nop             (tdllk);
+        nop             (tcke);
+
+        test_done;
+    end
diff --git a/sim/verilog/micron_2048Mb_ddr2/tb.do b/sim/verilog/micron_2048Mb_ddr2/tb.do
new file mode 100644
index 0000000..7f5f482
--- /dev/null
+++ b/sim/verilog/micron_2048Mb_ddr2/tb.do
@@ -0,0 +1,31 @@
+#########################################################################################
+#
+#   Disclaimer   This software code and all associated documentation, comments or other 
+#  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+#                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+#                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+#                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+#                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+#                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+#                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+#                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+#                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+#                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+#                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+#                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+#                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+#                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+#                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+#                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+#                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+#                limitation of liability for consequential or incidental damages, the 
+#                above limitation may not apply to you.
+#
+#                Copyright 2003 Micron Technology, Inc. All rights reserved.
+#
+#########################################################################################
+
+vlog -novopt ddr2.v tb.v
+vsim -novopt tb
+add wave -p sdramddr2/*
+run -all
diff --git a/sim/verilog/micron_2048Mb_ddr2/tb.v b/sim/verilog/micron_2048Mb_ddr2/tb.v
new file mode 100644
index 0000000..a08db2f
--- /dev/null
+++ b/sim/verilog/micron_2048Mb_ddr2/tb.v
@@ -0,0 +1,468 @@
+/****************************************************************************************
+*
+*    File Name:  tb.v
+*
+* Dependencies:  ddr2.v, ddr2_parameters.vh
+*
+*  Description:  Micron SDRAM DDR2 (Double Data Rate 2) test bench
+*
+*         Note: -Set simulator resolution to "ps" accuracy
+*               -Set Debug = 0 to disable $display messages
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+
+// DO NOT CHANGE THE TIMESCALE
+
+`timescale 1ps / 1ps
+
+module tb;
+
+`include "ddr2_parameters.vh"
+
+    // ports
+    reg                         ck;
+    wire                        ck_n = ~ck;
+    reg                         cke;
+    reg                         cs_n;
+    reg                         ras_n;
+    reg                         cas_n;
+    reg                         we_n;
+    reg           [BA_BITS-1:0] ba;
+    reg         [ADDR_BITS-1:0] a;
+    wire          [DM_BITS-1:0] dm;
+    wire          [DQ_BITS-1:0] dq;
+    wire         [DQS_BITS-1:0] dqs;
+    wire         [DQS_BITS-1:0] dqs_n;
+    wire         [DQS_BITS-1:0] rdqs_n;
+    reg                         odt;
+
+    // mode registers
+    reg         [ADDR_BITS-1:0] mode_reg0;                                 //Mode Register
+    reg         [ADDR_BITS-1:0] mode_reg1;                                 //Extended Mode Register
+    wire                  [2:0] cl       = mode_reg0[6:4];                 //CAS Latency
+    wire                        bo       = mode_reg0[3];                   //Burst Order
+    wire                  [7:0] bl       = (1<<mode_reg0[2:0]);            //Burst Length
+    wire                        rdqs_en  = mode_reg1[11];                  //RDQS Enable
+    wire                        dqs_n_en = ~mode_reg1[10];                 //dqs# Enable
+    wire                  [2:0] al       = mode_reg1[5:3];                 //Additive Latency
+    wire                  [3:0] rl       = al + cl;                        //Read Latency
+    wire                  [3:0] wl       = al + cl-1'b1;                   //Write Latency
+    
+    // dq transmit
+    reg                         dq_en;
+    reg           [DM_BITS-1:0] dm_out;
+    reg           [DQ_BITS-1:0] dq_out;
+    reg                         dqs_en;
+    reg          [DQS_BITS-1:0] dqs_out;
+    assign                      dm       = dq_en ? dm_out : {DM_BITS{1'bz}};
+    assign                      dq       = dq_en ? dq_out : {DQ_BITS{1'bz}};
+    assign                      dqs      = dqs_en ? dqs_out : {DQS_BITS{1'bz}};
+    assign                      dqs_n    = (dqs_en & dqs_n_en) ? ~dqs_out : {DQS_BITS{1'bz}};
+
+    // dq receive
+    reg           [DM_BITS-1:0] dm_fifo [2*(AL_MAX+CL_MAX)+BL_MAX:0];
+    reg           [DQ_BITS-1:0] dq_fifo [2*(AL_MAX+CL_MAX)+BL_MAX:0];
+    wire          [DQ_BITS-1:0] q0, q1, q2, q3;
+    reg                   [1:0] burst_cntr;
+    assign                      rdqs_n   = {DQS_BITS{1'bz}};
+
+    // timing definition in tCK units
+    real                        tck;
+    wire                 [11:0] taa      = ceil(CL_TIME/tck);
+    wire                 [11:0] tanpd    = TANPD;
+    wire                 [11:0] taond    = TAOND;
+    wire                 [11:0] taofd    = ceil(TAOFD);
+    wire                 [11:0] taxpd    = TAXPD;
+    wire                 [11:0] tccd     = TCCD;
+    wire                 [11:0] tcke     = TCKE;
+    wire                 [11:0] tdllk    = TDLLK;
+    wire                 [11:0] tfaw     = ceil(TFAW/tck);
+    wire                 [11:0] tmod     = ceil(TMOD/tck);
+    wire                 [11:0] tmrd     = TMRD;
+    wire                 [11:0] tras     = ceil(TRAS_MIN/tck);
+    wire                 [11:0] trc      = TRC;
+    wire                 [11:0] trcd     = ceil(TRCD/tck);
+    wire                 [11:0] trfc     = ceil(TRFC_MIN/tck);
+    wire                 [11:0] trp      = ceil(TRP/tck);
+    wire                 [11:0] trrd     = ceil(TRRD/tck);
+    wire                 [11:0] trtp     = ceil(TRTP/tck);
+    wire                 [11:0] twr      = ceil(TWR/tck);
+    wire                 [11:0] twtr     = ceil(TWTR/tck);
+    wire                 [11:0] txard    = TXARD;
+    wire                 [11:0] txards   = TXARDS;
+    wire                 [11:0] txp      = TXP;
+    wire                 [11:0] txsnr    = ceil(TXSNR/tck);
+    wire                 [11:0] txsrd    = TXSRD;
+
+    initial begin
+        $timeformat (-9, 1, " ns", 1);
+`ifdef period
+        tck <= `period; 
+`else
+        tck <= TCK_MIN;
+`endif
+        ck <= 1'b1;
+    end
+
+    // component instantiation
+    ddr2 sdramddr2 (
+        ck, 
+        ck_n, 
+        cke, 
+        cs_n, 
+        ras_n, 
+        cas_n, 
+        we_n, 
+        dm, 
+        ba, 
+        a, 
+        dq, 
+        dqs,
+        dqs_n,
+        rdqs_n,
+        odt
+    );
+
+    // clock generator
+    always @(posedge ck) begin
+      ck <= #(tck/2) 1'b0;
+      ck <= #(tck) 1'b1;
+    end
+
+    function integer ceil;
+        input number;
+        real number;
+        if (number > $rtoi(number))
+            ceil = $rtoi(number) + 1;
+        else
+            ceil = number;
+    endfunction
+
+    function integer max;
+        input arg1;
+        input arg2;
+        integer arg1;
+        integer arg2;
+        if (arg1 > arg2)
+            max = arg1;
+        else
+            max = arg2;
+    endfunction
+
+    task power_up;
+        begin
+            cke    <= 1'b0;
+            odt    <= 1'b0;
+            repeat(10) @(negedge ck);
+            cke    <= 1'b1;
+            nop (400000/tck+1);
+        end
+    endtask
+
+    task load_mode;
+        input   [BA_BITS-1:0] bank;
+        input [ADDR_BITS-1:0] addr;
+        begin
+            case (bank)
+                0: mode_reg0 = addr;
+                1: mode_reg1 = addr;
+            endcase
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b0;
+            cas_n <= 1'b0;
+            we_n  <= 1'b0;
+            ba    <= bank;
+            a     <= addr;
+            @(negedge ck);
+        end
+    endtask
+
+    task refresh;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b0;
+            cas_n <= 1'b0;
+            we_n  <= 1'b1;
+            @(negedge ck);
+        end
+    endtask
+     
+    task precharge;
+        input [BA_BITS-1:0] bank;
+        input               ap; //precharge all
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b0;
+            cas_n <= 1'b1;
+            we_n  <= 1'b0;
+            ba    <= bank;
+            a     <= (ap<<10);
+            @(negedge ck);
+        end
+    endtask
+     
+    task activate;
+        input   [BA_BITS-1:0] bank;
+        input  [ROW_BITS-1:0] row;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b0;
+            cas_n <= 1'b1;
+            we_n  <= 1'b1;
+            ba    <= bank;
+            a     <=  row;
+            @(negedge ck);
+        end
+    endtask
+
+    //write task supports burst lengths <= 8
+    task write;
+        input   [BA_BITS-1:0] bank;
+        input  [COL_BITS-1:0] col;
+        input                 ap; //Auto Precharge
+        input [8*DM_BITS-1:0] dm;
+        input [8*DQ_BITS-1:0] dq;
+        reg   [ADDR_BITS-1:0] atemp [1:0];
+        integer i;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b1;
+            cas_n <= 1'b0;
+            we_n  <= 1'b0;
+            ba    <= bank;
+            atemp[0] = col & 10'h3ff;   //addr[ 9: 0] = COL[ 9: 0]
+            atemp[1] = (col>>10)<<11;   //addr[ N:11] = COL[ N:10]
+            a     <= atemp[0] | atemp[1] | (ap<<10);
+            for (i=0; i<=bl; i=i+1) begin
+
+                dqs_en <= #(wl*tck + i*tck/2) 1'b1;
+                if (i%2 == 0) begin
+                    dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b0}};
+                end else begin
+                    dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b1}};
+                end
+
+                dq_en  <= #(wl*tck + i*tck/2 + tck/4) 1'b1;
+                dm_out <= #(wl*tck + i*tck/2 + tck/4) dm>>i*DM_BITS;
+                dq_out <= #(wl*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS;
+            end
+            dqs_en <= #(wl*tck + bl*tck/2 + tck/2) 1'b0;
+            dq_en  <= #(wl*tck + bl*tck/2 + tck/4) 1'b0;
+            @(negedge ck);  
+        end
+    endtask
+
+    // read without data verification
+    task read;
+        input    [BA_BITS-1:0] bank;
+        input   [COL_BITS-1:0] col;
+        input                  ap; //Auto Precharge
+        reg    [ADDR_BITS-1:0] atemp [1:0];
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b1;
+            cas_n <= 1'b0;
+            we_n  <= 1'b1;
+            ba    <= bank;
+            atemp[0] = col & 10'h3ff;   //addr[ 9: 0] = COL[ 9: 0]
+            atemp[1] = (col>>10)<<11;   //addr[ N:11] = COL[ N:10]
+            a     <= atemp[0] | atemp[1] | (ap<<10);
+            @(negedge ck);
+        end
+    endtask
+
+    task nop;
+        input [31:0] count;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b1;
+            cas_n <= 1'b1;
+            we_n  <= 1'b1;
+            repeat(count) @(negedge ck);
+        end
+    endtask
+
+    task deselect;
+        input [31:0] count;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b1;
+            ras_n <= 1'b1;
+            cas_n <= 1'b1;
+            we_n  <= 1'b1;
+            repeat(count) @(negedge ck);
+        end
+    endtask
+
+    task power_down;
+        input [31:0] count;
+        begin
+            cke   <= 1'b0;
+            cs_n  <= 1'b1;
+            ras_n <= 1'b1;
+            cas_n <= 1'b1;
+            we_n  <= 1'b1;
+            repeat(count) @(negedge ck);
+        end
+    endtask
+
+    task self_refresh;
+        input [31:0] count;
+        begin
+            cke   <= 1'b0;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b0;
+            cas_n <= 1'b0;
+            we_n  <= 1'b1;
+            cs_n  <= #(tck) 1'b1;
+            ras_n <= #(tck) 1'b1;
+            cas_n <= #(tck) 1'b1;
+            we_n  <= #(tck) 1'b1;
+            repeat(count) @(negedge ck);
+        end
+    endtask
+
+    // read with data verification
+    task read_verify;
+        input   [BA_BITS-1:0] bank;
+        input  [COL_BITS-1:0] col;
+        input                 ap; //Auto Precharge
+        input [8*DM_BITS-1:0] dm; //Expected Data Mask
+        input [8*DQ_BITS-1:0] dq; //Expected Data
+        integer i;
+        begin
+            read (bank, col, ap);
+            for (i=0; i<bl; i=i+1) begin
+                dm_fifo[2*rl + i] = dm >> (i*DM_BITS);
+                dq_fifo[2*rl + i] = dq >> (i*DQ_BITS);
+            end
+        end
+    endtask
+
+    // receiver(s) for data_verify process
+    dqrx dqrx[DQS_BITS-1:0] (dqs, dq, q0, q1, q2, q3);
+
+    // perform data verification as a result of read_verify task call
+    always @(ck) begin:data_verify
+        integer i;
+        integer j;
+        reg [DQ_BITS-1:0] bit_mask;
+        reg [DM_BITS-1:0] dm_temp;
+        reg [DQ_BITS-1:0] dq_temp;
+        
+        for (i = !ck; (i < 2/(2.0 - !ck)); i=i+1) begin
+            if (dm_fifo[i] === {DM_BITS{1'bx}}) begin
+                burst_cntr = 0;
+            end else begin
+
+                dm_temp = dm_fifo[i];
+                for (j=0; j<DQ_BITS; j=j+1) begin
+                    bit_mask[j] = !dm_temp[j/8];
+                end
+
+                case (burst_cntr)
+                    0: dq_temp =  q0;
+                    1: dq_temp =  q1;
+                    2: dq_temp =  q2;
+                    3: dq_temp =  q3;
+                endcase
+                //if ( ((dq_temp & bit_mask) === (dq_fifo[i] & bit_mask)))
+                //    $display ("%m at time %t: INFO: Successful read data compare.  Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
+                if ((dq_temp & bit_mask) !== (dq_fifo[i] & bit_mask))
+                    $display ("%m at time %t: ERROR: Read data miscompare.  Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
+
+                burst_cntr = burst_cntr + 1;
+            end
+        end
+
+        if (ck) begin
+            if (dm_fifo[2] === {DM_BITS{1'bx}}) begin
+                dqrx[0%DQS_BITS].ptr <= 0; // v2k syntax
+                dqrx[1%DQS_BITS].ptr <= 0; // v2k syntax
+                dqrx[2%DQS_BITS].ptr <= 0; // v2k syntax
+                dqrx[3%DQS_BITS].ptr <= 0; // v2k syntax
+            end
+        end else begin
+            for (i=0; i<=(2*(AL_MAX+CL_MAX)+BL_MAX); i=i+1) begin
+                dm_fifo[i] = dm_fifo[i+2];
+                dq_fifo[i] = dq_fifo[i+2];
+            end
+        end
+    end
+
+    // End-of-test triggered in 'subtest.vh'
+    task test_done;
+        begin
+            $display ("%m at time %t: INFO: Simulation is Complete", $time);
+            $stop(0);
+        end
+    endtask
+
+    // Test included from external file
+    `include "subtest.vh"
+
+endmodule
+
+module dqrx (
+    dqs, dq, q0, q1, q2, q3
+);
+
+    `include "ddr2_parameters.vh"
+
+    input  dqs;
+    input  [DQ_BITS/DQS_BITS-1:0] dq;
+    output [DQ_BITS/DQS_BITS-1:0] q0;
+    output [DQ_BITS/DQS_BITS-1:0] q1;
+    output [DQ_BITS/DQS_BITS-1:0] q2;
+    output [DQ_BITS/DQS_BITS-1:0] q3;
+
+    reg [DQ_BITS/DQS_BITS-1:0] q [3:0];
+
+    assign q0  = q[0];
+    assign q1  = q[1];
+    assign q2  = q[2];
+    assign q3  = q[3];
+
+    reg [1:0] ptr;
+    reg dqs_q;
+
+    always @(dqs) begin
+        if (dqs ^ dqs_q) begin
+            #(TDQSQ + 1);
+            q[ptr] <= dq;
+            ptr <= (ptr + 1)%4;
+        end
+        dqs_q <= dqs;
+    end
+    
+endmodule
diff --git a/sim/verilog/micron_mobile_ddr/1024Mb_mobile_ddr_parameters.vh b/sim/verilog/micron_mobile_ddr/1024Mb_mobile_ddr_parameters.vh
new file mode 100644
index 0000000..077b064
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/1024Mb_mobile_ddr_parameters.vh
@@ -0,0 +1,167 @@
+/****************************************************************************************
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2005 Micron Technology, Inc. All rights reserved.
+*
+*
+*	Revisions:	 baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK.  Fixed.
+*									Added ROW_BITS & BA_BITS for compatibility w/our system.
+*									Removed part size parameter.
+*
+****************************************************************************************/
+
+    //            Parameters current with 1024Mb datasheet rev C (10/02/07)
+    // 04.17.08 - Consolidated 1024Mb and T48M designs; Updated to rev E (03/08)
+    // 12.10.08 - Updated to datasheet rev G (07/08)
+
+
+                                          // SYMBOL UNITS DESCRIPTION
+                                          // ------ ----- -----------
+`ifdef sg5                                //              Timing Parameters for -5 (CL = 3)
+    parameter tAC3_max         =     5.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     5.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.40; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    15.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     2.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =    10.0; // tXP    ns    Exit power-down to first valid cmd Note: spec'd as 2 * tCK
+`else `ifdef sg54                         //              Timing Parameters for -6 (CL = 3)
+    parameter tAC3_max         =     5.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     5.4; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     5.4; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    58.2; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    16.2; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    16.2; // tRP    ns    Precharge command period
+    parameter tRRD             =    10.8; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     2.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =    10.8; // tXP    ns    Exit power-down to first valid cmd Note: spec'd as 2 * tCK
+`else `ifdef sg6                          //              Timing Parameters for -6 (CL = 3)
+    parameter tAC3_max         =     5.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    18.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    18.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     1.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =    12.0; // tXP    ns    Exit power-down to first valid cmd Note: spec'd as 2 * tCK
+`else `define sg75                        //              Timing Parameters for -75 (CL = 3)
+    parameter tAC3_max         =     6.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.60; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     6.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    45.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    75.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    22.5; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    22.5; // tRP    ns    Precharge command period
+    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     1.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =    15.0; // tXP    ns    Exit power-down to first valid cmd Note: spec'd as 2 * tCK
+`endif `endif `endif
+
+    parameter tAC2_min         =     2.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC3_min         =     2.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tLZ              =     1.0; // tLZ    ns    Data-out low Z window from CK/CK#
+    parameter tMRD             =     2.0; // tMRD  tCK    Load Mode Register command cycle time
+    parameter tRFC             =   110.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tSRC             =     1.0; // tSRC  tCK    SRR READ command to first valid command Note: model adds CL to this value                                           
+    parameter tSRR             =     2.0; // tSRR  tCK    SRR command to SRR READ command                                                  
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+    parameter tCH_MAX          =    0.55;                 // Clk high level width
+    parameter tCH_MIN          =    0.45;                 // Clk high level width
+    parameter tCL_MAX          =    0.55;                 // Clk low level width
+    parameter tCL_MIN          =    0.45;                 // Clk low level width
+    parameter tCKE             =    1.0 ;                 // Minimum tCKE High/Low time (in tCK's)
+    parameter CL_MAX           =    3   ;                 // Maximum CAS Latency
+    parameter BL_MAX           =    16  ;
+
+
+
+
+     // Size Parameters based on Part Width
+`ifdef x16
+    parameter ADDR_BITS        =      14; // Set this parameter to control how many Address bits are used
+    parameter ROW_BITS         =      14; // Set this parameter to control how many Row bits are used
+    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
+    parameter BA_BITS          =       2; // Set this parameter to control how many Bank bits are used
+`else `define x32
+  `ifdef RP // reduced page mode
+    parameter ADDR_BITS        =      14; // Set this parameter to control how many Address bits are used
+    parameter ROW_BITS         =      14; // Set this parameter to control how many Row bits are used
+    parameter DQ_BITS          =      32; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       4; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       4; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =       9; // Set this parameter to control how many Column bits are used
+    parameter BA_BITS          =       2; // Bank bits
+  `else
+    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+    parameter ROW_BITS         =      13; // Set this parameter to control how many Row bits are used
+    parameter DQ_BITS          =      32; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       4; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       4; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
+    parameter BA_BITS          =       2; // Bank bits
+  `endif
+`endif
+
+    // For use with the Multi Chip Package
+`ifdef DUAL_RANK
+    parameter CS_BITS          =       2; // Set this parameter to control how many Chip Select bits are used
+    parameter RANKS            =       2; // Set this parameter to control how many Ranks on the mcp are used
+`else 
+    parameter CS_BITS          =       2; // Set this parameter to control how many Chip Select bits are used
+    parameter RANKS            =       1; // Set this parameter to control how many Ranks on the mcp are used
+`endif
+
+    parameter full_mem_bits    = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
+    parameter part_mem_bits    = 10;                   // Set this parameter to control how many unique addresses are used
+    parameter part_size        = 1024;                 // Set this parameter to indicate part size(1024Mb, 512Mb, 256Mb, 128Mb)
+    
+
diff --git a/sim/verilog/micron_mobile_ddr/128Mb_mobile_ddr_parameters.vh b/sim/verilog/micron_mobile_ddr/128Mb_mobile_ddr_parameters.vh
new file mode 100644
index 0000000..c2a2fd7
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/128Mb_mobile_ddr_parameters.vh
@@ -0,0 +1,153 @@
+/****************************************************************************************
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2005 - 2006 Micron Technology, Inc. All rights reserved.
+*
+*
+*	Revisions:	 baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK - fixed.
+*									Added ROW_BITS & BA_BITS for compatibility w/our system.
+*									Also changed Col bits from 10 to 9 per spec.
+*									Removed x32 option and part size parameter.
+*
+****************************************************************************************/
+
+    //            Parameters current with 128Mb datasheet rev J (11/05)
+    // 04.17.08 - Parameters current with 128Mb Data sheet rev A (04/08)
+
+    // Timing parameters based on Speed Grade
+
+                                          // SYMBOL UNITS DESCRIPTION
+                                          // ------ ----- -----------
+`ifdef sg5                                //              Timing Parameters for -5 (CL = 3)
+    parameter tAC3_max         =     5.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     5.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.40; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    15.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     2.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     5.0; // tXP    ns    Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
+`else `ifdef sg54                         //              Timing Parameters for -6 (CL = 3)
+    parameter tAC3_max         =     5.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     5.4; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     5.4; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    58.2; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    16.2; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    16.2; // tRP    ns    Precharge command period
+    parameter tRRD             =    10.8; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     2.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     5.4; // tXP    ns    Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
+`else `ifdef sg6                          //              Timing Parameters for -6 (CL = 3)
+    parameter tAC3_max         =     5.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.50; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    18.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    18.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     2.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     6.0; // tXP    ns    Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
+`else `define sg75                        //              Timing Parameters for -75 (CL = 3)
+    parameter tAC3_max         =     6.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.60; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     6.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    45.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    75.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    22.5; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    22.5; // tRP    ns    Precharge command period
+    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     1.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     7.5; // tXP    ns    Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
+`endif `endif `endif
+
+    parameter tAC2_min         =     2.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC3_min         =     2.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tLZ              =     1.0; // tLZ    ns    Data-out low Z window from CK/CK#
+    parameter tMRD             =     2.0; // tMRD  tCK    Load Mode Register command cycle time
+    parameter tRFC             =    80.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tSRC             =     1.0; // tSRC  tCK    SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb Parts)
+    parameter tSRR             =     2.0; // tSRR  tCK    SRR command to SRR READ command         (Not Applicable for 128Mb, 256Mb Parts)
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+
+    // Size Parameters based on Part Width
+`ifdef x16
+    parameter ADDR_BITS        =      12; // Set this parameter to control how many Address bits are used
+    parameter ROW_BITS         =      12; // Set this parameter to control how many Row bits are used
+    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =       9; // Set this parameter to control how many Column bits are used
+    parameter BA_BITS          =       2; // Bank bits
+`else `define x32
+    parameter ADDR_BITS        =      12; // Set this parameter to control how many Address bits are used
+    parameter ROW_BITS         =      12; // Set this parameter to control how many Row bits are used
+    parameter DQ_BITS          =      32; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       4; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       4; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =       8; // Set this parameter to control how many Column bits are used
+    parameter BA_BITS          =       2; // Bank bits
+`endif
+
+    // For use with the Multi Chip Package
+`ifdef DUAL_RANK
+    parameter CS_BITS          =       2; // Set this parameter to control how many Chip Select bits are used
+    parameter RANKS            =       2; // Set this parameter to control how many Ranks on the mcp are used
+`else 
+    parameter CS_BITS          =       2; // Set this parameter to control how many Chip Select bits are used
+    parameter RANKS            =       1; // Set this parameter to control how many Ranks on the mcp are used
+`endif
+
+    parameter full_mem_bits    = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
+    parameter part_mem_bits    = 10;                   // Set this parameter to control how many unique addresses are used
+    parameter part_size        = 128;                  // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)
+    parameter tCH_MAX          = 0.55;                 // Clk high level width
+    parameter tCH_MIN          = 0.45;                 // Clk high level width
+    parameter tCL_MAX          = 0.55;                 // Clk low level width
+    parameter tCL_MIN          = 0.45;                 // Clk low level width
+    parameter tCKE             = 2.0;                  // Minimum tCKE High/Low time (in tCK's)
+    parameter CL_MAX           = 3;                    // Maximum CAS Latency
+    parameter BL_MAX           =    16  ;
diff --git a/sim/verilog/micron_mobile_ddr/2048Mb_mobile_ddr_parameters.vh b/sim/verilog/micron_mobile_ddr/2048Mb_mobile_ddr_parameters.vh
new file mode 100644
index 0000000..9653ab4
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/2048Mb_mobile_ddr_parameters.vh
@@ -0,0 +1,179 @@
+/****************************************************************************************
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2005 Micron Technology, Inc. All rights reserved.
+*
+*
+*	Revisions:	 baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK.  Fixed.
+*									Added ROW_BITS & BA_BITS for compatibility w/our system.
+*									Removed part size parameter.
+*
+****************************************************************************************/
+
+    //            Parameters current with 2048Mb LPDDR SDRAM
+    // 04.26.10 - Based on Rev 0.7 04/09EN (DDS)
+
+
+                                          // SYMBOL UNITS DESCRIPTION
+                                          // ------ ----- -----------
+`ifdef sg5                                //              Timing Parameters for -5 (CL = 3)
+    parameter tAC3_max         =     4.8; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     4.8; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     4.8; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.40; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     4.8; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    14.4; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    14.4; // tRP    ns    Precharge command period
+    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     2.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     6.0; // tXP    ns    Exit power-down to first valid cmd Note: spec'd as 2 * tCK
+    parameter tWR              =    14.4; // tWR    ns    Write recovery time
+`else `ifdef sg54                         //              Timing Parameters for -6 (CL = 3)
+    parameter tAC3_max         =     5.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     5.4; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     5.4; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    41.8; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    58.2; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    16.2; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    16.2; // tRP    ns    Precharge command period
+    parameter tRRD             =    10.8; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     2.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     6.0; // tXP    ns    Exit power-down to first valid cmd Note: spec'd as 2 * tCK
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`else `ifdef sg6                          //              Timing Parameters for -6 (CL = 3)
+    parameter tAC3_max         =     5.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    41.8; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    18.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    18.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     1.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     6.0; // tXP    ns    Exit power-down to first valid cmd Note: spec'd as 2 * tCK
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`else `define sg75                        //              Timing Parameters for -75 (CL = 3)
+    parameter tAC3_max         =     6.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.60; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     6.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    45.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    67.5; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    22.5; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    22.5; // tRP    ns    Precharge command period
+    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     1.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =    7.50; // tXP    ns    Exit power-down to first valid cmd Note: spec'd as 2 * tCK
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+`endif `endif `endif
+
+    parameter tAC2_min         =     2.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC3_min         =     2.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tLZ              =     1.0; // tLZ    ns    Data-out low Z window from CK/CK#
+    parameter tMRD             =     2.0; // tMRD  tCK    Load Mode Register command cycle time
+    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tSRC             =     1.0; // tSRC  tCK    SRR READ command to first valid command Note: model adds CL to this value                                           
+    parameter tSRR             =     2.0; // tSRR  tCK    SRR command to SRR READ command                                                  
+    parameter tCH_MAX          =    0.55;                 // Clk high level width
+    parameter tCH_MIN          =    0.45;                 // Clk high level width
+    parameter tCL_MAX          =    0.55;                 // Clk low level width
+    parameter tCL_MIN          =    0.45;                 // Clk low level width
+    parameter tCKE             =    1.0 ;                 // Minimum tCKE High/Low time (in tCK's)
+    parameter CL_MAX           =    3   ;                 // Maximum CAS Latency
+    parameter BL_MAX           =    16  ;
+
+
+
+
+     // Size Parameters based on Part Width
+`ifdef x16
+    `ifdef RP
+        parameter ADDR_BITS    =      15; // Set this parameter to control how many Address bits are used
+        parameter ROW_BITS     =      15; // Set this parameter to control how many Row bits are used
+        parameter DQ_BITS      =      16; // Set this parameter to control how many Data bits are used
+        parameter DQS_BITS     =       2; // Set this parameter to control how many DQS bits are used
+        parameter DM_BITS      =       2; // Set this parameter to control how many DM bits are used
+        parameter COL_BITS     =      10; // Set this parameter to control how many Column bits are used
+        parameter BA_BITS      =       2; // Set this parameter to control how many Bank bits are used
+    `else
+        parameter ADDR_BITS    =      14; // Set this parameter to control how many Address bits are used
+        parameter ROW_BITS     =      14; // Set this parameter to control how many Row bits are used
+        parameter DQ_BITS      =      16; // Set this parameter to control how many Data bits are used
+        parameter DQS_BITS     =       2; // Set this parameter to control how many DQS bits are used
+        parameter DM_BITS      =       2; // Set this parameter to control how many DM bits are used
+        parameter COL_BITS     =      11; // Set this parameter to control how many Column bits are used
+        parameter BA_BITS      =       2; // Set this parameter to control how many Bank bits are used
+    `endif
+`else `define x32
+    `ifdef RP // reduced page mode
+        parameter ADDR_BITS    =      15; // Set this parameter to control how many Address bits are used
+        parameter ROW_BITS     =      15; // Set this parameter to control how many Row bits are used
+        parameter DQ_BITS      =      32; // Set this parameter to control how many Data bits are used
+        parameter DQS_BITS     =       4; // Set this parameter to control how many DQS bits are used
+        parameter DM_BITS      =       4; // Set this parameter to control how many DM bits are used
+        parameter COL_BITS     =       9; // Set this parameter to control how many Column bits are used
+        parameter BA_BITS      =       2; // Bank bits
+    `else
+        parameter ADDR_BITS    =      14; // Set this parameter to control how many Address bits are used
+        parameter ROW_BITS     =      14; // Set this parameter to control how many Row bits are used
+        parameter DQ_BITS      =      32; // Set this parameter to control how many Data bits are used
+        parameter DQS_BITS     =       4; // Set this parameter to control how many DQS bits are used
+        parameter DM_BITS      =       4; // Set this parameter to control how many DM bits are used
+        parameter COL_BITS     =      10; // Set this parameter to control how many Column bits are used
+        parameter BA_BITS      =       2; // Bank bits
+    `endif
+`endif
+
+    // For use with the Multi Chip Package
+`ifdef DUAL_RANK
+    parameter CS_BITS          =       2; // Set this parameter to control how many Chip Select bits are used
+    parameter RANKS            =       2; // Set this parameter to control how many Ranks on the mcp are used
+`else 
+    parameter CS_BITS          =       2; // Set this parameter to control how many Chip Select bits are used
+    parameter RANKS            =       1; // Set this parameter to control how many Ranks on the mcp are used
+`endif
+
+    parameter full_mem_bits    = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
+    parameter part_mem_bits    = 10;                   // Set this parameter to control how many unique addresses are used
+    parameter part_size        = 2048;                 // Set this parameter to indicate part size(1024Mb, 512Mb, 256Mb, 128Mb)
+    
+
diff --git a/sim/verilog/micron_mobile_ddr/256Mb_mobile_ddr_parameters.vh b/sim/verilog/micron_mobile_ddr/256Mb_mobile_ddr_parameters.vh
new file mode 100644
index 0000000..f2357e2
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/256Mb_mobile_ddr_parameters.vh
@@ -0,0 +1,134 @@
+/****************************************************************************************
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2005 Micron Technology, Inc. All rights reserved.
+*
+*
+*	Revisions:	 baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK.  Fixed.
+*									Added ROW_BITS & BA_BITS for compatibility w/our system.
+*									Also changed x16 Col bits from 8 to 9 per spec.
+*									Removed part size parameter.
+*
+****************************************************************************************/
+
+    //            Parameters current with 256Mb datasheet rev E (05/07)
+    // 04.17.08 - Parameters current with 256Mb Data sheet rev H (03/08)
+
+    // Timing parameters based on Speed Grade
+
+                                          // SYMBOL UNITS DESCRIPTION
+                                          // ------ ----- -----------
+`ifdef sg6                                //              Timing Parameters for -6 (CL = 3)
+    parameter tAC3_max         =     5.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.50; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    18.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    18.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWR              =    12.0; // tWR    ns    Write recovery time
+    parameter tWTR             =     1.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     6.0; // tXP    ns    Exit power-down to first valid cmd
+`else `define sg75                        //              Timing Parameters for -75 (CL = 3)
+    parameter tAC3_max         =     6.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.60; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     6.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    45.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    75.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    22.5; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    22.5; // tRP    ns    Precharge command period
+    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+    parameter tWTR             =     1.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     7.5; // tXP    ns    Exit power-down to first valid cmd
+`endif 
+
+    parameter tAC2_min         =     2.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC3_min         =     2.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tLZ              =     1.0; // tLZ    ns    Data-out low Z window from CK/CK#
+    parameter tMRD             =     2.0; // tMRD  tCK    Load Mode Register command cycle time
+    parameter tRFC             =    70.0; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tSRC             =     1.0; // tSRC  tCK    SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts)
+    parameter tSRR             =     2.0; // tSRR  tCK    SRR command to SRR READ command         (Not Applicable for 128Mb, 256Mb, and 512Mb Parts)
+
+    // Size Parameters based on Part Width
+`ifdef x16
+    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+    parameter ROW_BITS         =      13; // Set this parameter to control how many Row bits are used
+    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =       9; // Set this parameter to control how many Column bits are used
+	parameter BA_BITS          =       2; // Bank bits
+`else `define x32
+    `ifdef RP
+    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+    parameter ROW_BITS         =      13; // Set this parameter to control how many Row bits are used
+    parameter DQ_BITS          =      32; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       4; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       4; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =       8; // Set this parameter to control how many Column bits are used
+    parameter BA_BITS          =       2; // Bank bits
+    `else
+    parameter ADDR_BITS        =      12; // Set this parameter to control how many Address bits are used
+    parameter ROW_BITS         =      12; // Set this parameter to control how many Row bits are used
+    parameter DQ_BITS          =      32; // Set this parameter to control how many Data bits are used
+    parameter DQS_BITS         =       4; // Set this parameter to control how many DQS bits are used
+    parameter DM_BITS          =       4; // Set this parameter to control how many DM bits are used
+    parameter COL_BITS         =       9; // Set this parameter to control how many Column bits are used
+    parameter BA_BITS          =       2; // Bank bits
+    `endif
+`endif
+
+    // For use with the Multi Chip Package
+`ifdef DUAL_RANK
+    parameter CS_BITS          =       2; // Set this parameter to control how many Chip Select bits are used
+    parameter RANKS            =       2; // Set this parameter to control how many Ranks on the mcp are used
+`else 
+    parameter CS_BITS          =       2; // Set this parameter to control how many Chip Select bits are used
+    parameter RANKS            =       1; // Set this parameter to control how many Ranks on the mcp are used
+`endif
+
+    parameter full_mem_bits    = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
+    parameter part_mem_bits    = 10;                  // For fast sim load
+    parameter part_size        = 256;                  // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)
+    parameter tCH_MAX          = 0.55;                 // Clk high level width
+    parameter tCH_MIN          = 0.45;                 // Clk high level width
+    parameter tCL_MAX          = 0.55;                 // Clk low level width
+    parameter tCL_MIN          = 0.45;                 // Clk low level width
+    parameter tCKE             = 2.0;                  // Minimum tCKE High/Low time (in tCK's)
+    parameter CL_MAX           = 3;                    // Maximum CAS Latency
+    parameter BL_MAX           = 16;
+
+
diff --git a/sim/verilog/micron_mobile_ddr/512Mb_mobile_ddr_parameters.vh b/sim/verilog/micron_mobile_ddr/512Mb_mobile_ddr_parameters.vh
new file mode 100644
index 0000000..7c607eb
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/512Mb_mobile_ddr_parameters.vh
@@ -0,0 +1,162 @@
+/****************************************************************************************
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2005 Micron Technology, Inc. All rights reserved.
+*
+*
+*	Revisions:	 baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK.  Fixed.
+*									Added ROW_BITS & BA_BITS for compatibility w/our system.
+*									Removed part size parameter.
+*
+****************************************************************************************/
+
+    // Parameters current with T47M datasheet rev M (07/07)
+    // 04.17.08 - Paramters current with 512Mb Data sheet rev C (03/08)
+    // Timing parameters based on Speed Grade
+
+
+                                          // SYMBOL UNITS DESCRIPTION
+                                          // ------ ----- -----------
+`ifdef sg5                                //              Timing Parameters for -5 (CL = 3)
+    parameter tAC3_max         =     5.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     5.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.40; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    15.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     2.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =    10.0; // tXP    ns    Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
+`else `ifdef sg54                         //              Timing Parameters for -6 (CL = 3)
+    parameter tAC3_max         =     5.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     5.4; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     5.4; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    59.4; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    16.2; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    16.2; // tRP    ns    Precharge command period
+    parameter tRRD             =    10.8; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     2.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =    10.8; // tXP    ns    Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
+`else `ifdef sg6                          //              Timing Parameters for -6 (CL = 3)
+    parameter tAC3_max         =     5.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     6.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.50; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     5.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    18.0; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    18.0; // tRP    ns    Precharge command period
+    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     2.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     6.0; // tXP    ns    Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
+`else `define sg75                        //              Timing Parameters for -75 (CL = 3)
+    parameter tAC3_max         =     6.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC2_max         =     6.5; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK3_min         =     7.5; // tCK    ns    Nominal Clock Cycle Time
+    parameter tCK2_min         =    12.0; // tCK    ns    Nominal Clock Cycle Time
+    parameter tDQSQ            =    0.60; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
+    parameter tHZ3_max         =     6.0; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tHZ2_max         =     6.5; // tHZ    ns    Data-out high Z window from CK/CK#
+    parameter tRAS             =    45.0; // tRAS   ns    Active to Precharge command time
+    parameter tRC              =    75.0; // tRC    ns    Active to Active/Auto Refresh command time
+    parameter tRCD             =    22.5; // tRCD   ns    Active to Read/Write command time
+    parameter tRP              =    22.5; // tRP    ns    Precharge command period
+    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
+    parameter tWTR             =     1.0; // tWTR  tCK    Internal Write-to-Read command delay
+    parameter tXP              =     7.5; // tXP    ns    Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part
+`endif `endif `endif
+
+    parameter tAC2_min         =     2.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tAC3_min         =     2.0; // tAC    ns    Access window of DQ from CK/CK#
+    parameter tLZ              =     1.0; // tLZ    ns    Data-out low Z window from CK/CK#
+    parameter tMRD             =     2.0; // tMRD  tCK    Load Mode Register command cycle time
+    parameter tRFC             =    97.5; // tRFC   ns    Refresh to Refresh Command interval time
+    parameter tSRC             =     1.0; // tSRC  tCK    SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb Parts)
+    parameter tSRR             =     2.0; // tSRR  tCK    SRR command to SRR READ command         (Not Applicable for 128Mb, 256Mb Parts)
+    parameter tWR              =    15.0; // tWR    ns    Write recovery time
+
+     // Size Parameters based on Part Width
+ `ifdef x16
+     parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+     parameter ROW_BITS         =      13; // Set this parameter to control how many Row bits are used
+     parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
+     parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
+     parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
+     parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
+     parameter BA_BITS          =       2; // Bank bits
+ `else `define x32
+     `ifdef RP
+     parameter ADDR_BITS        =      14; // Set this parameter to control how many Address bits are used
+     parameter ROW_BITS         =      14; // Set this parameter to control how many Row bits are used
+     parameter DQ_BITS          =      32; // Set this parameter to control how many Data bits are used
+     parameter DQS_BITS         =       4; // Set this parameter to control how many DQS bits are used
+     parameter DM_BITS          =       4; // Set this parameter to control how many DM bits are used
+     parameter COL_BITS         =       8; // Set this parameter to control how many Column bits are used
+     parameter BA_BITS          =       2; // Bank bits
+     `else
+     parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
+     parameter ROW_BITS         =      13; // Set this parameter to control how many Row bits are used
+     parameter DQ_BITS          =      32; // Set this parameter to control how many Data bits are used
+     parameter DQS_BITS         =       4; // Set this parameter to control how many DQS bits are used
+     parameter DM_BITS          =       4; // Set this parameter to control how many DM bits are used
+     parameter COL_BITS         =       9; // Set this parameter to control how many Column bits are used
+     parameter BA_BITS          =       2; // Bank bits
+     `endif
+`endif
+
+    // For use with the Multi Chip Package
+`ifdef DUAL_RANK
+    parameter CS_BITS          =       2; // Set this parameter to control how many Chip Select bits are used
+    parameter RANKS            =       2; // Set this parameter to control how many Ranks on the mcp are used
+`else 
+    parameter CS_BITS          =       2; // Set this parameter to control how many Chip Select bits are used
+    parameter RANKS            =       1; // Set this parameter to control how many Ranks on the mcp are used
+`endif
+
+    parameter full_mem_bits    = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
+    parameter part_mem_bits    = 10;                   // Set this parameter to control how many unique addresses are used
+    parameter part_size        = 512;                  // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb)
+    parameter tCH_MAX          = 0.55;                 // Clk high level width
+    parameter tCH_MIN          = 0.45;                 // Clk high level width
+    parameter tCL_MAX          = 0.55;                 // Clk low level width
+    parameter tCL_MIN          = 0.45;                 // Clk low level width
+    parameter tCKE             = 1.0;                  // Minimum tCKE High/Low time (in tCK's)
+    parameter CL_MAX           = 3;                    // Maximum CAS Latency
+    parameter BL_MAX           =    16  ;
diff --git a/sim/verilog/micron_mobile_ddr/mobile_ddr.v b/sim/verilog/micron_mobile_ddr/mobile_ddr.v
new file mode 100644
index 0000000..bac5ca1
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/mobile_ddr.v
@@ -0,0 +1,2126 @@
+/****************************************************************************************
+*
+*    File Name:  mobile_ddr.v
+*      Version:  6.03
+*        Model:  BUS Functional
+*
+* Dependencies:  mobile_ddr_parameters.vh
+*
+*  Description:  Micron MOBILE DDR SDRAM
+*
+*   Limitation:  - Doesn't check for 8K-cycle refresh
+*
+*         Note:  - Set simulator resolution to "ps" accuracy
+*                - Set Debug = 0 to disable $display messages
+*                - Model assume Clk and Clk# crossing at both edge
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2008 Micron Technology, Inc. All rights reserved.
+*
+* Rev  Author Date        Changes
+* ---  ------ ----------  ---------------------------------------
+* 1.0  NMB    03/19/02    - Initial Release of Mobile DDR model
+*                           based off of version 5.0 of DDR model
+* 1.1  ritz   12/03/04    - New feature:  1/8th strength driver in Drive Strength (Ext Mode Reg).
+*                           Bugfix - ba[0] ba[1] were swapped for determening ext_mode_enable
+*                           thus ext_mode_reg wasnt being programmed.
+* 1.2  ritz   12/07/04    - Logging transactions in transcript for automated testing
+* 1.3  ritz   01/31/05    - updated to SMG DDR model version 5.2 (dqs edge checking errors fix)
+* 1.4  ritz   02/15/05    - Fixed display.*WRITE to use hex for "data".
+* 1.5  ritz   03/22/05    - Fixed read latency (#0.5 and 2*Read_latency-1) for MMG latency
+* 2.0  bas    07/19/06    - Added PASR support and clk_n checking
+* 3.0  bas    08/07/06    - Added tXP check, tCke check, Power-down/Deep power down enter/exit messages
+                            FULL_MEM fix
+* 3.11 bas    10/18/06    - Added clk spd chk, added RP support, added T48M part, added SRR functionality, changed tMRD checker to measure in tck pos edge, DPD optimization for FULL_MEM mode
+* 3.12 bas    10/19/06    - Fixed PASR in FULL_MEM mode
+* 3.20 bas    10/23/06    - changed tXP check to tPDX check for T25L, Initial release to web
+* 3.30 bas    01/15/07    - Updated T48M Parameters (updated as of 12/06)
+* 3.35 bas    02/28/07    - Model uses tAC correctly to calculate strobe/data launch
+* 3.36 bas    03/05/07    - fixed error messages for different banks interrupting 
+                            reads/writes w/autoprecharge
+* 3.37 bas    03/21/07    - Added T47M Part to 512Mb parameter file
+* 3.40 bas    06/25/07    - Removed RP options from 1024Mb
+                          - Updated 128Mb, 256Mb, and 512Mb parts to 05/07 datasheet
+                          - Updated 1024Mb part to 02/07
+                          - Added illegal Cas Latency check per speed grade
+* 3.40 jwm    08/02/07    - Support for 512Mb T47M
+* 3.80 clk    10/29/07    - Support for 1024Mb T48M
+* 4.00 clk    12/30/07    - Fixed Read terminated by precharge testcase
+* 4.70 clk    03/30/08    - Fixed typo in SRR code
+* 4.80 clk    04/03/08    - Disable clk checking during initialization
+* 4.90 clk    04/16/08    - Fixed tInit, added mpc support, updated t35m timing
+* 5.00 clk    05/14/08    - Fixed back to back auto precharge commands          
+* 5.20 clk    05/21/08    - Fixed read interrupt by pre (BL8), fixed 1024Mb parameter file
+* 5.30 clk    05/22/08    - Fixed DM signal which cause false tWTR errors                    
+              05/27/08    - Rewrote write and read pipelines, strobes
+* 5.40 clk    05/28/08    - Fixed Addressing problem in Burst Order logic
+* 5.50 clk    07/25/08    - Added T36N part type                                   
+* 5.60 clk    09/05/08    - Fixed tXP in 256Mb part type                           
+* 5.70 clk    09/17/08    - Fixed burst term check for write w/ all DM active       
+* 5.80 clk    11/18/08    - Fixed internally latched dq & mask widths
+* 5.90 clk    12/10/08    - Updated T36N parameters to latest datasheet
+* 6.00 clk    03/05/09    - Fixed DQS problem w/ CL = 2, Fix Wr Pipeline during Rd interrupt
+* 6.01 sph    01/20/10    - Added clock stop detection to fix tCH/tCL timing violation
+* 6.02 sph    01/22/10    - Added check for nop/des is used when enter/exit stop clock mode
+* 6.03 sph    06/07/10    - Include all the mobile_ddr_parameters.vh into a single package
+****************************************************************************************/
+
+// DO NOT CHANGE THE TIMESCALE
+// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
+`timescale 1ns / 1ps
+
+module mobile_ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);
+
+`ifdef den128Mb
+    `include "128Mb_mobile_ddr_parameters.vh"
+`elsif den256Mb
+    `include "256Mb_mobile_ddr_parameters.vh"
+`elsif den512Mb
+    `include "512Mb_mobile_ddr_parameters.vh"
+`elsif den1024Mb
+    `include "1024Mb_mobile_ddr_parameters.vh"
+`elsif den2048Mb
+    `include "2048Mb_mobile_ddr_parameters.vh"
+`else
+    // NOTE: Intentionally cause a compile fail here to force the users
+    //       to select the correct component density before continuing
+    ERROR: You must specify component density with +define+den____Mb.
+`endif
+
+    `define MAX_PIPE   2*(CL_MAX + BL_MAX)
+
+    // Port Declarations
+    input                         Clk;
+    input                         Clk_n;
+    input                         Cke;
+    input                         Cs_n;
+    input                         Ras_n;
+    input                         Cas_n;
+    input                         We_n;
+    input     [ADDR_BITS - 1 : 0] Addr;
+    input                 [1 : 0] Ba;
+    inout       [DQ_BITS - 1 : 0] Dq;
+    inout      [DQS_BITS - 1 : 0] Dqs;
+    input       [DM_BITS - 1 : 0] Dm;
+
+    //time variables
+    realtime tXP_chk ;
+    reg  enter_DPD   ;
+    reg  enter_PD    ;
+    reg  enter_APD   ;
+
+    //integer clk checks
+
+    // Internal Wires (fixed width)
+    wire                 [31 : 0] Dq_in;
+    wire                  [3 : 0] Dqs_in;
+    wire                  [3 : 0] Dm_in;
+    
+    assign Dq_in   [DQ_BITS - 1 : 0] = Dq;
+    assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
+    assign Dm_in   [DM_BITS - 1 : 0] = Dm;
+
+    // Data pair
+    reg           [DQ_BITS-1 : 0] dq_rise;
+    reg           [DM_BITS-1 : 0] dm_rise;
+    reg           [DQ_BITS-1 : 0] dq_fall;
+    reg           [DM_BITS-1 : 0] dm_fall;
+    reg         [DM_BITS*2-1 : 0] dm_pair;
+    reg           [DQ_BITS-1 : 0] Dq_buf;
+
+    // Power-down cycle counter
+    reg  [03:00]                  PD_cntr    ;
+
+    // prev cmd value
+
+    reg                           prev_Cs_n  ;
+    reg                           prev_Ras_n ;
+    reg                           prev_Cas_n ;
+    reg                           prev_We_n  ;
+    reg  [01:00]                  prev_Ba    ;
+    reg                           prev_cke   ;
+
+    wire prev_nop = ~prev_Cs_n &  prev_Ras_n &  prev_Cas_n &  prev_We_n ;
+    wire prev_des =  prev_Cs_n ;
+    wire prev_bt  = ~prev_Cs_n &  prev_Ras_n &  prev_Cas_n & ~prev_We_n ;
+    wire prev_rd  = ~prev_Cs_n &  prev_Ras_n & ~prev_Cas_n &  prev_We_n ;
+    reg       Clk_Chk_enable  = 1'b0 ;
+
+    //differential clk
+    reg            diff_ck;
+    always @(posedge Clk)   diff_ck <= Clk;
+    always @(posedge Clk_n) diff_ck <= ~Clk_n;
+
+    //measure clock period
+    realtime clk_period ;
+    realtime pos_clk_edge ;
+    integer  clk_pos_edge_cnt ;
+    always @(posedge diff_ck) begin
+        clk_period = $realtime - pos_clk_edge ;
+        pos_clk_edge = $realtime ;
+        if ((Cke == 1'b1) && (clk_pos_edge_cnt < 2)) begin
+            clk_pos_edge_cnt = clk_pos_edge_cnt + 1 ;
+        end else if (Cke == 1'b0) begin
+            clk_pos_edge_cnt = 2'b00 ;
+        end
+    end
+
+    //measure duty cycle
+    realtime neg_clk_edge ;
+    always @(negedge diff_ck) begin
+        neg_clk_edge = $realtime ;
+    end
+    realtime pos_clk_time ;
+    realtime neg_clk_time ;
+    reg clock_stop = 0;
+
+    // Mode Register
+    reg       [ADDR_BITS - 1 : 0] Mode_reg;
+    reg       [ADDR_BITS - 1 : 0] Ext_Mode_reg;
+    reg       [2*DQ_BITS - 1 : 0] Srr_reg;
+
+
+    // SRR Registers
+    reg                           SRR_read;
+
+    // Internal System Clock
+    reg                           CkeZ, Sys_clk;
+
+    // Internal Dqs initialize
+//    reg                           Dqs_int;
+
+    // Dqs buffer
+    reg                           Dqs_out;
+//    reg        [DQS_BITS - 1 : 0] Dqs_gen;
+    reg                           Dqs_out_en;
+    // Dq buffer
+    reg         [DQ_BITS - 1 : 0] Dq_out_temp;
+    reg         [DQ_BITS - 1 : 0] Dq_out;
+    reg                           Dq_out_en;
+
+    // Read pipeline variables
+    reg           [`MAX_PIPE : 0] Read_pipeline        ;
+    reg                   [1 : 0] Read_bank [0 : 6];
+    reg        [COL_BITS - 1 : 0] Read_cols [0 : 6];
+
+    // Write pipeline variables
+    reg           [`MAX_PIPE :-2] Write_pipeline;
+    reg           [BA_BITS-1 : 0] Write_bank_pipeline [`MAX_PIPE :-2];
+    reg        [COL_BITS - 1 : 0] Write_col_pipeline [`MAX_PIPE :-2];
+
+    // Auto precharge variables
+    reg                     [3:0] Read_precharge_access  ;
+    reg                     [3:0] Read_precharge_pre     ;
+    reg                     [3:0] Write_precharge_access ;
+    reg                     [3:0] Write_precharge_pre    ;
+    integer                       Count_precharge [0:3];
+    reg                           SelfRefresh;
+    reg                     [3:0] Read_precharge_count [3:0] ;
+    reg                     [3:0] Write_precharge_count [3:0];
+
+
+    reg                           wr_ap_display_msg   ;
+    reg                           rd_ap_display_msg   ;
+
+    // Manual precharge variables
+//    reg                   [0 : 6] A10_precharge         ;
+//    reg                   [1 : 0] Bank_precharge [0 : 6];
+//    reg                   [0 : 6] Cmnd_precharge        ;
+
+    // Burst terminate variables
+//    reg                           Cmnd_bst [0 : 6];
+
+    // tMRD counter
+    integer MRD_cntr  ;
+    integer SRR_cntr  ;
+    integer SRC_cntr  ;
+    integer tWTR_cntr ;
+
+    // Memory Banks
+    `ifdef FULL_MEM
+        reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<<full_mem_bits)-1];
+    `else
+        reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<<part_mem_bits)-1];
+        reg   [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];
+        reg   [part_mem_bits     : 0] mem_used;
+        reg   [part_mem_bits     : 0] memory_index;
+        initial mem_used = 0;
+    `endif
+
+    // Dqs edge checking
+    integer i;
+    reg  [3:0] expect_pos_dqs;
+    reg  [3:0] expect_neg_dqs;
+
+    // Burst counter
+    reg        [COL_BITS - 1 : 0] Burst_counter;
+
+    // Burst counter delay
+    reg [COL_BITS - 1 : 0] Burst_counter_dly;
+    always @(Mode_reg or Burst_counter) begin
+       if (Mode_reg[6:4] == 3'b010) begin
+//           Burst_counter_dly <= #tAC2_max Burst_counter;
+       end else if (Mode_reg[6:4] == 3'b011) begin
+//           Burst_counter_dly <= #tAC3_max Burst_counter;
+       end
+    end
+
+    // Precharge variables
+    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;
+
+    // Activate variables
+    reg                           Act_b0, Act_b1, Act_b2, Act_b3;
+
+    // Data IO variables
+//    reg                           Data_in_enable;
+    wire                          Data_in_enable = Write_pipeline[-2];
+//    reg                           Data_out_enable;
+    wire                          Data_out_enable = Read_pipeline[0];
+    wire                          tWTR_en = ((|Write_pipeline[`MAX_PIPE : 0]) & ~(&Dm));
+
+    // Data Out Enable delay
+//    reg Data_out_enable_dly;
+//    always @(Mode_reg or Data_out_enable) begin
+//       if (Mode_reg[6:4] == 3'b010) begin
+//        Data_out_enable_dly <= #tAC2_max Data_out_enable;
+//       end else if (Mode_reg[6:4] == 3'b011) begin
+//        Data_out_enable_dly <= #tAC3_max Data_out_enable;
+//       end
+//    end
+
+    // Internal address mux variables
+    reg                   [1 : 0] Prev_bank;
+    reg                   [1 : 0] Bank_addr;
+    reg        [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp;
+    reg       [ADDR_BITS - 1 : 0] Rows_addr;
+    reg       [ADDR_BITS - 1 : 0] B0_row_addr;
+    reg       [ADDR_BITS - 1 : 0] B1_row_addr;
+    reg       [ADDR_BITS - 1 : 0] B2_row_addr;
+    reg       [ADDR_BITS - 1 : 0] B3_row_addr;
+
+    integer                       aref_count;
+    reg                           ext_mode_load_done;
+    reg                           mode_load_done;
+    reg                           power_up_done;
+
+    // Write DQS for tDSS , tDSH, tDQSH, tDQSL checks
+    wire      wdqs_valid = Write_pipeline[`MAX_PIPE:0];
+
+    // Commands Decode
+    wire      Active_enable   = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
+    wire      Aref_enable     = ~Cs_n & ~Ras_n & ~Cas_n &  We_n & Cke;
+    wire      Sref_enable     = ~Cs_n & ~Ras_n & ~Cas_n &  We_n & ~Cke;
+    wire      Burst_term      = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
+    wire      Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n &  Ba[1] & ~Ba[0];
+    wire      Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[1] & ~Ba[0];
+    wire      Prech_enable    = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
+    wire      Read_enable     = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
+    wire      Write_enable    = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;
+    wire      DPD_enable      = ~Cs_n &  Ras_n &  Cas_n & ~We_n & ~Cke;
+    wire      PD_enable       = ((~Cs_n &  Ras_n &  Cas_n &  We_n) | Cs_n) & ~Cke;
+    wire      nop_enable      = ~Cs_n &  Ras_n &  Cas_n &  We_n ;
+    wire      des_enable      =  Cs_n ;
+    wire      srr_enable      = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[1] &  Ba[0] & ((part_size==128)|(part_size==512)|(part_size==1024)) ;
+
+    reg       Cke_Chk = 0      ;
+    parameter tInit = 200000   ;
+    reg       Cke_Print = 1'b0 ;
+    real      Init_Cmd_Chk     ;
+    
+
+    // Burst Length Decode
+//    reg  [4:0] burst_length = 1 << (Mode_reg[2:0]);
+    reg  [4:0] burst_length ;
+    reg       read_precharge_truncation;
+
+    // CAS Latency Decode
+    wire [2:0] cas_latency    = Mode_reg[6:4] ;
+    wire [2:0] cas_latency_x2 = ((2*Mode_reg[6:4])-1);
+
+    real                          tAC_max ;
+    always @ (Mode_reg)
+    begin
+        if (Mode_reg[6:4] == 3'b011)
+            tAC_max = tAC3_max ;
+        else if (Mode_reg[6:4] == 3'b010)
+            tAC_max = tAC2_max ;
+    end
+
+    // DQS Buffer
+    reg [DQS_BITS - 1 : 0] dqs_delayed ;
+//    always@* begin
+//       dqs_delayed <= Dqs_out ;
+//    end
+
+    assign    Dqs = (Dqs_out_en) ? {DQS_BITS{Dqs_out}} : 'bz;
+    assign    Dq  = (Dq_out_en ) ? Dq_out              : 'bz;
+
+    // Debug message
+    wire      Debug = 1'b0;
+
+    // Timing Check
+//    realtime      MRD_chk;
+    realtime      RFC_chk;
+    realtime      RRD_chk;
+    realtime      RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
+    realtime      RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;
+    realtime      RC_chk0, RC_chk1, RC_chk2, RC_chk3;
+    realtime      RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
+    realtime      RP_chk0, RP_chk1, RP_chk2, RP_chk3;
+    realtime      WR_chk0, WR_chk1, WR_chk2, WR_chk3;
+    realtime      SRR_chk;
+
+    // 
+    reg       [2:0] current_init_state ;
+    parameter [2:0] begin_init      = 3'b000 ;
+    parameter [2:0] cke_init        = 3'b001 ;
+    parameter [2:0] prech_init      = 3'b010 ;
+    parameter [2:0] begin_mode_init = 3'b011 ;
+    parameter [2:0] mode_init       = 3'b100 ;
+    parameter [2:0] ext_mode_init   = 3'b101 ;
+    parameter [2:0] mode_done_init  = 3'b110 ;
+
+    initial begin
+        CkeZ = 1'b0;
+        Sys_clk = 1'b0;
+        {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
+        {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
+//        Dqs_int = 1'b0;
+        Dqs_out_en = {DQS_BITS{1'b0}};
+        Dqs_out = {DQS_BITS{1'bz}};
+//        Dqs_gen = {DQS_BITS{1'bz}};
+        Dq_out = {DQ_BITS{1'bz}};
+        Dq_out_en = {DQ_BITS{1'b0}};
+//        dq_delayed = {DQ_BITS{1'bz}};
+//        Data_in_enable = 1'b0;
+//        Data_out_enable = 1'b0;
+        aref_count = 0;
+        SelfRefresh = 1'b0;
+        power_up_done = 0;
+        ext_mode_load_done = 0;
+        mode_load_done = 0;
+//        MRD_chk = 0;
+        RFC_chk = 0;
+        RRD_chk = 0;
+        RAS_chk0 = 0;
+        RAS_chk1 = 0;
+        RAS_chk2 = 0;
+        RAS_chk3 = 0;
+        RAP_chk0 = 0;
+        RAP_chk1 = 0;
+        RAP_chk2 = 0;
+        RAP_chk3 = 0;
+        RC_chk0 = 0;
+        RC_chk1 = 0;
+        RC_chk2 = 0;
+        RC_chk3 = 0;
+        RCD_chk0 = 0;
+        RCD_chk1 = 0;
+        RCD_chk2 = 0;
+        RCD_chk3 = 0;
+        RP_chk0 = 0;
+        RP_chk1 = 0;
+        RP_chk2 = 0;
+        RP_chk3 = 0;
+        WR_chk0 = 0;
+        WR_chk1 = 0;
+        WR_chk2 = 0;
+        WR_chk3 = 0;
+        SRR_chk = 0;
+        $timeformat (-9, 3, " ns", 12);
+        pos_clk_time = 0;
+        neg_clk_time = 0;
+        enter_DPD    = 0;
+        enter_PD     = 0;
+        enter_APD    = 0;
+        current_init_state = begin_init ;
+        SRR_read  = 1'b0;
+        MRD_cntr  = 8;
+        SRR_cntr  = 8;
+        SRC_cntr  = 8;
+        tWTR_cntr = 8;
+        Read_precharge_access[0]  = 1'b0 ;
+        Read_precharge_access[1]  = 1'b0 ;
+        Read_precharge_access[2]  = 1'b0 ;
+        Read_precharge_access[3]  = 1'b0 ;
+        Read_precharge_pre[0]  = 1'b0 ;
+        Read_precharge_pre[1]  = 1'b0 ;
+        Read_precharge_pre[2]  = 1'b0 ;
+        Read_precharge_pre[3]  = 1'b0 ;
+        Write_precharge_access[0] = 1'b0 ;
+        Write_precharge_access[1] = 1'b0 ;
+        Write_precharge_access[2] = 1'b0 ;
+        Write_precharge_access[3] = 1'b0 ;
+        Write_precharge_pre[0] = 1'b0 ;
+        Write_precharge_pre[1] = 1'b0 ;
+        Write_precharge_pre[2] = 1'b0 ;
+        Write_precharge_pre[3] = 1'b0 ;
+        wr_ap_display_msg  = 1'b0 ;
+        rd_ap_display_msg  = 1'b0 ;
+        Read_precharge_count[0] = 4'hf;
+        Read_precharge_count[1] = 4'hf;
+        Read_precharge_count[2] = 4'hf;
+        Read_precharge_count[3] = 4'hf;
+        Write_precharge_count[0] = 4'hf;
+        Write_precharge_count[1] = 4'hf;
+        Write_precharge_count[2] = 4'hf;
+        Write_precharge_count[3] = 4'hf;
+    end
+
+    // make sure 200 us has passed since cke for first command
+    always @ (Clk_Chk_enable or nop_enable or des_enable)
+    begin
+        if (~Clk_Chk_enable) begin
+            if (~nop_enable & ~des_enable) begin
+                Clk_Chk_enable = 1'b1 ;
+                if (~Cke_Chk) begin
+                    if (($realtime - Init_Cmd_Chk < tInit - 0.001) & ~Cke_Print) begin
+                        $display("Warning: You must wait 200 us from CKE assertion before you perform a command.  Current wait time: %3.0f ns", $realtime - (Init_Cmd_Chk));                    
+                        Cke_Print = 1'b1 ;
+                    end
+                end                    
+            end    
+        end
+    end
+
+    // Check for tCH, tCK, and clock stop mode
+    always @(diff_ck) begin
+        if (diff_ck) begin
+            neg_clk_time = $realtime - neg_clk_edge ;
+        end
+        if (~diff_ck) begin
+            pos_clk_time = $realtime - pos_clk_edge ;
+        end
+        if (Cke & Clk_Chk_enable) begin
+            // clock stop mode when either pulse width is 2x bigger than the other (reasonable assumption???)
+            clock_stop = ((pos_clk_time / neg_clk_time > 2) | (neg_clk_time / pos_clk_time > 2));
+            
+            // Check if NOP/DES when enter/exit clock stop mode
+            if ((clock_stop && diff_ck) && (~(prev_nop || prev_des) || ~(nop_enable || des_enable))) begin
+                $display ("%m: at time %t ERROR: Nop or Deselect is required when enter or exit Stop Clock Mode", $time);
+            end
+            
+            if ((pos_clk_time / clk_period < tCH_MIN) && ~clock_stop) begin
+                $display ("%m: at time %t ERROR: tCH minimum violation on CLK by %t", $time, tCH_MIN*clk_period - pos_clk_time);
+            end
+            if ((pos_clk_time / clk_period > tCH_MAX) && ~clock_stop) begin
+                $display ("%m: at time %t ERROR: tCH maximum violation on CLK by %t", $time, pos_clk_time - tCH_MAX*clk_period);
+            end
+            if ((neg_clk_time / clk_period < tCL_MIN) && ~clock_stop) begin
+                $display ("%m: at time %t ERROR: tCL minimum violation on CLK by %t", $time, tCL_MIN*clk_period - pos_clk_time);
+            end
+            if ((neg_clk_time / clk_period > tCL_MAX) && ~clock_stop) begin
+                $display ("%m: at time %t ERROR: tCL maximum violation on CLK by %t", $time, pos_clk_time - tCL_MAX*clk_period);
+            end
+        end
+    end
+
+    //clock Frequency Check
+    always @(posedge diff_ck) begin
+        if (clk_pos_edge_cnt > 1) begin
+            if (Mode_reg[6:4] == 3'b011) begin
+                if (clk_period < (tCK3_min-0.001)) begin
+                    $display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 3", $realtime);
+                    $display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period);
+                end
+            end
+            if (Mode_reg[6:4] == 3'b010) begin
+                if (clk_period < (tCK2_min-0.001)) begin
+                    $display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 2", $realtime);
+                    $display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period);
+                end
+            end
+        end
+    end
+
+    //SRR reg settings
+    always @(posedge power_up_done) begin
+        Srr_reg        = 'b0 ;
+        Srr_reg[3:0]   = 4'b1111 ;                       //Manufacturer(Micron)
+        Srr_reg[7:4]   = 4'b0000 ;                       //Revision ID(Default to 0 in model)
+        Srr_reg[10:8]  = 3'b100 ;                        //Refresh Rate(based on temp sensor - will default to 1x in model)
+        Srr_reg[11]    = (DQ_BITS == 32)? 1'b1 : 1'b0 ;  //Part width(x32 or x16)
+        Srr_reg[12]    = 1'b0 ;                          //Device Type (LP DDR)
+        Srr_reg[15:13] = (part_size == 1024)? 3'b011 : 
+                         (part_size == 512 )? 3'b010 : 
+                         (part_size == 256 )? 3'b001 : 
+                                              3'b000 ;   //Density(1024Mb, 512Mb, 256Mb, 128Mb)
+    end
+
+    // System Clock
+    always begin
+        @ (posedge diff_ck) begin
+            Sys_clk = CkeZ;
+            CkeZ = Cke;
+        end
+        @ (negedge diff_ck) begin
+            Sys_clk = 1'b0;
+        end
+    end
+
+    task store_prev_cmd;
+    begin
+        prev_Cs_n  <= Cs_n  ;
+        prev_Ras_n <= Ras_n ;
+        prev_Cas_n <= Cas_n ;
+        prev_We_n  <= We_n  ;
+        prev_Ba[1] <= Ba[1] ;
+        prev_Ba[0] <= Ba[0] ;
+        prev_cke   <= Cke   ;
+    end
+    endtask
+
+    task MRD_counter;
+    begin
+        if (Cke) begin
+            if (MRD_cntr < tMRD) begin
+                MRD_cntr = MRD_cntr + 1'b1;
+            end
+        end
+    end
+    endtask
+
+    task SRR_counter;
+    begin
+        if (Cke) begin
+            if (SRR_cntr < tSRR) begin
+                SRR_cntr = SRR_cntr + 1'b1;
+            end
+        end
+    end
+    endtask
+
+    task SRC_counter;
+    begin
+        if (Cke) begin
+            if (SRC_cntr < ((Mode_reg[6:4])+1)) begin
+                SRC_cntr = SRC_cntr + 1'b1;
+            end
+        end
+    end
+    endtask
+
+    task tWTR_counter;
+    begin
+        if (Cke) begin
+            if (tWTR_en) begin
+                tWTR_cntr = 0               ;
+            end else begin
+                tWTR_cntr = tWTR_cntr + 1'b1;
+            end
+        end
+    end
+    endtask
+
+    task command_counter;
+    begin
+        if (Cke) begin
+            for (i=0; i<4;i=i+1) begin
+                if (Read_precharge_count[i] < 4'hf) begin
+                    Read_precharge_count[i] = Read_precharge_count[i] + 1'b1;
+                end
+            end
+            for (i=0; i<4;i=i+1) begin
+                if (Write_precharge_count[i] < 4'hf) begin
+                    Write_precharge_count[i] = Write_precharge_count[i] + 1'b1;
+                end
+            end
+        end
+    end
+    endtask
+
+
+    task PD_counter;
+    begin
+        if (~Cke) begin
+            if (PD_cntr < tCKE) begin
+                PD_cntr = PD_cntr + (enter_DPD | enter_PD | DPD_enable | PD_enable);
+            end
+        end else begin
+            PD_cntr = 4'h0 ;
+        end
+    end
+    endtask
+
+    task tXP_check;
+    begin
+        if (Cke == 1'b1 && prev_cke == 1'b0) begin
+            tXP_chk = $realtime ;
+        end
+        if (Cke) begin
+            if (~nop_enable && ~des_enable) begin
+                if ($realtime-tXP_chk < tXP - 0.001) begin
+`ifdef T25L
+                    $display ("%m: At time %t ERROR: tPDX violation", $realtime);
+`else
+                    $display ("%m: At time %t ERROR: tXP violation", $realtime);
+`endif
+                end
+            end
+        end
+    end
+    endtask
+
+    // DPD pos edge clk cntr
+    always begin
+        @ (posedge diff_ck) begin
+            tXP_check      ;
+            Power_down_chk ;
+            PD_counter     ;
+            store_prev_cmd ;
+        end
+    end
+
+    // Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high
+    always @(Cke) begin
+        if (Cke === 1'b1) begin
+            Init_Cmd_Chk = $realtime ;
+            if (SelfRefresh === 1'b1) begin
+                SelfRefresh = 1'b0;
+            end
+            if (!((Cs_n) || (~Cs_n &  Ras_n & Cas_n &  We_n))) begin
+                $display ("%m: At time %t MEMORY ERROR:  You must have a Deselect or NOP command applied", $realtime);
+                $display ("%m:           when the Clock Enable is brought High.");
+            end 
+        end
+    end
+
+    //BL Mode Reg settings
+    always@(Mode_reg[2:0] or mode_load_done) begin
+        if (mode_load_done) begin
+            case (Mode_reg[2:0])
+                3'b001 : burst_length = 5'b00010;
+                3'b010 : burst_length = 5'b00100;
+                3'b011 : burst_length = 5'b01000;
+                3'b100 : burst_length = 5'b10000;
+                default : burst_length = 5'bxxxxx;
+            endcase
+        end
+    end
+
+// Init sequence
+always @(current_init_state or Cke or Prech_enable or ext_mode_load_done or mode_load_done or aref_count) begin
+    if (current_init_state == begin_init) begin
+        if (Cke) begin
+            current_init_state = cke_init ;
+            power_up_done = 1'b0 ;
+        end
+    end
+    if (current_init_state == cke_init) begin
+        if (Prech_enable) begin
+            current_init_state = prech_init ;
+            aref_count = 0 ;
+        end
+    end
+    if (current_init_state == prech_init) begin
+        if (~Prech_enable) begin
+            current_init_state = begin_mode_init ;
+        end
+    end
+    if (current_init_state == begin_mode_init) begin
+        if (ext_mode_load_done) begin
+            current_init_state = ext_mode_init ;
+        end
+        if (mode_load_done) begin
+            current_init_state = mode_init ;
+        end
+    end
+    if (current_init_state == mode_init) begin
+        if (ext_mode_load_done) begin
+            current_init_state = mode_done_init ;
+        end
+    end
+    if (current_init_state == ext_mode_init) begin
+        if (mode_load_done) begin
+            current_init_state = mode_done_init ;
+        end
+    end
+    if (current_init_state == mode_done_init && aref_count >= 2) begin
+        power_up_done = 1'b1;
+    end
+end
+
+
+    // this task will erase the contents of 0 or more banks
+    task erase_mem;
+        input  [BA_BITS+1:0] bank_MSB_row; //bank bits + 2 row MSB
+        input                DPD_mode ; //erase all memory locations
+        integer i;
+        begin
+
+            if (DPD_mode) begin
+`ifdef FULL_MEM
+                for (i=0; i<{(BA_BITS+ROW_BITS+COL_BITS){1'b1}}; i=i+1) begin
+                    mem_array[i] = 'bx;
+                end
+`else
+                memory_index = 0;
+                i = 0;
+                // remove the selected banks
+                for (memory_index=0; memory_index<mem_used; memory_index=memory_index+1) begin
+                    addr_array[i] = 'bx;
+                    mem_array[i] = 'bx;
+                    i = i + 1;
+                end
+`endif
+            end else begin
+`ifdef FULL_MEM
+                for (i={bank_MSB_row, {(ROW_BITS+COL_BITS-2){1'b1}}}; i<={1'b0, {(BA_BITS+ROW_BITS+COL_BITS){1'b1}}}; i=i+1) begin
+                    mem_array[i] = 'bx;
+                end
+`else
+                memory_index = 0;
+                i = 0;
+                // remove the selected banks
+                for (memory_index=0; memory_index<mem_used; memory_index=memory_index+1) begin
+                    if (addr_array[memory_index]>({bank_MSB_row, {(ROW_BITS+COL_BITS-2){1'b1}}})) begin
+                        addr_array[i] = 'bx;
+                        mem_array[i] = 'bx;
+                        i = i + 1;
+                    end else begin
+                        i = i + 1;
+                    end
+                end
+`endif
+            end
+        end
+    endtask
+
+    // Write Memory
+    task write_mem;
+        input [full_mem_bits - 1 : 0] addr;
+        input       [DQ_BITS - 1 : 0] data;
+        reg       [part_mem_bits : 0] i;
+        begin
+`ifdef FULL_MEM
+            mem_array[addr] = data;
+`else
+            begin : loop
+                for (i = 0; i < mem_used; i = i + 1) begin
+                    if (addr_array[i] === addr) begin
+                        disable loop;
+                    end
+                end
+            end
+            if (i === mem_used) begin
+                if (i === (1<<part_mem_bits)) begin
+                    $display ("%m: At time %t ERROR: Memory overflow.\n  Write to Address %d with Data %d will be lost.\n You must increase the part_mem_bits parameter or `define FULL_MEM.", $realtime, addr, data);
+                end else begin
+                    mem_used = mem_used + 1;
+                    addr_array[i] = addr;
+                end
+            end
+            mem_array[i] = data;
+`endif
+        end
+    endtask
+
+    // Read Memory
+    task read_mem;
+        input [full_mem_bits - 1 : 0] addr;
+        output      [DQ_BITS - 1 : 0] data;
+        reg       [part_mem_bits : 0] i;
+        begin
+`ifdef FULL_MEM
+            data = mem_array[addr];
+`else
+            begin : loop
+                for (i = 0; i < mem_used; i = i + 1) begin
+                    if (addr_array[i] === addr) begin
+                        disable loop;
+                    end
+                end
+            end
+            if (i <= mem_used) begin
+                data = mem_array[i];
+            end else begin
+                data = 'bx;
+            end
+`endif
+        end
+    endtask
+
+    // Burst Decode
+    task Burst_Decode;
+    begin
+
+        // Advance Burst Counter
+//        if (Burst_counter < burst_length) begin
+        if (Write_pipeline[-2]) begin
+            Burst_counter = Burst_counter + 1;
+        end
+
+        // Burst Type
+        if (Mode_reg[3] === 1'b0) begin                         // Sequential Burst
+            Cols_temp = Cols_addr + 1;
+        end else if (Mode_reg[3] === 1'b1) begin                // Interleaved Burst
+            Cols_temp[2] =  Burst_counter[2] ^ Cols_brst[2];
+            Cols_temp[1] =  Burst_counter[1] ^ Cols_brst[1];
+            Cols_temp[0] =  Burst_counter[0] ^ Cols_brst[0];
+        end
+
+        // Burst Length
+        if (burst_length === 2) begin
+            Cols_addr [0] = Cols_temp [0];
+        end else if (burst_length === 4) begin
+            Cols_addr [1 : 0] = Cols_temp [1 : 0];
+        end else if (burst_length === 8) begin
+            Cols_addr [2 : 0] = Cols_temp [2 : 0];
+        end else if (burst_length === 16) begin
+            Cols_addr [3 : 0] = Cols_temp [3 : 0];
+        end else begin
+            Cols_addr = Cols_temp;
+        end
+
+        // Data Counter
+//        if (Burst_counter >= burst_length) begin
+//            Data_in_enable = 1'b0;
+//            Data_out_enable = 1'b0;
+//            read_precharge_truncation = 1'b0;
+//            SRR_read = 1'b0;
+//        end
+    end
+    endtask
+
+
+    // SRC check
+    task Timing_chk_SRC;
+    begin
+        if (Active_enable   || Aref_enable     || Sref_enable  || Burst_term  ||
+            Ext_mode_enable || Mode_reg_enable || Prech_enable || Read_enable ||
+            Write_enable    || DPD_enable      || PD_enable    || srr_enable) begin
+               if (part_size == 1024) begin
+                   if (SRC_cntr < ((Mode_reg[6:4])+tSRC)) begin
+                       $display ("%m: At time %t ERROR: tSRC Violation", $realtime);
+                   end
+               end
+        end
+    end
+    endtask
+
+    task ShiftPipelines;
+    begin
+        // read command pipeline
+        Read_pipeline = Read_pipeline >> 1;
+        Write_pipeline = Write_pipeline >> 1;
+        for (i = -2; i < `MAX_PIPE-1; i = i + 1)
+        begin
+            Write_col_pipeline [i]  = Write_col_pipeline[i+1];
+            Write_bank_pipeline [i] = Write_bank_pipeline[i+1];
+        end
+    end
+    endtask
+
+    // Dq and Dqs Drivers
+    task Dq_Dqs_Drivers;
+    begin
+
+        // Initialize Read command
+        if (Read_pipeline [0] === 1'b1) begin
+//            Data_out_enable = 1'b1;
+            Bank_addr = Write_bank_pipeline[0];
+            Cols_addr = Write_col_pipeline [0];
+            Cols_brst = Cols_addr [2 : 0];
+//            if (SRR_read == 1'b1) begin
+//                Burst_counter = burst_length - 2;
+//            end else begin
+//                Burst_counter = 0;
+//            end
+
+            // Row Address Mux
+            case (Bank_addr)
+                2'd0    : Rows_addr = B0_row_addr;
+                2'd1    : Rows_addr = B1_row_addr;
+                2'd2    : Rows_addr = B2_row_addr;
+                2'd3    : Rows_addr = B3_row_addr;
+                default : $display ("%m: At time %t ERROR: Invalid Bank Address", $realtime);
+            endcase
+        end
+
+        // Read latch
+        if (Read_pipeline[0] === 1'b1) begin
+            // output data
+            if (SRR_read == 1'b1) begin
+                if (Cols_addr == 0) begin
+                    Dq_out_temp = Srr_reg[DQ_BITS-1:0];
+                end else begin
+                    Dq_out_temp = Srr_reg[2*DQ_BITS-1:DQ_BITS];
+                    SRR_read = 1'b0 ;
+                end
+            end else begin
+                read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out_temp);
+            end
+            if (Debug) begin
+                $display ("At time %t %m:READ: Bank = %d, Row = %d, Col = %d, Data = %d", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_out);
+            end
+
+        end
+
+        Dq_out <=  #(tAC_max) Dq_out_temp ;
+        Dqs_out <= #(tAC_max) ((|Read_pipeline[0]) & Sys_clk) ; 
+
+        if (cas_latency == 3)
+            Dqs_out_en <= #(tAC_max) (|Read_pipeline[2:0]);
+        else
+            Dqs_out_en <= #(tAC_max) (|Read_pipeline[1:0]);
+        if (Sys_clk) begin
+            Dq_out_en <= #(tAC_max) (Read_pipeline[0]);
+        end
+
+    end
+    endtask
+
+    // Write FIFO and DM Mask Logic
+    task Write_FIFO_DM_Mask_Logic;
+    begin
+
+        // Initialize Write command
+        if (Write_pipeline [-2] === 1'b1) begin
+//            Data_in_enable = 1'b1;
+            Bank_addr = Write_bank_pipeline [-2];
+            Cols_addr = Write_col_pipeline [-2];
+            Cols_brst = Cols_addr [2 : 0];
+//            Burst_counter = 0;
+
+            // Row address mux
+            case (Bank_addr)
+                2'd0    : Rows_addr = B0_row_addr;
+                2'd1    : Rows_addr = B1_row_addr;
+                2'd2    : Rows_addr = B2_row_addr;
+                2'd3    : Rows_addr = B3_row_addr;
+                default : $display ("%m: At time %t ERROR: Invalid Row Address", $realtime);
+            endcase
+        end
+
+        // Write data
+//        if (Data_in_enable === 1'b1) begin
+        if (Write_pipeline[-2] === 1'b1) begin
+
+            // Data Buffer
+            read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
+
+            // write negedge Dqs on posedge Sys_clk
+            if (Sys_clk) begin
+                if (!dm_fall[0]) begin
+                    Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
+                end
+                if (!dm_fall[1]) begin
+                    Dq_buf [15 : 8] = dq_fall [15 : 8];
+                end
+`ifdef x32
+                if (!dm_fall[2]) begin
+                    Dq_buf [23 : 16] = dq_fall [23 : 16];
+                end
+                if (!dm_fall[3]) begin
+                    Dq_buf [31 : 24] = dq_fall [31 : 24];
+                end
+`endif
+                if (~&dm_fall) begin
+                    if (Debug) begin
+                        $display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
+                    end
+                end
+            // write posedge Dqs on negedge Sys_clk
+            end else begin
+                if (!dm_rise[0]) begin
+                    Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
+                end
+                if (!dm_rise[1]) begin
+                    Dq_buf [15 : 8] = dq_rise [15 : 8];
+                end
+`ifdef x32
+                if (!dm_rise[2]) begin
+                    Dq_buf [23 : 16] = dq_rise [23 : 16];
+                end
+                if (!dm_rise[3]) begin
+                    Dq_buf [31 : 24] = dq_rise [31 : 24];
+                end
+`endif
+                if (~&dm_rise) begin
+                    if (Debug) begin
+                        $display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
+                    end
+                end
+            end
+
+            // Write Data
+            write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
+            // tWR start and tWTR check
+            if (Sys_clk && &dm_pair === 1'b0)  begin
+                case (Bank_addr)
+                    2'd0    : WR_chk0 = $realtime;
+                    2'd1    : WR_chk1 = $realtime;
+                    2'd2    : WR_chk2 = $realtime;
+                    2'd3    : WR_chk3 = $realtime;
+                    default : $display ("%m: At time %t ERROR: Invalid Bank Address (tWR)", $realtime);
+                endcase
+
+//                // tWTR check
+//                if (Read_enable === 1'b1) begin
+//                    $display ("%m: At time %t ERROR: tWTR violation during Read", $realtime);
+//                end
+            end
+        end
+    end
+    endtask
+
+    // Auto Precharge Calculation
+    task Auto_Precharge_Calculation;
+    begin
+        // Precharge counter
+        if (Read_precharge_access [0] === 1'b1 || Write_precharge_access [0] === 1'b1) begin
+            Count_precharge [0] = Count_precharge [0] + 1;
+        end
+        if (Read_precharge_access [1] === 1'b1 || Write_precharge_access [1] === 1'b1) begin
+            Count_precharge [1] = Count_precharge [1] + 1;
+        end
+        if (Read_precharge_access [2] === 1'b1 || Write_precharge_access [2] === 1'b1) begin
+            Count_precharge [2] = Count_precharge [2] + 1;
+        end
+        if (Read_precharge_access [3] === 1'b1 || Write_precharge_access [3] === 1'b1) begin
+            Count_precharge [3] = Count_precharge [3] + 1;
+        end
+
+        // Read with AutoPrecharge Calculation
+        //      The device start internal precharge when:
+        //          1.  BL/2 cycles after command
+        //          2.  Meet tRAS requirement
+        if (Read_precharge_access[0] & (Count_precharge[0] >= burst_length/2)) begin
+            Read_precharge_access[0] = 1'b0 ;
+            Read_precharge_pre[0] = 1'b1 ;
+        end
+        if ((Read_precharge_pre[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS - 0.001)) begin
+            Pc_b0 = 1'b1;
+            Act_b0 = 1'b0;
+            RP_chk0 = $realtime;
+            Read_precharge_pre[0] = 1'b0;
+        end
+
+        if (Read_precharge_access[1] & (Count_precharge[1] >= burst_length/2)) begin
+            Read_precharge_access[1] = 1'b0 ;
+            Read_precharge_pre[1] = 1'b1 ;
+        end
+        if ((Read_precharge_pre[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS - 0.001)) begin
+            Pc_b1 = 1'b1;
+            Act_b1 = 1'b0;
+            RP_chk1 = $realtime;
+            Read_precharge_pre[1] = 1'b0;
+        end
+
+        if (Read_precharge_access[2] & (Count_precharge[2] >= burst_length/2)) begin
+            Read_precharge_access[2] = 1'b0 ;
+            Read_precharge_pre[2] = 1'b1 ;
+        end
+        if ((Read_precharge_pre[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS - 0.001)) begin
+            Pc_b2 = 1'b1;
+            Act_b2 = 1'b0;
+            RP_chk2 = $realtime;
+            Read_precharge_pre[2] = 1'b0;
+        end
+
+        if (Read_precharge_access[3] & (Count_precharge[3] >= burst_length/2)) begin
+            Read_precharge_access[3] = 1'b0 ;
+            Read_precharge_pre[3] = 1'b1 ;
+        end
+        if ((Read_precharge_pre[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS - 0.001)) begin
+            Pc_b3 = 1'b1;
+            Act_b3 = 1'b0;
+            RP_chk3 = $realtime;
+            Read_precharge_pre[3] = 1'b0;
+        end
+
+        // Write with AutoPrecharge Calculation
+        //      The device start internal precharge when:
+        //          1.  Meet tRAS requirement
+        //          2.  Two clock after last burst
+        // Since tWR is time base, the model will compensate tRP
+        if (Write_precharge_access[0] & (Count_precharge[0] >= burst_length/2+3)) begin
+            Write_precharge_access[0] = 1'b0 ;
+            Write_precharge_pre[0] = 1'b1 ;
+        end
+        if (Write_precharge_pre[0] & ($realtime - RAS_chk0 >= tRAS - 0.001)) begin
+                Write_precharge_pre[0] = 1'b0;
+                Pc_b0 = 1'b1;
+                Act_b0 = 1'b0;
+                RP_chk0 = $realtime - ((2 * clk_period) - tWR);
+        end
+
+        if (Write_precharge_access[1] & (Count_precharge[1] >= burst_length/2+3)) begin
+            Write_precharge_access[1] = 1'b0 ;
+            Write_precharge_pre[1] = 1'b1 ;
+        end
+        if (Write_precharge_pre[1] & ($realtime - RAS_chk1 >= tRAS - 0.001)) begin
+                Write_precharge_pre[1] = 1'b0;
+                Pc_b1 = 1'b1;
+                Act_b1 = 1'b0;
+                RP_chk1 = $realtime - ((2 * clk_period) - tWR);
+        end
+
+        if (Write_precharge_access[2] & (Count_precharge[2] >= burst_length/2+3)) begin
+            Write_precharge_access[2] = 1'b0 ;
+            Write_precharge_pre[2] = 1'b1 ;
+        end
+        if (Write_precharge_pre[2] & ($realtime - RAS_chk2 >= tRAS - 0.001)) begin
+                Write_precharge_pre[2] = 1'b0;
+                Pc_b2 = 1'b1;
+                Act_b2 = 1'b0;
+                RP_chk2 = $realtime - ((2 * clk_period) - tWR);
+        end
+
+        if (Write_precharge_access[3] & (Count_precharge[3] >= burst_length/2+3)) begin
+            Write_precharge_access[3] = 1'b0 ;
+            Write_precharge_pre[3] = 1'b1 ;
+        end
+        if (Write_precharge_pre[3] & ($realtime - RAS_chk3 >= tRAS - 0.001)) begin
+                Write_precharge_pre[3] = 1'b0;
+                Pc_b3 = 1'b1;
+                Act_b3 = 1'b0;
+                RP_chk3 = $realtime - ((2 * clk_period) - tWR);
+        end
+    end
+    endtask
+
+    task Power_down_chk;
+    begin
+        if (DPD_enable == 1'b1 && enter_DPD == 1'b0) begin
+            if (prev_cke & Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin
+                erase_mem(4'b0000, 1'b1);
+                current_init_state = begin_init ;
+                ext_mode_load_done = 1'b0 ;
+                mode_load_done = 1'b0 ;
+                enter_DPD = 1'b1;
+                $display ("%m: at time %t Entering Deep Power-Down Mode", $realtime);
+            end
+        end
+        if (enter_DPD == 1'b1) begin
+            if (Cke == 1'b1 && prev_cke == 1'b0) begin
+                if (PD_cntr < tCKE) begin
+                    $display ("%m: At time %t ERROR: tCKE violation during exiting of Deep Power-Down Mode", $realtime);
+                end
+                $display ("%m: at time %t Exiting Deep Power-Down Mode - A 200 us delay is required with either DESELECT or NOP commands present before the initialization sequence may begin", $realtime);
+                enter_DPD = 1'b0;
+            end
+        end
+        if (PD_enable == 1'b1 && enter_PD == 1'b0) begin
+            if (prev_cke) begin
+                if (Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin
+                    $display ("%m: at time %t Entering Power-Down Mode", $realtime);
+                    enter_PD = 1'b1;
+                end else if (~Pc_b0 | ~Pc_b1 | ~Pc_b2 | ~Pc_b3) begin
+                    $display ("%m: at time %t Entering Active Power-Down Mode", $realtime);
+                    enter_APD = 1'b1;
+                end
+            end
+        end
+        if (enter_PD == 1'b1 || enter_APD == 1'b1) begin
+            if (Cke == 1'b1 && prev_cke == 1'b0) begin
+                if (PD_cntr < tCKE) begin
+                    if (enter_PD == 1'b1) begin
+                        $display ("%m: At time %t ERROR: tCKE violation during exiting of Power-Down Mode", $realtime);
+                    end else if (enter_APD == 1'b1) begin
+                        $display ("%m: At time %t ERROR: tCKE violation during exiting of Active Power-Down Mode", $realtime);
+                    end
+                end
+                if (enter_PD == 1'b1) begin
+                    $display ("%m: at time %t Exiting Power-Down Mode", $realtime);
+                    enter_PD = 1'b0 ;
+                end else if (enter_APD == 1'b1) begin
+                    $display ("%m: at time %t Exiting Active Power-Down Mode", $realtime);
+                    enter_APD = 1'b0 ;
+                end
+            end
+        end
+
+    end
+    endtask
+
+    reg [31:0] xx ;
+    function [COL_BITS-1:0] Burst_Order;
+        input [COL_BITS-1:0] Col;
+        input [31:0]         i;
+    begin
+        if (Mode_reg[3] == 1'b1) //interleaved
+            Burst_Order = (Col & -1*burst_length) + (Col%burst_length ^ i);
+        else // sequential
+        begin
+            xx = -1*burst_length;
+            Burst_Order = (Col & xx) + (Col%burst_length + i) % (burst_length);
+        end
+    end
+    endfunction
+
+    // Control Logic
+    task Control_Logic;
+    begin
+
+      // Self Refresh
+        if (Sref_enable === 1'b1) begin
+            // Partial Array Self Refresh
+            if (part_size == 128) begin
+                case (Ext_Mode_reg[2:0])
+                    3'b000 : ;//keep Bank 0-7
+                    3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime)                  ; erase_mem(4'b0111, 1'b0); end
+                    3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime)                  ; erase_mem(4'b0011, 1'b0); end
+                    3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime)                                                                                      ; end
+                    3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime)                                                                                      ; end
+                    3'b101 : begin $display("%m: at time %t INFO: Reserved", $realtime)                                                                                      ; end
+                    3'b110 : begin $display("%m: at time %t INFO: Reserved", $realtime)                                                                                      ; end
+                endcase
+            end else begin
+                case (Ext_Mode_reg[2:0])
+                    3'b000 : ;//keep Bank 0-7
+                    3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime)                  ; erase_mem(4'b0111, 1'b0); end
+                    3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime)                  ; erase_mem(4'b0011, 1'b0); end
+                    3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime)                                                                                      ; end
+                    3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime)                                                                                      ; end
+                    3'b101 : begin $display("%m: at time %t INFO: Banks 1-3 and 1/2 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0001, 1'b0); end
+                    3'b110 : begin $display("%m: at time %t INFO: Banks 1-3 and 3/4 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0000, 1'b0); end
+                endcase
+            end
+            SelfRefresh = 1'b1;
+        end
+        if (Aref_enable === 1'b1) begin
+            if (Debug) begin
+                $display ("Debug: At time %t %m:AUTOREFRESH: Auto Refresh", $realtime);
+            end
+            // aref_count is to make sure we have met part of the initialization sequence
+            if (~power_up_done) begin
+                aref_count = aref_count + 1;
+            end
+
+            // Auto Refresh to Auto Refresh
+            if ($realtime - RFC_chk < tRFC - 0.001) begin
+                $display ("%m: At time %t ERROR: tRFC violation during Auto Refresh", $realtime);
+            end
+            
+            // Precharge to Auto Refresh
+            if (($realtime - RP_chk0 < tRP - 0.001) || ($realtime - RP_chk1 < tRP - 0.001) ||
+                ($realtime - RP_chk2 < tRP - 0.001) || ($realtime - RP_chk3 < tRP - 0.001)) begin
+                $display ("%m: At time %t ERROR: tRP violation during Auto Refresh", $realtime);
+            end
+            
+            // Precharge to Auto Refresh
+            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
+                $display ("%m: At time %t ERROR: All banks must be Precharged before Auto Refresh", $realtime);
+            end
+            
+            // Record Current tRFC time
+            RFC_chk = $realtime;
+        end
+
+        // SRR Register
+        if (srr_enable == 1'b1) begin
+            if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1 &&
+                Data_out_enable === 1'b0 && Data_in_enable === 1'b0) begin
+                SRR_read = 1'b1;
+                SRR_chk = $realtime;
+                SRR_cntr = 0;
+            end
+        end
+
+
+        // Extended Mode Register
+        if (Ext_mode_enable == 1'b1) begin
+            if (Debug) begin
+                $display ("Debug: At time %t %m:EMR  : Extended Mode Register", $realtime);
+            end
+
+            // Register Mode
+            Ext_Mode_reg = Addr;
+
+            if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
+                // ensure that power sequence is met properly
+                if (~power_up_done) begin
+                    ext_mode_load_done = 1'b1;
+                end
+                $display ("At time %t %m:ELMR  : Extended Load Mode Register", $realtime);
+                if (part_size == 128) begin
+                    // Self Refresh Coverage
+                    case (Addr[2 : 0])
+                        3'b000  : $display ("%m :                             Self Refresh Cov = 4 banks");
+                        3'b001  : $display ("%m :                             Self Refresh Cov = 2 banks");
+                        3'b010  : $display ("%m :                             Self Refresh Cov = 1 bank");
+                        3'b101  : $display ("%m :                             PASR = Reserved");
+                        3'b110  : $display ("%m :                             PASR = Reserved");
+                        default : $display ("%m :                             PASR = Reserved");
+                    endcase
+                end else begin
+                    // Self Refresh Coverage
+                    case (Addr[2 : 0])
+                        3'b000  : $display ("%m :                             Self Refresh Cov = 4 banks");
+                        3'b001  : $display ("%m :                             Self Refresh Cov = 2 banks");
+                        3'b010  : $display ("%m :                             Self Refresh Cov = 1 bank");
+                        3'b101  : $display ("%m :                             Self Refresh Cov = 1/2 bank");
+                        3'b110  : $display ("%m :                             Self Refresh Cov = 1/4 bank");
+                        default : $display ("%m :                             PASR = Reserved");
+                    endcase
+                end
+                // Maximum Case Temp
+//                case (Addr[4 : 3])
+//                    2'b11  : $display ("%m :                             Maximum Case Temp = 85C");
+//                    2'b00  : $display ("%m :                             Maximum Case Temp = 70C");
+//                    2'b01  : $display ("%m :                             Maximum Case Temp = 45C");
+//                    2'b10  : $display ("%m :                             Maximum Case Temp = 15C");
+//                endcase
+
+                // Drive Strength
+                case (Addr[7 : 5])  
+                    3'b000  : $display ("%m :                             Drive Strength    = Full Strength");
+                    3'b001  : $display ("%m :                             Drive Strength    = Half Strength");
+                    3'b010  : $display ("%m :                             Drive Strength    = Quarter Strength");
+                    3'b011  : $display ("%m :                             Drive Strength    = Three Quarter Strength");
+                    3'b100  : $display ("%m :                             Drive Strength    = Three Quarter Strength");
+                endcase
+
+            end else begin
+                $display ("%m: At time %t ERROR: all banks must be Precharged before Extended Mode Register", $realtime);
+            end
+
+            // Precharge to EMR
+            if (($realtime - RP_chk0 < tRP - 0.001) || ($realtime - RP_chk1 < tRP - 0.001) ||
+                ($realtime - RP_chk2 < tRP - 0.001) || ($realtime - RP_chk3 < tRP - 0.001)) begin
+                $display ("%m: At time %t ERROR: tRP violation during Extended Mode Register", $realtime);
+            end
+
+            // LMR/EMR to LMR/EMR
+//            if ($realtime - MRD_chk < tMRD) begin
+//                $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime);
+//            end
+
+            if (MRD_cntr < tMRD) begin
+                $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime);
+            end
+
+            // Record current tMRD time
+//            MRD_chk = $realtime;
+            MRD_cntr = 0;
+        end
+    
+        // Load Mode Register
+        if (Mode_reg_enable === 1'b1) begin
+            if (Debug) begin
+                $display ("Debug: At time %t %m:LMR  : Load Mode Register", $realtime);
+            end
+
+            // Register Mode
+            Mode_reg = Addr;
+
+            if (Mode_reg[6:4] == 3'b010) begin
+                if (tCK2_min == 0) begin
+                    $display ("%m : at time %t ERROR : Illegal CAS Latency of 2 set for current speed grade", $realtime);
+                end
+            end
+
+            // Precharge to LMR
+            if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
+                $display ("%m: At time %t ERROR: all banks must be Precharged before Load Mode Register", $realtime);
+            end
+
+            // Precharge to LMR
+            if (($realtime - RP_chk0 < tRP - 0.001) || ($realtime - RP_chk1 < tRP - 0.001) ||
+                ($realtime - RP_chk2 < tRP - 0.001) || ($realtime - RP_chk3 < tRP - 0.001)) begin
+                $display ("%m: At time %t ERROR: tRP violation during Load Mode Register", $realtime);
+            end
+
+            // LMR/EMR to LMR/EMR
+//            if ($realtime - MRD_chk < tMRD) begin
+//                $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime);
+//            end
+            if (MRD_cntr < tMRD) begin
+                $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime);
+            end
+
+            if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin
+                // ensure that power sequence is met properly
+                if (~power_up_done) begin
+                    mode_load_done = 1'b1;
+                end
+               // Burst Length
+               case (Addr [2 : 0])
+                   3'b001  : $display ("At time %t %m:LMR  : Burst Length = 2", $realtime); 
+                   3'b010  : $display ("At time %t %m:LMR  : Burst Length = 4", $realtime);
+                   3'b011  : $display ("At time %t %m:LMR  : Burst Length = 8", $realtime);
+                   3'b100  : $display ("At time %t %m:LMR  : Burst Length = 16",$realtime);
+                   default : 
+                     begin
+                       $display ("%m: At time %t ERROR: Undefined burst length selection", $realtime);
+                       $stop;
+                     end
+               endcase
+   
+               // CAS Latency
+               case (Addr [6 : 4])
+                   3'b010  : $display ("At time %t %m:LMR  : CAS Latency = 2", $realtime);
+                   3'b011  : $display ("At time %t %m:LMR  : CAS Latency = 3", $realtime);
+                   default : begin
+                       $display ("%m: At time %t ERROR: CAS Latency not supported", $realtime);
+                       $stop;
+                   end
+               endcase
+   
+            end
+            // Record current tMRD time
+//            MRD_chk = $realtime;
+            MRD_cntr = 0;
+        end
+
+        // Activate Block
+        if (Active_enable === 1'b1) begin
+            if (!(power_up_done)) begin
+                $display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $realtime);
+            end
+            // Display Debug Message
+            if (Debug) begin
+                $display ("Debug: At time %t %m:ACTIVATE: Bank = %d, Row = %d", $realtime, Ba, Addr);
+            end
+
+            // Activating an open bank can cause corruption.
+            if ((Ba === 2'b00 && Pc_b0  === 1'b0) || (Ba === 2'b01 && Pc_b1  === 1'b0) ||
+                (Ba === 2'b10 && Pc_b2  === 1'b0) || (Ba === 2'b11 && Pc_b3  === 1'b0)) begin
+                $display ("%m: At time %t ERROR: Bank = %d is already activated - data can be corrupted", $realtime, Ba);
+            end
+            
+            // Activate Bank 0
+            if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
+                // Activate to Activate (same bank)
+                if ($realtime - RC_chk0 < tRC - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
+                end
+
+                // Precharge to Activate
+                if ($realtime - RP_chk0 < tRP - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
+                end
+
+                // Record variables for checking violation
+                Act_b0 = 1'b1;
+                Pc_b0 = 1'b0;
+                B0_row_addr = Addr;
+                RC_chk0  = $realtime;
+                RCD_chk0 = $realtime;
+                RAS_chk0 = $realtime;
+                RAP_chk0 = $realtime;
+            end
+
+            // Activate Bank 1
+            if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
+                // Activate to Activate (same bank)
+                if ($realtime - RC_chk1 < tRC - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
+                end
+
+                // Precharge to Activate
+                if ($realtime - RP_chk1 < tRP - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
+                end
+
+                // Record variables for checking violation
+                Act_b1 = 1'b1;
+                Pc_b1 = 1'b0;
+                B1_row_addr = Addr;
+                RC_chk1  = $realtime;
+                RCD_chk1 = $realtime;
+                RAS_chk1 = $realtime;
+                RAP_chk1 = $realtime;
+            end
+
+            // Activate Bank 2
+            if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
+                // Activate to Activate (same bank)
+                if ($realtime - RC_chk2 < tRC - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
+                end
+
+                // Precharge to Activate
+                if ($realtime - RP_chk2 < tRP - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
+                end
+
+                // Record variables for checking violation
+                Act_b2 = 1'b1;
+                Pc_b2 = 1'b0;
+                B2_row_addr = Addr;
+                RC_chk2  = $realtime;
+                RCD_chk2 = $realtime;
+                RAS_chk2 = $realtime;
+                RAP_chk2 = $realtime;
+            end
+
+            // Activate Bank 3
+            if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
+                // Activate to Activate (same bank)
+                if ($realtime - RC_chk3 < tRC - 0.001) begin
+                    $display ("%m:  t time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba);
+                end
+
+                // Precharge to Activate
+                if ($realtime - RP_chk3 < tRP - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba);
+                end
+
+                // Record variables for checking violation
+                Act_b3 = 1'b1;
+                Pc_b3 = 1'b0;
+                B3_row_addr = Addr;
+                RC_chk3  = $realtime;
+                RCD_chk3 = $realtime;
+                RAS_chk3 = $realtime;
+                RAP_chk3 = $realtime;
+            end
+
+            // Activate to Activate (different bank)
+            if ((Prev_bank != Ba) && ($realtime - RRD_chk < tRRD - 0.001)) begin
+                $display ("%m: At time %t ERROR: tRRD violation during Activate bank = %d", $realtime, Ba);
+            end
+            
+            // AutoRefresh to Activate
+            if ($realtime - RFC_chk < tRFC - 0.001) begin
+                $display ("%m: At time %t ERROR: tRFC violation during Activate bank %d", $realtime, Ba);
+            end
+
+            // Record variable for checking violation
+            RRD_chk = $realtime;
+            Prev_bank = Ba;
+        end
+    
+        // Precharge Block - consider NOP if bank already precharged or in process of precharging
+        if (Prech_enable === 1'b1) begin
+            // Display Debug Message
+            if (Debug) begin
+                $display ("Debug: At time %t %m:PRE: Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba);
+            end
+
+            // EMR or LMR to Precharge
+//            if ($realtime - MRD_chk < tMRD) begin
+//                $display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime);
+//            end
+            if (MRD_cntr < tMRD) begin
+                $display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime);
+            end
+
+            // Precharge bank 0
+            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
+                Act_b0 = 1'b0;
+                Pc_b0 = 1'b1;
+                RP_chk0 = $realtime;
+                
+                // Activate to Precharge Bank
+                if ($realtime - RAS_chk0 < tRAS - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
+                end
+                
+                // tWR violation check for Write
+                if ($realtime - WR_chk0 < tWR - 0.001) begin
+                    $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
+                end
+            end
+
+            // Precharge bank 1
+            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
+                Act_b1 = 1'b0;
+                Pc_b1 = 1'b1;
+                RP_chk1 = $realtime;
+
+                // Activate to Precharge Bank 1
+                if ($realtime - RAS_chk1 < tRAS - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
+                end
+                
+                // tWR violation check for Write
+                if ($realtime - WR_chk1 < tWR - 0.001) begin
+                    $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
+                end
+            end
+
+            // Precharge bank 2
+            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
+                Act_b2 = 1'b0;
+                Pc_b2 = 1'b1;
+                RP_chk2 = $realtime;
+                
+                // Activate to Precharge Bank 2
+                if ($realtime - RAS_chk2 < tRAS - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
+                end
+                
+                // tWR violation check for Write
+                if ($realtime - WR_chk2 < tWR - 0.001) begin
+                    $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
+                end
+            end
+
+            // Precharge bank 3
+            if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
+                Act_b3 = 1'b0;
+                Pc_b3 = 1'b1;
+                RP_chk3 = $realtime;
+                
+                // Activate to Precharge Bank 3
+                if ($realtime - RAS_chk3 < tRAS - 0.001) begin
+                    $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime);
+                end
+                
+                // tWR violation check for Write
+                if ($realtime - WR_chk3 < tWR - 0.001) begin
+                    $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime);
+                end
+            end
+
+            // Pipeline for READ
+            if ((Addr[10] === 1'b1) | (Ba == Write_bank_pipeline[4]))
+                for (i = 4; i < `MAX_PIPE; i = i + 1)
+                    Read_pipeline[i] = 1'b0 ;
+    
+        end
+    
+        // Burst terminate
+        if (Burst_term === 1'b1) begin
+            // Display Debug Message
+            if (Debug) begin
+                $display ("Debug: %m: At time %t BURST_TERMINATE): Burst Terminate",$realtime);
+            end
+
+            // Burst Terminate Command Pipeline for Read
+            for (i = cas_latency_x2-1; i < `MAX_PIPE; i = i + 1)
+                Read_pipeline[i] = 1'b0 ;
+            // Illegal to burst terminate a Write
+            if ((Data_in_enable === 1'b1) & ~((&dm_rise) & (&dm_fall))) begin
+                $display ("%m: At time %t ERROR: It's illegal to burst terminate a Write", $realtime);
+            end
+            
+            // Illegal to burst terminate a Read with Auto Precharge
+            if (|Read_precharge_access) begin
+                $display ("%m: At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $realtime);
+            end
+        end
+        
+        // Read Command
+        if (Read_enable === 1'b1) begin
+            if (!(power_up_done)) begin
+                $display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $realtime);
+            end
+            // Display Debug Message
+            if (Debug) begin
+                $display ("Debug: At time %t %m:READ: Bank = %d, Col = %d", $realtime, Ba, {Addr [11], Addr [9 : 0]});
+            end
+            if (part_size == 1024) begin
+                if (SRR_read == 1'b1) begin
+                    if (SRR_cntr < tSRR) begin
+                        $display ("%m: At time %t ERROR: tSRR Violation", $realtime);
+                    end
+                    SRC_cntr = 0 ;
+                end
+            end else begin
+                if (SRR_read == 1'b1) begin
+                    if ($realtime - SRR_chk < tSRR-0.01) begin
+                        $display ("%m: At time %t ERROR: tSRR Violation", $realtime);
+                    end
+                    SRC_cntr = 0;
+                end
+            end
+            // CAS Latency pipeline
+            if (SRR_read) begin
+                if ({Ba, Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]} > 0) begin
+                   $display ("%m: At time %t ERROR: Address must be all 0 during SRR Read", $realtime);
+                end
+                for (i=0; i<2; i=i+1)          
+                begin
+                    Read_pipeline[cas_latency_x2 - 2 + i + 1] = 1'b1;
+                    Write_col_pipeline [cas_latency_x2 - 2 + i + 1] = i;
+                    Write_bank_pipeline [cas_latency_x2 - 2 + i + 1] = 0;
+                end
+            end else begin
+                for (i=0; i<burst_length; i=i+1)          
+                begin
+                    Read_pipeline[cas_latency_x2 - 2 + i + 1] = 1'b1;
+                    Write_bank_pipeline [cas_latency_x2 - 2 + i + 1] = Ba;
+                    Write_col_pipeline [cas_latency_x2 - 2 + i + 1] = Burst_Order({Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}, i);
+                end
+            end
+
+            // Clear out Write Pipeline
+            Write_pipeline = 64'b0;
+
+            // Interrupt a Read with Auto Precharge
+            if (Read_precharge_access [Ba] === 1'b1) begin
+                $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime);
+            end else if ((Read_precharge_access [0] === 1'b1) |
+                         (Read_precharge_access [1] === 1'b1) |
+                         (Read_precharge_access [2] === 1'b1) |
+                         (Read_precharge_access [3] === 1'b1) ) begin
+                $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (different banks)", $realtime);
+            end
+
+            // Interrupt a Write with Auto Precharge
+            if (Write_precharge_access [Ba] === 1'b1) begin
+//                $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same banks)", $realtime);
+            end else if ((Write_precharge_count [0] < (burst_length/2  )) & (Mode_reg[6:4] == 3'b010) |
+                         (Write_precharge_count [1] < (burst_length/2  )) & (Mode_reg[6:4] == 3'b010) |
+                         (Write_precharge_count [2] < (burst_length/2  )) & (Mode_reg[6:4] == 3'b010) |
+                         (Write_precharge_count [3] < (burst_length/2  )) & (Mode_reg[6:4] == 3'b010) |
+                         (Write_precharge_count [0] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
+                         (Write_precharge_count [1] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
+                         (Write_precharge_count [2] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) |
+                         (Write_precharge_count [3] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) ) begin
+                $display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Write with Auto Precharge (different banks)", $realtime);
+            end
+
+            // Activate to Read
+            if (((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
+                 (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) &&
+                (SRR_read == 1'b0)) begin
+                $display("%m: At time %t ERROR: Bank is not Activated for Read", $realtime);
+            end
+
+            // Activate to Read without Auto Precharge
+            if ((Addr [10] === 1'b0 && Ba === 2'b00 && $realtime - RCD_chk0 < tRCD - 0.001) ||
+                (Addr [10] === 1'b0 && Ba === 2'b01 && $realtime - RCD_chk1 < tRCD - 0.001) ||
+                (Addr [10] === 1'b0 && Ba === 2'b10 && $realtime - RCD_chk2 < tRCD - 0.001) ||
+                (Addr [10] === 1'b0 && Ba === 2'b11 && $realtime - RCD_chk3 < tRCD - 0.001)) begin
+                $display("%m: At time %t ERROR: tRCD violation during Read", $realtime);
+            end
+
+            // Auto Precharge
+            if (Addr[10] === 1'b1) begin
+                Read_precharge_access [Ba]= 1'b1;
+                Count_precharge [Ba]= 0;
+                Read_precharge_count[Ba] = 4'h0;
+            end
+            
+            // tWTR
+            if (tWTR_cntr < tWTR - 0.001) begin
+                $display("%m: At time %t ERROR: tWTR violation during Read", $realtime);
+            end
+        end
+
+        // Write Command
+        if (Write_enable === 1'b1) begin
+            if (!(power_up_done)) begin
+                $display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $realtime);
+            end
+            // display debug message
+            if (Debug) begin
+                $display ("Debug: At time %t %m:WRITE: Bank = %d, Col = %d", $realtime, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
+            end
+
+            // Pipeline for Write
+//            Write_pipeline [3] = 1'b1;
+            for (i=0; i<burst_length; i=i+1)          
+            begin
+                Write_pipeline[1 + i] = 1'b1;
+//                Write_col_pipeline [1 + i] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]} + i;
+                Write_col_pipeline [1 + i] = Burst_Order({Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}, i);
+                Write_bank_pipeline [1 + i] = Ba;
+
+            end
+
+            // Interrupt a Write with Auto Precharge (same bank only)
+            if (Write_precharge_access [Ba] === 1'b1) begin
+                $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge", $realtime);
+            end
+
+            // Activate to Write
+            if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
+                (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
+                $display("%m: At time %t ERROR: Bank is not Activated for Write", $realtime);
+            end
+
+            // Activate to Write
+            if ((Ba === 2'b00 && $realtime - RCD_chk0 < tRCD - 0.001) ||
+                (Ba === 2'b01 && $realtime - RCD_chk1 < tRCD - 0.001) ||
+                (Ba === 2'b10 && $realtime - RCD_chk2 < tRCD - 0.001) ||
+                (Ba === 2'b11 && $realtime - RCD_chk3 < tRCD - 0.001)) begin
+                $display("%m: At time %t ERROR: tRCD violation during Write to Bank %d", $realtime, Ba);
+            end
+
+            if (Read_pipeline[0]) begin
+                $display("%m: At time %t ERROR: Read to Write violation", $realtime);
+            end
+
+            // Interrupt a Write with Auto Precharge
+            if (Write_precharge_access [Ba] === 1'b1) begin
+                $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same bank)", $realtime);
+            end else if (((Write_precharge_access [0] === 1'b1) & (Count_precharge[0] < (burst_length/2))) |
+                         ((Write_precharge_access [1] === 1'b1) & (Count_precharge[1] < (burst_length/2))) |
+                         ((Write_precharge_access [2] === 1'b1) & (Count_precharge[2] < (burst_length/2))) |
+                         ((Write_precharge_access [3] === 1'b1) & (Count_precharge[3] < (burst_length/2))) ) begin
+                $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (different bank)", $realtime);
+            end
+
+            // Interrupt a Read with Auto Precharge
+            if (((Read_precharge_count [Ba] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | 
+                ((Read_precharge_count [Ba] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin
+//                $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime);
+            end else if (((Read_precharge_count [0] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
+                         ((Read_precharge_count [1] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
+                         ((Read_precharge_count [2] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
+                         ((Read_precharge_count [3] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) |
+                         ((Read_precharge_count [0] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
+                         ((Read_precharge_count [1] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
+                         ((Read_precharge_count [2] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) |
+                         ((Read_precharge_count [3] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin
+                $display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Read with Auto Precharge (different bank)", $realtime);
+            end
+            
+            // Auto Precharge
+            if (Addr[10] === 1'b1) begin
+                Write_precharge_access [Ba]= 1'b1;
+                Count_precharge [Ba]= 0;
+                Write_precharge_count[Ba] = 4'h0;
+            end
+        end
+
+    end
+    endtask
+
+    // Main Logic
+    always @ (posedge Sys_clk) begin
+        ShiftPipelines;
+//        Manual_Precharge_Pipeline;
+//        Burst_Terminate_Pipeline;
+        Dq_Dqs_Drivers;
+        Write_FIFO_DM_Mask_Logic;
+        Burst_Decode;
+        Auto_Precharge_Calculation;
+        Timing_chk_SRC;
+        Control_Logic;
+        MRD_counter;
+        SRR_counter;
+        SRC_counter;
+        tWTR_counter;
+        command_counter;
+    end
+
+    always @ (negedge Sys_clk) begin
+        ShiftPipelines;
+//        Manual_Precharge_Pipeline;
+//        Burst_Terminate_Pipeline;
+        Dq_Dqs_Drivers;
+        Write_FIFO_DM_Mask_Logic;
+        Burst_Decode;
+    end
+
+    // Dqs Receiver
+    always @ (posedge Dqs_in[0]) begin
+        // Latch data at posedge Dqs
+        dq_rise[7 : 0] = Dq_in[7 : 0];
+        dm_rise[0] = Dm_in[0];
+        expect_pos_dqs[0] = 0;
+    end
+
+    always @ (posedge Dqs_in[1]) begin
+        // Latch data at posedge Dqs
+        dq_rise[15 : 8] = Dq_in[15 : 8];
+        dm_rise[1] = Dm_in[1];
+        expect_pos_dqs[1] = 0;
+    end
+
+`ifdef x32
+    always @ (posedge Dqs_in[2]) begin
+        // Latch data at posedge Dqs
+        dq_rise[23 : 16] = Dq_in[23 : 16];
+        dm_rise[2] = Dm_in[2];
+        expect_pos_dqs[2] = 0;
+    end
+
+    always @ (posedge Dqs_in[3]) begin
+        // Latch data at posedge Dqs
+        dq_rise[31 : 24] = Dq_in[31 : 24];
+        dm_rise[3] = Dm_in[3];
+        expect_pos_dqs[3] = 0;
+    end
+`endif
+
+    always @ (negedge Dqs_in[0]) begin
+        // Latch data at negedge Dqs
+        dq_fall[7 : 0] = Dq_in[7 : 0];
+        dm_fall[0] = Dm_in[0];
+        dm_pair[1:0]  = {dm_rise[0], dm_fall[0]};
+        expect_neg_dqs[0] = 0;
+    end
+
+    always @ (negedge Dqs_in[1]) begin
+        // Latch data at negedge Dqs
+        dq_fall[15: 8] = Dq_in[15 : 8];
+        dm_fall[1] = Dm_in[1];
+        dm_pair[3:2]  = {dm_rise[1], dm_fall[1]};
+        expect_neg_dqs[1] = 0;
+    end
+
+`ifdef x32
+    always @ (negedge Dqs_in[2]) begin
+        // Latch data at negedge Dqs
+        dq_fall[23: 16] = Dq_in[23 : 16];
+        dm_fall[2] = Dm_in[2];
+        dm_pair[5:4]  = {dm_rise[2], dm_fall[2]};
+        expect_neg_dqs[2] = 0;
+    end
+
+    always @ (negedge Dqs_in[3]) begin
+        // Latch data at negedge Dqs
+        dq_fall[31: 24] = Dq_in[31 : 24];
+        dm_fall[3] = Dm_in[3];
+        dm_pair[7:6]  = {dm_rise[3], dm_fall[3]};
+        expect_neg_dqs[3] = 0;
+    end
+`endif
+
+    // Dqs edge checking
+    always @ (posedge Sys_clk) begin
+//        if (Write_pipeline[2] || Write_pipeline[1] || Data_in_enable) begin
+        if (Write_pipeline[-1]) begin
+            for (i=0; i<DQS_BITS; i=i+1) begin
+                if (expect_neg_dqs[i]) begin
+                    $display ("%m: At time %t ERROR: Negative DQS[%1d] transition required.", $realtime, i);
+                end
+                expect_neg_dqs[i] = 1'b1;
+            end
+        end else begin
+           expect_neg_dqs = 0;
+           expect_pos_dqs = 0;
+        end
+    end
+
+    always @ (negedge Sys_clk) begin
+//        if (Write_pipeline[2] || Write_pipeline[1] || Data_in_enable) begin
+        if (Write_pipeline[-1]) begin
+            for (i=0; i<DQS_BITS; i=i+1) begin
+                if (expect_pos_dqs[i]) begin
+                    $display ("%m: At time %t ERROR: Positive DQS[%1d] transition required.", $realtime, i);
+                end
+                expect_pos_dqs[i] = 1'b1;
+            end
+        end else begin
+           expect_neg_dqs = 0;
+           expect_pos_dqs = 0;
+        end
+    end
+
+    specify
+                                                   // SYMBOL UNITS DESCRIPTION
+                                                   // ------ ----- -----------
+`ifdef sg5                                         //              specparams for -6 (CL = 3)
+        specparam tCLK_MIN         =     5.0 ;     // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.0 ;     // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.0 ;     // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     1.0 ;     // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     1.0 ;     // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     1.75;     // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     1.75;     // tDQSL  ns    DQS input Low Pulse Width
+`elsif sg54                                  //              specparams for -6 (CL = 3)
+        specparam tCLK_MIN         =     5.4;      // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.08;     // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.08;     // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     1.0;      // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     1.0;      // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     2.16;     // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     2.16;     // tDQSL  ns    DQS input Low Pulse Width
+`elsif sg6                                   //              specparams for -6 (CL = 3)
+        specparam tCLK_MIN         =     6.0;      // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.2;      // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.2;      // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     1.1;      // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     1.1;      // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     2.1;      // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     2.1;      // tDQSL  ns    DQS input Low Pulse Width
+`elsif sg75                                  //              specparams for -75  (CL = 3)
+        specparam tCLK_MIN         =     7.5;      // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.5;      // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.5;      // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     1.3;      // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     1.3;      // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     3.0;      // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     3.0;      // tDQSL  ns    DQS input Low Pulse Width
+`elsif sg5v18                                 //              specparams for -6 (CL = 3)
+        specparam tCLK_MIN         =     5.0 ;     // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.0 ;     // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.0 ;     // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     0.9 ;     // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     0.9 ;     // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     2.0 ;     // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     2.0 ;     // tDQSL  ns    DQS input Low Pulse Width
+`elsif sg6v18                                //              specparams for -6 (CL = 3)
+        specparam tCLK_MIN         =     6.0;      // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.2;      // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.2;      // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     1.1;      // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     1.1;      // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     2.4;      // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     2.4;      // tDQSL  ns    DQS input Low Pulse Width
+`elsif sg75v18                               //              specparams for -75  (CL = 3)
+        specparam tCLK_MIN         =     7.5;      // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.5;      // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.5;      // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     1.3;      // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     1.3;      // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     3.0;      // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     3.0;      // tDQSL  ns    DQS input Low Pulse Width
+`elsif sg6v12                                //              specparams for -6 (CL = 3)
+        specparam tCLK_MIN         =     6.0;      // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.2;      // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.2;      // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     1.1;      // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     1.1;      // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     2.1;      // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     2.1;      // tDQSL  ns    DQS input Low Pulse Width
+`elsif sg75v12                               //              specparams for -75  (CL = 3)
+        specparam tCLK_MIN         =     7.5;      // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.5;      // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.5;      // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     1.3;      // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     1.3;      // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     3.0;      // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     3.0;      // tDQSL  ns    DQS input Low Pulse Width
+`elsif sg10v12                               //              specparams for -10 (CL = 3)
+        specparam tCLK_MIN         =     9.6;      // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.92;     // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.92;     // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     1.7;      // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     1.7;      // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     3.84;     // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     3.84;     // tDQSL  ns    DQS input Low Pulse Width
+`else `define sg10                                 //              specparams for -10 (CL = 3)
+        specparam tCLK_MIN         =     9.6;      // tCLK   ns    minimum clk cycle time
+        specparam tDSS             =     1.92;     // tDSS   ns    DQS falling edge to CLK rising (setup time)
+        specparam tDSH             =     1.92;     // tDSH   ns    DQS falling edge from CLK rising (hold time)
+        specparam tIH              =     1.5;      // tIH    ns    Input Hold Time (fast)
+        specparam tIS              =     1.5;      // tIS    ns    Input Setup Time (fast)
+        specparam tDQSH            =     3.84;     // tDQSH  ns    DQS input High Pulse Width
+        specparam tDQSL            =     3.84;     // tDQSL  ns    DQS input Low Pulse Width
+`endif
+        $period   (posedge Clk, tCLK_MIN);
+        $width    (posedge Dqs_in[0] &&& wdqs_valid, tDQSH);
+        $width    (posedge Dqs_in[1] &&& wdqs_valid, tDQSH);
+        $width    (negedge Dqs_in[0] &&& wdqs_valid, tDQSL);
+        $width    (negedge Dqs_in[1] &&& wdqs_valid, tDQSL);
+        $setuphold(posedge Clk,   Cke,   tIS, tIH);
+        $setuphold(posedge Clk,   Cs_n,  tIS, tIH);
+        $setuphold(posedge Clk,   Cas_n, tIS, tIH);
+        $setuphold(posedge Clk,   Ras_n, tIS, tIH);
+        $setuphold(posedge Clk,   We_n,  tIS, tIH);
+        $setuphold(posedge Clk,   Addr,  tIS, tIH);
+        $setuphold(posedge Clk,   Ba,    tIS, tIH);
+        $setuphold(posedge Clk, negedge Dqs &&& wdqs_valid, tDSS , tDSH);
+    endspecify
+
+endmodule
diff --git a/sim/verilog/micron_mobile_ddr/mobile_ddr_mcp.v b/sim/verilog/micron_mobile_ddr/mobile_ddr_mcp.v
new file mode 100644
index 0000000..7f46762
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/mobile_ddr_mcp.v
@@ -0,0 +1,84 @@
+/****************************************************************************************
+*
+*    File Name:  mobile_ddr_mcp.v
+*
+* Dependencies:  mobile_ddr.v, mobile_ddr_parameters.vh
+*
+*  Description:  Micron MOBILE DDR SDRAM multi-chip package model
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2008 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+`timescale 1ns / 1ps
+
+module mobile_ddr_mcp (
+    Clk   ,     
+    Clk_n ,     
+    Cke   ,     
+    Cs_n  ,     
+    Ras_n ,     
+    Cas_n ,     
+    We_n  ,     
+    Addr  ,     
+    Ba    ,     
+    Dq    ,     
+    Dqs   ,     
+    Dm          
+);
+
+    `include "mobile_ddr_parameters.vh"
+
+    // Declare Ports
+    input                         Clk   ;
+    input                         Clk_n ;
+    input       [CS_BITS - 1 : 0] Cke   ;
+    input       [CS_BITS - 1 : 0] Cs_n  ;
+    input                         Ras_n ;
+    input                         Cas_n ;
+    input                         We_n  ;
+    input     [ADDR_BITS - 1 : 0] Addr  ;
+    input                 [1 : 0] Ba    ;
+    inout       [DQ_BITS - 1 : 0] Dq    ;
+    inout      [DQS_BITS - 1 : 0] Dqs   ;
+    input       [DM_BITS - 1 : 0] Dm    ;
+
+    wire [RANKS - 1 : 0] Cke_mcp = Cke   ;
+    wire [RANKS - 1 : 0] Cs_n_mcp = Cs_n ;
+
+    mobile_ddr rank [RANKS - 1:0] (
+        .Clk   ( Clk       ) ,     
+        .Clk_n ( Clk_n     ) ,     
+        .Cke   ( Cke_mcp   ) ,     
+        .Cs_n  ( Cs_n_mcp  ) ,     
+        .Ras_n ( Ras_n     ) ,     
+        .Cas_n ( Cas_n     ) ,     
+        .We_n  ( We_n      ) ,     
+        .Addr  ( Addr      ) ,     
+        .Ba    ( Ba        ) ,     
+        .Dq    ( Dq        ) ,     
+        .Dqs   ( Dqs       ) ,     
+        .Dm    ( Dm        )      
+    );
+
+endmodule
diff --git a/sim/verilog/micron_mobile_ddr/readme.txt b/sim/verilog/micron_mobile_ddr/readme.txt
new file mode 100644
index 0000000..bd3b59d
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/readme.txt
@@ -0,0 +1,167 @@
+Disclaimer of Warranty:
+-----------------------
+This software code and all associated documentation, comments or other 
+information (collectively "Software") is provided "AS IS" without 
+warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+DAMAGES. Because some jurisdictions prohibit the exclusion or 
+limitation of liability for consequential or incidental damages, the 
+above limitation may not apply to you.
+
+Copyright 2008 Micron Technology, Inc. All rights reserved.
+
+Getting Started:
+----------------
+Unzip the included files to a folder.
+Compile mobile_ddr.v and tb.v using a verilog simulator.
+Simulate the top level test bench tb.
+Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
+
+File Descriptions:
+------------------
+mobile_ddr.v                    --mobile ddr model 
+mobile_ddr_mcp.v                --structural wrapper for mobile_ddr multi-chip package model
+128Mb_mobile_ddr_parameters.vh  --File that contains all parameters used by the model
+256Mb_mobile_ddr_parameters.vh  --File that contains all parameters used by the model
+512Mb_mobile_ddr_parameters.vh  --File that contains all parameters used by the model
+1024Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
+2048Mb_mobile_ddr_parameters.vh --File that contains all parameters used by the model
+readme.txt                      --This file
+tb.v                            --Test bench
+tb.do                           --File that compiles and runs the above files
+
+Defining the Density (part size):
+-------------------------
+The verilog compiler directive "`define" may be used to choose between on of the
+densities supported by the mobile ddr model.  Allowable densities are listed in
+the *.vh file.  The density is used to select a set of bank, row, column, and timing 
+parameters for the mobile ddr model.  The following are examples of defining 
+the density.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+den512Mb mobile_ddr.v
+    VCS         vcs +define+den512Mb mobile_ddr.v
+    NC-Verilog  ncverilog +define+den512Mb mobile_ddr.v
+
+
+Defining the Speed Grade:
+-------------------------
+The verilog compiler directive "`define" may be used to choose between 
+multiple speed grades supported by the mobile ddr model.  Allowable speed 
+grades are listed in the mobile_ddr_parameters.vh file and begin with the 
+letters "sg".  The speed grade is used to select a set of timing 
+parameters for the mobile ddr model.  The following are examples of defining 
+the speed grade.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+sg75 mobile_ddr.v
+    VCS         vcs +define+sg75 mobile_ddr.v
+    NC-Verilog  ncverilog +define+sg75 mobile_ddr.v
+
+
+Defining the Organization:
+--------------------------
+The verilog compiler directive "`define" may be used to choose between 
+multiple organizations supported by the mobile ddr model.  Valid 
+organizations include "x16" and "x32", and are listed in the 
+mobile_ddr_parameters.vh file.  The organization is used to select the amount 
+of memory and the port sizes of the mobile ddr model.  The following are
+examples of defining the organization.
+
+    vlog +define+x16 mobile_ddr.v
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+x16 mobile_ddr.v
+    VCS         vcs +define+x16 mobile_ddr.v
+    NC-Verilog  ncverilog +define+x16 mobile_ddr.v
+
+All combinations of speed grade and organization are considered valid 
+by the mobile ddr model even though a Micron part may not exist for every 
+combination.
+
+Allocating Memory:
+------------------
+An associative array has been implemented to reduce the amount of 
+static memory allocated by the mobile ddr model.  The number of 
+entries in the associative array is controlled by the part_mem_bits 
+parameter, and is equal to 2^part_mem_bits.  For example, if the 
+part_mem_bits parameter is equal to 10, the associative array will be 
+large enough to store 1024 write data transfers to unique addresses.  
+The following are examples of setting the MEM_BITS parameter to 8.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vsim -Gpart_mem_bits=8 mobile_ddr
+    VCS         vcs -pvalue+part_mem_bits=8 mobile_ddr.v
+    NC-Verilog  ncverilog +defparam+mobile_ddr.part_mem_bits=8 mobile_ddr.v
+
+It is possible to allocate memory for every address supported by the 
+mobile ddr model by using the verilog compiler directive "`define FULL_MEM".
+This procedure will improve simulation performance at the expense of 
+system memory.  The following are examples of allocating memory for
+every address.
+
+    Simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+FULL_MEM mobile_ddr.v
+    VCS         vcs +define+FULL_MEM mobile_ddr.v
+    NC-Verilog  ncverilog +define+FULL_MEM mobile_ddr.v
+
+
+Reduced Page Mode:
+------------------
+Mobile DDR 256Mb, 512Mb, and 1024Mb part may be built with the reduced page size
+architecture. This part is accessed with the +define+RP designator. RP
+parts have one extra row bit and one less column bit effectively cutting
+the page size in half but doubling the number of rows keeping total part
+size the same.
+
+    Part Size   Valid RP Designators
+    ---------   --------------------
+    256Mb       +define+RP
+    512Mb       +define+RP
+    1024Mb      +define+RP
+
+    Simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+RP mobile_ddr.v
+    VCS         vcs +define+RP mobile_ddr.v
+    NC-Verilog  ncverilog +define+RP mobile_ddr.v
+
+Multi-Chip Package Model:
+-------------------------
+The 1024Mb model can be supported in a Multi Chip Package, that allows
+multiple die models in one structural package. The number of ranks and 
+chip selects of the mcp can be configured by using the `DUAL_RANK define 
+on the simulator call line.  The currently supported configurations are 
+listed below:
+
+    Package Configuration   Valid MCP Designator
+    ---------------------   --------------------
+    2 Chip Selects, 2 Die   +define+DUAL_RANK
+    2 Chip Selects, 1 Die   (default)
+
+The single rank mcp is the default.  In order to simulate the DUAL_RANK 
+model, the define needs to be added:
+
+    Simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+DUAL_RANK mobile_ddr.v mobile_ddr_mcp.v
+    VCS         vcs +define+DUAL_RANK mobile_ddr.v mobile_ddr_mcp.v
+    NC-Verilog  ncverilog +define+DUAL_RANK mobile_ddr.v mobile_ddr_mcp.v
+
diff --git a/sim/verilog/micron_mobile_ddr/subtest.vh b/sim/verilog/micron_mobile_ddr/subtest.vh
new file mode 100644
index 0000000..8813f15
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/subtest.vh
@@ -0,0 +1,32 @@
+initial begin:test
+    //ck     <= 1'b0;
+    cke    <= 1'b0;
+    cs_n   <= 1'bz;
+    ras_n  <= 1'bz;
+    cas_n  <= 1'bz;
+    we_n   <= 1'bz;
+    a      <= {ADDR_BITS{1'bz}}; 
+    ba     <= {BA_BITS{1'bz}};
+    dq_en  <= 1'b0;
+    dqs_en <= 1'b0;
+    power_up;
+    nop (10); // wait 10 clocks intead of 200 us for simulation purposes
+    precharge('h00000000, 1);
+    nop(trp);
+    refresh;
+    nop(trfc);
+    refresh;
+    nop(trfc);
+    load_mode('h0, 'h00000032);
+    nop(tmrd);
+    load_mode('h2, 'h00004000);
+    nop(tmrd);
+    activate('h00000000, 'h00000000);
+    nop(trcd-1);
+    write('h00000000, 'h00000000, 0, { {DM_BITS{1'b0}}, {DM_BITS{1'b0}}, {DM_BITS{1'b0}}, {DM_BITS{1'b0}}}, { 16'h3000, 16'h2000, 16'h1000, 16'h0});
+    nop(bl/2+twr);
+    read('h00000000, 'h00000000, 1);
+    nop(bl/2-1);
+    nop('h00000014);
+    test_done;
+end
diff --git a/sim/verilog/micron_mobile_ddr/tb.do b/sim/verilog/micron_mobile_ddr/tb.do
new file mode 100644
index 0000000..9dce78e
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/tb.do
@@ -0,0 +1,39 @@
+#########################################################################################
+#
+#   Disclaimer   This software code and all associated documentation, comments or other 
+#  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+#                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+#                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+#                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+#                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+#                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+#                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+#                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+#                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+#                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+#                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+#                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+#                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+#                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+#                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+#                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+#                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+#                limitation of liability for consequential or incidental damages, the 
+#                above limitation may not apply to you.
+#
+#                Copyright 2005 Micron Technology, Inc. All rights reserved.
+#
+#########################################################################################
+
+vlib work
+vlog +define+den512Mb +define+sg75 +define+x16 mobile_ddr.v tb.v
+vsim tb
+add wave -p mobile_ddr/*
+run -a
+
+# For Reduced Page Parts run the following and comment out the lines above :
+
+#vlog +define+den512Mb  +define+sg75 +define+x32 mobile_ddr.v tb.v
+#vsim tb
+#add wave -p mobile_ddr/*
+#run -a
diff --git a/sim/verilog/micron_mobile_ddr/tb.v b/sim/verilog/micron_mobile_ddr/tb.v
new file mode 100644
index 0000000..92a6ba2
--- /dev/null
+++ b/sim/verilog/micron_mobile_ddr/tb.v
@@ -0,0 +1,587 @@
+/****************************************************************************************
+*
+*    File Name:  tb.v
+*      Version:  6.00
+*        Model:  BUS Functional
+*
+* Dependencies:  mobile_ddr.v, mobile_ddr_parameters.vh, subtest.vh
+*
+*  Description:  Micron SDRAM DDR (Double Data Rate) test bench
+*
+*         Note: -Set simulator resolution to "ps" accuracy
+*               -Set Debug = 0 to disable $display messages
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+* Rev  Author Date        Changes
+* ---  ------ ----------  ---------------------------------------
+* 4.1  JMK    01/14/2001  -Grouped specify parameters by speed grade
+*                         -Fixed mem_sizes parameter
+* 2.1  SPH    03/19/2002  -Second Release
+*                         -Fix tWR and several incompatability
+*                            between different simulators
+* 3.0  TFK    02/18/2003  -Added tDSS and tDSH timing checks.
+*                         -Added tDQSH and tDQSL timing checks.
+* 3.1  CAH    05/28/2003  -update all models to release version 3.1
+*                            (no changes to this model)
+* 3.2  JMK    06/16/2003  -updated all DDR400 models to support CAS Latency 3
+* 3.3  JMK    09/11/2003  -Added initialization sequence checks.
+* 4.0  JMK    12/01/2003  -Grouped parameters into "ddr_parameters.v"
+*                         -Fixed tWTR check
+* 4.2  JMK    03/19/2004  -Fixed pulse width checking on dqs
+* 4.3  JMK    04/27/2004  -Changed bl wire size in tb module
+*                         -Changed Dq_buf size to [15:0]
+* 5.0  JMK    06/16/2004  -Added read to write checking.
+*                         -Added read with precharge truncation to write checking.
+*                         -Added associative memory array to reduce memory consumption.
+*                         -Added checking for required DQS edges during write.
+* 6.0  DMR    12/03/2004  -new density
+* 6.01 BAAB   05/18/2006  -assimilating into Minneapolis site organization
+* 3.11 BAS    10/18/2006  -added read_verify
+* 3.35 bas    02/28/07    -mobile_ddr.v file  uses tAC correctly to calculate strobe/data launch
+* 3.36 bas    03/05/07    -fixed error messages for different banks interrupting 
+                             reads/writes w/autoprecharge
+* 3.37 bas    03/21/07    -added T47M part for 512Mb in parameters file,
+                             modified tXP check to measure in tCLK for T47M
+* 3.60 clk    09/19/07    -fixed dm/dq verification fifo's
+* 3.60 clk    09/19/07    -fixed dqrx module delay statement
+* 3.80 clk    10/29/07    - Support for 1024Mb T48M
+* 4.00 clk    12/30/07    - Fixed Read terminated by precharge testcase
+* 4.70 clk    03/30/08    - Fixed typo in SRR code
+* 4.80 clk    04/03/08    - Disable clk checking during initialization
+* 4.90 clk    04/16/08    - Fixed tInit, added mpc support, updated t35m timing
+* 5.00 clk    05/14/08    - Fixed back to back auto precharge commands          
+* 5.20 clk    05/21/08    - Fixed read interrupt by pre (BL8), fixed 1024Mb parameter file
+* 5.30 clk    05/22/08    - Fixed DM signal which cause false tWTR errors                    
+              05/27/08    - Rewrote write and read pipelins, strobes
+* 5.40 clk    05/28/08    - Fixed Addressing problem in Burst Order logic
+* 5.50 clk    07/25/08    - Added T36N part type                                   
+* 5.60 clk    09/05/08    - Fixed tXP in 256Mb part type                           
+* 5.70 clk    09/17/08    - Fixed burst term check for write w/ all DM active       
+* 5.80 clk    11/18/08    - Fixed internally latched dq & mask widths
+* 5.90 clk    12/10/08    - Updated T36N parameters to latest datasheet
+* 6.00 clk    03/05/09    - Fixed DQS problem w/ CL = 2
+****************************************************************************************/
+
+`timescale 1ns / 1ps
+
+module tb;
+
+`ifdef den128Mb
+    `include "128Mb_mobile_ddr_parameters.vh"
+`elsif den256Mb
+    `include "256Mb_mobile_ddr_parameters.vh"
+`elsif den512Mb
+    `include "512Mb_mobile_ddr_parameters.vh"
+`elsif den1024Mb
+    `include "1024Mb_mobile_ddr_parameters.vh"
+`elsif den2048Mb
+    `include "2048Mb_mobile_ddr_parameters.vh"
+`else
+    // NOTE: Intentionally cause a compile fail here to force the users
+    //       to select the correct component density before continuing
+    ERROR: You must specify component density with +define+den____Mb.
+`endif
+
+    reg                         ck_tb       ;
+    reg                         ck_enable = 1'b1 ;
+    // ports
+    wire                        ck;
+    wire                        ck_n = ~ck;
+    reg                         cke = 1'b0;
+    reg                         cs_n;
+    reg                         ras_n;
+    reg                         cas_n;
+    reg                         we_n;
+    reg           [BA_BITS-1:0] ba;
+    reg         [ADDR_BITS-1:0] a;
+    wire          [DM_BITS-1:0] dm;
+    wire          [DQ_BITS-1:0] dq;
+    wire         [DQS_BITS-1:0] dqs;
+
+    // mode registers
+    reg         [ADDR_BITS-1:0] mode_reg0;                                 //Mode Register
+    reg         [ADDR_BITS-1:0] mode_reg1;                                 //Extended Mode Register
+    wire                  [2:0] cl       = mode_reg0[6:4];                 //CAS Latency
+    wire                        bo       = mode_reg0[3];                   //Burst Order
+    wire                  [7:0] bl       = (1<<mode_reg0[2:0]);            //Burst Length
+    wire                        wl       = 1;                              //Write Latency
+
+    // dq transmit
+    reg                         dq_en;
+    reg           [DM_BITS-1:0] dm_out;
+    reg           [DQ_BITS-1:0] dq_out;
+    reg                         dqs_en;
+    reg          [DQS_BITS-1:0] dqs_out;
+    assign                      dm       = dq_en ? dm_out : {DM_BITS{1'b0}};
+    assign                      dq       = dq_en ? dq_out : {DQ_BITS{1'bz}};
+    assign                      dqs      = dqs_en ? dqs_out : {DQS_BITS{1'bz}};
+
+    // dq receive
+    reg           [DM_BITS-1:0] dm_fifo [2*CL_MAX+16:0];
+    reg           [DQ_BITS-1:0] dq_fifo [2*CL_MAX+16:0];
+    wire          [DQ_BITS-1:0] q0, q1, q2, q3;
+    reg                         ptr_rst_n;
+    reg                   [1:0] burst_cntr;
+
+    // timing definition in tCK units
+    real                        tck;
+    wire                 [11:0] trc   = tRC;
+    wire                 [11:0] trrd  = ceil(tRRD/tck);
+    wire                 [11:0] trcd  = ceil(tRCD/tck);
+    wire                 [11:0] tras  = ceil(tRAS/tck);
+    wire                 [11:0] twr   = ceil(tWR/tck);
+    wire                 [11:0] trp   = ceil(tRP/tck);
+    wire                 [11:0] tmrd  = tMRD;
+    wire                 [11:0] trfc  = ceil(tRFC/tck);
+    wire                 [11:0] tsrr  = ceil(tSRR);
+    wire                 [11:0] tsrc  = ceil(tSRC);
+    wire                 [11:0] tdqsq = tDQSQ;
+    wire                 [11:0] twtr  = tWTR;
+
+    initial begin
+        $timeformat (-9, 1, " ns", 1);
+`ifdef period
+        tck <= `period; 
+`else
+        tck <= tCK;
+`endif
+        ck_tb <= 1'b1;
+        dq_en  <= 1'b0;
+        dqs_en <= 1'b0;
+    end
+
+    // component instantiation
+    mobile_ddr mobile_ddr (
+        .Clk                ( ck    ) ,           
+        .Clk_n              ( ck_n  ) ,           
+        .Cke                ( cke   ) ,           
+        .Cs_n               ( cs_n  ) ,           
+        .Ras_n              ( ras_n ) ,           
+        .Cas_n              ( cas_n ) ,           
+        .We_n               ( we_n  ) ,           
+        .Addr               ( a     ) ,           
+        .Ba                 ( ba    ) ,           
+        .Dq                 ( dq    ) ,           
+        .Dqs                ( dqs   ) ,           
+        .Dm                 ( dm    )  
+    );
+
+    // clock generator
+    assign ck = ck_enable & ck_tb ;
+    always @(posedge ck_tb) begin
+      ck_tb <= #(tck/2) 1'b0;
+      ck_tb <= #(tck) 1'b1;
+    end
+
+    function integer ceil;
+        input number;
+        real number;
+        if (number > $rtoi(number))
+            ceil = $rtoi(number) + 1;
+        else
+            ceil = number;
+    endfunction
+
+    function integer max;
+        input arg1;
+        input arg2;
+        integer arg1;
+        integer arg2;
+        if (arg1 > arg2)
+            max = arg1;
+        else
+            max = arg2;
+    endfunction
+
+    function [8*DQ_BITS-1:0] burst_order;
+        input [8-1:0] col;
+        input [8*DQ_BITS-1:0] dq; 
+        reg [3:0] i;
+        reg [2:0] j;
+        integer k;
+        begin
+            burst_order = dq;
+            for (i=0; i<bl; i=i+1) begin
+                j = ((col%bl) ^ i);
+                if (!bo)
+                    j[1:0] = (col + i);
+                for (k=0; k<DQ_BITS; k=k+1) begin
+                    burst_order[i*DQ_BITS + k] = dq[j*DQ_BITS + k];
+                end
+            end
+        end
+    endfunction
+
+    task power_up;
+        begin
+            cke   <= 1'b0;
+            cs_n  <= 1'b1;
+            ras_n <= 1'b1;
+            cas_n <= 1'b1;
+            we_n  <= 1'b1;
+            ba    <= {BA_BITS{1'b0}};
+            a     <= {ADDR_BITS{1'b0}}; 
+            repeat(10) @(negedge ck_tb);
+            @ (negedge ck_tb) cke <= 1'b1;
+            $display ("%m at time %t TB:  A 200 us delay is required after cke is brought high.", $time);
+        end
+    endtask
+
+    task stop_clock_enter ;
+    begin
+        @ (negedge ck_tb);
+        ck_enable = 1'b0 ;
+    end
+    endtask
+
+    task stop_clock_exit ;
+    begin
+        @ (negedge ck_tb);
+        ck_enable = 1'b1 ;
+    end
+    endtask
+
+    task load_mode;
+        input   [BA_BITS-1:0] bank;
+        input  [ROW_BITS-1:0] row;
+        begin
+            case (bank)
+                0: mode_reg0 = row;
+                1: mode_reg1 = row;
+            endcase
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b0;
+            cas_n <= 1'b0;
+            we_n  <= 1'b0;
+            ba    <= bank;
+            a     <= row;
+            @(negedge ck_tb);
+        end
+    endtask
+
+    task refresh;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b0;
+            cas_n <= 1'b0;
+            we_n  <= 1'b1;
+            @(negedge ck_tb);
+        end
+    endtask
+     
+    task precharge;
+        input [BA_BITS-1:0] bank;
+        input               ap; //precharge all
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b0;
+            cas_n <= 1'b1;
+            we_n  <= 1'b0;
+            ba    <= bank;
+            a     <= (ap<<10);
+            @(negedge ck_tb);
+        end
+    endtask
+     
+    task activate;
+        input   [BA_BITS-1:0] bank;
+        input  [ROW_BITS-1:0] row;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b0;
+            cas_n <= 1'b1;
+            we_n  <= 1'b1;
+            ba    <= bank;
+            a     <= row;
+            @(negedge ck_tb);
+        end
+    endtask
+
+    //write task supports burst lengths <= 8
+    task write;
+        input   [BA_BITS-1:0] bank;
+        input  [COL_BITS-1:0] col;
+        input                 ap; //Auto Precharge
+        input [16*DM_BITS-1:0] dm;
+        input [16*DQ_BITS-1:0] dq;
+        reg   [ADDR_BITS-1:0] atemp [1:0];
+        integer i;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b1;
+            cas_n <= 1'b0;
+            we_n  <= 1'b0;
+            ba    <= bank;
+            atemp[0] = col & 10'h3ff;   //addr[ 9: 0] = COL[ 9: 0]
+            atemp[1] = (col>>10)<<11;   //addr[ N:11] = COL[ N:10]
+            a     <= atemp[0] | atemp[1] | (ap<<10);
+            for (i=0; i<=bl; i=i+1) begin
+                dqs_en <= #(wl*tck + i*tck/2) 1'b1;
+                if (i%2 == 0) begin
+                    dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b0}};
+                end else begin
+                    dqs_out <= #(wl*tck + i*tck/2) {DQS_BITS{1'b1}};
+                end
+
+                dq_en  <= #(wl*tck + i*tck/2 + tck/4) 1'b1;
+                dm_out <= #(wl*tck + i*tck/2 + tck/4) dm>>i*DM_BITS;
+                dq_out <= #(wl*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS;
+            end
+            dqs_en <= #(wl*tck + bl*tck/2 + tck/2) 1'b0;
+            dq_en  <= #(wl*tck + bl*tck/2 + tck/4) 1'b0;
+            @(negedge ck_tb);  
+        end
+    endtask
+
+    // read without data verification
+    task read;
+        input    [BA_BITS-1:0] bank;
+        input   [COL_BITS-1:0] col;
+        input                  ap; //Auto Precharge
+        reg    [ADDR_BITS-1:0] atemp [1:0];
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b1;
+            cas_n <= 1'b0;
+            we_n  <= 1'b1;
+            ba    <= bank;
+            atemp[0] = col & 10'h3ff;   //addr[ 9: 0] = COL[ 9: 0]
+            atemp[1] = (col>>10)<<11;   //addr[ N:11] = COL[ N:10]
+            a     <= atemp[0] | atemp[1] | (ap<<10);
+            @(negedge ck_tb);
+        end
+    endtask
+
+    task burst_term;
+        integer i;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b1;
+            cas_n <= 1'b1;
+            we_n  <= 1'b0;
+            @(negedge ck_tb);
+            for (i=0; i<bl; i=i+1) begin
+                dm_fifo[2*cl + i] <= {DM_BITS{1'bx}};
+                dq_fifo[2*cl + i] <= {DQ_BITS{1'bx}};
+            end
+        end
+    endtask
+
+    task nop;
+        input [31:0] count;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b1;
+            cas_n <= 1'b1;
+            we_n  <= 1'b1;
+            repeat(count) @(negedge ck_tb);
+        end
+    endtask
+
+    task deselect;
+        input [31:0] count;
+        begin
+            cke   <= 1'b1;
+            cs_n  <= 1'b1;
+//            ras_n <= 1'b1;
+//            cas_n <= 1'b1;
+//            we_n  <= 1'b1;
+            repeat(count) @(negedge ck_tb);
+        end
+    endtask
+
+    task power_down;
+        input [31:0] count;
+        begin
+            cke   <= 1'b0;
+            cs_n  <= 1'b1;
+            ras_n <= 1'b1;
+            cas_n <= 1'b1;
+            we_n  <= 1'b1;
+            repeat(count) @(negedge ck_tb);
+        end
+    endtask
+
+    task deep_power_down;
+        input [31:0] count;
+        begin
+            cke   <= 1'b0;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b1;
+            cas_n <= 1'b1;
+            we_n  <= 1'b0;
+            repeat(count) @(negedge ck_tb);
+        end
+    endtask
+
+    task self_refresh;
+        input [31:0] count;
+        begin
+            cke   <= 1'b0;
+            cs_n  <= 1'b0;
+            ras_n <= 1'b0;
+            cas_n <= 1'b0;
+            we_n  <= 1'b1;
+            repeat(count) @(negedge ck_tb);
+        end
+    endtask
+
+    // read with data verification
+    task read_verify;
+        input   [BA_BITS-1:0] bank;
+        input  [COL_BITS-1:0] col;
+        input                 ap; //Auto Precharge
+        input [16*DM_BITS-1:0] dm; //Expected Data Mask
+        input [16*DQ_BITS-1:0] dq; //Expected Data
+        integer i;
+        begin
+            read (bank, col, ap);
+            for (i=0; i<bl; i=i+1) begin
+                dm_fifo[2*cl + i] <= dm>>(i*DM_BITS);
+                dq_fifo[2*cl + i] <= dq>>(i*DQ_BITS);
+            end
+        end
+    endtask
+
+    // receiver(s) for data_verify process
+    dqrx dqrx[DQS_BITS-1:0] (ptr_rst_n, dqs, dq, q0, q1, q2, q3);
+
+    // perform data verification as a result of read_verify task call
+    reg [DQ_BITS-1:0] bit_mask;
+    reg [DM_BITS-1:0] dm_temp;
+    reg [DQ_BITS-1:0] dq_temp;
+    always @(ck) begin:data_verify
+        integer i;
+        integer j;
+        
+        for (i=!ck; (i<2/(2.0 - !ck)); i=i+1) begin
+            if (dm_fifo[i] === {DM_BITS{1'bx}}) begin
+                burst_cntr = 0;
+            end else begin
+
+                dm_temp = dm_fifo[i];
+                for (j=0; j<DQ_BITS; j=j+1) begin
+                    bit_mask[j] = !dm_temp[j/(DQ_BITS/DM_BITS)];
+                end
+
+                case (burst_cntr)
+                    0: dq_temp =  q0;
+                    1: dq_temp =  q1;
+                    2: dq_temp =  q2;
+                    3: dq_temp =  q3;
+                endcase
+                //if ( ((dq_temp & bit_mask) === (dq_fifo[i] & bit_mask)))
+                //    $display ("%m at time %t: INFO: Successful read data compare.  Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
+                if ((dq_temp & bit_mask) !== (dq_fifo[i] & bit_mask))
+                    $display ("%m at time %t: ERROR: Read data miscompare.  Expected = %h, Actual = %h, Mask = %h, i = %d", $time, dq_fifo[i], dq_temp, bit_mask, burst_cntr);
+
+                burst_cntr = burst_cntr + 1;
+            end
+        end
+
+        if (ck_tb) begin
+            ptr_rst_n <= (dm_fifo[4] !== {DM_BITS{1'bx}});
+        end else begin
+            //ptr_rst_n <= ptr_rst_n & (dm_fifo[6] !== {DM_BITS{1'bx}});
+            for (i=0; i<=2*CL_MAX+16; i=i+1) begin
+                dm_fifo[i] = dm_fifo[i+2];
+                dq_fifo[i] = dq_fifo[i+2];
+            end
+        end
+    end
+
+    // End-of-test triggered in 'subtest.vh'
+    task test_done;
+        begin
+            $display ("%m at time %t: INFO: Simulation is Complete", $time);
+            $stop(0);
+        end
+    endtask
+
+    // Test included from external file
+    `include "subtest.vh"
+
+endmodule
+
+module dqrx (
+    ptr_rst_n, dqs, dq, q0, q1, q2, q3
+);
+
+`ifdef den128Mb
+    `include "128Mb_mobile_ddr_parameters.vh"
+`elsif den256Mb
+    `include "256Mb_mobile_ddr_parameters.vh"
+`elsif den512Mb
+    `include "512Mb_mobile_ddr_parameters.vh"
+`elsif den1024Mb
+    `include "1024Mb_mobile_ddr_parameters.vh"
+`elsif den2048Mb
+    `include "2048Mb_mobile_ddr_parameters.vh"
+`else
+    // NOTE: Intentionally cause a compile fail here to force the users
+    //       to select the correct component density before continuing
+    ERROR: You must specify component density with +define+den____Mb.
+`endif
+
+    input  ptr_rst_n;
+    input  dqs;
+    input  [DQ_BITS/DQS_BITS-1:0] dq;
+    output [DQ_BITS/DQS_BITS-1:0] q0;
+    output [DQ_BITS/DQS_BITS-1:0] q1;
+    output [DQ_BITS/DQS_BITS-1:0] q2;
+    output [DQ_BITS/DQS_BITS-1:0] q3;
+
+    reg [1:0] ptr;
+    reg [DQ_BITS/DQS_BITS-1:0] q [3:0];
+
+    reg ptr_rst_dly_n;
+    always @(posedge ptr_rst_n) ptr_rst_dly_n <= #(tAC2_min + tDQSQ) ptr_rst_n;
+    always @(negedge ptr_rst_n) ptr_rst_dly_n <= #(tAC2_max + tDQSQ + 0.002) ptr_rst_n;
+
+    reg dqs_dly;
+    always @(dqs) dqs_dly <= #(tDQSQ + 0.001) dqs;
+
+    always @(negedge ptr_rst_dly_n or posedge dqs_dly or negedge dqs_dly) begin
+        if (!ptr_rst_dly_n) begin
+            ptr <= 0;
+        end else if (dqs_dly || ptr) begin
+            q[ptr] <= dq;
+            ptr <= ptr + 1;
+        end
+    end
+
+    assign q0  = q[0];
+    assign q1  = q[1];
+    assign q2  = q[2];
+    assign q3  = q[3];
+endmodule