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sim/verilog/micron_2048Mb_ddr2/ddr2_mcp.v

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+/****************************************************************************************
+*
+*    File Name:  ddr2_mcp.v
+*
+* Dependencies:  ddr2.v, ddr2_parameters.vh
+*
+*  Description:  Micron SDRAM DDR2 (Double Data Rate 2) multi-chip package model
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+ `timescale 1ps / 1ps
+
+module ddr2_mcp (
+    ck,
+    ck_n,
+    cke,
+    cs_n,
+    ras_n,
+    cas_n,
+    we_n,
+    dm_rdqs,
+    ba,
+    addr,
+    dq,
+    dqs,
+    dqs_n,
+    rdqs_n,
+    odt
+);
+
+    `include "ddr2_parameters.vh"
+
+    // Declare Ports
+    input   ck;
+    input   ck_n;
+    input   [CS_BITS-1:0]   cke;
+    input   [CS_BITS-1:0]   cs_n;
+    input   ras_n;
+    input   cas_n;
+    input   we_n;
+    inout   [DM_BITS-1:0]   dm_rdqs;
+    input   [BA_BITS-1:0]   ba;
+    input   [ADDR_BITS-1:0] addr;
+    inout   [DQ_BITS-1:0]   dq;
+    inout   [DQS_BITS-1:0]  dqs;
+    inout   [DQS_BITS-1:0]  dqs_n;
+    output  [DQS_BITS-1:0]  rdqs_n;
+    input   [CS_BITS-1:0]   odt;
+
+    wire [RANKS-1:0] cke_mcp = cke;
+    wire [RANKS-1:0] cs_n_mcp = cs_n;
+    wire [RANKS-1:0] odt_mcp = odt;
+
+    ddr2 rank [RANKS-1:0] (
+        ck, 
+        ck_n,
+        cke_mcp, 
+        cs_n_mcp,
+        ras_n, 
+        cas_n, 
+        we_n, 
+        dm_rdqs, 
+        ba, 
+        addr, 
+        dq, 
+        dqs,
+        dqs_n,
+        rdqs_n,
+        odt_mcp
+    );
+
+endmodule