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Wolfgang Spraul
225
sim/verilog/micron_2048Mb_ddr2/subtest.vh
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sim/verilog/micron_2048Mb_ddr2/subtest.vh
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/****************************************************************************************
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*
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* File Name: subtest.vh
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*
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* Description: Micron SDRAM DDR2 (Double Data Rate 2)
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* This file is included by tb.v
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*
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* Disclaimer This software code and all associated documentation, comments or other
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* of Warranty: information (collectively "Software") is provided "AS IS" without
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* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
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* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGES. Because some jurisdictions prohibit the exclusion or
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* limitation of liability for consequential or incidental damages, the
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* above limitation may not apply to you.
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*
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* Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
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initial begin : test
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cke <= 1'b0;
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cs_n <= 1'b1;
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ras_n <= 1'b1;
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cas_n <= 1'b1;
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we_n <= 1'b1;
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ba <= {BA_BITS{1'bz}};
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a <= {ADDR_BITS{1'bz}};
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odt <= 1'b0;
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dq_en <= 1'b0;
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dqs_en <= 1'b0;
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cke <= 1'b1;
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// POWERUP SECTION
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power_up;
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// INITIALIZE SECTION
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precharge (0, 1); // Precharge all banks
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nop (trp);
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load_mode (2, 0); // Extended Mode Register (2)
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nop (tmrd-1);
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load_mode (3, 0); // Extended Mode Register (3)
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nop (tmrd-1);
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load_mode (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with DLL Enable
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nop (tmrd-1);
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load_mode (0, 13'b0_000_1_0_000_0_011 | (twr-1)<<9 | taa<<4); // Mode Register without DLL Reset (bl=8)
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nop (tmrd-1);
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precharge (0, 1); // Precharge all banks
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nop (trp);
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refresh;
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nop (trfc-1);
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refresh;
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nop (trfc-1);
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load_mode (0, 13'b0_000_0_0_000_0_011 | (twr-1)<<9 | taa<<4); // Mode Register without DLL Reset (bl=8)
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nop (tmrd-1);
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load_mode (1, 13'b0_0_0_111_0_000_1_0_0); // Extended Mode Register with OCD Default
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nop (tmrd-1);
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load_mode (1, 13'b0_0_0_000_0_000_1_0_0); // Extended Mode Register with OCD Exit
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nop (tmrd-1);
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// DLL RESET ENABLE - you will need 200 TCK before any read command.
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nop (200);
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// WRITE SECTION
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activate (0, 0); // Activate Bank 0, Row 0
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nop (trcd-1);
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write (0, 4, 0, 0, 'h3210); // Write Bank 0, Col 0
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nop (tccd-1);
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write (0, 0, 1, 0, 'h0123); // Write Bank 0, Col 0
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activate (1, 0); // Activate Bank 1, Row 0
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nop (trcd-1);
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write (1, 0, 1, 0, 'h4567); // Write Bank 1, Col 0
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activate (2, 0); // Activate Bank 2, Row 0
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nop (trcd-1);
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write (2, 0, 1, 0, 'h89AB); // Write Bank 2, Col 0
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activate (3, 0); // Activate Bank 3, Row 0
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nop (trcd-1);
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write (3, 0, 1, 0, 'hCDEF); // Write Bank 3, Col 0
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nop (cl - 1 + bl/2 + twtr-1);
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nop (tras);
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// READ SECTION
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activate (0, 0); // Activate Bank 0, Row 0
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nop (trrd-1);
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activate (1, 0); // Activate Bank 1, Row 0
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nop (trrd-1);
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activate (2, 0); // Activate Bank 2, Row 0
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nop (trrd-1);
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activate (3, 0); // Activate Bank 3, Row 0
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read (0, 0, 1); // Read Bank 0, Col 0
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nop (bl/2);
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read (1, 1, 1); // Read Bank 1, Col 1
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nop (bl/2);
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read (2, 2, 1); // Read Bank 2, Col 2
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nop (bl/2);
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read (3, 3, 1); // Read Bank 3, Col 3
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nop (rl + bl/2);
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activate (0, 0); // Activate Bank 0, Row 0
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nop (trrd-1);
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activate (1, 0); // Activate Bank 1, Row 0
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nop (trcd-1);
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$display ("%m at time %t: Figure 22: Consecutive READ Bursts", $time);
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read (0, 0, 0); // Read Bank 0, Col 0
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nop (bl/2-1);
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read (0, 4, 0); // Read Bank 0, Col 4
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nop (rl + bl/2);
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$display ("%m at time %t: Figure 23: Nonconsecutive READ Bursts", $time);
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read (0, 0, 0); // Read Bank 0, Col 0
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nop (bl/2);
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read (0, 4, 0); // Read Bank 0, Col 4
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nop (rl + bl/2);
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$display ("%m at time %t: Figure 24: READ Interrupted by READ", $time);
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read (0, 0, 0); // Read Bank 0, Col 0
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nop (tccd-1);
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read (1, 0, 0); // Read Bank 0, Col 0
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nop (rl + bl/2);
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$display ("%m at time %t: Figure 25 & 26: READ to PRECHARGE", $time);
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read (0, 0, 0); // Read Bank 0, Col 0
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nop (al + bl/2 + trtp - 2);
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precharge (0, 0); // Precharge Bank 0
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nop (trp-1);
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activate (0, 0); // Activate Bank 0, Row 0
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nop (trcd-1);
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$display ("%m at time %t: Figure 27: READ to WRITE", $time);
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read (0, 0, 0); // Read Bank 0, Col 0
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nop (rl + bl/2 - wl);
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write (0, 0, 1, 0, 'h0123); // Write Bank 0, Col 0
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nop (wl + bl/2 + twr + trp-1);
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activate (0, 0); // Activate Bank 0, Row 0
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nop (trcd-1);
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$display ("%m at time %t: Figure 36: Nonconsecutive WRITE to WRITE", $time);
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write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0
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nop (bl/2);
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write (0, 4, 0, 0, 'h0123); // Write Bank 0, Col 0
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nop (wl + bl/2);
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$display ("%m at time %t: Figure 37: Random WRITE Cycles", $time);
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write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0
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nop (bl/2-1);
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write (0, 4, 0, 0, 'h0123); // Write Bank 0, Col 0
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nop (wl + bl/2);
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$display ("%m at time %t: Figure 37: Figure 38: WRITE Interrupted by WRITE", $time);
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write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0
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nop (tccd-1);
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write (1, 4, 0, 0, 'h0123); // Write Bank 0, Col 0
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nop (wl + bl/2);
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$display ("%m at time %t: Figure 39: WRITE to READ", $time);
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write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0
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nop (wl + bl/2 + twtr-1);
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read_verify (0, 0, 0, 0, 'h0123); // Read Bank 0, Col 0
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nop (rl + bl/2);
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$display ("%m at time %t: Figure 40: WRITE to PRECHARGE", $time);
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write (0, 0, 0, 0, 'h0123); // Write Bank 0, Col 0
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nop (wl + bl/2 + twr-1);
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precharge (0, 1); // Precharge all banks
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nop (trp-1);
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// odt Section
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$display ("%m at time %t: Figure 60: odt Timing for Active or Fast-Exit Power-Down Mode", $time);
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odt = 1'b1;
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nop (1);
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odt = 1'b0;
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nop (tanpd);
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$display ("%m at time %t: Figure 61: odt timing for Slow-Exit or Precharge Power-Down Modes", $time);
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cke = 1'b0;
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@(negedge ck);
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odt = 1'b1;
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@(negedge ck);
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odt = 1'b0;
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repeat(tanpd)@(negedge ck);
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nop (taxpd);
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$display ("%m at time %t: Figure 62 & 63: odt Transition Timings when Entering Power-Down Mode", $time);
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odt = 1'b1;
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nop (tanpd);
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power_down (tcke);
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// Self Refresh Section
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nop (taxpd);
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odt = 1'b0;
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nop (3); // taofd
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self_refresh (tcke);
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nop (tdllk);
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nop (tcke);
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test_done;
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end
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