From 30b1282bbc6107ab036471cab2e283d74b7986e7 Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Sat, 21 Aug 2010 16:38:23 -0500 Subject: [PATCH] s6 to eth-phy connections has been completed --- kicad/xue-rnc/DRAM.sch | 2 +- kicad/xue-rnc/FPGA.sch | 60 +- kicad/xue-rnc/NV_MEMORIES.sch | 2 +- kicad/xue-rnc/PSU.sch | 2 +- kicad/xue-rnc/USB.sch | 2 +- kicad/xue-rnc/eth_phy.sch | 2 +- kicad/xue-rnc/xue-rnc-cache.lib | 2 +- kicad/xue-rnc/xue-rnc.brd | 3802 ++++++++++++++++--------------- kicad/xue-rnc/xue-rnc.net | 1078 ++++----- kicad/xue-rnc/xue-rnc.sch | 2 +- 10 files changed, 2543 insertions(+), 2411 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index f657bbd..ee794b0 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 04:24:17 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index d7300f7..c1b0bea 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 04:24:17 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -59,6 +59,8 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Wire Line + 14000 8650 14250 8650 Wire Wire Line 14000 7850 14250 7850 Wire Wire Line @@ -329,7 +331,7 @@ Wire Wire Line Wire Wire Line 14650 1150 15100 1150 Wire Wire Line - 16400 12650 16400 12400 + 16400 12400 16400 12650 Wire Wire Line 1650 7800 2250 7800 Wire Wire Line @@ -357,13 +359,13 @@ Wire Wire Line 6000 12900 4600 12900 Connection ~ 4600 12900 Wire Wire Line - 4600 12950 4600 12850 + 4600 12850 4600 12950 Connection ~ 5300 12900 Wire Wire Line - 5300 12850 5300 12900 + 5300 12900 5300 12850 Connection ~ 4600 12400 Wire Wire Line - 4600 12350 4600 12450 + 4600 12450 4600 12350 Connection ~ 5300 12400 Wire Wire Line 5300 12400 5300 12450 @@ -390,13 +392,13 @@ Wire Wire Line 6000 13900 6000 13850 Connection ~ 4600 13900 Wire Wire Line - 4600 13950 4600 13850 + 4600 13850 4600 13950 Connection ~ 5300 13900 Wire Wire Line 5300 13900 5300 13850 Connection ~ 4600 13400 Wire Wire Line - 4600 13350 4600 13450 + 4600 13450 4600 13350 Connection ~ 5300 13400 Wire Wire Line 5300 13400 5300 13450 @@ -420,13 +422,13 @@ Wire Wire Line 6000 14850 4600 14850 Connection ~ 4600 14850 Wire Wire Line - 4600 14900 4600 14800 + 4600 14800 4600 14900 Connection ~ 5300 14850 Wire Wire Line 5300 14850 5300 14800 Connection ~ 4600 14350 Wire Wire Line - 4600 14300 4600 14400 + 4600 14400 4600 14300 Connection ~ 5300 14350 Wire Wire Line 5300 14350 5300 14400 @@ -442,13 +444,13 @@ Wire Wire Line Connection ~ 4950 14850 Connection ~ 1650 14850 Wire Wire Line - 1650 14900 1650 14800 + 1650 14800 1650 14900 Connection ~ 2350 14850 Wire Wire Line 2350 14850 2350 14800 Connection ~ 1650 14350 Wire Wire Line - 1650 14300 1650 14400 + 1650 14400 1650 14300 Connection ~ 2350 14350 Wire Wire Line 2350 14350 2350 14400 @@ -486,22 +488,22 @@ Connection ~ 2000 13450 Wire Wire Line 2350 13450 2350 13500 Wire Wire Line - 1650 14000 1650 13900 + 1650 13900 1650 14000 Wire Wire Line - 1650 13400 1650 13500 + 1650 13500 1650 13400 Wire Wire Line 2000 13500 2000 13450 Wire Wire Line 2000 13950 2000 13900 Connection ~ 1650 12900 Wire Wire Line - 1650 12950 1650 12850 + 1650 12850 1650 12950 Connection ~ 2350 12900 Wire Wire Line 2350 12900 2350 12850 Connection ~ 1650 12400 Wire Wire Line - 1650 12350 1650 12450 + 1650 12450 1650 12350 Connection ~ 2350 12400 Wire Wire Line 2350 12400 2350 12450 @@ -523,13 +525,11 @@ Wire Wire Line 18250 8150 17650 8150 Wire Wire Line 17650 8350 18250 8350 -Wire Wire Line - 14250 8650 14200 8650 Connection ~ 15900 6200 Wire Wire Line 15900 6200 15900 6100 Wire Wire Line - 16500 9850 16500 10000 + 16500 10000 16500 9850 Wire Bus Line 18450 6750 18350 6750 Wire Wire Line @@ -660,7 +660,7 @@ Connection ~ 16250 6200 Wire Wire Line 16250 6200 16250 6250 Wire Wire Line - 19700 800 19700 650 + 19700 650 19700 800 Connection ~ 20000 750 Wire Wire Line 20000 750 20000 800 @@ -686,7 +686,7 @@ Connection ~ 8300 750 Wire Wire Line 8300 750 8300 800 Wire Wire Line - 8100 800 8100 650 + 8100 650 8100 800 Connection ~ 8100 750 Connection ~ 18800 12500 Wire Wire Line @@ -1120,9 +1120,7 @@ Wire Wire Line Wire Bus Line 18350 6750 18350 7050 Wire Wire Line - 15000 9850 15000 10000 -Wire Wire Line - 14250 8550 14200 8550 + 15000 10000 15000 9850 Wire Bus Line 18350 8050 18350 8750 Wire Wire Line @@ -1189,7 +1187,7 @@ Wire Wire Line Wire Wire Line 15900 12500 15900 12400 Wire Wire Line - 5300 6400 5300 6250 + 5300 6250 5300 6400 Wire Wire Line 14650 1250 15100 1250 Wire Wire Line @@ -1485,13 +1483,15 @@ Wire Wire Line Wire Wire Line 14250 8450 13550 8450 Wire Wire Line - 14250 8150 13550 8150 + 13500 8550 14250 8550 +Wire Wire Line + 13950 8150 14250 8150 Text Label 13550 8450 0 60 ~ 0 -ETH_TXD1 -Text Label 13550 8150 0 60 ~ 0 ETH_TXD0 -Text Label 13550 8050 0 60 ~ 0 +Text Label 13550 8550 0 60 ~ 0 ETH_TXD2 +Text Label 13550 8050 0 60 ~ 0 +ETH_TXD1 Text Label 13550 7750 0 60 ~ 0 ETH_TXD3 Text Label 13550 7150 0 60 ~ 0 @@ -2629,9 +2629,9 @@ Text Label 18250 8350 2 60 ~ 0 NF_D2 Text Label 18250 8450 2 60 ~ 0 NF_D3 -Text HLabel 14200 8650 0 60 BiDi ~ 0 +Text HLabel 13950 8150 0 60 BiDi ~ 0 ETH_COL -Text HLabel 14200 8550 0 60 BiDi ~ 0 +Text HLabel 14000 8650 0 60 BiDi ~ 0 ETH_CRS Text HLabel 18000 7750 2 60 Output ~ 0 NF_WE_N diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index cd9d6b5..c922548 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 04:24:17 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index e002c58..e59a077 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 04:24:17 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 340d802..cb15340 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 04:24:17 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 27f3e70..0eaef6c 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 04:24:17 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index c7c7f82..a69ce06 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Sat 21 Aug 2010 07:16:33 AM COT +EESchema-LIBRARY Version 2.3 Date: Sat 21 Aug 2010 04:24:17 PM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 02488c9..d49dab1 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Sat 21 Aug 2010 09:12:30 AM COT +PCBNEW-BOARD Version 1 date Sat 21 Aug 2010 04:37:01 PM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -7,10 +7,10 @@ LayerCount 6 Ly 1FFF801F EnabledLayers 13FF801F Links 675 -NoConn 569 +NoConn 564 Di 45200 13470 70189 50668 Ndraw 7 -Ntrack 911 +Ntrack 977 Nzone 0 BoardThickness 630 Nmodule 161 @@ -90,7 +90,7 @@ Na 5 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A0" +Na 6 "/DDR_Banks/M0_A11" St ~ $EndEQUIPOT $EQUIPOT @@ -98,115 +98,115 @@ Na 7 "/DDR_Banks/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_A5" +Na 8 "/DDR_Banks/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_A6" +Na 9 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_A7" +Na 10 "/DDR_Banks/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_A9" +Na 11 "/DDR_Banks/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_BA0" +Na 12 "/DDR_Banks/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_BA1" +Na 13 "/DDR_Banks/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_CAS#" +Na 14 "/DDR_Banks/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_DQ2" +Na 15 "/DDR_Banks/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_DQ4" +Na 16 "/DDR_Banks/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_DQ5" +Na 17 "/DDR_Banks/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_LDM" +Na 18 "/DDR_Banks/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_LDQS" +Na 19 "/DDR_Banks/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M0_VREF" +Na 20 "/DDR_Banks/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M0_WE#" +Na 21 "/DDR_Banks/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M1_A0" +Na 22 "/DDR_Banks/M0_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_A11" +Na 23 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_A7" +Na 24 "/DDR_Banks/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_A8" +Na 25 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_BA1" +Na 26 "/DDR_Banks/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_CLK" +Na 27 "/DDR_Banks/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_CLK#" +Na 28 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_CS#" +Na 29 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_DQ1" +Na 30 "/DDR_Banks/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_DQ11" +Na 31 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_DQ12" +Na 32 "/DDR_Banks/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_DQ15" +Na 33 "/DDR_Banks/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_DQ4" +Na 34 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_DQ6" +Na 35 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT @@ -214,127 +214,127 @@ Na 36 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/DDR_Banks/M1_UDQS" +Na 37 "/DDR_Banks/M1_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M1_VREF" +Na 38 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/DDR_Banks/M1_WE#" +Na 39 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Ethernet_Phy/ETH_A1.8V" +Na 40 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_A3.3V" +Na 41 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_CLK" +Na 42 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_COL" +Na 43 "/Ethernet_Phy/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_CRS" +Na 44 "/Ethernet_Phy/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_INT" +Na 45 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_LED0" +Na 46 "/Ethernet_Phy/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_LED1" +Na 47 "/Ethernet_Phy/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_PLL1.8V" +Na 48 "/Ethernet_Phy/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_RXC" +Na 49 "/Ethernet_Phy/MAG_RX+" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/ETH_RXD0" +Na 50 "/Ethernet_Phy/MAG_RX-" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Ethernet_Phy/ETH_RXD3" +Na 51 "/Ethernet_Phy/MAG_SHIELD" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/Ethernet_Phy/ETH_RXDV" +Na 52 "/Ethernet_Phy/MAG_TX+" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/Ethernet_Phy/ETH_RXER" +Na 53 "/Ethernet_Phy/MAG_TX-" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/Ethernet_Phy/ETH_TXD0" +Na 54 "/FPGA_Spartan6/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/Ethernet_Phy/ETH_TXD1" +Na 55 "/FPGA_Spartan6/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/Ethernet_Phy/ETH_TXD2" +Na 56 "/FPGA_Spartan6/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/Ethernet_Phy/MAG_RX+" +Na 57 "/FPGA_Spartan6/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/Ethernet_Phy/MAG_RX-" +Na 58 "/FPGA_Spartan6/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/Ethernet_Phy/MAG_SHIELD" +Na 59 "/FPGA_Spartan6/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/Ethernet_Phy/MAG_TX+" +Na 60 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/Ethernet_Phy/MAG_TX-" +Na 61 "/FPGA_Spartan6/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/ETH_MDC" +Na 62 "/FPGA_Spartan6/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/ETH_MDIO" +Na 63 "/FPGA_Spartan6/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/ETH_RESET_N" +Na 64 "/FPGA_Spartan6/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/ETH_RXD1" +Na 65 "/FPGA_Spartan6/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/ETH_RXD2" +Na 66 "/FPGA_Spartan6/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/ETH_TXC" +Na 67 "/FPGA_Spartan6/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT @@ -342,43 +342,43 @@ Na 68 "/FPGA_Spartan6/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/ETH_TXEN" +Na 69 "/FPGA_Spartan6/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/ETH_TXER" +Na 70 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_A1" +Na 71 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_A10" +Na 72 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_A11" +Na 73 "/FPGA_Spartan6/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_A12" +Na 74 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_A3" +Na 75 "/FPGA_Spartan6/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_A4" +Na 76 "/FPGA_Spartan6/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_A8" +Na 77 "/FPGA_Spartan6/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_CKE" +Na 78 "/FPGA_Spartan6/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT @@ -394,139 +394,139 @@ Na 81 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_DQ1" +Na 82 "/FPGA_Spartan6/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_DQ10" +Na 83 "/FPGA_Spartan6/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_DQ11" +Na 84 "/FPGA_Spartan6/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M0_DQ12" +Na 85 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M0_DQ13" +Na 86 "/FPGA_Spartan6/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M0_DQ14" +Na 87 "/FPGA_Spartan6/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M0_DQ15" +Na 88 "/FPGA_Spartan6/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M0_DQ3" +Na 89 "/FPGA_Spartan6/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M0_DQ6" +Na 90 "/FPGA_Spartan6/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M0_DQ7" +Na 91 "/FPGA_Spartan6/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M0_DQ8" +Na 92 "/FPGA_Spartan6/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M0_DQ9" +Na 93 "/FPGA_Spartan6/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M0_RAS#" +Na 94 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M0_UDM" +Na 95 "/FPGA_Spartan6/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M0_UDQS" +Na 96 "/FPGA_Spartan6/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_A1" +Na 97 "/FPGA_Spartan6/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_A10" +Na 98 "/FPGA_Spartan6/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_A12" +Na 99 "/FPGA_Spartan6/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_A2" +Na 100 "/FPGA_Spartan6/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_A3" +Na 101 "/FPGA_Spartan6/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_A4" +Na 102 "/FPGA_Spartan6/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_A5" +Na 103 "/FPGA_Spartan6/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_A6" +Na 104 "/FPGA_Spartan6/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_A9" +Na 105 "/FPGA_Spartan6/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_BA0" +Na 106 "/FPGA_Spartan6/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_CAS#" +Na 107 "/FPGA_Spartan6/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_CKE" +Na 108 "/FPGA_Spartan6/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ0" +Na 109 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_DQ10" +Na 110 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_DQ13" +Na 111 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Spartan6/M1_DQ14" +Na 112 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_DQ2" +Na 113 "/FPGA_Spartan6/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Spartan6/M1_DQ3" +Na 114 "/FPGA_Spartan6/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/M1_DQ5" +Na 115 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT @@ -542,399 +542,399 @@ Na 118 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/M1_LDM" +Na 119 "/FPGA_Spartan6/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Spartan6/M1_LDQS" +Na 120 "/FPGA_Spartan6/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Spartan6/M1_RAS#" +Na 121 "/FPGA_Spartan6/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Spartan6/NF_ALE" +Na 122 "/FPGA_Spartan6/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Spartan6/NF_CLE" +Na 123 "/FPGA_Spartan6/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Spartan6/NF_D2" +Na 124 "/FPGA_Spartan6/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Spartan6/NF_D3" +Na 125 "/FPGA_Spartan6/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Spartan6/NF_D4" +Na 126 "/FPGA_Spartan6/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Spartan6/NF_D7" +Na 127 "/FPGA_Spartan6/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Spartan6/NF_RNB" +Na 128 "/FPGA_Spartan6/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/FPGA_Spartan6/PROG_CCLK" +Na 129 "/FPGA_Spartan6/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/FPGA_Spartan6/PROG_CSO" +Na 130 "/FPGA_Spartan6/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/FPGA_Spartan6/PROG_MISO0" +Na 131 "/FPGA_Spartan6/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/FPGA_Spartan6/PROG_MISO1" +Na 132 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/FPGA_Spartan6/PROG_MISO2" +Na 133 "/FPGA_Spartan6/R_M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/FPGA_Spartan6/PROG_MISO3" +Na 134 "/FPGA_Spartan6/R_M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/FPGA_Spartan6/R_M0_A0" +Na 135 "/FPGA_Spartan6/R_M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/FPGA_Spartan6/R_M0_A1" +Na 136 "/FPGA_Spartan6/R_M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/FPGA_Spartan6/R_M0_A10" +Na 137 "/FPGA_Spartan6/R_M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/FPGA_Spartan6/R_M0_A11" +Na 138 "/FPGA_Spartan6/R_M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/FPGA_Spartan6/R_M0_A12" +Na 139 "/FPGA_Spartan6/R_M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/FPGA_Spartan6/R_M0_A2" +Na 140 "/FPGA_Spartan6/R_M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/FPGA_Spartan6/R_M0_A3" +Na 141 "/FPGA_Spartan6/R_M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/FPGA_Spartan6/R_M0_A4" +Na 142 "/FPGA_Spartan6/R_M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/FPGA_Spartan6/R_M0_A5" +Na 143 "/FPGA_Spartan6/R_M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/FPGA_Spartan6/R_M0_A6" +Na 144 "/FPGA_Spartan6/R_M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/FPGA_Spartan6/R_M0_A7" +Na 145 "/FPGA_Spartan6/R_M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/FPGA_Spartan6/R_M0_A8" +Na 146 "/FPGA_Spartan6/R_M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/FPGA_Spartan6/R_M0_A9" +Na 147 "/FPGA_Spartan6/R_M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/FPGA_Spartan6/R_M0_BA0" +Na 148 "/FPGA_Spartan6/R_M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/FPGA_Spartan6/R_M0_BA1" +Na 149 "/FPGA_Spartan6/R_M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/FPGA_Spartan6/R_M0_CAS#" +Na 150 "/FPGA_Spartan6/R_M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/FPGA_Spartan6/R_M0_CKE" +Na 151 "/FPGA_Spartan6/R_M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/FPGA_Spartan6/R_M0_DQ0" +Na 152 "/FPGA_Spartan6/R_M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/FPGA_Spartan6/R_M0_DQ1" +Na 153 "/FPGA_Spartan6/R_M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/FPGA_Spartan6/R_M0_DQ10" +Na 154 "/FPGA_Spartan6/R_M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/FPGA_Spartan6/R_M0_DQ11" +Na 155 "/FPGA_Spartan6/R_M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/FPGA_Spartan6/R_M0_DQ12" +Na 156 "/FPGA_Spartan6/R_M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/FPGA_Spartan6/R_M0_DQ13" +Na 157 "/FPGA_Spartan6/R_M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/FPGA_Spartan6/R_M0_DQ14" +Na 158 "/FPGA_Spartan6/R_M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/FPGA_Spartan6/R_M0_DQ15" +Na 159 "/FPGA_Spartan6/R_M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/FPGA_Spartan6/R_M0_DQ2" +Na 160 "/FPGA_Spartan6/R_M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/FPGA_Spartan6/R_M0_DQ3" +Na 161 "/FPGA_Spartan6/R_M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/FPGA_Spartan6/R_M0_DQ4" +Na 162 "/FPGA_Spartan6/R_M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/FPGA_Spartan6/R_M0_DQ5" +Na 163 "/FPGA_Spartan6/R_M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/FPGA_Spartan6/R_M0_DQ6" +Na 164 "/FPGA_Spartan6/R_M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/FPGA_Spartan6/R_M0_DQ7" +Na 165 "/FPGA_Spartan6/R_M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/FPGA_Spartan6/R_M0_DQ8" +Na 166 "/FPGA_Spartan6/R_M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/FPGA_Spartan6/R_M0_DQ9" +Na 167 "/FPGA_Spartan6/R_M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/FPGA_Spartan6/R_M0_LDM" +Na 168 "/FPGA_Spartan6/R_M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/FPGA_Spartan6/R_M0_LDQS" +Na 169 "/FPGA_Spartan6/R_M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/FPGA_Spartan6/R_M0_RAS#" +Na 170 "/FPGA_Spartan6/R_M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/FPGA_Spartan6/R_M0_UDM" +Na 171 "/FPGA_Spartan6/R_M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/FPGA_Spartan6/R_M0_UDQS" +Na 172 "/FPGA_Spartan6/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/FPGA_Spartan6/R_M0_WE#" +Na 173 "/FPGA_Spartan6/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/FPGA_Spartan6/R_M1_A0" +Na 174 "/FPGA_Spartan6/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/FPGA_Spartan6/R_M1_A1" +Na 175 "/FPGA_Spartan6/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/FPGA_Spartan6/R_M1_A10" +Na 176 "/FPGA_Spartan6/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/FPGA_Spartan6/R_M1_A11" +Na 177 "/FPGA_Spartan6/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/FPGA_Spartan6/R_M1_A12" +Na 178 "/FPGA_Spartan6/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/FPGA_Spartan6/R_M1_A2" +Na 179 "/FPGA_Spartan6/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 180 "/FPGA_Spartan6/R_M1_A3" +Na 180 "/FPGA_Spartan6/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/FPGA_Spartan6/R_M1_A5" +Na 181 "/FPGA_Spartan6/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/FPGA_Spartan6/R_M1_A6" +Na 182 "/FPGA_Spartan6/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/FPGA_Spartan6/R_M1_A7" +Na 183 "/FPGA_Spartan6/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/FPGA_Spartan6/R_M1_A8" +Na 184 "/FPGA_Spartan6/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "/FPGA_Spartan6/R_M1_A9" +Na 185 "/FPGA_Spartan6/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "/FPGA_Spartan6/R_M1_BA0" +Na 186 "/FPGA_Spartan6/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "/FPGA_Spartan6/R_M1_BA1" +Na 187 "/FPGA_Spartan6/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "/FPGA_Spartan6/R_M1_CAS#" +Na 188 "/FPGA_Spartan6/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "/FPGA_Spartan6/R_M1_CKE" +Na 189 "/FPGA_Spartan6/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "/FPGA_Spartan6/R_M1_CS#" +Na 190 "/FPGA_Spartan6/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "/FPGA_Spartan6/R_M1_DQ0" +Na 191 "/FPGA_Spartan6/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "/FPGA_Spartan6/R_M1_DQ1" +Na 192 "/FPGA_Spartan6/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "/FPGA_Spartan6/R_M1_DQ10" +Na 193 "/FPGA_Spartan6/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "/FPGA_Spartan6/R_M1_DQ11" +Na 194 "/FPGA_Spartan6/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "/FPGA_Spartan6/R_M1_DQ12" +Na 195 "/FPGA_Spartan6/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "/FPGA_Spartan6/R_M1_DQ13" +Na 196 "/FPGA_Spartan6/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "/FPGA_Spartan6/R_M1_DQ14" +Na 197 "/FPGA_Spartan6/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "/FPGA_Spartan6/R_M1_DQ15" +Na 198 "/FPGA_Spartan6/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "/FPGA_Spartan6/R_M1_DQ2" +Na 199 "/FPGA_Spartan6/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "/FPGA_Spartan6/R_M1_DQ3" +Na 200 "/FPGA_Spartan6/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 201 "/FPGA_Spartan6/R_M1_DQ4" +Na 201 "/FPGA_Spartan6/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 202 "/FPGA_Spartan6/R_M1_DQ5" +Na 202 "/FPGA_Spartan6/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 203 "/FPGA_Spartan6/R_M1_DQ6" +Na 203 "/FPGA_Spartan6/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 204 "/FPGA_Spartan6/R_M1_DQ7" +Na 204 "/FPGA_Spartan6/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 205 "/FPGA_Spartan6/R_M1_DQ8" +Na 205 "/FPGA_Spartan6/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 206 "/FPGA_Spartan6/R_M1_DQ9" +Na 206 "/FPGA_Spartan6/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 207 "/FPGA_Spartan6/R_M1_LDM" +Na 207 "/FPGA_Spartan6/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 208 "/FPGA_Spartan6/R_M1_LDQS" +Na 208 "/FPGA_Spartan6/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 209 "/FPGA_Spartan6/R_M1_RAS#" +Na 209 "/FPGA_Spartan6/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 210 "/FPGA_Spartan6/R_M1_UDM" +Na 210 "/FPGA_Spartan6/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 211 "/FPGA_Spartan6/R_M1_UDQS" +Na 211 "/FPGA_Spartan6/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 212 "/FPGA_Spartan6/R_M1_WE#" +Na 212 "/FPGA_Spartan6/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 213 "/FPGA_Spartan6/SD_CMD" +Na 213 "/FPGA_Spartan6/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 214 "/FPGA_Spartan6/SD_DAT0" +Na 214 "/FPGA_Spartan6/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 215 "/FPGA_Spartan6/SD_DAT3" +Na 215 "/FPGA_Spartan6/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 216 "/FPGA_Spartan6/USBA_OE_N" +Na 216 "/Non_volatile_memories/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 217 "/FPGA_Spartan6/USBA_VM" +Na 217 "/Non_volatile_memories/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT @@ -946,19 +946,19 @@ Na 219 "/Non_volatile_memories/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 220 "/Non_volatile_memories/NF_D1" +Na 220 "/Non_volatile_memories/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 221 "/Non_volatile_memories/NF_D5" +Na 221 "/Non_volatile_memories/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 222 "/Non_volatile_memories/NF_D6" +Na 222 "/Non_volatile_memories/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 223 "/Non_volatile_memories/NF_RE_N" +Na 223 "/Non_volatile_memories/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT @@ -966,23 +966,23 @@ Na 224 "/Non_volatile_memories/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 225 "/Non_volatile_memories/SD_CLK" +Na 225 "/Non_volatile_memories/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 226 "/Non_volatile_memories/SD_DAT1" +Na 226 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 227 "/Non_volatile_memories/SD_DAT2" +Na 227 "/Non_volatile_memories/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 228 "/USB/USBA_RCV" +Na 228 "/USB/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 229 "/USB/USBA_SPD" +Na 229 "/USB/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT @@ -1083,130 +1083,137 @@ ViaDrill 79 uViaDia 197 uViaDrill 79 AddNet "" -AddNet "/DDR_Banks/M0_A0" +AddNet "/DDR_Banks/M0_A11" AddNet "/DDR_Banks/M0_A2" -AddNet "/DDR_Banks/M0_A5" AddNet "/DDR_Banks/M0_A6" -AddNet "/DDR_Banks/M0_A7" +AddNet "/DDR_Banks/M0_A8" AddNet "/DDR_Banks/M0_A9" -AddNet "/DDR_Banks/M0_BA0" AddNet "/DDR_Banks/M0_BA1" -AddNet "/DDR_Banks/M0_CAS#" -AddNet "/DDR_Banks/M0_DQ2" -AddNet "/DDR_Banks/M0_DQ4" -AddNet "/DDR_Banks/M0_DQ5" -AddNet "/DDR_Banks/M0_LDM" -AddNet "/DDR_Banks/M0_LDQS" -AddNet "/DDR_Banks/M0_WE#" +AddNet "/DDR_Banks/M0_CKE" +AddNet "/DDR_Banks/M0_DQ1" +AddNet "/DDR_Banks/M0_DQ11" +AddNet "/DDR_Banks/M0_DQ12" +AddNet "/DDR_Banks/M0_DQ6" +AddNet "/DDR_Banks/M0_DQ7" +AddNet "/DDR_Banks/M0_DQ8" +AddNet "/DDR_Banks/M0_DQ9" +AddNet "/DDR_Banks/M0_RAS#" +AddNet "/DDR_Banks/M0_UDQS" AddNet "/DDR_Banks/M1_A0" AddNet "/DDR_Banks/M1_A11" -AddNet "/DDR_Banks/M1_A7" +AddNet "/DDR_Banks/M1_A12" +AddNet "/DDR_Banks/M1_A2" +AddNet "/DDR_Banks/M1_A3" +AddNet "/DDR_Banks/M1_A5" AddNet "/DDR_Banks/M1_A8" -AddNet "/DDR_Banks/M1_BA1" -AddNet "/DDR_Banks/M1_CS#" -AddNet "/DDR_Banks/M1_DQ1" +AddNet "/DDR_Banks/M1_CAS#" +AddNet "/DDR_Banks/M1_DQ10" AddNet "/DDR_Banks/M1_DQ11" -AddNet "/DDR_Banks/M1_DQ12" -AddNet "/DDR_Banks/M1_DQ15" AddNet "/DDR_Banks/M1_DQ4" -AddNet "/DDR_Banks/M1_DQ6" +AddNet "/DDR_Banks/M1_LDM" +AddNet "/DDR_Banks/M1_LDQS" AddNet "/DDR_Banks/M1_UDM" -AddNet "/DDR_Banks/M1_UDQS" -AddNet "/Ethernet_Phy/ETH_CLK" -AddNet "/Ethernet_Phy/ETH_COL" -AddNet "/Ethernet_Phy/ETH_CRS" -AddNet "/Ethernet_Phy/ETH_INT" AddNet "/Ethernet_Phy/ETH_RXC" AddNet "/Ethernet_Phy/ETH_RXD0" -AddNet "/Ethernet_Phy/ETH_RXD3" -AddNet "/Ethernet_Phy/ETH_RXDV" +AddNet "/Ethernet_Phy/ETH_RXD1" AddNet "/Ethernet_Phy/ETH_RXER" -AddNet "/Ethernet_Phy/ETH_TXD0" -AddNet "/Ethernet_Phy/ETH_TXD1" -AddNet "/Ethernet_Phy/ETH_TXD2" +AddNet "/Ethernet_Phy/ETH_TXEN" +AddNet "/Ethernet_Phy/ETH_TXER" +AddNet "/FPGA_Spartan6/ETH_CLK" +AddNet "/FPGA_Spartan6/ETH_COL" +AddNet "/FPGA_Spartan6/ETH_CRS" +AddNet "/FPGA_Spartan6/ETH_INT" AddNet "/FPGA_Spartan6/ETH_MDC" AddNet "/FPGA_Spartan6/ETH_MDIO" AddNet "/FPGA_Spartan6/ETH_RESET_N" -AddNet "/FPGA_Spartan6/ETH_RXD1" AddNet "/FPGA_Spartan6/ETH_RXD2" +AddNet "/FPGA_Spartan6/ETH_RXD3" +AddNet "/FPGA_Spartan6/ETH_RXDV" AddNet "/FPGA_Spartan6/ETH_TXC" +AddNet "/FPGA_Spartan6/ETH_TXD0" +AddNet "/FPGA_Spartan6/ETH_TXD1" +AddNet "/FPGA_Spartan6/ETH_TXD2" AddNet "/FPGA_Spartan6/ETH_TXD3" -AddNet "/FPGA_Spartan6/ETH_TXEN" -AddNet "/FPGA_Spartan6/ETH_TXER" +AddNet "/FPGA_Spartan6/M0_A0" AddNet "/FPGA_Spartan6/M0_A1" -AddNet "/FPGA_Spartan6/M0_A11" AddNet "/FPGA_Spartan6/M0_A12" AddNet "/FPGA_Spartan6/M0_A3" AddNet "/FPGA_Spartan6/M0_A4" -AddNet "/FPGA_Spartan6/M0_A8" -AddNet "/FPGA_Spartan6/M0_CKE" +AddNet "/FPGA_Spartan6/M0_A5" +AddNet "/FPGA_Spartan6/M0_A7" +AddNet "/FPGA_Spartan6/M0_BA0" +AddNet "/FPGA_Spartan6/M0_CAS#" +AddNet "/FPGA_Spartan6/M0_CLK" +AddNet "/FPGA_Spartan6/M0_CLK#" AddNet "/FPGA_Spartan6/M0_DQ0" -AddNet "/FPGA_Spartan6/M0_DQ1" -AddNet "/FPGA_Spartan6/M0_DQ11" -AddNet "/FPGA_Spartan6/M0_DQ12" AddNet "/FPGA_Spartan6/M0_DQ14" AddNet "/FPGA_Spartan6/M0_DQ15" +AddNet "/FPGA_Spartan6/M0_DQ2" AddNet "/FPGA_Spartan6/M0_DQ3" -AddNet "/FPGA_Spartan6/M0_DQ6" -AddNet "/FPGA_Spartan6/M0_DQ8" -AddNet "/FPGA_Spartan6/M0_DQ9" -AddNet "/FPGA_Spartan6/M0_RAS#" +AddNet "/FPGA_Spartan6/M0_DQ4" +AddNet "/FPGA_Spartan6/M0_DQ5" +AddNet "/FPGA_Spartan6/M0_LDM" +AddNet "/FPGA_Spartan6/M0_LDQS" AddNet "/FPGA_Spartan6/M0_UDM" -AddNet "/FPGA_Spartan6/M0_UDQS" +AddNet "/FPGA_Spartan6/M0_WE#" AddNet "/FPGA_Spartan6/M1_A1" AddNet "/FPGA_Spartan6/M1_A10" -AddNet "/FPGA_Spartan6/M1_A12" -AddNet "/FPGA_Spartan6/M1_A2" -AddNet "/FPGA_Spartan6/M1_A3" AddNet "/FPGA_Spartan6/M1_A4" -AddNet "/FPGA_Spartan6/M1_A5" AddNet "/FPGA_Spartan6/M1_A6" +AddNet "/FPGA_Spartan6/M1_A7" AddNet "/FPGA_Spartan6/M1_A9" AddNet "/FPGA_Spartan6/M1_BA0" -AddNet "/FPGA_Spartan6/M1_CAS#" +AddNet "/FPGA_Spartan6/M1_BA1" AddNet "/FPGA_Spartan6/M1_CKE" +AddNet "/FPGA_Spartan6/M1_CLK" +AddNet "/FPGA_Spartan6/M1_CLK#" +AddNet "/FPGA_Spartan6/M1_CS#" AddNet "/FPGA_Spartan6/M1_DQ0" -AddNet "/FPGA_Spartan6/M1_DQ10" +AddNet "/FPGA_Spartan6/M1_DQ1" +AddNet "/FPGA_Spartan6/M1_DQ12" AddNet "/FPGA_Spartan6/M1_DQ13" AddNet "/FPGA_Spartan6/M1_DQ14" +AddNet "/FPGA_Spartan6/M1_DQ15" AddNet "/FPGA_Spartan6/M1_DQ2" AddNet "/FPGA_Spartan6/M1_DQ3" AddNet "/FPGA_Spartan6/M1_DQ5" +AddNet "/FPGA_Spartan6/M1_DQ6" AddNet "/FPGA_Spartan6/M1_DQ7" +AddNet "/FPGA_Spartan6/M1_DQ8" AddNet "/FPGA_Spartan6/M1_DQ9" -AddNet "/FPGA_Spartan6/M1_LDM" -AddNet "/FPGA_Spartan6/M1_LDQS" AddNet "/FPGA_Spartan6/M1_RAS#" -AddNet "/FPGA_Spartan6/NF_ALE" -AddNet "/FPGA_Spartan6/NF_CLE" +AddNet "/FPGA_Spartan6/M1_UDQS" +AddNet "/FPGA_Spartan6/M1_WE#" +AddNet "/FPGA_Spartan6/NF_D1" AddNet "/FPGA_Spartan6/NF_D2" -AddNet "/FPGA_Spartan6/NF_D3" AddNet "/FPGA_Spartan6/NF_D4" -AddNet "/FPGA_Spartan6/NF_D7" -AddNet "/FPGA_Spartan6/NF_RNB" +AddNet "/FPGA_Spartan6/NF_D5" +AddNet "/FPGA_Spartan6/NF_D6" AddNet "/FPGA_Spartan6/PROG_CCLK" AddNet "/FPGA_Spartan6/PROG_CSO" AddNet "/FPGA_Spartan6/PROG_MISO0" AddNet "/FPGA_Spartan6/PROG_MISO1" AddNet "/FPGA_Spartan6/PROG_MISO2" AddNet "/FPGA_Spartan6/PROG_MISO3" +AddNet "/FPGA_Spartan6/SD_CLK" AddNet "/FPGA_Spartan6/SD_CMD" AddNet "/FPGA_Spartan6/SD_DAT0" -AddNet "/FPGA_Spartan6/SD_DAT3" -AddNet "/FPGA_Spartan6/USBA_OE_N" -AddNet "/FPGA_Spartan6/USBA_VM" +AddNet "/FPGA_Spartan6/USBA_RCV" +AddNet "/FPGA_Spartan6/USBA_SPD" +AddNet "/Non_volatile_memories/NF_ALE" +AddNet "/Non_volatile_memories/NF_CLE" AddNet "/Non_volatile_memories/NF_CS1_N" AddNet "/Non_volatile_memories/NF_D0" -AddNet "/Non_volatile_memories/NF_D1" -AddNet "/Non_volatile_memories/NF_D5" -AddNet "/Non_volatile_memories/NF_D6" +AddNet "/Non_volatile_memories/NF_D3" +AddNet "/Non_volatile_memories/NF_D7" AddNet "/Non_volatile_memories/NF_RE_N" +AddNet "/Non_volatile_memories/NF_RNB" AddNet "/Non_volatile_memories/NF_WE_N" -AddNet "/Non_volatile_memories/SD_CLK" AddNet "/Non_volatile_memories/SD_DAT1" AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "/USB/USBA_RCV" -AddNet "/USB/USBA_SPD" +AddNet "/Non_volatile_memories/SD_DAT3" +AddNet "/USB/USBA_OE_N" +AddNet "/USB/USBA_VM" AddNet "/USB/USBA_VP" AddNet "N-000395" AddNet "N-000397" @@ -1247,10 +1254,6 @@ ViaDia 157 ViaDrill 79 uViaDia 197 uViaDrill 79 -AddNet "/DDR_Banks/M1_CLK" -AddNet "/DDR_Banks/M1_CLK#" -AddNet "/FPGA_Spartan6/M0_CLK" -AddNet "/FPGA_Spartan6/M0_CLK#" $EndNCLASS $NCLASS Name "DATA/DDR" @@ -1261,12 +1264,9 @@ ViaDia 157 ViaDrill 79 uViaDia 197 uViaDrill 79 -AddNet "/DDR_Banks/M1_WE#" AddNet "/FPGA_Spartan6/M0_A10" AddNet "/FPGA_Spartan6/M0_DQ10" AddNet "/FPGA_Spartan6/M0_DQ13" -AddNet "/FPGA_Spartan6/M0_DQ7" -AddNet "/FPGA_Spartan6/M1_DQ8" AddNet "/FPGA_Spartan6/R_M0_A0" AddNet "/FPGA_Spartan6/R_M0_A1" AddNet "/FPGA_Spartan6/R_M0_A10" @@ -1437,28 +1437,28 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_CLK" +Ne 54 "/FPGA_Spartan6/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/ETH_RXD1" +Ne 45 "/Ethernet_Phy/ETH_RXD1" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_RXDV" +Ne 63 "/FPGA_Spartan6/ETH_RXDV" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_RXC" +Ne 43 "/Ethernet_Phy/ETH_RXC" Po -1771 -4133 $EndPAD $PAD @@ -1472,35 +1472,35 @@ $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXD0" +Ne 55 "/FPGA_Spartan6/ETH_COL" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_INT" +Ne 57 "/FPGA_Spartan6/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/NF_D7" +Ne 221 "/Non_volatile_memories/NF_D7" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/NF_D3" +Ne 220 "/Non_volatile_memories/NF_D3" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 220 "/Non_volatile_memories/NF_D1" +Ne 122 "/FPGA_Spartan6/NF_D1" Po 590 -4133 $EndPAD $PAD @@ -1514,28 +1514,28 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_ALE" +Ne 216 "/Non_volatile_memories/NF_ALE" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/NF_RNB" +Ne 223 "/Non_volatile_memories/NF_RNB" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 227 "/Non_volatile_memories/SD_DAT2" +Ne 226 "/Non_volatile_memories/SD_DAT2" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 214 "/FPGA_Spartan6/SD_DAT0" +Ne 213 "/FPGA_Spartan6/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -1605,7 +1605,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_RXD0" +Ne 44 "/Ethernet_Phy/ETH_RXD0" Po -2165 -3739 $EndPAD $PAD @@ -1619,7 +1619,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_RXER" +Ne 46 "/Ethernet_Phy/ETH_RXER" Po -1377 -3739 $EndPAD $PAD @@ -1633,7 +1633,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_COL" +Ne 56 "/FPGA_Spartan6/ETH_CRS" Po -590 -3739 $EndPAD $PAD @@ -1647,7 +1647,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/NF_D4" +Ne 124 "/FPGA_Spartan6/NF_D4" Po 196 -3739 $EndPAD $PAD @@ -1675,7 +1675,7 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 223 "/Non_volatile_memories/NF_RE_N" +Ne 222 "/Non_volatile_memories/NF_RE_N" Po 1771 -3739 $EndPAD $PAD @@ -1689,7 +1689,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 226 "/Non_volatile_memories/SD_DAT1" +Ne 225 "/Non_volatile_memories/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1724,7 +1724,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/FPGA_Spartan6/R_M0_A11" +Ne 136 "/FPGA_Spartan6/R_M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1752,42 +1752,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXD3" +Ne 62 "/FPGA_Spartan6/ETH_RXD3" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/ETH_RXD2" +Ne 61 "/FPGA_Spartan6/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_RESET_N" +Ne 60 "/FPGA_Spartan6/ETH_RESET_N" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/ETH_TXC" +Ne 64 "/FPGA_Spartan6/ETH_TXC" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/Ethernet_Phy/ETH_TXD2" +Ne 66 "/FPGA_Spartan6/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_CRS" +Ne 67 "/FPGA_Spartan6/ETH_TXD2" Po -590 -3346 $EndPAD $PAD @@ -1801,14 +1801,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/Non_volatile_memories/NF_D5" +Ne 125 "/FPGA_Spartan6/NF_D5" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/NF_D2" +Ne 123 "/FPGA_Spartan6/NF_D2" Po 590 -3346 $EndPAD $PAD @@ -1836,7 +1836,7 @@ $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 215 "/FPGA_Spartan6/SD_DAT3" +Ne 227 "/Non_volatile_memories/SD_DAT3" Po 2165 -3346 $EndPAD $PAD @@ -1857,7 +1857,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/FPGA_Spartan6/R_M1_A8" +Ne 182 "/FPGA_Spartan6/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1871,21 +1871,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "/FPGA_Spartan6/R_M1_A9" +Ne 183 "/FPGA_Spartan6/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/FPGA_Spartan6/R_M0_A12" +Ne 137 "/FPGA_Spartan6/R_M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/FPGA_Spartan6/R_M0_CKE" +Ne 149 "/FPGA_Spartan6/R_M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1913,42 +1913,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_MDIO" +Ne 59 "/FPGA_Spartan6/ETH_MDIO" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_MDC" +Ne 58 "/FPGA_Spartan6/ETH_MDC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/ETH_TXER" +Ne 48 "/Ethernet_Phy/ETH_TXER" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/ETH_TXEN" +Ne 47 "/Ethernet_Phy/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/ETH_TXD1" +Ne 65 "/FPGA_Spartan6/ETH_TXD0" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "/Non_volatile_memories/NF_D6" +Ne 126 "/FPGA_Spartan6/NF_D6" Po -196 -2952 $EndPAD $PAD @@ -1976,7 +1976,7 @@ $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/NF_CLE" +Ne 217 "/Non_volatile_memories/NF_CLE" Po 1377 -2952 $EndPAD $PAD @@ -1990,7 +1990,7 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 213 "/FPGA_Spartan6/SD_CMD" +Ne 212 "/FPGA_Spartan6/SD_CMD" Po 2165 -2952 $EndPAD $PAD @@ -2018,21 +2018,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/FPGA_Spartan6/R_M1_CKE" +Ne 187 "/FPGA_Spartan6/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/FPGA_Spartan6/R_M1_A12" +Ne 176 "/FPGA_Spartan6/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA_Spartan6/R_M0_A9" +Ne 145 "/FPGA_Spartan6/R_M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -2046,7 +2046,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA_Spartan6/R_M0_A8" +Ne 144 "/FPGA_Spartan6/R_M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -2137,7 +2137,7 @@ $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 225 "/Non_volatile_memories/SD_CLK" +Ne 211 "/FPGA_Spartan6/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -2165,7 +2165,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/FPGA_Spartan6/R_M1_A7" +Ne 181 "/FPGA_Spartan6/R_M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -2179,7 +2179,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/FPGA_Spartan6/R_M1_A2" +Ne 177 "/FPGA_Spartan6/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -2193,14 +2193,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/FPGA_Spartan6/R_M0_WE#" +Ne 171 "/FPGA_Spartan6/R_M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/FPGA_Spartan6/R_M0_A4" +Ne 140 "/FPGA_Spartan6/R_M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -2312,7 +2312,7 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/FPGA_Spartan6/R_M1_A11" +Ne 175 "/FPGA_Spartan6/R_M1_A11" Po 2952 -2165 $EndPAD $PAD @@ -2326,21 +2326,21 @@ $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/FPGA_Spartan6/R_M1_A0" +Ne 172 "/FPGA_Spartan6/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/FPGA_Spartan6/R_M1_A1" +Ne 173 "/FPGA_Spartan6/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_Spartan6/R_M0_BA1" +Ne 147 "/FPGA_Spartan6/R_M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -2354,14 +2354,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA_Spartan6/R_M0_BA0" +Ne 146 "/FPGA_Spartan6/R_M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA_Spartan6/R_M0_A10" +Ne 135 "/FPGA_Spartan6/R_M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -2466,14 +2466,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/FPGA_Spartan6/R_M1_A10" +Ne 174 "/FPGA_Spartan6/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 180 "/FPGA_Spartan6/R_M1_A3" +Ne 178 "/FPGA_Spartan6/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2494,14 +2494,14 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_Spartan6/R_M0_A1" +Ne 134 "/FPGA_Spartan6/R_M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_Spartan6/R_M0_A0" +Ne 133 "/FPGA_Spartan6/R_M0_A0" Po -3739 -1377 $EndPAD $PAD @@ -2522,14 +2522,14 @@ $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/FPGA_Spartan6/R_M0_A2" +Ne 138 "/FPGA_Spartan6/R_M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA_Spartan6/R_M0_A7" +Ne 143 "/FPGA_Spartan6/R_M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -2599,7 +2599,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/FPGA_Spartan6/R_M1_CS#" +Ne 188 "/FPGA_Spartan6/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -2620,35 +2620,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 212 "/FPGA_Spartan6/R_M1_WE#" +Ne 210 "/FPGA_Spartan6/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_CLK" +Ne 103 "/FPGA_Spartan6/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 209 "/FPGA_Spartan6/R_M1_RAS#" +Ne 207 "/FPGA_Spartan6/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/FPGA_Spartan6/R_M1_CAS#" +Ne 186 "/FPGA_Spartan6/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/FPGA_Spartan6/R_M0_DQ5" +Ne 161 "/FPGA_Spartan6/R_M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -2662,14 +2662,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_Spartan6/R_M0_DQ4" +Ne 160 "/FPGA_Spartan6/R_M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/FPGA_Spartan6/R_M0_A6" +Ne 142 "/FPGA_Spartan6/R_M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2760,7 +2760,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 186 "/FPGA_Spartan6/R_M1_BA0" +Ne 184 "/FPGA_Spartan6/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2774,14 +2774,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_CLK#" +Ne 104 "/FPGA_Spartan6/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "/FPGA_Spartan6/R_M1_DQ4" +Ne 199 "/FPGA_Spartan6/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD @@ -2795,49 +2795,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 202 "/FPGA_Spartan6/R_M1_DQ5" +Ne 200 "/FPGA_Spartan6/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/FPGA_Spartan6/R_M0_DQ7" +Ne 163 "/FPGA_Spartan6/R_M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/FPGA_Spartan6/R_M0_DQ6" +Ne 162 "/FPGA_Spartan6/R_M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/FPGA_Spartan6/R_M0_A5" +Ne 141 "/FPGA_Spartan6/R_M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/FPGA_Spartan6/R_M0_CAS#" +Ne 148 "/FPGA_Spartan6/R_M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/FPGA_Spartan6/R_M0_RAS#" +Ne 168 "/FPGA_Spartan6/R_M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/FPGA_Spartan6/R_M0_A3" +Ne 139 "/FPGA_Spartan6/R_M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2914,7 +2914,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/FPGA_Spartan6/R_M1_BA1" +Ne 185 "/FPGA_Spartan6/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2928,28 +2928,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/FPGA_Spartan6/R_M1_A6" +Ne 180 "/FPGA_Spartan6/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/FPGA_Spartan6/R_M1_A5" +Ne 179 "/FPGA_Spartan6/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 203 "/FPGA_Spartan6/R_M1_DQ6" +Ne 201 "/FPGA_Spartan6/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 204 "/FPGA_Spartan6/R_M1_DQ7" +Ne 202 "/FPGA_Spartan6/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2970,14 +2970,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/FPGA_Spartan6/R_M0_LDQS" +Ne 167 "/FPGA_Spartan6/R_M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/FPGA_Spartan6/R_M0_LDM" +Ne 166 "/FPGA_Spartan6/R_M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -3082,14 +3082,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 207 "/FPGA_Spartan6/R_M1_LDM" +Ne 205 "/FPGA_Spartan6/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 208 "/FPGA_Spartan6/R_M1_LDQS" +Ne 206 "/FPGA_Spartan6/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -3110,21 +3110,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_Spartan6/R_M0_DQ3" +Ne 159 "/FPGA_Spartan6/R_M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/FPGA_Spartan6/R_M0_DQ2" +Ne 158 "/FPGA_Spartan6/R_M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/FPGA_Spartan6/R_M0_UDM" +Ne 169 "/FPGA_Spartan6/R_M0_UDM" Po -3346 196 $EndPAD $PAD @@ -3229,7 +3229,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/FPGA_Spartan6/USBA_VM" +Ne 229 "/USB/USBA_VM" Po 2558 196 $EndPAD $PAD @@ -3243,28 +3243,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 210 "/FPGA_Spartan6/R_M1_UDM" +Ne 208 "/FPGA_Spartan6/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 199 "/FPGA_Spartan6/R_M1_DQ2" +Ne 197 "/FPGA_Spartan6/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 200 "/FPGA_Spartan6/R_M1_DQ3" +Ne 198 "/FPGA_Spartan6/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_Spartan6/R_M0_DQ1" +Ne 151 "/FPGA_Spartan6/R_M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -3278,7 +3278,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/FPGA_Spartan6/R_M0_DQ0" +Ne 150 "/FPGA_Spartan6/R_M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -3369,7 +3369,7 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 228 "/USB/USBA_RCV" +Ne 214 "/FPGA_Spartan6/USBA_RCV" Po 1771 590 $EndPAD $PAD @@ -3397,7 +3397,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/FPGA_Spartan6/R_M1_DQ0" +Ne 189 "/FPGA_Spartan6/R_M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -3411,21 +3411,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 192 "/FPGA_Spartan6/R_M1_DQ1" +Ne 190 "/FPGA_Spartan6/R_M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/FPGA_Spartan6/R_M0_DQ9" +Ne 165 "/FPGA_Spartan6/R_M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/FPGA_Spartan6/R_M0_DQ8" +Ne 164 "/FPGA_Spartan6/R_M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3537,7 +3537,7 @@ $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 216 "/FPGA_Spartan6/USBA_OE_N" +Ne 228 "/USB/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -3558,21 +3558,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 205 "/FPGA_Spartan6/R_M1_DQ8" +Ne 203 "/FPGA_Spartan6/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "/FPGA_Spartan6/R_M1_DQ9" +Ne 204 "/FPGA_Spartan6/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/FPGA_Spartan6/R_M0_DQ11" +Ne 153 "/FPGA_Spartan6/R_M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3586,7 +3586,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_Spartan6/R_M0_DQ10" +Ne 152 "/FPGA_Spartan6/R_M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3698,14 +3698,14 @@ $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "/USB/USBA_SPD" +Ne 215 "/FPGA_Spartan6/USBA_SPD" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 193 "/FPGA_Spartan6/R_M1_DQ10" +Ne 191 "/FPGA_Spartan6/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3719,7 +3719,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 194 "/FPGA_Spartan6/R_M1_DQ11" +Ne 192 "/FPGA_Spartan6/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3733,7 +3733,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/FPGA_Spartan6/R_M0_UDQS" +Ne 170 "/FPGA_Spartan6/R_M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3754,7 +3754,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/PROG_CSO" +Ne 128 "/FPGA_Spartan6/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -3866,7 +3866,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 211 "/FPGA_Spartan6/R_M1_UDQS" +Ne 209 "/FPGA_Spartan6/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3880,7 +3880,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_Spartan6/R_M0_DQ13" +Ne 155 "/FPGA_Spartan6/R_M0_DQ13" Po -4133 2165 $EndPAD $PAD @@ -3894,7 +3894,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/FPGA_Spartan6/R_M0_DQ12" +Ne 154 "/FPGA_Spartan6/R_M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3964,14 +3964,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Spartan6/PROG_MISO3" +Ne 132 "/FPGA_Spartan6/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Spartan6/PROG_MISO2" +Ne 131 "/FPGA_Spartan6/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -4013,7 +4013,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 195 "/FPGA_Spartan6/R_M1_DQ12" +Ne 193 "/FPGA_Spartan6/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -4027,21 +4027,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 196 "/FPGA_Spartan6/R_M1_DQ13" +Ne 194 "/FPGA_Spartan6/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/FPGA_Spartan6/R_M0_DQ15" +Ne 157 "/FPGA_Spartan6/R_M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_Spartan6/R_M0_DQ14" +Ne 156 "/FPGA_Spartan6/R_M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -4174,14 +4174,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 197 "/FPGA_Spartan6/R_M1_DQ14" +Ne 195 "/FPGA_Spartan6/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 198 "/FPGA_Spartan6/R_M1_DQ15" +Ne 196 "/FPGA_Spartan6/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -4629,14 +4629,14 @@ $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Spartan6/PROG_MISO1" +Ne 130 "/FPGA_Spartan6/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/PROG_CCLK" +Ne 127 "/FPGA_Spartan6/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -4783,7 +4783,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/PROG_MISO0" +Ne 129 "/FPGA_Spartan6/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -4966,14 +4966,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/FPGA_Spartan6/R_M0_UDM" +Ne 169 "/FPGA_Spartan6/R_M0_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/FPGA_Spartan6/M0_UDM" +Ne 92 "/FPGA_Spartan6/M0_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4994,14 +4994,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 172 "/FPGA_Spartan6/R_M0_UDQS" +Ne 170 "/FPGA_Spartan6/R_M0_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 96 "/FPGA_Spartan6/M0_UDQS" +Ne 21 "/DDR_Banks/M0_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5022,14 +5022,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 151 "/FPGA_Spartan6/R_M0_CKE" +Ne 149 "/FPGA_Spartan6/R_M0_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 78 "/FPGA_Spartan6/M0_CKE" +Ne 12 "/DDR_Banks/M0_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5076,35 +5076,35 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 135 "/FPGA_Spartan6/R_M0_A0" +Ne 133 "/FPGA_Spartan6/R_M0_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 136 "/FPGA_Spartan6/R_M0_A1" +Ne 134 "/FPGA_Spartan6/R_M0_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 140 "/FPGA_Spartan6/R_M0_A2" +Ne 138 "/FPGA_Spartan6/R_M0_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 141 "/FPGA_Spartan6/R_M0_A3" +Ne 139 "/FPGA_Spartan6/R_M0_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 75 "/FPGA_Spartan6/M0_A3" +Ne 73 "/FPGA_Spartan6/M0_A3" Po 295 177 $EndPAD $PAD @@ -5118,14 +5118,14 @@ $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 71 "/FPGA_Spartan6/M0_A1" +Ne 70 "/FPGA_Spartan6/M0_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 6 "/DDR_Banks/M0_A0" +Ne 69 "/FPGA_Spartan6/M0_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5144,56 +5144,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/FPGA_Spartan6/R_M0_RAS#" +Ne 168 "/FPGA_Spartan6/R_M0_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 148 "/FPGA_Spartan6/R_M0_BA0" +Ne 146 "/FPGA_Spartan6/R_M0_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/FPGA_Spartan6/R_M0_BA1" +Ne 147 "/FPGA_Spartan6/R_M0_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 137 "/FPGA_Spartan6/R_M0_A10" +Ne 135 "/FPGA_Spartan6/R_M0_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 72 "/FPGA_Spartan6/M0_A10" +Ne 71 "/FPGA_Spartan6/M0_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 13 "/DDR_Banks/M0_BA1" +Ne 11 "/DDR_Banks/M0_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 12 "/DDR_Banks/M0_BA0" +Ne 77 "/FPGA_Spartan6/M0_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/FPGA_Spartan6/M0_RAS#" +Ne 20 "/DDR_Banks/M0_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5212,56 +5212,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/FPGA_Spartan6/R_M0_LDQS" +Ne 167 "/FPGA_Spartan6/R_M0_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/FPGA_Spartan6/R_M0_LDM" +Ne 166 "/FPGA_Spartan6/R_M0_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 173 "/FPGA_Spartan6/R_M0_WE#" +Ne 171 "/FPGA_Spartan6/R_M0_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/FPGA_Spartan6/R_M0_CAS#" +Ne 148 "/FPGA_Spartan6/R_M0_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 14 "/DDR_Banks/M0_CAS#" +Ne 78 "/FPGA_Spartan6/M0_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 21 "/DDR_Banks/M0_WE#" +Ne 93 "/FPGA_Spartan6/M0_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Banks/M0_LDM" +Ne 90 "/FPGA_Spartan6/M0_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 19 "/DDR_Banks/M0_LDQS" +Ne 91 "/FPGA_Spartan6/M0_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5280,56 +5280,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 145 "/FPGA_Spartan6/R_M0_A7" +Ne 143 "/FPGA_Spartan6/R_M0_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/FPGA_Spartan6/R_M0_A6" +Ne 142 "/FPGA_Spartan6/R_M0_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/FPGA_Spartan6/R_M0_A5" +Ne 141 "/FPGA_Spartan6/R_M0_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/FPGA_Spartan6/R_M0_A4" +Ne 140 "/FPGA_Spartan6/R_M0_A4" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 76 "/FPGA_Spartan6/M0_A4" +Ne 74 "/FPGA_Spartan6/M0_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 8 "/DDR_Banks/M0_A5" +Ne 75 "/FPGA_Spartan6/M0_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 9 "/DDR_Banks/M0_A6" +Ne 8 "/DDR_Banks/M0_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 10 "/DDR_Banks/M0_A7" +Ne 76 "/FPGA_Spartan6/M0_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5348,56 +5348,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 139 "/FPGA_Spartan6/R_M0_A12" +Ne 137 "/FPGA_Spartan6/R_M0_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 138 "/FPGA_Spartan6/R_M0_A11" +Ne 136 "/FPGA_Spartan6/R_M0_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 147 "/FPGA_Spartan6/R_M0_A9" +Ne 145 "/FPGA_Spartan6/R_M0_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 146 "/FPGA_Spartan6/R_M0_A8" +Ne 144 "/FPGA_Spartan6/R_M0_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 77 "/FPGA_Spartan6/M0_A8" +Ne 9 "/DDR_Banks/M0_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 11 "/DDR_Banks/M0_A9" +Ne 10 "/DDR_Banks/M0_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 73 "/FPGA_Spartan6/M0_A11" +Ne 6 "/DDR_Banks/M0_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 74 "/FPGA_Spartan6/M0_A12" +Ne 72 "/FPGA_Spartan6/M0_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5416,56 +5416,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/FPGA_Spartan6/R_M0_DQ4" +Ne 160 "/FPGA_Spartan6/R_M0_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/FPGA_Spartan6/R_M0_DQ5" +Ne 161 "/FPGA_Spartan6/R_M0_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/FPGA_Spartan6/R_M0_DQ6" +Ne 162 "/FPGA_Spartan6/R_M0_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/FPGA_Spartan6/R_M0_DQ7" +Ne 163 "/FPGA_Spartan6/R_M0_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 91 "/FPGA_Spartan6/M0_DQ7" +Ne 17 "/DDR_Banks/M0_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 90 "/FPGA_Spartan6/M0_DQ6" +Ne 16 "/DDR_Banks/M0_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 17 "/DDR_Banks/M0_DQ5" +Ne 89 "/FPGA_Spartan6/M0_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 16 "/DDR_Banks/M0_DQ4" +Ne 88 "/FPGA_Spartan6/M0_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5484,49 +5484,49 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 152 "/FPGA_Spartan6/R_M0_DQ0" +Ne 150 "/FPGA_Spartan6/R_M0_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/FPGA_Spartan6/R_M0_DQ1" +Ne 151 "/FPGA_Spartan6/R_M0_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/FPGA_Spartan6/R_M0_DQ2" +Ne 158 "/FPGA_Spartan6/R_M0_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/FPGA_Spartan6/R_M0_DQ3" +Ne 159 "/FPGA_Spartan6/R_M0_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 89 "/FPGA_Spartan6/M0_DQ3" +Ne 87 "/FPGA_Spartan6/M0_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 15 "/DDR_Banks/M0_DQ2" +Ne 86 "/FPGA_Spartan6/M0_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 82 "/FPGA_Spartan6/M0_DQ1" +Ne 13 "/DDR_Banks/M0_DQ1" Po -98 177 $EndPAD $PAD @@ -5552,56 +5552,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/FPGA_Spartan6/R_M0_DQ8" +Ne 164 "/FPGA_Spartan6/R_M0_DQ8" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/FPGA_Spartan6/R_M0_DQ9" +Ne 165 "/FPGA_Spartan6/R_M0_DQ9" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 154 "/FPGA_Spartan6/R_M0_DQ10" +Ne 152 "/FPGA_Spartan6/R_M0_DQ10" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/FPGA_Spartan6/R_M0_DQ11" +Ne 153 "/FPGA_Spartan6/R_M0_DQ11" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Spartan6/M0_DQ11" +Ne 14 "/DDR_Banks/M0_DQ11" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 83 "/FPGA_Spartan6/M0_DQ10" +Ne 82 "/FPGA_Spartan6/M0_DQ10" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 93 "/FPGA_Spartan6/M0_DQ9" +Ne 19 "/DDR_Banks/M0_DQ9" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 92 "/FPGA_Spartan6/M0_DQ8" +Ne 18 "/DDR_Banks/M0_DQ8" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5620,56 +5620,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/FPGA_Spartan6/R_M0_DQ12" +Ne 154 "/FPGA_Spartan6/R_M0_DQ12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/FPGA_Spartan6/R_M0_DQ13" +Ne 155 "/FPGA_Spartan6/R_M0_DQ13" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/FPGA_Spartan6/R_M0_DQ14" +Ne 156 "/FPGA_Spartan6/R_M0_DQ14" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/FPGA_Spartan6/R_M0_DQ15" +Ne 157 "/FPGA_Spartan6/R_M0_DQ15" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 88 "/FPGA_Spartan6/M0_DQ15" +Ne 85 "/FPGA_Spartan6/M0_DQ15" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 87 "/FPGA_Spartan6/M0_DQ14" +Ne 84 "/FPGA_Spartan6/M0_DQ14" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 86 "/FPGA_Spartan6/M0_DQ13" +Ne 83 "/FPGA_Spartan6/M0_DQ13" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 85 "/FPGA_Spartan6/M0_DQ12" +Ne 15 "/DDR_Banks/M0_DQ12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5873,14 +5873,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 211 "/FPGA_Spartan6/R_M1_UDQS" +Ne 209 "/FPGA_Spartan6/R_M1_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 37 "/DDR_Banks/M1_UDQS" +Ne 120 "/FPGA_Spartan6/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5901,14 +5901,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 190 "/FPGA_Spartan6/R_M1_CS#" +Ne 188 "/FPGA_Spartan6/R_M1_CS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/DDR_Banks/M1_CS#" +Ne 105 "/FPGA_Spartan6/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5929,14 +5929,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 189 "/FPGA_Spartan6/R_M1_CKE" +Ne 187 "/FPGA_Spartan6/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 108 "/FPGA_Spartan6/M1_CKE" +Ne 102 "/FPGA_Spartan6/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5957,7 +5957,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 210 "/FPGA_Spartan6/R_M1_UDM" +Ne 208 "/FPGA_Spartan6/R_M1_UDM" Po -176 0 $EndPAD $PAD @@ -5983,56 +5983,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 198 "/FPGA_Spartan6/R_M1_DQ15" +Ne 196 "/FPGA_Spartan6/R_M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 197 "/FPGA_Spartan6/R_M1_DQ14" +Ne 195 "/FPGA_Spartan6/R_M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 196 "/FPGA_Spartan6/R_M1_DQ13" +Ne 194 "/FPGA_Spartan6/R_M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 195 "/FPGA_Spartan6/R_M1_DQ12" +Ne 193 "/FPGA_Spartan6/R_M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Banks/M1_DQ12" +Ne 108 "/FPGA_Spartan6/M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 111 "/FPGA_Spartan6/M1_DQ13" +Ne 109 "/FPGA_Spartan6/M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 112 "/FPGA_Spartan6/M1_DQ14" +Ne 110 "/FPGA_Spartan6/M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_DQ15" +Ne 111 "/FPGA_Spartan6/M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6051,28 +6051,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 194 "/FPGA_Spartan6/R_M1_DQ11" +Ne 192 "/FPGA_Spartan6/R_M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 193 "/FPGA_Spartan6/R_M1_DQ10" +Ne 191 "/FPGA_Spartan6/R_M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 206 "/FPGA_Spartan6/R_M1_DQ9" +Ne 204 "/FPGA_Spartan6/R_M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 205 "/FPGA_Spartan6/R_M1_DQ8" +Ne 203 "/FPGA_Spartan6/R_M1_DQ8" Po 295 -177 $EndPAD $PAD @@ -6093,14 +6093,14 @@ $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 110 "/FPGA_Spartan6/M1_DQ10" +Ne 31 "/DDR_Banks/M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/DDR_Banks/M1_DQ11" +Ne 32 "/DDR_Banks/M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6121,14 +6121,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M1_CLK#" +Ne 104 "/FPGA_Spartan6/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Banks/M1_CLK" +Ne 103 "/FPGA_Spartan6/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6147,56 +6147,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 178 "/FPGA_Spartan6/R_M1_A12" +Ne 176 "/FPGA_Spartan6/R_M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 177 "/FPGA_Spartan6/R_M1_A11" +Ne 175 "/FPGA_Spartan6/R_M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "/FPGA_Spartan6/R_M1_A9" +Ne 183 "/FPGA_Spartan6/R_M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/FPGA_Spartan6/R_M1_A8" +Ne 182 "/FPGA_Spartan6/R_M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M1_A8" +Ne 29 "/DDR_Banks/M1_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 105 "/FPGA_Spartan6/M1_A9" +Ne 99 "/FPGA_Spartan6/M1_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/DDR_Banks/M1_A11" +Ne 24 "/DDR_Banks/M1_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 99 "/FPGA_Spartan6/M1_A12" +Ne 25 "/DDR_Banks/M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6215,21 +6215,21 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/FPGA_Spartan6/R_M1_A7" +Ne 181 "/FPGA_Spartan6/R_M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/FPGA_Spartan6/R_M1_A6" +Ne 180 "/FPGA_Spartan6/R_M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/FPGA_Spartan6/R_M1_A5" +Ne 179 "/FPGA_Spartan6/R_M1_A5" Po 98 -177 $EndPAD $PAD @@ -6243,28 +6243,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 102 "/FPGA_Spartan6/M1_A4" +Ne 96 "/FPGA_Spartan6/M1_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/FPGA_Spartan6/M1_A5" +Ne 28 "/DDR_Banks/M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/FPGA_Spartan6/M1_A6" +Ne 97 "/FPGA_Spartan6/M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Banks/M1_A7" +Ne 98 "/FPGA_Spartan6/M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6283,56 +6283,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 191 "/FPGA_Spartan6/R_M1_DQ0" +Ne 189 "/FPGA_Spartan6/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 192 "/FPGA_Spartan6/R_M1_DQ1" +Ne 190 "/FPGA_Spartan6/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 199 "/FPGA_Spartan6/R_M1_DQ2" +Ne 197 "/FPGA_Spartan6/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 200 "/FPGA_Spartan6/R_M1_DQ3" +Ne 198 "/FPGA_Spartan6/R_M1_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 114 "/FPGA_Spartan6/M1_DQ3" +Ne 113 "/FPGA_Spartan6/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 113 "/FPGA_Spartan6/M1_DQ2" +Ne 112 "/FPGA_Spartan6/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Banks/M1_DQ1" +Ne 107 "/FPGA_Spartan6/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 109 "/FPGA_Spartan6/M1_DQ0" +Ne 106 "/FPGA_Spartan6/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6351,56 +6351,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 208 "/FPGA_Spartan6/R_M1_LDQS" +Ne 206 "/FPGA_Spartan6/R_M1_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 207 "/FPGA_Spartan6/R_M1_LDM" +Ne 205 "/FPGA_Spartan6/R_M1_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 212 "/FPGA_Spartan6/R_M1_WE#" +Ne 210 "/FPGA_Spartan6/R_M1_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 188 "/FPGA_Spartan6/R_M1_CAS#" +Ne 186 "/FPGA_Spartan6/R_M1_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/FPGA_Spartan6/M1_CAS#" +Ne 30 "/DDR_Banks/M1_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M1_WE#" +Ne 121 "/FPGA_Spartan6/M1_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 119 "/FPGA_Spartan6/M1_LDM" +Ne 34 "/DDR_Banks/M1_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 120 "/FPGA_Spartan6/M1_LDQS" +Ne 35 "/DDR_Banks/M1_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6419,28 +6419,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "/FPGA_Spartan6/R_M1_DQ4" +Ne 199 "/FPGA_Spartan6/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 202 "/FPGA_Spartan6/R_M1_DQ5" +Ne 200 "/FPGA_Spartan6/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 203 "/FPGA_Spartan6/R_M1_DQ6" +Ne 201 "/FPGA_Spartan6/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 204 "/FPGA_Spartan6/R_M1_DQ7" +Ne 202 "/FPGA_Spartan6/R_M1_DQ7" Po 295 -177 $EndPAD $PAD @@ -6454,21 +6454,21 @@ $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/DDR_Banks/M1_DQ6" +Ne 115 "/FPGA_Spartan6/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 115 "/FPGA_Spartan6/M1_DQ5" +Ne 114 "/FPGA_Spartan6/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/DDR_Banks/M1_DQ4" +Ne 33 "/DDR_Banks/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6487,56 +6487,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 209 "/FPGA_Spartan6/R_M1_RAS#" +Ne 207 "/FPGA_Spartan6/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 186 "/FPGA_Spartan6/R_M1_BA0" +Ne 184 "/FPGA_Spartan6/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 187 "/FPGA_Spartan6/R_M1_BA1" +Ne 185 "/FPGA_Spartan6/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 176 "/FPGA_Spartan6/R_M1_A10" +Ne 174 "/FPGA_Spartan6/R_M1_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 98 "/FPGA_Spartan6/M1_A10" +Ne 95 "/FPGA_Spartan6/M1_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Banks/M1_BA1" +Ne 101 "/FPGA_Spartan6/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 106 "/FPGA_Spartan6/M1_BA0" +Ne 100 "/FPGA_Spartan6/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 121 "/FPGA_Spartan6/M1_RAS#" +Ne 119 "/FPGA_Spartan6/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6555,56 +6555,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 174 "/FPGA_Spartan6/R_M1_A0" +Ne 172 "/FPGA_Spartan6/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 175 "/FPGA_Spartan6/R_M1_A1" +Ne 173 "/FPGA_Spartan6/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 179 "/FPGA_Spartan6/R_M1_A2" +Ne 177 "/FPGA_Spartan6/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 180 "/FPGA_Spartan6/R_M1_A3" +Ne 178 "/FPGA_Spartan6/R_M1_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 101 "/FPGA_Spartan6/M1_A3" +Ne 27 "/DDR_Banks/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 100 "/FPGA_Spartan6/M1_A2" +Ne 26 "/DDR_Banks/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 97 "/FPGA_Spartan6/M1_A1" +Ne 94 "/FPGA_Spartan6/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 22 "/DDR_Banks/M1_A0" +Ne 23 "/DDR_Banks/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6653,14 +6653,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_A1.8V" +Ne 38 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 48 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 42 "/Ethernet_Phy/ETH_PLL1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6688,7 +6688,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_A1.8V" +Ne 38 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6716,7 +6716,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_A3.3V" +Ne 39 "/Ethernet_Phy/ETH_A3.3V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6890,42 +6890,42 @@ $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/PROG_CSO" +Ne 128 "/FPGA_Spartan6/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Spartan6/PROG_MISO3" +Ne 132 "/FPGA_Spartan6/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/PROG_CCLK" +Ne 127 "/FPGA_Spartan6/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/PROG_MISO0" +Ne 129 "/FPGA_Spartan6/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Spartan6/PROG_MISO1" +Ne 130 "/FPGA_Spartan6/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Spartan6/PROG_MISO2" +Ne 131 "/FPGA_Spartan6/PROG_MISO2" Po 250 1050 $EndPAD $PAD @@ -8311,7 +8311,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_VREF" +Ne 37 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD @@ -8682,7 +8682,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_VREF" +Ne 37 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8703,7 +8703,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/DDR_Banks/M0_VREF" +Ne 22 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD @@ -8738,7 +8738,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/DDR_Banks/M0_VREF" +Ne 22 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8766,7 +8766,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_VREF" +Ne 37 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8787,7 +8787,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_VREF" +Ne 37 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD @@ -8815,7 +8815,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/DDR_Banks/M0_VREF" +Ne 22 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD @@ -8850,7 +8850,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/DDR_Banks/M0_VREF" +Ne 22 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9002,7 +9002,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_A3.3V" +Ne 39 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD @@ -9282,7 +9282,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_A1.8V" +Ne 38 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD @@ -9310,7 +9310,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_A3.3V" +Ne 39 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD @@ -9338,7 +9338,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 48 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 42 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD @@ -9422,7 +9422,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 59 "/Ethernet_Phy/MAG_SHIELD" +Ne 51 "/Ethernet_Phy/MAG_SHIELD" Po -176 0 $EndPAD $PAD @@ -9478,7 +9478,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 63 "/FPGA_Spartan6/ETH_MDIO" +Ne 59 "/FPGA_Spartan6/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -9541,7 +9541,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 60 "/Ethernet_Phy/MAG_TX+" +Ne 52 "/Ethernet_Phy/MAG_TX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9569,7 +9569,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 61 "/Ethernet_Phy/MAG_TX-" +Ne 53 "/Ethernet_Phy/MAG_TX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9597,7 +9597,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 57 "/Ethernet_Phy/MAG_RX+" +Ne 49 "/Ethernet_Phy/MAG_RX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9625,7 +9625,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 58 "/Ethernet_Phy/MAG_RX-" +Ne 50 "/Ethernet_Phy/MAG_RX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9653,7 +9653,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/Ethernet_Phy/ETH_LED0" +Ne 40 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9681,7 +9681,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/ETH_LED1" +Ne 41 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9702,7 +9702,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 59 "/Ethernet_Phy/MAG_SHIELD" +Ne 51 "/Ethernet_Phy/MAG_SHIELD" Po -176 0 $EndPAD $PAD @@ -9780,14 +9780,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ1" +Ne 13 "/DDR_Banks/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ2" +Ne 86 "/FPGA_Spartan6/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -9801,14 +9801,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M0_DQ3" +Ne 87 "/FPGA_Spartan6/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ4" +Ne 88 "/FPGA_Spartan6/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -9822,14 +9822,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ5" +Ne 89 "/FPGA_Spartan6/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M0_DQ6" +Ne 16 "/DDR_Banks/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -9843,7 +9843,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M0_DQ7" +Ne 17 "/DDR_Banks/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -9864,7 +9864,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_LDQS" +Ne 91 "/FPGA_Spartan6/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -9892,28 +9892,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_LDM" +Ne 90 "/FPGA_Spartan6/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_WE#" +Ne 93 "/FPGA_Spartan6/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_CAS#" +Ne 78 "/FPGA_Spartan6/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M0_RAS#" +Ne 20 "/DDR_Banks/M0_RAS#" Po 1535 2176 $EndPAD $PAD @@ -9934,35 +9934,35 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_BA0" +Ne 77 "/FPGA_Spartan6/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_BA1" +Ne 11 "/DDR_Banks/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_A10" +Ne 71 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A0" +Ne 69 "/FPGA_Spartan6/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A1" +Ne 70 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD @@ -9976,7 +9976,7 @@ $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_A3" +Ne 73 "/FPGA_Spartan6/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -9997,56 +9997,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_A4" +Ne 74 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A5" +Ne 75 "/FPGA_Spartan6/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A6" +Ne 8 "/DDR_Banks/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_A7" +Ne 76 "/FPGA_Spartan6/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_A8" +Ne 9 "/DDR_Banks/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_A9" +Ne 10 "/DDR_Banks/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_A11" +Ne 6 "/DDR_Banks/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_A12" +Ne 72 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -10067,7 +10067,7 @@ $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_CKE" +Ne 12 "/DDR_Banks/M0_CKE" Po 1279 -2176 $EndPAD $PAD @@ -10081,7 +10081,7 @@ $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M0_UDM" +Ne 92 "/FPGA_Spartan6/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -10095,7 +10095,7 @@ $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_VREF" +Ne 22 "/DDR_Banks/M0_VREF" Po 255 -2176 $EndPAD $PAD @@ -10109,7 +10109,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M0_UDQS" +Ne 21 "/DDR_Banks/M0_UDQS" Po -255 -2176 $EndPAD $PAD @@ -10130,7 +10130,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M0_DQ8" +Ne 18 "/DDR_Banks/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10144,14 +10144,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M0_DQ9" +Ne 19 "/DDR_Banks/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ10" +Ne 82 "/FPGA_Spartan6/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -10165,14 +10165,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ11" +Ne 14 "/DDR_Banks/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ12" +Ne 15 "/DDR_Banks/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10186,14 +10186,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ13" +Ne 83 "/FPGA_Spartan6/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_DQ14" +Ne 84 "/FPGA_Spartan6/M0_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10207,7 +10207,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_DQ15" +Ne 85 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10243,7 +10243,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ0" +Ne 106 "/FPGA_Spartan6/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -10257,14 +10257,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ1" +Ne 107 "/FPGA_Spartan6/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_DQ2" +Ne 112 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD @@ -10278,14 +10278,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/M1_DQ3" +Ne 113 "/FPGA_Spartan6/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_DQ4" +Ne 33 "/DDR_Banks/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -10299,14 +10299,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/M1_DQ5" +Ne 114 "/FPGA_Spartan6/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_DQ6" +Ne 115 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -10341,7 +10341,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/M1_LDQS" +Ne 35 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -10369,35 +10369,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/M1_LDM" +Ne 34 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M1_WE#" +Ne 121 "/FPGA_Spartan6/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_CAS#" +Ne 30 "/DDR_Banks/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/M1_RAS#" +Ne 119 "/FPGA_Spartan6/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_CS#" +Ne 105 "/FPGA_Spartan6/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -10411,49 +10411,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_BA0" +Ne 100 "/FPGA_Spartan6/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_BA1" +Ne 101 "/FPGA_Spartan6/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_A10" +Ne 95 "/FPGA_Spartan6/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_A0" +Ne 23 "/DDR_Banks/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_A1" +Ne 94 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_A2" +Ne 26 "/DDR_Banks/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_A3" +Ne 27 "/DDR_Banks/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -10474,56 +10474,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_A4" +Ne 96 "/FPGA_Spartan6/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_A5" +Ne 28 "/DDR_Banks/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_A6" +Ne 97 "/FPGA_Spartan6/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A7" +Ne 98 "/FPGA_Spartan6/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A8" +Ne 29 "/DDR_Banks/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_A9" +Ne 99 "/FPGA_Spartan6/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A11" +Ne 24 "/DDR_Banks/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_A12" +Ne 25 "/DDR_Banks/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -10537,21 +10537,21 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_CLK#" +Ne 104 "/FPGA_Spartan6/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_CKE" +Ne 102 "/FPGA_Spartan6/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_CLK" +Ne 103 "/FPGA_Spartan6/M1_CLK" Po 1023 -2176 $EndPAD $PAD @@ -10572,7 +10572,7 @@ $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_VREF" +Ne 37 "/DDR_Banks/M1_VREF" Po 255 -2176 $EndPAD $PAD @@ -10586,7 +10586,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/DDR_Banks/M1_UDQS" +Ne 120 "/FPGA_Spartan6/M1_UDQS" Po -255 -2176 $EndPAD $PAD @@ -10628,7 +10628,7 @@ $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ10" +Ne 31 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -10642,14 +10642,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ11" +Ne 32 "/DDR_Banks/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_DQ12" +Ne 108 "/FPGA_Spartan6/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10663,14 +10663,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_DQ13" +Ne 109 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_DQ14" +Ne 110 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10684,7 +10684,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_DQ15" +Ne 111 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10727,14 +10727,14 @@ $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "/USB/USBA_SPD" +Ne 215 "/FPGA_Spartan6/USBA_SPD" Po -511 -1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 228 "/USB/USBA_RCV" +Ne 214 "/FPGA_Spartan6/USBA_RCV" Po -255 -1112 $EndPAD $PAD @@ -10748,7 +10748,7 @@ $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 217 "/FPGA_Spartan6/USBA_VM" +Ne 229 "/USB/USBA_VM" Po 255 -1112 $EndPAD $PAD @@ -10776,7 +10776,7 @@ $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 216 "/FPGA_Spartan6/USBA_OE_N" +Ne 228 "/USB/USBA_OE_N" Po 511 1112 $EndPAD $PAD @@ -10831,35 +10831,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 59 "/Ethernet_Phy/MAG_SHIELD" +Ne 51 "/Ethernet_Phy/MAG_SHIELD" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 59 "/Ethernet_Phy/MAG_SHIELD" +Ne 51 "/Ethernet_Phy/MAG_SHIELD" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 59 "/Ethernet_Phy/MAG_SHIELD" +Ne 51 "/Ethernet_Phy/MAG_SHIELD" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 59 "/Ethernet_Phy/MAG_SHIELD" +Ne 51 "/Ethernet_Phy/MAG_SHIELD" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 60 "/Ethernet_Phy/MAG_TX+" +Ne 52 "/Ethernet_Phy/MAG_TX+" Po -1750 -2500 $EndPAD $PAD @@ -10880,14 +10880,14 @@ $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 57 "/Ethernet_Phy/MAG_RX+" +Ne 49 "/Ethernet_Phy/MAG_RX+" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 61 "/Ethernet_Phy/MAG_TX-" +Ne 53 "/Ethernet_Phy/MAG_TX-" Po -1250 -3500 $EndPAD $PAD @@ -10908,7 +10908,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 58 "/Ethernet_Phy/MAG_RX-" +Ne 50 "/Ethernet_Phy/MAG_RX-" Po 1750 -3500 $EndPAD $PAD @@ -10961,21 +10961,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 227 "/Non_volatile_memories/SD_DAT2" +Ne 226 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 215 "/FPGA_Spartan6/SD_DAT3" +Ne 227 "/Non_volatile_memories/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 213 "/FPGA_Spartan6/SD_CMD" +Ne 212 "/FPGA_Spartan6/SD_CMD" Po -433 0 $EndPAD $PAD @@ -10989,7 +10989,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 225 "/Non_volatile_memories/SD_CLK" +Ne 211 "/FPGA_Spartan6/SD_CLK" Po 433 0 $EndPAD $PAD @@ -11003,14 +11003,14 @@ $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 214 "/FPGA_Spartan6/SD_DAT0" +Ne 213 "/FPGA_Spartan6/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 226 "/Non_volatile_memories/SD_DAT1" +Ne 225 "/Non_volatile_memories/SD_DAT1" Po 1732 0 $EndPAD $PAD @@ -11302,21 +11302,21 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/NF_RNB" +Ne 223 "/Non_volatile_memories/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/NF_RNB" +Ne 223 "/Non_volatile_memories/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 223 "/Non_volatile_memories/NF_RE_N" +Ne 222 "/Non_volatile_memories/NF_RE_N" Po -890 3850 $EndPAD $PAD @@ -11372,14 +11372,14 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/NF_CLE" +Ne 217 "/Non_volatile_memories/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_ALE" +Ne 216 "/Non_volatile_memories/NF_ALE" Po 880 3850 $EndPAD $PAD @@ -11470,21 +11470,21 @@ $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 220 "/Non_volatile_memories/NF_D1" +Ne 122 "/FPGA_Spartan6/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/NF_D2" +Ne 123 "/FPGA_Spartan6/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/NF_D3" +Ne 220 "/Non_volatile_memories/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -11547,28 +11547,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/NF_D4" +Ne 124 "/FPGA_Spartan6/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/Non_volatile_memories/NF_D5" +Ne 125 "/FPGA_Spartan6/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 222 "/Non_volatile_memories/NF_D6" +Ne 126 "/FPGA_Spartan6/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/NF_D7" +Ne 221 "/Non_volatile_memories/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -11625,21 +11625,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_RXER" +Ne 46 "/Ethernet_Phy/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_RXC" +Ne 43 "/Ethernet_Phy/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_RXDV" +Ne 63 "/FPGA_Spartan6/ETH_RXDV" Po -1613 491 $EndPAD $PAD @@ -11660,63 +11660,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_RXD0" +Ne 44 "/Ethernet_Phy/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/ETH_RXD1" +Ne 45 "/Ethernet_Phy/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/ETH_RXD2" +Ne 61 "/FPGA_Spartan6/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXD3" +Ne 62 "/FPGA_Spartan6/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_MDC" +Ne 58 "/FPGA_Spartan6/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_MDIO" +Ne 59 "/FPGA_Spartan6/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_RESET_N" +Ne 60 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 42 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_CLK" +Ne 54 "/FPGA_Spartan6/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -11751,14 +11751,14 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/Ethernet_Phy/MAG_TX+" +Ne 52 "/Ethernet_Phy/MAG_TX+" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/Ethernet_Phy/MAG_TX-" +Ne 53 "/Ethernet_Phy/MAG_TX-" Po 491 -1613 $EndPAD $PAD @@ -11772,7 +11772,7 @@ $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_A3.3V" +Ne 39 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD @@ -11786,21 +11786,21 @@ $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_INT" +Ne 57 "/FPGA_Spartan6/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_LED0" +Ne 40 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_LED1" +Ne 41 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -11828,21 +11828,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_A1.8V" +Ne 38 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/Ethernet_Phy/MAG_RX-" +Ne 50 "/Ethernet_Phy/MAG_RX-" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/Ethernet_Phy/MAG_RX+" +Ne 49 "/Ethernet_Phy/MAG_RX+" Po 1613 -491 $EndPAD $PAD @@ -11877,42 +11877,42 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/ETH_TXER" +Ne 48 "/Ethernet_Phy/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/ETH_TXC" +Ne 64 "/FPGA_Spartan6/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/ETH_TXEN" +Ne 47 "/Ethernet_Phy/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXD0" +Ne 65 "/FPGA_Spartan6/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/ETH_TXD1" +Ne 66 "/FPGA_Spartan6/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/Ethernet_Phy/ETH_TXD2" +Ne 67 "/FPGA_Spartan6/ETH_TXD2" Po 98 1613 $EndPAD $PAD @@ -11926,14 +11926,14 @@ $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_COL" +Ne 55 "/FPGA_Spartan6/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_CRS" +Ne 56 "/FPGA_Spartan6/ETH_CRS" Po 688 1613 $EndPAD $PAD @@ -12568,18 +12568,14 @@ Po 3 53317 30472 53317 30472 157 -1 De 15 1 4 0 0 Po 0 53317 30443 53317 30472 79 -1 De 15 0 4 0 0 -Po 0 50995 31576 50694 31576 39 -1 -De 15 0 6 0 800 -Po 0 49921 31535 49768 31535 39 -1 -De 0 0 6 0 400 -Po 0 49961 31575 49921 31535 39 -1 -De 0 0 6 0 0 -Po 0 50693 31575 49961 31575 39 -1 -De 0 0 6 0 0 -Po 3 50693 31575 50693 31575 157 -1 -De 15 1 6 0 0 -Po 0 50694 31576 50693 31575 39 -1 +Po 0 47941 32134 47425 32134 39 -1 +De 0 0 6 0 800 +Po 0 47216 32343 46643 32343 39 -1 +De 15 0 6 0 400 +Po 0 47425 32134 47216 32343 39 -1 De 15 0 6 0 0 +Po 3 47425 32134 47425 32134 157 -1 +De 15 1 6 0 0 Po 0 50995 31064 50688 31064 39 -1 De 15 0 7 0 800 Po 0 50189 31142 49768 31142 39 -1 @@ -12592,746 +12588,934 @@ Po 3 50685 31067 50685 31067 157 -1 De 15 1 7 0 0 Po 0 50688 31064 50685 31067 39 -1 De 15 0 7 0 0 -Po 0 47937 31338 47294 31338 39 -1 -De 0 0 8 0 800 -Po 0 47020 31064 46643 31064 39 -1 -De 15 0 8 0 400 -Po 0 47110 31154 47020 31064 39 -1 -De 15 0 8 0 0 -Po 3 47110 31154 47110 31154 157 -1 -De 15 1 8 0 0 -Po 0 47294 31338 47110 31154 39 -1 -De 0 0 8 0 0 Po 0 47937 31142 47417 31142 39 -1 -De 0 0 9 0 800 +De 0 0 8 0 800 Po 0 47239 31320 46643 31320 39 -1 -De 15 0 9 0 400 +De 15 0 8 0 400 Po 0 47417 31142 47239 31320 39 -1 -De 15 0 9 0 0 +De 15 0 8 0 0 Po 3 47417 31142 47417 31142 157 -1 +De 15 1 8 0 0 +Po 0 47941 32527 47256 32527 39 -1 +De 0 0 9 0 800 +Po 0 46883 31832 46643 31832 39 -1 +De 15 0 9 0 400 +Po 0 46980 31929 46883 31832 39 -1 +De 15 0 9 0 0 +Po 3 46980 31929 46980 31929 157 -1 De 15 1 9 0 0 -Po 0 47937 30945 47646 30945 39 -1 -De 0 0 10 0 800 -Po 0 47417 31576 46643 31576 39 -1 -De 15 0 10 0 400 -Po 0 47575 31418 47417 31576 39 -1 -De 15 0 10 0 0 -Po 0 47575 31016 47575 31418 39 -1 -De 15 0 10 0 0 -Po 0 47646 30945 47575 31016 39 -1 -De 15 0 10 0 0 -Po 3 47646 30945 47646 30945 157 -1 -De 15 1 10 0 0 +Po 0 46980 32251 46980 31929 39 -1 +De 0 0 9 0 0 +Po 0 47256 32527 46980 32251 39 -1 +De 0 0 9 0 0 Po 0 47941 32330 47353 32330 39 -1 -De 0 0 11 0 800 +De 0 0 10 0 800 Po 0 47111 32088 46643 32088 39 -1 -De 15 0 11 0 400 +De 15 0 10 0 400 Po 0 47165 32142 47111 32088 39 -1 -De 15 0 11 0 0 +De 15 0 10 0 0 Po 3 47165 32142 47165 32142 157 -1 -De 15 1 11 0 0 +De 15 1 10 0 0 Po 0 47353 32330 47165 32142 39 -1 -De 0 0 11 0 0 -Po 0 50995 32344 50017 32344 39 -1 -De 15 0 12 0 800 -Po 0 49988 32315 49775 32315 39 -1 -De 0 0 12 0 400 -Po 0 50016 32343 49988 32315 39 -1 -De 0 0 12 0 0 -Po 3 50016 32343 50016 32343 157 -1 -De 15 1 12 0 0 -Po 0 50017 32344 50016 32343 39 -1 -De 15 0 12 0 0 +De 0 0 10 0 0 Po 0 50995 32088 50706 32088 39 -1 -De 15 0 13 0 800 +De 15 0 11 0 800 Po 0 50657 32119 49775 32119 39 -1 -De 0 0 13 0 400 +De 0 0 11 0 400 Po 0 50697 32079 50657 32119 39 -1 -De 0 0 13 0 0 +De 0 0 11 0 0 Po 3 50697 32079 50697 32079 157 -1 -De 15 1 13 0 0 +De 15 1 11 0 0 Po 0 50706 32088 50697 32079 39 -1 +De 15 0 11 0 0 +Po 0 46643 33367 47765 33367 39 -1 +De 15 0 12 0 800 +Po 0 48072 33189 48151 33268 39 -1 +De 0 0 12 0 400 +Po 0 47933 33189 48072 33189 39 -1 +De 0 0 12 0 0 +Po 0 47923 33199 47933 33189 39 -1 +De 0 0 12 0 0 +Po 3 47923 33199 47923 33199 157 -1 +De 15 1 12 0 0 +Po 0 47923 33209 47923 33199 39 -1 +De 15 0 12 0 0 +Po 0 47765 33367 47923 33209 39 -1 +De 15 0 12 0 0 +Po 0 50995 37972 50141 37972 39 -1 +De 15 0 13 0 800 +Po 0 50058 37889 49838 37889 39 -1 +De 0 0 13 0 400 +Po 0 50071 37902 50058 37889 39 -1 +De 0 0 13 0 0 +Po 3 50071 37902 50071 37902 157 -1 +De 15 1 13 0 0 +Po 0 50141 37972 50071 37902 39 -1 De 15 0 13 0 0 -Po 0 50995 33367 50298 33367 39 -1 -De 15 0 14 0 800 -Po 0 50039 33626 49795 33626 39 -1 -De 0 0 14 0 400 -Po 0 50055 33610 50039 33626 39 -1 -De 0 0 14 0 0 -Po 3 50055 33610 50055 33610 157 -1 -De 15 1 14 0 0 -Po 0 50298 33367 50055 33610 39 -1 +Po 0 47351 36590 47209 36590 39 -1 +De 0 0 14 0 800 +Po 0 46850 36949 46643 36949 39 -1 +De 15 0 14 0 400 +Po 0 47000 36799 46850 36949 39 -1 De 15 0 14 0 0 -Po 0 49838 37693 50661 37693 39 -1 -De 0 0 15 0 800 -Po 0 50684 37716 50995 37716 39 -1 -De 15 0 15 0 400 -Po 0 50661 37693 50684 37716 39 -1 -De 15 0 15 0 0 -Po 3 50661 37693 50661 37693 157 -1 +Po 3 47000 36799 47000 36799 157 -1 +De 15 1 14 0 0 +Po 0 47209 36590 47000 36799 39 -1 +De 0 0 14 0 0 +Po 0 46643 37204 46900 37204 39 -1 +De 15 0 15 0 800 +Po 0 47188 37492 47362 37492 39 -1 +De 0 0 15 0 400 +Po 0 47035 37339 47188 37492 39 -1 +De 0 0 15 0 0 +Po 3 47035 37339 47035 37339 157 -1 De 15 1 15 0 0 -Po 0 49846 36535 49976 36535 39 -1 +Po 0 46900 37204 47035 37339 39 -1 +De 15 0 15 0 0 +Po 0 49846 36142 50666 36142 39 -1 De 0 0 16 0 800 -Po 0 50709 36949 50995 36949 39 -1 +Po 0 50705 36181 50995 36181 39 -1 De 15 0 16 0 400 -Po 0 50689 36929 50709 36949 39 -1 +Po 0 50685 36161 50705 36181 39 -1 De 15 0 16 0 0 -Po 3 50689 36929 50689 36929 157 -1 +Po 3 50685 36161 50685 36161 157 -1 De 15 1 16 0 0 -Po 0 50370 36929 50689 36929 39 -1 +Po 0 50666 36142 50685 36161 39 -1 De 0 0 16 0 0 -Po 0 49976 36535 50370 36929 39 -1 -De 0 0 16 0 0 -Po 0 49846 36338 50056 36338 39 -1 +Po 0 49846 35945 50071 35945 39 -1 De 0 0 17 0 800 -Po 0 50161 36437 50995 36437 39 -1 +Po 0 50347 35669 50995 35669 39 -1 De 15 0 17 0 400 -Po 0 50059 36335 50161 36437 39 -1 +Po 0 50071 35945 50347 35669 39 -1 De 15 0 17 0 0 -Po 3 50059 36335 50059 36335 157 -1 +Po 3 50071 35945 50071 35945 157 -1 De 15 1 17 0 0 -Po 0 50056 36338 50059 36335 39 -1 -De 0 0 17 0 0 -Po 0 50995 33879 50672 33879 39 -1 +Po 0 46643 35669 46826 35669 39 -1 De 15 0 18 0 800 -Po 0 50532 34019 49795 34019 39 -1 +Po 0 47157 36000 47351 36000 39 -1 De 0 0 18 0 400 -Po 0 50610 33941 50532 34019 39 -1 +Po 0 47035 35878 47157 36000 39 -1 De 0 0 18 0 0 -Po 3 50610 33941 50610 33941 157 -1 +Po 3 47035 35878 47035 35878 157 -1 De 15 1 18 0 0 -Po 0 50672 33879 50610 33941 39 -1 +Po 0 46826 35669 47035 35878 39 -1 De 15 0 18 0 0 -Po 0 50995 34901 50688 34901 39 -1 -De 15 0 19 0 800 -Po 0 50003 34216 49795 34216 39 -1 -De 0 0 19 0 400 -Po 0 50681 34894 50003 34216 39 -1 -De 0 0 19 0 0 -Po 3 50681 34894 50681 34894 157 -1 -De 15 1 19 0 0 -Po 0 50688 34901 50681 34894 39 -1 +Po 0 47351 36197 47031 36197 39 -1 +De 0 0 19 0 800 +Po 0 47015 36181 46643 36181 39 -1 +De 15 0 19 0 400 +Po 0 47031 36197 47015 36181 39 -1 De 15 0 19 0 0 -Po 0 46643 34391 47017 34391 79 -1 -De 15 0 20 0 800 -Po 0 47265 34290 47265 34154 79 -1 -De 0 0 20 0 400 -Po 0 47165 34390 47265 34290 79 -1 -De 0 0 20 0 0 -Po 0 47018 34390 47165 34390 79 -1 -De 0 0 20 0 0 -Po 3 47018 34390 47018 34390 157 -1 -De 15 1 20 0 0 -Po 0 47017 34391 47018 34390 79 -1 +Po 3 47031 36197 47031 36197 157 -1 +De 15 1 19 0 0 +Po 0 49775 32512 49858 32512 39 -1 +De 0 0 20 0 800 +Po 0 50457 33111 50995 33111 39 -1 +De 15 0 20 0 400 +Po 0 50039 32693 50457 33111 39 -1 De 15 0 20 0 0 +Po 3 50039 32693 50039 32693 157 -1 +De 15 1 20 0 0 +Po 0 49858 32512 50039 32693 39 -1 +De 0 0 20 0 0 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53512 33591 53512 33591 157 -1 -De 15 1 170 0 0 +De 15 1 168 0 0 Po 0 53512 33591 53709 33788 39 -1 -De 15 0 170 0 0 +De 15 0 168 0 0 Po 0 53709 33788 53711 33788 39 -1 -De 15 0 170 0 400 +De 15 0 168 0 400 Po 0 53307 33386 53512 33591 39 -1 -De 0 0 170 0 0 +De 0 0 168 0 0 Po 0 52536 33386 53307 33386 39 -1 -De 0 0 170 0 0 +De 0 0 168 0 0 Po 0 52323 33173 52536 33386 39 -1 -De 0 0 170 0 0 +De 0 0 168 0 0 Po 0 51846 33173 52323 33173 39 -1 -De 0 0 170 0 0 +De 0 0 168 0 0 Po 3 51846 33173 51846 33173 157 -1 -De 15 1 170 0 0 +De 15 1 168 0 0 Po 0 51747 33173 51846 33173 39 -1 -De 3 0 170 0 0 +De 3 0 168 0 0 Po 0 51487 32913 51747 33173 39 -1 -De 3 0 170 0 0 +De 3 0 168 0 0 Po 0 50000 32913 51487 32913 39 -1 -De 3 0 170 0 0 +De 3 0 168 0 0 Po 0 49815 32728 50000 32913 39 -1 -De 3 0 170 0 0 +De 3 0 168 0 0 Po 0 49141 32728 49815 32728 39 -1 -De 3 0 170 0 0 +De 3 0 168 0 0 Po 0 49051 32638 49141 32728 39 -1 -De 3 0 170 0 0 +De 3 0 168 0 0 Po 3 49051 32638 49051 32638 157 -1 -De 15 1 170 0 0 +De 15 1 168 0 0 Po 0 49177 32512 49051 32638 39 -1 -De 0 0 170 0 0 +De 0 0 168 0 0 Po 0 52327 32433 52330 32433 39 -1 -De 0 0 173 0 0 +De 0 0 171 0 0 Po 0 48937 33823 48854 33740 39 -1 -De 0 0 173 0 0 +De 0 0 171 0 0 Po 0 48854 33740 48854 33563 39 -1 -De 0 0 173 0 0 +De 0 0 171 0 0 Po 0 48854 33563 48976 33441 39 -1 -De 0 0 173 0 0 +De 0 0 171 0 0 Po 0 48976 33441 50527 33441 39 -1 -De 0 0 173 0 0 +De 0 0 171 0 0 Po 0 50527 33441 50941 33027 39 -1 -De 0 0 173 0 0 +De 0 0 171 0 0 Po 0 50941 33027 51733 33027 39 -1 -De 0 0 173 0 0 +De 0 0 171 0 0 Po 0 51733 33027 52327 32433 39 -1 -De 0 0 173 0 0 +De 0 0 171 0 0 Po 0 49441 33823 48937 33823 39 -1 -De 0 0 173 0 800 +De 0 0 171 0 800 Po 0 52550 32213 52530 32213 39 -1 -De 15 0 173 0 400 +De 15 0 171 0 400 Po 0 52732 32031 52550 32213 39 -1 -De 15 0 173 0 0 +De 15 0 171 0 0 Po 3 52732 32031 52732 32031 157 -1 -De 15 1 173 0 0 +De 15 1 171 0 0 Po 0 52330 32433 52732 32031 39 -1 -De 0 0 173 0 0 +De 0 0 171 0 0 Po 0 52516 32213 52530 32213 39 -1 -De 15 0 173 0 400 +De 15 0 171 0 400 Po 0 55286 30639 55286 30631 79 -1 De 15 0 231 0 800 Po 3 55098 30443 55098 30443 157 -1 diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index e186d03..5a9d608 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,4 +1,4 @@ -# EESchema Netlist Version 1.1 created Sat 21 Aug 2010 06:47:10 AM COT +# EESchema Netlist Version 1.1 created Sat 21 Aug 2010 04:30:32 PM COT ( ( /4C69ED5F/4C6D2FD7 0805 C82 4.7uF {Lib=CAP} ( 1 N-000434 ) @@ -137,10 +137,10 @@ ( COM GND ) ( CD ? ) ( 1 /Non_volatile_memories/SD_DAT2 ) - ( 2 /FPGA_Spartan6/SD_DAT3 ) + ( 2 /Non_volatile_memories/SD_DAT3 ) ( 3 /FPGA_Spartan6/SD_CMD ) ( 4 +3.3V ) - ( 5 /Non_volatile_memories/SD_CLK ) + ( 5 /FPGA_Spartan6/SD_CLK ) ( 6 GND ) ( 7 /FPGA_Spartan6/SD_DAT0 ) ( 8 /Non_volatile_memories/SD_DAT1 ) @@ -151,8 +151,8 @@ ( 3 ? ) ( 4 ? ) ( 5 ? ) - ( 6 /FPGA_Spartan6/NF_RNB ) - ( 7 /FPGA_Spartan6/NF_RNB ) + ( 6 /Non_volatile_memories/NF_RNB ) + ( 7 /Non_volatile_memories/NF_RNB ) ( 8 /Non_volatile_memories/NF_RE_N ) ( 9 /Non_volatile_memories/NF_CS1_N ) ( 10 ? ) @@ -161,8 +161,8 @@ ( 13 GND ) ( 14 ? ) ( 15 ? ) - ( 16 /FPGA_Spartan6/NF_CLE ) - ( 17 /FPGA_Spartan6/NF_ALE ) + ( 16 /Non_volatile_memories/NF_CLE ) + ( 17 /Non_volatile_memories/NF_ALE ) ( 18 /Non_volatile_memories/NF_WE_N ) ( 19 +3.3V ) ( 20 ? ) @@ -175,9 +175,9 @@ ( 27 ? ) ( 28 ? ) ( 29 /Non_volatile_memories/NF_D0 ) - ( 30 /Non_volatile_memories/NF_D1 ) + ( 30 /FPGA_Spartan6/NF_D1 ) ( 31 /FPGA_Spartan6/NF_D2 ) - ( 32 /FPGA_Spartan6/NF_D3 ) + ( 32 /Non_volatile_memories/NF_D3 ) ( 33 ? ) ( 34 ? ) ( 35 ? ) @@ -187,9 +187,9 @@ ( 39 ? ) ( 40 ? ) ( 41 /FPGA_Spartan6/NF_D4 ) - ( 42 /Non_volatile_memories/NF_D5 ) - ( 43 /Non_volatile_memories/NF_D6 ) - ( 44 /FPGA_Spartan6/NF_D7 ) + ( 42 /FPGA_Spartan6/NF_D5 ) + ( 43 /FPGA_Spartan6/NF_D6 ) + ( 44 /Non_volatile_memories/NF_D7 ) ( 45 ? ) ( 46 ? ) ( 47 ? ) @@ -301,13 +301,13 @@ ) ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) - ( 2 /USB/USBA_SPD ) - ( 3 /USB/USBA_RCV ) + ( 2 /FPGA_Spartan6/USBA_SPD ) + ( 3 /FPGA_Spartan6/USBA_RCV ) ( 4 /USB/USBA_VP ) - ( 5 /FPGA_Spartan6/USBA_VM ) + ( 5 /USB/USBA_VM ) ( 7 GND ) ( 8 GND ) - ( 9 /FPGA_Spartan6/USBA_OE_N ) + ( 9 /USB/USBA_OE_N ) ( 10 N-000426 ) ( 11 N-000430 ) ( 12 +3.3V ) @@ -327,11 +327,11 @@ ) ( /4C431A63/4C6B216D 0402 R22 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M0_UDQS ) - ( 2 /FPGA_Spartan6/M0_UDQS ) + ( 2 /DDR_Banks/M0_UDQS ) ) ( /4C431A63/4C6B216B 0402 R24 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M0_CKE ) - ( 2 /FPGA_Spartan6/M0_CKE ) + ( 2 /DDR_Banks/M0_CKE ) ) ( /4C431A63/4C6B1B90 0402 R21 120 {Lib=R} ( 1 /FPGA_Spartan6/M0_CLK ) @@ -345,7 +345,7 @@ ( 5 /FPGA_Spartan6/M0_A3 ) ( 6 /DDR_Banks/M0_A2 ) ( 7 /FPGA_Spartan6/M0_A1 ) - ( 8 /DDR_Banks/M0_A0 ) + ( 8 /FPGA_Spartan6/M0_A0 ) ) ( /4C431A63/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_RAS# ) @@ -354,18 +354,18 @@ ( 4 /FPGA_Spartan6/R_M0_A10 ) ( 5 /FPGA_Spartan6/M0_A10 ) ( 6 /DDR_Banks/M0_BA1 ) - ( 7 /DDR_Banks/M0_BA0 ) - ( 8 /FPGA_Spartan6/M0_RAS# ) + ( 7 /FPGA_Spartan6/M0_BA0 ) + ( 8 /DDR_Banks/M0_RAS# ) ) ( /4C431A63/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_LDQS ) ( 2 /FPGA_Spartan6/R_M0_LDM ) ( 3 /FPGA_Spartan6/R_M0_WE# ) ( 4 /FPGA_Spartan6/R_M0_CAS# ) - ( 5 /DDR_Banks/M0_CAS# ) - ( 6 /DDR_Banks/M0_WE# ) - ( 7 /DDR_Banks/M0_LDM ) - ( 8 /DDR_Banks/M0_LDQS ) + ( 5 /FPGA_Spartan6/M0_CAS# ) + ( 6 /FPGA_Spartan6/M0_WE# ) + ( 7 /FPGA_Spartan6/M0_LDM ) + ( 8 /FPGA_Spartan6/M0_LDQS ) ) ( /4C431A63/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_A7 ) @@ -373,18 +373,18 @@ ( 3 /FPGA_Spartan6/R_M0_A5 ) ( 4 /FPGA_Spartan6/R_M0_A4 ) ( 5 /FPGA_Spartan6/M0_A4 ) - ( 6 /DDR_Banks/M0_A5 ) + ( 6 /FPGA_Spartan6/M0_A5 ) ( 7 /DDR_Banks/M0_A6 ) - ( 8 /DDR_Banks/M0_A7 ) + ( 8 /FPGA_Spartan6/M0_A7 ) ) ( /4C431A63/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_A12 ) ( 2 /FPGA_Spartan6/R_M0_A11 ) ( 3 /FPGA_Spartan6/R_M0_A9 ) ( 4 /FPGA_Spartan6/R_M0_A8 ) - ( 5 /FPGA_Spartan6/M0_A8 ) + ( 5 /DDR_Banks/M0_A8 ) ( 6 /DDR_Banks/M0_A9 ) - ( 7 /FPGA_Spartan6/M0_A11 ) + ( 7 /DDR_Banks/M0_A11 ) ( 8 /FPGA_Spartan6/M0_A12 ) ) ( /4C431A63/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4} @@ -392,10 +392,10 @@ ( 2 /FPGA_Spartan6/R_M0_DQ5 ) ( 3 /FPGA_Spartan6/R_M0_DQ6 ) ( 4 /FPGA_Spartan6/R_M0_DQ7 ) - ( 5 /FPGA_Spartan6/M0_DQ7 ) - ( 6 /FPGA_Spartan6/M0_DQ6 ) - ( 7 /DDR_Banks/M0_DQ5 ) - ( 8 /DDR_Banks/M0_DQ4 ) + ( 5 /DDR_Banks/M0_DQ7 ) + ( 6 /DDR_Banks/M0_DQ6 ) + ( 7 /FPGA_Spartan6/M0_DQ5 ) + ( 8 /FPGA_Spartan6/M0_DQ4 ) ) ( /4C431A63/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_DQ0 ) @@ -403,8 +403,8 @@ ( 3 /FPGA_Spartan6/R_M0_DQ2 ) ( 4 /FPGA_Spartan6/R_M0_DQ3 ) ( 5 /FPGA_Spartan6/M0_DQ3 ) - ( 6 /DDR_Banks/M0_DQ2 ) - ( 7 /FPGA_Spartan6/M0_DQ1 ) + ( 6 /FPGA_Spartan6/M0_DQ2 ) + ( 7 /DDR_Banks/M0_DQ1 ) ( 8 /FPGA_Spartan6/M0_DQ0 ) ) ( /4C431A63/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4} @@ -412,10 +412,10 @@ ( 2 /FPGA_Spartan6/R_M0_DQ9 ) ( 3 /FPGA_Spartan6/R_M0_DQ10 ) ( 4 /FPGA_Spartan6/R_M0_DQ11 ) - ( 5 /FPGA_Spartan6/M0_DQ11 ) + ( 5 /DDR_Banks/M0_DQ11 ) ( 6 /FPGA_Spartan6/M0_DQ10 ) - ( 7 /FPGA_Spartan6/M0_DQ9 ) - ( 8 /FPGA_Spartan6/M0_DQ8 ) + ( 7 /DDR_Banks/M0_DQ9 ) + ( 8 /DDR_Banks/M0_DQ8 ) ) ( /4C431A63/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_DQ12 ) @@ -425,15 +425,15 @@ ( 5 /FPGA_Spartan6/M0_DQ15 ) ( 6 /FPGA_Spartan6/M0_DQ14 ) ( 7 /FPGA_Spartan6/M0_DQ13 ) - ( 8 /FPGA_Spartan6/M0_DQ12 ) + ( 8 /DDR_Banks/M0_DQ12 ) ) ( /4C431A63/4C69E7DD 0402 R19 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_UDQS ) - ( 2 /DDR_Banks/M1_UDQS ) + ( 2 /FPGA_Spartan6/M1_UDQS ) ) ( /4C431A63/4C69E92D 0402 R20 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CS# ) - ( 2 /DDR_Banks/M1_CS# ) + ( 2 /FPGA_Spartan6/M1_CS# ) ) ( /4C431A63/4C69E7F8 0402 R17 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CKE ) @@ -450,7 +450,7 @@ ( 4 /FPGA_Spartan6/R_M1_DQ8 ) ( 5 /FPGA_Spartan6/M1_DQ8 ) ( 6 /FPGA_Spartan6/M1_DQ9 ) - ( 7 /FPGA_Spartan6/M1_DQ10 ) + ( 7 /DDR_Banks/M1_DQ10 ) ( 8 /DDR_Banks/M1_DQ11 ) ) ( /4C431A63/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} @@ -458,14 +458,14 @@ ( 2 /FPGA_Spartan6/R_M1_DQ14 ) ( 3 /FPGA_Spartan6/R_M1_DQ13 ) ( 4 /FPGA_Spartan6/R_M1_DQ12 ) - ( 5 /DDR_Banks/M1_DQ12 ) + ( 5 /FPGA_Spartan6/M1_DQ12 ) ( 6 /FPGA_Spartan6/M1_DQ13 ) ( 7 /FPGA_Spartan6/M1_DQ14 ) - ( 8 /DDR_Banks/M1_DQ15 ) + ( 8 /FPGA_Spartan6/M1_DQ15 ) ) ( /4C431A63/4C69DF7A 0402 R16 120 {Lib=R} - ( 1 /DDR_Banks/M1_CLK# ) - ( 2 /DDR_Banks/M1_CLK ) + ( 1 /FPGA_Spartan6/M1_CLK# ) + ( 2 /FPGA_Spartan6/M1_CLK ) ) ( /4C431A63/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A12 ) @@ -475,7 +475,7 @@ ( 5 /DDR_Banks/M1_A8 ) ( 6 /FPGA_Spartan6/M1_A9 ) ( 7 /DDR_Banks/M1_A11 ) - ( 8 /FPGA_Spartan6/M1_A12 ) + ( 8 /DDR_Banks/M1_A12 ) ) ( /4C431A63/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A7 ) @@ -483,9 +483,9 @@ ( 3 /FPGA_Spartan6/R_M1_A5 ) ( 4 ? ) ( 5 /FPGA_Spartan6/M1_A4 ) - ( 6 /FPGA_Spartan6/M1_A5 ) + ( 6 /DDR_Banks/M1_A5 ) ( 7 /FPGA_Spartan6/M1_A6 ) - ( 8 /DDR_Banks/M1_A7 ) + ( 8 /FPGA_Spartan6/M1_A7 ) ) ( /4C431A63/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ0 ) @@ -494,7 +494,7 @@ ( 4 /FPGA_Spartan6/R_M1_DQ3 ) ( 5 /FPGA_Spartan6/M1_DQ3 ) ( 6 /FPGA_Spartan6/M1_DQ2 ) - ( 7 /DDR_Banks/M1_DQ1 ) + ( 7 /FPGA_Spartan6/M1_DQ1 ) ( 8 /FPGA_Spartan6/M1_DQ0 ) ) ( /4C431A63/4C69D3A4 $noname RP3 R_PACK4 {Lib=R_PACK4} @@ -502,10 +502,10 @@ ( 2 /FPGA_Spartan6/R_M1_LDM ) ( 3 /FPGA_Spartan6/R_M1_WE# ) ( 4 /FPGA_Spartan6/R_M1_CAS# ) - ( 5 /FPGA_Spartan6/M1_CAS# ) - ( 6 /DDR_Banks/M1_WE# ) - ( 7 /FPGA_Spartan6/M1_LDM ) - ( 8 /FPGA_Spartan6/M1_LDQS ) + ( 5 /DDR_Banks/M1_CAS# ) + ( 6 /FPGA_Spartan6/M1_WE# ) + ( 7 /DDR_Banks/M1_LDM ) + ( 8 /DDR_Banks/M1_LDQS ) ) ( /4C431A63/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ4 ) @@ -513,7 +513,7 @@ ( 3 /FPGA_Spartan6/R_M1_DQ6 ) ( 4 /FPGA_Spartan6/R_M1_DQ7 ) ( 5 /FPGA_Spartan6/M1_DQ7 ) - ( 6 /DDR_Banks/M1_DQ6 ) + ( 6 /FPGA_Spartan6/M1_DQ6 ) ( 7 /FPGA_Spartan6/M1_DQ5 ) ( 8 /DDR_Banks/M1_DQ4 ) ) @@ -523,7 +523,7 @@ ( 3 /FPGA_Spartan6/R_M1_BA1 ) ( 4 /FPGA_Spartan6/R_M1_A10 ) ( 5 /FPGA_Spartan6/M1_A10 ) - ( 6 /DDR_Banks/M1_BA1 ) + ( 6 /FPGA_Spartan6/M1_BA1 ) ( 7 /FPGA_Spartan6/M1_BA0 ) ( 8 /FPGA_Spartan6/M1_RAS# ) ) @@ -532,8 +532,8 @@ ( 2 /FPGA_Spartan6/R_M1_A1 ) ( 3 /FPGA_Spartan6/R_M1_A2 ) ( 4 /FPGA_Spartan6/R_M1_A3 ) - ( 5 /FPGA_Spartan6/M1_A3 ) - ( 6 /FPGA_Spartan6/M1_A2 ) + ( 5 /DDR_Banks/M1_A3 ) + ( 6 /DDR_Banks/M1_A2 ) ( 7 /FPGA_Spartan6/M1_A1 ) ( 8 /DDR_Banks/M1_A0 ) ) @@ -711,7 +711,7 @@ ( L20 /FPGA_Spartan6/R_M1_LDQS ) ( K20 /FPGA_Spartan6/R_M1_A5 ) ( J20 /FPGA_Spartan6/R_M1_DQ4 ) - ( H20 /DDR_Banks/M1_CLK ) + ( H20 /FPGA_Spartan6/M1_CLK ) ( G20 /FPGA_Spartan6/R_M1_A3 ) ( F20 ? ) ( E20 /FPGA_Spartan6/R_M1_A7 ) @@ -784,15 +784,15 @@ ( C3 ? ) ( B3 ? ) ( G10 +3.3V ) - ( D10 /Ethernet_Phy/ETH_TXD1 ) - ( C10 /Ethernet_Phy/ETH_CRS ) - ( B10 /Ethernet_Phy/ETH_COL ) - ( A10 /Ethernet_Phy/ETH_INT ) + ( D10 /FPGA_Spartan6/ETH_TXD0 ) + ( C10 /FPGA_Spartan6/ETH_TXD2 ) + ( B10 /FPGA_Spartan6/ETH_CRS ) + ( A10 /FPGA_Spartan6/ETH_INT ) ( E9 +3.3V ) - ( D9 /FPGA_Spartan6/ETH_TXEN ) - ( C9 /Ethernet_Phy/ETH_TXD2 ) - ( A9 /Ethernet_Phy/ETH_TXD0 ) - ( D8 /FPGA_Spartan6/ETH_TXER ) + ( D9 /Ethernet_Phy/ETH_TXEN ) + ( C9 /FPGA_Spartan6/ETH_TXD1 ) + ( A9 /FPGA_Spartan6/ETH_COL ) + ( D8 /Ethernet_Phy/ETH_TXER ) ( C8 /FPGA_Spartan6/ETH_TXC ) ( B8 /Ethernet_Phy/ETH_RXER ) ( A8 /FPGA_Spartan6/ETH_TXD3 ) @@ -803,31 +803,31 @@ ( D6 /FPGA_Spartan6/ETH_MDIO ) ( C6 /FPGA_Spartan6/ETH_RXD2 ) ( B6 /Ethernet_Phy/ETH_RXD0 ) - ( A6 /Ethernet_Phy/ETH_RXDV ) - ( C5 /Ethernet_Phy/ETH_RXD3 ) - ( A5 /FPGA_Spartan6/ETH_RXD1 ) + ( A6 /FPGA_Spartan6/ETH_RXDV ) + ( C5 /FPGA_Spartan6/ETH_RXD3 ) + ( A5 /Ethernet_Phy/ETH_RXD1 ) ( B4 +3.3V ) - ( A4 /Ethernet_Phy/ETH_CLK ) + ( A4 /FPGA_Spartan6/ETH_CLK ) ( A3 ? ) ( U19 ? ) ( T19 ? ) - ( R19 /USB/USBA_SPD ) + ( R19 /FPGA_Spartan6/USBA_SPD ) ( P19 ? ) ( B19 +3.3V ) ( B18 /Non_volatile_memories/SD_DAT1 ) ( A18 /FPGA_Spartan6/SD_DAT0 ) ( E17 +3.3V ) ( D17 /FPGA_Spartan6/SD_CMD ) - ( C17 /FPGA_Spartan6/SD_DAT3 ) + ( C17 /Non_volatile_memories/SD_DAT3 ) ( A17 /Non_volatile_memories/SD_DAT2 ) - ( E16 /Non_volatile_memories/SD_CLK ) + ( E16 /FPGA_Spartan6/SD_CLK ) ( C16 /Non_volatile_memories/NF_CS1_N ) ( B16 /Non_volatile_memories/NF_RE_N ) - ( A16 /FPGA_Spartan6/NF_RNB ) - ( D15 /FPGA_Spartan6/NF_CLE ) + ( A16 /Non_volatile_memories/NF_RNB ) + ( D15 /Non_volatile_memories/NF_CLE ) ( C15 /Non_volatile_memories/NF_WE_N ) ( B15 +3.3V ) - ( A15 /FPGA_Spartan6/NF_ALE ) + ( A15 /Non_volatile_memories/NF_ALE ) ( G14 +3.3V ) ( D14 /Non_volatile_memories/NF_D0 ) ( C14 ? ) @@ -835,14 +835,14 @@ ( A14 ? ) ( E13 +3.3V ) ( C13 /FPGA_Spartan6/NF_D2 ) - ( A13 /Non_volatile_memories/NF_D1 ) - ( C12 /Non_volatile_memories/NF_D5 ) + ( A13 /FPGA_Spartan6/NF_D1 ) + ( C12 /FPGA_Spartan6/NF_D5 ) ( B12 /FPGA_Spartan6/NF_D4 ) - ( A12 /FPGA_Spartan6/NF_D3 ) - ( D11 /Non_volatile_memories/NF_D6 ) + ( A12 /Non_volatile_memories/NF_D3 ) + ( D11 /FPGA_Spartan6/NF_D6 ) ( C11 ? ) ( B11 +3.3V ) - ( A11 /FPGA_Spartan6/NF_D7 ) + ( A11 /Non_volatile_memories/NF_D7 ) ( J16 ? ) ( H16 /FPGA_Spartan6/R_M1_CS# ) ( G16 ? ) @@ -877,7 +877,7 @@ ( M19 ? ) ( L19 /FPGA_Spartan6/R_M1_LDM ) ( K19 /FPGA_Spartan6/R_M1_A6 ) - ( J19 /DDR_Banks/M1_CLK# ) + ( J19 /FPGA_Spartan6/M1_CLK# ) ( H19 /FPGA_Spartan6/R_M1_WE# ) ( G19 /FPGA_Spartan6/R_M1_A10 ) ( F19 /FPGA_Spartan6/R_M1_A11 ) @@ -885,9 +885,9 @@ ( D19 ? ) ( C19 ? ) ( U18 +2.5V ) - ( P18 /FPGA_Spartan6/USBA_OE_N ) + ( P18 /USB/USBA_OE_N ) ( N18 +2.5V ) - ( M18 /FPGA_Spartan6/USBA_VM ) + ( M18 /USB/USBA_VM ) ( K18 ? ) ( J18 +2.5V ) ( H18 ? ) @@ -900,7 +900,7 @@ ( H17 ? ) ( G17 ? ) ( F17 ? ) - ( N16 /USB/USBA_RCV ) + ( N16 /FPGA_Spartan6/USBA_RCV ) ( M16 ? ) ( L16 +2.5V ) ( K16 ? ) @@ -1222,29 +1222,29 @@ ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} ( 1 /FPGA_Spartan6/ETH_MDIO ) ( 2 /FPGA_Spartan6/ETH_MDC ) - ( 3 /Ethernet_Phy/ETH_RXD3 ) + ( 3 /FPGA_Spartan6/ETH_RXD3 ) ( 4 /FPGA_Spartan6/ETH_RXD2 ) - ( 5 /FPGA_Spartan6/ETH_RXD1 ) + ( 5 /Ethernet_Phy/ETH_RXD1 ) ( 6 /Ethernet_Phy/ETH_RXD0 ) ( 7 +3.3V ) ( 8 GND ) - ( 9 /Ethernet_Phy/ETH_RXDV ) + ( 9 /FPGA_Spartan6/ETH_RXDV ) ( 10 /Ethernet_Phy/ETH_RXC ) ( 11 /Ethernet_Phy/ETH_RXER ) ( 12 GND ) ( 13 +1.8V ) - ( 14 /FPGA_Spartan6/ETH_TXER ) + ( 14 /Ethernet_Phy/ETH_TXER ) ( 15 /FPGA_Spartan6/ETH_TXC ) - ( 16 /FPGA_Spartan6/ETH_TXEN ) - ( 17 /Ethernet_Phy/ETH_TXD0 ) - ( 18 /Ethernet_Phy/ETH_TXD1 ) - ( 19 /Ethernet_Phy/ETH_TXD2 ) + ( 16 /Ethernet_Phy/ETH_TXEN ) + ( 17 /FPGA_Spartan6/ETH_TXD0 ) + ( 18 /FPGA_Spartan6/ETH_TXD1 ) + ( 19 /FPGA_Spartan6/ETH_TXD2 ) ( 20 /FPGA_Spartan6/ETH_TXD3 ) - ( 21 /Ethernet_Phy/ETH_COL ) - ( 22 /Ethernet_Phy/ETH_CRS ) + ( 21 /FPGA_Spartan6/ETH_COL ) + ( 22 /FPGA_Spartan6/ETH_CRS ) ( 23 GND ) ( 24 +3.3V ) - ( 25 /Ethernet_Phy/ETH_INT ) + ( 25 /FPGA_Spartan6/ETH_INT ) ( 26 /Ethernet_Phy/ETH_LED0 ) ( 27 /Ethernet_Phy/ETH_LED1 ) ( 28 ? ) @@ -1265,7 +1265,7 @@ ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 /Ethernet_Phy/ETH_CLK ) + ( 46 /FPGA_Spartan6/ETH_CLK ) ( 47 /Ethernet_Phy/ETH_PLL1.8V ) ( 48 /FPGA_Spartan6/ETH_RESET_N ) ) @@ -1313,68 +1313,68 @@ ( 1 +2.5V ) ( 2 /FPGA_Spartan6/M1_DQ0 ) ( 3 +2.5V ) - ( 4 /DDR_Banks/M1_DQ1 ) + ( 4 /FPGA_Spartan6/M1_DQ1 ) ( 5 /FPGA_Spartan6/M1_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M1_DQ3 ) ( 8 /DDR_Banks/M1_DQ4 ) ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M1_DQ5 ) - ( 11 /DDR_Banks/M1_DQ6 ) + ( 11 /FPGA_Spartan6/M1_DQ6 ) ( 12 GND ) ( 13 /FPGA_Spartan6/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /FPGA_Spartan6/M1_LDQS ) + ( 16 /DDR_Banks/M1_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Spartan6/M1_LDM ) - ( 21 /DDR_Banks/M1_WE# ) - ( 22 /FPGA_Spartan6/M1_CAS# ) + ( 20 /DDR_Banks/M1_LDM ) + ( 21 /FPGA_Spartan6/M1_WE# ) + ( 22 /DDR_Banks/M1_CAS# ) ( 23 /FPGA_Spartan6/M1_RAS# ) - ( 24 /DDR_Banks/M1_CS# ) + ( 24 /FPGA_Spartan6/M1_CS# ) ( 25 ? ) ( 26 /FPGA_Spartan6/M1_BA0 ) - ( 27 /DDR_Banks/M1_BA1 ) + ( 27 /FPGA_Spartan6/M1_BA1 ) ( 28 /FPGA_Spartan6/M1_A10 ) ( 29 /DDR_Banks/M1_A0 ) ( 30 /FPGA_Spartan6/M1_A1 ) - ( 31 /FPGA_Spartan6/M1_A2 ) - ( 32 /FPGA_Spartan6/M1_A3 ) + ( 31 /DDR_Banks/M1_A2 ) + ( 32 /DDR_Banks/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M1_A4 ) - ( 36 /FPGA_Spartan6/M1_A5 ) + ( 36 /DDR_Banks/M1_A5 ) ( 37 /FPGA_Spartan6/M1_A6 ) - ( 38 /DDR_Banks/M1_A7 ) + ( 38 /FPGA_Spartan6/M1_A7 ) ( 39 /DDR_Banks/M1_A8 ) ( 40 /FPGA_Spartan6/M1_A9 ) ( 41 /DDR_Banks/M1_A11 ) - ( 42 /FPGA_Spartan6/M1_A12 ) + ( 42 /DDR_Banks/M1_A12 ) ( 43 ? ) - ( 44 /DDR_Banks/M1_CLK# ) + ( 44 /FPGA_Spartan6/M1_CLK# ) ( 45 /FPGA_Spartan6/M1_CKE ) - ( 46 /DDR_Banks/M1_CLK ) + ( 46 /FPGA_Spartan6/M1_CLK ) ( 47 /DDR_Banks/M1_UDM ) ( 48 GND ) ( 49 /DDR_Banks/M1_VREF ) ( 50 ? ) - ( 51 /DDR_Banks/M1_UDQS ) + ( 51 /FPGA_Spartan6/M1_UDQS ) ( 52 GND ) ( 53 ? ) ( 54 /FPGA_Spartan6/M1_DQ8 ) ( 55 +2.5V ) ( 56 /FPGA_Spartan6/M1_DQ9 ) - ( 57 /FPGA_Spartan6/M1_DQ10 ) + ( 57 /DDR_Banks/M1_DQ10 ) ( 58 GND ) ( 59 /DDR_Banks/M1_DQ11 ) - ( 60 /DDR_Banks/M1_DQ12 ) + ( 60 /FPGA_Spartan6/M1_DQ12 ) ( 61 +2.5V ) ( 62 /FPGA_Spartan6/M1_DQ13 ) ( 63 /FPGA_Spartan6/M1_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M1_DQ15 ) + ( 65 /FPGA_Spartan6/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} @@ -1477,63 +1477,63 @@ ( 1 +2.5V ) ( 2 /FPGA_Spartan6/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M0_DQ1 ) - ( 5 /DDR_Banks/M0_DQ2 ) + ( 4 /DDR_Banks/M0_DQ1 ) + ( 5 /FPGA_Spartan6/M0_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M0_DQ3 ) - ( 8 /DDR_Banks/M0_DQ4 ) + ( 8 /FPGA_Spartan6/M0_DQ4 ) ( 9 +2.5V ) - ( 10 /DDR_Banks/M0_DQ5 ) - ( 11 /FPGA_Spartan6/M0_DQ6 ) + ( 10 /FPGA_Spartan6/M0_DQ5 ) + ( 11 /DDR_Banks/M0_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Spartan6/M0_DQ7 ) + ( 13 /DDR_Banks/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /DDR_Banks/M0_LDQS ) + ( 16 /FPGA_Spartan6/M0_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /DDR_Banks/M0_LDM ) - ( 21 /DDR_Banks/M0_WE# ) - ( 22 /DDR_Banks/M0_CAS# ) - ( 23 /FPGA_Spartan6/M0_RAS# ) + ( 20 /FPGA_Spartan6/M0_LDM ) + ( 21 /FPGA_Spartan6/M0_WE# ) + ( 22 /FPGA_Spartan6/M0_CAS# ) + ( 23 /DDR_Banks/M0_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 /DDR_Banks/M0_BA0 ) + ( 26 /FPGA_Spartan6/M0_BA0 ) ( 27 /DDR_Banks/M0_BA1 ) ( 28 /FPGA_Spartan6/M0_A10 ) - ( 29 /DDR_Banks/M0_A0 ) + ( 29 /FPGA_Spartan6/M0_A0 ) ( 30 /FPGA_Spartan6/M0_A1 ) ( 31 /DDR_Banks/M0_A2 ) ( 32 /FPGA_Spartan6/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M0_A4 ) - ( 36 /DDR_Banks/M0_A5 ) + ( 36 /FPGA_Spartan6/M0_A5 ) ( 37 /DDR_Banks/M0_A6 ) - ( 38 /DDR_Banks/M0_A7 ) - ( 39 /FPGA_Spartan6/M0_A8 ) + ( 38 /FPGA_Spartan6/M0_A7 ) + ( 39 /DDR_Banks/M0_A8 ) ( 40 /DDR_Banks/M0_A9 ) - ( 41 /FPGA_Spartan6/M0_A11 ) + ( 41 /DDR_Banks/M0_A11 ) ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) ( 44 /FPGA_Spartan6/M0_CLK# ) - ( 45 /FPGA_Spartan6/M0_CKE ) + ( 45 /DDR_Banks/M0_CKE ) ( 46 /FPGA_Spartan6/M0_CLK ) ( 47 /FPGA_Spartan6/M0_UDM ) ( 48 GND ) ( 49 /DDR_Banks/M0_VREF ) ( 50 ? ) - ( 51 /FPGA_Spartan6/M0_UDQS ) + ( 51 /DDR_Banks/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /FPGA_Spartan6/M0_DQ8 ) + ( 54 /DDR_Banks/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M0_DQ9 ) + ( 56 /DDR_Banks/M0_DQ9 ) ( 57 /FPGA_Spartan6/M0_DQ10 ) ( 58 GND ) - ( 59 /FPGA_Spartan6/M0_DQ11 ) - ( 60 /FPGA_Spartan6/M0_DQ12 ) + ( 59 /DDR_Banks/M0_DQ11 ) + ( 60 /DDR_Banks/M0_DQ12 ) ( 61 +2.5V ) ( 62 /FPGA_Spartan6/M0_DQ13 ) ( 63 /FPGA_Spartan6/M0_DQ14 ) @@ -2141,15 +2141,15 @@ $endfootprintlist } { Pin List by Nets Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" - U8 1 U1 T5 + U8 1 Net 2 "/Non volatile memories/NF_RE_N" "NF_RE_N" - U1 B16 U5 8 + U1 B16 Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" - U1 C16 U5 9 -Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE" + U1 C16 +Net 4 "/Non volatile memories/NF_ALE" "NF_ALE" U5 17 U1 A15 Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" @@ -2158,34 +2158,34 @@ Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" Net 6 "/Ethernet Phy/ETH_RXC" "ETH_RXC" U4 10 U1 A7 -Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK" - U4 46 +Net 7 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" U1 A4 -Net 8 "/USB/USBA_SPD" "USBA_SPD" + U4 46 +Net 8 "/FPGA Spartan6/USBA_SPD" "USBA_SPD" U6 2 U1 R19 -Net 9 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" +Net 9 "/USB/USBA_OE_N" "USBA_OE_N" U6 9 U1 P18 -Net 10 "/USB/USBA_RCV" "USBA_RCV" +Net 10 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" U1 N16 U6 3 Net 11 "/USB/USBA_VP" "USBA_VP" U1 P17 U6 4 -Net 12 "/FPGA Spartan6/USBA_VM" "USBA_VM" +Net 12 "/USB/USBA_VM" "USBA_VM" U6 5 U1 M18 -Net 13 "/Ethernet Phy/ETH_COL" "ETH_COL" +Net 13 "/FPGA Spartan6/ETH_COL" "ETH_COL" + U1 A9 U4 21 +Net 14 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" U1 B10 -Net 14 "/Ethernet Phy/ETH_CRS" "ETH_CRS" - U1 C10 U4 22 -Net 15 "/Non volatile memories/SD_CLK" "SD_CLK" +Net 15 "/FPGA Spartan6/SD_CLK" "SD_CLK" J1 5 U1 E16 -Net 16 "/Ethernet Phy/ETH_INT" "ETH_INT" +Net 16 "/FPGA Spartan6/ETH_INT" "ETH_INT" U1 A10 U4 25 Net 17 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" @@ -2196,57 +2196,57 @@ Net 18 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" U1 D6 R1 1 Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" - U1 C7 U4 48 -Net 20 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" + U1 C7 +Net 20 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" U1 A6 U4 9 Net 21 "/Ethernet Phy/ETH_RXER" "ETH_RXER" U4 11 U1 B8 -Net 22 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" +Net 22 "/Ethernet Phy/ETH_TXER" "ETH_TXER" U1 D8 U4 14 -Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" - U1 D9 +Net 23 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" U4 16 -Net 24 "/DDR Banks/M1_CS#" "M1_CS#" - U3 24 + U1 D9 +Net 24 "/FPGA Spartan6/M1_CS#" "M1_CS#" R20 2 + U3 24 Net 25 "/DDR Banks/M1_UDM" "M1_UDM" - R18 2 U3 47 -Net 26 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" - U3 16 + R18 2 +Net 26 "/DDR Banks/M1_LDQS" "M1_LDQS" RP3 8 -Net 27 "/FPGA Spartan6/M1_LDM" "M1_LDM" + U3 16 +Net 27 "/DDR Banks/M1_LDM" "M1_LDM" U3 20 RP3 7 -Net 28 "/DDR Banks/M1_UDQS" "M1_UDQS" +Net 28 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" U3 51 R19 2 -Net 29 "/FPGA Spartan6/M0_UDQS" "M0_UDQS" +Net 29 "/DDR Banks/M0_UDQS" "M0_UDQS" R22 2 U2 51 -Net 30 "/DDR Banks/M0_LDM" "M0_LDM" - U2 20 +Net 30 "/FPGA Spartan6/M0_LDM" "M0_LDM" RP16 7 -Net 31 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" - RP3 5 + U2 20 +Net 31 "/DDR Banks/M1_CAS#" "M1_CAS#" U3 22 + RP3 5 Net 32 "/FPGA Spartan6/M1_CKE" "M1_CKE" U3 45 R17 2 -Net 33 "/DDR Banks/M1_CLK" "M1_CLK" - R16 2 - U1 H20 +Net 33 "/FPGA Spartan6/M1_CLK" "M1_CLK" U3 46 -Net 34 "/DDR Banks/M1_CLK#" "M1_CLK#" + U1 H20 + R16 2 +Net 34 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" U3 44 - R16 1 U1 J19 + R16 1 Net 35 "GND" "GND" - C76 2 + J1 6 J1 CASE J1 CASE U3 58 @@ -2284,7 +2284,6 @@ Net 35 "GND" "GND" U5 36 J1 CASE J1 COM - J1 6 U2 6 U8 4 C68 2 @@ -2306,30 +2305,27 @@ Net 35 "GND" "GND" C53 2 C41 2 C44 2 - C47 2 - U10 5 - U10 2 C39 2 - C42 2 - C45 2 U11 2 + C42 2 + U9 PAD + C45 2 C48 2 C40 2 - U9 PAD U9 8 C81 2 + C85 2 C65 2 + C78 2 C80 2 R25 2 + C47 2 C50 2 C56 2 C59 2 C62 2 - C85 2 R27 2 U12 2 - C78 2 - C66 2 U1 W16 U1 AA5 U1 J15 @@ -2340,6 +2336,7 @@ Net 35 "GND" "GND" U1 K14 U1 N13 U1 L13 + C76 2 C77 2 U1 W7 U1 U7 @@ -2362,7 +2359,6 @@ Net 35 "GND" "GND" U1 P12 U1 M12 U1 K12 - U10 PAD U1 AB1 U1 U21 U1 N21 @@ -2370,6 +2366,9 @@ Net 35 "GND" "GND" U1 E21 U1 N11 U1 L11 + C66 2 + U10 5 + U10 2 U1 J13 U1 AA17 U1 AA13 @@ -2389,246 +2388,247 @@ Net 35 "GND" "GND" U1 M10 U1 K10 U1 N9 + U10 PAD U1 L9 U1 J9 - U3 12 - L5 2 - U3 52 - J4 4 - J4 5 - U3 34 - L7 2 - U3 64 + R15 2 + C38 2 + V3 2 + V4 2 + C37 2 + U3 66 + R10 2 + C16 2 U7 8 + U7 7 + U3 6 + U4 23 + U4 44 U4 35 U4 36 - C16 2 - R10 2 - U3 66 + J4 4 + J4 5 + C36 2 + C35 2 + U4 39 + U4 12 + V1 2 + U6 8 + U3 64 + L7 2 + U3 34 + U3 52 + L5 2 + U3 12 U3 48 - C13 2 + V2 2 + C15 2 C14 2 - C10 2 + C13 2 + U6 7 + C84 2 + C82 2 + C1 2 C9 2 C6 2 C4 2 - C2 2 - U6 8 - U6 7 - C35 2 - C36 2 - C37 2 - V4 2 - V3 2 - C38 2 - R15 2 - U4 12 - U4 39 - U3 6 - U7 7 - U4 23 - U4 44 - C82 2 - R2 2 - C11 2 - C15 2 - V2 2 - V1 2 - U4 8 - C8 2 - C7 2 - U2 58 - U2 48 C12 2 R9 2 - C84 2 - C5 2 + C11 2 + R2 2 + C10 2 + C7 2 + C8 2 + U4 8 C3 2 - C1 2 + C2 2 + U2 48 + U2 58 + C5 2 Net 36 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" + U2 44 U1 H3 R21 2 - U2 44 Net 37 "/FPGA Spartan6/M0_CLK" "M0_CLK" - R21 1 U2 46 + R21 1 U1 H4 -Net 38 "/FPGA Spartan6/M0_CKE" "M0_CKE" +Net 38 "/DDR Banks/M0_CKE" "M0_CKE" R24 2 U2 45 -Net 39 "/DDR Banks/M0_CAS#" "M0_CAS#" - RP16 5 +Net 39 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" U2 22 -Net 40 "/DDR Banks/M1_WE#" "M1_WE#" + RP16 5 +Net 40 "/FPGA Spartan6/M1_WE#" "M1_WE#" RP3 6 U3 21 Net 41 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" - RP2 8 U3 23 -Net 42 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" + RP2 8 +Net 42 "/DDR Banks/M0_RAS#" "M0_RAS#" RP15 8 U2 23 -Net 43 "/DDR Banks/M0_WE#" "M0_WE#" +Net 43 "/FPGA Spartan6/M0_WE#" "M0_WE#" RP16 6 U2 21 -Net 44 "/DDR Banks/M0_LDQS" "M0_LDQS" - RP16 8 +Net 44 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" U2 16 + RP16 8 Net 45 "/FPGA Spartan6/M0_UDM" "M0_UDM" - R23 2 U2 47 + R23 2 Net 46 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" U1 AA21 U8 6 -Net 47 "/FPGA Spartan6/NF_RNB" "NF_RNB" - U5 7 +Net 47 "/Non volatile memories/NF_RNB" "NF_RNB" U5 6 + U5 7 U1 A16 Net 48 "/Non volatile memories/NF_WE_N" "NF_WE_N" U5 18 U1 C15 -Net 49 "/FPGA Spartan6/NF_CLE" "NF_CLE" - U1 D15 +Net 49 "/Non volatile memories/NF_CLE" "NF_CLE" U5 16 + U1 D15 Net 50 "/FPGA Spartan6/SD_CMD" "SD_CMD" - U1 D17 J1 3 + U1 D17 Net 55 "+2.5V" "+2.5V" - C17 1 - U1 L2 U1 R2 - U6 1 - U1 W2 - C29 1 - C31 1 U1 U18 U1 N18 - U2 1 - U2 3 U1 J18 - U1 L16 - U3 33 - U1 L8 - U1 N8 - U1 C21 - U1 H9 - U1 G21 - U3 18 - U1 L21 - U1 R21 - U1 R10 - U1 E19 - U1 U11 - C30 1 - C32 1 - C27 1 - U1 G12 - U1 F6 - U3 15 - U1 R12 - C34 1 - C71 1 - C70 1 - U2 33 - C22 1 - C23 1 - C25 1 - C24 1 - C26 1 - C21 1 - U1 F4 - C33 1 + C51 1 + C49 1 + C46 1 + C52 1 C43 1 C40 1 C63 1 C60 1 C57 1 C54 1 - R13 1 - U2 9 C68 1 C65 1 - U2 61 + U2 1 + U1 U11 + U1 G12 + U2 3 + U3 15 + U1 R12 + U3 33 + U1 L8 + U1 N8 + U1 H9 + U2 33 + U3 18 + U1 L16 + U1 F4 + U6 1 + U1 L2 + U1 L7 + C34 1 + C71 1 + C70 1 + C17 1 + U1 E19 + U1 G21 + C27 1 + C32 1 + U1 L21 + C30 1 + U1 R21 + C31 1 + C29 1 + U1 N5 + U1 J5 + U1 U5 + U1 F6 + U1 W2 + U1 C21 + C24 1 C62 1 - U2 18 + C26 1 C59 1 C56 1 - U2 55 - U2 15 - C28 1 + C21 1 C15 1 - C19 1 C53 1 - C51 1 - R11 1 - C49 1 - C46 1 - C52 1 - C37 1 + C28 1 + U1 W21 + C33 1 + C22 1 + C23 1 + C25 1 + U2 15 U1 G2 U1 C2 - U1 U5 - C77 1 + U3 3 + U2 55 + U1 H15 + U1 K15 U1 M15 U1 D16 + U2 9 C66 1 U1 R6 U1 V6 + R13 1 + C77 1 + C37 1 + C19 1 + R11 1 U3 61 + U2 18 U7 1 - U1 J5 - U1 N5 + U1 R10 U1 F11 - U1 W21 + U2 61 + U3 9 U3 55 U3 1 - U1 K15 - U1 H15 - U3 3 - U1 L7 - U3 9 Net 58 "/DDR Banks/M0_VREF" "M0_VREF" - U2 49 - C18 1 C17 2 - R11 2 + C18 1 R12 1 + R11 2 + U2 49 Net 59 "/DDR Banks/M1_VREF" "M1_VREF" C20 1 C19 2 - R13 2 R14 1 + R13 2 U3 49 Net 68 "VCCO2" "VCCO2" - U1 T9 + U1 T13 U1 AA3 + U1 W5 + U8 8 U1 V8 U1 AA15 - U8 8 - U1 V16 - U1 T13 - U1 V12 - U1 AA19 - C69 1 - C67 1 - C64 1 - C61 1 - C58 1 - C55 1 - U1 AA7 - U1 W5 U1 AA11 + U1 T9 + U1 V16 + U1 AA7 + U1 V12 + C58 1 + U1 AA19 + C61 1 + C64 1 + C55 1 + C67 1 + C69 1 Net 87 "+3.3V" "+3.3V" - U1 B15 U1 B4 - U1 B7 - U1 E17 - U1 B19 - U1 E9 - U1 G10 U1 B11 + U1 G10 U1 E13 + U1 E9 U1 G14 + U1 B15 + U1 B19 + U1 E17 + U1 B7 J4 6 J4 9 J4 11 @@ -2653,7 +2653,9 @@ Net 87 "+3.3V" "+3.3V" C79 1 C81 1 L8 1 - C14 1 + C47 1 + C44 1 + C41 1 C13 1 U7 14 U7 12 @@ -2668,21 +2670,19 @@ Net 87 "+3.3V" "+3.3V" U4 24 J4 3 C50 1 - C47 1 - C44 1 - C41 1 + C14 1 Net 100 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" RP1 3 U1 E22 Net 101 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" - RP1 2 U1 F22 + RP1 2 Net 103 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" - U1 C22 RP7 3 + U1 C22 Net 104 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" - RP7 1 U1 D22 + RP7 1 Net 105 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" RP6 3 U1 K20 @@ -2711,14 +2711,14 @@ Net 116 "/FPGA Spartan6/R_M0_A5" "R_M0_A5" U1 K3 RP17 3 Net 117 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" - RP10 3 U1 V2 + RP10 3 Net 118 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" - U1 U3 RP10 1 + U1 U3 Net 119 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" - U1 P1 RP11 2 + U1 P1 Net 120 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" RP11 4 U1 R1 @@ -2729,51 +2729,51 @@ Net 122 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" RP13 2 U1 N1 Net 123 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" - RP13 4 U1 M1 + RP13 4 Net 124 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" RP12 1 U1 J3 Net 168 "+1.2V" "+1.2V" - U1 J12 - U1 L12 - R28 1 - U1 M11 - U1 P11 - L9 1 - C85 1 - U1 K11 - U1 R14 - C39 1 - U1 J14 - C42 1 - C45 1 - U1 K13 - U1 M13 - U1 N14 - C76 1 - U1 P13 - U1 N12 - U1 J8 - U1 K9 C84 1 C83 1 + U1 R14 + U1 N14 + U1 L14 + U1 K11 + U1 M11 + U1 P11 + U1 J14 + U1 K9 U1 M9 U1 P9 + U1 M13 + C42 1 U1 J10 + C45 1 U1 L10 - C48 1 - U1 L14 + C85 1 U1 N10 + L9 1 + R28 1 + C48 1 + U1 K13 + U1 J12 + C39 1 + U1 L12 + U1 N12 + U1 J8 + U1 P13 + C76 1 Net 169 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" - RP2 2 U1 J17 + RP2 2 Net 170 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" - RP12 3 U1 K2 + RP12 3 Net 171 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" - U1 K17 RP2 3 + U1 K17 Net 172 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" U1 R20 RP9 2 @@ -2786,45 +2786,45 @@ Net 174 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" Net 175 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" RP5 1 U1 N20 -Net 180 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" +Net 180 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" + U1 L20 + RP3 1 +Net 181 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" RP3 2 U1 L19 -Net 181 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" - U1 H19 +Net 182 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" RP3 3 -Net 197 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" - RP8 1 + U1 H19 +Net 198 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" U1 V22 -Net 198 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" + RP8 1 +Net 199 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" RP8 3 U1 U22 -Net 200 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" - U1 R22 +Net 201 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" RP9 1 -Net 207 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" - RP6 2 + U1 R22 +Net 208 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" U1 K19 -Net 208 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" + RP6 2 +Net 209 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" RP2 4 U1 G19 -Net 209 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" +Net 210 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" RP7 2 U1 F19 -Net 212 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" - RP3 1 - U1 L20 Net 213 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" - U1 M20 R18 1 + U1 M20 Net 242 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" - RP10 4 U1 V1 + RP10 4 Net 243 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" - RP10 2 U1 U1 + RP10 2 Net 246 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" - RP12 4 U1 K1 + RP12 4 Net 247 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" RP12 2 U1 J1 @@ -2832,53 +2832,53 @@ Net 249 "/FPGA Spartan6/R_M0_A12" "R_M0_A12" U1 D1 RP18 1 Net 310 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" - U1 J20 RP4 1 + U1 J20 Net 311 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" - U1 G20 RP1 4 + U1 G20 Net 313 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" RP6 1 U1 E20 Net 315 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" - U1 C20 RP7 4 + U1 C20 Net 330 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" - RP9 3 U1 P22 + RP9 3 Net 331 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" - U1 N22 RP5 2 + U1 N22 Net 332 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" - RP5 4 U1 M22 + RP5 4 Net 334 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" - RP4 4 U1 K22 + RP4 4 Net 335 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" RP4 2 U1 J22 Net 338 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" - U1 V21 RP8 2 + U1 V21 Net 339 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" U1 P21 RP9 4 Net 340 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" - RP4 3 U1 K21 + RP4 3 Net 341 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" - U1 F21 RP1 1 + U1 F21 Net 352 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" - U1 N3 RP13 1 + U1 N3 Net 353 "/FPGA Spartan6/R_M0_LDQS" "R_M0_LDQS" U1 L3 RP16 1 Net 354 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0" - RP15 2 U1 G3 + RP15 2 Net 355 "/FPGA Spartan6/R_M0_A8" "R_M0_A8" U1 E3 RP18 4 @@ -2886,59 +2886,59 @@ Net 360 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS" R22 1 U1 T2 Net 361 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" - U1 P2 RP11 1 + U1 P2 Net 362 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" - RP13 3 U1 M2 + RP13 3 Net 363 "/FPGA Spartan6/R_M0_A0" "R_M0_A0" - RP14 1 U1 H2 + RP14 1 Net 368 "/FPGA Spartan6/R_M0_A7" "R_M0_A7" - U1 H6 RP17 1 + U1 H6 Net 382 "/FPGA Spartan6/R_M0_A6" "R_M0_A6" - RP17 2 U1 J4 + RP17 2 Net 383 "/FPGA Spartan6/R_M0_A10" "R_M0_A10" - RP15 4 U1 G4 -Net 384 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" - U1 H22 - RP3 4 -Net 385 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" - R19 1 - U1 T21 -Net 386 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" - R17 1 - U1 D21 -Net 387 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" - R20 1 - U1 H16 -Net 388 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" + RP15 4 +Net 384 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" U1 H21 RP2 1 +Net 385 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" + RP3 4 + U1 H22 +Net 386 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" + U1 T21 + R19 1 +Net 387 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" + R17 1 + U1 D21 +Net 388 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" + U1 H16 + R20 1 Net 389 "/FPGA Spartan6/R_M0_RAS#" "R_M0_RAS#" - U1 K5 RP15 1 + U1 K5 Net 390 "/FPGA Spartan6/R_M0_CKE" "R_M0_CKE" - U1 D2 R24 1 + U1 D2 Net 391 "/FPGA Spartan6/R_M0_UDM" "R_M0_UDM" - U1 M3 R23 1 + U1 M3 Net 392 "/FPGA Spartan6/R_M0_LDM" "R_M0_LDM" - RP16 2 U1 L4 + RP16 2 Net 393 "/FPGA Spartan6/R_M0_WE#" "R_M0_WE#" U1 F2 RP16 3 Net 394 "/FPGA Spartan6/R_M0_CAS#" "R_M0_CAS#" - RP16 4 U1 K4 + RP16 4 Net 395 "" "" - J4 10 R7 1 + J4 10 Net 396 "/Ethernet Phy/ETH_LED0" "ETH_LED0" U4 26 R7 2 @@ -2946,115 +2946,115 @@ Net 397 "" "" R2 1 U4 37 Net 398 "" "" - R8 1 J4 12 + R8 1 Net 399 "/Ethernet Phy/ETH_LED1" "ETH_LED1" U4 27 R8 2 Net 405 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD" - J4 13 - J4 14 C12 1 R9 1 + J4 14 + J4 13 Net 406 "/Ethernet Phy/MAG_TX-" "MAG_TX-" + R4 2 J4 2 U4 40 - R4 2 Net 407 "/Ethernet Phy/MAG_TX+" "MAG_TX+" - J4 1 U4 41 + J4 1 R3 2 Net 408 "/Ethernet Phy/MAG_RX+" "MAG_RX+" + U4 33 J4 7 R5 2 - U4 33 Net 409 "/Ethernet Phy/MAG_RX-" "MAG_RX-" - J4 8 R6 2 + J4 8 U4 32 Net 410 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + L3 2 C9 1 U4 47 - L3 2 Net 411 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - U4 38 C7 1 C8 1 L2 2 + U4 38 Net 412 "+1.8V" "+1.8V" - L1 1 C4 1 C2 1 U4 13 + L1 1 Net 415 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" U4 31 L3 1 C6 1 L1 2 Net 422 "" "" - F2 1 L6 1 + F2 1 Net 424 "" "" - J5 S1 - J5 S2 C16 1 R10 1 J5 S4 J5 S3 + J5 S2 + J5 S1 Net 425 "" "" - L5 1 J5 4 + L5 1 Net 426 "" "" V2 1 - U6 10 V2 1 + U6 10 J5 2 Net 427 "" "" - L4 2 J5 1 + L4 2 Net 428 "+5V" "+5V" - F2 2 F1 2 + F2 2 Net 429 "" "" L4 1 F1 1 Net 430 "" "" - U6 11 + V1 1 + V1 1 J5 3 - V1 1 - V1 1 + U6 11 Net 431 "" "" + V4 1 + V4 1 U7 10 - V4 1 - V4 1 Net 432 "" "" V3 1 V3 1 U7 11 Net 433 "" "" - R15 1 C38 1 + R15 1 Net 434 "" "" - U12 4 C82 1 + U12 4 U12 1 Net 435 "" "" - C83 2 U12 5 R27 1 R28 2 + C83 2 Net 436 "" "" - U11 4 U11 1 + U11 4 C78 1 Net 437 "" "" - R25 1 - C79 2 U11 5 + C79 2 + R25 1 R26 2 Net 447 "" "" - L8 2 U11 3 + L8 2 Net 466 "" "" L9 2 U12 3 @@ -3065,256 +3065,256 @@ Net 468 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" U8 3 U1 U14 Net 469 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" - U1 AA20 U8 2 + U1 AA20 Net 470 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" U1 AB20 U8 5 -Net 471 "/FPGA Spartan6/NF_D7" "NF_D7" +Net 471 "/Non volatile memories/NF_D7" "NF_D7" U5 44 U1 A11 -Net 472 "/Non volatile memories/NF_D6" "NF_D6" +Net 472 "/FPGA Spartan6/NF_D6" "NF_D6" U5 43 U1 D11 -Net 473 "/Non volatile memories/NF_D5" "NF_D5" +Net 473 "/FPGA Spartan6/NF_D5" "NF_D5" U5 42 U1 C12 Net 474 "/FPGA Spartan6/NF_D4" "NF_D4" U5 41 U1 B12 -Net 475 "/FPGA Spartan6/NF_D3" "NF_D3" +Net 475 "/Non volatile memories/NF_D3" "NF_D3" U5 32 U1 A12 Net 476 "/FPGA Spartan6/NF_D2" "NF_D2" U5 31 U1 C13 -Net 477 "/Non volatile memories/NF_D1" "NF_D1" - U1 A13 +Net 477 "/FPGA Spartan6/NF_D1" "NF_D1" U5 30 + U1 A13 Net 478 "/Non volatile memories/NF_D0" "NF_D0" U5 29 U1 D14 Net 479 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" - U4 20 U1 A8 -Net 480 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" + U4 20 +Net 480 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" + U1 C10 U4 19 +Net 481 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" U1 C9 -Net 481 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" U4 18 +Net 482 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" U1 D10 -Net 482 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" - U1 A9 U4 17 -Net 483 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" - U4 3 +Net 483 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" U1 C5 + U4 3 Net 484 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" U4 4 U1 C6 -Net 485 "/FPGA Spartan6/ETH_RXD1" "ETH_RXD1" +Net 485 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" U4 5 U1 A5 Net 486 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" U4 6 U1 B6 Net 487 "/DDR Banks/M0_BA1" "M0_BA1" - RP15 6 U2 27 -Net 488 "/DDR Banks/M0_BA0" "M0_BA0" + RP15 6 +Net 488 "/FPGA Spartan6/M0_BA0" "M0_BA0" RP15 7 U2 26 -Net 489 "/DDR Banks/M1_BA1" "M1_BA1" +Net 489 "/FPGA Spartan6/M1_BA1" "M1_BA1" RP2 6 U3 27 Net 490 "/FPGA Spartan6/M1_BA0" "M1_BA0" U3 26 RP2 7 -Net 491 "/DDR Banks/M1_DQ15" "M1_DQ15" +Net 491 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" RP8 8 U3 65 Net 492 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" - RP8 7 U3 63 + RP8 7 Net 493 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" - U3 62 RP8 6 -Net 494 "/DDR Banks/M1_DQ12" "M1_DQ12" + U3 62 +Net 494 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" RP8 5 U3 60 Net 495 "/DDR Banks/M1_DQ11" "M1_DQ11" RP9 8 U3 59 -Net 496 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" +Net 496 "/DDR Banks/M1_DQ10" "M1_DQ10" U3 57 RP9 7 -Net 497 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" +Net 497 "/Non volatile memories/SD_DAT3" "SD_DAT3" U1 C17 J1 2 Net 498 "/Non volatile memories/SD_DAT2" "SD_DAT2" U1 A17 J1 1 Net 499 "/Non volatile memories/SD_DAT1" "SD_DAT1" - U1 B18 J1 8 + U1 B18 Net 500 "/FPGA Spartan6/SD_DAT0" "SD_DAT0" - J1 7 U1 A18 -Net 501 "/DDR Banks/M1_A7" "M1_A7" + J1 7 +Net 501 "/FPGA Spartan6/M1_A7" "M1_A7" U3 38 RP6 8 Net 502 "/FPGA Spartan6/M1_A6" "M1_A6" - U3 37 RP6 7 -Net 503 "/FPGA Spartan6/M1_A5" "M1_A5" + U3 37 +Net 503 "/DDR Banks/M1_A5" "M1_A5" U3 36 RP6 6 Net 504 "/FPGA Spartan6/M1_A4" "M1_A4" - U3 35 RP6 5 -Net 505 "/FPGA Spartan6/M1_A3" "M1_A3" - U3 32 + U3 35 +Net 505 "/DDR Banks/M1_A3" "M1_A3" RP1 5 -Net 506 "/FPGA Spartan6/M1_A2" "M1_A2" - U3 31 + U3 32 +Net 506 "/DDR Banks/M1_A2" "M1_A2" RP1 6 + U3 31 Net 507 "/FPGA Spartan6/M1_A1" "M1_A1" - RP1 7 U3 30 + RP1 7 Net 508 "/DDR Banks/M1_A0" "M1_A0" - RP1 8 U3 29 + RP1 8 Net 509 "/FPGA Spartan6/M0_A12" "M0_A12" U2 42 RP18 8 -Net 510 "/FPGA Spartan6/M0_A11" "M0_A11" +Net 510 "/DDR Banks/M0_A11" "M0_A11" U2 41 RP18 7 Net 511 "/FPGA Spartan6/M0_A10" "M0_A10" U2 28 RP15 5 Net 512 "/DDR Banks/M0_A9" "M0_A9" - U2 40 RP18 6 -Net 513 "/FPGA Spartan6/M0_A8" "M0_A8" - RP18 5 + U2 40 +Net 513 "/DDR Banks/M0_A8" "M0_A8" U2 39 -Net 514 "/DDR Banks/M0_A7" "M0_A7" + RP18 5 +Net 514 "/FPGA Spartan6/M0_A7" "M0_A7" RP17 8 U2 38 Net 515 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" - U3 56 RP9 6 + U3 56 Net 516 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" RP9 5 U3 54 Net 517 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" - RP4 5 U3 13 -Net 518 "/DDR Banks/M1_DQ6" "M1_DQ6" + RP4 5 +Net 518 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" U3 11 RP4 6 Net 519 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" - RP4 7 U3 10 + RP4 7 Net 520 "/DDR Banks/M1_DQ4" "M1_DQ4" U3 8 RP4 8 Net 521 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" - RP5 5 U3 7 + RP5 5 Net 522 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" RP5 6 U3 5 -Net 523 "/DDR Banks/M1_DQ1" "M1_DQ1" - U3 4 +Net 523 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" RP5 7 + U3 4 Net 524 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" U3 2 RP5 8 -Net 525 "/FPGA Spartan6/M1_A12" "M1_A12" - U3 42 +Net 525 "/DDR Banks/M1_A12" "M1_A12" RP7 8 + U3 42 Net 526 "/DDR Banks/M1_A11" "M1_A11" - RP7 7 U3 41 + RP7 7 Net 527 "/FPGA Spartan6/M1_A10" "M1_A10" - U3 28 RP2 5 + U3 28 Net 528 "/FPGA Spartan6/M1_A9" "M1_A9" RP7 6 U3 40 Net 529 "/DDR Banks/M1_A8" "M1_A8" - U3 39 RP7 5 + U3 39 Net 530 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" U2 7 RP13 5 -Net 531 "/DDR Banks/M0_DQ2" "M0_DQ2" - U2 5 +Net 531 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" RP13 6 -Net 532 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" - U2 4 + U2 5 +Net 532 "/DDR Banks/M0_DQ1" "M0_DQ1" RP13 7 + U2 4 Net 533 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" - RP13 8 U2 2 + RP13 8 Net 534 "/DDR Banks/M0_A6" "M0_A6" - RP17 7 U2 37 -Net 535 "/DDR Banks/M0_A5" "M0_A5" + RP17 7 +Net 535 "/FPGA Spartan6/M0_A5" "M0_A5" RP17 6 U2 36 Net 536 "/FPGA Spartan6/M0_A4" "M0_A4" - RP17 5 U2 35 + RP17 5 Net 537 "/FPGA Spartan6/M0_A3" "M0_A3" - U2 32 RP14 5 + U2 32 Net 538 "/DDR Banks/M0_A2" "M0_A2" - U2 31 RP14 6 + U2 31 Net 539 "/FPGA Spartan6/M0_A1" "M0_A1" RP14 7 U2 30 -Net 540 "/DDR Banks/M0_A0" "M0_A0" - RP14 8 +Net 540 "/FPGA Spartan6/M0_A0" "M0_A0" U2 29 + RP14 8 Net 541 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" - U2 65 RP10 5 + U2 65 Net 542 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" - RP10 6 U2 63 + RP10 6 Net 543 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" RP10 7 U2 62 -Net 544 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" +Net 544 "/DDR Banks/M0_DQ12" "M0_DQ12" RP10 8 U2 60 -Net 545 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" - U2 59 +Net 545 "/DDR Banks/M0_DQ11" "M0_DQ11" RP11 5 + U2 59 Net 546 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" U2 57 RP11 6 -Net 547 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" +Net 547 "/DDR Banks/M0_DQ9" "M0_DQ9" U2 56 RP11 7 -Net 548 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" - RP11 8 +Net 548 "/DDR Banks/M0_DQ8" "M0_DQ8" U2 54 -Net 549 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" + RP11 8 +Net 549 "/DDR Banks/M0_DQ7" "M0_DQ7" U2 13 RP12 5 -Net 550 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" - U2 11 +Net 550 "/DDR Banks/M0_DQ6" "M0_DQ6" RP12 6 -Net 551 "/DDR Banks/M0_DQ5" "M0_DQ5" - U2 10 + U2 11 +Net 551 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" RP12 7 -Net 552 "/DDR Banks/M0_DQ4" "M0_DQ4" - RP12 8 + U2 10 +Net 552 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" U2 8 + RP12 8 } #End diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 5e5cd36..2ede12a 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 21 Aug 2010 07:16:33 AM COT +EESchema Schematic File Version 2 date Sat 21 Aug 2010 04:24:17 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03