From 35a1b35c7f4ca7fc9aca6e68641be2b2e60ccfce Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Fri, 13 Aug 2010 09:27:10 -0500 Subject: [PATCH] usb added --- kicad/xue-rnc/DRAM.sch | 58 +- kicad/xue-rnc/FPGA.sch | 34 +- kicad/xue-rnc/NV_MEMORIES.sch | 22 +- kicad/xue-rnc/USB.sch | 308 +++- kicad/xue-rnc/eth_phy.sch | 2 +- kicad/xue-rnc/xue-rnc-cache.lib | 2 +- kicad/xue-rnc/xue-rnc.brd | 1551 ++++++++++------ kicad/xue-rnc/xue-rnc.cmp | 247 ++- kicad/xue-rnc/xue-rnc.net | 3006 ++++++++++++------------------- kicad/xue-rnc/xue-rnc.pro | 2 +- kicad/xue-rnc/xue-rnc.sch | 2 +- 11 files changed, 2760 insertions(+), 2474 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 9b1c0ea..4af4b46 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 09:19:35 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -500,37 +500,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR020 +L GND #PWR026 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR020" H 6900 6200 30 0001 C CNN +F 0 "#PWR026" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR021 +L +2.5V #PWR027 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR021" H 6900 5750 20 0001 C CNN +F 0 "#PWR027" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR022 +L +2.5V #PWR028 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR022" H 1700 5750 20 0001 C CNN +F 0 "#PWR028" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR023 +L GND #PWR029 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR023" H 1700 6200 30 0001 C CNN +F 0 "#PWR029" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -546,19 +546,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR024 +L +2.5V #PWR030 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR024" H 3050 1700 20 0001 C CNN +F 0 "#PWR030" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR025 +L +2.5V #PWR031 U 1 1 4C61CFC6 P 8300 1750 -F 0 "#PWR025" H 8300 1700 20 0001 C CNN +F 0 "#PWR031" H 8300 1700 20 0001 C CNN F 1 "+2.5V" H 8300 1850 30 0000 C CNN 1 8300 1750 1 0 0 -1 @@ -624,37 +624,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR026 +L +2.5V #PWR032 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR026" H 8300 5700 20 0001 C CNN +F 0 "#PWR032" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR027 +L GND #PWR033 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR027" H 8300 6350 30 0001 C CNN +F 0 "#PWR033" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR028 +L GND #PWR034 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR028" H 3050 6350 30 0001 C CNN +F 0 "#PWR034" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR029 +L +2.5V #PWR035 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR029" H 3050 5700 20 0001 C CNN +F 0 "#PWR035" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -740,19 +740,19 @@ F 2 "0402" H 9850 1850 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR030 +L +2.5V #PWR036 U 1 1 4C61CE2F P 9850 1000 -F 0 "#PWR030" H 9850 950 20 0001 C CNN +F 0 "#PWR036" H 9850 950 20 0001 C CNN F 1 "+2.5V" H 9850 1100 30 0000 C CNN 1 9850 1000 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR031 +L +2.5V #PWR037 U 1 1 4C61CDF1 P 4550 900 -F 0 "#PWR031" H 4550 850 20 0001 C CNN +F 0 "#PWR037" H 4550 850 20 0001 C CNN F 1 "+2.5V" H 4550 1000 30 0000 C CNN 1 4550 900 1 0 0 -1 @@ -844,10 +844,10 @@ $EndComp Text HLabel 4950 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR032 +L GND #PWR038 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR032" H 3000 5200 30 0001 C CNN +F 0 "#PWR038" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1141,10 +1141,10 @@ Entry Wire Line Entry Wire Line 9950 3650 10050 3750 $Comp -L GND #PWR033 +L GND #PWR039 U 1 1 4C437C3F P 8250 5200 -F 0 "#PWR033" H 8250 5200 30 0001 C CNN +F 0 "#PWR039" H 8250 5200 30 0001 C CNN F 1 "GND" H 8250 5130 30 0001 C CNN 1 8250 5200 1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index cf803a6..358f4a0 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 09:19:35 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -908,46 +908,46 @@ ETH_COL Text HLabel 14150 10650 0 60 BiDi ~ 0 ETH_CRS $Comp -L +3.3V #PWR07 +L +3.3V #PWR013 U 1 1 4C61E5B3 P 15850 8200 -F 0 "#PWR07" H 15850 8160 30 0001 C CNN +F 0 "#PWR013" H 15850 8160 30 0001 C CNN F 1 "+3.3V" H 15850 8310 30 0000 C CNN 1 15850 8200 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR08 +L +1.2V #PWR014 U 1 1 4C61E58C P 14050 12900 -F 0 "#PWR08" H 14050 13040 20 0001 C CNN +F 0 "#PWR014" H 14050 13040 20 0001 C CNN F 1 "+1.2V" H 14050 13010 30 0000 C CNN 1 14050 12900 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR09 +L +2.5V #PWR015 U 1 1 4C61E577 P 12550 12900 -F 0 "#PWR09" H 12550 12850 20 0001 C CNN +F 0 "#PWR015" H 12550 12850 20 0001 C CNN F 1 "+2.5V" H 12550 13000 30 0000 C CNN 1 12550 12900 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR010 +L +2.5V #PWR016 U 1 1 4C61E523 P 16000 600 -F 0 "#PWR010" H 16000 550 20 0001 C CNN +F 0 "#PWR016" H 16000 550 20 0001 C CNN F 1 "+2.5V" H 16000 700 30 0000 C CNN 1 16000 600 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR011 +L +2.5V #PWR017 U 1 1 4C61E51F P 5300 650 -F 0 "#PWR011" H 5300 600 20 0001 C CNN +F 0 "#PWR017" H 5300 600 20 0001 C CNN F 1 "+2.5V" H 5300 750 30 0000 C CNN 1 5300 650 1 0 0 -1 @@ -993,19 +993,19 @@ M0_BA[0..1] Text HLabel 12400 4850 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR012 +L GND #PWR018 U 1 1 4C60C24F P 12550 5100 -F 0 "#PWR012" H 12550 5100 30 0001 C CNN +F 0 "#PWR018" H 12550 5100 30 0001 C CNN F 1 "GND" H 12550 5030 30 0001 C CNN 1 12550 5100 -1 0 0 -1 $EndComp $Comp -L GND #PWR013 +L GND #PWR019 U 1 1 4C60C21D P 1600 5950 -F 0 "#PWR013" H 1600 5950 30 0001 C CNN +F 0 "#PWR019" H 1600 5950 30 0001 C CNN F 1 "GND" H 1600 5880 30 0001 C CNN 1 1600 5950 -1 0 0 -1 @@ -1481,10 +1481,10 @@ M0_CLK Text HLabel 7750 4700 2 60 Output ~ 0 M0_CLK# $Comp -L GND #PWR014 +L GND #PWR020 U 1 1 4C439B7E P 13950 15700 -F 0 "#PWR014" H 13950 15700 30 0001 C CNN +F 0 "#PWR020" H 13950 15700 30 0001 C CNN F 1 "GND" H 13950 15630 30 0001 C CNN 1 13950 15700 -1 0 0 -1 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index a063a29..ac90a1f 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 09:19:35 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -191,19 +191,19 @@ Entry Wire Line Entry Wire Line 8150 3150 8250 3050 $Comp -L +3.3V #PWR015 +L +3.3V #PWR021 U 1 1 4C646C14 P 7950 2900 -F 0 "#PWR015" H 7950 2860 30 0001 C CNN +F 0 "#PWR021" H 7950 2860 30 0001 C CNN F 1 "+3.3V" H 7950 3010 30 0000 C CNN 1 7950 2900 1 0 0 -1 $EndComp $Comp -L GND #PWR016 +L GND #PWR022 U 1 1 4C646BEA P 7950 3000 -F 0 "#PWR016" H 7950 3000 30 0001 C CNN +F 0 "#PWR022" H 7950 3000 30 0001 C CNN F 1 "GND" H 7950 2930 30 0001 C CNN 1 7950 3000 1 0 0 -1 @@ -253,10 +253,10 @@ SD_DAT3 Text Label 2800 5850 0 30 ~ 0 SD_CMD $Comp -L GND #PWR017 +L GND #PWR023 U 1 1 4C61D875 P 3050 6150 -F 0 "#PWR017" H 3050 6150 30 0001 C CNN +F 0 "#PWR023" H 3050 6150 30 0001 C CNN F 1 "GND" H 3050 6080 30 0001 C CNN 1 3050 6150 1 0 0 -1 @@ -268,19 +268,19 @@ SD_DAT0 Text Label 2800 5600 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR018 +L GND #PWR024 U 1 1 4C438ADC P 4400 5950 -F 0 "#PWR018" H 4400 5950 30 0001 C CNN +F 0 "#PWR024" H 4400 5950 30 0001 C CNN F 1 "GND" H 4400 5880 30 0001 C CNN 1 4400 5950 1 0 0 -1 $EndComp $Comp -L GND #PWR019 +L GND #PWR025 U 1 1 4C438AD5 P 3950 6300 -F 0 "#PWR019" H 3950 6300 30 0001 C CNN +F 0 "#PWR025" H 3950 6300 30 0001 C CNN F 1 "GND" H 3950 6230 30 0001 C CNN 1 3950 6300 1 0 0 -1 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 7bdff2c..41a47ab 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 09:19:35 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -55,6 +55,288 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +$Comp +L MIC2550AYTS U7 +U 1 1 4C6552BF +P 2050 6450 +F 0 "U7" H 1900 5950 60 0000 C CNN +F 1 "MIC2550AYTS" H 2050 6850 60 0000 C CNN + 1 2050 6450 + 1 0 0 -1 +$EndComp +$Comp +L C C35 +U 1 1 4C6552BE +P 2500 5200 +F 0 "C35" H 2550 5300 50 0000 L CNN +F 1 "1uF" H 2550 5100 50 0000 L CNN + 1 2500 5200 + 1 0 0 -1 +$EndComp +$Comp +L C C36 +U 1 1 4C6552BD +P 2850 5200 +F 0 "C36" H 2900 5300 50 0000 L CNN +F 1 "1uF" H 2900 5100 50 0000 L CNN + 1 2850 5200 + 1 0 0 -1 +$EndComp +$Comp +L C C37 +U 1 1 4C6552BC +P 3200 5200 +F 0 "C37" H 3250 5300 50 0000 L CNN +F 1 "470nF" H 3250 5100 50 0000 L CNN + 1 3200 5200 + 1 0 0 -1 +$EndComp +$Comp +L MICROSMD075F F2 +U 1 1 4C6552BA +P 4400 5400 +F 0 "F2" V 4350 5600 60 0000 C CNN +F 1 "MICROSMD075F" V 4450 5950 60 0000 C CNN + 1 4400 5400 + 0 1 1 0 +$EndComp +$Comp +L V0402MHS03 V4 +U 1 1 4C6552B9 +P 3400 6900 +F 0 "V4" H 3500 6700 60 0000 C CNN +F 1 "V0402MHS03" H 3450 6900 60 0000 C CNN + 1 3400 6900 + 0 1 1 0 +$EndComp +$Comp +L V0402MHS03 V3 +U 1 1 4C6552B8 +P 3050 6900 +F 0 "V3" H 3150 6700 60 0000 C CNN +F 1 "V0402MHS03" H 3100 6900 60 0000 C CNN + 1 3050 6900 + 0 1 1 0 +$EndComp +$Comp +L C C38 +U 1 1 4C6552B7 +P 5500 6950 +F 0 "C38" H 5350 7050 50 0000 L CNN +F 1 "4.7nF" H 5200 6850 50 0000 L CNN + 1 5500 6950 + 1 0 0 -1 +$EndComp +$Comp +L R R15 +U 1 1 4C6552B6 +P 5800 6950 +F 0 "R15" V 5880 6950 50 0000 C CNN +F 1 "1M" V 5800 6950 50 0000 C CNN + 1 5800 6950 + 1 0 0 -1 +$EndComp +Text HLabel 1650 6350 0 40 BiDi ~ 0 +USBD_SPD +Text HLabel 1650 6450 0 40 BiDi ~ 0 +USBD_OE_N +Text HLabel 1650 6550 0 40 BiDi ~ 0 +USBD_RCV +Text HLabel 1650 6650 0 40 BiDi ~ 0 +USBD_VP +Text HLabel 1650 6750 0 40 BiDi ~ 0 +USBD_VM +$Comp +L GND #PWR01 +U 1 1 4C6552B5 +P 5650 7450 +F 0 "#PWR01" H 5650 7450 30 0001 C CNN +F 1 "GND" H 5650 7380 30 0001 C CNN + 1 5650 7450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 4C6552B4 +P 2200 7500 +F 0 "#PWR02" H 2200 7500 30 0001 C CNN +F 1 "GND" H 2200 7430 30 0001 C CNN + 1 2200 7500 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 4C6552B3 +P 2850 5550 +F 0 "#PWR03" H 2850 5550 30 0001 C CNN +F 1 "GND" H 2850 5480 30 0001 C CNN + 1 2850 5550 + 1 0 0 -1 +$EndComp +$Comp +L +2.5V #PWR04 +U 1 1 4C6552B2 +P 1600 6150 +F 0 "#PWR04" H 1600 6100 20 0001 C CNN +F 1 "+2.5V" H 1600 6250 30 0000 C CNN + 1 1600 6150 + 1 0 0 -1 +$EndComp +Text GLabel 2550 6100 3 40 BiDi ~ 0 +3.3V +Text Notes 2600 6250 0 60 ~ 0 +Warning!! VIF = 2.5!! ToDo: review the DS\n +$Comp +L INDUCTOR L7 +U 1 1 4C6552B1 +P 4600 7050 +F 0 "L7" V 4550 7050 40 0000 C CNN +F 1 "FB" V 4700 7050 40 0000 C CNN +F 2 "0603" H 4600 7050 60 0001 C CNN + 1 4600 7050 + 1 0 0 -1 +$EndComp +$Comp +L INDUCTOR L6 +U 1 1 4C6552B0 +P 4400 6050 +F 0 "L6" V 4350 6050 40 0000 C CNN +F 1 "FB" V 4500 6050 40 0000 C CNN +F 2 "0603" H 4400 6050 60 0001 C CNN + 1 4400 6050 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR05 +U 1 1 4C6552AF +P 4400 5050 +F 0 "#PWR05" H 4400 5140 20 0001 C CNN +F 1 "+5V" H 4400 5140 30 0000 C CNN + 1 4400 5050 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR06 +U 1 1 4C6552AE +P 4600 7400 +F 0 "#PWR06" H 4600 7400 30 0001 C CNN +F 1 "GND" H 4600 7330 30 0001 C CNN + 1 4600 7400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4600 7350 4600 7400 +Wire Wire Line + 4400 5650 4400 5750 +Wire Wire Line + 1550 6850 1550 7400 +Wire Wire Line + 3300 7300 3300 7400 +Wire Wire Line + 3300 6550 3300 6650 +Wire Wire Line + 1700 6750 1650 6750 +Wire Wire Line + 1700 6550 1650 6550 +Wire Wire Line + 1700 6350 1650 6350 +Wire Wire Line + 1700 6250 1600 6250 +Connection ~ 2950 7400 +Connection ~ 5650 7350 +Wire Wire Line + 5650 7350 5650 7450 +Connection ~ 5500 6450 +Wire Wire Line + 5350 6450 5500 6450 +Wire Wire Line + 5800 7200 5800 7350 +Wire Wire Line + 5800 7350 5500 7350 +Wire Wire Line + 5500 7350 5500 7150 +Wire Wire Line + 5800 6700 5800 6650 +Wire Wire Line + 5800 6650 5350 6650 +Connection ~ 3300 6550 +Wire Wire Line + 4700 6450 3700 6450 +Wire Wire Line + 3700 6450 3700 6500 +Wire Wire Line + 3700 6500 3600 6500 +Wire Wire Line + 3600 6500 3600 6550 +Wire Wire Line + 3600 6550 2450 6550 +Wire Wire Line + 3200 5000 3200 4850 +Wire Wire Line + 3200 4850 2500 4850 +Wire Wire Line + 2500 4850 2500 5000 +Connection ~ 2850 5500 +Wire Wire Line + 2500 5400 2500 5500 +Wire Wire Line + 2500 5500 3200 5500 +Wire Wire Line + 3200 5500 3200 5400 +Connection ~ 2850 4850 +Wire Wire Line + 4700 6550 3650 6550 +Wire Wire Line + 3650 6550 3650 6450 +Wire Wire Line + 3650 6450 2450 6450 +Connection ~ 2950 6450 +Wire Wire Line + 4400 6350 4700 6350 +Connection ~ 5500 6650 +Wire Wire Line + 5350 6350 5500 6350 +Wire Wire Line + 5500 6350 5500 6750 +Wire Wire Line + 5350 6550 5500 6550 +Connection ~ 5500 6550 +Wire Wire Line + 4700 6650 4600 6650 +Connection ~ 2200 7400 +Wire Wire Line + 1550 6850 1700 6850 +Wire Wire Line + 3300 7400 1550 7400 +Wire Wire Line + 1700 6450 1650 6450 +Wire Wire Line + 1700 6650 1650 6650 +Wire Wire Line + 2850 5400 2850 5550 +Wire Wire Line + 2950 6450 2950 6650 +Wire Wire Line + 2950 7400 2950 7300 +Wire Wire Line + 2200 7500 2200 7050 +Wire Wire Line + 1600 6250 1600 6150 +Wire Wire Line + 2550 6100 2550 6350 +Wire Wire Line + 2550 6350 2450 6350 +Wire Wire Line + 2450 6250 2550 6250 +Connection ~ 2550 6250 +Wire Wire Line + 4400 5100 4400 5050 +Wire Wire Line + 4600 6650 4600 6750 +Wire Wire Line + 2850 4750 2850 5000 +Text Notes 2850 4700 0 60 ~ 0 +? Text Notes 2800 1000 0 60 ~ 0 ? Wire Wire Line @@ -169,19 +451,19 @@ Wire Wire Line Wire Wire Line 4550 3650 4550 3700 $Comp -L GND #PWR01 +L GND #PWR07 U 1 1 4C63F2B5 P 4550 3700 -F 0 "#PWR01" H 4550 3700 30 0001 C CNN +F 0 "#PWR07" H 4550 3700 30 0001 C CNN F 1 "GND" H 4550 3630 30 0001 C CNN 1 4550 3700 1 0 0 -1 $EndComp $Comp -L +5V #PWR02 +L +5V #PWR08 U 1 1 4C63F295 P 4350 1350 -F 0 "#PWR02" H 4350 1440 20 0001 C CNN +F 0 "#PWR08" H 4350 1440 20 0001 C CNN F 1 "+5V" H 4350 1440 30 0000 C CNN 1 4350 1350 1 0 0 -1 @@ -211,37 +493,37 @@ Warning!! VIF = 2.5!! ToDo: review the DS\n Text GLabel 2500 2400 3 40 BiDi ~ 0 3.3V $Comp -L +2.5V #PWR03 +L +2.5V #PWR09 U 1 1 4C63EC16 P 1550 2450 -F 0 "#PWR03" H 1550 2400 20 0001 C CNN +F 0 "#PWR09" H 1550 2400 20 0001 C CNN F 1 "+2.5V" H 1550 2550 30 0000 C CNN 1 1550 2450 1 0 0 -1 $EndComp $Comp -L GND #PWR04 +L GND #PWR010 U 1 1 4C63EA2A P 2800 1850 -F 0 "#PWR04" H 2800 1850 30 0001 C CNN +F 0 "#PWR010" H 2800 1850 30 0001 C CNN F 1 "GND" H 2800 1780 30 0001 C CNN 1 2800 1850 1 0 0 -1 $EndComp $Comp -L GND #PWR05 +L GND #PWR011 U 1 1 4C63EA1B P 2150 3800 -F 0 "#PWR05" H 2150 3800 30 0001 C CNN +F 0 "#PWR011" H 2150 3800 30 0001 C CNN F 1 "GND" H 2150 3730 30 0001 C CNN 1 2150 3800 1 0 0 -1 $EndComp $Comp -L GND #PWR06 +L GND #PWR012 U 1 1 4C63E9FA P 5600 3750 -F 0 "#PWR06" H 5600 3750 30 0001 C CNN +F 0 "#PWR012" H 5600 3750 30 0001 C CNN F 1 "GND" H 5600 3680 30 0001 C CNN 1 5600 3750 1 0 0 -1 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 9238c18..64275fa 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 09:19:35 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 753507a..5f007fe 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Thu 12 Aug 2010 09:08:15 PM COT +EESchema-LIBRARY Version 2.3 Date: Fri 13 Aug 2010 09:19:35 AM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 915e4c8..5b699a6 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Fri 13 Aug 2010 06:14:57 AM COT +PCBNEW-BOARD Version 1 date Fri 13 Aug 2010 09:21:41 AM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -6,15 +6,15 @@ $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 1FFF801F -Links 431 -NoConn 431 -Di 39754 11114 68579 39600 +Links 451 +NoConn 451 +Di -1750 -2094 68579 39600 Ndraw 2 Ntrack 0 Nzone 0 BoardThickness 630 -Nmodule 65 -Nnets 158 +Nmodule 76 +Nnets 163 $EndGENERAL $SHEETDESCR @@ -86,511 +86,511 @@ Na 4 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/DDR_Banks/M0_A11" +Na 5 "/DDR_Ban101" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A3" +Na 6 "/DDR_Ban103" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_A7" +Na 7 "/DDR_Ban105" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_A8" +Na 8 "/DDR_Ban109" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_CAS#" +Na 9 "/DDR_Ban112" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_CKE" +Na 10 "/DDR_Ban115" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_CLK" +Na 11 "/DDR_Ban119" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_CLK#" +Na 12 "/DDR_Ban121" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_DQ10" +Na 13 "/DDR_Ban27" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_DQ14" +Na 14 "/DDR_Ban38" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_DQ2" +Na 15 "/DDR_Ban39" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_DQ3" +Na 16 "/DDR_Ban48" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_DQ4" +Na 17 "/DDR_Ban57" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_LDM" +Na 18 "/DDR_Ban59" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_RAS#" +Na 19 "/DDR_Ban64" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M0_WE#" +Na 20 "/DDR_Ban65" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M1_A10" +Na 21 "/DDR_Ban72" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M1_A5" +Na 22 "/DDR_Ban76" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_A8" +Na 23 "/DDR_Ban77" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_BA1" +Na 24 "/DDR_Ban88" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_CKE" +Na 25 "/DDR_Ban89" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_CLK" +Na 26 "/DDR_Ban90" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_DQ12" +Na 27 "/DDR_Ban91" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_DQ3" +Na 28 "/DDR_Ban96" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_DQ4" +Na 29 "/DDR_Ban97" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_DQ6" +Na 30 "/DDR_Ban98" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_DQ7" +Na 31 "/DDR_Ban99" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_LDQS" +Na 32 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_RAS#" +Na 33 "/DDR_Banks/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_UDM" +Na 34 "/Etherne1" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_WE#" +Na 35 "/Etherne11" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/Ethernet_Phy/ETH_1.8V" +Na 36 "/Etherne12" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/Ethernet_Phy/ETH_A1.8V" +Na 37 "/Etherne13" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/Ethernet_Phy/ETH_A3.3V" +Na 38 "/Etherne14" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/Ethernet_Phy/ETH_COL" +Na 39 "/Etherne15" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Ethernet_Phy/ETH_INT" +Na 40 "/Etherne18" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_LED0" +Na 41 "/Etherne2" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_LED1" +Na 42 "/Etherne23" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_MDC" +Na 43 "/Etherne25" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_MDIO" +Na 44 "/Etherne28" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_PLL1.8V" +Na 45 "/Etherne3" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_RXD0" +Na 46 "/Etherne30" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_RXD1" +Na 47 "/Etherne31" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_TXD1" +Na 48 "/Etherne32" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_TXD2" +Na 49 "/Etherne4" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/ETH_TXEN" +Na 50 "/Etherne41" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/FPGA_Spartan6/ETH_CLK" +Na 51 "/Etherne43" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Spartan6/ETH_CRS" +Na 52 "/FPGA_Sp100" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Spartan6/ETH_RESET_N" +Na 53 "/FPGA_Sp102" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Spartan6/ETH_RXC" +Na 54 "/FPGA_Sp104" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Spartan6/ETH_RXD2" +Na 55 "/FPGA_Sp106" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/ETH_RXD3" +Na 56 "/FPGA_Sp107" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/ETH_RXDV" +Na 57 "/FPGA_Sp108" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/ETH_RXER" +Na 58 "/FPGA_Sp110" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/ETH_TXC" +Na 59 "/FPGA_Sp111" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/ETH_TXD0" +Na 60 "/FPGA_Sp113" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/ETH_TXD3" +Na 61 "/FPGA_Sp114" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/ETH_TXER" +Na 62 "/FPGA_Sp116" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/M0_A0" +Na 63 "/FPGA_Sp117" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/M0_A1" +Na 64 "/FPGA_Sp118" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/M0_A10" +Na 65 "/FPGA_Sp120" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/M0_A12" +Na 66 "/FPGA_Sp122" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/M0_A2" +Na 67 "/FPGA_Sp123" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/M0_A4" +Na 68 "/FPGA_Sp16" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_A5" +Na 69 "/FPGA_Sp17" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_A6" +Na 70 "/FPGA_Sp19" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_A9" +Na 71 "/FPGA_Sp20" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_BA0" +Na 72 "/FPGA_Sp22" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_BA1" +Na 73 "/FPGA_Sp24" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_DQ0" +Na 74 "/FPGA_Sp29" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_DQ1" +Na 75 "/FPGA_Sp33" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_DQ11" +Na 76 "/FPGA_Sp34" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_DQ12" +Na 77 "/FPGA_Sp35" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_DQ13" +Na 78 "/FPGA_Sp36" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_DQ15" +Na 79 "/FPGA_Sp37" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_DQ5" +Na 80 "/FPGA_Sp40" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_DQ6" +Na 81 "/FPGA_Sp42" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_DQ7" +Na 82 "/FPGA_Sp44" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_DQ8" +Na 83 "/FPGA_Sp47" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_DQ9" +Na 84 "/FPGA_Sp49" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M0_LDQS" +Na 85 "/FPGA_Sp50" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M0_UDM" +Na 86 "/FPGA_Sp51" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M0_UDQS" +Na 87 "/FPGA_Sp52" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M1_A0" +Na 88 "/FPGA_Sp53" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M1_A1" +Na 89 "/FPGA_Sp54" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M1_A11" +Na 90 "/FPGA_Sp55" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M1_A12" +Na 91 "/FPGA_Sp56" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M1_A2" +Na 92 "/FPGA_Sp58" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M1_A3" +Na 93 "/FPGA_Sp60" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_A4" +Na 94 "/FPGA_Sp61" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_A6" +Na 95 "/FPGA_Sp62" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_A7" +Na 96 "/FPGA_Sp63" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_A9" +Na 97 "/FPGA_Sp66" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_BA0" +Na 98 "/FPGA_Sp67" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_CAS#" +Na 99 "/FPGA_Sp68" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_CLK#" +Na 100 "/FPGA_Sp69" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_DQ0" +Na 101 "/FPGA_Sp7" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_DQ1" +Na 102 "/FPGA_Sp70" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_DQ10" +Na 103 "/FPGA_Sp71" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_DQ11" +Na 104 "/FPGA_Sp73" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ13" +Na 105 "/FPGA_Sp74" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_DQ14" +Na 106 "/FPGA_Sp75" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_DQ15" +Na 107 "/FPGA_Sp78" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_DQ2" +Na 108 "/FPGA_Sp79" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ5" +Na 109 "/FPGA_Sp8" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_DQ8" +Na 110 "/FPGA_Sp80" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_DQ9" +Na 111 "/FPGA_Sp81" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Spartan6/M1_LDM" +Na 112 "/FPGA_Sp82" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_UDQS" +Na 113 "/FPGA_Sp83" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Spartan6/NF_D1" +Na 114 "/FPGA_Sp84" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/NF_D2" +Na 115 "/FPGA_Sp85" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/NF_D3" +Na 116 "/FPGA_Sp86" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Spartan6/NF_D4" +Na 117 "/FPGA_Sp87" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA_Spartan6/NF_D6" +Na 118 "/FPGA_Sp9" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/SD_CLK" +Na 119 "/FPGA_Sp92" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Spartan6/SD_DAT1" +Na 120 "/FPGA_Sp93" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Spartan6/USBA_RCV" +Na 121 "/FPGA_Sp94" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Spartan6/USBA_VP" +Na 122 "/FPGA_Sp95" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/Non_volatile_memories/NF_D0" +Na 123 "/Non_vol10" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/Non_volatile_memories/NF_D5" +Na 124 "/Non_vol124" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/Non_volatile_memories/NF_D7" +Na 125 "/Non_vol21" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/Non_volatile_memories/NF_RNB" +Na 126 "/Non_vol26" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/Non_volatile_memories/SD_CMD" +Na 127 "/Non_vol45" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/Non_volatile_memories/SD_DAT0" +Na 128 "/Non_vol46" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/Non_volatile_memories/SD_DAT2" +Na 129 "/Non_vol5" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/Non_volatile_memories/SD_DAT3" +Na 130 "/Non_vol6" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/USB/USBA_OE_N" +Na 131 "/USB/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT @@ -626,7 +626,7 @@ Na 139 "N-000053" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "N-000110" +Na 140 "N-000156" St ~ $EndEQUIPOT $EQUIPOT @@ -674,27 +674,47 @@ Na 151 "N-000349" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "N-000350" +Na 152 "N-000353" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "N-000351" +Na 153 "N-000356" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "N-000353" +Na 154 "N-000358" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "N-000354" +Na 155 "N-000359" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "N-000355" +Na 156 "N-000362" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "N-000356" +Na 157 "N-000363" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 158 "N-000364" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 159 "N-000365" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 160 "N-000366" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 161 "N-000367" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 162 "N-000368" St ~ $EndEQUIPOT $NCLASS @@ -711,133 +731,133 @@ AddNet "+1.2V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" -AddNet "/DDR_Banks/M0_A11" -AddNet "/DDR_Banks/M0_A3" -AddNet "/DDR_Banks/M0_A7" +AddNet "/DDR_Ban101" +AddNet "/DDR_Ban103" +AddNet "/DDR_Ban105" +AddNet "/DDR_Ban109" +AddNet "/DDR_Ban112" +AddNet "/DDR_Ban115" +AddNet "/DDR_Ban119" +AddNet "/DDR_Ban121" +AddNet "/DDR_Ban27" +AddNet "/DDR_Ban38" +AddNet "/DDR_Ban39" +AddNet "/DDR_Ban48" +AddNet "/DDR_Ban57" +AddNet "/DDR_Ban59" +AddNet "/DDR_Ban64" +AddNet "/DDR_Ban65" +AddNet "/DDR_Ban72" +AddNet "/DDR_Ban76" +AddNet "/DDR_Ban77" +AddNet "/DDR_Ban88" +AddNet "/DDR_Ban89" +AddNet "/DDR_Ban90" +AddNet "/DDR_Ban91" +AddNet "/DDR_Ban96" +AddNet "/DDR_Ban97" +AddNet "/DDR_Ban98" +AddNet "/DDR_Ban99" AddNet "/DDR_Banks/M0_A8" -AddNet "/DDR_Banks/M0_CAS#" -AddNet "/DDR_Banks/M0_CKE" -AddNet "/DDR_Banks/M0_CLK" -AddNet "/DDR_Banks/M0_CLK#" -AddNet "/DDR_Banks/M0_DQ10" -AddNet "/DDR_Banks/M0_DQ14" -AddNet "/DDR_Banks/M0_DQ2" -AddNet "/DDR_Banks/M0_DQ3" -AddNet "/DDR_Banks/M0_DQ4" -AddNet "/DDR_Banks/M0_LDM" -AddNet "/DDR_Banks/M0_RAS#" -AddNet "/DDR_Banks/M0_WE#" -AddNet "/DDR_Banks/M1_A10" -AddNet "/DDR_Banks/M1_A5" -AddNet "/DDR_Banks/M1_A8" -AddNet "/DDR_Banks/M1_BA1" -AddNet "/DDR_Banks/M1_CKE" -AddNet "/DDR_Banks/M1_CLK" -AddNet "/DDR_Banks/M1_DQ12" -AddNet "/DDR_Banks/M1_DQ3" -AddNet "/DDR_Banks/M1_DQ4" -AddNet "/DDR_Banks/M1_DQ6" -AddNet "/DDR_Banks/M1_DQ7" -AddNet "/DDR_Banks/M1_LDQS" -AddNet "/DDR_Banks/M1_RAS#" -AddNet "/DDR_Banks/M1_UDM" -AddNet "/DDR_Banks/M1_WE#" -AddNet "/Ethernet_Phy/ETH_1.8V" -AddNet "/Ethernet_Phy/ETH_A1.8V" -AddNet "/Ethernet_Phy/ETH_A3.3V" -AddNet "/Ethernet_Phy/ETH_COL" -AddNet "/Ethernet_Phy/ETH_INT" -AddNet "/Ethernet_Phy/ETH_LED0" -AddNet "/Ethernet_Phy/ETH_LED1" -AddNet "/Ethernet_Phy/ETH_MDC" -AddNet "/Ethernet_Phy/ETH_MDIO" -AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/ETH_RXD0" -AddNet "/Ethernet_Phy/ETH_RXD1" -AddNet "/Ethernet_Phy/ETH_TXD1" -AddNet "/Ethernet_Phy/ETH_TXD2" -AddNet "/Ethernet_Phy/ETH_TXEN" -AddNet "/FPGA_Spartan6/ETH_CLK" -AddNet "/FPGA_Spartan6/ETH_CRS" -AddNet "/FPGA_Spartan6/ETH_RESET_N" -AddNet "/FPGA_Spartan6/ETH_RXC" -AddNet "/FPGA_Spartan6/ETH_RXD2" -AddNet "/FPGA_Spartan6/ETH_RXD3" -AddNet "/FPGA_Spartan6/ETH_RXDV" -AddNet "/FPGA_Spartan6/ETH_RXER" -AddNet "/FPGA_Spartan6/ETH_TXC" -AddNet "/FPGA_Spartan6/ETH_TXD0" -AddNet "/FPGA_Spartan6/ETH_TXD3" -AddNet "/FPGA_Spartan6/ETH_TXER" -AddNet "/FPGA_Spartan6/M0_A0" -AddNet "/FPGA_Spartan6/M0_A1" -AddNet "/FPGA_Spartan6/M0_A10" -AddNet "/FPGA_Spartan6/M0_A12" -AddNet "/FPGA_Spartan6/M0_A2" -AddNet "/FPGA_Spartan6/M0_A4" -AddNet "/FPGA_Spartan6/M0_A5" -AddNet "/FPGA_Spartan6/M0_A6" -AddNet "/FPGA_Spartan6/M0_A9" -AddNet "/FPGA_Spartan6/M0_BA0" -AddNet "/FPGA_Spartan6/M0_BA1" -AddNet "/FPGA_Spartan6/M0_DQ0" -AddNet "/FPGA_Spartan6/M0_DQ1" -AddNet "/FPGA_Spartan6/M0_DQ11" -AddNet "/FPGA_Spartan6/M0_DQ12" -AddNet "/FPGA_Spartan6/M0_DQ13" -AddNet "/FPGA_Spartan6/M0_DQ15" -AddNet "/FPGA_Spartan6/M0_DQ5" -AddNet "/FPGA_Spartan6/M0_DQ6" -AddNet "/FPGA_Spartan6/M0_DQ7" -AddNet "/FPGA_Spartan6/M0_DQ8" -AddNet "/FPGA_Spartan6/M0_DQ9" -AddNet "/FPGA_Spartan6/M0_LDQS" -AddNet "/FPGA_Spartan6/M0_UDM" -AddNet "/FPGA_Spartan6/M0_UDQS" -AddNet "/FPGA_Spartan6/M1_A0" -AddNet "/FPGA_Spartan6/M1_A1" -AddNet "/FPGA_Spartan6/M1_A11" -AddNet "/FPGA_Spartan6/M1_A12" -AddNet "/FPGA_Spartan6/M1_A2" -AddNet "/FPGA_Spartan6/M1_A3" -AddNet "/FPGA_Spartan6/M1_A4" -AddNet "/FPGA_Spartan6/M1_A6" -AddNet "/FPGA_Spartan6/M1_A7" -AddNet "/FPGA_Spartan6/M1_A9" -AddNet "/FPGA_Spartan6/M1_BA0" -AddNet "/FPGA_Spartan6/M1_CAS#" -AddNet "/FPGA_Spartan6/M1_CLK#" -AddNet "/FPGA_Spartan6/M1_DQ0" -AddNet "/FPGA_Spartan6/M1_DQ1" -AddNet "/FPGA_Spartan6/M1_DQ10" -AddNet "/FPGA_Spartan6/M1_DQ11" -AddNet "/FPGA_Spartan6/M1_DQ13" -AddNet "/FPGA_Spartan6/M1_DQ14" -AddNet "/FPGA_Spartan6/M1_DQ15" -AddNet "/FPGA_Spartan6/M1_DQ2" -AddNet "/FPGA_Spartan6/M1_DQ5" -AddNet "/FPGA_Spartan6/M1_DQ8" -AddNet "/FPGA_Spartan6/M1_DQ9" -AddNet "/FPGA_Spartan6/M1_LDM" -AddNet "/FPGA_Spartan6/M1_UDQS" -AddNet "/FPGA_Spartan6/NF_D1" -AddNet "/FPGA_Spartan6/NF_D2" -AddNet "/FPGA_Spartan6/NF_D3" -AddNet "/FPGA_Spartan6/NF_D4" -AddNet "/FPGA_Spartan6/NF_D6" -AddNet "/FPGA_Spartan6/SD_CLK" -AddNet "/FPGA_Spartan6/SD_DAT1" -AddNet "/FPGA_Spartan6/USBA_RCV" -AddNet "/FPGA_Spartan6/USBA_VP" -AddNet "/Non_volatile_memories/NF_D0" -AddNet "/Non_volatile_memories/NF_D5" -AddNet "/Non_volatile_memories/NF_D7" -AddNet "/Non_volatile_memories/NF_RNB" -AddNet "/Non_volatile_memories/SD_CMD" -AddNet "/Non_volatile_memories/SD_DAT0" -AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "/Non_volatile_memories/SD_DAT3" -AddNet "/USB/USBA_OE_N" +AddNet "/DDR_Banks/M1_A4" +AddNet "/Etherne1" +AddNet "/Etherne11" +AddNet "/Etherne12" +AddNet "/Etherne13" +AddNet "/Etherne14" +AddNet "/Etherne15" +AddNet "/Etherne18" +AddNet "/Etherne2" +AddNet "/Etherne23" +AddNet "/Etherne25" +AddNet "/Etherne28" +AddNet "/Etherne3" +AddNet "/Etherne30" +AddNet "/Etherne31" +AddNet "/Etherne32" +AddNet "/Etherne4" +AddNet "/Etherne41" +AddNet "/Etherne43" +AddNet "/FPGA_Sp100" +AddNet "/FPGA_Sp102" +AddNet "/FPGA_Sp104" +AddNet "/FPGA_Sp106" +AddNet "/FPGA_Sp107" +AddNet "/FPGA_Sp108" +AddNet "/FPGA_Sp110" +AddNet "/FPGA_Sp111" +AddNet "/FPGA_Sp113" +AddNet "/FPGA_Sp114" +AddNet "/FPGA_Sp116" +AddNet "/FPGA_Sp117" +AddNet "/FPGA_Sp118" +AddNet "/FPGA_Sp120" +AddNet "/FPGA_Sp122" +AddNet "/FPGA_Sp123" +AddNet "/FPGA_Sp16" +AddNet "/FPGA_Sp17" +AddNet "/FPGA_Sp19" +AddNet "/FPGA_Sp20" +AddNet "/FPGA_Sp22" +AddNet "/FPGA_Sp24" +AddNet "/FPGA_Sp29" +AddNet "/FPGA_Sp33" +AddNet "/FPGA_Sp34" +AddNet "/FPGA_Sp35" +AddNet "/FPGA_Sp36" +AddNet "/FPGA_Sp37" +AddNet "/FPGA_Sp40" +AddNet "/FPGA_Sp42" +AddNet "/FPGA_Sp44" +AddNet "/FPGA_Sp47" +AddNet "/FPGA_Sp49" +AddNet "/FPGA_Sp50" +AddNet "/FPGA_Sp51" +AddNet "/FPGA_Sp52" +AddNet "/FPGA_Sp53" +AddNet "/FPGA_Sp54" +AddNet "/FPGA_Sp55" +AddNet "/FPGA_Sp56" +AddNet "/FPGA_Sp58" +AddNet "/FPGA_Sp60" +AddNet "/FPGA_Sp61" +AddNet "/FPGA_Sp62" +AddNet "/FPGA_Sp63" +AddNet "/FPGA_Sp66" +AddNet "/FPGA_Sp67" +AddNet "/FPGA_Sp68" +AddNet "/FPGA_Sp69" +AddNet "/FPGA_Sp7" +AddNet "/FPGA_Sp70" +AddNet "/FPGA_Sp71" +AddNet "/FPGA_Sp73" +AddNet "/FPGA_Sp74" +AddNet "/FPGA_Sp75" +AddNet "/FPGA_Sp78" +AddNet "/FPGA_Sp79" +AddNet "/FPGA_Sp8" +AddNet "/FPGA_Sp80" +AddNet "/FPGA_Sp81" +AddNet "/FPGA_Sp82" +AddNet "/FPGA_Sp83" +AddNet "/FPGA_Sp84" +AddNet "/FPGA_Sp85" +AddNet "/FPGA_Sp86" +AddNet "/FPGA_Sp87" +AddNet "/FPGA_Sp9" +AddNet "/FPGA_Sp92" +AddNet "/FPGA_Sp93" +AddNet "/FPGA_Sp94" +AddNet "/FPGA_Sp95" +AddNet "/Non_vol10" +AddNet "/Non_vol124" +AddNet "/Non_vol21" +AddNet "/Non_vol26" +AddNet "/Non_vol45" +AddNet "/Non_vol46" +AddNet "/Non_vol5" +AddNet "/Non_vol6" +AddNet "/USB/USBA_RCV" AddNet "/USB/USBA_SPD" AddNet "/USB/USBA_VM" AddNet "3.3V" @@ -846,7 +866,7 @@ AddNet "N-000049" AddNet "N-000050" AddNet "N-000051" AddNet "N-000053" -AddNet "N-000110" +AddNet "N-000156" AddNet "N-000327" AddNet "N-000328" AddNet "N-000329" @@ -858,12 +878,17 @@ AddNet "N-000339" AddNet "N-000340" AddNet "N-000343" AddNet "N-000349" -AddNet "N-000350" -AddNet "N-000351" AddNet "N-000353" -AddNet "N-000354" -AddNet "N-000355" AddNet "N-000356" +AddNet "N-000358" +AddNet "N-000359" +AddNet "N-000362" +AddNet "N-000363" +AddNet "N-000364" +AddNet "N-000365" +AddNet "N-000366" +AddNet "N-000367" +AddNet "N-000368" $EndNCLASS $MODULE FGG484bga-p10 Po 56450 33930 0 15 4C4325AE 4C431E53 ~~ @@ -907,70 +932,70 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_INT" +Ne 38 "/Etherne14" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_MDIO" +Ne 35 "/Etherne11" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_RXD1" +Ne 39 "/Etherne15" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RXDV" +Ne 68 "/FPGA_Sp16" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_TXER" +Ne 69 "/FPGA_Sp17" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_TXD2" +Ne 40 "/Etherne18" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_COL" +Ne 70 "/FPGA_Sp19" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/Non_volatile_memories/NF_D7" +Ne 71 "/FPGA_Sp20" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_D3" +Ne 125 "/Non_vol21" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/NF_D1" +Ne 72 "/FPGA_Sp22" Po 590 -4133 $EndPAD $PAD @@ -998,14 +1023,14 @@ $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/Non_volatile_memories/SD_DAT2" +Ne 129 "/Non_vol5" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/Non_volatile_memories/SD_DAT0" +Ne 118 "/FPGA_Sp9" Po 2558 -4133 $EndPAD $PAD @@ -1075,7 +1100,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_RXD2" +Ne 42 "/Etherne23" Po -2165 -3739 $EndPAD $PAD @@ -1089,7 +1114,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RXER" +Ne 73 "/FPGA_Sp24" Po -1377 -3739 $EndPAD $PAD @@ -1103,7 +1128,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_CRS" +Ne 43 "/Etherne25" Po -590 -3739 $EndPAD $PAD @@ -1117,7 +1142,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_D4" +Ne 126 "/Non_vol26" Po 196 -3739 $EndPAD $PAD @@ -1159,7 +1184,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/SD_DAT1" +Ne 123 "/Non_vol10" Po 2558 -3739 $EndPAD $PAD @@ -1194,7 +1219,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_A11" +Ne 13 "/DDR_Ban27" Po -4133 -3346 $EndPAD $PAD @@ -1222,42 +1247,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_MDC" +Ne 44 "/Etherne28" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_RXD3" +Ne 74 "/FPGA_Sp29" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_RXD0" +Ne 46 "/Etherne30" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_TXD0" +Ne 47 "/Etherne31" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_TXD1" +Ne 48 "/Etherne32" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/ETH_CLK" +Ne 75 "/FPGA_Sp33" Po -590 -3346 $EndPAD $PAD @@ -1271,14 +1296,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/Non_volatile_memories/NF_D5" +Ne 76 "/FPGA_Sp34" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_D2" +Ne 77 "/FPGA_Sp35" Po 590 -3346 $EndPAD $PAD @@ -1306,7 +1331,7 @@ $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/Non_volatile_memories/SD_DAT3" +Ne 130 "/Non_vol6" Po 2165 -3346 $EndPAD $PAD @@ -1327,7 +1352,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A8" +Ne 78 "/FPGA_Sp36" Po 3346 -3346 $EndPAD $PAD @@ -1341,21 +1366,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_A9" +Ne 79 "/FPGA_Sp37" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A12" +Ne 14 "/DDR_Ban38" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_CKE" +Ne 15 "/DDR_Ban39" Po -3739 -2952 $EndPAD $PAD @@ -1383,42 +1408,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_RESET_N" +Ne 80 "/FPGA_Sp40" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_TXD3" +Ne 50 "/Etherne41" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_TXC" +Ne 81 "/FPGA_Sp42" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_TXEN" +Ne 51 "/Etherne43" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_RXC" +Ne 82 "/FPGA_Sp44" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/NF_D6" +Ne 127 "/Non_vol45" Po -196 -2952 $EndPAD $PAD @@ -1439,7 +1464,7 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/Non_volatile_memories/NF_D0" +Ne 128 "/Non_vol46" Po 983 -2952 $EndPAD $PAD @@ -1460,7 +1485,7 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/Non_volatile_memories/SD_CMD" +Ne 101 "/FPGA_Sp7" Po 2165 -2952 $EndPAD $PAD @@ -1488,21 +1513,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_CKE" +Ne 83 "/FPGA_Sp47" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A12" +Ne 16 "/DDR_Ban48" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A9" +Ne 84 "/FPGA_Sp49" Po -4133 -2558 $EndPAD $PAD @@ -1516,7 +1541,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A8" +Ne 32 "/DDR_Banks/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1607,7 +1632,7 @@ $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/SD_CLK" +Ne 109 "/FPGA_Sp8" Po 1771 -2558 $EndPAD $PAD @@ -1635,7 +1660,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_A7" +Ne 85 "/FPGA_Sp50" Po 3346 -2558 $EndPAD $PAD @@ -1649,7 +1674,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A2" +Ne 86 "/FPGA_Sp51" Po 4133 -2558 $EndPAD $PAD @@ -1663,14 +1688,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_WE#" +Ne 87 "/FPGA_Sp52" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A4" +Ne 88 "/FPGA_Sp53" Po -3346 -2165 $EndPAD $PAD @@ -1782,35 +1807,35 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A11" +Ne 89 "/FPGA_Sp54" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A4" +Ne 33 "/DDR_Banks/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M1_A0" +Ne 90 "/FPGA_Sp55" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A1" +Ne 91 "/FPGA_Sp56" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_BA1" +Ne 17 "/DDR_Ban57" Po -4133 -1771 $EndPAD $PAD @@ -1824,14 +1849,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_BA0" +Ne 92 "/FPGA_Sp58" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A10" +Ne 18 "/DDR_Ban59" Po -2952 -1771 $EndPAD $PAD @@ -1936,14 +1961,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_A10" +Ne 93 "/FPGA_Sp60" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_A3" +Ne 94 "/FPGA_Sp61" Po 3346 -1771 $EndPAD $PAD @@ -1964,42 +1989,42 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A1" +Ne 95 "/FPGA_Sp62" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M0_A0" +Ne 96 "/FPGA_Sp63" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_CLK#" +Ne 19 "/DDR_Ban64" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_CLK" +Ne 20 "/DDR_Ban65" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A2" +Ne 97 "/FPGA_Sp66" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A7" +Ne 98 "/FPGA_Sp67" Po -2165 -1377 $EndPAD $PAD @@ -2090,35 +2115,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_WE#" +Ne 99 "/FPGA_Sp68" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_CLK" +Ne 100 "/FPGA_Sp69" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_RAS#" +Ne 102 "/FPGA_Sp70" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_CAS#" +Ne 103 "/FPGA_Sp71" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ5" +Ne 21 "/DDR_Ban72" Po -4133 -983 $EndPAD $PAD @@ -2132,14 +2157,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ4" +Ne 104 "/FPGA_Sp73" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A6" +Ne 105 "/FPGA_Sp74" Po -2952 -983 $EndPAD $PAD @@ -2230,7 +2255,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_BA0" +Ne 106 "/FPGA_Sp75" Po 2165 -983 $EndPAD $PAD @@ -2244,14 +2269,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_CLK#" +Ne 22 "/DDR_Ban76" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_DQ4" +Ne 23 "/DDR_Ban77" Po 3346 -983 $EndPAD $PAD @@ -2265,49 +2290,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ5" +Ne 107 "/FPGA_Sp78" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ7" +Ne 108 "/FPGA_Sp79" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ6" +Ne 110 "/FPGA_Sp80" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A5" +Ne 111 "/FPGA_Sp81" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_CAS#" +Ne 112 "/FPGA_Sp82" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_RAS#" +Ne 113 "/FPGA_Sp83" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A3" +Ne 114 "/FPGA_Sp84" Po -2165 -590 $EndPAD $PAD @@ -2384,7 +2409,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_BA1" +Ne 115 "/FPGA_Sp85" Po 2165 -590 $EndPAD $PAD @@ -2398,28 +2423,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A6" +Ne 116 "/FPGA_Sp86" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_A5" +Ne 117 "/FPGA_Sp87" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ6" +Ne 24 "/DDR_Ban88" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ7" +Ne 25 "/DDR_Ban89" Po 4133 -590 $EndPAD $PAD @@ -2440,14 +2465,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_LDQS" +Ne 26 "/DDR_Ban90" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_LDM" +Ne 27 "/DDR_Ban91" Po -2952 -196 $EndPAD $PAD @@ -2552,14 +2577,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_LDM" +Ne 119 "/FPGA_Sp92" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_LDQS" +Ne 120 "/FPGA_Sp93" Po 3346 -196 $EndPAD $PAD @@ -2580,21 +2605,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ3" +Ne 121 "/FPGA_Sp94" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ2" +Ne 122 "/FPGA_Sp95" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_UDM" +Ne 28 "/DDR_Ban96" Po -3346 196 $EndPAD $PAD @@ -2713,28 +2738,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_UDM" +Ne 29 "/DDR_Ban97" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ2" +Ne 30 "/DDR_Ban98" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_DQ3" +Ne 31 "/DDR_Ban99" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_DQ1" +Ne 52 "/FPGA_Sp100" Po -4133 590 $EndPAD $PAD @@ -2748,7 +2773,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_DQ0" +Ne 5 "/DDR_Ban101" Po -3346 590 $EndPAD $PAD @@ -2839,7 +2864,7 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/USBA_RCV" +Ne 131 "/USB/USBA_RCV" Po 1771 590 $EndPAD $PAD @@ -2867,7 +2892,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ0" +Ne 53 "/FPGA_Sp102" Po 3346 590 $EndPAD $PAD @@ -2881,21 +2906,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ1" +Ne 6 "/DDR_Ban103" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ9" +Ne 54 "/FPGA_Sp104" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ8" +Ne 7 "/DDR_Ban105" Po -3739 983 $EndPAD $PAD @@ -3000,14 +3025,14 @@ $PAD Sh "P17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/USBA_VP" +Ne 55 "/FPGA_Sp106" Po 2165 983 $EndPAD $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/USB/USBA_OE_N" +Ne 56 "/FPGA_Sp107" Po 2558 983 $EndPAD $PAD @@ -3028,21 +3053,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ8" +Ne 57 "/FPGA_Sp108" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_DQ9" +Ne 8 "/DDR_Ban109" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ11" +Ne 58 "/FPGA_Sp110" Po -4133 1377 $EndPAD $PAD @@ -3056,7 +3081,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ10" +Ne 59 "/FPGA_Sp111" Po -3346 1377 $EndPAD $PAD @@ -3175,7 +3200,7 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ10" +Ne 9 "/DDR_Ban112" Po 3346 1377 $EndPAD $PAD @@ -3189,7 +3214,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ11" +Ne 60 "/FPGA_Sp113" Po 4133 1377 $EndPAD $PAD @@ -3203,7 +3228,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_UDQS" +Ne 61 "/FPGA_Sp114" Po -3739 1771 $EndPAD $PAD @@ -3252,7 +3277,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po -983 1771 $EndPAD $PAD @@ -3280,7 +3305,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po 590 1771 $EndPAD $PAD @@ -3336,7 +3361,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_UDQS" +Ne 10 "/DDR_Ban115" Po 3739 1771 $EndPAD $PAD @@ -3350,7 +3375,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ13" +Ne 62 "/FPGA_Sp116" Po -4133 2165 $EndPAD $PAD @@ -3364,7 +3389,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ12" +Ne 63 "/FPGA_Sp117" Po -3346 2165 $EndPAD $PAD @@ -3483,7 +3508,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_DQ12" +Ne 64 "/FPGA_Sp118" Po 3346 2165 $EndPAD $PAD @@ -3497,21 +3522,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ13" +Ne 11 "/DDR_Ban119" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ15" +Ne 65 "/FPGA_Sp120" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ14" +Ne 12 "/DDR_Ban121" Po -3739 2558 $EndPAD $PAD @@ -3553,7 +3578,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po -1377 2558 $EndPAD $PAD @@ -3581,7 +3606,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po 196 2558 $EndPAD $PAD @@ -3609,7 +3634,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po 1771 2558 $EndPAD $PAD @@ -3644,14 +3669,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ14" +Ne 66 "/FPGA_Sp122" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ15" +Ne 67 "/FPGA_Sp123" Po 4133 2558 $EndPAD $PAD @@ -3686,7 +3711,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po -2558 2952 $EndPAD $PAD @@ -3980,7 +4005,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po -3346 3739 $EndPAD $PAD @@ -4008,7 +4033,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po -1771 3739 $EndPAD $PAD @@ -4036,7 +4061,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po -196 3739 $EndPAD $PAD @@ -4064,7 +4089,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po 1377 3739 $EndPAD $PAD @@ -4092,7 +4117,7 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000110" +Ne 140 "N-000156" Po 2952 3739 $EndPAD $PAD @@ -4296,21 +4321,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RXER" +Ne 73 "/FPGA_Sp24" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_RXC" +Ne 82 "/FPGA_Sp44" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RXDV" +Ne 68 "/FPGA_Sp16" Po -1613 491 $EndPAD $PAD @@ -4331,63 +4356,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_RXD0" +Ne 46 "/Etherne30" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_RXD1" +Ne 39 "/Etherne15" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_RXD2" +Ne 42 "/Etherne23" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_RXD3" +Ne 74 "/FPGA_Sp29" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_MDC" +Ne 44 "/Etherne28" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_MDIO" +Ne 35 "/Etherne11" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_RESET_N" +Ne 80 "/FPGA_Sp40" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 49 "/Etherne4" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/ETH_CLK" +Ne 75 "/FPGA_Sp33" Po -688 -1613 $EndPAD $PAD @@ -4443,7 +4468,7 @@ $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_A3.3V" +Ne 45 "/Etherne3" Po 885 -1613 $EndPAD $PAD @@ -4457,21 +4482,21 @@ $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_INT" +Ne 38 "/Etherne14" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_LED0" +Ne 36 "/Etherne12" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_LED1" +Ne 37 "/Etherne13" Po 1613 688 $EndPAD $PAD @@ -4499,7 +4524,7 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_A1.8V" +Ne 41 "/Etherne2" Po 1613 -98 $EndPAD $PAD @@ -4541,70 +4566,70 @@ $PAD Sh "13" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_1.8V" +Ne 34 "/Etherne1" Po -1082 1613 $EndPAD $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_TXER" +Ne 69 "/FPGA_Sp17" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_TXC" +Ne 81 "/FPGA_Sp42" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_TXEN" +Ne 51 "/Etherne43" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_TXD0" +Ne 47 "/Etherne31" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_TXD1" +Ne 48 "/Etherne32" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_TXD2" +Ne 40 "/Etherne18" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_TXD3" +Ne 50 "/Etherne41" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_COL" +Ne 70 "/FPGA_Sp19" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_CRS" +Ne 43 "/Etherne25" Po 688 1613 $EndPAD $PAD @@ -4882,14 +4907,14 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/Non_volatile_memories/NF_RNB" +Ne 124 "/Non_vol124" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/Non_volatile_memories/NF_RNB" +Ne 124 "/Non_vol124" Po -1090 3850 $EndPAD $PAD @@ -5043,28 +5068,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/Non_volatile_memories/NF_D0" +Ne 128 "/Non_vol46" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/NF_D1" +Ne 72 "/FPGA_Sp22" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_D2" +Ne 77 "/FPGA_Sp35" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_D3" +Ne 125 "/Non_vol21" Po 880 -3850 $EndPAD $PAD @@ -5127,28 +5152,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_D4" +Ne 126 "/Non_vol26" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/Non_volatile_memories/NF_D5" +Ne 76 "/FPGA_Sp34" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/NF_D6" +Ne 127 "/Non_vol45" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/Non_volatile_memories/NF_D7" +Ne 71 "/FPGA_Sp20" Po -1480 -3850 $EndPAD $PAD @@ -5201,21 +5226,21 @@ $PAD Sh "1" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 129 "/Non_volatile_memories/SD_DAT2" +Ne 129 "/Non_vol5" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 130 "/Non_volatile_memories/SD_DAT3" +Ne 130 "/Non_vol6" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 127 "/Non_volatile_memories/SD_CMD" +Ne 101 "/FPGA_Sp7" Po -433 0 $EndPAD $PAD @@ -5229,7 +5254,7 @@ $PAD Sh "5" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 119 "/FPGA_Spartan6/SD_CLK" +Ne 109 "/FPGA_Sp8" Po 433 0 $EndPAD $PAD @@ -5243,14 +5268,14 @@ $PAD Sh "7" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 128 "/Non_volatile_memories/SD_DAT0" +Ne 118 "/FPGA_Sp9" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 120 "/FPGA_Spartan6/SD_DAT1" +Ne 123 "/Non_vol10" Po 1732 0 $EndPAD $PAD @@ -5446,14 +5471,14 @@ $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 121 "/FPGA_Spartan6/USBA_RCV" +Ne 131 "/USB/USBA_RCV" Po -255 -1112 $EndPAD $PAD Sh "4" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 122 "/FPGA_Spartan6/USBA_VP" +Ne 55 "/FPGA_Sp106" Po 0 -1112 $EndPAD $PAD @@ -5488,21 +5513,21 @@ $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 131 "/USB/USBA_OE_N" +Ne 56 "/FPGA_Sp107" Po 511 1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 151 "N-000349" +Ne 159 "N-000365" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 154 "N-000353" +Ne 162 "N-000368" Po 0 1112 $EndPAD $PAD @@ -5552,7 +5577,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ0" +Ne 53 "/FPGA_Sp102" Po -3838 2176 $EndPAD $PAD @@ -5566,14 +5591,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ1" +Ne 6 "/DDR_Ban103" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ2" +Ne 30 "/DDR_Ban98" Po -3070 2176 $EndPAD $PAD @@ -5587,14 +5612,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_DQ3" +Ne 31 "/DDR_Ban99" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_DQ4" +Ne 23 "/DDR_Ban77" Po -2303 2176 $EndPAD $PAD @@ -5608,14 +5633,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ5" +Ne 107 "/FPGA_Sp78" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ6" +Ne 24 "/DDR_Ban88" Po -1535 2176 $EndPAD $PAD @@ -5629,7 +5654,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ7" +Ne 25 "/DDR_Ban89" Po -1023 2176 $EndPAD $PAD @@ -5650,7 +5675,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_LDQS" +Ne 120 "/FPGA_Sp93" Po -255 2176 $EndPAD $PAD @@ -5678,28 +5703,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_LDM" +Ne 119 "/FPGA_Sp92" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_WE#" +Ne 99 "/FPGA_Sp68" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_CAS#" +Ne 103 "/FPGA_Sp71" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_RAS#" +Ne 102 "/FPGA_Sp70" Po 1535 2176 $EndPAD $PAD @@ -5720,49 +5745,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_BA0" +Ne 106 "/FPGA_Sp75" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_BA1" +Ne 115 "/FPGA_Sp85" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_A10" +Ne 93 "/FPGA_Sp60" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M1_A0" +Ne 90 "/FPGA_Sp55" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A1" +Ne 91 "/FPGA_Sp56" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A2" +Ne 86 "/FPGA_Sp51" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_A3" +Ne 94 "/FPGA_Sp61" Po 3838 2176 $EndPAD $PAD @@ -5783,56 +5808,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A4" +Ne 33 "/DDR_Banks/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_A5" +Ne 117 "/FPGA_Sp87" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A6" +Ne 116 "/FPGA_Sp86" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_A7" +Ne 85 "/FPGA_Sp50" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A8" +Ne 78 "/FPGA_Sp36" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_A9" +Ne 79 "/FPGA_Sp37" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A11" +Ne 89 "/FPGA_Sp54" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A12" +Ne 16 "/DDR_Ban48" Po 2047 -2176 $EndPAD $PAD @@ -5846,28 +5871,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_CLK#" +Ne 22 "/DDR_Ban76" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_CKE" +Ne 83 "/FPGA_Sp47" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_CLK" +Ne 100 "/FPGA_Sp69" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_UDM" +Ne 29 "/DDR_Ban97" Po 767 -2176 $EndPAD $PAD @@ -5895,7 +5920,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_UDQS" +Ne 10 "/DDR_Ban115" Po -255 -2176 $EndPAD $PAD @@ -5916,7 +5941,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ8" +Ne 57 "/FPGA_Sp108" Po -1023 -2176 $EndPAD $PAD @@ -5930,14 +5955,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_DQ9" +Ne 8 "/DDR_Ban109" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ10" +Ne 9 "/DDR_Ban112" Po -1791 -2176 $EndPAD $PAD @@ -5951,14 +5976,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ11" +Ne 60 "/FPGA_Sp113" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_DQ12" +Ne 64 "/FPGA_Sp118" Po -2558 -2176 $EndPAD $PAD @@ -5972,14 +5997,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ13" +Ne 11 "/DDR_Ban119" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ14" +Ne 66 "/FPGA_Sp122" Po -3326 -2176 $EndPAD $PAD @@ -5993,7 +6018,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ15" +Ne 67 "/FPGA_Sp123" Po -3838 -2176 $EndPAD $PAD @@ -6029,7 +6054,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_DQ0" +Ne 5 "/DDR_Ban101" Po -3838 2176 $EndPAD $PAD @@ -6043,14 +6068,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_DQ1" +Ne 52 "/FPGA_Sp100" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ2" +Ne 122 "/FPGA_Sp95" Po -3070 2176 $EndPAD $PAD @@ -6064,14 +6089,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ3" +Ne 121 "/FPGA_Sp94" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ4" +Ne 104 "/FPGA_Sp73" Po -2303 2176 $EndPAD $PAD @@ -6085,14 +6110,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ5" +Ne 21 "/DDR_Ban72" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ6" +Ne 110 "/FPGA_Sp80" Po -1535 2176 $EndPAD $PAD @@ -6106,7 +6131,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ7" +Ne 108 "/FPGA_Sp79" Po -1023 2176 $EndPAD $PAD @@ -6127,7 +6152,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_LDQS" +Ne 26 "/DDR_Ban90" Po -255 2176 $EndPAD $PAD @@ -6155,28 +6180,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_LDM" +Ne 27 "/DDR_Ban91" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_WE#" +Ne 87 "/FPGA_Sp52" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_CAS#" +Ne 112 "/FPGA_Sp82" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_RAS#" +Ne 113 "/FPGA_Sp83" Po 1535 2176 $EndPAD $PAD @@ -6197,49 +6222,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_BA0" +Ne 92 "/FPGA_Sp58" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_BA1" +Ne 17 "/DDR_Ban57" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A10" +Ne 18 "/DDR_Ban59" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M0_A0" +Ne 96 "/FPGA_Sp63" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A1" +Ne 95 "/FPGA_Sp62" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A2" +Ne 97 "/FPGA_Sp66" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A3" +Ne 114 "/FPGA_Sp84" Po 3838 2176 $EndPAD $PAD @@ -6260,56 +6285,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A4" +Ne 88 "/FPGA_Sp53" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A5" +Ne 111 "/FPGA_Sp81" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A6" +Ne 105 "/FPGA_Sp74" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A7" +Ne 98 "/FPGA_Sp67" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A8" +Ne 32 "/DDR_Banks/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A9" +Ne 84 "/FPGA_Sp49" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_A11" +Ne 13 "/DDR_Ban27" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A12" +Ne 14 "/DDR_Ban38" Po 2047 -2176 $EndPAD $PAD @@ -6323,28 +6348,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_CLK#" +Ne 19 "/DDR_Ban64" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_CKE" +Ne 15 "/DDR_Ban39" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_CLK" +Ne 20 "/DDR_Ban65" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_UDM" +Ne 28 "/DDR_Ban96" Po 767 -2176 $EndPAD $PAD @@ -6372,7 +6397,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_UDQS" +Ne 61 "/FPGA_Sp114" Po -255 -2176 $EndPAD $PAD @@ -6393,7 +6418,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ8" +Ne 7 "/DDR_Ban105" Po -1023 -2176 $EndPAD $PAD @@ -6407,14 +6432,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ9" +Ne 54 "/FPGA_Sp104" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ10" +Ne 59 "/FPGA_Sp111" Po -1791 -2176 $EndPAD $PAD @@ -6428,14 +6453,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ11" +Ne 58 "/FPGA_Sp110" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ12" +Ne 63 "/FPGA_Sp117" Po -2558 -2176 $EndPAD $PAD @@ -6449,14 +6474,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ13" +Ne 62 "/FPGA_Sp116" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ14" +Ne 12 "/DDR_Ban121" Po -3326 -2176 $EndPAD $PAD @@ -6470,7 +6495,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ15" +Ne 65 "/FPGA_Sp120" Po -3838 -2176 $EndPAD $PAD @@ -6498,7 +6523,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 155 "N-000354" +Ne 156 "N-000362" Po -176 0 $EndPAD $PAD @@ -6561,7 +6586,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/Ethernet_Phy/ETH_LED1" +Ne 37 "/Etherne13" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6589,7 +6614,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_LED0" +Ne 36 "/Etherne12" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6750,7 +6775,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_MDIO" +Ne 35 "/Etherne11" Po -176 0 $EndPAD $PAD @@ -6778,7 +6803,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 155 "N-000354" +Ne 156 "N-000362" Po -176 0 $EndPAD $PAD @@ -6890,7 +6915,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 49 "/Etherne4" Po -176 0 $EndPAD $PAD @@ -6918,7 +6943,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/Ethernet_Phy/ETH_A3.3V" +Ne 45 "/Etherne3" Po -176 0 $EndPAD $PAD @@ -6946,7 +6971,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_A1.8V" +Ne 41 "/Etherne2" Po -176 0 $EndPAD $PAD @@ -7058,7 +7083,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_1.8V" +Ne 34 "/Etherne1" Po -176 0 $EndPAD $PAD @@ -7086,7 +7111,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000349" +Ne 159 "N-000365" Po -294 0 $EndPAD $PAD @@ -7114,7 +7139,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 154 "N-000353" +Ne 162 "N-000368" Po -294 0 $EndPAD $PAD @@ -7142,14 +7167,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_A1.8V" +Ne 41 "/Etherne2" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 49 "/Etherne4" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7177,7 +7202,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_A3.3V" +Ne 45 "/Etherne3" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7205,7 +7230,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_A1.8V" +Ne 41 "/Etherne2" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7226,7 +7251,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 157 "N-000356" +Ne 157 "N-000363" Po -294 0 $EndPAD $PAD @@ -7254,7 +7279,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 157 "N-000356" +Ne 157 "N-000363" Po -294 0 $EndPAD $PAD @@ -7282,7 +7307,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 157 "N-000356" +Ne 157 "N-000363" Po -294 0 $EndPAD $PAD @@ -7310,7 +7335,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_A3.3V" +Ne 45 "/Etherne3" Po -294 0 $EndPAD $PAD @@ -7366,7 +7391,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 152 "N-000350" +Ne 161 "N-000367" Po -570 0 $EndPAD $PAD @@ -7399,56 +7424,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 156 "N-000355" +Ne 160 "N-000366" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 151 "N-000349" +Ne 159 "N-000365" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 154 "N-000353" +Ne 162 "N-000368" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 154 "N-000353" +Ne 162 "N-000368" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 155 "N-000354" +Ne 156 "N-000362" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 155 "N-000354" +Ne 156 "N-000362" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 155 "N-000354" +Ne 156 "N-000362" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 155 "N-000354" +Ne 156 "N-000362" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -8085,7 +8110,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 153 "N-000351" +Ne 158 "N-000364" Po -294 0 $EndPAD $PAD @@ -8113,17 +8138,417 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 152 "N-000350" +Ne 161 "N-000367" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "N-000355" +Ne 160 "N-000366" Po 294 0 $EndPAD $EndMODULE 0603 +$MODULE 0603 +Po 0 0 0 15 4C5FF890 4C65540A ~~ +Li 0603 +Sc 4C65540A +AR /4C5F1EDC/4C6552B0 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L6" +T1 0 150 200 200 0 40 N I 25 N"FB" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 155 "N-000359" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 0 0 0 15 4C5FF890 4C65540C ~~ +Li 0603 +Sc 4C65540C +AR /4C5F1EDC/4C6552B1 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L7" +T1 0 150 200 200 0 40 N I 25 N"FB" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C6554EB ~~ +Li 0402 +Sc 4C6554EB +AR /4C5F1EDC/4C6552B6 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R15" +T1 0 150 200 200 0 40 N I 25 N"1M" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 153 "N-000356" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C6554ED ~~ +Li 0402 +Sc 4C6554ED +AR /4C5F1EDC/4C6552B7 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C38" +T1 0 150 200 200 0 40 N I 25 N"4.7nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 153 "N-000356" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C6554EF ~~ +Li 0402 +Sc 4C6554EF +AR /4C5F1EDC/4C6552BC +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C37" +T1 0 150 200 200 0 40 N I 25 N"470nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 151 "N-000349" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 0 0 0 15 4C5FF890 4C6554F0 ~~ +Li 0603 +Sc 4C6554F0 +AR /4C5F1EDC/4C6552B9 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"V4" +T1 0 150 200 200 0 40 N I 25 N"V0402MHS03" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 154 "N-000358" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 0 0 0 15 4C5FF890 4C6554F2 ~~ +Li 0603 +Sc 4C6554F2 +AR /4C5F1EDC/4C6552B8 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"V3" +T1 0 150 200 200 0 40 N I 25 N"V0402MHS03" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 152 "N-000353" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0805 +Po 0 0 0 15 4C5FF890 4C6554F3 ~~ +Li 0805 +Sc 4C6554F3 +AR /4C5F1EDC/4C6552BD +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C36" +T1 0 150 200 200 0 40 N I 25 N"1uF" +DS -561 305 -561 -305 50 21 +DS -561 -305 561 -305 50 21 +DS 561 -305 561 305 50 21 +DS 561 305 -561 305 50 21 +$PAD +Sh "1" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 151 "N-000349" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0805 +Po 0 0 0 15 4C5FF890 4C6554F5 ~~ +Li 0805 +Sc 4C6554F5 +AR /4C5F1EDC/4C6552BE +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C35" +T1 0 150 200 200 0 40 N I 25 N"1uF" +DS -561 305 -561 -305 50 21 +DS -561 -305 561 -305 50 21 +DS 561 -305 561 305 50 21 +DS 561 305 -561 305 50 21 +$PAD +Sh "1" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 151 "N-000349" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 1210 +Po 0 0 0 15 4C5FF890 4C6554F6 ~~ +Li 1210 +Sc 4C6554F6 +AR /4C5F1EDC/4C6552BA +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"F2" +T1 0 150 200 200 0 40 N I 25 N"MICROSMD075F" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 155 "N-000359" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+5V" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE TSSOP-14 +Po 0 0 0 15 4C5F22BD 4C6554F7 ~~ +Li TSSOP-14 +Sc 4C6554F7 +AR /4C5F1EDC/4C6552BF +Op 0 0 0 +T0 50 -1822 276 276 0 69 N V 21 N"U7" +T1 70 1848 276 276 0 69 N V 21 N"MIC2550AYTS" +DC -738 409 -666 418 150 21 +DS 987 634 -984 628 150 21 +DS -984 628 -984 187 150 21 +DS -984 187 -726 187 150 21 +DS -726 187 -726 -185 150 21 +DS -726 -185 -987 -188 150 21 +DS -987 -188 -984 -649 150 21 +DS -984 -649 982 -650 150 21 +DS 982 -650 986 634 150 21 +DS -984 -787 984 -787 1 21 +DS 984 -787 984 787 1 21 +DS -984 787 984 787 1 21 +DS -984 -787 -984 787 1 21 +$PAD +Sh "1" R 137 570 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 2 "+2.5V" +Po -767 1112 +$EndPAD +$PAD +Sh "2" R 137 570 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -511 1112 +$EndPAD +$PAD +Sh "3" R 137 570 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -255 1112 +$EndPAD +$PAD +Sh "4" R 137 570 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 1112 +$EndPAD +$PAD +Sh "5" R 137 570 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 255 1112 +$EndPAD +$PAD +Sh "6" R 137 570 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 511 1112 +$EndPAD +$PAD +Sh "7" R 137 570 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "GND" +Po 767 1112 +$EndPAD +$PAD +Sh "8" R 137 570 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "GND" +Po 767 -1112 +$EndPAD +$PAD +Sh "9" R 137 570 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 511 -1112 +$EndPAD +$PAD +Sh "10" R 137 570 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 154 "N-000358" +Po 255 -1112 +$EndPAD +$PAD +Sh "11" R 137 570 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 152 "N-000353" +Po 0 -1112 +$EndPAD +$PAD +Sh "12" R 137 570 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 134 "3.3V" +Po -255 -1112 +$EndPAD +$PAD +Sh "13" R 137 570 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -511 -1112 +$EndPAD +$PAD +Sh "14" R 137 570 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 134 "3.3V" +Po -767 -1112 +$EndPAD +$EndMODULE TSSOP-14 $COTATION Ge 0 24 0 Va 21654 diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp index c41bb32..0e2f2c1 100644 --- a/kicad/xue-rnc/xue-rnc.cmp +++ b/kicad/xue-rnc/xue-rnc.cmp @@ -1,4 +1,4 @@ -Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Mon 09 Aug 2010 09:53:42 PM COT +Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Fri 13 Aug 2010 09:21:17 AM COT BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; @@ -112,6 +112,160 @@ ValeurCmp = 4.7nF; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C421DD3/4C61CC73; +Reference = C17; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CC96; +Reference = C18; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CCE3; +Reference = C19; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CCE2; +Reference = C20; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CF2F; +Reference = C21; +ValeurCmp = 1uF; +IdModule = 0603; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CEB9; +Reference = C22; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CEF7; +Reference = C23; +ValeurCmp = 10nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CF17; +Reference = C24; +ValeurCmp = 10nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CF16; +Reference = C25; +ValeurCmp = 10nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CF27; +Reference = C26; +ValeurCmp = 10nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CFA0; +Reference = C27; +ValeurCmp = 1uF; +IdModule = 0603; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CFA5; +Reference = C28; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CFA4; +Reference = C29; +ValeurCmp = 10nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CFA2; +Reference = C30; +ValeurCmp = 10nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CFA3; +Reference = C31; +ValeurCmp = 10nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CFA1; +Reference = C32; +ValeurCmp = 10nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61D151; +Reference = C33; +ValeurCmp = 1uF; +IdModule = 0805; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61D1D4; +Reference = C34; +ValeurCmp = 1uF; +IdModule = 0805; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C6552BE; +Reference = C35; +ValeurCmp = 1uF; +IdModule = 0805; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C6552BD; +Reference = C36; +ValeurCmp = 1uF; +IdModule = 0805; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C6552BC; +Reference = C37; +ValeurCmp = 470nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C6552B7; +Reference = C38; +ValeurCmp = 4.7nF; +IdModule = 0402; +EndCmp + BeginCmp TimeStamp = /4C5F1EDC/4C5F2B55; Reference = F1; @@ -119,6 +273,13 @@ ValeurCmp = MICROSMD075F; IdModule = 1210; EndCmp +BeginCmp +TimeStamp = /4C5F1EDC/4C6552BA; +Reference = F2; +ValeurCmp = MICROSMD075F; +IdModule = 1210; +EndCmp + BeginCmp TimeStamp = /4C4227FE/4B76F5E2; Reference = J1; @@ -161,6 +322,34 @@ ValeurCmp = INDUCTOR; IdModule = 0603; EndCmp +BeginCmp +TimeStamp = /4C5F1EDC/4C63F252; +Reference = L4; +ValeurCmp = FB; +IdModule = 0603; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C63F248; +Reference = L5; +ValeurCmp = FB; +IdModule = 0603; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C6552B0; +Reference = L6; +ValeurCmp = FB; +IdModule = 0603; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C6552B1; +Reference = L7; +ValeurCmp = FB; +IdModule = 0603; +EndCmp + BeginCmp TimeStamp = /4C4320F3/4C5D7F39; Reference = R1; @@ -231,6 +420,41 @@ ValeurCmp = 1M; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C421DD3/4C61CD4A; +Reference = R11; +ValeurCmp = 1K_1%; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CDB5; +Reference = R12; +ValeurCmp = 1K_1%; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CE31; +Reference = R13; +ValeurCmp = 1K_1%; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C61CE30; +Reference = R14; +ValeurCmp = 1K_1%; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C6552B6; +Reference = R15; +ValeurCmp = 1M; +IdModule = 0402; +EndCmp + BeginCmp TimeStamp = /4C431A63/4C431E53; Reference = U1; @@ -273,6 +497,13 @@ ValeurCmp = MIC2550AYTS; IdModule = TSSOP-14; EndCmp +BeginCmp +TimeStamp = /4C5F1EDC/4C6552BF; +Reference = U7; +ValeurCmp = MIC2550AYTS; +IdModule = TSSOP-14; +EndCmp + BeginCmp TimeStamp = /4C5F1EDC/4C5F2CA7; Reference = V1; @@ -287,4 +518,18 @@ ValeurCmp = V0402MHS03; IdModule = 0603; EndCmp +BeginCmp +TimeStamp = /4C5F1EDC/4C6552B8; +Reference = V3; +ValeurCmp = V0402MHS03; +IdModule = 0603; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C6552B9; +Reference = V4; +ValeurCmp = V0402MHS03; +IdModule = 0603; +EndCmp + EndListe diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index fb7936d..aed1123 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,1039 +1,1057 @@ -# EESchema Netlist Version 1.1 created Thu 12 Aug 2010 09:08:23 PM COT +# EESchema Netlist Version 1.1 created Fri 13 Aug 2010 09:21:17 AM COT ( - ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000350 ) - ( 2 N-000355 ) + ( /4C4320F3/4C5D7F9F 0603 C1 1uF + ( 1 3.3V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000351 ) - ( 2 GND ) + ( /4C4320F3/4C5D80ED 0402 C2 C + ( 1 /Etherne1 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000354 ) - ( 2 GND ) + ( /4C4320F3/4C5D7FA1 0402 C3 100nF + ( 1 3.3V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000354 ) - ( 2 GND ) + ( /4C4320F3/4C5D80F0 0402 C4 C + ( 1 N-000331 ) + ( 2 N-000340 ) ) - ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000353 ) - ( 2 GND ) + ( /4C4320F3/4C5D7FA3 0402 C5 100nF + ( 1 3.3V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000349 ) - ( 2 GND ) + ( /4C4320F3/4C5D8104 0402 C6 C + ( 1 /Etherne2 ) + ( 2 N-000340 ) ) - ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000350 ) - ( 2 +5V ) + ( /4C4320F3/4C5D7FA5 0603 C7 1uF + ( 1 /Etherne3 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000354 ) - ( S2 N-000354 ) - ( S3 N-000354 ) - ( S4 N-000354 ) - ( 1 N-000355 ) - ( 2 N-000349 ) - ( 3 N-000353 ) - ( 4 N-000351 ) + ( /4C4320F3/4C5D7FA7 0402 C8 100nF + ( 1 /Etherne3 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} - ( 1 N-000356 ) - ( 2 GND ) + ( /4C4320F3/4C5D8114 0402 C9 C + ( 1 /Etherne4 ) + ( 2 N-000340 ) ) - ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} - ( 1 N-000356 ) - ( 2 GND ) + ( /4C4320F3/4C5D7E41 0402 C10 100nF + ( 1 3.3V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} - ( 1 N-000356 ) - ( 2 GND ) + ( /4C4320F3/4C5D7E43 0402 C11 100nF + ( 1 3.3V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} - ( 1 +2.5V ) - ( 2 /USB/USBA_SPD ) - ( 3 /FPGA_Spartan6/USBA_RCV ) - ( 4 /FPGA_Spartan6/USBA_VP ) - ( 5 /USB/USBA_VM ) - ( 7 GND ) - ( 8 GND ) - ( 9 /USB/USBA_OE_N ) - ( 10 N-000349 ) - ( 11 N-000353 ) - ( 12 3.3V ) - ( 14 3.3V ) + ( /4C4320F3/4C5D7DCB 0402 C12 47nF + ( 1 N-000329 ) + ( 2 GND ) ) - ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} - ( P7 ? ) - ( N7 ? ) - ( M7 ? ) - ( L7 +2.5V ) - ( K7 ? ) - ( J7 ? ) - ( G7 ? ) - ( F7 ? ) - ( P6 ? ) - ( N6 ? ) - ( M6 ? ) - ( L6 ? ) - ( K6 /DDR_Banks/M0_A3 ) - ( J6 ? ) - ( H6 /DDR_Banks/M0_A7 ) - ( G6 ? ) - ( F6 +2.5V ) - ( E6 ? ) - ( U5 +2.5V ) - ( P5 ? ) - ( N5 +2.5V ) - ( M5 ? ) - ( K5 /DDR_Banks/M0_RAS# ) - ( J5 +2.5V ) - ( H5 /FPGA_Spartan6/M0_A2 ) - ( F5 ? ) - ( E5 ? ) - ( D5 ? ) - ( U4 ? ) - ( H21 /DDR_Banks/M1_RAS# ) - ( G21 +2.5V ) - ( F21 /FPGA_Spartan6/M1_A0 ) - ( D21 /DDR_Banks/M1_CKE ) - ( C21 +2.5V ) - ( B21 ? ) - ( A21 ? ) - ( W20 ? ) - ( V20 ? ) - ( U20 /DDR_Banks/M1_DQ12 ) - ( T20 ? ) - ( R20 /FPGA_Spartan6/M1_DQ10 ) - ( P20 ? ) - ( N20 /FPGA_Spartan6/M1_DQ0 ) - ( M20 /DDR_Banks/M1_UDM ) - ( L20 /DDR_Banks/M1_LDQS ) - ( K20 /DDR_Banks/M1_A5 ) - ( J20 /DDR_Banks/M1_DQ4 ) - ( H20 /DDR_Banks/M1_CLK ) - ( G20 /FPGA_Spartan6/M1_A3 ) - ( F20 /FPGA_Spartan6/M1_A4 ) - ( E20 /FPGA_Spartan6/M1_A7 ) - ( D20 ? ) - ( C20 /DDR_Banks/M1_A8 ) - ( B20 ? ) - ( A20 ? ) - ( P8 ? ) - ( M8 ? ) - ( K8 ? ) - ( H8 ? ) - ( B3 ? ) - ( W2 +2.5V ) - ( V2 /DDR_Banks/M0_DQ14 ) - ( T2 /FPGA_Spartan6/M0_UDQS ) - ( R2 +2.5V ) - ( P2 /FPGA_Spartan6/M0_DQ8 ) - ( M2 /DDR_Banks/M0_DQ2 ) - ( L2 +2.5V ) - ( K2 /FPGA_Spartan6/M0_DQ6 ) - ( H2 /FPGA_Spartan6/M0_A0 ) - ( G2 +2.5V ) - ( F2 /DDR_Banks/M0_WE# ) - ( D2 /DDR_Banks/M0_CKE ) - ( C2 +2.5V ) - ( B2 ? ) - ( A2 ? ) - ( Y1 ? ) - ( W1 ? ) - ( V1 /FPGA_Spartan6/M0_DQ15 ) - ( U1 /FPGA_Spartan6/M0_DQ13 ) - ( T1 ? ) - ( R1 /FPGA_Spartan6/M0_DQ11 ) - ( P1 /FPGA_Spartan6/M0_DQ9 ) - ( N1 /FPGA_Spartan6/M0_DQ1 ) - ( M1 /DDR_Banks/M0_DQ3 ) - ( L1 ? ) - ( K1 /FPGA_Spartan6/M0_DQ7 ) - ( J1 /FPGA_Spartan6/M0_DQ5 ) - ( H1 /FPGA_Spartan6/M0_A1 ) - ( G1 /FPGA_Spartan6/M0_BA1 ) - ( T4 ? ) - ( R4 ? ) - ( P4 ? ) - ( N4 ? ) - ( M4 ? ) - ( L4 /DDR_Banks/M0_LDM ) - ( K4 /DDR_Banks/M0_CAS# ) - ( J4 /FPGA_Spartan6/M0_A6 ) - ( H4 /DDR_Banks/M0_CLK ) - ( G4 /FPGA_Spartan6/M0_A10 ) - ( F4 +2.5V ) - ( E4 ? ) - ( C4 ? ) - ( W3 ? ) - ( V3 ? ) - ( U3 /FPGA_Spartan6/M0_DQ12 ) - ( T3 ? ) - ( R3 /DDR_Banks/M0_DQ10 ) - ( P3 ? ) - ( N3 /FPGA_Spartan6/M0_DQ0 ) - ( M3 /FPGA_Spartan6/M0_UDM ) - ( L3 /FPGA_Spartan6/M0_LDQS ) - ( K3 /FPGA_Spartan6/M0_A5 ) - ( J3 /DDR_Banks/M0_DQ4 ) - ( H3 /DDR_Banks/M0_CLK# ) - ( G3 /FPGA_Spartan6/M0_BA0 ) - ( F3 /FPGA_Spartan6/M0_A4 ) - ( E3 /DDR_Banks/M0_A8 ) - ( D3 ? ) - ( C3 ? ) - ( G10 +3.3V ) - ( D10 /FPGA_Spartan6/ETH_RXC ) - ( C10 /FPGA_Spartan6/ETH_CLK ) - ( B10 /FPGA_Spartan6/ETH_CRS ) - ( A10 /Ethernet_Phy/ETH_COL ) - ( E9 +3.3V ) - ( D9 /Ethernet_Phy/ETH_TXEN ) - ( C9 /Ethernet_Phy/ETH_TXD1 ) - ( A9 /Ethernet_Phy/ETH_TXD2 ) - ( D8 /FPGA_Spartan6/ETH_TXC ) - ( C8 /FPGA_Spartan6/ETH_TXD0 ) - ( B8 /FPGA_Spartan6/ETH_RXER ) - ( A8 /FPGA_Spartan6/ETH_TXER ) - ( D7 /FPGA_Spartan6/ETH_TXD3 ) - ( C7 /Ethernet_Phy/ETH_RXD0 ) - ( B7 +3.3V ) - ( A7 /FPGA_Spartan6/ETH_RXDV ) - ( D6 /FPGA_Spartan6/ETH_RESET_N ) - ( C6 /FPGA_Spartan6/ETH_RXD3 ) - ( B6 /FPGA_Spartan6/ETH_RXD2 ) - ( A6 /Ethernet_Phy/ETH_RXD1 ) - ( C5 /Ethernet_Phy/ETH_MDC ) - ( A5 /Ethernet_Phy/ETH_MDIO ) - ( B4 +3.3V ) - ( A4 /Ethernet_Phy/ETH_INT ) - ( U19 ? ) - ( T19 ? ) - ( R19 /USB/USBA_SPD ) - ( P19 ? ) - ( N19 ? ) - ( B19 +3.3V ) - ( B18 /FPGA_Spartan6/SD_DAT1 ) - ( A18 /Non_volatile_memories/SD_DAT0 ) - ( E17 +3.3V ) - ( D17 /Non_volatile_memories/SD_CMD ) - ( C17 /Non_volatile_memories/SD_DAT3 ) - ( A17 /Non_volatile_memories/SD_DAT2 ) - ( E16 /FPGA_Spartan6/SD_CLK ) - ( C16 ? ) - ( B16 ? ) - ( A16 ? ) - ( D15 ? ) - ( C15 ? ) - ( B15 +3.3V ) - ( A15 ? ) - ( G14 +3.3V ) - ( D14 /Non_volatile_memories/NF_D0 ) - ( C14 ? ) - ( B14 ? ) - ( A14 ? ) - ( E13 +3.3V ) - ( C13 /FPGA_Spartan6/NF_D2 ) - ( A13 /FPGA_Spartan6/NF_D1 ) - ( C12 /Non_volatile_memories/NF_D5 ) - ( B12 /FPGA_Spartan6/NF_D4 ) - ( A12 /FPGA_Spartan6/NF_D3 ) - ( D11 /FPGA_Spartan6/NF_D6 ) - ( C11 ? ) - ( B11 +3.3V ) - ( A11 /Non_volatile_memories/NF_D7 ) - ( H16 ? ) - ( G16 ? ) - ( F16 ? ) - ( L15 ? ) - ( W22 ? ) - ( V22 /FPGA_Spartan6/M1_DQ15 ) - ( U22 /FPGA_Spartan6/M1_DQ13 ) - ( T22 ? ) - ( R22 /FPGA_Spartan6/M1_DQ11 ) - ( P22 /FPGA_Spartan6/M1_DQ9 ) - ( N22 /FPGA_Spartan6/M1_DQ1 ) - ( M22 /DDR_Banks/M1_DQ3 ) - ( L22 ? ) - ( K22 /DDR_Banks/M1_DQ7 ) - ( J22 /FPGA_Spartan6/M1_DQ5 ) - ( H22 /FPGA_Spartan6/M1_CAS# ) - ( G22 ? ) - ( F22 /FPGA_Spartan6/M1_A1 ) - ( E22 /FPGA_Spartan6/M1_A2 ) - ( D22 /FPGA_Spartan6/M1_A12 ) - ( C22 /FPGA_Spartan6/M1_A9 ) - ( B22 ? ) - ( W21 +2.5V ) - ( V21 /FPGA_Spartan6/M1_DQ14 ) - ( T21 /FPGA_Spartan6/M1_UDQS ) - ( R21 +2.5V ) - ( P21 /FPGA_Spartan6/M1_DQ8 ) - ( M21 /FPGA_Spartan6/M1_DQ2 ) - ( L21 +2.5V ) - ( K21 /DDR_Banks/M1_DQ6 ) - ( M19 ? ) - ( L19 /FPGA_Spartan6/M1_LDM ) - ( K19 /FPGA_Spartan6/M1_A6 ) - ( J19 /FPGA_Spartan6/M1_CLK# ) - ( H19 /DDR_Banks/M1_WE# ) - ( G19 /DDR_Banks/M1_A10 ) - ( F19 /FPGA_Spartan6/M1_A11 ) - ( E19 +2.5V ) - ( D19 ? ) - ( U18 +2.5V ) - ( P18 /USB/USBA_OE_N ) - ( N18 +2.5V ) - ( M18 /USB/USBA_VM ) - ( K18 ? ) - ( J18 +2.5V ) - ( H18 ? ) - ( F18 ? ) - ( P17 /FPGA_Spartan6/USBA_VP ) - ( M17 ? ) - ( L17 ? ) - ( K17 /DDR_Banks/M1_BA1 ) - ( J17 /FPGA_Spartan6/M1_BA0 ) - ( H17 ? ) - ( G17 ? ) - ( F17 ? ) - ( N16 /FPGA_Spartan6/USBA_RCV ) - ( M16 ? ) - ( L16 +2.5V ) - ( K16 ? ) - ( J16 ? ) - ( J14 +1.2V ) - ( H14 ? ) - ( F14 ? ) - ( E14 ? ) - ( P13 +1.2V ) - ( N13 GND ) - ( M13 +1.2V ) - ( L13 GND ) - ( K13 +1.2V ) - ( J13 GND ) - ( H13 ? ) - ( G13 ? ) - ( F13 ? ) - ( D13 ? ) - ( B13 GND ) - ( Y22 ? ) - ( A22 GND ) - ( R12 +2.5V ) - ( P12 GND ) - ( N12 +1.2V ) - ( M12 GND ) - ( L12 +1.2V ) - ( K12 ? ) - ( J12 +1.2V ) - ( H12 ? ) - ( G12 +2.5V ) - ( F12 ? ) - ( E12 ? ) - ( D12 ? ) - ( AB1 GND ) - ( A19 ? ) - ( R18 GND ) - ( L18 GND ) - ( G18 GND ) - ( E18 ? ) - ( D18 GND ) - ( C18 ? ) - ( R17 ? ) - ( N17 GND ) - ( B17 GND ) - ( W16 GND ) - ( P16 ? ) - ( D16 +2.5V ) - ( AA5 GND ) - ( P15 ? ) - ( N15 ? ) - ( M15 +2.5V ) - ( K15 +2.5V ) - ( J15 GND ) - ( H15 +2.5V ) - ( G15 ? ) - ( F15 ? ) - ( E15 GND ) - ( V14 GND ) - ( R14 +1.2V ) - ( P14 GND ) - ( N14 +1.2V ) - ( M14 GND ) - ( L14 +1.2V ) - ( K14 GND ) - ( L9 GND ) - ( K9 +1.2V ) - ( J9 GND ) - ( H9 +2.5V ) - ( G9 ? ) - ( F9 ? ) - ( B9 GND ) - ( N8 +2.5V ) - ( L8 +2.5V ) - ( J8 +1.2V ) - ( G8 ? ) - ( F8 ? ) - ( E8 ? ) - ( W7 GND ) - ( U7 GND ) - ( H7 GND ) - ( E7 GND ) - ( V6 +2.5V ) - ( R6 +2.5V ) - ( R5 GND ) - ( L5 GND ) - ( G5 GND ) - ( B5 GND ) - ( V4 GND ) - ( D4 GND ) - ( U2 GND ) - ( N2 GND ) - ( J2 GND ) - ( E2 GND ) - ( A1 GND ) - ( AA1 ? ) - ( U21 GND ) - ( N21 GND ) - ( J21 GND ) - ( E21 GND ) - ( U11 +2.5V ) - ( P11 +1.2V ) - ( N11 GND ) - ( M11 +1.2V ) - ( L11 GND ) - ( K11 +1.2V ) - ( J11 GND ) - ( H11 ? ) - ( G11 ? ) - ( F11 +2.5V ) - ( E11 ? ) - ( V10 GND ) - ( R10 +2.5V ) - ( P10 GND ) - ( N10 +1.2V ) - ( M10 GND ) - ( L10 +1.2V ) - ( K10 GND ) - ( J10 +1.2V ) - ( H10 ? ) - ( F10 ? ) - ( E10 ? ) - ( P9 +1.2V ) - ( N9 GND ) - ( M9 +1.2V ) - ( V19 ? ) - ( AB8 ? ) - ( AA8 ? ) - ( Y18 ? ) - ( W18 ? ) - ( V18 ? ) - ( T18 ? ) - ( AB7 ? ) - ( AA7 N-000110 ) - ( Y17 ? ) - ( W17 ? ) - ( V17 ? ) - ( U17 ? ) - ( T17 ? ) - ( AB6 ? ) - ( AA6 ? ) - ( Y16 ? ) - ( V16 N-000110 ) - ( U16 ? ) - ( T16 ? ) - ( R16 ? ) - ( AB5 ? ) - ( Y15 ? ) - ( W15 ? ) - ( V15 ? ) - ( U15 ? ) - ( T15 ? ) - ( R15 ? ) - ( AB4 ? ) - ( AA4 ? ) - ( F1 ? ) - ( E1 /FPGA_Spartan6/M0_A9 ) - ( D1 /FPGA_Spartan6/M0_A12 ) - ( C1 /DDR_Banks/M0_A11 ) - ( B1 ? ) - ( AB19 ? ) - ( AA19 N-000110 ) - ( AB18 ? ) - ( AA18 ? ) - ( AB17 ? ) - ( AB16 ? ) - ( AA16 ? ) - ( AB15 ? ) - ( AA15 N-000110 ) - ( AB14 ? ) - ( AA14 ? ) - ( AB13 ? ) - ( AA22 ? ) - ( AB12 ? ) - ( AA12 ? ) - ( AB21 ? ) - ( AA21 ? ) - ( AB11 ? ) - ( AA11 N-000110 ) - ( AB20 ? ) - ( AA20 ? ) - ( AB10 ? ) - ( AA10 ? ) - ( AB9 ? ) - ( Y19 ? ) - ( V9 ? ) - ( U9 ? ) - ( T9 N-000110 ) - ( R9 ? ) - ( Y8 ? ) - ( W8 ? ) - ( V8 N-000110 ) - ( U8 ? ) - ( T8 ? ) - ( R8 ? ) - ( Y7 ? ) - ( V7 ? ) - ( T7 ? ) - ( R7 ? ) - ( Y6 ? ) - ( W6 ? ) - ( U6 ? ) - ( T6 ? ) - ( Y5 ? ) - ( W5 N-000110 ) - ( V5 ? ) - ( T5 ? ) - ( Y4 ? ) - ( W4 ? ) - ( Y3 ? ) - ( AA17 GND ) - ( AA13 GND ) - ( AB22 GND ) - ( AA9 GND ) - ( W19 GND ) - ( Y14 ? ) - ( W14 ? ) - ( U14 ? ) - ( T14 ? ) - ( AB3 ? ) - ( AA3 N-000110 ) - ( Y13 ? ) - ( W13 ? ) - ( V13 ? ) - ( U13 ? ) - ( T13 N-000110 ) - ( R13 ? ) - ( AB2 ? ) - ( AA2 ? ) - ( Y12 ? ) - ( W12 ? ) - ( V12 N-000110 ) - ( U12 ? ) - ( T12 ? ) - ( Y11 ? ) - ( W11 ? ) - ( V11 ? ) - ( T11 ? ) - ( R11 ? ) - ( Y10 ? ) - ( W10 ? ) - ( U10 ? ) - ( T10 ? ) - ( Y9 ? ) - ( W9 ? ) + ( /4C5F1EDC/4C5F2033 0603 C13 1uF + ( 1 N-000363 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} - ( 1 /Ethernet_Phy/ETH_PLL1.8V ) - ( 2 N-000340 ) + ( /4C5F1EDC/4C5F2037 0603 C14 1uF + ( 1 N-000363 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D810A $noname L3 INDUCTOR {Lib=INDUCTOR} - ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 /Ethernet_Phy/ETH_PLL1.8V ) + ( /4C5F1EDC/4C5F2039 0603 C15 470nF + ( 1 N-000363 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D8104 $noname C6 C {Lib=C} - ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 N-000340 ) + ( /4C5F1EDC/4C5F2D1E 0402 C16 4.7nF + ( 1 N-000362 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR} - ( 1 N-000331 ) - ( 2 /Ethernet_Phy/ETH_A1.8V ) + ( /4C421DD3/4C61CC73 0402 C17 100nF + ( 1 +2.5V ) + ( 2 N-000051 ) ) - ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} - ( 1 N-000331 ) - ( 2 N-000340 ) + ( /4C421DD3/4C61CC96 0402 C18 100nF + ( 1 N-000051 ) + ( 2 N-000053 ) ) - ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} - ( 1 /Ethernet_Phy/ETH_1.8V ) - ( 2 GND ) + ( /4C421DD3/4C61CCE3 0402 C19 100nF + ( 1 +2.5V ) + ( 2 N-000050 ) ) - ( /4C4320F3/4C5D7FB7 $noname L2 FB {Lib=INDUCTOR} - ( 1 3.3V ) - ( 2 /Ethernet_Phy/ETH_A3.3V ) + ( /4C421DD3/4C61CCE2 0402 C20 100nF + ( 1 N-000050 ) + ( 2 N-000049 ) ) - ( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C} - ( 1 /Ethernet_Phy/ETH_A3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CF2F 0603 C21 1uF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C} - ( 1 /Ethernet_Phy/ETH_A3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CEB9 0402 C22 100nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CEF7 0402 C23 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CF17 0402 C24 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CF16 0402 C25 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} - ( 1 /Ethernet_Phy/ETH_MDIO ) - ( 2 3.3V ) + ( /4C421DD3/4C61CF27 0402 C26 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000337 ) - ( 2 GND ) + ( /4C421DD3/4C61CFA0 0603 C27 1uF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CFA5 0402 C28 100nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) + ( /4C421DD3/4C61CFA4 0402 C29 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000329 ) - ( 2 GND ) + ( /4C421DD3/4C61CFA2 0402 C30 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000329 ) - ( 2 GND ) + ( /4C421DD3/4C61CFA3 0402 C31 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /Ethernet_Phy/ETH_MDIO ) - ( 2 /Ethernet_Phy/ETH_MDC ) - ( 3 /FPGA_Spartan6/ETH_RXD3 ) - ( 4 /FPGA_Spartan6/ETH_RXD2 ) - ( 5 /Ethernet_Phy/ETH_RXD1 ) - ( 6 /Ethernet_Phy/ETH_RXD0 ) - ( 7 3.3V ) - ( 8 GND ) - ( 9 /FPGA_Spartan6/ETH_RXDV ) - ( 10 /FPGA_Spartan6/ETH_RXC ) - ( 11 /FPGA_Spartan6/ETH_RXER ) - ( 12 GND ) - ( 13 /Ethernet_Phy/ETH_1.8V ) - ( 14 /FPGA_Spartan6/ETH_TXER ) - ( 15 /FPGA_Spartan6/ETH_TXC ) - ( 16 /Ethernet_Phy/ETH_TXEN ) - ( 17 /FPGA_Spartan6/ETH_TXD0 ) - ( 18 /Ethernet_Phy/ETH_TXD1 ) - ( 19 /Ethernet_Phy/ETH_TXD2 ) - ( 20 /FPGA_Spartan6/ETH_TXD3 ) - ( 21 /Ethernet_Phy/ETH_COL ) - ( 22 /FPGA_Spartan6/ETH_CRS ) - ( 23 GND ) - ( 24 3.3V ) - ( 25 /Ethernet_Phy/ETH_INT ) - ( 26 /Ethernet_Phy/ETH_LED0 ) - ( 27 /Ethernet_Phy/ETH_LED1 ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000338 ) - ( 33 N-000328 ) - ( 34 ? ) - ( 35 GND ) - ( 36 GND ) - ( 37 N-000337 ) - ( 38 /Ethernet_Phy/ETH_A3.3V ) - ( 39 GND ) - ( 40 N-000339 ) - ( 41 N-000327 ) - ( 42 ? ) - ( 43 ? ) - ( 44 GND ) - ( 45 ? ) - ( 46 /FPGA_Spartan6/ETH_CLK ) - ( 47 /Ethernet_Phy/ETH_PLL1.8V ) - ( 48 /FPGA_Spartan6/ETH_RESET_N ) + ( /4C421DD3/4C61CFA1 0402 C32 10nF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000327 ) + ( /4C421DD3/4C61D151 0805 C33 1uF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000339 ) + ( /4C421DD3/4C61D1D4 0805 C34 1uF + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000338 ) + ( /4C5F1EDC/4C6552BE 0805 C35 1uF + ( 1 N-000349 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000328 ) + ( /4C5F1EDC/4C6552BD 0805 C36 1uF + ( 1 N-000349 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000343 ) - ( 2 /Ethernet_Phy/ETH_LED1 ) + ( /4C5F1EDC/4C6552BC 0402 C37 470nF + ( 1 N-000349 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000330 ) - ( 2 /Ethernet_Phy/ETH_LED0 ) + ( /4C5F1EDC/4C6552B7 0402 C38 4.7nF + ( 1 N-000356 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000327 ) - ( 2 N-000339 ) - ( 3 3.3V ) - ( 4 GND ) - ( 5 GND ) - ( 6 3.3V ) - ( 7 N-000328 ) - ( 8 N-000338 ) - ( 9 3.3V ) - ( 10 N-000330 ) - ( 11 3.3V ) - ( 12 N-000343 ) - ( 13 N-000329 ) - ( 14 N-000329 ) + ( /4C5F1EDC/4C5F2B55 1210 F1 MICROSMD075F + ( 1 N-000367 ) + ( 2 +5V ) ) - ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} + ( /4C5F1EDC/4C6552BA 1210 F2 MICROSMD075F + ( 1 N-000359 ) + ( 2 +5V ) + ) + ( /4C4227FE/4B76F5E2 MICROSD-500901 J1 MICROSD + ( 1 /Non_vol5 ) + ( 2 /Non_vol6 ) + ( 3 /FPGA_Sp7 ) + ( 4 ? ) + ( 5 /FPGA_Sp8 ) + ( 6 GND ) + ( 7 /FPGA_Sp9 ) + ( 8 /Non_vol10 ) ( CASE GND ) - ( COM GND ) - ( CD ? ) - ( 1 /Non_volatile_memories/SD_DAT2 ) - ( 2 /Non_volatile_memories/SD_DAT3 ) - ( 3 /Non_volatile_memories/SD_CMD ) - ( 4 ? ) - ( 5 /FPGA_Spartan6/SD_CLK ) - ( 6 GND ) - ( 7 /Non_volatile_memories/SD_DAT0 ) - ( 8 /FPGA_Spartan6/SD_DAT1 ) + ( CD ? ) + ( COM GND ) ) - ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 /Non_volatile_memories/NF_RNB ) - ( 7 /Non_volatile_memories/NF_RNB ) - ( 8 ? ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 3.3V ) - ( 13 GND ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ( 17 ? ) - ( 18 ? ) - ( 19 3.3V ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 ? ) - ( 24 ? ) - ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 ? ) - ( 29 /Non_volatile_memories/NF_D0 ) - ( 30 /FPGA_Spartan6/NF_D1 ) - ( 31 /FPGA_Spartan6/NF_D2 ) - ( 32 /FPGA_Spartan6/NF_D3 ) - ( 33 ? ) - ( 34 ? ) - ( 35 ? ) - ( 36 GND ) - ( 37 +3.3V ) - ( 38 ? ) - ( 39 ? ) - ( 40 ? ) - ( 41 /FPGA_Spartan6/NF_D4 ) - ( 42 /Non_volatile_memories/NF_D5 ) - ( 43 /FPGA_Spartan6/NF_D6 ) - ( 44 /Non_volatile_memories/NF_D7 ) - ( 45 ? ) - ( 46 ? ) - ( 47 ? ) - ( 48 ? ) + ( /4C4320F3/4C5D6F5A SD-48025 J4 RJ45-48025 + ( 1 N-000327 ) + ( 2 N-000339 ) + ( 3 3.3V ) + ( 4 GND ) + ( 5 GND ) + ( 6 3.3V ) + ( 7 N-000328 ) + ( 8 N-000338 ) + ( 9 3.3V ) + ( 10 N-000330 ) + ( 11 3.3V ) + ( 12 N-000343 ) + ( 13 N-000329 ) + ( 14 N-000329 ) ) - ( /4C421DD3/4C61D1D4 1206 C34 1uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C5F1EDC/4C5F23DD USB-48204 J5 USB-48204-0001 + ( 1 N-000366 ) + ( 2 N-000365 ) + ( 3 N-000368 ) + ( 4 N-000364 ) + ( S1 N-000362 ) + ( S2 N-000362 ) + ( S3 N-000362 ) + ( S4 N-000362 ) ) - ( /4C421DD3/4C61D151 1206 C33 1uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D80F3 0603 L1 INDUCTOR + ( 1 N-000331 ) + ( 2 /Etherne2 ) ) - ( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7FB7 0603 L2 FB + ( 1 3.3V ) + ( 2 /Etherne3 ) ) - ( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D810A 0603 L3 INDUCTOR + ( 1 /Etherne2 ) + ( 2 /Etherne4 ) ) - ( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C5F1EDC/4C63F252 0603 L4 FB + ( 1 N-000367 ) + ( 2 N-000366 ) ) - ( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C5F1EDC/4C63F248 0603 L5 FB + ( 1 N-000364 ) + ( 2 GND ) ) - ( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B0 0603 L6 FB + ( 1 N-000359 ) + ( 2 ? ) ) - ( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B1 0603 L7 FB + ( 1 ? ) + ( 2 GND ) ) - ( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7F39 0402 R1 4.7K + ( 1 /Etherne11 ) + ( 2 3.3V ) ) - ( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7ECF 0402 R2 6.65K + ( 1 N-000337 ) + ( 2 GND ) ) - ( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7AFE 0402 R3 49.9 + ( 1 3.3V ) + ( 2 N-000327 ) ) - ( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7AFC 0402 R4 49.9 + ( 1 3.3V ) + ( 2 N-000339 ) ) - ( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7AF7 0402 R5 49.9 + ( 1 3.3V ) + ( 2 N-000328 ) ) - ( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) + ( /4C4320F3/4C5D7AF9 0402 R6 49.9 + ( 1 3.3V ) + ( 2 N-000338 ) ) - ( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R} - ( 1 +2.5V ) - ( 2 N-000050 ) + ( /4C4320F3/4C5D719D 0402 R7 220 + ( 1 N-000330 ) + ( 2 /Etherne12 ) ) - ( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R} - ( 1 N-000050 ) - ( 2 N-000049 ) + ( /4C4320F3/4C5D71DB 0402 R8 220 + ( 1 N-000343 ) + ( 2 /Etherne13 ) ) - ( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R} - ( 1 N-000051 ) - ( 2 N-000053 ) + ( /4C4320F3/4C5D7DC4 0402 R9 1M + ( 1 N-000329 ) + ( 2 GND ) ) - ( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R} - ( 1 +2.5V ) - ( 2 N-000051 ) + ( /4C5F1EDC/4C5F2D27 0402 R10 1M + ( 1 N-000362 ) + ( 2 GND ) ) - ( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 N-000050 ) + ( /4C421DD3/4C61CD4A 0402 R11 1K_1% + ( 1 +2.5V ) + ( 2 N-000051 ) ) - ( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP} - ( 1 N-000050 ) - ( 2 N-000049 ) + ( /4C421DD3/4C61CDB5 0402 R12 1K_1% + ( 1 N-000051 ) + ( 2 N-000053 ) ) - ( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP} - ( 1 N-000051 ) - ( 2 N-000053 ) + ( /4C421DD3/4C61CE31 0402 R13 1K_1% + ( 1 +2.5V ) + ( 2 N-000050 ) ) - ( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 N-000051 ) + ( /4C421DD3/4C61CE30 0402 R14 1K_1% + ( 1 N-000050 ) + ( 2 N-000049 ) ) - ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} - ( 1 +2.5V ) - ( 2 /FPGA_Spartan6/M1_DQ0 ) - ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M1_DQ1 ) - ( 5 /FPGA_Spartan6/M1_DQ2 ) - ( 6 GND ) - ( 7 /DDR_Banks/M1_DQ3 ) - ( 8 /DDR_Banks/M1_DQ4 ) - ( 9 +2.5V ) - ( 10 /FPGA_Spartan6/M1_DQ5 ) - ( 11 /DDR_Banks/M1_DQ6 ) - ( 12 GND ) - ( 13 /DDR_Banks/M1_DQ7 ) - ( 14 ? ) - ( 15 +2.5V ) - ( 16 /DDR_Banks/M1_LDQS ) - ( 17 ? ) - ( 18 +2.5V ) - ( 19 ? ) - ( 20 /FPGA_Spartan6/M1_LDM ) - ( 21 /DDR_Banks/M1_WE# ) - ( 22 /FPGA_Spartan6/M1_CAS# ) - ( 23 /DDR_Banks/M1_RAS# ) - ( 24 GND ) - ( 25 ? ) - ( 26 /FPGA_Spartan6/M1_BA0 ) - ( 27 /DDR_Banks/M1_BA1 ) - ( 28 /DDR_Banks/M1_A10 ) - ( 29 /FPGA_Spartan6/M1_A0 ) - ( 30 /FPGA_Spartan6/M1_A1 ) - ( 31 /FPGA_Spartan6/M1_A2 ) - ( 32 /FPGA_Spartan6/M1_A3 ) - ( 33 +2.5V ) - ( 34 GND ) - ( 35 /FPGA_Spartan6/M1_A4 ) - ( 36 /DDR_Banks/M1_A5 ) - ( 37 /FPGA_Spartan6/M1_A6 ) - ( 38 /FPGA_Spartan6/M1_A7 ) - ( 39 /DDR_Banks/M1_A8 ) - ( 40 /FPGA_Spartan6/M1_A9 ) - ( 41 /FPGA_Spartan6/M1_A11 ) - ( 42 /FPGA_Spartan6/M1_A12 ) - ( 43 ? ) - ( 44 /FPGA_Spartan6/M1_CLK# ) - ( 45 /DDR_Banks/M1_CKE ) - ( 46 /DDR_Banks/M1_CLK ) - ( 47 /DDR_Banks/M1_UDM ) - ( 48 GND ) - ( 49 N-000050 ) - ( 50 ? ) - ( 51 /FPGA_Spartan6/M1_UDQS ) - ( 52 GND ) - ( 53 ? ) - ( 54 /FPGA_Spartan6/M1_DQ8 ) - ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M1_DQ9 ) - ( 57 /FPGA_Spartan6/M1_DQ10 ) - ( 58 GND ) - ( 59 /FPGA_Spartan6/M1_DQ11 ) - ( 60 /DDR_Banks/M1_DQ12 ) - ( 61 +2.5V ) - ( 62 /FPGA_Spartan6/M1_DQ13 ) - ( 63 /FPGA_Spartan6/M1_DQ14 ) - ( 64 GND ) - ( 65 /FPGA_Spartan6/M1_DQ15 ) - ( 66 GND ) + ( /4C5F1EDC/4C6552B6 0402 R15 1M + ( 1 N-000356 ) + ( 2 GND ) ) - ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} - ( 1 +2.5V ) - ( 2 /FPGA_Spartan6/M0_DQ0 ) - ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M0_DQ1 ) - ( 5 /DDR_Banks/M0_DQ2 ) - ( 6 GND ) - ( 7 /DDR_Banks/M0_DQ3 ) - ( 8 /DDR_Banks/M0_DQ4 ) - ( 9 +2.5V ) - ( 10 /FPGA_Spartan6/M0_DQ5 ) - ( 11 /FPGA_Spartan6/M0_DQ6 ) - ( 12 GND ) - ( 13 /FPGA_Spartan6/M0_DQ7 ) - ( 14 ? ) - ( 15 +2.5V ) - ( 16 /FPGA_Spartan6/M0_LDQS ) - ( 17 ? ) - ( 18 +2.5V ) - ( 19 ? ) - ( 20 /DDR_Banks/M0_LDM ) - ( 21 /DDR_Banks/M0_WE# ) - ( 22 /DDR_Banks/M0_CAS# ) - ( 23 /DDR_Banks/M0_RAS# ) - ( 24 GND ) - ( 25 ? ) - ( 26 /FPGA_Spartan6/M0_BA0 ) - ( 27 /FPGA_Spartan6/M0_BA1 ) - ( 28 /FPGA_Spartan6/M0_A10 ) - ( 29 /FPGA_Spartan6/M0_A0 ) - ( 30 /FPGA_Spartan6/M0_A1 ) - ( 31 /FPGA_Spartan6/M0_A2 ) - ( 32 /DDR_Banks/M0_A3 ) - ( 33 +2.5V ) - ( 34 GND ) - ( 35 /FPGA_Spartan6/M0_A4 ) - ( 36 /FPGA_Spartan6/M0_A5 ) - ( 37 /FPGA_Spartan6/M0_A6 ) - ( 38 /DDR_Banks/M0_A7 ) - ( 39 /DDR_Banks/M0_A8 ) - ( 40 /FPGA_Spartan6/M0_A9 ) - ( 41 /DDR_Banks/M0_A11 ) - ( 42 /FPGA_Spartan6/M0_A12 ) - ( 43 ? ) - ( 44 /DDR_Banks/M0_CLK# ) - ( 45 /DDR_Banks/M0_CKE ) - ( 46 /DDR_Banks/M0_CLK ) - ( 47 /FPGA_Spartan6/M0_UDM ) - ( 48 GND ) - ( 49 N-000051 ) - ( 50 ? ) - ( 51 /FPGA_Spartan6/M0_UDQS ) - ( 52 GND ) - ( 53 ? ) - ( 54 /FPGA_Spartan6/M0_DQ8 ) - ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M0_DQ9 ) - ( 57 /DDR_Banks/M0_DQ10 ) - ( 58 GND ) - ( 59 /FPGA_Spartan6/M0_DQ11 ) - ( 60 /FPGA_Spartan6/M0_DQ12 ) - ( 61 +2.5V ) - ( 62 /FPGA_Spartan6/M0_DQ13 ) - ( 63 /DDR_Banks/M0_DQ14 ) - ( 64 GND ) - ( 65 /FPGA_Spartan6/M0_DQ15 ) - ( 66 GND ) + ( /4C431A63/4C431E53 FGG484bga-p10 U1 XC6SLX45FGG484 + ( A1 GND ) + ( A2 ? ) + ( A4 /Etherne14 ) + ( A5 /Etherne11 ) + ( A6 /Etherne15 ) + ( A7 /FPGA_Sp16 ) + ( A8 /FPGA_Sp17 ) + ( A9 /Etherne18 ) + ( A10 /FPGA_Sp19 ) + ( A11 /FPGA_Sp20 ) + ( A12 /Non_vol21 ) + ( A13 /FPGA_Sp22 ) + ( A14 ? ) + ( A15 ? ) + ( A16 ? ) + ( A17 /Non_vol5 ) + ( A18 /FPGA_Sp9 ) + ( A19 ? ) + ( A20 ? ) + ( A21 ? ) + ( A22 GND ) + ( AA1 ? ) + ( AA2 ? ) + ( AA3 N-000156 ) + ( AA4 ? ) + ( AA5 GND ) + ( AA6 ? ) + ( AA7 N-000156 ) + ( AA8 ? ) + ( AA9 GND ) + ( AA10 ? ) + ( AA11 N-000156 ) + ( AA12 ? ) + ( AA13 GND ) + ( AA14 ? ) + ( AA15 N-000156 ) + ( AA16 ? ) + ( AA17 GND ) + ( AA18 ? ) + ( AA19 N-000156 ) + ( AA20 ? ) + ( AA21 ? ) + ( AA22 ? ) + ( AB1 GND ) + ( AB2 ? ) + ( AB3 ? ) + ( AB4 ? ) + ( AB5 ? ) + ( AB6 ? ) + ( AB7 ? ) + ( AB8 ? ) + ( AB9 ? ) + ( AB10 ? ) + ( AB11 ? ) + ( AB12 ? ) + ( AB13 ? ) + ( AB14 ? ) + ( AB15 ? ) + ( AB16 ? ) + ( AB17 ? ) + ( AB18 ? ) + ( AB19 ? ) + ( AB20 ? ) + ( AB21 ? ) + ( AB22 GND ) + ( B1 ? ) + ( B2 ? ) + ( B3 ? ) + ( B4 +3.3V ) + ( B5 GND ) + ( B6 /Etherne23 ) + ( B7 +3.3V ) + ( B8 /FPGA_Sp24 ) + ( B9 GND ) + ( B10 /Etherne25 ) + ( B11 +3.3V ) + ( B12 /Non_vol26 ) + ( B13 GND ) + ( B14 ? ) + ( B15 +3.3V ) + ( B16 ? ) + ( B17 GND ) + ( B18 /Non_vol10 ) + ( B19 +3.3V ) + ( B20 ? ) + ( B21 ? ) + ( B22 ? ) + ( C1 /DDR_Ban27 ) + ( C2 +2.5V ) + ( C3 ? ) + ( C4 ? ) + ( C5 /Etherne28 ) + ( C6 /FPGA_Sp29 ) + ( C7 /Etherne30 ) + ( C8 /Etherne31 ) + ( C9 /Etherne32 ) + ( C10 /FPGA_Sp33 ) + ( C11 ? ) + ( C12 /FPGA_Sp34 ) + ( C13 /FPGA_Sp35 ) + ( C14 ? ) + ( C15 ? ) + ( C16 ? ) + ( C17 /Non_vol6 ) + ( C18 ? ) + ( C20 /FPGA_Sp36 ) + ( C21 +2.5V ) + ( C22 /FPGA_Sp37 ) + ( D1 /DDR_Ban38 ) + ( D2 /DDR_Ban39 ) + ( D3 ? ) + ( D4 GND ) + ( D5 ? ) + ( D6 /FPGA_Sp40 ) + ( D7 /Etherne41 ) + ( D8 /FPGA_Sp42 ) + ( D9 /Etherne43 ) + ( D10 /FPGA_Sp44 ) + ( D11 /Non_vol45 ) + ( D12 ? ) + ( D13 ? ) + ( D14 /Non_vol46 ) + ( D15 ? ) + ( D16 +2.5V ) + ( D17 /FPGA_Sp7 ) + ( D18 GND ) + ( D19 ? ) + ( D20 ? ) + ( D21 /FPGA_Sp47 ) + ( D22 /DDR_Ban48 ) + ( E1 /FPGA_Sp49 ) + ( E2 GND ) + ( E3 /DDR_Banks/M0_A8 ) + ( E4 ? ) + ( E5 ? ) + ( E6 ? ) + ( E7 GND ) + ( E8 ? ) + ( E9 +3.3V ) + ( E10 ? ) + ( E11 ? ) + ( E12 ? ) + ( E13 +3.3V ) + ( E14 ? ) + ( E15 GND ) + ( E16 /FPGA_Sp8 ) + ( E17 +3.3V ) + ( E18 ? ) + ( E19 +2.5V ) + ( E20 /FPGA_Sp50 ) + ( E21 GND ) + ( E22 /FPGA_Sp51 ) + ( F1 ? ) + ( F2 /FPGA_Sp52 ) + ( F3 /FPGA_Sp53 ) + ( F4 +2.5V ) + ( F5 ? ) + ( F6 +2.5V ) + ( F7 ? ) + ( F8 ? ) + ( F9 ? ) + ( F10 ? ) + ( F11 +2.5V ) + ( F12 ? ) + ( F13 ? ) + ( F14 ? ) + ( F15 ? ) + ( F16 ? ) + ( F17 ? ) + ( F18 ? ) + ( F19 /FPGA_Sp54 ) + ( F20 /DDR_Banks/M1_A4 ) + ( F21 /FPGA_Sp55 ) + ( F22 /FPGA_Sp56 ) + ( G1 /DDR_Ban57 ) + ( G2 +2.5V ) + ( G3 /FPGA_Sp58 ) + ( G4 /DDR_Ban59 ) + ( G5 GND ) + ( G6 ? ) + ( G7 ? ) + ( G8 ? ) + ( G9 ? ) + ( G10 +3.3V ) + ( G11 ? ) + ( G12 +2.5V ) + ( G13 ? ) + ( G14 +3.3V ) + ( G15 ? ) + ( G16 ? ) + ( G17 ? ) + ( G18 GND ) + ( G19 /FPGA_Sp60 ) + ( G20 /FPGA_Sp61 ) + ( G21 +2.5V ) + ( G22 ? ) + ( H1 /FPGA_Sp62 ) + ( H2 /FPGA_Sp63 ) + ( H3 /DDR_Ban64 ) + ( H4 /DDR_Ban65 ) + ( H5 /FPGA_Sp66 ) + ( H6 /FPGA_Sp67 ) + ( H7 GND ) + ( H8 ? ) + ( H9 +2.5V ) + ( H10 ? ) + ( H11 ? ) + ( H12 ? ) + ( H13 ? ) + ( H14 ? ) + ( H15 +2.5V ) + ( H16 ? ) + ( H17 ? ) + ( H18 ? ) + ( H19 /FPGA_Sp68 ) + ( H20 /FPGA_Sp69 ) + ( H21 /FPGA_Sp70 ) + ( H22 /FPGA_Sp71 ) + ( J1 /DDR_Ban72 ) + ( J2 GND ) + ( J3 /FPGA_Sp73 ) + ( J4 /FPGA_Sp74 ) + ( J5 +2.5V ) + ( J6 ? ) + ( J7 ? ) + ( J8 +1.2V ) + ( J9 GND ) + ( J10 +1.2V ) + ( J11 GND ) + ( J12 +1.2V ) + ( J13 GND ) + ( J14 +1.2V ) + ( J15 GND ) + ( J16 ? ) + ( J17 /FPGA_Sp75 ) + ( J18 +2.5V ) + ( J19 /DDR_Ban76 ) + ( J20 /DDR_Ban77 ) + ( J21 GND ) + ( J22 /FPGA_Sp78 ) + ( K1 /FPGA_Sp79 ) + ( K2 /FPGA_Sp80 ) + ( K3 /FPGA_Sp81 ) + ( K4 /FPGA_Sp82 ) + ( K5 /FPGA_Sp83 ) + ( K6 /FPGA_Sp84 ) + ( K7 ? ) + ( K8 ? ) + ( K9 +1.2V ) + ( K10 GND ) + ( K11 +1.2V ) + ( K12 ? ) + ( K13 +1.2V ) + ( K14 GND ) + ( K15 +2.5V ) + ( K16 ? ) + ( K17 /FPGA_Sp85 ) + ( K18 ? ) + ( K19 /FPGA_Sp86 ) + ( K20 /FPGA_Sp87 ) + ( K21 /DDR_Ban88 ) + ( K22 /DDR_Ban89 ) + ( L1 ? ) + ( L2 +2.5V ) + ( L3 /DDR_Ban90 ) + ( L4 /DDR_Ban91 ) + ( L5 GND ) + ( L6 ? ) + ( L7 +2.5V ) + ( L8 +2.5V ) + ( L9 GND ) + ( L10 +1.2V ) + ( L11 GND ) + ( L12 +1.2V ) + ( L13 GND ) + ( L14 +1.2V ) + ( L15 ? ) + ( L16 +2.5V ) + ( L17 ? ) + ( L18 GND ) + ( L19 /FPGA_Sp92 ) + ( L20 /FPGA_Sp93 ) + ( L21 +2.5V ) + ( L22 ? ) + ( M1 /FPGA_Sp94 ) + ( M2 /FPGA_Sp95 ) + ( M3 /DDR_Ban96 ) + ( M4 ? ) + ( M5 ? ) + ( M6 ? ) + ( M7 ? ) + ( M8 ? ) + ( M9 +1.2V ) + ( M10 GND ) + ( M11 +1.2V ) + ( M12 GND ) + ( M13 +1.2V ) + ( M14 GND ) + ( M15 +2.5V ) + ( M16 ? ) + ( M17 ? ) + ( M18 /USB/USBA_VM ) + ( M19 ? ) + ( M20 /DDR_Ban97 ) + ( M21 /DDR_Ban98 ) + ( M22 /DDR_Ban99 ) + ( N1 /FPGA_Sp100 ) + ( N2 GND ) + ( N3 /DDR_Ban101 ) + ( N4 ? ) + ( N5 +2.5V ) + ( N6 ? ) + ( N7 ? ) + ( N8 +2.5V ) + ( N9 GND ) + ( N10 +1.2V ) + ( N11 GND ) + ( N12 +1.2V ) + ( N13 GND ) + ( N14 +1.2V ) + ( N15 ? ) + ( N16 /USB/USBA_RCV ) + ( N17 GND ) + ( N18 +2.5V ) + ( N19 ? ) + ( N20 /FPGA_Sp102 ) + ( N21 GND ) + ( N22 /DDR_Ban103 ) + ( P1 /FPGA_Sp104 ) + ( P2 /DDR_Ban105 ) + ( P3 ? ) + ( P4 ? ) + ( P5 ? ) + ( P6 ? ) + ( P7 ? ) + ( P8 ? ) + ( P9 +1.2V ) + ( P10 GND ) + ( P11 +1.2V ) + ( P12 GND ) + ( P13 +1.2V ) + ( P14 GND ) + ( P15 ? ) + ( P16 ? ) + ( P17 /FPGA_Sp106 ) + ( P18 /FPGA_Sp107 ) + ( P19 ? ) + ( P20 ? ) + ( P21 /FPGA_Sp108 ) + ( P22 /DDR_Ban109 ) + ( R1 /FPGA_Sp110 ) + ( R2 +2.5V ) + ( R3 /FPGA_Sp111 ) + ( R4 ? ) + ( R5 GND ) + ( R6 +2.5V ) + ( R7 ? ) + ( R8 ? ) + ( R9 ? ) + ( R10 +2.5V ) + ( R11 ? ) + ( R12 +2.5V ) + ( R13 ? ) + ( R14 +1.2V ) + ( R15 ? ) + ( R16 ? ) + ( R17 ? ) + ( R18 GND ) + ( R19 /USB/USBA_SPD ) + ( R20 /DDR_Ban112 ) + ( R21 +2.5V ) + ( R22 /FPGA_Sp113 ) + ( T1 ? ) + ( T2 /FPGA_Sp114 ) + ( T3 ? ) + ( T4 ? ) + ( T5 ? ) + ( T6 ? ) + ( T7 ? ) + ( T8 ? ) + ( T9 N-000156 ) + ( T10 ? ) + ( T11 ? ) + ( T12 ? ) + ( T13 N-000156 ) + ( T14 ? ) + ( T15 ? ) + ( T16 ? ) + ( T17 ? ) + ( T18 ? ) + ( T19 ? ) + ( T20 ? ) + ( T21 /DDR_Ban115 ) + ( T22 ? ) + ( U1 /FPGA_Sp116 ) + ( U2 GND ) + ( U3 /FPGA_Sp117 ) + ( U4 ? ) + ( U5 +2.5V ) + ( U6 ? ) + ( U7 GND ) + ( U8 ? ) + ( U9 ? ) + ( U10 ? ) + ( U11 +2.5V ) + ( U12 ? ) + ( U13 ? ) + ( U14 ? ) + ( U15 ? ) + ( U16 ? ) + ( U17 ? ) + ( U18 +2.5V ) + ( U19 ? ) + ( U20 /FPGA_Sp118 ) + ( U21 GND ) + ( U22 /DDR_Ban119 ) + ( V1 /FPGA_Sp120 ) + ( V2 /DDR_Ban121 ) + ( V3 ? ) + ( V4 GND ) + ( V5 ? ) + ( V6 +2.5V ) + ( V7 ? ) + ( V8 N-000156 ) + ( V9 ? ) + ( V10 GND ) + ( V11 ? ) + ( V12 N-000156 ) + ( V13 ? ) + ( V14 GND ) + ( V15 ? ) + ( V16 N-000156 ) + ( V17 ? ) + ( V18 ? ) + ( V19 ? ) + ( V20 ? ) + ( V21 /FPGA_Sp122 ) + ( V22 /FPGA_Sp123 ) + ( W1 ? ) + ( W2 +2.5V ) + ( W3 ? ) + ( W4 ? ) + ( W5 N-000156 ) + ( W6 ? ) + ( W7 GND ) + ( W8 ? ) + ( W9 ? ) + ( W10 ? ) + ( W11 ? ) + ( W12 ? ) + ( W13 ? ) + ( W14 ? ) + ( W15 ? ) + ( W16 GND ) + ( W17 ? ) + ( W18 ? ) + ( W19 GND ) + ( W20 ? ) + ( W21 +2.5V ) + ( W22 ? ) + ( Y1 ? ) + ( Y3 ? ) + ( Y4 ? ) + ( Y5 ? ) + ( Y6 ? ) + ( Y7 ? ) + ( Y8 ? ) + ( Y9 ? ) + ( Y10 ? ) + ( Y11 ? ) + ( Y12 ? ) + ( Y13 ? ) + ( Y14 ? ) + ( Y15 ? ) + ( Y16 ? ) + ( Y17 ? ) + ( Y18 ? ) + ( Y19 ? ) + ( Y22 ? ) + ) + ( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG + ( 1 +2.5V ) + ( 2 /DDR_Ban101 ) + ( 3 +2.5V ) + ( 4 /FPGA_Sp100 ) + ( 5 /FPGA_Sp95 ) + ( 6 GND ) + ( 7 /FPGA_Sp94 ) + ( 8 /FPGA_Sp73 ) + ( 9 +2.5V ) + ( 10 /DDR_Ban72 ) + ( 11 /FPGA_Sp80 ) + ( 12 GND ) + ( 13 /FPGA_Sp79 ) + ( 14 ? ) + ( 15 +2.5V ) + ( 16 /DDR_Ban90 ) + ( 17 ? ) + ( 18 +2.5V ) + ( 19 ? ) + ( 20 /DDR_Ban91 ) + ( 21 /FPGA_Sp52 ) + ( 22 /FPGA_Sp82 ) + ( 23 /FPGA_Sp83 ) + ( 24 GND ) + ( 25 ? ) + ( 26 /FPGA_Sp58 ) + ( 27 /DDR_Ban57 ) + ( 28 /DDR_Ban59 ) + ( 29 /FPGA_Sp63 ) + ( 30 /FPGA_Sp62 ) + ( 31 /FPGA_Sp66 ) + ( 32 /FPGA_Sp84 ) + ( 33 +2.5V ) + ( 34 GND ) + ( 35 /FPGA_Sp53 ) + ( 36 /FPGA_Sp81 ) + ( 37 /FPGA_Sp74 ) + ( 38 /FPGA_Sp67 ) + ( 39 /DDR_Banks/M0_A8 ) + ( 40 /FPGA_Sp49 ) + ( 41 /DDR_Ban27 ) + ( 42 /DDR_Ban38 ) + ( 43 ? ) + ( 44 /DDR_Ban64 ) + ( 45 /DDR_Ban39 ) + ( 46 /DDR_Ban65 ) + ( 47 /DDR_Ban96 ) + ( 48 GND ) + ( 49 N-000051 ) + ( 50 ? ) + ( 51 /FPGA_Sp114 ) + ( 52 GND ) + ( 53 ? ) + ( 54 /DDR_Ban105 ) + ( 55 +2.5V ) + ( 56 /FPGA_Sp104 ) + ( 57 /FPGA_Sp111 ) + ( 58 GND ) + ( 59 /FPGA_Sp110 ) + ( 60 /FPGA_Sp117 ) + ( 61 +2.5V ) + ( 62 /FPGA_Sp116 ) + ( 63 /DDR_Ban121 ) + ( 64 GND ) + ( 65 /FPGA_Sp120 ) + ( 66 GND ) + ) + ( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG + ( 1 +2.5V ) + ( 2 /FPGA_Sp102 ) + ( 3 +2.5V ) + ( 4 /DDR_Ban103 ) + ( 5 /DDR_Ban98 ) + ( 6 GND ) + ( 7 /DDR_Ban99 ) + ( 8 /DDR_Ban77 ) + ( 9 +2.5V ) + ( 10 /FPGA_Sp78 ) + ( 11 /DDR_Ban88 ) + ( 12 GND ) + ( 13 /DDR_Ban89 ) + ( 14 ? ) + ( 15 +2.5V ) + ( 16 /FPGA_Sp93 ) + ( 17 ? ) + ( 18 +2.5V ) + ( 19 ? ) + ( 20 /FPGA_Sp92 ) + ( 21 /FPGA_Sp68 ) + ( 22 /FPGA_Sp71 ) + ( 23 /FPGA_Sp70 ) + ( 24 GND ) + ( 25 ? ) + ( 26 /FPGA_Sp75 ) + ( 27 /FPGA_Sp85 ) + ( 28 /FPGA_Sp60 ) + ( 29 /FPGA_Sp55 ) + ( 30 /FPGA_Sp56 ) + ( 31 /FPGA_Sp51 ) + ( 32 /FPGA_Sp61 ) + ( 33 +2.5V ) + ( 34 GND ) + ( 35 /DDR_Banks/M1_A4 ) + ( 36 /FPGA_Sp87 ) + ( 37 /FPGA_Sp86 ) + ( 38 /FPGA_Sp50 ) + ( 39 /FPGA_Sp36 ) + ( 40 /FPGA_Sp37 ) + ( 41 /FPGA_Sp54 ) + ( 42 /DDR_Ban48 ) + ( 43 ? ) + ( 44 /DDR_Ban76 ) + ( 45 /FPGA_Sp47 ) + ( 46 /FPGA_Sp69 ) + ( 47 /DDR_Ban97 ) + ( 48 GND ) + ( 49 N-000050 ) + ( 50 ? ) + ( 51 /DDR_Ban115 ) + ( 52 GND ) + ( 53 ? ) + ( 54 /FPGA_Sp108 ) + ( 55 +2.5V ) + ( 56 /DDR_Ban109 ) + ( 57 /DDR_Ban112 ) + ( 58 GND ) + ( 59 /FPGA_Sp113 ) + ( 60 /FPGA_Sp118 ) + ( 61 +2.5V ) + ( 62 /DDR_Ban119 ) + ( 63 /FPGA_Sp122 ) + ( 64 GND ) + ( 65 /FPGA_Sp123 ) + ( 66 GND ) + ) + ( /4C4320F3/4C432132 LQFP48 U4 K8001 + ( 1 /Etherne11 ) + ( 2 /Etherne28 ) + ( 3 /FPGA_Sp29 ) + ( 4 /Etherne23 ) + ( 5 /Etherne15 ) + ( 6 /Etherne30 ) + ( 7 3.3V ) + ( 8 GND ) + ( 9 /FPGA_Sp16 ) + ( 10 /FPGA_Sp44 ) + ( 11 /FPGA_Sp24 ) + ( 12 GND ) + ( 13 /Etherne1 ) + ( 14 /FPGA_Sp17 ) + ( 15 /FPGA_Sp42 ) + ( 16 /Etherne43 ) + ( 17 /Etherne31 ) + ( 18 /Etherne32 ) + ( 19 /Etherne18 ) + ( 20 /Etherne41 ) + ( 21 /FPGA_Sp19 ) + ( 22 /Etherne25 ) + ( 23 GND ) + ( 24 3.3V ) + ( 25 /Etherne14 ) + ( 26 /Etherne12 ) + ( 27 /Etherne13 ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 /Etherne2 ) + ( 32 N-000338 ) + ( 33 N-000328 ) + ( 34 ? ) + ( 35 GND ) + ( 36 GND ) + ( 37 N-000337 ) + ( 38 /Etherne3 ) + ( 39 GND ) + ( 40 N-000339 ) + ( 41 N-000327 ) + ( 42 ? ) + ( 43 ? ) + ( 44 GND ) + ( 45 ? ) + ( 46 /FPGA_Sp33 ) + ( 47 /Etherne4 ) + ( 48 /FPGA_Sp40 ) + ) + ( /4C4227FE/4B76F108 NAND-48TSOP U5 NAND + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 /Non_vol124 ) + ( 7 /Non_vol124 ) + ( 8 ? ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 3.3V ) + ( 13 GND ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ( 17 ? ) + ( 18 ? ) + ( 19 3.3V ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 ? ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 ? ) + ( 29 /Non_vol46 ) + ( 30 /FPGA_Sp22 ) + ( 31 /FPGA_Sp35 ) + ( 32 /Non_vol21 ) + ( 33 ? ) + ( 34 ? ) + ( 35 ? ) + ( 36 GND ) + ( 37 +3.3V ) + ( 38 ? ) + ( 39 ? ) + ( 40 ? ) + ( 41 /Non_vol26 ) + ( 42 /FPGA_Sp34 ) + ( 43 /Non_vol45 ) + ( 44 /FPGA_Sp20 ) + ( 45 ? ) + ( 46 ? ) + ( 47 ? ) + ( 48 ? ) + ) + ( /4C5F1EDC/4C5F2025 TSSOP-14 U6 MIC2550AYTS + ( 1 +2.5V ) + ( 2 /USB/USBA_SPD ) + ( 3 /USB/USBA_RCV ) + ( 4 /FPGA_Sp106 ) + ( 5 /USB/USBA_VM ) + ( 7 GND ) + ( 8 GND ) + ( 9 /FPGA_Sp107 ) + ( 10 N-000365 ) + ( 11 N-000368 ) + ( 12 3.3V ) + ( 14 3.3V ) + ) + ( /4C5F1EDC/4C6552BF TSSOP-14 U7 MIC2550AYTS + ( 1 +2.5V ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 7 GND ) + ( 8 GND ) + ( 9 ? ) + ( 10 N-000358 ) + ( 11 N-000353 ) + ( 12 3.3V ) + ( 14 3.3V ) + ) + ( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 + ( 1 N-000368 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 + ( 1 N-000365 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C6552B8 0603 V3 V0402MHS03 + ( 1 N-000353 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C6552B9 0603 V4 V0402MHS03 + ( 1 N-000358 ) + ( 2 GND ) ) ) * { Allowed footprints by component: -$component R10 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C16 - SM* - C? - C1-1 -$endlist -$component C15 - SM* - C? - C1-1 -$endlist -$component C14 - SM* - C? - C1-1 -$endlist -$component C13 - SM* - C? - C1-1 -$endlist -$component C9 - SM* - C? - C1-1 -$endlist -$component C6 - SM* - C? - C1-1 -$endlist -$component C4 +$component C1 SM* C? C1-1 @@ -1043,12 +1061,12 @@ $component C2 C? C1-1 $endlist -$component C8 +$component C3 SM* C? C1-1 $endlist -$component C7 +$component C4 SM* C? C1-1 @@ -1058,12 +1076,167 @@ $component C5 C? C1-1 $endlist -$component C3 +$component C6 SM* C? C1-1 $endlist -$component C1 +$component C7 + SM* + C? + C1-1 +$endlist +$component C8 + SM* + C? + C1-1 +$endlist +$component C9 + SM* + C? + C1-1 +$endlist +$component C10 + SM* + C? + C1-1 +$endlist +$component C11 + SM* + C? + C1-1 +$endlist +$component C12 + SM* + C? + C1-1 +$endlist +$component C13 + SM* + C? + C1-1 +$endlist +$component C14 + SM* + C? + C1-1 +$endlist +$component C15 + SM* + C? + C1-1 +$endlist +$component C16 + SM* + C? + C1-1 +$endlist +$component C17 + SM* + C? + C1-1 +$endlist +$component C18 + SM* + C? + C1-1 +$endlist +$component C19 + SM* + C? + C1-1 +$endlist +$component C20 + SM* + C? + C1-1 +$endlist +$component C21 + SM* + C? + C1-1 +$endlist +$component C22 + SM* + C? + C1-1 +$endlist +$component C23 + SM* + C? + C1-1 +$endlist +$component C24 + SM* + C? + C1-1 +$endlist +$component C25 + SM* + C? + C1-1 +$endlist +$component C26 + SM* + C? + C1-1 +$endlist +$component C27 + SM* + C? + C1-1 +$endlist +$component C28 + SM* + C? + C1-1 +$endlist +$component C29 + SM* + C? + C1-1 +$endlist +$component C30 + SM* + C? + C1-1 +$endlist +$component C31 + SM* + C? + C1-1 +$endlist +$component C32 + SM* + C? + C1-1 +$endlist +$component C33 + SM* + C? + C1-1 +$endlist +$component C34 + SM* + C? + C1-1 +$endlist +$component C35 + SM* + C? + C1-1 +$endlist +$component C36 + SM* + C? + C1-1 +$endlist +$component C37 + SM* + C? + C1-1 +$endlist +$component C38 SM* C? C1-1 @@ -1080,27 +1253,6 @@ $component R2 SM0805 R?-* $endlist -$component C11 - SM* - C? - C1-1 -$endlist -$component C10 - SM* - C? - C1-1 -$endlist -$component C12 - SM* - C? - C1-1 -$endlist -$component R9 - R? - SM0603 - SM0805 - R?-* -$endlist $component R3 R? SM0603 @@ -1113,19 +1265,13 @@ $component R4 SM0805 R?-* $endlist -$component R6 - R? - SM0603 - SM0805 - R?-* -$endlist $component R5 R? SM0603 SM0805 R?-* $endlist -$component R8 +$component R6 R? SM0603 SM0805 @@ -1137,75 +1283,35 @@ $component R7 SM0805 R?-* $endlist -$component C34 - SM* - C? - C1-1 +$component R8 + R? + SM0603 + SM0805 + R?-* $endlist -$component C33 - SM* - C? - C1-1 +$component R9 + R? + SM0603 + SM0805 + R?-* $endlist -$component C28 - SM* - C? - C1-1 +$component R10 + R? + SM0603 + SM0805 + R?-* $endlist -$component C29 - SM* - C? - C1-1 +$component R11 + R? + SM0603 + SM0805 + R?-* $endlist -$component C31 - SM* - C? - C1-1 -$endlist -$component C30 - SM* - C? - C1-1 -$endlist -$component C32 - SM* - C? - C1-1 -$endlist -$component C27 - SM* - C? - C1-1 -$endlist -$component C21 - SM* - C? - C1-1 -$endlist -$component C26 - SM* - C? - C1-1 -$endlist -$component C24 - SM* - C? - C1-1 -$endlist -$component C25 - SM* - C? - C1-1 -$endlist -$component C23 - SM* - C? - C1-1 -$endlist -$component C22 - SM* - C? - C1-1 +$component R12 + R? + SM0603 + SM0805 + R?-* $endlist $component R13 R? @@ -1219,783 +1325,11 @@ $component R14 SM0805 R?-* $endlist -$component R12 +$component R15 R? SM0603 SM0805 R?-* $endlist -$component R11 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C19 - SM* - C? - C1-1 -$endlist -$component C20 - SM* - C? - C1-1 -$endlist -$component C18 - SM* - C? - C1-1 -$endlist -$component C17 - SM* - C? - C1-1 -$endlist $endfootprintlist } -{ Pin List by Nets -Net 1 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" - U1 C10 - U4 46 -Net 2 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" - U1 D8 - U4 15 -Net 3 "/DDR Banks/M0_WE#" "M0_WE#" - U1 F2 - U2 21 -Net 4 "/Non volatile memories/NF_RNB" "NF_RNB" - U5 7 - U5 6 -Net 11 "/Non volatile memories/SD_CMD" "SD_CMD" - J1 3 - U1 D17 -Net 12 "/FPGA Spartan6/SD_CLK" "SD_CLK" - J1 5 - U1 E16 -Net 13 "/Ethernet Phy/ETH_INT" "ETH_INT" - U1 A4 - U4 25 -Net 14 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" - U1 A7 - U4 9 -Net 15 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" - U4 11 - U1 B8 -Net 16 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" - U1 A8 - U4 14 -Net 17 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" - U1 D9 - U4 16 -Net 18 "/Ethernet Phy/ETH_MDC" "ETH_MDC" - U4 2 - U1 C5 -Net 19 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" - R1 1 - U1 A5 - U4 1 -Net 20 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" - U1 D6 - U4 48 -Net 21 "/FPGA Spartan6/ETH_RXC" "ETH_RXC" - U4 10 - U1 D10 -Net 22 "/Ethernet Phy/ETH_COL" "ETH_COL" - U1 A10 - U4 21 -Net 23 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" - U1 B10 - U4 22 -Net 24 "/DDR Banks/M1_UDM" "M1_UDM" - U1 M20 - U3 47 -Net 25 "/DDR Banks/M1_LDQS" "M1_LDQS" - U3 16 - U1 L20 -Net 26 "/FPGA Spartan6/M1_LDM" "M1_LDM" - U3 20 - U1 L19 -Net 27 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" - U3 51 - U1 T21 -Net 28 "/FPGA Spartan6/M0_UDQS" "M0_UDQS" - U2 51 - U1 T2 -Net 29 "/DDR Banks/M0_LDM" "M0_LDM" - U1 L4 - U2 20 -Net 30 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" - U1 H22 - U3 22 -Net 31 "/DDR Banks/M1_CKE" "M1_CKE" - U1 D21 - U3 45 -Net 32 "GND" "GND" - U4 44 - U1 G5 - V2 2 - U1 AA9 - U1 AB22 - U1 AA13 - U4 23 - U1 AA17 - C15 2 - U1 N13 - C10 2 - U1 K14 - U3 66 - U1 M14 - C11 2 - R2 2 - U1 P14 - U1 V14 - U3 48 - U3 58 - U3 52 - U1 E15 - U3 24 - U3 34 - U3 64 - L5 2 - U1 V10 - U1 K10 - U1 M10 - U1 P10 - U4 12 - U1 B9 - C13 2 - C14 2 - U1 J11 - U1 L11 - U1 N11 - U1 J9 - U6 8 - U6 7 - U1 B17 - U1 W16 - U5 13 - U1 AA5 - U1 W7 - U1 U7 - U1 H7 - J1 COM - J1 CASE - J1 CASE - J1 CASE - R9 2 - U1 J15 - U1 R5 - U5 36 - U1 L5 - U1 E7 - U2 34 - U2 24 - U1 R18 - U1 L18 - U1 G18 - U2 58 - U2 48 - U1 D18 - U1 N17 - U2 66 - U3 6 - U1 L13 - U1 J13 - U1 W19 - U3 12 - U2 64 - C12 2 - J1 6 - U4 8 - U2 6 - U2 52 - U2 12 - C30 2 - C31 2 - C22 2 - C23 2 - C25 2 - C24 2 - C26 2 - C29 2 - C21 2 - C27 2 - C32 2 - C2 2 - U1 L9 - C28 2 - C33 2 - C34 2 - U4 39 - U1 E21 - U1 A1 - U1 E2 - U1 J2 - U1 N2 - U1 U2 - U1 D4 - C1 2 - C3 2 - C5 2 - C7 2 - U1 V4 - C8 2 - U1 B5 - U1 U21 - J4 5 - J4 4 - U1 AB1 - U1 J21 - U1 N21 - V1 2 - U1 P12 - U1 A22 - U1 B13 - U1 N9 - C16 2 - R10 2 - U4 36 - U4 35 - U1 M12 -Net 33 "/DDR Banks/M0_CKE" "M0_CKE" - U2 45 - U1 D2 -Net 34 "/DDR Banks/M0_CAS#" "M0_CAS#" - U1 K4 - U2 22 -Net 35 "/DDR Banks/M1_WE#" "M1_WE#" - U1 H19 - U3 21 -Net 36 "/DDR Banks/M1_RAS#" "M1_RAS#" - U1 H21 - U3 23 -Net 37 "/DDR Banks/M0_RAS#" "M0_RAS#" - U1 K5 - U2 23 -Net 38 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" - U1 L3 - U2 16 -Net 39 "/FPGA Spartan6/M0_UDM" "M0_UDM" - U1 M3 - U2 47 -Net 40 "/USB/USBA_VM" "USBA_VM" - U6 5 - U1 M18 -Net 41 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" - U1 N16 - U6 3 -Net 42 "/USB/USBA_SPD" "USBA_SPD" - U6 2 - U1 R19 -Net 43 "/DDR Banks/M0_CLK#" "M0_CLK#" - U1 H3 - U2 44 -Net 44 "/DDR Banks/M0_CLK" "M0_CLK" - U1 H4 - U2 46 -Net 45 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" - U3 44 - U1 J19 -Net 46 "/DDR Banks/M1_CLK" "M1_CLK" - U3 46 - U1 H20 -Net 47 "/FPGA Spartan6/USBA_VP" "USBA_VP" - U1 P17 - U6 4 -Net 48 "/USB/USBA_OE_N" "USBA_OE_N" - U6 9 - U1 P18 -Net 49 "" "" - R14 2 - C20 2 -Net 50 "" "" - R14 1 - R13 2 - C19 2 - C20 1 - U3 49 -Net 51 "" "" - R12 1 - R11 2 - U2 49 - C17 2 - C18 1 -Net 52 "+2.5V" "+2.5V" - U1 M15 - U1 D16 - U1 L7 - U1 L16 - U6 1 - U1 W2 - U1 H15 - U1 K15 - U1 R2 - U1 L2 - U1 C2 - U1 G2 - U1 E19 - U1 J18 - U1 R21 - U1 N18 - U1 L21 - U1 U18 - U1 G21 - U1 F4 - U1 W21 - U1 C21 - U2 61 - U2 33 - U2 1 - U2 3 - U2 9 - C29 1 - C28 1 - C33 1 - U1 G12 - U1 J5 - U1 N5 - U2 15 - U3 55 - U2 55 - U1 U5 - U1 F6 - U1 R10 - U3 9 - U1 F11 - U3 61 - R11 1 - C19 1 - C17 1 - U1 H9 - U3 3 - U3 1 - U1 R12 - U1 L8 - U2 18 - U1 N8 - U1 R6 - C24 1 - C25 1 - C23 1 - U1 V6 - C22 1 - R13 1 - C21 1 - C27 1 - C32 1 - C30 1 - C31 1 - U1 U11 - U3 18 - U3 15 - C26 1 - C34 1 - U3 33 -Net 53 "" "" - R12 2 - C18 2 -Net 98 "3.3V" "3.3V" - U4 24 - R4 1 - R6 1 - R5 1 - J4 3 - J4 6 - J4 9 - J4 11 - L2 1 - C5 1 - C3 1 - C1 1 - R1 2 - U6 12 - U6 14 - R3 1 - U5 19 - U5 12 - C11 1 - U4 7 - C10 1 -Net 99 "+3.3V" "+3.3V" - U1 B19 - U1 E17 - U1 B7 - U1 B4 - U1 E13 - U1 G14 - U1 B15 - U1 B11 - U5 37 - U1 G10 - U1 E9 -Net 110 "" "" - U1 V16 - U1 AA15 - U1 AA11 - U1 AA7 - U1 T13 - U1 AA3 - U1 AA19 - U1 V8 - U1 T9 - U1 V12 - U1 W5 -Net 111 "+1.2V" "+1.2V" - U1 J8 - U1 P13 - U1 N12 - U1 M13 - U1 K13 - U1 N14 - U1 L14 - U1 M9 - U1 J12 - U1 L12 - U1 J14 - U1 L10 - U1 R14 - U1 J10 - U1 K11 - U1 M11 - U1 K9 - U1 P9 - U1 P11 - U1 N10 -Net 326 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - U4 26 - R7 2 -Net 327 "" "" - R3 2 - U4 41 - J4 1 -Net 328 "" "" - J4 7 - R5 2 - U4 33 -Net 329 "" "" - C12 1 - R9 1 - J4 13 - J4 14 -Net 330 "" "" - J4 10 - R7 1 -Net 331 "" "" - L1 1 - C4 1 -Net 332 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" - U4 13 - C2 1 -Net 333 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - L3 2 - C9 1 - U4 47 -Net 336 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - L3 1 - L1 2 - U4 31 - C6 1 -Net 337 "" "" - U4 37 - R2 1 -Net 338 "" "" - U4 32 - J4 8 - R6 2 -Net 339 "" "" - R4 2 - J4 2 - U4 40 -Net 340 "" "" - C9 2 - C6 2 - C4 2 -Net 341 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - C7 1 - C8 1 - L2 2 - U4 38 -Net 342 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - R8 2 - U4 27 -Net 343 "" "" - J4 12 - R8 1 -Net 349 "" "" - V2 1 - J5 2 - U6 10 - V2 1 -Net 350 "" "" - F1 1 - L4 1 -Net 351 "" "" - J5 4 - L5 1 -Net 353 "" "" - V1 1 - V1 1 - U6 11 - J5 3 -Net 354 "" "" - J5 S1 - J5 S2 - J5 S3 - J5 S4 - R10 1 - C16 1 -Net 355 "" "" - J5 1 - L4 2 -Net 356 "" "" - C13 1 - C14 1 - C15 1 -Net 357 "/Non volatile memories/SD_DAT3" "SD_DAT3" - U1 C17 - J1 2 -Net 358 "/Non volatile memories/SD_DAT2" "SD_DAT2" - J1 1 - U1 A17 -Net 359 "/FPGA Spartan6/SD_DAT1" "SD_DAT1" - U1 B18 - J1 8 -Net 360 "/Non volatile memories/SD_DAT0" "SD_DAT0" - J1 7 - U1 A18 -Net 361 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" - U4 20 - U1 D7 -Net 362 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" - U4 19 - U1 A9 -Net 363 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" - U4 18 - U1 C9 -Net 364 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" - U1 C8 - U4 17 -Net 365 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" - U4 3 - U1 C6 -Net 366 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" - U4 4 - U1 B6 -Net 367 "/DDR Banks/M1_BA1" "M1_BA1" - U1 K17 - U3 27 -Net 368 "/FPGA Spartan6/M1_BA0" "M1_BA0" - U1 J17 - U3 26 -Net 369 "/FPGA Spartan6/M0_BA1" "M0_BA1" - U1 G1 - U2 27 -Net 370 "/FPGA Spartan6/M0_BA0" "M0_BA0" - U1 G3 - U2 26 -Net 371 "/Non volatile memories/NF_D7" "NF_D7" - U5 44 - U1 A11 -Net 372 "/FPGA Spartan6/NF_D6" "NF_D6" - U1 D11 - U5 43 -Net 373 "/Non volatile memories/NF_D5" "NF_D5" - U1 C12 - U5 42 -Net 374 "/FPGA Spartan6/NF_D4" "NF_D4" - U5 41 - U1 B12 -Net 375 "/FPGA Spartan6/NF_D3" "NF_D3" - U1 A12 - U5 32 -Net 376 "/FPGA Spartan6/NF_D2" "NF_D2" - U1 C13 - U5 31 -Net 377 "/FPGA Spartan6/NF_D1" "NF_D1" - U1 A13 - U5 30 -Net 378 "/Non volatile memories/NF_D0" "NF_D0" - U5 29 - U1 D14 -Net 379 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" - U1 A6 - U4 5 -Net 380 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" - U1 C7 - U4 6 -Net 381 "/DDR Banks/M1_A8" "M1_A8" - U3 39 - U1 C20 -Net 382 "/FPGA Spartan6/M1_A7" "M1_A7" - U1 E20 - U3 38 -Net 383 "/FPGA Spartan6/M1_A6" "M1_A6" - U3 37 - U1 K19 -Net 384 "/DDR Banks/M1_A5" "M1_A5" - U3 36 - U1 K20 -Net 385 "/FPGA Spartan6/M1_A4" "M1_A4" - U1 F20 - U3 35 -Net 386 "/FPGA Spartan6/M1_A3" "M1_A3" - U3 32 - U1 G20 -Net 387 "/FPGA Spartan6/M1_A2" "M1_A2" - U3 31 - U1 E22 -Net 388 "/FPGA Spartan6/M1_A1" "M1_A1" - U1 F22 - U3 30 -Net 389 "/FPGA Spartan6/M1_A0" "M1_A0" - U1 F21 - U3 29 -Net 390 "/FPGA Spartan6/M0_A12" "M0_A12" - U2 42 - U1 D1 -Net 391 "/DDR Banks/M0_A11" "M0_A11" - U1 C1 - U2 41 -Net 392 "/FPGA Spartan6/M0_A10" "M0_A10" - U1 G4 - U2 28 -Net 393 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" - U1 V22 - U3 65 -Net 394 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" - U1 V21 - U3 63 -Net 395 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" - U3 62 - U1 U22 -Net 396 "/DDR Banks/M1_DQ12" "M1_DQ12" - U1 U20 - U3 60 -Net 397 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" - U3 59 - U1 R22 -Net 398 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" - U3 57 - U1 R20 -Net 399 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" - U1 P22 - U3 56 -Net 400 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" - U1 P21 - U3 54 -Net 401 "/DDR Banks/M1_DQ7" "M1_DQ7" - U3 13 - U1 K22 -Net 402 "/DDR Banks/M1_DQ6" "M1_DQ6" - U1 K21 - U3 11 -Net 403 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" - U1 J22 - U3 10 -Net 404 "/DDR Banks/M1_DQ4" "M1_DQ4" - U1 J20 - U3 8 -Net 405 "/DDR Banks/M1_DQ3" "M1_DQ3" - U1 M22 - U3 7 -Net 406 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" - U1 M21 - U3 5 -Net 407 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" - U3 4 - U1 N22 -Net 408 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" - U3 2 - U1 N20 -Net 409 "/FPGA Spartan6/M1_A12" "M1_A12" - U1 D22 - U3 42 -Net 410 "/FPGA Spartan6/M1_A11" "M1_A11" - U3 41 - U1 F19 -Net 411 "/DDR Banks/M1_A10" "M1_A10" - U1 G19 - U3 28 -Net 412 "/FPGA Spartan6/M1_A9" "M1_A9" - U1 C22 - U3 40 -Net 413 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" - U1 K1 - U2 13 -Net 414 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" - U1 K2 - U2 11 -Net 415 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" - U1 J1 - U2 10 -Net 416 "/DDR Banks/M0_DQ4" "M0_DQ4" - U2 8 - U1 J3 -Net 417 "/DDR Banks/M0_DQ3" "M0_DQ3" - U2 7 - U1 M1 -Net 418 "/DDR Banks/M0_DQ2" "M0_DQ2" - U2 5 - U1 M2 -Net 419 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" - U1 N1 - U2 4 -Net 420 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" - U1 N3 - U2 2 -Net 421 "/FPGA Spartan6/M0_A9" "M0_A9" - U1 E1 - U2 40 -Net 422 "/DDR Banks/M0_A8" "M0_A8" - U1 E3 - U2 39 -Net 423 "/DDR Banks/M0_A7" "M0_A7" - U2 38 - U1 H6 -Net 424 "/FPGA Spartan6/M0_A6" "M0_A6" - U1 J4 - U2 37 -Net 425 "/FPGA Spartan6/M0_A5" "M0_A5" - U1 K3 - U2 36 -Net 426 "/FPGA Spartan6/M0_A4" "M0_A4" - U2 35 - U1 F3 -Net 427 "/DDR Banks/M0_A3" "M0_A3" - U1 K6 - U2 32 -Net 428 "/FPGA Spartan6/M0_A2" "M0_A2" - U2 31 - U1 H5 -Net 429 "/FPGA Spartan6/M0_A1" "M0_A1" - U1 H1 - U2 30 -Net 430 "/FPGA Spartan6/M0_A0" "M0_A0" - U2 29 - U1 H2 -Net 431 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" - U2 65 - U1 V1 -Net 432 "/DDR Banks/M0_DQ14" "M0_DQ14" - U1 V2 - U2 63 -Net 433 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" - U1 U1 - U2 62 -Net 434 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" - U2 60 - U1 U3 -Net 435 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" - U2 59 - U1 R1 -Net 436 "/DDR Banks/M0_DQ10" "M0_DQ10" - U2 57 - U1 R3 -Net 437 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" - U1 P1 - U2 56 -Net 438 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" - U2 54 - U1 P2 -} -#End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 01a41d9..aa279c8 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Fri 13 Aug 2010 06:15:05 AM COT +update=Fri 13 Aug 2010 09:21:41 AM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index e9a9bdc..8dfd54a 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 09:19:35 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001