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Code

ddr mobile replaced by ddr

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This commit is contained in:
Andres Calderon 2010-08-03 21:23:17 -05:00
parent 1e0102079e
commit 3e25e8dec9
11 changed files with 2136 additions and 2978 deletions
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3
kicad/modules/60fbga_ddr.mdc Normal file
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@ -0,0 +1,3 @@
PCBNEW-LibDoc----V1 27/9/2008-16:35:21
#
$EndLIBDOC

1557
kicad/xue-rnc/DRAM.sch
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9
kicad/xue-rnc/FPGA.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Wed 28 Jul 2010 06:08:38 AM COT
EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT
LIBS:power
LIBS:device
LIBS:transistors
@ -29,13 +29,14 @@ LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:micron_ddr_512Mb
LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A2 23400 16535
Sheet 3 5
Title ""
Date "28 jul 2010"
Date "4 aug 2010"
Rev ""
Comp ""
Comment1 ""
@ -469,10 +470,10 @@ M0_CLK
Text HLabel 7700 4700 2 60 Output ~ 0
M0_CLK#
$Comp
L GND #PWR?
L GND #PWR01
U 1 1 4C439B7E
P 13450 15700
F 0 "#PWR?" H 13450 15700 30 0001 C CNN
F 0 "#PWR01" H 13450 15700 30 0001 C CNN
F 1 "GND" H 13450 15630 30 0001 C CNN
1 13450 15700
1 0 0 -1

13
kicad/xue-rnc/NV_MEMORIES.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Wed 28 Jul 2010 06:08:38 AM COT
EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT
LIBS:power
LIBS:device
LIBS:transistors
@ -29,13 +29,14 @@ LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:micron_ddr_512Mb
LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 4 5
Title ""
Date "28 jul 2010"
Date "4 aug 2010"
Rev ""
Comp ""
Comment1 ""
@ -161,19 +162,19 @@ Wire Wire Line
4400 5750 4400 5950
Connection ~ 4400 5850
$Comp
L GND #PWR4
L GND #PWR02
U 1 1 4C438ADC
P 4400 5950
F 0 "#PWR4" H 4400 5950 30 0001 C CNN
F 0 "#PWR02" H 4400 5950 30 0001 C CNN
F 1 "GND" H 4400 5880 30 0001 C CNN
1 4400 5950
1 0 0 -1
$EndComp
$Comp
L GND #PWR3
L GND #PWR03
U 1 1 4C438AD5
P 3950 6300
F 0 "#PWR3" H 3950 6300 30 0001 C CNN
F 0 "#PWR03" H 3950 6300 30 0001 C CNN
F 1 "GND" H 3950 6230 30 0001 C CNN
1 3950 6300
1 0 0 -1

5
kicad/xue-rnc/eth_phy.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Wed 28 Jul 2010 06:08:38 AM COT
EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT
LIBS:power
LIBS:device
LIBS:transistors
@ -29,13 +29,14 @@ LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:micron_ddr_512Mb
LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 2 5
Title ""
Date "28 jul 2010"
Date "4 aug 2010"
Rev ""
Comp ""
Comment1 ""

160
kicad/xue-rnc/xue-rnc-cache.lib
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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Wed 28 Jul 2010 06:08:38 AM COT
EESchema-LIBRARY Version 2.3 Date: Tue 03 Aug 2010 09:21:21 PM COT
#
# GND
#
@ -150,103 +150,73 @@ X CASE3 CASE 1350 300 150 L 25 25 1 1 B
ENDDRAW
ENDDEF
#
# MT46HC64M32LFCM
# MT46V32M16FN
#
DEF MT46HC64M32LFCM U 0 40 Y Y 1 F N
DEF MT46V32M16FN U 0 40 Y Y 1 F N
F0 "U" 0 100 70 H V C CNN
F1 "MT46HC64M32LFCM" 0 -100 70 H V C CNN
F1 "MT46V32M16FN" 0 -100 70 H V C CNN
DRAW
S -900 -1700 900 1700 1 1 0 f
X VSS A1 -600 -2000 300 U 60 60 1 1 P
X VDDQ B1 -200 2000 300 D 60 60 1 1 P
X VSSQ C1 -100 -2000 300 U 60 60 1 1 P
X VDDQ D1 0 2000 300 D 60 60 1 1 P
X VSSQ E1 0 -2000 300 U 60 60 1 1 P
X VDD F1 -500 2000 300 D 60 60 1 1 P
X CKE G1 -1200 -100 300 R 60 60 1 1 P
X A9 H1 -1200 700 300 R 60 60 1 1 P
X A6 J1 -1200 1000 300 R 60 60 1 1 P
X A4 K1 -1200 1200 300 R 60 60 1 1 P
X VSSQ L1 100 -2000 300 U 60 60 1 1 P
X VDDQ M1 300 2000 300 D 60 60 1 1 P
X VSSQ N1 300 -2000 300 U 60 60 1 1 P
X VDDQ P1 500 2000 300 D 60 60 1 1 P
X VSS R1 -400 -2000 300 U 60 60 1 1 P
X DQ31 A2 1200 800 300 L 60 60 1 1 P
X DQ29 B2 1200 600 300 L 60 60 1 1 P
X DQ27 C2 1200 400 300 L 60 60 1 1 P
X DQ25 D2 1200 200 300 L 60 60 1 1 P
X DQS3 E2 1200 1200 300 L 60 60 1 1 P
X DM3 F2 -1200 -800 300 R 60 60 1 1 P
X CLK G2 -1200 -200 300 R 60 60 1 1 P
X A11 H2 -1200 500 300 R 60 60 1 1 P
X A7 J2 -1200 900 300 R 60 60 1 1 P
X DM1 K2 -1200 -600 300 R 60 60 1 1 P
X DQS1 L2 1200 1000 300 L 60 60 1 1 P
X DQ9 M2 1200 -1400 300 L 60 60 1 1 P
X DQ11 N2 1200 -1200 300 L 60 60 1 1 P
X DQ13 P2 1200 -1000 300 L 60 60 1 1 P
X DQ15 R2 1200 -800 300 L 60 60 1 1 P
X VSSQ A3 -300 -2000 300 U 60 60 1 1 P
X DQ30 B3 1200 700 300 L 60 60 1 1 P
X DQ28 C3 1200 500 300 L 60 60 1 1 P
X DQ26 D3 1200 300 300 L 60 60 1 1 P
X DQ24 E3 1200 100 300 L 60 60 1 1 P
X NC F3 1200 1300 300 L 60 60 1 1 P
X CLK# G3 -1200 -300 300 R 60 60 1 1 I I
X A12 H3 -1200 400 300 R 60 60 1 1 P
X A8 J3 -1200 800 300 R 60 60 1 1 P
X A5 K3 -1200 1100 300 R 60 60 1 1 P
X DQ8 L3 1200 -1500 300 L 60 60 1 1 P
X DQ10 M3 1200 -1300 300 L 60 60 1 1 P
X DQ12 N3 1200 -1100 300 L 60 60 1 1 P
X DQ14 P3 1200 -900 300 L 60 60 1 1 P
X VSSQ R3 500 -2000 300 U 60 60 1 1 P
X VDDQ A7 -300 2000 300 D 60 60 1 1 P
X DQ17 B7 1200 -600 300 L 60 60 1 1 P
X DQ19 C7 1200 -400 300 L 60 60 1 1 P
X DQ21 D7 1200 -200 300 L 60 60 1 1 P
X DQ23 E7 1200 0 300 L 60 60 1 1 P
X A13 F7 -1200 300 300 R 60 60 1 1 P
X WE# G7 1200 1600 300 L 60 60 1 1 I I
X CS# H7 -1200 -400 300 R 60 60 1 1 I I
X A10 J7 -1200 600 300 R 60 60 1 1 P
X A2 K7 -1200 1400 300 R 60 60 1 1 P
X DQ7 L7 1200 -1600 300 L 60 60 1 1 P
X DQ5 M7 -1200 -1400 300 R 60 60 1 1 P
X DQ3 N7 -1200 -1200 300 R 60 60 1 1 P
X DQ1 P7 -1200 -1000 300 R 60 60 1 1 P
X VDDQ R7 600 2000 300 D 60 60 1 1 P
X DQ16 A8 1200 -700 300 L 60 60 1 1 P
X DQ18 B8 1200 -500 300 L 60 60 1 1 P
X DQ20 C8 1200 -300 300 L 60 60 1 1 P
X DQ22 D8 1200 -100 300 L 60 60 1 1 P
X DQS2 E8 1200 1100 300 L 60 60 1 1 P
X DM2 F8 -1200 -700 300 R 60 60 1 1 P
X CAS# G8 -1200 0 300 R 60 60 1 1 I I
X BA0 H8 -1200 200 300 R 60 60 1 1 P
X A0 J8 -1200 1600 300 R 60 60 1 1 P
X DM0 K8 -1200 -500 300 R 60 60 1 1 P
X DQS0 L8 1200 900 300 L 60 60 1 1 P
X DQ6 M8 -1200 -1500 300 R 60 60 1 1 P
X DQ4 N8 -1200 -1300 300 R 60 60 1 1 P
X DQ2 P8 -1200 -1100 300 R 60 60 1 1 P
X DQ0 R8 -1200 -900 300 R 60 60 1 1 P
X VDD A9 -600 2000 300 D 60 60 1 1 P
X VSSQ B9 -200 -2000 300 U 60 60 1 1 P
X VDDQ C9 -100 2000 300 D 60 60 1 1 P
X TEST D9 1200 1500 300 L 60 60 1 1 P
X VDDQ E9 100 2000 300 D 60 60 1 1 P
X VSS F9 -500 -2000 300 U 60 60 1 1 P
X RAS# G9 1200 1400 300 L 60 60 1 1 I I
X BA1 H9 -1200 100 300 R 60 60 1 1 P
X A1 J9 -1200 1500 300 R 60 60 1 1 P
X A3 K9 -1200 1300 300 R 60 60 1 1 P
X VDDQ L9 200 2000 300 D 60 60 1 1 P
X VSSQ M9 200 -2000 300 U 60 60 1 1 P
X VDDQ N9 400 2000 300 D 60 60 1 1 P
X VSSQ P9 400 -2000 300 U 60 60 1 1 P
X VDD R9 -400 2000 300 D 60 60 1 1 P
S -700 -1200 700 1200 1 1 0 f
X VSSQ A1 -100 -1500 300 U 60 60 1 1 P
X DQ14 B1 1000 100 300 L 60 60 1 1 P
X DQ12 C1 1000 -100 300 L 60 60 1 1 P
X DQ10 D1 1000 -300 300 L 60 60 1 1 P
X DQ8 E1 1000 -500 300 L 60 60 1 1 P
X VREF F1 1000 900 300 L 60 60 1 1 P
X DQ15 A2 1000 200 300 L 60 60 1 1 P
X VDDQ B2 0 1500 300 D 60 60 1 1 P
X VSSQ C2 100 -1500 300 U 60 60 1 1 P
X VDDQ D2 200 1500 300 D 60 60 1 1 P
X VSSQ E2 300 -1500 300 U 60 60 1 1 P
X VSS F2 -300 -1500 300 U 60 60 1 1 P
X CLK G2 -1000 -600 300 R 60 60 1 1 P
X A12 H2 -1000 -100 300 R 60 60 1 1 P
X A11 J2 -1000 0 300 R 60 60 1 1 P
X A8 K2 -1000 300 300 R 60 60 1 1 P
X A6 L2 -1000 500 300 R 60 60 1 1 P
X A4 M2 -1000 700 300 R 60 60 1 1 P
X VSS A3 -400 -1500 300 U 60 60 1 1 P
X DQ13 B3 1000 0 300 L 60 60 1 1 P
X DQ11 C3 1000 -200 300 L 60 60 1 1 P
X DQ9 D3 1000 -400 300 L 60 60 1 1 P
X UDQS E3 1000 800 300 L 60 60 1 1 P
X UDM F3 1000 700 300 L 60 60 1 1 P
X CLK_ G3 -1000 -700 300 R 60 60 1 1 P
X CKE H3 -1000 -500 300 R 60 60 1 1 P
X A9 J3 -1000 200 300 R 60 60 1 1 P
X A7 K3 -1000 400 300 R 60 60 1 1 P
X A5 L3 -1000 600 300 R 60 60 1 1 P
X VSS M3 -200 -1500 300 U 60 60 1 1 P
X VDD A7 -400 1500 300 D 60 60 1 1 P
X DQ2 B7 1000 -1100 300 L 60 60 1 1 P
X DQ4 C7 1000 -900 300 L 60 60 1 1 P
X DQ6 D7 1000 -700 300 L 60 60 1 1 P
X LDQS E7 1000 400 300 L 60 60 1 1 P
X LDM F7 1000 300 300 L 60 60 1 1 P
X WE_ G7 1000 1000 300 L 60 60 1 1 P
X RAS_ H7 1000 600 300 L 60 60 1 1 P
X BA1 J7 -1000 -300 300 R 60 60 1 1 P
X A0 K7 -1000 1100 300 R 60 60 1 1 P
X A2 L7 -1000 900 300 R 60 60 1 1 P
X VDD M7 -200 1500 300 D 60 60 1 1 P
X DQ0 A8 -1000 -900 300 R 60 60 1 1 P
X VSSQ B8 0 -1500 300 U 60 60 1 1 P
X VDDQ C8 100 1500 300 D 60 60 1 1 P
X VSSQ D8 200 -1500 300 U 60 60 1 1 P
X VDDQ E8 300 1500 300 D 60 60 1 1 P
X VDD F8 -300 1500 300 D 60 60 1 1 P
X CAS_ G8 -1000 -400 300 R 60 60 1 1 P
X CS_ H8 -1000 -800 300 R 60 60 1 1 P
X BA0 J8 -1000 -200 300 R 60 60 1 1 P
X A10 K8 -1000 100 300 R 60 60 1 1 P
X A1 L8 -1000 1000 300 R 60 60 1 1 P
X A3 M8 -1000 800 300 R 60 60 1 1 P
X VDDQ A9 -100 1500 300 D 60 60 1 1 P
X DQ1 B9 -1000 -1000 300 R 60 60 1 1 P
X DQ3 C9 1000 -1000 300 L 60 60 1 1 P
X DQ5 D9 1000 -800 300 L 60 60 1 1 P
X DQ7 E9 1000 -600 300 L 60 60 1 1 P
X NC F9 1000 500 300 L 60 60 1 1 P
ENDDRAW
ENDDEF
#

2416
kicad/xue-rnc/xue-rnc.brd
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14
kicad/xue-rnc/xue-rnc.cmp
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@ -1,4 +1,4 @@
Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Sun 18 Jul 2010 06:38:38 PM COT
Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Tue 03 Aug 2010 08:52:46 PM COT
BeginCmp
TimeStamp = /4C4227FE/4B76F5E2;
@ -15,17 +15,17 @@ IdModule = FGG484bga-p10;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C43203A;
TimeStamp = /4C421DD3/4C58A711;
Reference = U2;
ValeurCmp = MT46HC64M32LFCM;
IdModule = 90vfbga_mobile_ddr;
ValeurCmp = MT46V32M16TG;
IdModule = 60fbga_ddr;
EndCmp
BeginCmp
TimeStamp = /4C421DD3/4C432040;
TimeStamp = /4C421DD3/4C58A1CF;
Reference = U3;
ValeurCmp = MT46HC64M32LFCM;
IdModule = 90vfbga_mobile_ddr;
ValeurCmp = MT46V32M16TG;
IdModule = 60fbga_ddr;
EndCmp
BeginCmp

834
kicad/xue-rnc/xue-rnc.net
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18
kicad/xue-rnc/xue-rnc.pro
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@ -1,13 +1,8 @@
update=Wed 28 Jul 2010 06:43:00 AM COT
update=Tue 03 Aug 2010 09:21:55 PM COT
version=1
last_client=pcbnew
[general]
version=1
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[eeschema]
version=1
LibDir=
@ -38,9 +33,9 @@ offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
SimCmd=
UseNetN=0
LabSize=60
PrintMonochrome=1
ShowSheetReferenceAndTitleBlock=1
[eeschema/libraries]
LibName1=power
LibName2=device
@ -76,6 +71,12 @@ LibName31=k8001
LibName32=micron_mobile_ddr
LibName33=xc6slx45fgg484
LibName34=xue-nv
LibName35=/home/afc/devel/Qi/xue/kicad/library/micron_ddr_512Mb
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
version=1
PadDrlX=320
@ -111,3 +112,4 @@ LibName12=FGG484bga-p10
LibName13=LQFP48
LibName14=48TSOP-NAND
LibName15=micro-sd
LibName16=60fbga_ddr

85
kicad/xue-rnc/xue-rnc.sch
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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Wed 28 Jul 2010 06:08:38 AM COT
EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT
LIBS:power
LIBS:device
LIBS:transistors
@ -29,13 +29,14 @@ LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:micron_ddr_512Mb
LIBS:xue-rnc-cache
EELAYER 24 0
EELAYER END
$Descr A4 11700 8267
Sheet 1 5
Title ""
Date "28 jul 2010"
Date "4 aug 2010"
Rev ""
Comp ""
Comment1 ""
@ -43,24 +44,24 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Wire Line
4000 2300 2750 2300
Wire Wire Line
2750 4350 4000 4350
Wire Wire Line
7800 4550 7350 4550
Wire Wire Line
4000 2000 2750 2000
Wire Wire Line
2750 4100 4000 4100
Wire Bus Line
4000 3300 4000 3250
Wire Bus Line
4000 3250 2750 3250
Wire Bus Line
2750 1150 4000 1150
4000 1200 4000 1150
Wire Wire Line
2750 4250 4000 4250
Wire Wire Line
2750 2200 4000 2200
Wire Bus Line
4000 1150 4000 1200
Wire Wire Line
4000 4200 2750 4200
Wire Wire Line
2750 2100 4000 2100
4000 1150 2750 1150
$Sheet
S 7800 4450 1450 2200
U 4C4320F3
@ -87,10 +88,10 @@ S 4000 900 3350 5800
U 4C431A63
F0 "FPGA Spartan6" 60
F1 "FPGA.sch" 60
F2 "M1_CLK" O L 4000 2000 60
F3 "M1_CLK#" O L 4000 2100 60
F4 "M0_CLK" O L 4000 4100 60
F5 "M0_CLK#" O L 4000 4200 60
F2 "M1_CLK" O L 4000 2200 60
F3 "M1_CLK#" O L 4000 2300 60
F4 "M0_CLK" O L 4000 4250 60
F5 "M0_CLK#" O L 4000 4350 60
F6 "ETH_INT" I R 7350 4550 60
$EndSheet
$Sheet
@ -104,29 +105,33 @@ S 1650 900 1100 4000
U 4C421DD3
F0 "DDR Banks" 60
F1 "DRAM.sch" 60
F2 "M1_DQ[0..31]" B R 2750 1150 60
F3 "M0_DQ[0..31]" B R 2750 3250 60
F4 "M0_BA[0..1]" I R 2750 3700 60
F5 "M1_BA[0..1]" I R 2750 1600 60
F6 "M0_DM[0..3]" I R 2750 3850 60
F7 "M1_DM[0..3]" I R 2750 1750 60
F8 "M1_A[0..13]" I R 2750 1450 60
F9 "M0_A[0..13]" I R 2750 3550 60
F10 "M0_WE#" I R 2750 4600 60
F11 "M0_RAS#" I R 2750 4450 60
F12 "M1_RAS#" I R 2750 2350 60
F13 "M1_WE#" I R 2750 2500 60
F14 "M0_CAS#" I R 2750 4350 60
F15 "M0_CKE" I R 2750 4000 60
F16 "M0_CLK" I R 2750 4100 60
F17 "M0_CLK#" I R 2750 4200 60
F18 "M0_CS#" I R 2750 3100 60
F19 "M1_CS#" I R 2750 1000 60
F20 "M1_CLK#" I R 2750 2100 60
F21 "M1_CLK" I R 2750 2000 60
F22 "M1_CKE" I R 2750 1900 60
F23 "M1_CAS#" I R 2750 2250 60
F24 "M1_DQS[0..3]" B R 2750 1300 60
F25 "M0_DQS[0..3]" B R 2750 3400 60
F2 "M0_BA[0..1]" I R 2750 3450 60
F3 "M1_BA[0..1]" I R 2750 1350 60
F4 "M0_WE#" I R 2750 4750 60
F5 "M0_RAS#" I R 2750 4600 60
F6 "M1_RAS#" I R 2750 2550 60
F7 "M1_WE#" I R 2750 2700 60
F8 "M0_CAS#" I R 2750 4500 60
F9 "M0_CKE" I R 2750 4150 60
F10 "M0_CLK" I R 2750 4250 60
F11 "M0_CLK#" I R 2750 4350 60
F12 "M0_CS#" I R 2750 3100 60
F13 "M1_CLK#" I R 2750 2300 60
F14 "M1_CLK" I R 2750 2200 60
F15 "M1_CKE" I R 2750 2100 60
F16 "M1_CAS#" I R 2750 2450 60
F17 "M0_DQ[0..15]" B R 2750 3250 60
F18 "M0_UDM" I R 2750 3900 60
F19 "M0_LDQS" I R 2750 3700 60
F20 "M0_A[0..12]" I R 2750 3350 60
F21 "M0_LDM" I R 2750 4000 60
F22 "M0_UDQS" I R 2750 3600 60
F23 "M1_UDQS" I R 2750 1550 60
F24 "M1_LDM" I R 2750 1950 60
F25 "M1_LDQS" I R 2750 1650 60
F26 "M1_UDM" I R 2750 1850 60
F27 "M1_CS#" I R 2750 1000 60
F28 "M1_A[0..12]" I R 2750 1250 60
F29 "M1_DQ[0..15]" B R 2750 1150 60
$EndSheet
$EndSCHEMATC