diff --git a/kicad/xue-rnc/DBG_PRG.sch b/kicad/xue-rnc/DBG_PRG.sch
index 715bc65..d02e54f 100644
--- a/kicad/xue-rnc/DBG_PRG.sch
+++ b/kicad/xue-rnc/DBG_PRG.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 23 Aug 2010 10:36:19 PM COT
+EESchema Schematic File Version 2  date Tue 24 Aug 2010 06:53:07 AM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch
index c07a6fa..25c61b1 100644
--- a/kicad/xue-rnc/DRAM.sch
+++ b/kicad/xue-rnc/DRAM.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 23 Aug 2010 10:36:19 PM COT
+EESchema Schematic File Version 2  date Tue 24 Aug 2010 06:53:07 AM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch
index 72a388c..7c7bcca 100644
--- a/kicad/xue-rnc/FPGA.sch
+++ b/kicad/xue-rnc/FPGA.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 23 Aug 2010 10:36:19 PM COT
+EESchema Schematic File Version 2  date Tue 24 Aug 2010 06:53:07 AM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -59,26 +59,26 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
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+Text HLabel 17500 1800 0    60   BiDi ~ 0
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 Wire Wire Line
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-Text HLabel 17150 800  0    60   BiDi ~ 0
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 USBD_SPD
-Text HLabel 17150 600  0    60   BiDi ~ 0
+Text HLabel 17500 2100 0    60   BiDi ~ 0
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-Text HLabel 17150 900  0    60   BiDi ~ 0
+Text HLabel 17500 2000 0    60   BiDi ~ 0
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-Text HLabel 17150 500  0    60   BiDi ~ 0
+Text HLabel 17500 1900 0    60   BiDi ~ 0
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 Wire Wire Line
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+	17600 2100 17500 2100
 Wire Wire Line
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+	17500 1800 17600 1800
 Wire Wire Line
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+	17600 2000 17500 2000
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+	17600 1900 17500 1900
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 Wire Wire Line
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 Wire Wire Line
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+	5650 14400 5650 14350
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+	4950 14350 4950 14400
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 Connection ~ 2000 12400
 Wire Wire Line
-	2700 12900 2700 12850
+	2700 12850 2700 12900
 Wire Wire Line
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+	2000 12900 2000 12850
 Connection ~ 2000 12900
 Connection ~ 1650 13450
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 Text HLabel 17500 2600 0    60   BiDi ~ 0
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 USBA_RCV
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 USBA_OE_N
 Text HLabel 17500 1600 0    60   BiDi ~ 0
 USBA_SPD
diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch
index 82e0dd1..36da8d2 100644
--- a/kicad/xue-rnc/NV_MEMORIES.sch
+++ b/kicad/xue-rnc/NV_MEMORIES.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 23 Aug 2010 10:36:19 PM COT
+EESchema Schematic File Version 2  date Tue 24 Aug 2010 06:53:07 AM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch
index 448834e..4d28ba4 100644
--- a/kicad/xue-rnc/PSU.sch
+++ b/kicad/xue-rnc/PSU.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 23 Aug 2010 10:36:19 PM COT
+EESchema Schematic File Version 2  date Tue 24 Aug 2010 06:53:07 AM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch
index 4e40c7b..ea44d96 100644
--- a/kicad/xue-rnc/USB.sch
+++ b/kicad/xue-rnc/USB.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 23 Aug 2010 10:36:19 PM COT
+EESchema Schematic File Version 2  date Tue 24 Aug 2010 06:53:07 AM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -59,6 +59,14 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
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+USBD_D+
+Text Label 3950 6450 0    40   ~ 0
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+Text Label 4100 2850 0    40   ~ 0
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+Text Label 4100 2750 0    40   ~ 0
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 $Comp
 L C C86
 U 1 1 4C71C9C5
@@ -74,8 +82,8 @@ L C C87
 U 1 1 4C71C9C4
 P 7850 1500
 F 0 "C87" H 7900 1600 50  0000 L CNN
-F 1 "1uF" H 7900 1400 50  0000 L CNN
-F 2 "0603" H 7850 1500 60  0001 C CNN
+F 1 "100nF" H 7900 1400 50  0000 L CNN
+F 2 "0402" H 7850 1500 60  0001 C CNN
 	1    7850 1500
 	1    0    0    -1  
 $EndComp
@@ -84,7 +92,7 @@ L C C88
 U 1 1 4C71C9C3
 P 8200 1500
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-F 1 "470nF" H 8250 1400 50  0000 L CNN
+F 1 "100nF" H 8250 1400 50  0000 L CNN
 F 2 "0402" H 8200 1500 60  0001 C CNN
 	1    8200 1500
 	1    0    0    -1  
@@ -734,7 +742,8 @@ L C C36
 U 1 1 4C6552BD
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 F 0 "C36" H 2900 5300 50  0000 L CNN
-F 1 "1uF" H 2900 5100 50  0000 L CNN
+F 1 "100nF" H 2900 5100 50  0000 L CNN
+F 2 "0402" H 2850 5200 60  0001 C CNN
 	1    2850 5200
 	1    0    0    -1  
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@@ -743,7 +752,8 @@ L C C37
 U 1 1 4C6552BC
 P 3200 5200
 F 0 "C37" H 3250 5300 50  0000 L CNN
-F 1 "470nF" H 3250 5100 50  0000 L CNN
+F 1 "100nF" H 3250 5100 50  0000 L CNN
+F 2 "0402" H 3200 5200 60  0001 C CNN
 	1    3200 5200
 	1    0    0    -1  
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@@ -977,7 +987,7 @@ L C C15
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-F 1 "470nF" H 3200 1400 50  0000 L CNN
+F 1 "100nF" H 3200 1400 50  0000 L CNN
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 	1    0    0    -1  
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@@ -986,7 +996,8 @@ L C C14
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-F 1 "1uF" H 2850 1400 50  0000 L CNN
+F 1 "100nF" H 2850 1400 50  0000 L CNN
+F 2 "0402" H 2800 1500 60  0001 C CNN
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 	1    0    0    -1  
 $EndComp
diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch
index 58bee4d..4e4937e 100644
--- a/kicad/xue-rnc/eth_phy.sch
+++ b/kicad/xue-rnc/eth_phy.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 23 Aug 2010 10:36:19 PM COT
+EESchema Schematic File Version 2  date Tue 24 Aug 2010 06:53:07 AM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
diff --git a/kicad/xue-rnc/xue-rnc-brd.png b/kicad/xue-rnc/xue-rnc-brd.png
index c371e9f..255bdc7 100644
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index 274e654..263e7b0 100644
--- a/kicad/xue-rnc/xue-rnc-brd.svg
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@@ -54170,8 +53966,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30260">
     <ellipse
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-       cy="27480"
+       cx="56728"
+       cy="27110"
        rx="39"
        ry="39"
        id="ellipse30262" />
@@ -54181,8 +53977,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30264">
     <ellipse
-       cx="54331"
-       cy="30846"
+       cx="55551"
+       cy="32476"
        rx="39"
        ry="39"
        id="ellipse30266" />
@@ -54192,8 +53988,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30268">
     <ellipse
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-       cy="28031"
+       cx="55118"
+       cy="31654"
        rx="39"
        ry="39"
        id="ellipse30270" />
@@ -54203,8 +53999,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30272">
     <ellipse
-       cx="54715"
-       cy="30856"
+       cx="62028"
+       cy="15874"
        rx="39"
        ry="39"
        id="ellipse30274" />
@@ -54214,8 +54010,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30276">
     <ellipse
-       cx="55492"
-       cy="31240"
+       cx="48795"
+       cy="27587"
        rx="39"
        ry="39"
        id="ellipse30278" />
@@ -54225,8 +54021,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30280">
     <ellipse
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-       cy="27687"
+       cx="46543"
+       cy="23642"
        rx="39"
        ry="39"
        id="ellipse30282" />
@@ -54236,8 +54032,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30284">
     <ellipse
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-       cy="27697"
+       cx="53165"
+       cy="20571"
        rx="39"
        ry="39"
        id="ellipse30286" />
@@ -54247,8 +54043,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30288">
     <ellipse
-       cx="55488"
-       cy="30846"
+       cx="59382"
+       cy="30480"
        rx="39"
        ry="39"
        id="ellipse30290" />
@@ -54258,8 +54054,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30292">
     <ellipse
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-       cy="27854"
+       cx="58575"
+       cy="31657"
        rx="39"
        ry="39"
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@@ -54269,8 +54065,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30296">
     <ellipse
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-       cy="31270"
+       cx="60106"
+       cy="26343"
        rx="39"
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@@ -54280,8 +54076,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30300">
     <ellipse
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-       cy="28268"
+       cx="60110"
+       cy="24862"
        rx="39"
        ry="39"
        id="ellipse30302" />
@@ -54291,8 +54087,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31270"
+       cx="53449"
+       cy="26512"
        rx="39"
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@@ -54302,8 +54098,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31319"
+       cx="57654"
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        rx="39"
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@@ -54313,8 +54109,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30312">
     <ellipse
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-       cy="31898"
+       cx="47047"
+       cy="20567"
        rx="39"
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@@ -54324,8 +54120,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30316">
     <ellipse
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-       cy="31937"
+       cx="55876"
+       cy="30453"
        rx="39"
        ry="39"
        id="ellipse30318" />
@@ -54335,8 +54131,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30320">
     <ellipse
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-       cy="31067"
+       cx="54311"
+       cy="30472"
        rx="39"
        ry="39"
        id="ellipse30322" />
@@ -54346,8 +54142,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30324">
     <ellipse
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-       cy="31154"
+       cx="53317"
+       cy="30472"
        rx="39"
        ry="39"
        id="ellipse30326" />
@@ -54357,8 +54153,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30328">
     <ellipse
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-       cy="31142"
+       cx="60047"
+       cy="29752"
        rx="39"
        ry="39"
        id="ellipse30330" />
@@ -54368,8 +54164,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30332">
     <ellipse
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-       cy="30945"
+       cx="57799"
+       cy="32445"
        rx="39"
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        id="ellipse30334" />
@@ -54379,8 +54175,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30336">
     <ellipse
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-       cy="31929"
+       cx="59024"
+       cy="32004"
        rx="39"
        ry="39"
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@@ -54390,8 +54186,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30340">
     <ellipse
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-       cy="32343"
+       cx="59390"
+       cy="30055"
        rx="39"
        ry="39"
        id="ellipse30342" />
@@ -54401,8 +54197,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30344">
     <ellipse
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-       cy="32079"
+       cx="59055"
+       cy="30791"
        rx="39"
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@@ -54412,8 +54208,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33610"
+       cx="47657"
+       cy="31937"
        rx="39"
        ry="39"
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@@ -54423,8 +54219,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33533"
+       cx="47110"
+       cy="31154"
        rx="39"
        ry="39"
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@@ -54434,8 +54230,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33209"
+       cx="47417"
+       cy="31142"
        rx="39"
        ry="39"
        id="ellipse30358" />
@@ -54445,8 +54241,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30360">
     <ellipse
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-       cy="33563"
+       cx="46980"
+       cy="31929"
        rx="39"
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@@ -54456,8 +54252,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33169"
+       cx="50016"
+       cy="32343"
        rx="39"
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@@ -54467,8 +54263,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33209"
+       cx="47923"
+       cy="33199"
        rx="39"
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@@ -54478,8 +54274,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33264"
+       cx="46949"
+       cy="33533"
        rx="39"
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@@ -54489,8 +54285,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="38421"
+       cx="53126"
+       cy="33209"
        rx="39"
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@@ -54500,8 +54296,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="37902"
+       cx="51598"
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        rx="39"
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@@ -54511,8 +54307,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30384">
     <ellipse
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-       cy="36799"
+       cx="50673"
+       cy="38421"
        rx="39"
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@@ -54522,8 +54318,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="37339"
+       cx="50071"
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        rx="39"
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@@ -54533,8 +54329,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="37689"
+       cx="46972"
+       cy="38370"
        rx="39"
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@@ -54544,8 +54340,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="38370"
+       cx="50661"
+       cy="37693"
        rx="39"
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@@ -54555,8 +54351,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="37693"
+       cx="50059"
+       cy="36335"
        rx="39"
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@@ -54566,8 +54362,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="37319"
+       cx="47035"
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        rx="39"
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@@ -54577,8 +54373,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="36161"
+       cx="50039"
+       cy="32693"
        rx="39"
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@@ -54588,8 +54384,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="35878"
+       cx="47921"
+       cy="33874"
        rx="39"
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@@ -54599,8 +54395,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="36197"
+       cx="47846"
+       cy="34996"
        rx="39"
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@@ -54610,8 +54406,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="32693"
+       cx="47018"
+       cy="34390"
        rx="39"
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@@ -54621,8 +54417,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33874"
+       cx="50382"
+       cy="33606"
        rx="39"
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@@ -54632,8 +54428,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="34996"
+       cx="48528"
+       cy="25126"
        rx="39"
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@@ -54643,8 +54439,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33606"
+       cx="46500"
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        rx="39"
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@@ -54654,8 +54450,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="24965"
+       cx="47431"
+       cy="25453"
        rx="39"
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@@ -54665,8 +54461,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="30835"
+       cx="53219"
+       cy="29951"
        rx="39"
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@@ -54676,8 +54472,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31244"
+       cx="47805"
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        rx="39"
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@@ -54687,8 +54483,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="24890"
+       cx="51919"
+       cy="27677"
        rx="39"
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@@ -54698,8 +54494,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31220"
+       cx="55205"
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        rx="39"
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@@ -54709,8 +54505,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="28724"
+       cx="52254"
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        rx="39"
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@@ -54720,8 +54516,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="30925"
+       cx="55661"
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        rx="39"
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@@ -54731,8 +54527,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="29520"
+       cx="49657"
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        rx="39"
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@@ -54742,8 +54538,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="40283"
+       cx="49360"
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        rx="39"
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@@ -54753,8 +54549,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="38299"
+       cx="47677"
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        rx="39"
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@@ -54764,8 +54560,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="39354"
+       cx="53898"
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@@ -54775,8 +54571,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="36331"
+       cx="47362"
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        rx="39"
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@@ -54786,8 +54582,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="39969"
+       cx="55492"
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@@ -54797,8 +54593,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="36728"
+       cx="51260"
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@@ -54808,8 +54604,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="32791"
+       cx="51421"
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@@ -54819,8 +54615,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31579"
+       cx="55094"
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@@ -54830,8 +54626,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31335"
+       cx="51112"
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@@ -54841,8 +54637,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="32630"
+       cx="55118"
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@@ -54852,8 +54648,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="32795"
+       cx="47461"
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@@ -54863,8 +54659,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31925"
+       cx="47510"
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@@ -54874,8 +54670,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31224"
+       cx="52087"
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@@ -54885,8 +54681,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31583"
+       cx="55465"
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@@ -54896,8 +54692,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31075"
+       cx="54301"
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@@ -54907,8 +54703,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="32791"
+       cx="47913"
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@@ -54918,8 +54714,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33587"
+       cx="47244"
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@@ -54929,8 +54725,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="30839"
+       cx="54331"
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@@ -54940,8 +54736,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="32008"
+       cx="50955"
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@@ -54951,8 +54747,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31669"
+       cx="54715"
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@@ -54962,8 +54758,8 @@
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     <ellipse
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-       cy="31339"
+       cx="51585"
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@@ -54973,8 +54769,8 @@
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     <ellipse
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-       cy="33965"
+       cx="55488"
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@@ -54984,8 +54780,8 @@
      transform="translate(0 0) scale(1 1)"
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-       cy="33177"
+       cx="54890"
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@@ -54995,8 +54791,8 @@
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-       cy="31138"
+       cx="51752"
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@@ -55006,8 +54802,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="48894"
-       cy="30941"
+       cx="50945"
+       cy="28268"
        rx="39"
        ry="39"
        id="ellipse30566" />
@@ -55017,8 +54813,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30568">
     <ellipse
-       cx="53902"
-       cy="32803"
+       cx="54724"
+       cy="31270"
        rx="39"
        ry="39"
        id="ellipse30570" />
@@ -55028,8 +54824,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30572">
     <ellipse
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-       cy="31618"
+       cx="50693"
+       cy="31575"
        rx="39"
        ry="39"
        id="ellipse30574" />
@@ -55039,8 +54835,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30576">
     <ellipse
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-       cy="31587"
+       cx="50039"
+       cy="31319"
        rx="39"
        ry="39"
        id="ellipse30578" />
@@ -55050,8 +54846,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30580">
     <ellipse
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-       cy="32394"
+       cx="50051"
+       cy="31898"
        rx="39"
        ry="39"
        id="ellipse30582" />
@@ -55061,8 +54857,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30584">
     <ellipse
-       cx="50197"
-       cy="32520"
+       cx="47425"
+       cy="32134"
        rx="39"
        ry="39"
        id="ellipse30586" />
@@ -55072,8 +54868,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30588">
     <ellipse
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-       cy="32059"
+       cx="50685"
+       cy="31067"
        rx="39"
        ry="39"
        id="ellipse30590" />
@@ -55083,8 +54879,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30592">
     <ellipse
-       cx="49063"
-       cy="32173"
+       cx="50047"
+       cy="30807"
        rx="39"
        ry="39"
        id="ellipse30594" />
@@ -55094,8 +54890,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30596">
     <ellipse
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-       cy="32283"
+       cx="46941"
+       cy="30906"
        rx="39"
        ry="39"
        id="ellipse30598" />
@@ -55105,8 +54901,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30600">
     <ellipse
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-       cy="33602"
+       cx="47646"
+       cy="30945"
        rx="39"
        ry="39"
        id="ellipse30602" />
@@ -55116,8 +54912,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30604">
     <ellipse
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-       cy="33622"
+       cx="47165"
+       cy="32142"
        rx="39"
        ry="39"
        id="ellipse30606" />
@@ -55127,8 +54923,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30608">
     <ellipse
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-       cy="33071"
+       cx="50697"
+       cy="32079"
        rx="39"
        ry="39"
        id="ellipse30610" />
@@ -55138,8 +54934,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30612">
     <ellipse
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-       cy="31232"
+       cx="50055"
+       cy="33610"
        rx="39"
        ry="39"
        id="ellipse30614" />
@@ -55149,8 +54945,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30616">
     <ellipse
-       cx="49228"
-       cy="38087"
+       cx="46959"
+       cy="33169"
        rx="39"
        ry="39"
        id="ellipse30618" />
@@ -55160,8 +54956,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30620">
     <ellipse
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-       cy="35205"
+       cx="52740"
+       cy="33209"
        rx="39"
        ry="39"
        id="ellipse30622" />
@@ -55171,8 +54967,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30624">
     <ellipse
-       cx="51748"
-       cy="35102"
+       cx="51610"
+       cy="33264"
        rx="39"
        ry="39"
        id="ellipse30626" />
@@ -55182,8 +54978,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30628">
     <ellipse
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-       cy="37823"
+       cx="47004"
+       cy="36433"
        rx="39"
        ry="39"
        id="ellipse30630" />
@@ -55193,8 +54989,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30632">
     <ellipse
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-       cy="36197"
+       cx="47000"
+       cy="36799"
        rx="39"
        ry="39"
        id="ellipse30634" />
@@ -55204,8 +55000,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30636">
     <ellipse
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-       cy="35563"
+       cx="47035"
+       cy="37339"
        rx="39"
        ry="39"
        id="ellipse30638" />
@@ -55215,8 +55011,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30640">
     <ellipse
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-       cy="35776"
+       cx="47028"
+       cy="37689"
        rx="39"
        ry="39"
        id="ellipse30642" />
@@ -55226,8 +55022,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30644">
     <ellipse
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-       cy="36583"
+       cx="47020"
+       cy="37925"
        rx="39"
        ry="39"
        id="ellipse30646" />
@@ -55237,8 +55033,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30648">
     <ellipse
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-       cy="37307"
+       cx="50150"
+       cy="37319"
        rx="39"
        ry="39"
        id="ellipse30650" />
@@ -55248,8 +55044,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30652">
     <ellipse
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-       cy="36354"
+       cx="50126"
+       cy="36736"
        rx="39"
        ry="39"
        id="ellipse30654" />
@@ -55259,8 +55055,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30656">
     <ellipse
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-       cy="37571"
+       cx="50685"
+       cy="36161"
        rx="39"
        ry="39"
        id="ellipse30658" />
@@ -55270,8 +55066,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30660">
     <ellipse
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-       cy="36720"
+       cx="50071"
+       cy="35945"
        rx="39"
        ry="39"
        id="ellipse30662" />
@@ -55281,8 +55077,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30664">
     <ellipse
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-       cy="37169"
+       cx="47031"
+       cy="36197"
        rx="39"
        ry="39"
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@@ -55292,8 +55088,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30668">
     <ellipse
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-       cy="37819"
+       cx="50520"
+       cy="33957"
        rx="39"
        ry="39"
        id="ellipse30670" />
@@ -55303,8 +55099,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30672">
     <ellipse
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-       cy="38299"
+       cx="50681"
+       cy="34894"
        rx="39"
        ry="39"
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@@ -55314,8 +55110,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30676">
     <ellipse
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-       cy="37610"
+       cx="53866"
+       cy="24965"
        rx="39"
        ry="39"
        id="ellipse30678" />
@@ -55325,8 +55121,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30680">
     <ellipse
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-       cy="37213"
+       cx="56555"
+       cy="30835"
        rx="39"
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@@ -55336,8 +55132,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30684">
     <ellipse
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-       cy="34846"
+       cx="57075"
+       cy="31244"
        rx="39"
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@@ -55347,8 +55143,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30688">
     <ellipse
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-       cy="34917"
+       cx="53520"
+       cy="24890"
        rx="39"
        ry="39"
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@@ -55358,8 +55154,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30692">
     <ellipse
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-       cy="36760"
+       cx="54079"
+       cy="25799"
        rx="39"
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@@ -55369,8 +55165,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="34457"
+       cx="56713"
+       cy="30417"
        rx="39"
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@@ -55380,8 +55176,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33965"
+       cx="55933"
+       cy="31220"
        rx="39"
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@@ -55391,8 +55187,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30704">
     <ellipse
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-       cy="34823"
+       cx="54409"
+       cy="28724"
        rx="39"
        ry="39"
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@@ -55402,8 +55198,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30708">
     <ellipse
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-       cy="33957"
+       cx="59598"
+       cy="40283"
        rx="39"
        ry="39"
        id="ellipse30710" />
@@ -55413,8 +55209,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30712">
     <ellipse
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-       cy="33961"
+       cx="59827"
+       cy="38299"
        rx="39"
        ry="39"
        id="ellipse30714" />
@@ -55424,8 +55220,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30716">
     <ellipse
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-       cy="35319"
+       cx="57189"
+       cy="39354"
        rx="39"
        ry="39"
        id="ellipse30718" />
@@ -55435,8 +55231,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30720">
     <ellipse
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-       cy="35134"
+       cx="53894"
+       cy="36331"
        rx="39"
        ry="39"
        id="ellipse30722" />
@@ -55446,8 +55242,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30724">
     <ellipse
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-       cy="34457"
+       cx="59268"
+       cy="39969"
        rx="39"
        ry="39"
        id="ellipse30726" />
@@ -55457,8 +55253,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="35165"
+       cx="57043"
+       cy="36728"
        rx="39"
        ry="39"
        id="ellipse30730" />
@@ -55468,8 +55264,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="35618"
+       cx="52319"
+       cy="32791"
        rx="39"
        ry="39"
        id="ellipse30734" />
@@ -55479,8 +55275,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="35886"
+       cx="49075"
+       cy="31579"
        rx="39"
        ry="39"
        id="ellipse30738" />
@@ -55490,8 +55286,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="35382"
+       cx="49102"
+       cy="31335"
        rx="39"
        ry="39"
        id="ellipse30742" />
@@ -55501,8 +55297,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30744">
     <ellipse
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-       cy="34020"
+       cx="51858"
+       cy="32630"
        rx="39"
        ry="39"
        id="ellipse30746" />
@@ -55512,8 +55308,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30748">
     <ellipse
-       cx="53122"
-       cy="33992"
+       cx="53130"
+       cy="32795"
        rx="39"
        ry="39"
        id="ellipse30750" />
@@ -55523,8 +55319,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30752">
     <ellipse
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-       cy="34276"
+       cx="49075"
+       cy="31925"
        rx="39"
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@@ -55534,8 +55330,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30756">
     <ellipse
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-       cy="34350"
+       cx="52307"
+       cy="31224"
        rx="39"
        ry="39"
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@@ -55545,8 +55341,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33591"
+       cx="51343"
+       cy="31583"
        rx="39"
        ry="39"
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@@ -55556,8 +55352,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="33173"
+       cx="49106"
+       cy="31075"
        rx="39"
        ry="39"
        id="ellipse30766" />
@@ -55567,8 +55363,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="32638"
+       cx="53496"
+       cy="32791"
        rx="39"
        ry="39"
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@@ -55578,8 +55374,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="34787"
+       cx="53882"
+       cy="33587"
        rx="39"
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@@ -55589,8 +55385,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="34307"
+       cx="49126"
+       cy="30839"
        rx="39"
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@@ -55600,8 +55396,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="51559"
-       cy="36350"
+       cx="53114"
+       cy="32008"
        rx="39"
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@@ -55611,8 +55407,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="32031"
+       cx="48354"
+       cy="31669"
        rx="39"
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        id="ellipse30786" />
@@ -55622,8 +55418,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="29335"
+       cx="48642"
+       cy="31339"
        rx="39"
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@@ -55633,8 +55429,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="16764"
+       cx="52717"
+       cy="33965"
        rx="39"
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@@ -55644,8 +55440,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="29197"
+       cx="53504"
+       cy="33177"
        rx="39"
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@@ -55655,8 +55451,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="16799"
+       cx="48752"
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        rx="39"
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@@ -55666,8 +55462,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="29311"
+       cx="48894"
+       cy="30941"
        rx="39"
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@@ -55677,8 +55473,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="63358"
-       cy="16835"
+       cx="53902"
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        rx="39"
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@@ -55688,8 +55484,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="16748"
+       cx="52720"
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        rx="39"
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@@ -55699,8 +55495,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="28583"
+       cx="52323"
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        rx="39"
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@@ -55710,8 +55506,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="58598"
-       cy="28906"
+       cx="49059"
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        rx="39"
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@@ -55721,8 +55517,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="61083"
-       cy="16728"
+       cx="50197"
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        rx="39"
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@@ -55732,7 +55528,7 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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+       cx="51331"
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      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="32083"
+       cx="49063"
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@@ -55754,8 +55550,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="31228"
+       cx="51272"
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@@ -55765,8 +55561,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="29370"
+       cx="53102"
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@@ -55776,8 +55572,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="25799"
+       cx="49035"
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@@ -55787,8 +55583,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="30417"
+       cx="48469"
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@@ -55798,8 +55594,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="16732"
+       cx="52689"
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@@ -55809,8 +55605,8 @@
      transform="translate(0 0) scale(1 1)"
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-       cy="30874"
+       cx="49228"
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@@ -55820,8 +55616,8 @@
      transform="translate(0 0) scale(1 1)"
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-       cy="31161"
+       cx="53114"
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@@ -55831,8 +55627,8 @@
      transform="translate(0 0) scale(1 1)"
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-       cy="31618"
+       cx="51748"
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@@ -55842,8 +55638,8 @@
      transform="translate(0 0) scale(1 1)"
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-       cy="27280"
+       cx="48890"
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@@ -55853,8 +55649,8 @@
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     <ellipse
-       cx="56386"
-       cy="27256"
+       cx="48161"
+       cy="36197"
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@@ -55864,8 +55660,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="51976"
-       cy="30087"
+       cx="51992"
+       cy="35563"
        rx="39"
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@@ -55875,8 +55671,8 @@
      transform="translate(0 0) scale(1 1)"
      id="g30880">
     <ellipse
-       cx="54299"
-       cy="31626"
+       cx="51807"
+       cy="35776"
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@@ -55886,8 +55682,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="59016"
-       cy="31346"
+       cx="48138"
+       cy="36583"
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@@ -55897,8 +55693,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="58543"
-       cy="30528"
+       cx="48031"
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@@ -55908,8 +55704,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="48421"
-       cy="39165"
+       cx="52705"
+       cy="36354"
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@@ -55919,8 +55715,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="47570"
-       cy="30025"
+       cx="48051"
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@@ -55930,8 +55726,8 @@
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     <ellipse
-       cx="50575"
-       cy="37465"
+       cx="51799"
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@@ -55941,8 +55737,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="50559"
-       cy="35913"
+       cx="51854"
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@@ -55952,8 +55748,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="53512"
-       cy="34350"
+       cx="48075"
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@@ -55963,8 +55759,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="47311"
-       cy="30531"
+       cx="47972"
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@@ -55974,8 +55770,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="46870"
-       cy="35157"
+       cx="51508"
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@@ -55985,8 +55781,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="50472"
-       cy="33126"
+       cx="48752"
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@@ -55996,8 +55792,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="52701"
-       cy="35150"
+       cx="51748"
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@@ -56007,8 +55803,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="52390"
-       cy="33189"
+       cx="51398"
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@@ -56018,8 +55814,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="52350"
-       cy="32024"
+       cx="48850"
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@@ -56029,8 +55825,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="47701"
-       cy="24394"
+       cx="49878"
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@@ -56040,8 +55836,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="46346"
-       cy="24051"
+       cx="51709"
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@@ -56051,8 +55847,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="47303"
-       cy="23634"
+       cx="49772"
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@@ -56062,8 +55858,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="60598"
-       cy="30055"
+       cx="51402"
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@@ -56073,8 +55869,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="57469"
-       cy="31697"
+       cx="52343"
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@@ -56084,8 +55880,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="30811"
+       cx="49303"
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@@ -56095,8 +55891,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="26047"
+       cx="49492"
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@@ -56106,8 +55902,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="59965"
-       cy="24173"
+       cx="51488"
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@@ -56117,8 +55913,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="53445"
-       cy="25846"
+       cx="51976"
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@@ -56128,8 +55924,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="55098"
-       cy="30443"
+       cx="48055"
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@@ -56139,8 +55935,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="53543"
-       cy="30650"
+       cx="48169"
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        rx="39"
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@@ -56150,8 +55946,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="48494"
-       cy="27224"
+       cx="51508"
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        rx="39"
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@@ -56161,8 +55957,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="46732"
-       cy="26565"
+       cx="49035"
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        rx="39"
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@@ -56172,8 +55968,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="46673"
-       cy="25591"
+       cx="53122"
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        rx="39"
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@@ -56183,8 +55979,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
-       cx="50862"
-       cy="18560"
+       cx="49039"
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        rx="39"
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@@ -56194,8 +55990,8 @@
      transform="translate(0 0) scale(1 1)"
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     <ellipse
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-       cy="27884"
+       cx="52724"
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@@ -56205,8 +56001,8 @@
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     <ellipse
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-       cy="28159"
+       cx="53512"
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@@ -56216,10 +56012,736 @@
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     <ellipse
-       cx="46717"
-       cy="25161"
+       cx="51846"
+       cy="33173"
        rx="39"
        ry="39"
        id="ellipse31006" />
   </g>
+  <g
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+     id="g31008">
+    <ellipse
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+       cy="32638"
+       rx="39"
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+       cy="34787"
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+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31124">
+    <ellipse
+       cx="59760"
+       cy="30780"
+       rx="39"
+       ry="39"
+       id="ellipse31126" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31128">
+    <ellipse
+       cx="60256"
+       cy="30488"
+       rx="39"
+       ry="39"
+       id="ellipse31130" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31132">
+    <ellipse
+       cx="58134"
+       cy="27280"
+       rx="39"
+       ry="39"
+       id="ellipse31134" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31136">
+    <ellipse
+       cx="56386"
+       cy="27256"
+       rx="39"
+       ry="39"
+       id="ellipse31138" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31140">
+    <ellipse
+       cx="51976"
+       cy="30087"
+       rx="39"
+       ry="39"
+       id="ellipse31142" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31144">
+    <ellipse
+       cx="54299"
+       cy="31626"
+       rx="39"
+       ry="39"
+       id="ellipse31146" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31148">
+    <ellipse
+       cx="59016"
+       cy="31346"
+       rx="39"
+       ry="39"
+       id="ellipse31150" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31152">
+    <ellipse
+       cx="58669"
+       cy="30402"
+       rx="39"
+       ry="39"
+       id="ellipse31154" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31156">
+    <ellipse
+       cx="48421"
+       cy="39165"
+       rx="39"
+       ry="39"
+       id="ellipse31158" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31160">
+    <ellipse
+       cx="47570"
+       cy="30025"
+       rx="39"
+       ry="39"
+       id="ellipse31162" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31164">
+    <ellipse
+       cx="50575"
+       cy="37465"
+       rx="39"
+       ry="39"
+       id="ellipse31166" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31168">
+    <ellipse
+       cx="50559"
+       cy="35913"
+       rx="39"
+       ry="39"
+       id="ellipse31170" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31172">
+    <ellipse
+       cx="53512"
+       cy="34350"
+       rx="39"
+       ry="39"
+       id="ellipse31174" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31176">
+    <ellipse
+       cx="47311"
+       cy="30531"
+       rx="39"
+       ry="39"
+       id="ellipse31178" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31180">
+    <ellipse
+       cx="46870"
+       cy="35157"
+       rx="39"
+       ry="39"
+       id="ellipse31182" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31184">
+    <ellipse
+       cx="50472"
+       cy="33126"
+       rx="39"
+       ry="39"
+       id="ellipse31186" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31188">
+    <ellipse
+       cx="52701"
+       cy="35150"
+       rx="39"
+       ry="39"
+       id="ellipse31190" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31192">
+    <ellipse
+       cx="52390"
+       cy="33189"
+       rx="39"
+       ry="39"
+       id="ellipse31194" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31196">
+    <ellipse
+       cx="52350"
+       cy="32024"
+       rx="39"
+       ry="39"
+       id="ellipse31198" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31200">
+    <ellipse
+       cx="47701"
+       cy="24394"
+       rx="39"
+       ry="39"
+       id="ellipse31202" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31204">
+    <ellipse
+       cx="46346"
+       cy="24051"
+       rx="39"
+       ry="39"
+       id="ellipse31206" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31208">
+    <ellipse
+       cx="47303"
+       cy="23634"
+       rx="39"
+       ry="39"
+       id="ellipse31210" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31212">
+    <ellipse
+       cx="60598"
+       cy="30055"
+       rx="39"
+       ry="39"
+       id="ellipse31214" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31216">
+    <ellipse
+       cx="57469"
+       cy="31697"
+       rx="39"
+       ry="39"
+       id="ellipse31218" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31220">
+    <ellipse
+       cx="56866"
+       cy="30811"
+       rx="39"
+       ry="39"
+       id="ellipse31222" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31224">
+    <ellipse
+       cx="60197"
+       cy="26047"
+       rx="39"
+       ry="39"
+       id="ellipse31226" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31228">
+    <ellipse
+       cx="59965"
+       cy="24173"
+       rx="39"
+       ry="39"
+       id="ellipse31230" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31232">
+    <ellipse
+       cx="53445"
+       cy="25846"
+       rx="39"
+       ry="39"
+       id="ellipse31234" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31236">
+    <ellipse
+       cx="55098"
+       cy="30443"
+       rx="39"
+       ry="39"
+       id="ellipse31238" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31240">
+    <ellipse
+       cx="53543"
+       cy="30650"
+       rx="39"
+       ry="39"
+       id="ellipse31242" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31244">
+    <ellipse
+       cx="48494"
+       cy="27224"
+       rx="39"
+       ry="39"
+       id="ellipse31246" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31248">
+    <ellipse
+       cx="46732"
+       cy="26565"
+       rx="39"
+       ry="39"
+       id="ellipse31250" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31252">
+    <ellipse
+       cx="46673"
+       cy="25591"
+       rx="39"
+       ry="39"
+       id="ellipse31254" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31256">
+    <ellipse
+       cx="50862"
+       cy="18560"
+       rx="39"
+       ry="39"
+       id="ellipse31258" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31260">
+    <ellipse
+       cx="49911"
+       cy="27884"
+       rx="39"
+       ry="39"
+       id="ellipse31262" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31264">
+    <ellipse
+       cx="48967"
+       cy="28159"
+       rx="39"
+       ry="39"
+       id="ellipse31266" />
+  </g>
+  <g
+     style="fill:#FFFFFF; fill-opacity:1.0;    stroke:#FFFFFF; stroke-linecap:round; stroke-linejoin:round; stroke-opacity:1.0; stroke-opacity:1.0; stroke-width:0"
+     transform="translate(0 0) scale(1 1)"
+     id="g31268">
+    <ellipse
+       cx="46717"
+       cy="25161"
+       rx="39"
+       ry="39"
+       id="ellipse31270" />
+  </g>
 </svg>
diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib
index 4be8c10..03970cb 100644
--- a/kicad/xue-rnc/xue-rnc-cache.lib
+++ b/kicad/xue-rnc/xue-rnc-cache.lib
@@ -1,4 +1,4 @@
-EESchema-LIBRARY Version 2.3  Date: Mon 23 Aug 2010 10:36:19 PM COT
+EESchema-LIBRARY Version 2.3  Date: Tue 24 Aug 2010 06:53:07 AM COT
 #
 # +1.2V
 #
diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd
index 1d767dc..8b00e4f 100644
--- a/kicad/xue-rnc/xue-rnc.brd
+++ b/kicad/xue-rnc/xue-rnc.brd
@@ -1,4 +1,4 @@
-PCBNEW-BOARD Version 1 date Mon 23 Aug 2010 10:56:46 PM COT
+PCBNEW-BOARD Version 1 date Tue 24 Aug 2010 06:56:28 AM COT
 
 # Created by Pcbnew(2010-07-15 BZR 2414)-unstable
 
@@ -7,10 +7,10 @@ LayerCount 6
 Ly 1FFF801F
 EnabledLayers 13FF801F
 Links 709
-NoConn 479
+NoConn 466
 Di 45200 12863 75973 50668
 Ndraw 7
-Ntrack 2168
+Ntrack 2257
 Nzone 0
 BoardThickness 630
 Nmodule 173
@@ -106,23 +106,23 @@ Na 9 "/DBG_PRG/FPGA_TMS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 10 "/DDR_Banks/M0_A0"
+Na 10 "/DDR_Banks/M0_A12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 11 "/DDR_Banks/M0_A11"
+Na 11 "/DDR_Banks/M0_A5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 12 "/DDR_Banks/M0_A3"
+Na 12 "/DDR_Banks/M0_A6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 13 "/DDR_Banks/M0_A4"
+Na 13 "/DDR_Banks/M0_A8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 14 "/DDR_Banks/M0_A9"
+Na 14 "/DDR_Banks/M0_BA0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -130,415 +130,415 @@ Na 15 "/DDR_Banks/M0_CKE"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 16 "/DDR_Banks/M0_DQ10"
+Na 16 "/DDR_Banks/M0_CLK"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 17 "/DDR_Banks/M0_DQ14"
+Na 17 "/DDR_Banks/M0_DQ0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 18 "/DDR_Banks/M0_DQ4"
+Na 18 "/DDR_Banks/M0_DQ1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 19 "/DDR_Banks/M0_DQ5"
+Na 19 "/DDR_Banks/M0_DQ15"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 20 "/DDR_Banks/M0_DQ7"
+Na 20 "/DDR_Banks/M0_DQ2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 21 "/DDR_Banks/M0_LDM"
+Na 21 "/DDR_Banks/M0_DQ5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 22 "/DDR_Banks/M0_LDQS"
+Na 22 "/DDR_Banks/M0_DQ8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 23 "/DDR_Banks/M0_VREF"
+Na 23 "/DDR_Banks/M0_RAS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 24 "/DDR_Banks/M1_A1"
+Na 24 "/DDR_Banks/M0_UDM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 25 "/DDR_Banks/M1_A11"
+Na 25 "/DDR_Banks/M0_UDQS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 26 "/DDR_Banks/M1_A6"
+Na 26 "/DDR_Banks/M0_VREF"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 27 "/DDR_Banks/M1_BA0"
+Na 27 "/DDR_Banks/M0_WE#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 28 "/DDR_Banks/M1_BA1"
+Na 28 "/DDR_Banks/M1_A0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 29 "/DDR_Banks/M1_CLK#"
+Na 29 "/DDR_Banks/M1_A12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 30 "/DDR_Banks/M1_CS#"
+Na 30 "/DDR_Banks/M1_A5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 31 "/DDR_Banks/M1_DQ0"
+Na 31 "/DDR_Banks/M1_A8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 32 "/DDR_Banks/M1_DQ4"
+Na 32 "/DDR_Banks/M1_A9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 33 "/DDR_Banks/M1_DQ9"
+Na 33 "/DDR_Banks/M1_BA0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 34 "/DDR_Banks/M1_VREF"
+Na 34 "/DDR_Banks/M1_CKE"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 35 "/DDR_Banks/M1_WE#"
+Na 35 "/DDR_Banks/M1_CLK"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 36 "/Ethernet_Phy/ETH_A1.8V"
+Na 36 "/DDR_Banks/M1_DQ10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 37 "/Ethernet_Phy/ETH_A3.3V"
+Na 37 "/DDR_Banks/M1_DQ12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 38 "/Ethernet_Phy/ETH_COL"
+Na 38 "/DDR_Banks/M1_DQ3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 39 "/Ethernet_Phy/ETH_LED0"
+Na 39 "/DDR_Banks/M1_DQ5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 40 "/Ethernet_Phy/ETH_LED1"
+Na 40 "/DDR_Banks/M1_DQ6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 41 "/Ethernet_Phy/ETH_MDIO"
+Na 41 "/DDR_Banks/M1_LDM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 42 "/Ethernet_Phy/ETH_PLL1.8V"
+Na 42 "/DDR_Banks/M1_UDQS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 43 "/Ethernet_Phy/ETH_RXD0"
+Na 43 "/DDR_Banks/M1_VREF"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 44 "/Ethernet_Phy/ETH_RXD2"
+Na 44 "/Ethernet_Phy/ETH_A1.8V"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 45 "/Ethernet_Phy/ETH_RXER"
+Na 45 "/Ethernet_Phy/ETH_A3.3V"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 46 "/Ethernet_Phy/ETH_TXD1"
+Na 46 "/Ethernet_Phy/ETH_CLK"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 47 "/Ethernet_Phy/ETH_TXD3"
+Na 47 "/Ethernet_Phy/ETH_COL"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 48 "/Ethernet_Phy/MAG_RX+"
+Na 48 "/Ethernet_Phy/ETH_INT"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 49 "/Ethernet_Phy/MAG_RX-"
+Na 49 "/Ethernet_Phy/ETH_LED0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 50 "/Ethernet_Phy/MAG_SHIELD"
+Na 50 "/Ethernet_Phy/ETH_LED1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 51 "/Ethernet_Phy/MAG_TX+"
+Na 51 "/Ethernet_Phy/ETH_MDIO"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 52 "/Ethernet_Phy/MAG_TX-"
+Na 52 "/Ethernet_Phy/ETH_PLL1.8V"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 53 "/FPGA_Spartan6/ETH_CLK"
+Na 53 "/Ethernet_Phy/ETH_RXD1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 54 "/FPGA_Spartan6/ETH_CRS"
+Na 54 "/Ethernet_Phy/ETH_RXD3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 55 "/FPGA_Spartan6/ETH_INT"
+Na 55 "/Ethernet_Phy/ETH_TXD0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 56 "/FPGA_Spartan6/ETH_MDC"
+Na 56 "/Ethernet_Phy/ETH_TXD1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 57 "/FPGA_Spartan6/ETH_RESET_N"
+Na 57 "/Ethernet_Phy/ETH_TXEN"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 58 "/FPGA_Spartan6/ETH_RXC"
+Na 58 "/Ethernet_Phy/MAG_RX+"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 59 "/FPGA_Spartan6/ETH_RXD1"
+Na 59 "/Ethernet_Phy/MAG_RX-"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 60 "/FPGA_Spartan6/ETH_RXD3"
+Na 60 "/Ethernet_Phy/MAG_SHIELD"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 61 "/FPGA_Spartan6/ETH_RXDV"
+Na 61 "/Ethernet_Phy/MAG_TX+"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 62 "/FPGA_Spartan6/ETH_TXC"
+Na 62 "/Ethernet_Phy/MAG_TX-"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 63 "/FPGA_Spartan6/ETH_TXD0"
+Na 63 "/FPGA_Spartan6/ETH_CRS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 64 "/FPGA_Spartan6/ETH_TXD2"
+Na 64 "/FPGA_Spartan6/ETH_MDC"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 65 "/FPGA_Spartan6/ETH_TXEN"
+Na 65 "/FPGA_Spartan6/ETH_RESET_N"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 66 "/FPGA_Spartan6/ETH_TXER"
+Na 66 "/FPGA_Spartan6/ETH_RXC"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 67 "/FPGA_Spartan6/M0_A1"
+Na 67 "/FPGA_Spartan6/ETH_RXD0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 68 "/FPGA_Spartan6/M0_A10"
+Na 68 "/FPGA_Spartan6/ETH_RXD2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 69 "/FPGA_Spartan6/M0_A12"
+Na 69 "/FPGA_Spartan6/ETH_RXDV"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 70 "/FPGA_Spartan6/M0_A2"
+Na 70 "/FPGA_Spartan6/ETH_RXER"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 71 "/FPGA_Spartan6/M0_A5"
+Na 71 "/FPGA_Spartan6/ETH_TXC"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 72 "/FPGA_Spartan6/M0_A6"
+Na 72 "/FPGA_Spartan6/ETH_TXD2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 73 "/FPGA_Spartan6/M0_A7"
+Na 73 "/FPGA_Spartan6/ETH_TXD3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 74 "/FPGA_Spartan6/M0_A8"
+Na 74 "/FPGA_Spartan6/ETH_TXER"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 75 "/FPGA_Spartan6/M0_BA0"
+Na 75 "/FPGA_Spartan6/M0_A0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 76 "/FPGA_Spartan6/M0_BA1"
+Na 76 "/FPGA_Spartan6/M0_A1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 77 "/FPGA_Spartan6/M0_CAS#"
+Na 77 "/FPGA_Spartan6/M0_A10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 78 "/FPGA_Spartan6/M0_CLK"
+Na 78 "/FPGA_Spartan6/M0_A11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 79 "/FPGA_Spartan6/M0_CLK#"
+Na 79 "/FPGA_Spartan6/M0_A2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 80 "/FPGA_Spartan6/M0_DQ0"
+Na 80 "/FPGA_Spartan6/M0_A3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 81 "/FPGA_Spartan6/M0_DQ1"
+Na 81 "/FPGA_Spartan6/M0_A4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 82 "/FPGA_Spartan6/M0_DQ11"
+Na 82 "/FPGA_Spartan6/M0_A7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 83 "/FPGA_Spartan6/M0_DQ12"
+Na 83 "/FPGA_Spartan6/M0_A9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 84 "/FPGA_Spartan6/M0_DQ13"
+Na 84 "/FPGA_Spartan6/M0_BA1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 85 "/FPGA_Spartan6/M0_DQ15"
+Na 85 "/FPGA_Spartan6/M0_CAS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 86 "/FPGA_Spartan6/M0_DQ2"
+Na 86 "/FPGA_Spartan6/M0_CLK#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 87 "/FPGA_Spartan6/M0_DQ3"
+Na 87 "/FPGA_Spartan6/M0_DQ10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 88 "/FPGA_Spartan6/M0_DQ6"
+Na 88 "/FPGA_Spartan6/M0_DQ11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 89 "/FPGA_Spartan6/M0_DQ8"
+Na 89 "/FPGA_Spartan6/M0_DQ12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 90 "/FPGA_Spartan6/M0_DQ9"
+Na 90 "/FPGA_Spartan6/M0_DQ13"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 91 "/FPGA_Spartan6/M0_RAS#"
+Na 91 "/FPGA_Spartan6/M0_DQ14"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 92 "/FPGA_Spartan6/M0_UDM"
+Na 92 "/FPGA_Spartan6/M0_DQ3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 93 "/FPGA_Spartan6/M0_UDQS"
+Na 93 "/FPGA_Spartan6/M0_DQ4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 94 "/FPGA_Spartan6/M0_WE#"
+Na 94 "/FPGA_Spartan6/M0_DQ6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 95 "/FPGA_Spartan6/M1_A0"
+Na 95 "/FPGA_Spartan6/M0_DQ7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 96 "/FPGA_Spartan6/M1_A10"
+Na 96 "/FPGA_Spartan6/M0_DQ9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 97 "/FPGA_Spartan6/M1_A12"
+Na 97 "/FPGA_Spartan6/M0_LDM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 98 "/FPGA_Spartan6/M1_A2"
+Na 98 "/FPGA_Spartan6/M0_LDQS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 99 "/FPGA_Spartan6/M1_A3"
+Na 99 "/FPGA_Spartan6/M1_A1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 100 "/FPGA_Spartan6/M1_A4"
+Na 100 "/FPGA_Spartan6/M1_A10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 101 "/FPGA_Spartan6/M1_A5"
+Na 101 "/FPGA_Spartan6/M1_A11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 102 "/FPGA_Spartan6/M1_A7"
+Na 102 "/FPGA_Spartan6/M1_A2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 103 "/FPGA_Spartan6/M1_A8"
+Na 103 "/FPGA_Spartan6/M1_A3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 104 "/FPGA_Spartan6/M1_A9"
+Na 104 "/FPGA_Spartan6/M1_A4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 105 "/FPGA_Spartan6/M1_CAS#"
+Na 105 "/FPGA_Spartan6/M1_A6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 106 "/FPGA_Spartan6/M1_CKE"
+Na 106 "/FPGA_Spartan6/M1_A7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 107 "/FPGA_Spartan6/M1_CLK"
+Na 107 "/FPGA_Spartan6/M1_BA1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 108 "/FPGA_Spartan6/M1_DQ1"
+Na 108 "/FPGA_Spartan6/M1_CAS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 109 "/FPGA_Spartan6/M1_DQ10"
+Na 109 "/FPGA_Spartan6/M1_CLK#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 110 "/FPGA_Spartan6/M1_DQ11"
+Na 110 "/FPGA_Spartan6/M1_CS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 111 "/FPGA_Spartan6/M1_DQ12"
+Na 111 "/FPGA_Spartan6/M1_DQ0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 112 "/FPGA_Spartan6/M1_DQ13"
+Na 112 "/FPGA_Spartan6/M1_DQ1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 113 "/FPGA_Spartan6/M1_DQ14"
+Na 113 "/FPGA_Spartan6/M1_DQ11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 114 "/FPGA_Spartan6/M1_DQ15"
+Na 114 "/FPGA_Spartan6/M1_DQ13"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 115 "/FPGA_Spartan6/M1_DQ2"
+Na 115 "/FPGA_Spartan6/M1_DQ14"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 116 "/FPGA_Spartan6/M1_DQ3"
+Na 116 "/FPGA_Spartan6/M1_DQ15"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 117 "/FPGA_Spartan6/M1_DQ5"
+Na 117 "/FPGA_Spartan6/M1_DQ2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 118 "/FPGA_Spartan6/M1_DQ6"
+Na 118 "/FPGA_Spartan6/M1_DQ4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -550,7 +550,7 @@ Na 120 "/FPGA_Spartan6/M1_DQ8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 121 "/FPGA_Spartan6/M1_LDM"
+Na 121 "/FPGA_Spartan6/M1_DQ9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -566,7 +566,7 @@ Na 124 "/FPGA_Spartan6/M1_UDM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 125 "/FPGA_Spartan6/M1_UDQS"
+Na 125 "/FPGA_Spartan6/M1_WE#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -582,11 +582,11 @@ Na 128 "/FPGA_Spartan6/NF_D1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 129 "/FPGA_Spartan6/NF_D4"
+Na 129 "/FPGA_Spartan6/NF_D3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 130 "/FPGA_Spartan6/NF_D5"
+Na 130 "/FPGA_Spartan6/NF_D4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -598,399 +598,399 @@ Na 132 "/FPGA_Spartan6/NF_D7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 133 "/FPGA_Spartan6/NF_RE_N"
+Na 133 "/FPGA_Spartan6/PROG_CCLK"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 134 "/FPGA_Spartan6/PROG_CCLK"
+Na 134 "/FPGA_Spartan6/PROG_CSO"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 135 "/FPGA_Spartan6/PROG_CSO"
+Na 135 "/FPGA_Spartan6/PROG_MISO0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 136 "/FPGA_Spartan6/PROG_MISO0"
+Na 136 "/FPGA_Spartan6/PROG_MISO1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 137 "/FPGA_Spartan6/PROG_MISO1"
+Na 137 "/FPGA_Spartan6/PROG_MISO2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 138 "/FPGA_Spartan6/PROG_MISO2"
+Na 138 "/FPGA_Spartan6/PROG_MISO3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 139 "/FPGA_Spartan6/PROG_MISO3"
+Na 139 "/FPGA_Spartan6/R_M0_A0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 140 "/FPGA_Spartan6/R_M0_A0"
+Na 140 "/FPGA_Spartan6/R_M0_A1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 141 "/FPGA_Spartan6/R_M0_A1"
+Na 141 "/FPGA_Spartan6/R_M0_A10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 142 "/FPGA_Spartan6/R_M0_A10"
+Na 142 "/FPGA_Spartan6/R_M0_A11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 143 "/FPGA_Spartan6/R_M0_A11"
+Na 143 "/FPGA_Spartan6/R_M0_A12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 144 "/FPGA_Spartan6/R_M0_A12"
+Na 144 "/FPGA_Spartan6/R_M0_A2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 145 "/FPGA_Spartan6/R_M0_A2"
+Na 145 "/FPGA_Spartan6/R_M0_A3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 146 "/FPGA_Spartan6/R_M0_A3"
+Na 146 "/FPGA_Spartan6/R_M0_A4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 147 "/FPGA_Spartan6/R_M0_A4"
+Na 147 "/FPGA_Spartan6/R_M0_A5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 148 "/FPGA_Spartan6/R_M0_A5"
+Na 148 "/FPGA_Spartan6/R_M0_A6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 149 "/FPGA_Spartan6/R_M0_A6"
+Na 149 "/FPGA_Spartan6/R_M0_A7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 150 "/FPGA_Spartan6/R_M0_A7"
+Na 150 "/FPGA_Spartan6/R_M0_A8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 151 "/FPGA_Spartan6/R_M0_A8"
+Na 151 "/FPGA_Spartan6/R_M0_A9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 152 "/FPGA_Spartan6/R_M0_A9"
+Na 152 "/FPGA_Spartan6/R_M0_BA0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 153 "/FPGA_Spartan6/R_M0_BA0"
+Na 153 "/FPGA_Spartan6/R_M0_BA1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 154 "/FPGA_Spartan6/R_M0_BA1"
+Na 154 "/FPGA_Spartan6/R_M0_CAS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 155 "/FPGA_Spartan6/R_M0_CAS#"
+Na 155 "/FPGA_Spartan6/R_M0_CKE"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 156 "/FPGA_Spartan6/R_M0_CKE"
+Na 156 "/FPGA_Spartan6/R_M0_DQ0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 157 "/FPGA_Spartan6/R_M0_DQ0"
+Na 157 "/FPGA_Spartan6/R_M0_DQ1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 158 "/FPGA_Spartan6/R_M0_DQ1"
+Na 158 "/FPGA_Spartan6/R_M0_DQ10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 159 "/FPGA_Spartan6/R_M0_DQ10"
+Na 159 "/FPGA_Spartan6/R_M0_DQ11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 160 "/FPGA_Spartan6/R_M0_DQ11"
+Na 160 "/FPGA_Spartan6/R_M0_DQ12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 161 "/FPGA_Spartan6/R_M0_DQ12"
+Na 161 "/FPGA_Spartan6/R_M0_DQ13"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 162 "/FPGA_Spartan6/R_M0_DQ13"
+Na 162 "/FPGA_Spartan6/R_M0_DQ14"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 163 "/FPGA_Spartan6/R_M0_DQ14"
+Na 163 "/FPGA_Spartan6/R_M0_DQ15"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 164 "/FPGA_Spartan6/R_M0_DQ15"
+Na 164 "/FPGA_Spartan6/R_M0_DQ2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 165 "/FPGA_Spartan6/R_M0_DQ2"
+Na 165 "/FPGA_Spartan6/R_M0_DQ3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 166 "/FPGA_Spartan6/R_M0_DQ3"
+Na 166 "/FPGA_Spartan6/R_M0_DQ4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 167 "/FPGA_Spartan6/R_M0_DQ4"
+Na 167 "/FPGA_Spartan6/R_M0_DQ5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 168 "/FPGA_Spartan6/R_M0_DQ5"
+Na 168 "/FPGA_Spartan6/R_M0_DQ6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 169 "/FPGA_Spartan6/R_M0_DQ6"
+Na 169 "/FPGA_Spartan6/R_M0_DQ7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 170 "/FPGA_Spartan6/R_M0_DQ7"
+Na 170 "/FPGA_Spartan6/R_M0_DQ8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 171 "/FPGA_Spartan6/R_M0_DQ8"
+Na 171 "/FPGA_Spartan6/R_M0_DQ9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 172 "/FPGA_Spartan6/R_M0_DQ9"
+Na 172 "/FPGA_Spartan6/R_M0_LDM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 173 "/FPGA_Spartan6/R_M0_LDM"
+Na 173 "/FPGA_Spartan6/R_M0_LDQS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 174 "/FPGA_Spartan6/R_M0_LDQS"
+Na 174 "/FPGA_Spartan6/R_M0_RAS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 175 "/FPGA_Spartan6/R_M0_RAS#"
+Na 175 "/FPGA_Spartan6/R_M0_UDM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 176 "/FPGA_Spartan6/R_M0_UDM"
+Na 176 "/FPGA_Spartan6/R_M0_UDQS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 177 "/FPGA_Spartan6/R_M0_UDQS"
+Na 177 "/FPGA_Spartan6/R_M0_WE#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 178 "/FPGA_Spartan6/R_M0_WE#"
+Na 178 "/FPGA_Spartan6/R_M1_A0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 179 "/FPGA_Spartan6/R_M1_A0"
+Na 179 "/FPGA_Spartan6/R_M1_A1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 180 "/FPGA_Spartan6/R_M1_A1"
+Na 180 "/FPGA_Spartan6/R_M1_A10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 181 "/FPGA_Spartan6/R_M1_A10"
+Na 181 "/FPGA_Spartan6/R_M1_A11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 182 "/FPGA_Spartan6/R_M1_A11"
+Na 182 "/FPGA_Spartan6/R_M1_A12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 183 "/FPGA_Spartan6/R_M1_A12"
+Na 183 "/FPGA_Spartan6/R_M1_A2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 184 "/FPGA_Spartan6/R_M1_A2"
+Na 184 "/FPGA_Spartan6/R_M1_A3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 185 "/FPGA_Spartan6/R_M1_A3"
+Na 185 "/FPGA_Spartan6/R_M1_A5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 186 "/FPGA_Spartan6/R_M1_A5"
+Na 186 "/FPGA_Spartan6/R_M1_A6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 187 "/FPGA_Spartan6/R_M1_A6"
+Na 187 "/FPGA_Spartan6/R_M1_A7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 188 "/FPGA_Spartan6/R_M1_A7"
+Na 188 "/FPGA_Spartan6/R_M1_A8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 189 "/FPGA_Spartan6/R_M1_A8"
+Na 189 "/FPGA_Spartan6/R_M1_A9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 190 "/FPGA_Spartan6/R_M1_A9"
+Na 190 "/FPGA_Spartan6/R_M1_BA0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 191 "/FPGA_Spartan6/R_M1_BA0"
+Na 191 "/FPGA_Spartan6/R_M1_BA1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 192 "/FPGA_Spartan6/R_M1_BA1"
+Na 192 "/FPGA_Spartan6/R_M1_CAS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 193 "/FPGA_Spartan6/R_M1_CAS#"
+Na 193 "/FPGA_Spartan6/R_M1_CKE"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 194 "/FPGA_Spartan6/R_M1_CKE"
+Na 194 "/FPGA_Spartan6/R_M1_CS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 195 "/FPGA_Spartan6/R_M1_CS#"
+Na 195 "/FPGA_Spartan6/R_M1_DQ0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 196 "/FPGA_Spartan6/R_M1_DQ0"
+Na 196 "/FPGA_Spartan6/R_M1_DQ1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 197 "/FPGA_Spartan6/R_M1_DQ1"
+Na 197 "/FPGA_Spartan6/R_M1_DQ10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 198 "/FPGA_Spartan6/R_M1_DQ10"
+Na 198 "/FPGA_Spartan6/R_M1_DQ11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 199 "/FPGA_Spartan6/R_M1_DQ11"
+Na 199 "/FPGA_Spartan6/R_M1_DQ12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 200 "/FPGA_Spartan6/R_M1_DQ12"
+Na 200 "/FPGA_Spartan6/R_M1_DQ13"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 201 "/FPGA_Spartan6/R_M1_DQ13"
+Na 201 "/FPGA_Spartan6/R_M1_DQ14"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 202 "/FPGA_Spartan6/R_M1_DQ14"
+Na 202 "/FPGA_Spartan6/R_M1_DQ15"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 203 "/FPGA_Spartan6/R_M1_DQ15"
+Na 203 "/FPGA_Spartan6/R_M1_DQ2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 204 "/FPGA_Spartan6/R_M1_DQ2"
+Na 204 "/FPGA_Spartan6/R_M1_DQ3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 205 "/FPGA_Spartan6/R_M1_DQ3"
+Na 205 "/FPGA_Spartan6/R_M1_DQ4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 206 "/FPGA_Spartan6/R_M1_DQ4"
+Na 206 "/FPGA_Spartan6/R_M1_DQ5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 207 "/FPGA_Spartan6/R_M1_DQ5"
+Na 207 "/FPGA_Spartan6/R_M1_DQ6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 208 "/FPGA_Spartan6/R_M1_DQ6"
+Na 208 "/FPGA_Spartan6/R_M1_DQ7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 209 "/FPGA_Spartan6/R_M1_DQ7"
+Na 209 "/FPGA_Spartan6/R_M1_DQ8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 210 "/FPGA_Spartan6/R_M1_DQ8"
+Na 210 "/FPGA_Spartan6/R_M1_DQ9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 211 "/FPGA_Spartan6/R_M1_DQ9"
+Na 211 "/FPGA_Spartan6/R_M1_LDM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 212 "/FPGA_Spartan6/R_M1_LDM"
+Na 212 "/FPGA_Spartan6/R_M1_LDQS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 213 "/FPGA_Spartan6/R_M1_LDQS"
+Na 213 "/FPGA_Spartan6/R_M1_RAS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 214 "/FPGA_Spartan6/R_M1_RAS#"
+Na 214 "/FPGA_Spartan6/R_M1_UDM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 215 "/FPGA_Spartan6/R_M1_UDM"
+Na 215 "/FPGA_Spartan6/R_M1_UDQS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 216 "/FPGA_Spartan6/R_M1_UDQS"
+Na 216 "/FPGA_Spartan6/R_M1_WE#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 217 "/FPGA_Spartan6/R_M1_WE#"
+Na 217 "/FPGA_Spartan6/SD_CLK"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 218 "/FPGA_Spartan6/SD_CLK"
+Na 218 "/FPGA_Spartan6/SD_CMD"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 219 "/FPGA_Spartan6/SD_DAT0"
+Na 219 "/FPGA_Spartan6/SD_DAT2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 220 "/FPGA_Spartan6/SD_DAT1"
+Na 220 "/FPGA_Spartan6/SD_DAT3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 221 "/FPGA_Spartan6/SD_DAT2"
+Na 221 "/FPGA_Spartan6/USBA_OE_N"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 222 "/FPGA_Spartan6/SD_DAT3"
+Na 222 "/FPGA_Spartan6/USBA_RCV"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 223 "/FPGA_Spartan6/USBA_OE_N"
+Na 223 "/FPGA_Spartan6/USBA_SPD"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 224 "/FPGA_Spartan6/USBA_RCV"
+Na 224 "/FPGA_Spartan6/USBD_OE_N"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 225 "/FPGA_Spartan6/USBA_SPD"
+Na 225 "/FPGA_Spartan6/USBD_RCV"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 226 "/FPGA_Spartan6/USBD_RCV"
+Na 226 "/FPGA_Spartan6/USBD_VP"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 227 "/FPGA_Spartan6/USBD_VM"
+Na 227 "/Non_volatile_memories/NF_CLE"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 228 "/Non_volatile_memories/NF_CLE"
+Na 228 "/Non_volatile_memories/NF_CS1_N"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 229 "/Non_volatile_memories/NF_CS1_N"
+Na 229 "/Non_volatile_memories/NF_D2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 230 "/Non_volatile_memories/NF_D2"
+Na 230 "/Non_volatile_memories/NF_D5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 231 "/Non_volatile_memories/NF_D3"
+Na 231 "/Non_volatile_memories/NF_RE_N"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -1002,95 +1002,95 @@ Na 233 "/Non_volatile_memories/NF_WE_N"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 234 "/Non_volatile_memories/SD_CMD"
+Na 234 "/Non_volatile_memories/SD_DAT0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 235 "/USB/USBA_VM"
+Na 235 "/Non_volatile_memories/SD_DAT1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 236 "/USB/USBA_VP"
+Na 236 "/USB/USBA_D+"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 237 "/USB/USBD_OE_N"
+Na 237 "/USB/USBA_D-"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 238 "/USB/USBD_SPD"
+Na 238 "/USB/USBA_VM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 239 "/USB/USBD_VP"
+Na 239 "/USB/USBA_VP"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 240 "GND"
+Na 240 "/USB/USBD_D+"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 241 "N-000264"
+Na 241 "/USB/USBD_D-"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 242 "N-000382"
+Na 242 "/USB/USBD_SPD"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 243 "N-000401"
+Na 243 "/USB/USBD_VM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 244 "N-000405"
+Na 244 "GND"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 245 "N-000406"
+Na 245 "N-000264"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 246 "N-000415"
+Na 246 "N-000382"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 247 "N-000417"
+Na 247 "N-000400"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 248 "N-000421"
+Na 248 "N-000404"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 249 "N-000422"
+Na 249 "N-000405"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 250 "N-000423"
+Na 250 "N-000418"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 251 "N-000424"
+Na 251 "N-000420"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 252 "N-000425"
+Na 252 "N-000426"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 253 "N-000426"
+Na 253 "N-000427"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 254 "N-000427"
+Na 254 "N-000429"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 255 "N-000428"
+Na 255 "N-000431"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 256 "N-000430"
+Na 256 "N-000432"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -1139,130 +1139,139 @@ ViaDrill 79
 uViaDia 197
 uViaDrill 79
 AddNet ""
-AddNet "/DDR_Banks/M0_A0"
-AddNet "/DDR_Banks/M0_A11"
-AddNet "/DDR_Banks/M0_A3"
-AddNet "/DDR_Banks/M0_A4"
-AddNet "/DDR_Banks/M0_A9"
+AddNet "/DBG_PRG/FPGA_TCK"
+AddNet "/DBG_PRG/FPGA_TDI"
+AddNet "/DBG_PRG/FPGA_TDO"
+AddNet "/DBG_PRG/FPGA_TMS"
+AddNet "/DDR_Banks/M0_A12"
+AddNet "/DDR_Banks/M0_A5"
+AddNet "/DDR_Banks/M0_A6"
+AddNet "/DDR_Banks/M0_A8"
+AddNet "/DDR_Banks/M0_BA0"
 AddNet "/DDR_Banks/M0_CKE"
-AddNet "/DDR_Banks/M0_DQ10"
-AddNet "/DDR_Banks/M0_DQ14"
-AddNet "/DDR_Banks/M0_DQ4"
+AddNet "/DDR_Banks/M0_CLK"
+AddNet "/DDR_Banks/M0_DQ0"
+AddNet "/DDR_Banks/M0_DQ1"
+AddNet "/DDR_Banks/M0_DQ15"
+AddNet "/DDR_Banks/M0_DQ2"
 AddNet "/DDR_Banks/M0_DQ5"
-AddNet "/DDR_Banks/M0_DQ7"
-AddNet "/DDR_Banks/M0_LDM"
-AddNet "/DDR_Banks/M0_LDQS"
+AddNet "/DDR_Banks/M0_DQ8"
+AddNet "/DDR_Banks/M0_RAS#"
+AddNet "/DDR_Banks/M0_UDM"
+AddNet "/DDR_Banks/M0_UDQS"
 AddNet "/DDR_Banks/M0_VREF"
-AddNet "/DDR_Banks/M1_A1"
-AddNet "/DDR_Banks/M1_A11"
-AddNet "/DDR_Banks/M1_A6"
+AddNet "/DDR_Banks/M0_WE#"
+AddNet "/DDR_Banks/M1_A0"
+AddNet "/DDR_Banks/M1_A12"
+AddNet "/DDR_Banks/M1_A5"
+AddNet "/DDR_Banks/M1_A8"
+AddNet "/DDR_Banks/M1_A9"
 AddNet "/DDR_Banks/M1_BA0"
-AddNet "/DDR_Banks/M1_BA1"
-AddNet "/DDR_Banks/M1_CLK#"
-AddNet "/DDR_Banks/M1_CS#"
-AddNet "/DDR_Banks/M1_DQ0"
-AddNet "/DDR_Banks/M1_DQ4"
-AddNet "/DDR_Banks/M1_DQ9"
+AddNet "/DDR_Banks/M1_CKE"
+AddNet "/DDR_Banks/M1_CLK"
+AddNet "/DDR_Banks/M1_DQ10"
+AddNet "/DDR_Banks/M1_DQ12"
+AddNet "/DDR_Banks/M1_DQ3"
+AddNet "/DDR_Banks/M1_DQ5"
+AddNet "/DDR_Banks/M1_DQ6"
+AddNet "/DDR_Banks/M1_LDM"
+AddNet "/DDR_Banks/M1_UDQS"
 AddNet "/DDR_Banks/M1_VREF"
-AddNet "/DDR_Banks/M1_WE#"
 AddNet "/Ethernet_Phy/ETH_A1.8V"
 AddNet "/Ethernet_Phy/ETH_A3.3V"
+AddNet "/Ethernet_Phy/ETH_CLK"
 AddNet "/Ethernet_Phy/ETH_COL"
+AddNet "/Ethernet_Phy/ETH_INT"
 AddNet "/Ethernet_Phy/ETH_LED0"
 AddNet "/Ethernet_Phy/ETH_LED1"
 AddNet "/Ethernet_Phy/ETH_MDIO"
 AddNet "/Ethernet_Phy/ETH_PLL1.8V"
-AddNet "/Ethernet_Phy/ETH_RXD0"
-AddNet "/Ethernet_Phy/ETH_RXD2"
-AddNet "/Ethernet_Phy/ETH_RXER"
+AddNet "/Ethernet_Phy/ETH_RXD1"
+AddNet "/Ethernet_Phy/ETH_RXD3"
+AddNet "/Ethernet_Phy/ETH_TXD0"
 AddNet "/Ethernet_Phy/ETH_TXD1"
-AddNet "/Ethernet_Phy/ETH_TXD3"
+AddNet "/Ethernet_Phy/ETH_TXEN"
 AddNet "/Ethernet_Phy/MAG_RX+"
 AddNet "/Ethernet_Phy/MAG_RX-"
 AddNet "/Ethernet_Phy/MAG_SHIELD"
 AddNet "/Ethernet_Phy/MAG_TX+"
 AddNet "/Ethernet_Phy/MAG_TX-"
-AddNet "/FPGA_Spartan6/ETH_CLK"
 AddNet "/FPGA_Spartan6/ETH_CRS"
-AddNet "/FPGA_Spartan6/ETH_INT"
 AddNet "/FPGA_Spartan6/ETH_MDC"
 AddNet "/FPGA_Spartan6/ETH_RESET_N"
 AddNet "/FPGA_Spartan6/ETH_RXC"
-AddNet "/FPGA_Spartan6/ETH_RXD1"
-AddNet "/FPGA_Spartan6/ETH_RXD3"
+AddNet "/FPGA_Spartan6/ETH_RXD0"
+AddNet "/FPGA_Spartan6/ETH_RXD2"
 AddNet "/FPGA_Spartan6/ETH_RXDV"
+AddNet "/FPGA_Spartan6/ETH_RXER"
 AddNet "/FPGA_Spartan6/ETH_TXC"
-AddNet "/FPGA_Spartan6/ETH_TXD0"
 AddNet "/FPGA_Spartan6/ETH_TXD2"
-AddNet "/FPGA_Spartan6/ETH_TXEN"
+AddNet "/FPGA_Spartan6/ETH_TXD3"
 AddNet "/FPGA_Spartan6/ETH_TXER"
+AddNet "/FPGA_Spartan6/M0_A0"
 AddNet "/FPGA_Spartan6/M0_A1"
 AddNet "/FPGA_Spartan6/M0_A10"
-AddNet "/FPGA_Spartan6/M0_A12"
+AddNet "/FPGA_Spartan6/M0_A11"
 AddNet "/FPGA_Spartan6/M0_A2"
-AddNet "/FPGA_Spartan6/M0_A5"
-AddNet "/FPGA_Spartan6/M0_A6"
+AddNet "/FPGA_Spartan6/M0_A3"
+AddNet "/FPGA_Spartan6/M0_A4"
 AddNet "/FPGA_Spartan6/M0_A7"
-AddNet "/FPGA_Spartan6/M0_A8"
-AddNet "/FPGA_Spartan6/M0_BA0"
+AddNet "/FPGA_Spartan6/M0_A9"
 AddNet "/FPGA_Spartan6/M0_BA1"
 AddNet "/FPGA_Spartan6/M0_CAS#"
-AddNet "/FPGA_Spartan6/M0_CLK"
 AddNet "/FPGA_Spartan6/M0_CLK#"
-AddNet "/FPGA_Spartan6/M0_DQ0"
-AddNet "/FPGA_Spartan6/M0_DQ1"
+AddNet "/FPGA_Spartan6/M0_DQ10"
 AddNet "/FPGA_Spartan6/M0_DQ11"
 AddNet "/FPGA_Spartan6/M0_DQ12"
 AddNet "/FPGA_Spartan6/M0_DQ13"
-AddNet "/FPGA_Spartan6/M0_DQ15"
-AddNet "/FPGA_Spartan6/M0_DQ2"
+AddNet "/FPGA_Spartan6/M0_DQ14"
 AddNet "/FPGA_Spartan6/M0_DQ3"
+AddNet "/FPGA_Spartan6/M0_DQ4"
 AddNet "/FPGA_Spartan6/M0_DQ6"
-AddNet "/FPGA_Spartan6/M0_DQ8"
+AddNet "/FPGA_Spartan6/M0_DQ7"
 AddNet "/FPGA_Spartan6/M0_DQ9"
-AddNet "/FPGA_Spartan6/M0_RAS#"
-AddNet "/FPGA_Spartan6/M0_UDM"
-AddNet "/FPGA_Spartan6/M0_UDQS"
-AddNet "/FPGA_Spartan6/M0_WE#"
-AddNet "/FPGA_Spartan6/M1_A0"
+AddNet "/FPGA_Spartan6/M0_LDM"
+AddNet "/FPGA_Spartan6/M0_LDQS"
+AddNet "/FPGA_Spartan6/M1_A1"
 AddNet "/FPGA_Spartan6/M1_A10"
-AddNet "/FPGA_Spartan6/M1_A12"
+AddNet "/FPGA_Spartan6/M1_A11"
 AddNet "/FPGA_Spartan6/M1_A2"
 AddNet "/FPGA_Spartan6/M1_A3"
 AddNet "/FPGA_Spartan6/M1_A4"
-AddNet "/FPGA_Spartan6/M1_A5"
+AddNet "/FPGA_Spartan6/M1_A6"
 AddNet "/FPGA_Spartan6/M1_A7"
-AddNet "/FPGA_Spartan6/M1_A8"
-AddNet "/FPGA_Spartan6/M1_A9"
+AddNet "/FPGA_Spartan6/M1_BA1"
 AddNet "/FPGA_Spartan6/M1_CAS#"
-AddNet "/FPGA_Spartan6/M1_CKE"
-AddNet "/FPGA_Spartan6/M1_CLK"
+AddNet "/FPGA_Spartan6/M1_CLK#"
+AddNet "/FPGA_Spartan6/M1_CS#"
+AddNet "/FPGA_Spartan6/M1_DQ0"
 AddNet "/FPGA_Spartan6/M1_DQ1"
-AddNet "/FPGA_Spartan6/M1_DQ10"
 AddNet "/FPGA_Spartan6/M1_DQ11"
-AddNet "/FPGA_Spartan6/M1_DQ12"
 AddNet "/FPGA_Spartan6/M1_DQ13"
 AddNet "/FPGA_Spartan6/M1_DQ14"
 AddNet "/FPGA_Spartan6/M1_DQ15"
 AddNet "/FPGA_Spartan6/M1_DQ2"
-AddNet "/FPGA_Spartan6/M1_DQ3"
-AddNet "/FPGA_Spartan6/M1_DQ5"
-AddNet "/FPGA_Spartan6/M1_DQ6"
+AddNet "/FPGA_Spartan6/M1_DQ4"
 AddNet "/FPGA_Spartan6/M1_DQ7"
 AddNet "/FPGA_Spartan6/M1_DQ8"
-AddNet "/FPGA_Spartan6/M1_LDM"
+AddNet "/FPGA_Spartan6/M1_DQ9"
 AddNet "/FPGA_Spartan6/M1_LDQS"
 AddNet "/FPGA_Spartan6/M1_RAS#"
 AddNet "/FPGA_Spartan6/M1_UDM"
-AddNet "/FPGA_Spartan6/M1_UDQS"
+AddNet "/FPGA_Spartan6/M1_WE#"
 AddNet "/FPGA_Spartan6/NF_ALE"
 AddNet "/FPGA_Spartan6/NF_D0"
 AddNet "/FPGA_Spartan6/NF_D1"
+AddNet "/FPGA_Spartan6/NF_D3"
 AddNet "/FPGA_Spartan6/NF_D4"
-AddNet "/FPGA_Spartan6/NF_D5"
 AddNet "/FPGA_Spartan6/NF_D6"
 AddNet "/FPGA_Spartan6/NF_D7"
-AddNet "/FPGA_Spartan6/NF_RE_N"
+AddNet "/FPGA_Spartan6/PROG_CCLK"
+AddNet "/FPGA_Spartan6/PROG_CSO"
+AddNet "/FPGA_Spartan6/PROG_MISO0"
+AddNet "/FPGA_Spartan6/PROG_MISO1"
+AddNet "/FPGA_Spartan6/PROG_MISO2"
+AddNet "/FPGA_Spartan6/PROG_MISO3"
 AddNet "/FPGA_Spartan6/R_M0_A0"
 AddNet "/FPGA_Spartan6/R_M0_A1"
 AddNet "/FPGA_Spartan6/R_M0_A10"
@@ -1341,29 +1350,31 @@ AddNet "/FPGA_Spartan6/R_M1_RAS#"
 AddNet "/FPGA_Spartan6/R_M1_UDM"
 AddNet "/FPGA_Spartan6/R_M1_UDQS"
 AddNet "/FPGA_Spartan6/R_M1_WE#"
+AddNet "/FPGA_Spartan6/SD_CLK"
+AddNet "/FPGA_Spartan6/SD_CMD"
+AddNet "/FPGA_Spartan6/SD_DAT2"
+AddNet "/FPGA_Spartan6/SD_DAT3"
 AddNet "/Non_volatile_memories/NF_CLE"
 AddNet "/Non_volatile_memories/NF_CS1_N"
 AddNet "/Non_volatile_memories/NF_D2"
-AddNet "/Non_volatile_memories/NF_D3"
+AddNet "/Non_volatile_memories/NF_D5"
+AddNet "/Non_volatile_memories/NF_RE_N"
 AddNet "/Non_volatile_memories/NF_RNB"
 AddNet "/Non_volatile_memories/NF_WE_N"
-AddNet "/Non_volatile_memories/SD_CMD"
+AddNet "/Non_volatile_memories/SD_DAT0"
+AddNet "/Non_volatile_memories/SD_DAT1"
 AddNet "N-000264"
 AddNet "N-000382"
-AddNet "N-000401"
+AddNet "N-000400"
+AddNet "N-000404"
 AddNet "N-000405"
-AddNet "N-000406"
-AddNet "N-000415"
-AddNet "N-000417"
-AddNet "N-000421"
-AddNet "N-000422"
-AddNet "N-000423"
-AddNet "N-000424"
-AddNet "N-000425"
+AddNet "N-000418"
+AddNet "N-000420"
 AddNet "N-000426"
 AddNet "N-000427"
-AddNet "N-000428"
-AddNet "N-000430"
+AddNet "N-000429"
+AddNet "N-000431"
+AddNet "N-000432"
 AddNet "N-000435"
 AddNet "N-000436"
 AddNet "N-000437"
@@ -1432,16 +1443,6 @@ ViaDia 157
 ViaDrill 79
 uViaDia 197
 uViaDrill 79
-AddNet "/DBG_PRG/FPGA_TCK"
-AddNet "/DBG_PRG/FPGA_TDI"
-AddNet "/DBG_PRG/FPGA_TDO"
-AddNet "/DBG_PRG/FPGA_TMS"
-AddNet "/FPGA_Spartan6/PROG_CCLK"
-AddNet "/FPGA_Spartan6/PROG_CSO"
-AddNet "/FPGA_Spartan6/PROG_MISO0"
-AddNet "/FPGA_Spartan6/PROG_MISO1"
-AddNet "/FPGA_Spartan6/PROG_MISO2"
-AddNet "/FPGA_Spartan6/PROG_MISO3"
 $EndNCLASS
 $NCLASS
 Name "POWER"
@@ -1469,11 +1470,6 @@ ViaDia 157
 ViaDrill 79
 uViaDia 197
 uViaDrill 79
-AddNet "/FPGA_Spartan6/SD_CLK"
-AddNet "/FPGA_Spartan6/SD_DAT0"
-AddNet "/FPGA_Spartan6/SD_DAT1"
-AddNet "/FPGA_Spartan6/SD_DAT2"
-AddNet "/FPGA_Spartan6/SD_DAT3"
 $EndNCLASS
 $NCLASS
 Name "USB"
@@ -1487,13 +1483,17 @@ uViaDrill 79
 AddNet "/FPGA_Spartan6/USBA_OE_N"
 AddNet "/FPGA_Spartan6/USBA_RCV"
 AddNet "/FPGA_Spartan6/USBA_SPD"
+AddNet "/FPGA_Spartan6/USBD_OE_N"
 AddNet "/FPGA_Spartan6/USBD_RCV"
-AddNet "/FPGA_Spartan6/USBD_VM"
+AddNet "/FPGA_Spartan6/USBD_VP"
+AddNet "/USB/USBA_D+"
+AddNet "/USB/USBA_D-"
 AddNet "/USB/USBA_VM"
 AddNet "/USB/USBA_VP"
-AddNet "/USB/USBD_OE_N"
+AddNet "/USB/USBD_D+"
+AddNet "/USB/USBD_D-"
 AddNet "/USB/USBD_SPD"
-AddNet "/USB/USBD_VP"
+AddNet "/USB/USBD_VM"
 $EndNCLASS
 $MODULE FGG484bga-p10
 Po 56269 34378 0 15 4C6D0021 4C6A0A06 ~~
@@ -1516,7 +1516,7 @@ $PAD
 Sh "A1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -4133 -4133
 $EndPAD
 $PAD
@@ -1537,49 +1537,49 @@ $PAD
 Sh "A4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "/FPGA_Spartan6/ETH_CLK"
+Ne 46 "/Ethernet_Phy/ETH_CLK"
 Po -2952 -4133
 $EndPAD
 $PAD
 Sh "A5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "/FPGA_Spartan6/ETH_RXD1"
+Ne 53 "/Ethernet_Phy/ETH_RXD1"
 Po -2558 -4133
 $EndPAD
 $PAD
 Sh "A6" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 61 "/FPGA_Spartan6/ETH_RXDV"
+Ne 69 "/FPGA_Spartan6/ETH_RXDV"
 Po -2165 -4133
 $EndPAD
 $PAD
 Sh "A7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "/FPGA_Spartan6/ETH_RXC"
+Ne 66 "/FPGA_Spartan6/ETH_RXC"
 Po -1771 -4133
 $EndPAD
 $PAD
 Sh "A8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 47 "/Ethernet_Phy/ETH_TXD3"
+Ne 73 "/FPGA_Spartan6/ETH_TXD3"
 Po -1377 -4133
 $EndPAD
 $PAD
 Sh "A9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 38 "/Ethernet_Phy/ETH_COL"
+Ne 47 "/Ethernet_Phy/ETH_COL"
 Po -983 -4133
 $EndPAD
 $PAD
 Sh "A10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "/FPGA_Spartan6/ETH_INT"
+Ne 48 "/Ethernet_Phy/ETH_INT"
 Po -590 -4133
 $EndPAD
 $PAD
@@ -1593,14 +1593,14 @@ $PAD
 Sh "A12" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 129 "/FPGA_Spartan6/NF_D4"
+Ne 130 "/FPGA_Spartan6/NF_D4"
 Po 196 -4133
 $EndPAD
 $PAD
 Sh "A13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 230 "/Non_volatile_memories/NF_D2"
+Ne 229 "/Non_volatile_memories/NF_D2"
 Po 590 -4133
 $EndPAD
 $PAD
@@ -1621,21 +1621,21 @@ $PAD
 Sh "A16" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 221 "/FPGA_Spartan6/SD_DAT2"
+Ne 219 "/FPGA_Spartan6/SD_DAT2"
 Po 1771 -4133
 $EndPAD
 $PAD
 Sh "A17" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 218 "/FPGA_Spartan6/SD_CLK"
+Ne 217 "/FPGA_Spartan6/SD_CLK"
 Po 2165 -4133
 $EndPAD
 $PAD
 Sh "A18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 219 "/FPGA_Spartan6/SD_DAT0"
+Ne 234 "/Non_volatile_memories/SD_DAT0"
 Po 2558 -4133
 $EndPAD
 $PAD
@@ -1649,21 +1649,21 @@ $PAD
 Sh "A20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 225 "/FPGA_Spartan6/USBD_RCV"
 Po 3346 -4133
 $EndPAD
 $PAD
 Sh "A21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 224 "/FPGA_Spartan6/USBD_OE_N"
 Po 3739 -4133
 $EndPAD
 $PAD
 Sh "A22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 4133 -4133
 $EndPAD
 $PAD
@@ -1698,14 +1698,14 @@ $PAD
 Sh "B5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2558 -3739
 $EndPAD
 $PAD
 Sh "B6" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 43 "/Ethernet_Phy/ETH_RXD0"
+Ne 67 "/FPGA_Spartan6/ETH_RXD0"
 Po -2165 -3739
 $EndPAD
 $PAD
@@ -1719,21 +1719,21 @@ $PAD
 Sh "B8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 45 "/Ethernet_Phy/ETH_RXER"
+Ne 70 "/FPGA_Spartan6/ETH_RXER"
 Po -1377 -3739
 $EndPAD
 $PAD
 Sh "B9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -983 -3739
 $EndPAD
 $PAD
 Sh "B10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "/FPGA_Spartan6/ETH_CRS"
+Ne 63 "/FPGA_Spartan6/ETH_CRS"
 Po -590 -3739
 $EndPAD
 $PAD
@@ -1747,21 +1747,21 @@ $PAD
 Sh "B12" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 231 "/Non_volatile_memories/NF_D3"
+Ne 129 "/FPGA_Spartan6/NF_D3"
 Po 196 -3739
 $EndPAD
 $PAD
 Sh "B13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 590 -3739
 $EndPAD
 $PAD
 Sh "B14" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 228 "/Non_volatile_memories/NF_CLE"
+Ne 227 "/Non_volatile_memories/NF_CLE"
 Po 983 -3739
 $EndPAD
 $PAD
@@ -1775,21 +1775,21 @@ $PAD
 Sh "B16" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 222 "/FPGA_Spartan6/SD_DAT3"
+Ne 220 "/FPGA_Spartan6/SD_DAT3"
 Po 1771 -3739
 $EndPAD
 $PAD
 Sh "B17" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 2165 -3739
 $EndPAD
 $PAD
 Sh "B18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 220 "/FPGA_Spartan6/SD_DAT1"
+Ne 235 "/Non_volatile_memories/SD_DAT1"
 Po 2558 -3739
 $EndPAD
 $PAD
@@ -1803,28 +1803,28 @@ $PAD
 Sh "B20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 223 "/FPGA_Spartan6/USBA_OE_N"
+Ne 242 "/USB/USBD_SPD"
 Po 3346 -3739
 $EndPAD
 $PAD
 Sh "B21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 226 "/FPGA_Spartan6/USBD_VP"
 Po 3739 -3739
 $EndPAD
 $PAD
 Sh "B22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 243 "/USB/USBD_VM"
 Po 4133 -3739
 $EndPAD
 $PAD
 Sh "C1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 143 "/FPGA_Spartan6/R_M0_A11"
+Ne 142 "/FPGA_Spartan6/R_M0_A11"
 Po -4133 -3346
 $EndPAD
 $PAD
@@ -1852,49 +1852,49 @@ $PAD
 Sh "C5" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 60 "/FPGA_Spartan6/ETH_RXD3"
+Ne 54 "/Ethernet_Phy/ETH_RXD3"
 Po -2558 -3346
 $EndPAD
 $PAD
 Sh "C6" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 44 "/Ethernet_Phy/ETH_RXD2"
+Ne 68 "/FPGA_Spartan6/ETH_RXD2"
 Po -2165 -3346
 $EndPAD
 $PAD
 Sh "C7" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "/FPGA_Spartan6/ETH_RESET_N"
+Ne 65 "/FPGA_Spartan6/ETH_RESET_N"
 Po -1771 -3346
 $EndPAD
 $PAD
 Sh "C8" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 62 "/FPGA_Spartan6/ETH_TXC"
+Ne 71 "/FPGA_Spartan6/ETH_TXC"
 Po -1377 -3346
 $EndPAD
 $PAD
 Sh "C9" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 46 "/Ethernet_Phy/ETH_TXD1"
+Ne 56 "/Ethernet_Phy/ETH_TXD1"
 Po -983 -3346
 $EndPAD
 $PAD
 Sh "C10" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 64 "/FPGA_Spartan6/ETH_TXD2"
+Ne 72 "/FPGA_Spartan6/ETH_TXD2"
 Po -590 -3346
 $EndPAD
 $PAD
 Sh "C11" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 130 "/FPGA_Spartan6/NF_D5"
+Ne 230 "/Non_volatile_memories/NF_D5"
 Po -196 -3346
 $EndPAD
 $PAD
@@ -1922,14 +1922,14 @@ $PAD
 Sh "C15" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 133 "/FPGA_Spartan6/NF_RE_N"
+Ne 231 "/Non_volatile_memories/NF_RE_N"
 Po 1377 -3346
 $EndPAD
 $PAD
 Sh "C16" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 234 "/Non_volatile_memories/SD_CMD"
+Ne 218 "/FPGA_Spartan6/SD_CMD"
 Po 1771 -3346
 $EndPAD
 $PAD
@@ -1950,14 +1950,14 @@ $PAD
 Sh "C19" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 235 "/USB/USBA_VM"
+Ne 221 "/FPGA_Spartan6/USBA_OE_N"
 Po 2952 -3346
 $EndPAD
 $PAD
 Sh "C20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 189 "/FPGA_Spartan6/R_M1_A8"
+Ne 188 "/FPGA_Spartan6/R_M1_A8"
 Po 3346 -3346
 $EndPAD
 $PAD
@@ -1971,21 +1971,21 @@ $PAD
 Sh "C22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 190 "/FPGA_Spartan6/R_M1_A9"
+Ne 189 "/FPGA_Spartan6/R_M1_A9"
 Po 4133 -3346
 $EndPAD
 $PAD
 Sh "D1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 144 "/FPGA_Spartan6/R_M0_A12"
+Ne 143 "/FPGA_Spartan6/R_M0_A12"
 Po -4133 -2952
 $EndPAD
 $PAD
 Sh "D2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 156 "/FPGA_Spartan6/R_M0_CKE"
+Ne 155 "/FPGA_Spartan6/R_M0_CKE"
 Po -3739 -2952
 $EndPAD
 $PAD
@@ -1999,7 +1999,7 @@ $PAD
 Sh "D4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2952 -2952
 $EndPAD
 $PAD
@@ -2013,35 +2013,35 @@ $PAD
 Sh "D6" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 41 "/Ethernet_Phy/ETH_MDIO"
+Ne 51 "/Ethernet_Phy/ETH_MDIO"
 Po -2165 -2952
 $EndPAD
 $PAD
 Sh "D7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "/FPGA_Spartan6/ETH_MDC"
+Ne 64 "/FPGA_Spartan6/ETH_MDC"
 Po -1771 -2952
 $EndPAD
 $PAD
 Sh "D8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 66 "/FPGA_Spartan6/ETH_TXER"
+Ne 74 "/FPGA_Spartan6/ETH_TXER"
 Po -1377 -2952
 $EndPAD
 $PAD
 Sh "D9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 65 "/FPGA_Spartan6/ETH_TXEN"
+Ne 57 "/Ethernet_Phy/ETH_TXEN"
 Po -983 -2952
 $EndPAD
 $PAD
 Sh "D10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 63 "/FPGA_Spartan6/ETH_TXD0"
+Ne 55 "/Ethernet_Phy/ETH_TXD0"
 Po -590 -2952
 $EndPAD
 $PAD
@@ -2076,7 +2076,7 @@ $PAD
 Sh "D15" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 229 "/Non_volatile_memories/NF_CS1_N"
+Ne 228 "/Non_volatile_memories/NF_CS1_N"
 Po 1377 -2952
 $EndPAD
 $PAD
@@ -2097,56 +2097,56 @@ $PAD
 Sh "D18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 2558 -2952
 $EndPAD
 $PAD
 Sh "D19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 236 "/USB/USBA_VP"
+Ne 239 "/USB/USBA_VP"
 Po 2952 -2952
 $EndPAD
 $PAD
 Sh "D20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 238 "/USB/USBA_VM"
 Po 3346 -2952
 $EndPAD
 $PAD
 Sh "D21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 194 "/FPGA_Spartan6/R_M1_CKE"
+Ne 193 "/FPGA_Spartan6/R_M1_CKE"
 Po 3739 -2952
 $EndPAD
 $PAD
 Sh "D22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 183 "/FPGA_Spartan6/R_M1_A12"
+Ne 182 "/FPGA_Spartan6/R_M1_A12"
 Po 4133 -2952
 $EndPAD
 $PAD
 Sh "E1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 152 "/FPGA_Spartan6/R_M0_A9"
+Ne 151 "/FPGA_Spartan6/R_M0_A9"
 Po -4133 -2558
 $EndPAD
 $PAD
 Sh "E2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -3739 -2558
 $EndPAD
 $PAD
 Sh "E3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 151 "/FPGA_Spartan6/R_M0_A8"
+Ne 150 "/FPGA_Spartan6/R_M0_A8"
 Po -3346 -2558
 $EndPAD
 $PAD
@@ -2174,7 +2174,7 @@ $PAD
 Sh "E7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -1771 -2558
 $EndPAD
 $PAD
@@ -2202,7 +2202,7 @@ $PAD
 Sh "E11" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -196 -2558
 $EndPAD
 $PAD
@@ -2230,7 +2230,7 @@ $PAD
 Sh "E15" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 1377 -2558
 $EndPAD
 $PAD
@@ -2265,21 +2265,21 @@ $PAD
 Sh "E20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 188 "/FPGA_Spartan6/R_M1_A7"
+Ne 187 "/FPGA_Spartan6/R_M1_A7"
 Po 3346 -2558
 $EndPAD
 $PAD
 Sh "E21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 3739 -2558
 $EndPAD
 $PAD
 Sh "E22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 184 "/FPGA_Spartan6/R_M1_A2"
+Ne 183 "/FPGA_Spartan6/R_M1_A2"
 Po 4133 -2558
 $EndPAD
 $PAD
@@ -2293,14 +2293,14 @@ $PAD
 Sh "F2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 178 "/FPGA_Spartan6/R_M0_WE#"
+Ne 177 "/FPGA_Spartan6/R_M0_WE#"
 Po -3739 -2165
 $EndPAD
 $PAD
 Sh "F3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 147 "/FPGA_Spartan6/R_M0_A4"
+Ne 146 "/FPGA_Spartan6/R_M0_A4"
 Po -3346 -2165
 $EndPAD
 $PAD
@@ -2391,14 +2391,14 @@ $PAD
 Sh "F16" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 225 "/FPGA_Spartan6/USBA_SPD"
+Ne 223 "/FPGA_Spartan6/USBA_SPD"
 Po 1771 -2165
 $EndPAD
 $PAD
 Sh "F17" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 224 "/FPGA_Spartan6/USBA_RCV"
+Ne 222 "/FPGA_Spartan6/USBA_RCV"
 Po 2165 -2165
 $EndPAD
 $PAD
@@ -2412,7 +2412,7 @@ $PAD
 Sh "F19" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 182 "/FPGA_Spartan6/R_M1_A11"
+Ne 181 "/FPGA_Spartan6/R_M1_A11"
 Po 2952 -2165
 $EndPAD
 $PAD
@@ -2426,21 +2426,21 @@ $PAD
 Sh "F21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 179 "/FPGA_Spartan6/R_M1_A0"
+Ne 178 "/FPGA_Spartan6/R_M1_A0"
 Po 3739 -2165
 $EndPAD
 $PAD
 Sh "F22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 180 "/FPGA_Spartan6/R_M1_A1"
+Ne 179 "/FPGA_Spartan6/R_M1_A1"
 Po 4133 -2165
 $EndPAD
 $PAD
 Sh "G1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 154 "/FPGA_Spartan6/R_M0_BA1"
+Ne 153 "/FPGA_Spartan6/R_M0_BA1"
 Po -4133 -1771
 $EndPAD
 $PAD
@@ -2454,21 +2454,21 @@ $PAD
 Sh "G3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 153 "/FPGA_Spartan6/R_M0_BA0"
+Ne 152 "/FPGA_Spartan6/R_M0_BA0"
 Po -3346 -1771
 $EndPAD
 $PAD
 Sh "G4" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 142 "/FPGA_Spartan6/R_M0_A10"
+Ne 141 "/FPGA_Spartan6/R_M0_A10"
 Po -2952 -1771
 $EndPAD
 $PAD
 Sh "G5" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2558 -1771
 $EndPAD
 $PAD
@@ -2559,21 +2559,21 @@ $PAD
 Sh "G18" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 2558 -1771
 $EndPAD
 $PAD
 Sh "G19" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 181 "/FPGA_Spartan6/R_M1_A10"
+Ne 180 "/FPGA_Spartan6/R_M1_A10"
 Po 2952 -1771
 $EndPAD
 $PAD
 Sh "G20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 185 "/FPGA_Spartan6/R_M1_A3"
+Ne 184 "/FPGA_Spartan6/R_M1_A3"
 Po 3346 -1771
 $EndPAD
 $PAD
@@ -2594,49 +2594,49 @@ $PAD
 Sh "H1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 141 "/FPGA_Spartan6/R_M0_A1"
+Ne 140 "/FPGA_Spartan6/R_M0_A1"
 Po -4133 -1377
 $EndPAD
 $PAD
 Sh "H2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 140 "/FPGA_Spartan6/R_M0_A0"
+Ne 139 "/FPGA_Spartan6/R_M0_A0"
 Po -3739 -1377
 $EndPAD
 $PAD
 Sh "H3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 79 "/FPGA_Spartan6/M0_CLK#"
+Ne 86 "/FPGA_Spartan6/M0_CLK#"
 Po -3346 -1377
 $EndPAD
 $PAD
 Sh "H4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 78 "/FPGA_Spartan6/M0_CLK"
+Ne 16 "/DDR_Banks/M0_CLK"
 Po -2952 -1377
 $EndPAD
 $PAD
 Sh "H5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 145 "/FPGA_Spartan6/R_M0_A2"
+Ne 144 "/FPGA_Spartan6/R_M0_A2"
 Po -2558 -1377
 $EndPAD
 $PAD
 Sh "H6" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 150 "/FPGA_Spartan6/R_M0_A7"
+Ne 149 "/FPGA_Spartan6/R_M0_A7"
 Po -2165 -1377
 $EndPAD
 $PAD
 Sh "H7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -1771 -1377
 $EndPAD
 $PAD
@@ -2699,7 +2699,7 @@ $PAD
 Sh "H16" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 195 "/FPGA_Spartan6/R_M1_CS#"
+Ne 194 "/FPGA_Spartan6/R_M1_CS#"
 Po 1771 -1377
 $EndPAD
 $PAD
@@ -2720,56 +2720,56 @@ $PAD
 Sh "H19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 217 "/FPGA_Spartan6/R_M1_WE#"
+Ne 216 "/FPGA_Spartan6/R_M1_WE#"
 Po 2952 -1377
 $EndPAD
 $PAD
 Sh "H20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 107 "/FPGA_Spartan6/M1_CLK"
+Ne 35 "/DDR_Banks/M1_CLK"
 Po 3346 -1377
 $EndPAD
 $PAD
 Sh "H21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 214 "/FPGA_Spartan6/R_M1_RAS#"
+Ne 213 "/FPGA_Spartan6/R_M1_RAS#"
 Po 3739 -1377
 $EndPAD
 $PAD
 Sh "H22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 193 "/FPGA_Spartan6/R_M1_CAS#"
+Ne 192 "/FPGA_Spartan6/R_M1_CAS#"
 Po 4133 -1377
 $EndPAD
 $PAD
 Sh "J1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 168 "/FPGA_Spartan6/R_M0_DQ5"
+Ne 167 "/FPGA_Spartan6/R_M0_DQ5"
 Po -4133 -983
 $EndPAD
 $PAD
 Sh "J2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -3739 -983
 $EndPAD
 $PAD
 Sh "J3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 167 "/FPGA_Spartan6/R_M0_DQ4"
+Ne 166 "/FPGA_Spartan6/R_M0_DQ4"
 Po -3346 -983
 $EndPAD
 $PAD
 Sh "J4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 149 "/FPGA_Spartan6/R_M0_A6"
+Ne 148 "/FPGA_Spartan6/R_M0_A6"
 Po -2952 -983
 $EndPAD
 $PAD
@@ -2804,7 +2804,7 @@ $PAD
 Sh "J9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -983 -983
 $EndPAD
 $PAD
@@ -2818,7 +2818,7 @@ $PAD
 Sh "J11" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -196 -983
 $EndPAD
 $PAD
@@ -2832,7 +2832,7 @@ $PAD
 Sh "J13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 590 -983
 $EndPAD
 $PAD
@@ -2846,7 +2846,7 @@ $PAD
 Sh "J15" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 1377 -983
 $EndPAD
 $PAD
@@ -2860,7 +2860,7 @@ $PAD
 Sh "J17" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 191 "/FPGA_Spartan6/R_M1_BA0"
+Ne 190 "/FPGA_Spartan6/R_M1_BA0"
 Po 2165 -983
 $EndPAD
 $PAD
@@ -2874,70 +2874,70 @@ $PAD
 Sh "J19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 29 "/DDR_Banks/M1_CLK#"
+Ne 109 "/FPGA_Spartan6/M1_CLK#"
 Po 2952 -983
 $EndPAD
 $PAD
 Sh "J20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 206 "/FPGA_Spartan6/R_M1_DQ4"
+Ne 205 "/FPGA_Spartan6/R_M1_DQ4"
 Po 3346 -983
 $EndPAD
 $PAD
 Sh "J21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 3739 -983
 $EndPAD
 $PAD
 Sh "J22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 207 "/FPGA_Spartan6/R_M1_DQ5"
+Ne 206 "/FPGA_Spartan6/R_M1_DQ5"
 Po 4133 -983
 $EndPAD
 $PAD
 Sh "K1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 170 "/FPGA_Spartan6/R_M0_DQ7"
+Ne 169 "/FPGA_Spartan6/R_M0_DQ7"
 Po -4133 -590
 $EndPAD
 $PAD
 Sh "K2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 169 "/FPGA_Spartan6/R_M0_DQ6"
+Ne 168 "/FPGA_Spartan6/R_M0_DQ6"
 Po -3739 -590
 $EndPAD
 $PAD
 Sh "K3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 148 "/FPGA_Spartan6/R_M0_A5"
+Ne 147 "/FPGA_Spartan6/R_M0_A5"
 Po -3346 -590
 $EndPAD
 $PAD
 Sh "K4" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 155 "/FPGA_Spartan6/R_M0_CAS#"
+Ne 154 "/FPGA_Spartan6/R_M0_CAS#"
 Po -2952 -590
 $EndPAD
 $PAD
 Sh "K5" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 175 "/FPGA_Spartan6/R_M0_RAS#"
+Ne 174 "/FPGA_Spartan6/R_M0_RAS#"
 Po -2558 -590
 $EndPAD
 $PAD
 Sh "K6" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 146 "/FPGA_Spartan6/R_M0_A3"
+Ne 145 "/FPGA_Spartan6/R_M0_A3"
 Po -2165 -590
 $EndPAD
 $PAD
@@ -2965,7 +2965,7 @@ $PAD
 Sh "K10" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -590 -590
 $EndPAD
 $PAD
@@ -2979,7 +2979,7 @@ $PAD
 Sh "K12" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 196 -590
 $EndPAD
 $PAD
@@ -2993,7 +2993,7 @@ $PAD
 Sh "K14" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 983 -590
 $EndPAD
 $PAD
@@ -3014,7 +3014,7 @@ $PAD
 Sh "K17" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 192 "/FPGA_Spartan6/R_M1_BA1"
+Ne 191 "/FPGA_Spartan6/R_M1_BA1"
 Po 2165 -590
 $EndPAD
 $PAD
@@ -3028,28 +3028,28 @@ $PAD
 Sh "K19" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 187 "/FPGA_Spartan6/R_M1_A6"
+Ne 186 "/FPGA_Spartan6/R_M1_A6"
 Po 2952 -590
 $EndPAD
 $PAD
 Sh "K20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 186 "/FPGA_Spartan6/R_M1_A5"
+Ne 185 "/FPGA_Spartan6/R_M1_A5"
 Po 3346 -590
 $EndPAD
 $PAD
 Sh "K21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 208 "/FPGA_Spartan6/R_M1_DQ6"
+Ne 207 "/FPGA_Spartan6/R_M1_DQ6"
 Po 3739 -590
 $EndPAD
 $PAD
 Sh "K22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 209 "/FPGA_Spartan6/R_M1_DQ7"
+Ne 208 "/FPGA_Spartan6/R_M1_DQ7"
 Po 4133 -590
 $EndPAD
 $PAD
@@ -3070,21 +3070,21 @@ $PAD
 Sh "L3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 174 "/FPGA_Spartan6/R_M0_LDQS"
+Ne 173 "/FPGA_Spartan6/R_M0_LDQS"
 Po -3346 -196
 $EndPAD
 $PAD
 Sh "L4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 173 "/FPGA_Spartan6/R_M0_LDM"
+Ne 172 "/FPGA_Spartan6/R_M0_LDM"
 Po -2952 -196
 $EndPAD
 $PAD
 Sh "L5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2558 -196
 $EndPAD
 $PAD
@@ -3112,7 +3112,7 @@ $PAD
 Sh "L9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -983 -196
 $EndPAD
 $PAD
@@ -3126,7 +3126,7 @@ $PAD
 Sh "L11" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -196 -196
 $EndPAD
 $PAD
@@ -3140,7 +3140,7 @@ $PAD
 Sh "L13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 590 -196
 $EndPAD
 $PAD
@@ -3175,21 +3175,21 @@ $PAD
 Sh "L18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 2558 -196
 $EndPAD
 $PAD
 Sh "L19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 212 "/FPGA_Spartan6/R_M1_LDM"
+Ne 211 "/FPGA_Spartan6/R_M1_LDM"
 Po 2952 -196
 $EndPAD
 $PAD
 Sh "L20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 213 "/FPGA_Spartan6/R_M1_LDQS"
+Ne 212 "/FPGA_Spartan6/R_M1_LDQS"
 Po 3346 -196
 $EndPAD
 $PAD
@@ -3210,21 +3210,21 @@ $PAD
 Sh "M1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 166 "/FPGA_Spartan6/R_M0_DQ3"
+Ne 165 "/FPGA_Spartan6/R_M0_DQ3"
 Po -4133 196
 $EndPAD
 $PAD
 Sh "M2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 165 "/FPGA_Spartan6/R_M0_DQ2"
+Ne 164 "/FPGA_Spartan6/R_M0_DQ2"
 Po -3739 196
 $EndPAD
 $PAD
 Sh "M3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 176 "/FPGA_Spartan6/R_M0_UDM"
+Ne 175 "/FPGA_Spartan6/R_M0_UDM"
 Po -3346 196
 $EndPAD
 $PAD
@@ -3273,7 +3273,7 @@ $PAD
 Sh "M10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -590 196
 $EndPAD
 $PAD
@@ -3287,7 +3287,7 @@ $PAD
 Sh "M12" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 196 196
 $EndPAD
 $PAD
@@ -3301,7 +3301,7 @@ $PAD
 Sh "M14" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 983 196
 $EndPAD
 $PAD
@@ -3322,14 +3322,14 @@ $PAD
 Sh "M17" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 226 "/FPGA_Spartan6/USBD_RCV"
+Ne 0 ""
 Po 2165 196
 $EndPAD
 $PAD
 Sh "M18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 238 "/USB/USBD_SPD"
+Ne 0 ""
 Po 2558 196
 $EndPAD
 $PAD
@@ -3343,42 +3343,42 @@ $PAD
 Sh "M20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 215 "/FPGA_Spartan6/R_M1_UDM"
+Ne 214 "/FPGA_Spartan6/R_M1_UDM"
 Po 3346 196
 $EndPAD
 $PAD
 Sh "M21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 204 "/FPGA_Spartan6/R_M1_DQ2"
+Ne 203 "/FPGA_Spartan6/R_M1_DQ2"
 Po 3739 196
 $EndPAD
 $PAD
 Sh "M22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 205 "/FPGA_Spartan6/R_M1_DQ3"
+Ne 204 "/FPGA_Spartan6/R_M1_DQ3"
 Po 4133 196
 $EndPAD
 $PAD
 Sh "N1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 158 "/FPGA_Spartan6/R_M0_DQ1"
+Ne 157 "/FPGA_Spartan6/R_M0_DQ1"
 Po -4133 590
 $EndPAD
 $PAD
 Sh "N2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -3739 590
 $EndPAD
 $PAD
 Sh "N3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 157 "/FPGA_Spartan6/R_M0_DQ0"
+Ne 156 "/FPGA_Spartan6/R_M0_DQ0"
 Po -3346 590
 $EndPAD
 $PAD
@@ -3420,7 +3420,7 @@ $PAD
 Sh "N9" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -983 590
 $EndPAD
 $PAD
@@ -3434,7 +3434,7 @@ $PAD
 Sh "N11" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -196 590
 $EndPAD
 $PAD
@@ -3448,7 +3448,7 @@ $PAD
 Sh "N13" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 590 590
 $EndPAD
 $PAD
@@ -3462,21 +3462,21 @@ $PAD
 Sh "N15" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 1377 590
 $EndPAD
 $PAD
 Sh "N16" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 237 "/USB/USBD_OE_N"
+Ne 0 ""
 Po 1771 590
 $EndPAD
 $PAD
 Sh "N17" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 2165 590
 $EndPAD
 $PAD
@@ -3497,35 +3497,35 @@ $PAD
 Sh "N20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 196 "/FPGA_Spartan6/R_M1_DQ0"
+Ne 195 "/FPGA_Spartan6/R_M1_DQ0"
 Po 3346 590
 $EndPAD
 $PAD
 Sh "N21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 3739 590
 $EndPAD
 $PAD
 Sh "N22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 197 "/FPGA_Spartan6/R_M1_DQ1"
+Ne 196 "/FPGA_Spartan6/R_M1_DQ1"
 Po 4133 590
 $EndPAD
 $PAD
 Sh "P1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 172 "/FPGA_Spartan6/R_M0_DQ9"
+Ne 171 "/FPGA_Spartan6/R_M0_DQ9"
 Po -4133 983
 $EndPAD
 $PAD
 Sh "P2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 171 "/FPGA_Spartan6/R_M0_DQ8"
+Ne 170 "/FPGA_Spartan6/R_M0_DQ8"
 Po -3739 983
 $EndPAD
 $PAD
@@ -3581,7 +3581,7 @@ $PAD
 Sh "P10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -590 983
 $EndPAD
 $PAD
@@ -3595,7 +3595,7 @@ $PAD
 Sh "P12" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 196 983
 $EndPAD
 $PAD
@@ -3609,7 +3609,7 @@ $PAD
 Sh "P14" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 983 983
 $EndPAD
 $PAD
@@ -3630,14 +3630,14 @@ $PAD
 Sh "P17" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 239 "/USB/USBD_VP"
+Ne 0 ""
 Po 2165 983
 $EndPAD
 $PAD
 Sh "P18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 227 "/FPGA_Spartan6/USBD_VM"
+Ne 0 ""
 Po 2558 983
 $EndPAD
 $PAD
@@ -3658,21 +3658,21 @@ $PAD
 Sh "P21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 210 "/FPGA_Spartan6/R_M1_DQ8"
+Ne 209 "/FPGA_Spartan6/R_M1_DQ8"
 Po 3739 983
 $EndPAD
 $PAD
 Sh "P22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 211 "/FPGA_Spartan6/R_M1_DQ9"
+Ne 210 "/FPGA_Spartan6/R_M1_DQ9"
 Po 4133 983
 $EndPAD
 $PAD
 Sh "R1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 160 "/FPGA_Spartan6/R_M0_DQ11"
+Ne 159 "/FPGA_Spartan6/R_M0_DQ11"
 Po -4133 1377
 $EndPAD
 $PAD
@@ -3686,7 +3686,7 @@ $PAD
 Sh "R3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 159 "/FPGA_Spartan6/R_M0_DQ10"
+Ne 158 "/FPGA_Spartan6/R_M0_DQ10"
 Po -3346 1377
 $EndPAD
 $PAD
@@ -3700,7 +3700,7 @@ $PAD
 Sh "R5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2558 1377
 $EndPAD
 $PAD
@@ -3791,7 +3791,7 @@ $PAD
 Sh "R18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 2558 1377
 $EndPAD
 $PAD
@@ -3805,7 +3805,7 @@ $PAD
 Sh "R20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 198 "/FPGA_Spartan6/R_M1_DQ10"
+Ne 197 "/FPGA_Spartan6/R_M1_DQ10"
 Po 3346 1377
 $EndPAD
 $PAD
@@ -3819,7 +3819,7 @@ $PAD
 Sh "R22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 199 "/FPGA_Spartan6/R_M1_DQ11"
+Ne 198 "/FPGA_Spartan6/R_M1_DQ11"
 Po 4133 1377
 $EndPAD
 $PAD
@@ -3833,7 +3833,7 @@ $PAD
 Sh "T2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 177 "/FPGA_Spartan6/R_M0_UDQS"
+Ne 176 "/FPGA_Spartan6/R_M0_UDQS"
 Po -3739 1771
 $EndPAD
 $PAD
@@ -3854,7 +3854,7 @@ $PAD
 Sh "T5" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 135 "/FPGA_Spartan6/PROG_CSO"
+Ne 134 "/FPGA_Spartan6/PROG_CSO"
 Po -2558 1771
 $EndPAD
 $PAD
@@ -3966,7 +3966,7 @@ $PAD
 Sh "T21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 216 "/FPGA_Spartan6/R_M1_UDQS"
+Ne 215 "/FPGA_Spartan6/R_M1_UDQS"
 Po 3739 1771
 $EndPAD
 $PAD
@@ -3980,21 +3980,21 @@ $PAD
 Sh "U1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 162 "/FPGA_Spartan6/R_M0_DQ13"
+Ne 161 "/FPGA_Spartan6/R_M0_DQ13"
 Po -4133 2165
 $EndPAD
 $PAD
 Sh "U2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -3739 2165
 $EndPAD
 $PAD
 Sh "U3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 161 "/FPGA_Spartan6/R_M0_DQ12"
+Ne 160 "/FPGA_Spartan6/R_M0_DQ12"
 Po -3346 2165
 $EndPAD
 $PAD
@@ -4022,7 +4022,7 @@ $PAD
 Sh "U7" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -1771 2165
 $EndPAD
 $PAD
@@ -4064,14 +4064,14 @@ $PAD
 Sh "U13" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 139 "/FPGA_Spartan6/PROG_MISO3"
+Ne 138 "/FPGA_Spartan6/PROG_MISO3"
 Po 590 2165
 $EndPAD
 $PAD
 Sh "U14" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 138 "/FPGA_Spartan6/PROG_MISO2"
+Ne 137 "/FPGA_Spartan6/PROG_MISO2"
 Po 983 2165
 $EndPAD
 $PAD
@@ -4113,35 +4113,35 @@ $PAD
 Sh "U20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 200 "/FPGA_Spartan6/R_M1_DQ12"
+Ne 199 "/FPGA_Spartan6/R_M1_DQ12"
 Po 3346 2165
 $EndPAD
 $PAD
 Sh "U21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 3739 2165
 $EndPAD
 $PAD
 Sh "U22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 201 "/FPGA_Spartan6/R_M1_DQ13"
+Ne 200 "/FPGA_Spartan6/R_M1_DQ13"
 Po 4133 2165
 $EndPAD
 $PAD
 Sh "V1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 164 "/FPGA_Spartan6/R_M0_DQ15"
+Ne 163 "/FPGA_Spartan6/R_M0_DQ15"
 Po -4133 2558
 $EndPAD
 $PAD
 Sh "V2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 163 "/FPGA_Spartan6/R_M0_DQ14"
+Ne 162 "/FPGA_Spartan6/R_M0_DQ14"
 Po -3739 2558
 $EndPAD
 $PAD
@@ -4155,7 +4155,7 @@ $PAD
 Sh "V4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2952 2558
 $EndPAD
 $PAD
@@ -4197,7 +4197,7 @@ $PAD
 Sh "V10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -590 2558
 $EndPAD
 $PAD
@@ -4225,7 +4225,7 @@ $PAD
 Sh "V14" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 983 2558
 $EndPAD
 $PAD
@@ -4274,14 +4274,14 @@ $PAD
 Sh "V21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 202 "/FPGA_Spartan6/R_M1_DQ14"
+Ne 201 "/FPGA_Spartan6/R_M1_DQ14"
 Po 3739 2558
 $EndPAD
 $PAD
 Sh "V22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 203 "/FPGA_Spartan6/R_M1_DQ15"
+Ne 202 "/FPGA_Spartan6/R_M1_DQ15"
 Po 4133 2558
 $EndPAD
 $PAD
@@ -4330,7 +4330,7 @@ $PAD
 Sh "W7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -1771 2952
 $EndPAD
 $PAD
@@ -4393,7 +4393,7 @@ $PAD
 Sh "W16" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 1771 2952
 $EndPAD
 $PAD
@@ -4414,7 +4414,7 @@ $PAD
 Sh "W19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 2952 2952
 $EndPAD
 $PAD
@@ -4589,14 +4589,14 @@ $PAD
 Sh "Y22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 241 "N-000264"
+Ne 245 "N-000264"
 Po 4133 3346
 $EndPAD
 $PAD
 Sh "AA1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 242 "N-000382"
+Ne 246 "N-000382"
 Po -4133 3739
 $EndPAD
 $PAD
@@ -4624,7 +4624,7 @@ $PAD
 Sh "AA5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2558 3739
 $EndPAD
 $PAD
@@ -4652,7 +4652,7 @@ $PAD
 Sh "AA9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -983 3739
 $EndPAD
 $PAD
@@ -4680,7 +4680,7 @@ $PAD
 Sh "AA13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 590 3739
 $EndPAD
 $PAD
@@ -4708,7 +4708,7 @@ $PAD
 Sh "AA17" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 2165 3739
 $EndPAD
 $PAD
@@ -4729,14 +4729,14 @@ $PAD
 Sh "AA20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 137 "/FPGA_Spartan6/PROG_MISO1"
+Ne 136 "/FPGA_Spartan6/PROG_MISO1"
 Po 3346 3739
 $EndPAD
 $PAD
 Sh "AA21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 134 "/FPGA_Spartan6/PROG_CCLK"
+Ne 133 "/FPGA_Spartan6/PROG_CCLK"
 Po 3739 3739
 $EndPAD
 $PAD
@@ -4750,7 +4750,7 @@ $PAD
 Sh "AB1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -4133 4133
 $EndPAD
 $PAD
@@ -4883,7 +4883,7 @@ $PAD
 Sh "AB20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 136 "/FPGA_Spartan6/PROG_MISO0"
+Ne 135 "/FPGA_Spartan6/PROG_MISO0"
 Po 3346 4133
 $EndPAD
 $PAD
@@ -4897,7 +4897,7 @@ $PAD
 Sh "AB22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 4133 4133
 $EndPAD
 $EndMODULE  FGG484bga-p10
@@ -4919,7 +4919,7 @@ $PAD
 Sh "PAD" R 904 628 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 0 0
 $EndPAD
 $PAD
@@ -4940,7 +4940,7 @@ $PAD
 Sh "2" R 99 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -196 491
 $EndPAD
 $PAD
@@ -4982,7 +4982,7 @@ $PAD
 Sh "5" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 393 491
 $EndPAD
 $PAD
@@ -5017,7 +5017,7 @@ $PAD
 Sh "2" R 157 236 0 0 1350
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -5045,7 +5045,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -5066,14 +5066,14 @@ $PAD
 Sh "1" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 176 "/FPGA_Spartan6/R_M0_UDM"
+Ne 175 "/FPGA_Spartan6/R_M0_UDM"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 92 "/FPGA_Spartan6/M0_UDM"
+Ne 24 "/DDR_Banks/M0_UDM"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -5094,14 +5094,14 @@ $PAD
 Sh "1" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 177 "/FPGA_Spartan6/R_M0_UDQS"
+Ne 176 "/FPGA_Spartan6/R_M0_UDQS"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 93 "/FPGA_Spartan6/M0_UDQS"
+Ne 25 "/DDR_Banks/M0_UDQS"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -5122,7 +5122,7 @@ $PAD
 Sh "1" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 156 "/FPGA_Spartan6/R_M0_CKE"
+Ne 155 "/FPGA_Spartan6/R_M0_CKE"
 Po -176 0
 $EndPAD
 $PAD
@@ -5150,14 +5150,14 @@ $PAD
 Sh "1" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 78 "/FPGA_Spartan6/M0_CLK"
+Ne 16 "/DDR_Banks/M0_CLK"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 79 "/FPGA_Spartan6/M0_CLK#"
+Ne 86 "/FPGA_Spartan6/M0_CLK#"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -5176,56 +5176,56 @@ $PAD
 Sh "1" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 140 "/FPGA_Spartan6/R_M0_A0"
+Ne 139 "/FPGA_Spartan6/R_M0_A0"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 141 "/FPGA_Spartan6/R_M0_A1"
+Ne 140 "/FPGA_Spartan6/R_M0_A1"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 145 "/FPGA_Spartan6/R_M0_A2"
+Ne 144 "/FPGA_Spartan6/R_M0_A2"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 146 "/FPGA_Spartan6/R_M0_A3"
+Ne 145 "/FPGA_Spartan6/R_M0_A3"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 12 "/DDR_Banks/M0_A3"
+Ne 80 "/FPGA_Spartan6/M0_A3"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 70 "/FPGA_Spartan6/M0_A2"
+Ne 79 "/FPGA_Spartan6/M0_A2"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 67 "/FPGA_Spartan6/M0_A1"
+Ne 76 "/FPGA_Spartan6/M0_A1"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 10 "/DDR_Banks/M0_A0"
+Ne 75 "/FPGA_Spartan6/M0_A0"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -5244,56 +5244,56 @@ $PAD
 Sh "1" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 175 "/FPGA_Spartan6/R_M0_RAS#"
+Ne 174 "/FPGA_Spartan6/R_M0_RAS#"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 153 "/FPGA_Spartan6/R_M0_BA0"
+Ne 152 "/FPGA_Spartan6/R_M0_BA0"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 154 "/FPGA_Spartan6/R_M0_BA1"
+Ne 153 "/FPGA_Spartan6/R_M0_BA1"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 142 "/FPGA_Spartan6/R_M0_A10"
+Ne 141 "/FPGA_Spartan6/R_M0_A10"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 68 "/FPGA_Spartan6/M0_A10"
+Ne 77 "/FPGA_Spartan6/M0_A10"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 76 "/FPGA_Spartan6/M0_BA1"
+Ne 84 "/FPGA_Spartan6/M0_BA1"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 75 "/FPGA_Spartan6/M0_BA0"
+Ne 14 "/DDR_Banks/M0_BA0"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 91 "/FPGA_Spartan6/M0_RAS#"
+Ne 23 "/DDR_Banks/M0_RAS#"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -5312,56 +5312,56 @@ $PAD
 Sh "1" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 174 "/FPGA_Spartan6/R_M0_LDQS"
+Ne 173 "/FPGA_Spartan6/R_M0_LDQS"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 173 "/FPGA_Spartan6/R_M0_LDM"
+Ne 172 "/FPGA_Spartan6/R_M0_LDM"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 178 "/FPGA_Spartan6/R_M0_WE#"
+Ne 177 "/FPGA_Spartan6/R_M0_WE#"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 155 "/FPGA_Spartan6/R_M0_CAS#"
+Ne 154 "/FPGA_Spartan6/R_M0_CAS#"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 77 "/FPGA_Spartan6/M0_CAS#"
+Ne 85 "/FPGA_Spartan6/M0_CAS#"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 94 "/FPGA_Spartan6/M0_WE#"
+Ne 27 "/DDR_Banks/M0_WE#"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 21 "/DDR_Banks/M0_LDM"
+Ne 97 "/FPGA_Spartan6/M0_LDM"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 22 "/DDR_Banks/M0_LDQS"
+Ne 98 "/FPGA_Spartan6/M0_LDQS"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -5380,56 +5380,56 @@ $PAD
 Sh "1" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 150 "/FPGA_Spartan6/R_M0_A7"
+Ne 149 "/FPGA_Spartan6/R_M0_A7"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 149 "/FPGA_Spartan6/R_M0_A6"
+Ne 148 "/FPGA_Spartan6/R_M0_A6"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 148 "/FPGA_Spartan6/R_M0_A5"
+Ne 147 "/FPGA_Spartan6/R_M0_A5"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 147 "/FPGA_Spartan6/R_M0_A4"
+Ne 146 "/FPGA_Spartan6/R_M0_A4"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 13 "/DDR_Banks/M0_A4"
+Ne 81 "/FPGA_Spartan6/M0_A4"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 71 "/FPGA_Spartan6/M0_A5"
+Ne 11 "/DDR_Banks/M0_A5"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 72 "/FPGA_Spartan6/M0_A6"
+Ne 12 "/DDR_Banks/M0_A6"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 73 "/FPGA_Spartan6/M0_A7"
+Ne 82 "/FPGA_Spartan6/M0_A7"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -5448,56 +5448,56 @@ $PAD
 Sh "1" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 144 "/FPGA_Spartan6/R_M0_A12"
+Ne 143 "/FPGA_Spartan6/R_M0_A12"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 143 "/FPGA_Spartan6/R_M0_A11"
+Ne 142 "/FPGA_Spartan6/R_M0_A11"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 152 "/FPGA_Spartan6/R_M0_A9"
+Ne 151 "/FPGA_Spartan6/R_M0_A9"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 151 "/FPGA_Spartan6/R_M0_A8"
+Ne 150 "/FPGA_Spartan6/R_M0_A8"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 74 "/FPGA_Spartan6/M0_A8"
+Ne 13 "/DDR_Banks/M0_A8"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 14 "/DDR_Banks/M0_A9"
+Ne 83 "/FPGA_Spartan6/M0_A9"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 11 "/DDR_Banks/M0_A11"
+Ne 78 "/FPGA_Spartan6/M0_A11"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 69 "/FPGA_Spartan6/M0_A12"
+Ne 10 "/DDR_Banks/M0_A12"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -5516,56 +5516,56 @@ $PAD
 Sh "1" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 167 "/FPGA_Spartan6/R_M0_DQ4"
+Ne 166 "/FPGA_Spartan6/R_M0_DQ4"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 168 "/FPGA_Spartan6/R_M0_DQ5"
+Ne 167 "/FPGA_Spartan6/R_M0_DQ5"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 169 "/FPGA_Spartan6/R_M0_DQ6"
+Ne 168 "/FPGA_Spartan6/R_M0_DQ6"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 170 "/FPGA_Spartan6/R_M0_DQ7"
+Ne 169 "/FPGA_Spartan6/R_M0_DQ7"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 20 "/DDR_Banks/M0_DQ7"
+Ne 95 "/FPGA_Spartan6/M0_DQ7"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 88 "/FPGA_Spartan6/M0_DQ6"
+Ne 94 "/FPGA_Spartan6/M0_DQ6"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 19 "/DDR_Banks/M0_DQ5"
+Ne 21 "/DDR_Banks/M0_DQ5"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 18 "/DDR_Banks/M0_DQ4"
+Ne 93 "/FPGA_Spartan6/M0_DQ4"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -5584,56 +5584,56 @@ $PAD
 Sh "1" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 157 "/FPGA_Spartan6/R_M0_DQ0"
+Ne 156 "/FPGA_Spartan6/R_M0_DQ0"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 158 "/FPGA_Spartan6/R_M0_DQ1"
+Ne 157 "/FPGA_Spartan6/R_M0_DQ1"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 165 "/FPGA_Spartan6/R_M0_DQ2"
+Ne 164 "/FPGA_Spartan6/R_M0_DQ2"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 166 "/FPGA_Spartan6/R_M0_DQ3"
+Ne 165 "/FPGA_Spartan6/R_M0_DQ3"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 87 "/FPGA_Spartan6/M0_DQ3"
+Ne 92 "/FPGA_Spartan6/M0_DQ3"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 86 "/FPGA_Spartan6/M0_DQ2"
+Ne 20 "/DDR_Banks/M0_DQ2"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 81 "/FPGA_Spartan6/M0_DQ1"
+Ne 18 "/DDR_Banks/M0_DQ1"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 80 "/FPGA_Spartan6/M0_DQ0"
+Ne 17 "/DDR_Banks/M0_DQ0"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -5652,56 +5652,56 @@ $PAD
 Sh "1" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 171 "/FPGA_Spartan6/R_M0_DQ8"
+Ne 170 "/FPGA_Spartan6/R_M0_DQ8"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 172 "/FPGA_Spartan6/R_M0_DQ9"
+Ne 171 "/FPGA_Spartan6/R_M0_DQ9"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 159 "/FPGA_Spartan6/R_M0_DQ10"
+Ne 158 "/FPGA_Spartan6/R_M0_DQ10"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 160 "/FPGA_Spartan6/R_M0_DQ11"
+Ne 159 "/FPGA_Spartan6/R_M0_DQ11"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 82 "/FPGA_Spartan6/M0_DQ11"
+Ne 88 "/FPGA_Spartan6/M0_DQ11"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 16 "/DDR_Banks/M0_DQ10"
+Ne 87 "/FPGA_Spartan6/M0_DQ10"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 90 "/FPGA_Spartan6/M0_DQ9"
+Ne 96 "/FPGA_Spartan6/M0_DQ9"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 89 "/FPGA_Spartan6/M0_DQ8"
+Ne 22 "/DDR_Banks/M0_DQ8"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -5720,56 +5720,56 @@ $PAD
 Sh "1" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 161 "/FPGA_Spartan6/R_M0_DQ12"
+Ne 160 "/FPGA_Spartan6/R_M0_DQ12"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 162 "/FPGA_Spartan6/R_M0_DQ13"
+Ne 161 "/FPGA_Spartan6/R_M0_DQ13"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 163 "/FPGA_Spartan6/R_M0_DQ14"
+Ne 162 "/FPGA_Spartan6/R_M0_DQ14"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 164 "/FPGA_Spartan6/R_M0_DQ15"
+Ne 163 "/FPGA_Spartan6/R_M0_DQ15"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 85 "/FPGA_Spartan6/M0_DQ15"
+Ne 19 "/DDR_Banks/M0_DQ15"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 17 "/DDR_Banks/M0_DQ14"
+Ne 91 "/FPGA_Spartan6/M0_DQ14"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 84 "/FPGA_Spartan6/M0_DQ13"
+Ne 90 "/FPGA_Spartan6/M0_DQ13"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 83 "/FPGA_Spartan6/M0_DQ12"
+Ne 89 "/FPGA_Spartan6/M0_DQ12"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -5791,28 +5791,28 @@ $PAD
 Sh "PAD" R 433 433 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -235 235
 $EndPAD
 $PAD
 Sh "PAD" R 433 433 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -235 -235
 $EndPAD
 $PAD
 Sh "PAD" R 433 433 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 235 235
 $EndPAD
 $PAD
 Sh "PAD" R 433 433 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 235 -235
 $EndPAD
 $PAD
@@ -5924,7 +5924,7 @@ $PAD
 Sh "8" R 157 98 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 688 0
 $EndPAD
 $PAD
@@ -5973,14 +5973,14 @@ $PAD
 Sh "1" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 216 "/FPGA_Spartan6/R_M1_UDQS"
+Ne 215 "/FPGA_Spartan6/R_M1_UDQS"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 125 "/FPGA_Spartan6/M1_UDQS"
+Ne 42 "/DDR_Banks/M1_UDQS"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -6001,14 +6001,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 195 "/FPGA_Spartan6/R_M1_CS#"
+Ne 194 "/FPGA_Spartan6/R_M1_CS#"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 30 "/DDR_Banks/M1_CS#"
+Ne 110 "/FPGA_Spartan6/M1_CS#"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -6029,14 +6029,14 @@ $PAD
 Sh "1" R 157 236 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 194 "/FPGA_Spartan6/R_M1_CKE"
+Ne 193 "/FPGA_Spartan6/R_M1_CKE"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 106 "/FPGA_Spartan6/M1_CKE"
+Ne 34 "/DDR_Banks/M1_CKE"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -6057,7 +6057,7 @@ $PAD
 Sh "1" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 215 "/FPGA_Spartan6/R_M1_UDM"
+Ne 214 "/FPGA_Spartan6/R_M1_UDM"
 Po -176 0
 $EndPAD
 $PAD
@@ -6083,56 +6083,56 @@ $PAD
 Sh "1" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 114 "/FPGA_Spartan6/M1_DQ15"
+Ne 116 "/FPGA_Spartan6/M1_DQ15"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 113 "/FPGA_Spartan6/M1_DQ14"
+Ne 115 "/FPGA_Spartan6/M1_DQ14"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 112 "/FPGA_Spartan6/M1_DQ13"
+Ne 114 "/FPGA_Spartan6/M1_DQ13"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 111 "/FPGA_Spartan6/M1_DQ12"
+Ne 37 "/DDR_Banks/M1_DQ12"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 200 "/FPGA_Spartan6/R_M1_DQ12"
+Ne 199 "/FPGA_Spartan6/R_M1_DQ12"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 201 "/FPGA_Spartan6/R_M1_DQ13"
+Ne 200 "/FPGA_Spartan6/R_M1_DQ13"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 202 "/FPGA_Spartan6/R_M1_DQ14"
+Ne 201 "/FPGA_Spartan6/R_M1_DQ14"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 203 "/FPGA_Spartan6/R_M1_DQ15"
+Ne 202 "/FPGA_Spartan6/R_M1_DQ15"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -6151,21 +6151,21 @@ $PAD
 Sh "1" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 110 "/FPGA_Spartan6/M1_DQ11"
+Ne 113 "/FPGA_Spartan6/M1_DQ11"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 109 "/FPGA_Spartan6/M1_DQ10"
+Ne 36 "/DDR_Banks/M1_DQ10"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 33 "/DDR_Banks/M1_DQ9"
+Ne 121 "/FPGA_Spartan6/M1_DQ9"
 Po 98 -177
 $EndPAD
 $PAD
@@ -6179,28 +6179,28 @@ $PAD
 Sh "5" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 210 "/FPGA_Spartan6/R_M1_DQ8"
+Ne 209 "/FPGA_Spartan6/R_M1_DQ8"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 211 "/FPGA_Spartan6/R_M1_DQ9"
+Ne 210 "/FPGA_Spartan6/R_M1_DQ9"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 198 "/FPGA_Spartan6/R_M1_DQ10"
+Ne 197 "/FPGA_Spartan6/R_M1_DQ10"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 199 "/FPGA_Spartan6/R_M1_DQ11"
+Ne 198 "/FPGA_Spartan6/R_M1_DQ11"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -6221,14 +6221,14 @@ $PAD
 Sh "1" R 157 236 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 29 "/DDR_Banks/M1_CLK#"
+Ne 109 "/FPGA_Spartan6/M1_CLK#"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 107 "/FPGA_Spartan6/M1_CLK"
+Ne 35 "/DDR_Banks/M1_CLK"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -6247,56 +6247,56 @@ $PAD
 Sh "1" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 97 "/FPGA_Spartan6/M1_A12"
+Ne 29 "/DDR_Banks/M1_A12"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 25 "/DDR_Banks/M1_A11"
+Ne 101 "/FPGA_Spartan6/M1_A11"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 104 "/FPGA_Spartan6/M1_A9"
+Ne 32 "/DDR_Banks/M1_A9"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 103 "/FPGA_Spartan6/M1_A8"
+Ne 31 "/DDR_Banks/M1_A8"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 189 "/FPGA_Spartan6/R_M1_A8"
+Ne 188 "/FPGA_Spartan6/R_M1_A8"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 190 "/FPGA_Spartan6/R_M1_A9"
+Ne 189 "/FPGA_Spartan6/R_M1_A9"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 182 "/FPGA_Spartan6/R_M1_A11"
+Ne 181 "/FPGA_Spartan6/R_M1_A11"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 183 "/FPGA_Spartan6/R_M1_A12"
+Ne 182 "/FPGA_Spartan6/R_M1_A12"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -6315,28 +6315,28 @@ $PAD
 Sh "1" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 102 "/FPGA_Spartan6/M1_A7"
+Ne 106 "/FPGA_Spartan6/M1_A7"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 26 "/DDR_Banks/M1_A6"
+Ne 105 "/FPGA_Spartan6/M1_A6"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 101 "/FPGA_Spartan6/M1_A5"
+Ne 30 "/DDR_Banks/M1_A5"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 100 "/FPGA_Spartan6/M1_A4"
+Ne 104 "/FPGA_Spartan6/M1_A4"
 Po 295 -177
 $EndPAD
 $PAD
@@ -6350,21 +6350,21 @@ $PAD
 Sh "6" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 186 "/FPGA_Spartan6/R_M1_A5"
+Ne 185 "/FPGA_Spartan6/R_M1_A5"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 187 "/FPGA_Spartan6/R_M1_A6"
+Ne 186 "/FPGA_Spartan6/R_M1_A6"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 188 "/FPGA_Spartan6/R_M1_A7"
+Ne 187 "/FPGA_Spartan6/R_M1_A7"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -6383,56 +6383,56 @@ $PAD
 Sh "1" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 196 "/FPGA_Spartan6/R_M1_DQ0"
+Ne 195 "/FPGA_Spartan6/R_M1_DQ0"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 197 "/FPGA_Spartan6/R_M1_DQ1"
+Ne 196 "/FPGA_Spartan6/R_M1_DQ1"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 204 "/FPGA_Spartan6/R_M1_DQ2"
+Ne 203 "/FPGA_Spartan6/R_M1_DQ2"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 205 "/FPGA_Spartan6/R_M1_DQ3"
+Ne 204 "/FPGA_Spartan6/R_M1_DQ3"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 116 "/FPGA_Spartan6/M1_DQ3"
+Ne 38 "/DDR_Banks/M1_DQ3"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 115 "/FPGA_Spartan6/M1_DQ2"
+Ne 117 "/FPGA_Spartan6/M1_DQ2"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 108 "/FPGA_Spartan6/M1_DQ1"
+Ne 112 "/FPGA_Spartan6/M1_DQ1"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 31 "/DDR_Banks/M1_DQ0"
+Ne 111 "/FPGA_Spartan6/M1_DQ0"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -6451,49 +6451,49 @@ $PAD
 Sh "1" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 213 "/FPGA_Spartan6/R_M1_LDQS"
+Ne 212 "/FPGA_Spartan6/R_M1_LDQS"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 212 "/FPGA_Spartan6/R_M1_LDM"
+Ne 211 "/FPGA_Spartan6/R_M1_LDM"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 217 "/FPGA_Spartan6/R_M1_WE#"
+Ne 216 "/FPGA_Spartan6/R_M1_WE#"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 193 "/FPGA_Spartan6/R_M1_CAS#"
+Ne 192 "/FPGA_Spartan6/R_M1_CAS#"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 105 "/FPGA_Spartan6/M1_CAS#"
+Ne 108 "/FPGA_Spartan6/M1_CAS#"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 35 "/DDR_Banks/M1_WE#"
+Ne 125 "/FPGA_Spartan6/M1_WE#"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 121 "/FPGA_Spartan6/M1_LDM"
+Ne 41 "/DDR_Banks/M1_LDM"
 Po -98 177
 $EndPAD
 $PAD
@@ -6519,28 +6519,28 @@ $PAD
 Sh "1" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 206 "/FPGA_Spartan6/R_M1_DQ4"
+Ne 205 "/FPGA_Spartan6/R_M1_DQ4"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 207 "/FPGA_Spartan6/R_M1_DQ5"
+Ne 206 "/FPGA_Spartan6/R_M1_DQ5"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 208 "/FPGA_Spartan6/R_M1_DQ6"
+Ne 207 "/FPGA_Spartan6/R_M1_DQ6"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 209 "/FPGA_Spartan6/R_M1_DQ7"
+Ne 208 "/FPGA_Spartan6/R_M1_DQ7"
 Po 295 -177
 $EndPAD
 $PAD
@@ -6554,21 +6554,21 @@ $PAD
 Sh "6" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 118 "/FPGA_Spartan6/M1_DQ6"
+Ne 40 "/DDR_Banks/M1_DQ6"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 117 "/FPGA_Spartan6/M1_DQ5"
+Ne 39 "/DDR_Banks/M1_DQ5"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 32 "/DDR_Banks/M1_DQ4"
+Ne 118 "/FPGA_Spartan6/M1_DQ4"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -6587,49 +6587,49 @@ $PAD
 Sh "1" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 214 "/FPGA_Spartan6/R_M1_RAS#"
+Ne 213 "/FPGA_Spartan6/R_M1_RAS#"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 191 "/FPGA_Spartan6/R_M1_BA0"
+Ne 190 "/FPGA_Spartan6/R_M1_BA0"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 192 "/FPGA_Spartan6/R_M1_BA1"
+Ne 191 "/FPGA_Spartan6/R_M1_BA1"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 181 "/FPGA_Spartan6/R_M1_A10"
+Ne 180 "/FPGA_Spartan6/R_M1_A10"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 96 "/FPGA_Spartan6/M1_A10"
+Ne 100 "/FPGA_Spartan6/M1_A10"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 28 "/DDR_Banks/M1_BA1"
+Ne 107 "/FPGA_Spartan6/M1_BA1"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 27 "/DDR_Banks/M1_BA0"
+Ne 33 "/DDR_Banks/M1_BA0"
 Po -98 177
 $EndPAD
 $PAD
@@ -6655,56 +6655,56 @@ $PAD
 Sh "1" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 179 "/FPGA_Spartan6/R_M1_A0"
+Ne 178 "/FPGA_Spartan6/R_M1_A0"
 Po -295 -177
 $EndPAD
 $PAD
 Sh "2" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 180 "/FPGA_Spartan6/R_M1_A1"
+Ne 179 "/FPGA_Spartan6/R_M1_A1"
 Po -98 -177
 $EndPAD
 $PAD
 Sh "3" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 184 "/FPGA_Spartan6/R_M1_A2"
+Ne 183 "/FPGA_Spartan6/R_M1_A2"
 Po 98 -177
 $EndPAD
 $PAD
 Sh "4" R 118 157 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 185 "/FPGA_Spartan6/R_M1_A3"
+Ne 184 "/FPGA_Spartan6/R_M1_A3"
 Po 295 -177
 $EndPAD
 $PAD
 Sh "5" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 99 "/FPGA_Spartan6/M1_A3"
+Ne 103 "/FPGA_Spartan6/M1_A3"
 Po 295 177
 $EndPAD
 $PAD
 Sh "6" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 98 "/FPGA_Spartan6/M1_A2"
+Ne 102 "/FPGA_Spartan6/M1_A2"
 Po 98 177
 $EndPAD
 $PAD
 Sh "7" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 24 "/DDR_Banks/M1_A1"
+Ne 99 "/FPGA_Spartan6/M1_A1"
 Po -98 177
 $EndPAD
 $PAD
 Sh "8" R 118 157 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 95 "/FPGA_Spartan6/M1_A0"
+Ne 28 "/DDR_Banks/M1_A0"
 Po -295 177
 $EndPAD
 $EndMODULE  R_PACK4-0402
@@ -6725,7 +6725,7 @@ $PAD
 Sh "1" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -176 0
 $EndPAD
 $PAD
@@ -6753,14 +6753,14 @@ $PAD
 Sh "1" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 36 "/Ethernet_Phy/ETH_A1.8V"
+Ne 44 "/Ethernet_Phy/ETH_A1.8V"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 42 "/Ethernet_Phy/ETH_PLL1.8V"
+Ne 52 "/Ethernet_Phy/ETH_PLL1.8V"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -6788,7 +6788,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 36 "/Ethernet_Phy/ETH_A1.8V"
+Ne 44 "/Ethernet_Phy/ETH_A1.8V"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -6816,7 +6816,7 @@ $PAD
 Sh "2" R 197 354 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -6844,7 +6844,7 @@ $PAD
 Sh "2" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -6872,7 +6872,7 @@ $PAD
 Sh "2" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -6900,7 +6900,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -6928,7 +6928,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -6962,49 +6962,49 @@ $PAD
 Sh "1" R 200 450 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 135 "/FPGA_Spartan6/PROG_CSO"
+Ne 134 "/FPGA_Spartan6/PROG_CSO"
 Po -750 1050
 $EndPAD
 $PAD
 Sh "7" R 200 450 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 139 "/FPGA_Spartan6/PROG_MISO3"
+Ne 138 "/FPGA_Spartan6/PROG_MISO3"
 Po -250 -1050
 $EndPAD
 $PAD
 Sh "6" R 200 450 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 134 "/FPGA_Spartan6/PROG_CCLK"
+Ne 133 "/FPGA_Spartan6/PROG_CCLK"
 Po 250 -1050
 $EndPAD
 $PAD
 Sh "5" R 200 450 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 136 "/FPGA_Spartan6/PROG_MISO0"
+Ne 135 "/FPGA_Spartan6/PROG_MISO0"
 Po 750 -1050
 $EndPAD
 $PAD
 Sh "2" R 200 450 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 137 "/FPGA_Spartan6/PROG_MISO1"
+Ne 136 "/FPGA_Spartan6/PROG_MISO1"
 Po -250 1050
 $EndPAD
 $PAD
 Sh "3" R 200 450 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 138 "/FPGA_Spartan6/PROG_MISO2"
+Ne 137 "/FPGA_Spartan6/PROG_MISO2"
 Po 250 1050
 $EndPAD
 $PAD
 Sh "4" R 200 450 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 750 1050
 $EndPAD
 $SHAPE3D
@@ -7038,7 +7038,7 @@ $PAD
 Sh "2" R 355 668 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 570 0
 $EndPAD
 $EndMODULE  1206
@@ -7066,7 +7066,7 @@ $PAD
 Sh "2" R 157 236 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7094,7 +7094,7 @@ $PAD
 Sh "2" R 355 984 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 570 0
 $EndPAD
 $EndMODULE  1210
@@ -7122,7 +7122,7 @@ $PAD
 Sh "2" R 355 984 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 570 0
 $EndPAD
 $EndMODULE  1210
@@ -7150,7 +7150,7 @@ $PAD
 Sh "2" R 355 984 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 570 0
 $EndPAD
 $EndMODULE  1210
@@ -7178,7 +7178,7 @@ $PAD
 Sh "2" R 355 984 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 570 0
 $EndPAD
 $EndMODULE  1210
@@ -7206,7 +7206,7 @@ $PAD
 Sh "2" R 355 984 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 570 0
 $EndPAD
 $EndMODULE  1210
@@ -7234,7 +7234,7 @@ $PAD
 Sh "2" R 355 984 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 570 0
 $EndPAD
 $EndMODULE  1210
@@ -7262,7 +7262,7 @@ $PAD
 Sh "2" R 275 510 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 373 0
 $EndPAD
 $EndMODULE  0805
@@ -7290,7 +7290,7 @@ $PAD
 Sh "2" R 275 510 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 373 0
 $EndPAD
 $EndMODULE  0805
@@ -7318,7 +7318,7 @@ $PAD
 Sh "2" R 275 510 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 373 0
 $EndPAD
 $EndMODULE  0805
@@ -7346,7 +7346,7 @@ $PAD
 Sh "2" R 275 510 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 373 0
 $EndPAD
 $EndMODULE  0805
@@ -7374,7 +7374,7 @@ $PAD
 Sh "2" R 275 510 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 373 0
 $EndPAD
 $EndMODULE  0805
@@ -7402,7 +7402,7 @@ $PAD
 Sh "2" R 275 510 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 373 0
 $EndPAD
 $EndMODULE  0805
@@ -7430,7 +7430,7 @@ $PAD
 Sh "2" R 275 510 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 373 0
 $EndPAD
 $EndMODULE  0805
@@ -7458,7 +7458,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7486,7 +7486,7 @@ $PAD
 Sh "2" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7514,7 +7514,7 @@ $PAD
 Sh "2" R 157 236 0 0 2250
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7542,7 +7542,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7570,7 +7570,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7598,7 +7598,7 @@ $PAD
 Sh "2" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7626,7 +7626,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7654,7 +7654,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7682,7 +7682,7 @@ $PAD
 Sh "2" R 157 236 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7710,7 +7710,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7738,7 +7738,7 @@ $PAD
 Sh "2" R 157 236 0 0 1350
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7766,7 +7766,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7794,7 +7794,7 @@ $PAD
 Sh "2" R 157 236 0 0 450
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7822,7 +7822,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7850,7 +7850,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7878,7 +7878,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -7906,66 +7906,10 @@ $PAD
 Sh "2" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
-$MODULE 0805
-Po 62236 25969 0 15 4C5FF890 4C6552BE ~~
-Li 0805
-Sc 4C6552BE
-AR /4C5F1EDC/4C6552BE
-Op 0 0 0
-At SMD 
-T0 0 -150 200 200 0 40 N V 25 N"C35"
-T1 0 150 200 200 0 40 N I 25 N"1uF"
-DS -561 305 -561 -305 50 21
-DS -561 -305 561 -305 50 21
-DS 561 -305 561 305 50 21
-DS 561 305 -561 305 50 21
-$PAD
-Sh "1" R 275 510 0 0 0
-Dr 0 0 0
-At SMD N 00888000
-Ne 4 "+3.3V"
-Po -373 0
-$EndPAD
-$PAD
-Sh "2" R 275 510 0 0 0
-Dr 0 0 0
-At SMD N 00888000
-Ne 240 "GND"
-Po 373 0
-$EndPAD
-$EndMODULE  0805
-$MODULE 0805
-Po 63614 25996 0 15 4C5FF890 4C6552BD ~~
-Li 0805
-Sc 4C6552BD
-AR /4C5F1EDC/4C6552BD
-Op 0 0 0
-At SMD 
-T0 0 -150 200 200 0 40 N V 25 N"C36"
-T1 0 150 200 200 0 40 N I 25 N"1uF"
-DS -561 305 -561 -305 50 21
-DS -561 -305 561 -305 50 21
-DS 561 -305 561 305 50 21
-DS 561 305 -561 305 50 21
-$PAD
-Sh "1" R 275 510 0 0 0
-Dr 0 0 0
-At SMD N 00888000
-Ne 4 "+3.3V"
-Po -373 0
-$EndPAD
-$PAD
-Sh "2" R 275 510 0 0 0
-Dr 0 0 0
-At SMD N 00888000
-Ne 240 "GND"
-Po 373 0
-$EndPAD
-$EndMODULE  0805
 $MODULE 0603
 Po 63909 27335 0 15 4C5FF890 4C6552B8 ~~
 Li 0603
@@ -7983,14 +7927,14 @@ $PAD
 Sh "1" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 249 "N-000422"
+Ne 240 "/USB/USBD_D+"
 Po -294 0
 $EndPAD
 $PAD
 Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -8011,42 +7955,42 @@ $PAD
 Sh "1" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 248 "N-000421"
+Ne 241 "/USB/USBD_D-"
 Po -294 0
 $EndPAD
 $PAD
 Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
 $MODULE 0402
-Po 61756 26673 0 15 4C5FF890 4C6552BC ~~
+Po 56575 26291 900 0 4C5FF890 4C6552BC ~~
 Li 0402
 Sc 4C6552BC
 AR /4C5F1EDC/4C6552BC
 Op 0 0 0
 At SMD 
-T0 0 -150 200 200 0 40 N V 25 N"C37"
-T1 0 150 200 200 0 40 N I 25 N"470nF"
-DS -305 168 -305 -168 50 21
-DS -305 -168 305 -168 50 21
-DS 305 -168 305 168 50 21
-DS 305 168 -305 168 50 21
+T0 0 150 200 200 900 40 M V 20 N"C37"
+T1 0 -150 200 200 900 40 M I 20 N"100nF"
+DS -305 -168 -305 168 50 20
+DS -305 168 305 168 50 20
+DS 305 168 305 -168 50 20
+DS 305 -168 -305 -168 50 20
 $PAD
-Sh "1" R 157 236 0 0 0
+Sh "1" R 157 236 0 0 900
 Dr 0 0 0
-At SMD N 00888000
+At SMD N 00440001
 Ne 3 "+2.5V"
 Po -176 0
 $EndPAD
 $PAD
-Sh "2" R 157 236 0 0 0
+Sh "2" R 157 236 0 0 900
 Dr 0 0 0
-At SMD N 00888000
-Ne 240 "GND"
+At SMD N 00440001
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8067,14 +8011,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 256 "N-000430"
+Ne 254 "N-000429"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8095,14 +8039,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 256 "N-000430"
+Ne 254 "N-000429"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8130,7 +8074,7 @@ $PAD
 Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -8151,14 +8095,14 @@ $PAD
 Sh "1" R 197 354 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 254 "N-000427"
+Ne 253 "N-000427"
 Po -294 0
 $EndPAD
 $PAD
 Sh "2" R 197 354 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 252 "N-000425"
+Ne 252 "N-000426"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -8179,14 +8123,14 @@ $PAD
 Sh "1" R 197 354 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 253 "N-000426"
+Ne 256 "N-000432"
 Po -294 0
 $EndPAD
 $PAD
 Sh "2" R 197 354 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -8207,14 +8151,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 34 "/DDR_Banks/M1_VREF"
+Ne 43 "/DDR_Banks/M1_VREF"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8242,7 +8186,7 @@ $PAD
 Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -8270,7 +8214,7 @@ $PAD
 Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -8298,7 +8242,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8326,7 +8270,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8354,7 +8298,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8382,7 +8326,7 @@ $PAD
 Sh "2" R 157 236 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8410,7 +8354,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8438,7 +8382,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8466,7 +8410,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8494,7 +8438,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8522,7 +8466,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8550,7 +8494,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8578,7 +8522,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 34 "/DDR_Banks/M1_VREF"
+Ne 43 "/DDR_Banks/M1_VREF"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8599,14 +8543,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 23 "/DDR_Banks/M0_VREF"
+Ne 26 "/DDR_Banks/M0_VREF"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8634,7 +8578,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 23 "/DDR_Banks/M0_VREF"
+Ne 26 "/DDR_Banks/M0_VREF"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8662,7 +8606,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 34 "/DDR_Banks/M1_VREF"
+Ne 43 "/DDR_Banks/M1_VREF"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8683,14 +8627,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 34 "/DDR_Banks/M1_VREF"
+Ne 43 "/DDR_Banks/M1_VREF"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8711,14 +8655,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 23 "/DDR_Banks/M0_VREF"
+Ne 26 "/DDR_Banks/M0_VREF"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8746,7 +8690,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 23 "/DDR_Banks/M0_VREF"
+Ne 26 "/DDR_Banks/M0_VREF"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -8772,56 +8716,56 @@ $PAD
 Sh "1" R 470 470 0 0 1800
 Dr 360 0 0
 At STD N 0CC0FFFF
-Ne 252 "N-000425"
+Ne 252 "N-000426"
 Po 0 -2362
 $EndPAD
 $PAD
 Sh "2" C 470 470 0 0 1800
 Dr 360 0 0
 At STD N 0CC0FFFF
-Ne 250 "N-000423"
+Ne 237 "/USB/USBA_D-"
 Po 0 -1575
 $EndPAD
 $PAD
 Sh "3" C 470 470 0 0 1800
 Dr 360 0 0
 At STD N 0CC0FFFF
-Ne 251 "N-000424"
+Ne 236 "/USB/USBA_D+"
 Po 0 -787
 $EndPAD
 $PAD
 Sh "3" C 470 470 0 0 1800
 Dr 360 0 0
 At STD N 0CC0FFFF
-Ne 251 "N-000424"
+Ne 236 "/USB/USBA_D+"
 Po 0 0
 $EndPAD
 $PAD
 Sh "S1" C 670 670 0 0 1800
 Dr 532 0 0
 At STD N 0CC0FFFF
-Ne 255 "N-000428"
+Ne 255 "N-000431"
 Po 1077 287
 $EndPAD
 $PAD
 Sh "S2" C 670 670 0 0 1800
 Dr 532 0 0
 At STD N 0CC0FFFF
-Ne 255 "N-000428"
+Ne 255 "N-000431"
 Po -1077 287
 $EndPAD
 $PAD
 Sh "S3" C 670 670 0 0 1800
 Dr 532 0 0
 At STD N 0CC0FFFF
-Ne 255 "N-000428"
+Ne 255 "N-000431"
 Po 1077 -2468
 $EndPAD
 $PAD
 Sh "S4" C 670 670 0 0 1800
 Dr 532 0 0
 At STD N 0CC0FFFF
-Ne 255 "N-000428"
+Ne 255 "N-000431"
 Po -1077 -2468
 $EndPAD
 $EndMODULE  USB-48204
@@ -8842,7 +8786,7 @@ $PAD
 Sh "1" R 355 984 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 254 "N-000427"
+Ne 253 "N-000427"
 Po -570 0
 $EndPAD
 $PAD
@@ -8877,7 +8821,7 @@ $PAD
 Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -8898,98 +8842,42 @@ $PAD
 Sh "1" R 197 354 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 37 "/Ethernet_Phy/ETH_A3.3V"
+Ne 45 "/Ethernet_Phy/ETH_A3.3V"
 Po -294 0
 $EndPAD
 $PAD
 Sh "2" R 197 354 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
 $MODULE 0603
-Po 55500 26343 1800 0 4C5FF890 4C5F2033 ~~
+Po 55165 25685 0 0 4C5FF890 4C5F2033 ~~
 Li 0603
 Sc 4C5F2033
 AR /4C5F1EDC/4C5F2033
 Op 0 0 0
 At SMD 
-T0 0 150 200 200 1800 40 M V 20 N"C13"
-T1 0 -150 200 200 1800 40 M I 20 N"1uF"
+T0 0 150 200 200 0 40 M V 20 N"C13"
+T1 0 -150 200 200 0 40 M I 20 N"1uF"
 DS -443 -227 -443 227 50 20
 DS -443 227 443 227 50 20
 DS 443 227 443 -227 50 20
 DS 443 -227 -443 -227 50 20
 $PAD
-Sh "1" R 197 354 0 0 1800
+Sh "1" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00440001
 Ne 4 "+3.3V"
 Po -294 0
 $EndPAD
 $PAD
-Sh "2" R 197 354 0 0 1800
+Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
-Po 294 0
-$EndPAD
-$EndMODULE  0603
-$MODULE 0603
-Po 55484 25740 1800 0 4C5FF890 4C5F2037 ~~
-Li 0603
-Sc 4C5F2037
-AR /4C5F1EDC/4C5F2037
-Op 0 0 0
-At SMD 
-T0 0 150 200 200 1800 40 M V 20 N"C14"
-T1 0 -150 200 200 1800 40 M I 20 N"1uF"
-DS -443 -227 -443 227 50 20
-DS -443 227 443 227 50 20
-DS 443 227 443 -227 50 20
-DS 443 -227 -443 -227 50 20
-$PAD
-Sh "1" R 197 354 0 0 1800
-Dr 0 0 0
-At SMD N 00440001
-Ne 4 "+3.3V"
-Po -294 0
-$EndPAD
-$PAD
-Sh "2" R 197 354 0 0 1800
-Dr 0 0 0
-At SMD N 00440001
-Ne 240 "GND"
-Po 294 0
-$EndPAD
-$EndMODULE  0603
-$MODULE 0603
-Po 56791 25996 1800 0 4C5FF890 4C5F2039 ~~
-Li 0603
-Sc 4C5F2039
-AR /4C5F1EDC/4C5F2039
-Op 0 0 0
-At SMD 
-T0 0 150 200 200 1800 40 M V 20 N"C15"
-T1 0 -150 200 200 1800 40 M I 20 N"470nF"
-DS -443 -227 -443 227 50 20
-DS -443 227 443 227 50 20
-DS 443 227 443 -227 50 20
-DS 443 -227 -443 -227 50 20
-$PAD
-Sh "1" R 197 354 0 0 1800
-Dr 0 0 0
-At SMD N 00440001
-Ne 3 "+2.5V"
-Po -294 0
-$EndPAD
-$PAD
-Sh "2" R 197 354 0 0 1800
-Dr 0 0 0
-At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -9010,14 +8898,14 @@ $PAD
 Sh "1" R 197 354 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 251 "N-000424"
+Ne 236 "/USB/USBA_D+"
 Po -294 0
 $EndPAD
 $PAD
 Sh "2" R 197 354 0 0 2700
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -9038,14 +8926,14 @@ $PAD
 Sh "1" R 197 354 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 250 "N-000423"
+Ne 237 "/USB/USBA_D-"
 Po -294 0
 $EndPAD
 $PAD
 Sh "2" R 197 354 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -9073,7 +8961,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9101,7 +8989,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9129,7 +9017,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9157,7 +9045,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9178,14 +9066,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 36 "/Ethernet_Phy/ETH_A1.8V"
+Ne 44 "/Ethernet_Phy/ETH_A1.8V"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9206,14 +9094,14 @@ $PAD
 Sh "1" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 37 "/Ethernet_Phy/ETH_A3.3V"
+Ne 45 "/Ethernet_Phy/ETH_A3.3V"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9234,14 +9122,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 42 "/Ethernet_Phy/ETH_PLL1.8V"
+Ne 52 "/Ethernet_Phy/ETH_PLL1.8V"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9269,7 +9157,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9297,7 +9185,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9318,14 +9206,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 50 "/Ethernet_Phy/MAG_SHIELD"
+Ne 60 "/Ethernet_Phy/MAG_SHIELD"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9346,14 +9234,14 @@ $PAD
 Sh "1" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 255 "N-000428"
+Ne 255 "N-000431"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9374,7 +9262,7 @@ $PAD
 Sh "1" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 41 "/Ethernet_Phy/ETH_MDIO"
+Ne 51 "/Ethernet_Phy/ETH_MDIO"
 Po -176 0
 $EndPAD
 $PAD
@@ -9402,14 +9290,14 @@ $PAD
 Sh "1" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 243 "N-000401"
+Ne 247 "N-000400"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9437,7 +9325,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 51 "/Ethernet_Phy/MAG_TX+"
+Ne 61 "/Ethernet_Phy/MAG_TX+"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9465,7 +9353,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 52 "/Ethernet_Phy/MAG_TX-"
+Ne 62 "/Ethernet_Phy/MAG_TX-"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9493,7 +9381,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 48 "/Ethernet_Phy/MAG_RX+"
+Ne 58 "/Ethernet_Phy/MAG_RX+"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9521,7 +9409,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 49 "/Ethernet_Phy/MAG_RX-"
+Ne 59 "/Ethernet_Phy/MAG_RX-"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9542,14 +9430,14 @@ $PAD
 Sh "1" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 244 "N-000405"
+Ne 248 "N-000404"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 39 "/Ethernet_Phy/ETH_LED0"
+Ne 49 "/Ethernet_Phy/ETH_LED0"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9570,14 +9458,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 245 "N-000406"
+Ne 249 "N-000405"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 40 "/Ethernet_Phy/ETH_LED1"
+Ne 50 "/Ethernet_Phy/ETH_LED1"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9598,14 +9486,14 @@ $PAD
 Sh "1" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 50 "/Ethernet_Phy/MAG_SHIELD"
+Ne 60 "/Ethernet_Phy/MAG_SHIELD"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9626,14 +9514,14 @@ $PAD
 Sh "1" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 255 "N-000428"
+Ne 255 "N-000431"
 Po -176 0
 $EndPAD
 $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -9662,7 +9550,7 @@ $PAD
 Sh "2" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 80 "/FPGA_Spartan6/M0_DQ0"
+Ne 17 "/DDR_Banks/M0_DQ0"
 Po -3838 2176
 $EndPAD
 $PAD
@@ -9676,35 +9564,35 @@ $PAD
 Sh "4" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 81 "/FPGA_Spartan6/M0_DQ1"
+Ne 18 "/DDR_Banks/M0_DQ1"
 Po -3326 2176
 $EndPAD
 $PAD
 Sh "5" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 86 "/FPGA_Spartan6/M0_DQ2"
+Ne 20 "/DDR_Banks/M0_DQ2"
 Po -3070 2176
 $EndPAD
 $PAD
 Sh "6" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2814 2176
 $EndPAD
 $PAD
 Sh "7" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 87 "/FPGA_Spartan6/M0_DQ3"
+Ne 92 "/FPGA_Spartan6/M0_DQ3"
 Po -2558 2176
 $EndPAD
 $PAD
 Sh "8" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 18 "/DDR_Banks/M0_DQ4"
+Ne 93 "/FPGA_Spartan6/M0_DQ4"
 Po -2303 2176
 $EndPAD
 $PAD
@@ -9718,28 +9606,28 @@ $PAD
 Sh "10" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 19 "/DDR_Banks/M0_DQ5"
+Ne 21 "/DDR_Banks/M0_DQ5"
 Po -1791 2176
 $EndPAD
 $PAD
 Sh "11" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 88 "/FPGA_Spartan6/M0_DQ6"
+Ne 94 "/FPGA_Spartan6/M0_DQ6"
 Po -1535 2176
 $EndPAD
 $PAD
 Sh "12" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -1279 2176
 $EndPAD
 $PAD
 Sh "13" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 20 "/DDR_Banks/M0_DQ7"
+Ne 95 "/FPGA_Spartan6/M0_DQ7"
 Po -1023 2176
 $EndPAD
 $PAD
@@ -9760,7 +9648,7 @@ $PAD
 Sh "16" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 22 "/DDR_Banks/M0_LDQS"
+Ne 98 "/FPGA_Spartan6/M0_LDQS"
 Po -255 2176
 $EndPAD
 $PAD
@@ -9788,35 +9676,35 @@ $PAD
 Sh "20" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 21 "/DDR_Banks/M0_LDM"
+Ne 97 "/FPGA_Spartan6/M0_LDM"
 Po 767 2176
 $EndPAD
 $PAD
 Sh "21" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 94 "/FPGA_Spartan6/M0_WE#"
+Ne 27 "/DDR_Banks/M0_WE#"
 Po 1023 2176
 $EndPAD
 $PAD
 Sh "22" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 77 "/FPGA_Spartan6/M0_CAS#"
+Ne 85 "/FPGA_Spartan6/M0_CAS#"
 Po 1279 2176
 $EndPAD
 $PAD
 Sh "23" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 91 "/FPGA_Spartan6/M0_RAS#"
+Ne 23 "/DDR_Banks/M0_RAS#"
 Po 1535 2176
 $EndPAD
 $PAD
 Sh "24" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 1791 2176
 $EndPAD
 $PAD
@@ -9830,49 +9718,49 @@ $PAD
 Sh "26" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 75 "/FPGA_Spartan6/M0_BA0"
+Ne 14 "/DDR_Banks/M0_BA0"
 Po 2302 2176
 $EndPAD
 $PAD
 Sh "27" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 76 "/FPGA_Spartan6/M0_BA1"
+Ne 84 "/FPGA_Spartan6/M0_BA1"
 Po 2558 2176
 $EndPAD
 $PAD
 Sh "28" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 68 "/FPGA_Spartan6/M0_A10"
+Ne 77 "/FPGA_Spartan6/M0_A10"
 Po 2814 2176
 $EndPAD
 $PAD
 Sh "29" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 10 "/DDR_Banks/M0_A0"
+Ne 75 "/FPGA_Spartan6/M0_A0"
 Po 3070 2176
 $EndPAD
 $PAD
 Sh "30" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 67 "/FPGA_Spartan6/M0_A1"
+Ne 76 "/FPGA_Spartan6/M0_A1"
 Po 3326 2176
 $EndPAD
 $PAD
 Sh "31" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 70 "/FPGA_Spartan6/M0_A2"
+Ne 79 "/FPGA_Spartan6/M0_A2"
 Po 3582 2176
 $EndPAD
 $PAD
 Sh "32" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 12 "/DDR_Banks/M0_A3"
+Ne 80 "/FPGA_Spartan6/M0_A3"
 Po 3838 2176
 $EndPAD
 $PAD
@@ -9886,63 +9774,63 @@ $PAD
 Sh "34" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 4094 -2176
 $EndPAD
 $PAD
 Sh "35" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 13 "/DDR_Banks/M0_A4"
+Ne 81 "/FPGA_Spartan6/M0_A4"
 Po 3838 -2176
 $EndPAD
 $PAD
 Sh "36" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 71 "/FPGA_Spartan6/M0_A5"
+Ne 11 "/DDR_Banks/M0_A5"
 Po 3582 -2176
 $EndPAD
 $PAD
 Sh "37" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 72 "/FPGA_Spartan6/M0_A6"
+Ne 12 "/DDR_Banks/M0_A6"
 Po 3326 -2176
 $EndPAD
 $PAD
 Sh "38" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 73 "/FPGA_Spartan6/M0_A7"
+Ne 82 "/FPGA_Spartan6/M0_A7"
 Po 3070 -2176
 $EndPAD
 $PAD
 Sh "39" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 74 "/FPGA_Spartan6/M0_A8"
+Ne 13 "/DDR_Banks/M0_A8"
 Po 2814 -2176
 $EndPAD
 $PAD
 Sh "40" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 14 "/DDR_Banks/M0_A9"
+Ne 83 "/FPGA_Spartan6/M0_A9"
 Po 2558 -2176
 $EndPAD
 $PAD
 Sh "41" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 11 "/DDR_Banks/M0_A11"
+Ne 78 "/FPGA_Spartan6/M0_A11"
 Po 2303 -2176
 $EndPAD
 $PAD
 Sh "42" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 69 "/FPGA_Spartan6/M0_A12"
+Ne 10 "/DDR_Banks/M0_A12"
 Po 2047 -2176
 $EndPAD
 $PAD
@@ -9956,7 +9844,7 @@ $PAD
 Sh "44" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 79 "/FPGA_Spartan6/M0_CLK#"
+Ne 86 "/FPGA_Spartan6/M0_CLK#"
 Po 1535 -2176
 $EndPAD
 $PAD
@@ -9970,28 +9858,28 @@ $PAD
 Sh "46" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 78 "/FPGA_Spartan6/M0_CLK"
+Ne 16 "/DDR_Banks/M0_CLK"
 Po 1023 -2176
 $EndPAD
 $PAD
 Sh "47" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 92 "/FPGA_Spartan6/M0_UDM"
+Ne 24 "/DDR_Banks/M0_UDM"
 Po 767 -2176
 $EndPAD
 $PAD
 Sh "48" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 511 -2176
 $EndPAD
 $PAD
 Sh "49" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 23 "/DDR_Banks/M0_VREF"
+Ne 26 "/DDR_Banks/M0_VREF"
 Po 255 -2176
 $EndPAD
 $PAD
@@ -10005,14 +9893,14 @@ $PAD
 Sh "51" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 93 "/FPGA_Spartan6/M0_UDQS"
+Ne 25 "/DDR_Banks/M0_UDQS"
 Po -255 -2176
 $EndPAD
 $PAD
 Sh "52" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -511 -2176
 $EndPAD
 $PAD
@@ -10026,7 +9914,7 @@ $PAD
 Sh "54" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 89 "/FPGA_Spartan6/M0_DQ8"
+Ne 22 "/DDR_Banks/M0_DQ8"
 Po -1023 -2176
 $EndPAD
 $PAD
@@ -10040,35 +9928,35 @@ $PAD
 Sh "56" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 90 "/FPGA_Spartan6/M0_DQ9"
+Ne 96 "/FPGA_Spartan6/M0_DQ9"
 Po -1535 -2176
 $EndPAD
 $PAD
 Sh "57" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 16 "/DDR_Banks/M0_DQ10"
+Ne 87 "/FPGA_Spartan6/M0_DQ10"
 Po -1791 -2176
 $EndPAD
 $PAD
 Sh "58" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2047 -2176
 $EndPAD
 $PAD
 Sh "59" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 82 "/FPGA_Spartan6/M0_DQ11"
+Ne 88 "/FPGA_Spartan6/M0_DQ11"
 Po -2303 -2176
 $EndPAD
 $PAD
 Sh "60" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 83 "/FPGA_Spartan6/M0_DQ12"
+Ne 89 "/FPGA_Spartan6/M0_DQ12"
 Po -2558 -2176
 $EndPAD
 $PAD
@@ -10082,35 +9970,35 @@ $PAD
 Sh "62" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 84 "/FPGA_Spartan6/M0_DQ13"
+Ne 90 "/FPGA_Spartan6/M0_DQ13"
 Po -3070 -2176
 $EndPAD
 $PAD
 Sh "63" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 17 "/DDR_Banks/M0_DQ14"
+Ne 91 "/FPGA_Spartan6/M0_DQ14"
 Po -3326 -2176
 $EndPAD
 $PAD
 Sh "64" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -3582 -2176
 $EndPAD
 $PAD
 Sh "65" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 85 "/FPGA_Spartan6/M0_DQ15"
+Ne 19 "/DDR_Banks/M0_DQ15"
 Po -3838 -2176
 $EndPAD
 $PAD
 Sh "66" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -4094 -2176
 $EndPAD
 $EndMODULE  TSOP-66
@@ -10139,7 +10027,7 @@ $PAD
 Sh "2" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 31 "/DDR_Banks/M1_DQ0"
+Ne 111 "/FPGA_Spartan6/M1_DQ0"
 Po -3838 2176
 $EndPAD
 $PAD
@@ -10153,35 +10041,35 @@ $PAD
 Sh "4" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 108 "/FPGA_Spartan6/M1_DQ1"
+Ne 112 "/FPGA_Spartan6/M1_DQ1"
 Po -3326 2176
 $EndPAD
 $PAD
 Sh "5" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 115 "/FPGA_Spartan6/M1_DQ2"
+Ne 117 "/FPGA_Spartan6/M1_DQ2"
 Po -3070 2176
 $EndPAD
 $PAD
 Sh "6" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2814 2176
 $EndPAD
 $PAD
 Sh "7" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 116 "/FPGA_Spartan6/M1_DQ3"
+Ne 38 "/DDR_Banks/M1_DQ3"
 Po -2558 2176
 $EndPAD
 $PAD
 Sh "8" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 32 "/DDR_Banks/M1_DQ4"
+Ne 118 "/FPGA_Spartan6/M1_DQ4"
 Po -2303 2176
 $EndPAD
 $PAD
@@ -10195,21 +10083,21 @@ $PAD
 Sh "10" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 117 "/FPGA_Spartan6/M1_DQ5"
+Ne 39 "/DDR_Banks/M1_DQ5"
 Po -1791 2176
 $EndPAD
 $PAD
 Sh "11" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 118 "/FPGA_Spartan6/M1_DQ6"
+Ne 40 "/DDR_Banks/M1_DQ6"
 Po -1535 2176
 $EndPAD
 $PAD
 Sh "12" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -1279 2176
 $EndPAD
 $PAD
@@ -10265,21 +10153,21 @@ $PAD
 Sh "20" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 121 "/FPGA_Spartan6/M1_LDM"
+Ne 41 "/DDR_Banks/M1_LDM"
 Po 767 2176
 $EndPAD
 $PAD
 Sh "21" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 35 "/DDR_Banks/M1_WE#"
+Ne 125 "/FPGA_Spartan6/M1_WE#"
 Po 1023 2176
 $EndPAD
 $PAD
 Sh "22" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 105 "/FPGA_Spartan6/M1_CAS#"
+Ne 108 "/FPGA_Spartan6/M1_CAS#"
 Po 1279 2176
 $EndPAD
 $PAD
@@ -10293,7 +10181,7 @@ $PAD
 Sh "24" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 30 "/DDR_Banks/M1_CS#"
+Ne 110 "/FPGA_Spartan6/M1_CS#"
 Po 1791 2176
 $EndPAD
 $PAD
@@ -10307,49 +10195,49 @@ $PAD
 Sh "26" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 27 "/DDR_Banks/M1_BA0"
+Ne 33 "/DDR_Banks/M1_BA0"
 Po 2302 2176
 $EndPAD
 $PAD
 Sh "27" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 28 "/DDR_Banks/M1_BA1"
+Ne 107 "/FPGA_Spartan6/M1_BA1"
 Po 2558 2176
 $EndPAD
 $PAD
 Sh "28" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 96 "/FPGA_Spartan6/M1_A10"
+Ne 100 "/FPGA_Spartan6/M1_A10"
 Po 2814 2176
 $EndPAD
 $PAD
 Sh "29" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 95 "/FPGA_Spartan6/M1_A0"
+Ne 28 "/DDR_Banks/M1_A0"
 Po 3070 2176
 $EndPAD
 $PAD
 Sh "30" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 24 "/DDR_Banks/M1_A1"
+Ne 99 "/FPGA_Spartan6/M1_A1"
 Po 3326 2176
 $EndPAD
 $PAD
 Sh "31" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 98 "/FPGA_Spartan6/M1_A2"
+Ne 102 "/FPGA_Spartan6/M1_A2"
 Po 3582 2176
 $EndPAD
 $PAD
 Sh "32" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 99 "/FPGA_Spartan6/M1_A3"
+Ne 103 "/FPGA_Spartan6/M1_A3"
 Po 3838 2176
 $EndPAD
 $PAD
@@ -10363,63 +10251,63 @@ $PAD
 Sh "34" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 4094 -2176
 $EndPAD
 $PAD
 Sh "35" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 100 "/FPGA_Spartan6/M1_A4"
+Ne 104 "/FPGA_Spartan6/M1_A4"
 Po 3838 -2176
 $EndPAD
 $PAD
 Sh "36" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 101 "/FPGA_Spartan6/M1_A5"
+Ne 30 "/DDR_Banks/M1_A5"
 Po 3582 -2176
 $EndPAD
 $PAD
 Sh "37" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 26 "/DDR_Banks/M1_A6"
+Ne 105 "/FPGA_Spartan6/M1_A6"
 Po 3326 -2176
 $EndPAD
 $PAD
 Sh "38" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 102 "/FPGA_Spartan6/M1_A7"
+Ne 106 "/FPGA_Spartan6/M1_A7"
 Po 3070 -2176
 $EndPAD
 $PAD
 Sh "39" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 103 "/FPGA_Spartan6/M1_A8"
+Ne 31 "/DDR_Banks/M1_A8"
 Po 2814 -2176
 $EndPAD
 $PAD
 Sh "40" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 104 "/FPGA_Spartan6/M1_A9"
+Ne 32 "/DDR_Banks/M1_A9"
 Po 2558 -2176
 $EndPAD
 $PAD
 Sh "41" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 25 "/DDR_Banks/M1_A11"
+Ne 101 "/FPGA_Spartan6/M1_A11"
 Po 2303 -2176
 $EndPAD
 $PAD
 Sh "42" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 97 "/FPGA_Spartan6/M1_A12"
+Ne 29 "/DDR_Banks/M1_A12"
 Po 2047 -2176
 $EndPAD
 $PAD
@@ -10433,21 +10321,21 @@ $PAD
 Sh "44" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 29 "/DDR_Banks/M1_CLK#"
+Ne 109 "/FPGA_Spartan6/M1_CLK#"
 Po 1535 -2176
 $EndPAD
 $PAD
 Sh "45" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 106 "/FPGA_Spartan6/M1_CKE"
+Ne 34 "/DDR_Banks/M1_CKE"
 Po 1279 -2176
 $EndPAD
 $PAD
 Sh "46" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 107 "/FPGA_Spartan6/M1_CLK"
+Ne 35 "/DDR_Banks/M1_CLK"
 Po 1023 -2176
 $EndPAD
 $PAD
@@ -10461,14 +10349,14 @@ $PAD
 Sh "48" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 511 -2176
 $EndPAD
 $PAD
 Sh "49" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 34 "/DDR_Banks/M1_VREF"
+Ne 43 "/DDR_Banks/M1_VREF"
 Po 255 -2176
 $EndPAD
 $PAD
@@ -10482,14 +10370,14 @@ $PAD
 Sh "51" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 125 "/FPGA_Spartan6/M1_UDQS"
+Ne 42 "/DDR_Banks/M1_UDQS"
 Po -255 -2176
 $EndPAD
 $PAD
 Sh "52" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -511 -2176
 $EndPAD
 $PAD
@@ -10517,35 +10405,35 @@ $PAD
 Sh "56" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 33 "/DDR_Banks/M1_DQ9"
+Ne 121 "/FPGA_Spartan6/M1_DQ9"
 Po -1535 -2176
 $EndPAD
 $PAD
 Sh "57" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 109 "/FPGA_Spartan6/M1_DQ10"
+Ne 36 "/DDR_Banks/M1_DQ10"
 Po -1791 -2176
 $EndPAD
 $PAD
 Sh "58" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2047 -2176
 $EndPAD
 $PAD
 Sh "59" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 110 "/FPGA_Spartan6/M1_DQ11"
+Ne 113 "/FPGA_Spartan6/M1_DQ11"
 Po -2303 -2176
 $EndPAD
 $PAD
 Sh "60" R 137 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 111 "/FPGA_Spartan6/M1_DQ12"
+Ne 37 "/DDR_Banks/M1_DQ12"
 Po -2558 -2176
 $EndPAD
 $PAD
@@ -10559,35 +10447,35 @@ $PAD
 Sh "62" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 112 "/FPGA_Spartan6/M1_DQ13"
+Ne 114 "/FPGA_Spartan6/M1_DQ13"
 Po -3070 -2176
 $EndPAD
 $PAD
 Sh "63" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 113 "/FPGA_Spartan6/M1_DQ14"
+Ne 115 "/FPGA_Spartan6/M1_DQ14"
 Po -3326 -2176
 $EndPAD
 $PAD
 Sh "64" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -3582 -2176
 $EndPAD
 $PAD
 Sh "65" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 114 "/FPGA_Spartan6/M1_DQ15"
+Ne 116 "/FPGA_Spartan6/M1_DQ15"
 Po -3838 -2176
 $EndPAD
 $PAD
 Sh "66" R 138 275 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -4094 -2176
 $EndPAD
 $EndMODULE  TSOP-66
@@ -10607,35 +10495,35 @@ $PAD
 Sh "13" C 1646 1646 0 0 1800
 Dr 1252 0 0
 At STD N 0CC0FFFF
-Ne 50 "/Ethernet_Phy/MAG_SHIELD"
+Ne 60 "/Ethernet_Phy/MAG_SHIELD"
 Po 2250 0
 $EndPAD
 $PAD
 Sh "13" C 984 984 0 0 1800
 Dr 640 0 0
 At STD N 0CC0FFFF
-Ne 50 "/Ethernet_Phy/MAG_SHIELD"
+Ne 60 "/Ethernet_Phy/MAG_SHIELD"
 Po 3100 -1200
 $EndPAD
 $PAD
 Sh "14" C 1646 1646 0 0 1800
 Dr 1252 0 0
 At STD N 0CC0FFFF
-Ne 50 "/Ethernet_Phy/MAG_SHIELD"
+Ne 60 "/Ethernet_Phy/MAG_SHIELD"
 Po -2250 0
 $EndPAD
 $PAD
 Sh "14" C 984 984 0 0 1800
 Dr 640 0 0
 At STD N 0CC0FFFF
-Ne 50 "/Ethernet_Phy/MAG_SHIELD"
+Ne 60 "/Ethernet_Phy/MAG_SHIELD"
 Po -3100 -1200
 $EndPAD
 $PAD
 Sh "1" R 540 540 0 0 1800
 Dr 350 0 0
 At STD N 0CC0FFFF
-Ne 51 "/Ethernet_Phy/MAG_TX+"
+Ne 61 "/Ethernet_Phy/MAG_TX+"
 Po -1750 -2500
 $EndPAD
 $PAD
@@ -10649,28 +10537,28 @@ $PAD
 Sh "5" C 540 540 0 0 1800
 Dr 350 0 0
 At STD N 0CC0FFFF
-Ne 240 "GND"
+Ne 244 "GND"
 Po 250 -2500
 $EndPAD
 $PAD
 Sh "7" C 540 540 0 0 1800
 Dr 350 0 0
 At STD N 0CC0FFFF
-Ne 48 "/Ethernet_Phy/MAG_RX+"
+Ne 58 "/Ethernet_Phy/MAG_RX+"
 Po 1250 -2500
 $EndPAD
 $PAD
 Sh "2" C 540 540 0 0 1800
 Dr 350 0 0
 At STD N 0CC0FFFF
-Ne 52 "/Ethernet_Phy/MAG_TX-"
+Ne 62 "/Ethernet_Phy/MAG_TX-"
 Po -1250 -3500
 $EndPAD
 $PAD
 Sh "4" C 540 540 0 0 1800
 Dr 350 0 0
 At STD N 0CC0FFFF
-Ne 240 "GND"
+Ne 244 "GND"
 Po -250 -3500
 $EndPAD
 $PAD
@@ -10684,7 +10572,7 @@ $PAD
 Sh "8" C 540 540 0 0 1800
 Dr 350 0 0
 At STD N 0CC0FFFF
-Ne 49 "/Ethernet_Phy/MAG_RX-"
+Ne 59 "/Ethernet_Phy/MAG_RX-"
 Po 1750 -3500
 $EndPAD
 $PAD
@@ -10698,7 +10586,7 @@ $PAD
 Sh "10" C 540 540 0 0 1800
 Dr 350 0 0
 At STD N 0CC0FFFF
-Ne 244 "N-000405"
+Ne 248 "N-000404"
 Po -1150 -5400
 $EndPAD
 $PAD
@@ -10712,7 +10600,7 @@ $PAD
 Sh "12" C 540 540 0 0 1800
 Dr 350 0 0
 At STD N 0CC0FFFF
-Ne 245 "N-000406"
+Ne 249 "N-000405"
 Po 2150 -5400
 $EndPAD
 $EndMODULE  SD-48025
@@ -10737,21 +10625,21 @@ $PAD
 Sh "1" R 315 590 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 221 "/FPGA_Spartan6/SD_DAT2"
+Ne 219 "/FPGA_Spartan6/SD_DAT2"
 Po -1299 0
 $EndPAD
 $PAD
 Sh "2" R 315 590 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 222 "/FPGA_Spartan6/SD_DAT3"
+Ne 220 "/FPGA_Spartan6/SD_DAT3"
 Po -866 0
 $EndPAD
 $PAD
 Sh "3" R 315 590 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 234 "/Non_volatile_memories/SD_CMD"
+Ne 218 "/FPGA_Spartan6/SD_CMD"
 Po -433 0
 $EndPAD
 $PAD
@@ -10765,56 +10653,56 @@ $PAD
 Sh "5" R 315 590 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 218 "/FPGA_Spartan6/SD_CLK"
+Ne 217 "/FPGA_Spartan6/SD_CLK"
 Po 433 0
 $EndPAD
 $PAD
 Sh "6" R 315 590 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 866 0
 $EndPAD
 $PAD
 Sh "7" R 315 590 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 219 "/FPGA_Spartan6/SD_DAT0"
+Ne 234 "/Non_volatile_memories/SD_DAT0"
 Po 1299 0
 $EndPAD
 $PAD
 Sh "8" R 315 590 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 220 "/FPGA_Spartan6/SD_DAT1"
+Ne 235 "/Non_volatile_memories/SD_DAT1"
 Po 1732 0
 $EndPAD
 $PAD
 Sh "CASE" R 571 787 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 2707 1024
 $EndPAD
 $PAD
 Sh "CASE" R 571 787 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2707 1024
 $EndPAD
 $PAD
 Sh "CASE" R 571 787 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po -2707 -2244
 $EndPAD
 $PAD
 Sh "CASE" R 571 787 0 0 0
 Dr 0 0 0
 At STD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 2707 -2244
 $EndPAD
 $EndMODULE  MICROSD-500901
@@ -11092,14 +10980,14 @@ $PAD
 Sh "8" R 100 600 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 133 "/FPGA_Spartan6/NF_RE_N"
+Ne 231 "/Non_volatile_memories/NF_RE_N"
 Po -890 3850
 $EndPAD
 $PAD
 Sh "9" R 100 600 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 229 "/Non_volatile_memories/NF_CS1_N"
+Ne 228 "/Non_volatile_memories/NF_CS1_N"
 Po -690 3850
 $EndPAD
 $PAD
@@ -11127,7 +11015,7 @@ $PAD
 Sh "13" R 100 600 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 100 3850
 $EndPAD
 $PAD
@@ -11148,7 +11036,7 @@ $PAD
 Sh "16" R 100 600 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 228 "/Non_volatile_memories/NF_CLE"
+Ne 227 "/Non_volatile_memories/NF_CLE"
 Po 690 3850
 $EndPAD
 $PAD
@@ -11253,14 +11141,14 @@ $PAD
 Sh "31" R 100 600 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 230 "/Non_volatile_memories/NF_D2"
+Ne 229 "/Non_volatile_memories/NF_D2"
 Po 1080 -3850
 $EndPAD
 $PAD
 Sh "32" R 100 600 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 231 "/Non_volatile_memories/NF_D3"
+Ne 129 "/FPGA_Spartan6/NF_D3"
 Po 880 -3850
 $EndPAD
 $PAD
@@ -11288,7 +11176,7 @@ $PAD
 Sh "36" R 100 600 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 100 -3850
 $EndPAD
 $PAD
@@ -11323,14 +11211,14 @@ $PAD
 Sh "41" R 100 600 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 129 "/FPGA_Spartan6/NF_D4"
+Ne 130 "/FPGA_Spartan6/NF_D4"
 Po -890 -3850
 $EndPAD
 $PAD
 Sh "42" R 100 600 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 130 "/FPGA_Spartan6/NF_D5"
+Ne 230 "/Non_volatile_memories/NF_D5"
 Po -1090 -3850
 $EndPAD
 $PAD
@@ -11394,35 +11282,35 @@ $PAD
 Sh "12" R 315 98 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -1613 1082
 $EndPAD
 $PAD
 Sh "11" R 315 99 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 45 "/Ethernet_Phy/ETH_RXER"
+Ne 70 "/FPGA_Spartan6/ETH_RXER"
 Po -1613 885
 $EndPAD
 $PAD
 Sh "10" R 315 99 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "/FPGA_Spartan6/ETH_RXC"
+Ne 66 "/FPGA_Spartan6/ETH_RXC"
 Po -1613 688
 $EndPAD
 $PAD
 Sh "9" R 315 99 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 61 "/FPGA_Spartan6/ETH_RXDV"
+Ne 69 "/FPGA_Spartan6/ETH_RXDV"
 Po -1613 491
 $EndPAD
 $PAD
 Sh "8" R 315 98 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -1613 295
 $EndPAD
 $PAD
@@ -11436,63 +11324,63 @@ $PAD
 Sh "6" R 315 98 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 43 "/Ethernet_Phy/ETH_RXD0"
+Ne 67 "/FPGA_Spartan6/ETH_RXD0"
 Po -1613 -98
 $EndPAD
 $PAD
 Sh "5" R 315 98 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "/FPGA_Spartan6/ETH_RXD1"
+Ne 53 "/Ethernet_Phy/ETH_RXD1"
 Po -1613 -295
 $EndPAD
 $PAD
 Sh "4" R 315 99 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 44 "/Ethernet_Phy/ETH_RXD2"
+Ne 68 "/FPGA_Spartan6/ETH_RXD2"
 Po -1613 -491
 $EndPAD
 $PAD
 Sh "3" R 315 99 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 60 "/FPGA_Spartan6/ETH_RXD3"
+Ne 54 "/Ethernet_Phy/ETH_RXD3"
 Po -1613 -688
 $EndPAD
 $PAD
 Sh "2" R 315 99 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "/FPGA_Spartan6/ETH_MDC"
+Ne 64 "/FPGA_Spartan6/ETH_MDC"
 Po -1613 -885
 $EndPAD
 $PAD
 Sh "1" R 315 98 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 41 "/Ethernet_Phy/ETH_MDIO"
+Ne 51 "/Ethernet_Phy/ETH_MDIO"
 Po -1613 -1082
 $EndPAD
 $PAD
 Sh "48" R 98 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "/FPGA_Spartan6/ETH_RESET_N"
+Ne 65 "/FPGA_Spartan6/ETH_RESET_N"
 Po -1082 -1613
 $EndPAD
 $PAD
 Sh "47" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 42 "/Ethernet_Phy/ETH_PLL1.8V"
+Ne 52 "/Ethernet_Phy/ETH_PLL1.8V"
 Po -885 -1613
 $EndPAD
 $PAD
 Sh "46" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "/FPGA_Spartan6/ETH_CLK"
+Ne 46 "/Ethernet_Phy/ETH_CLK"
 Po -688 -1613
 $EndPAD
 $PAD
@@ -11506,7 +11394,7 @@ $PAD
 Sh "44" R 98 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po -295 -1613
 $EndPAD
 $PAD
@@ -11527,56 +11415,56 @@ $PAD
 Sh "41" R 98 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "/Ethernet_Phy/MAG_TX+"
+Ne 61 "/Ethernet_Phy/MAG_TX+"
 Po 295 -1613
 $EndPAD
 $PAD
 Sh "40" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "/Ethernet_Phy/MAG_TX-"
+Ne 62 "/Ethernet_Phy/MAG_TX-"
 Po 491 -1613
 $EndPAD
 $PAD
 Sh "39" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 688 -1613
 $EndPAD
 $PAD
 Sh "38" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 37 "/Ethernet_Phy/ETH_A3.3V"
+Ne 45 "/Ethernet_Phy/ETH_A3.3V"
 Po 885 -1613
 $EndPAD
 $PAD
 Sh "37" R 98 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 243 "N-000401"
+Ne 247 "N-000400"
 Po 1082 -1613
 $EndPAD
 $PAD
 Sh "25" R 315 98 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "/FPGA_Spartan6/ETH_INT"
+Ne 48 "/Ethernet_Phy/ETH_INT"
 Po 1613 1082
 $EndPAD
 $PAD
 Sh "26" R 315 99 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 39 "/Ethernet_Phy/ETH_LED0"
+Ne 49 "/Ethernet_Phy/ETH_LED0"
 Po 1613 885
 $EndPAD
 $PAD
 Sh "27" R 315 99 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 40 "/Ethernet_Phy/ETH_LED1"
+Ne 50 "/Ethernet_Phy/ETH_LED1"
 Po 1613 688
 $EndPAD
 $PAD
@@ -11604,21 +11492,21 @@ $PAD
 Sh "31" R 315 98 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 36 "/Ethernet_Phy/ETH_A1.8V"
+Ne 44 "/Ethernet_Phy/ETH_A1.8V"
 Po 1613 -98
 $EndPAD
 $PAD
 Sh "32" R 315 98 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 49 "/Ethernet_Phy/MAG_RX-"
+Ne 59 "/Ethernet_Phy/MAG_RX-"
 Po 1613 -295
 $EndPAD
 $PAD
 Sh "33" R 315 99 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 48 "/Ethernet_Phy/MAG_RX+"
+Ne 58 "/Ethernet_Phy/MAG_RX+"
 Po 1613 -491
 $EndPAD
 $PAD
@@ -11632,14 +11520,14 @@ $PAD
 Sh "35" R 315 99 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 1613 -885
 $EndPAD
 $PAD
 Sh "36" R 315 98 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 1613 -1082
 $EndPAD
 $PAD
@@ -11653,70 +11541,70 @@ $PAD
 Sh "14" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 66 "/FPGA_Spartan6/ETH_TXER"
+Ne 74 "/FPGA_Spartan6/ETH_TXER"
 Po -885 1613
 $EndPAD
 $PAD
 Sh "15" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 62 "/FPGA_Spartan6/ETH_TXC"
+Ne 71 "/FPGA_Spartan6/ETH_TXC"
 Po -688 1613
 $EndPAD
 $PAD
 Sh "16" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 65 "/FPGA_Spartan6/ETH_TXEN"
+Ne 57 "/Ethernet_Phy/ETH_TXEN"
 Po -491 1613
 $EndPAD
 $PAD
 Sh "17" R 98 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 63 "/FPGA_Spartan6/ETH_TXD0"
+Ne 55 "/Ethernet_Phy/ETH_TXD0"
 Po -295 1613
 $EndPAD
 $PAD
 Sh "18" R 98 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 46 "/Ethernet_Phy/ETH_TXD1"
+Ne 56 "/Ethernet_Phy/ETH_TXD1"
 Po -98 1613
 $EndPAD
 $PAD
 Sh "19" R 98 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 64 "/FPGA_Spartan6/ETH_TXD2"
+Ne 72 "/FPGA_Spartan6/ETH_TXD2"
 Po 98 1613
 $EndPAD
 $PAD
 Sh "20" R 98 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 47 "/Ethernet_Phy/ETH_TXD3"
+Ne 73 "/FPGA_Spartan6/ETH_TXD3"
 Po 295 1613
 $EndPAD
 $PAD
 Sh "21" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 38 "/Ethernet_Phy/ETH_COL"
+Ne 47 "/Ethernet_Phy/ETH_COL"
 Po 491 1613
 $EndPAD
 $PAD
 Sh "22" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "/FPGA_Spartan6/ETH_CRS"
+Ne 63 "/FPGA_Spartan6/ETH_CRS"
 Po 688 1613
 $EndPAD
 $PAD
 Sh "23" R 99 315 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 885 1613
 $EndPAD
 $PAD
@@ -11751,7 +11639,7 @@ $PAD
 Sh "2" R 355 668 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 570 0
 $EndPAD
 $EndMODULE  1206
@@ -11794,7 +11682,7 @@ $PAD
 Sh "2" R 200 300 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 0 500
 $EndPAD
 $PAD
@@ -11850,7 +11738,7 @@ $PAD
 Sh "2" R 200 300 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 0 500
 $EndPAD
 $PAD
@@ -11919,7 +11807,7 @@ $PAD
 Sh "2" R 157 236 0 0 900
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -11975,7 +11863,7 @@ $PAD
 Sh "2" R 157 236 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -12003,7 +11891,7 @@ $PAD
 Sh "2" R 157 236 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -12059,7 +11947,7 @@ $PAD
 Sh "2" R 157 236 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -12115,7 +12003,7 @@ $PAD
 Sh "2" R 275 510 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 373 0
 $EndPAD
 $EndMODULE  0805
@@ -12143,7 +12031,7 @@ $PAD
 Sh "2" R 275 510 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 373 0
 $EndPAD
 $EndMODULE  0805
@@ -12171,7 +12059,7 @@ $PAD
 Sh "2" R 355 668 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 570 0
 $EndPAD
 $EndMODULE  1206
@@ -12199,7 +12087,7 @@ $PAD
 Sh "2" R 355 668 0 0 2700
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 570 0
 $EndPAD
 $EndMODULE  1206
@@ -12283,7 +12171,7 @@ $PAD
 Sh "2" R 197 354 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 37 "/Ethernet_Phy/ETH_A3.3V"
+Ne 45 "/Ethernet_Phy/ETH_A3.3V"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -12311,7 +12199,7 @@ $PAD
 Sh "2" R 157 236 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 241 "N-000264"
+Ne 245 "N-000264"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -12339,7 +12227,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 242 "N-000382"
+Ne 246 "N-000382"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -12508,49 +12396,49 @@ $PAD
 Sh "1" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 238 "/USB/USBD_SPD"
+Ne 242 "/USB/USBD_SPD"
 Po -295 491
 $EndPAD
 $PAD
 Sh "11" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 249 "N-000422"
+Ne 240 "/USB/USBD_D+"
 Po -98 -491
 $EndPAD
 $PAD
 Sh "2" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 226 "/FPGA_Spartan6/USBD_RCV"
+Ne 225 "/FPGA_Spartan6/USBD_RCV"
 Po -98 491
 $EndPAD
 $PAD
 Sh "10" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 248 "N-000421"
+Ne 241 "/USB/USBD_D-"
 Po 98 -491
 $EndPAD
 $PAD
 Sh "3" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 239 "/USB/USBD_VP"
+Ne 226 "/FPGA_Spartan6/USBD_VP"
 Po 98 491
 $EndPAD
 $PAD
 Sh "9" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 237 "/USB/USBD_OE_N"
+Ne 224 "/FPGA_Spartan6/USBD_OE_N"
 Po 295 -491
 $EndPAD
 $PAD
 Sh "4" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 227 "/FPGA_Spartan6/USBD_VM"
+Ne 243 "/USB/USBD_VM"
 Po 295 491
 $EndPAD
 $PAD
@@ -12578,7 +12466,7 @@ $PAD
 Sh "6" R 157 98 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 491 98
 $EndPAD
 $PAD
@@ -12592,7 +12480,7 @@ $PAD
 Sh "7" R 157 98 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 491 -98
 $EndPAD
 $PAD
@@ -12642,49 +12530,49 @@ $PAD
 Sh "1" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 225 "/FPGA_Spartan6/USBA_SPD"
+Ne 223 "/FPGA_Spartan6/USBA_SPD"
 Po -295 491
 $EndPAD
 $PAD
 Sh "11" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 251 "N-000424"
+Ne 236 "/USB/USBA_D+"
 Po -98 -491
 $EndPAD
 $PAD
 Sh "2" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 224 "/FPGA_Spartan6/USBA_RCV"
+Ne 222 "/FPGA_Spartan6/USBA_RCV"
 Po -98 491
 $EndPAD
 $PAD
 Sh "10" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 250 "N-000423"
+Ne 237 "/USB/USBA_D-"
 Po 98 -491
 $EndPAD
 $PAD
 Sh "3" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 236 "/USB/USBA_VP"
+Ne 239 "/USB/USBA_VP"
 Po 98 491
 $EndPAD
 $PAD
 Sh "9" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 223 "/FPGA_Spartan6/USBA_OE_N"
+Ne 221 "/FPGA_Spartan6/USBA_OE_N"
 Po 295 -491
 $EndPAD
 $PAD
 Sh "4" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 235 "/USB/USBA_VM"
+Ne 238 "/USB/USBA_VM"
 Po 295 491
 $EndPAD
 $PAD
@@ -12712,7 +12600,7 @@ $PAD
 Sh "6" R 157 98 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 491 98
 $EndPAD
 $PAD
@@ -12726,7 +12614,7 @@ $PAD
 Sh "7" R 157 98 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 491 -98
 $EndPAD
 $PAD
@@ -12768,7 +12656,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -12796,7 +12684,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -12808,7 +12696,7 @@ AR /4C5F1EDC/4C71C9C3
 Op 0 0 0
 At SMD 
 T0 0 -150 200 200 0 40 N V 25 N"C88"
-T1 0 150 200 200 0 40 N I 25 N"470nF"
+T1 0 150 200 200 0 40 N I 25 N"100nF"
 DS -305 168 -305 -168 50 21
 DS -305 -168 305 -168 50 21
 DS 305 -168 305 168 50 21
@@ -12824,7 +12712,7 @@ $PAD
 Sh "2" R 157 236 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 176 0
 $EndPAD
 $EndMODULE  0402
@@ -12845,7 +12733,7 @@ $PAD
 Sh "1" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 246 "N-000415"
+Ne 250 "N-000418"
 Po -294 0
 $EndPAD
 $PAD
@@ -12880,7 +12768,7 @@ $PAD
 Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -12901,19 +12789,19 @@ $PAD
 Sh "1" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 247 "N-000417"
+Ne 251 "N-000420"
 Po -294 0
 $EndPAD
 $PAD
 Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
 $MODULE 0603
-Po 47380 42317 0 15 4C5FF890 4C71CB46 ~~
+Po 47059 41287 0 15 4C5FF890 4C71CB46 ~~
 Li 0603
 Sc 4C71CB46
 AR /4C5F1EDC/4C71C9C0
@@ -12936,40 +12824,12 @@ $PAD
 Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
 $MODULE 0603
-Po 47380 42317 0 15 4C5FF890 4C71CB48 ~~
-Li 0603
-Sc 4C71CB48
-AR /4C5F1EDC/4C71C9C4
-Op 0 0 0
-At SMD 
-T0 0 -150 200 200 0 40 N V 25 N"C87"
-T1 0 150 200 200 0 40 N I 25 N"1uF"
-DS -443 227 -443 -227 50 21
-DS -443 -227 443 -227 50 21
-DS 443 -227 443 227 50 21
-DS 443 227 -443 227 50 21
-$PAD
-Sh "1" R 197 354 0 0 0
-Dr 0 0 0
-At SMD N 00888000
-Ne 4 "+3.3V"
-Po -294 0
-$EndPAD
-$PAD
-Sh "2" R 197 354 0 0 0
-Dr 0 0 0
-At SMD N 00888000
-Ne 240 "GND"
-Po 294 0
-$EndPAD
-$EndMODULE  0603
-$MODULE 0603
-Po 47380 42317 0 15 4C5FF890 4C71CB4A ~~
+Po 47516 42984 0 15 4C5FF890 4C71CB4A ~~
 Li 0603
 Sc 4C71CB4A
 AR /4C5F1EDC/4C71C9C5
@@ -12992,7 +12852,7 @@ $PAD
 Sh "2" R 197 354 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 240 "GND"
+Ne 244 "GND"
 Po 294 0
 $EndPAD
 $EndMODULE  0603
@@ -13013,7 +12873,7 @@ $PAD
 Sh "1" R 355 984 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 246 "N-000415"
+Ne 250 "N-000418"
 Po -570 0
 $EndPAD
 $PAD
@@ -13063,7 +12923,7 @@ $PAD
 Sh "11" R 98 157 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 247 "N-000417"
+Ne 251 "N-000420"
 Po -98 -491
 $EndPAD
 $PAD
@@ -13126,7 +12986,7 @@ $PAD
 Sh "6" R 157 98 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 491 98
 $EndPAD
 $PAD
@@ -13140,7 +13000,7 @@ $PAD
 Sh "7" R 157 98 0 0 0
 Dr 0 0 0
 At SMD N 00440001
-Ne 240 "GND"
+Ne 244 "GND"
 Po 491 -98
 $EndPAD
 $PAD
@@ -13158,6 +13018,146 @@ Ne 0 ""
 Po 491 -295
 $EndPAD
 $EndMODULE  MLF16
+$MODULE 0402
+Po 54642 26984 900 0 4C5FF890 4C5F2039 ~~
+Li 0402
+Sc 4C5F2039
+AR /4C5F1EDC/4C5F2039
+Op 0 0 0
+At SMD 
+T0 0 150 200 200 900 40 M V 20 N"C15"
+T1 0 -150 200 200 900 40 M I 20 N"100nF"
+DS -305 -168 -305 168 50 20
+DS -305 168 305 168 50 20
+DS 305 168 305 -168 50 20
+DS 305 -168 -305 -168 50 20
+$PAD
+Sh "1" R 157 236 0 0 900
+Dr 0 0 0
+At SMD N 00440001
+Ne 3 "+2.5V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 900
+Dr 0 0 0
+At SMD N 00440001
+Ne 244 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 55161 26307 0 0 4C5FF890 4C5F2037 ~~
+Li 0402
+Sc 4C5F2037
+AR /4C5F1EDC/4C5F2037
+Op 0 0 0
+At SMD 
+T0 0 150 200 200 0 40 M V 20 N"C14"
+T1 0 -150 200 200 0 40 M I 20 N"100nF"
+DS -305 -168 -305 168 50 20
+DS -305 168 305 168 50 20
+DS 305 168 305 -168 50 20
+DS 305 -168 -305 -168 50 20
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00440001
+Ne 4 "+3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00440001
+Ne 244 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0402
+Po 57055 26291 900 0 4C5FF890 4C6552BD ~~
+Li 0402
+Sc 4C6552BD
+AR /4C5F1EDC/4C6552BD
+Op 0 0 0
+At SMD 
+T0 0 150 200 200 900 40 M V 20 N"C36"
+T1 0 -150 200 200 900 40 M I 20 N"100nF"
+DS -305 -168 -305 168 50 20
+DS -305 168 305 168 50 20
+DS 305 168 305 -168 50 20
+DS 305 -168 -305 -168 50 20
+$PAD
+Sh "1" R 157 236 0 0 900
+Dr 0 0 0
+At SMD N 00440001
+Ne 4 "+3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 900
+Dr 0 0 0
+At SMD N 00440001
+Ne 244 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
+$MODULE 0603
+Po 56827 25638 0 0 4C5FF890 4C6552BE ~~
+Li 0603
+Sc 4C6552BE
+AR /4C5F1EDC/4C6552BE
+Op 0 0 0
+At SMD 
+T0 0 150 200 200 0 40 M V 20 N"C35"
+T1 0 -150 200 200 0 40 M I 20 N"1uF"
+DS -443 -227 -443 227 50 20
+DS -443 227 443 227 50 20
+DS 443 227 443 -227 50 20
+DS 443 -227 -443 -227 50 20
+$PAD
+Sh "1" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00440001
+Ne 4 "+3.3V"
+Po -294 0
+$EndPAD
+$PAD
+Sh "2" R 197 354 0 0 0
+Dr 0 0 0
+At SMD N 00440001
+Ne 244 "GND"
+Po 294 0
+$EndPAD
+$EndMODULE  0603
+$MODULE 0402
+Po 48933 42732 0 15 4C5FF890 4C71CB48 ~~
+Li 0402
+Sc 4C71CB48
+AR /4C5F1EDC/4C71C9C4
+Op 0 0 0
+At SMD 
+T0 0 -150 200 200 0 40 N V 25 N"C87"
+T1 0 150 200 200 0 40 N I 25 N"100nF"
+DS -305 168 -305 -168 50 21
+DS -305 -168 305 -168 50 21
+DS 305 -168 305 168 50 21
+DS 305 168 -305 168 50 21
+$PAD
+Sh "1" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 4 "+3.3V"
+Po -176 0
+$EndPAD
+$PAD
+Sh "2" R 157 236 0 0 0
+Dr 0 0 0
+At SMD N 00888000
+Ne 244 "GND"
+Po 176 0
+$EndPAD
+$EndMODULE  0402
 $COTATION
 Ge 0 25 0
 Va 21500
@@ -13249,6 +13249,20 @@ Po 3 50069 27352 50069 27352 157 -1
 De 15 1 2 0 0
 Po 0 50071 27354 50069 27352 79 -1
 De 15 0 2 0 0
+Po 0 54913 27275 54757 27275 79 -1
+De 0 0 3 0 0
+Po 0 54757 27275 54642 27160 79 -1
+De 0 0 3 0 400
+Po 0 55226 27370 55008 27370 79 -1
+De 0 0 3 0 800
+Po 0 55004 27366 54913 27275 79 -1
+De 0 0 3 0 0
+Po 0 54913 27275 54916 27278 79 -1
+De 0 0 3 0 0
+Po 3 55004 27366 55004 27366 157 -1
+De 15 1 3 0 0
+Po 0 55008 27370 55004 27366 79 -1
+De 0 0 3 0 0
 Po 0 56760 27370 56760 27381 79 -1
 De 0 0 3 0 0
 Po 0 56938 27370 56760 27370 79 -1
@@ -13585,6 +13599,48 @@ Po 0 52530 32607 52530 32608 79 -1
 De 15 0 3 0 800
 Po 0 52530 32608 52717 32795 79 -1
 De 15 0 3 0 0
+Po 0 57055 26467 57230 26467 79 -1
+De 0 0 4 0 800
+Po 0 57232 26465 57236 26465 79 -1
+De 15 0 4 0 0
+Po 3 57232 26465 57232 26465 157 -1
+De 15 1 4 0 0
+Po 0 57230 26467 57232 26465 79 -1
+De 0 0 4 0 0
+Po 0 57134 26781 57134 26546 79 -1
+De 0 0 4 0 800
+Po 0 57134 26546 57055 26467 79 -1
+De 0 0 4 0 400
+Po 0 55422 26781 55422 26617 79 -1
+De 0 0 4 0 800
+Po 3 55425 26614 55425 26614 157 -1
+De 15 1 4 0 0
+Po 0 55422 26617 55425 26614 79 -1
+De 0 0 4 0 0
+Po 0 54871 25685 54871 26193 79 -1
+De 0 0 4 0 800
+Po 0 54871 26193 54985 26307 79 -1
+De 0 0 4 0 400
+Po 0 54985 26307 54985 26658 79 -1
+De 0 0 4 0 800
+Po 0 54985 26658 55000 26673 79 -1
+De 0 0 4 0 0
+Po 0 55422 26781 55108 26781 79 -1
+De 0 0 4 0 800
+Po 0 55108 26781 55000 26673 79 -1
+De 0 0 4 0 0
+Po 0 55226 27174 55103 27174 79 -1
+De 0 0 4 0 800
+Po 0 55000 26673 55008 26673 79 -1
+De 15 0 4 0 0
+Po 3 55000 26673 55000 26673 157 -1
+De 15 1 4 0 0
+Po 0 55031 26704 55000 26673 79 -1
+De 0 0 4 0 0
+Po 0 55031 27102 55031 26704 79 -1
+De 0 0 4 0 0
+Po 0 55103 27174 55031 27102 79 -1
+De 0 0 4 0 0
 Po 0 56938 27174 56773 27174 79 -1
 De 0 0 4 0 800
 Po 3 56728 27110 56728 27110 157 -1
@@ -13653,9 +13709,9 @@ Po 0 53164 20570 53165 20571 79 -1
 De 0 0 4 0 0
 Po 0 59221 30639 59221 30633 79 -1
 De 15 0 4 0 800
-Po 3 59413 30441 59413 30441 157 -1
+Po 3 59382 30480 59382 30480 157 -1
 De 15 1 4 0 0
-Po 0 59221 30633 59413 30441 79 -1
+Po 0 59221 30633 59382 30480 79 -1
 De 15 0 4 0 0
 Po 0 58434 31820 58434 31818 79 -1
 De 15 0 4 0 800
@@ -13801,17 +13857,15 @@ Po 3 59024 32004 59024 32004 157 -1
 De 15 1 7 0 0
 Po 0 58840 31820 59024 32004 59 -1
 De 15 0 7 0 0
-Po 0 59221 30245 59221 30102 59 -1
+Po 0 59221 30245 59221 30224 59 -1
 De 15 0 8 0 800
-Po 0 60622 28713 60622 28709 59 -1
+Po 0 60642 28803 60642 28799 59 -1
 De 3 0 8 0 0
-Po 0 59465 29870 60622 28713 59 -1
+Po 0 59390 30055 60642 28803 59 -1
 De 3 0 8 0 0
-Po 3 59465 29870 59465 29870 157 -1
+Po 3 59390 30055 59390 30055 157 -1
 De 15 1 8 0 0
-Po 0 59453 29870 59465 29870 59 -1
-De 15 0 8 0 0
-Po 0 59221 30102 59453 29870 59 -1
+Po 0 59221 30224 59390 30055 59 -1
 De 15 0 8 0 0
 Po 0 58827 31032 58827 31027 59 -1
 De 15 0 9 0 800
@@ -13821,64 +13875,64 @@ Po 0 59213 29842 60464 28591 59 -1
 De 3 0 9 0 0
 Po 0 59213 30641 59213 29842 59 -1
 De 3 0 9 0 0
-Po 0 59008 30846 59213 30641 59 -1
+Po 0 59055 30791 59213 30641 59 -1
 De 3 0 9 0 0
-Po 3 59008 30846 59008 30846 157 -1
+Po 3 59055 30791 59055 30791 157 -1
 De 15 1 9 0 0
-Po 0 58827 31027 59008 30846 59 -1
+Po 0 58827 31027 59055 30791 59 -1
 De 15 0 9 0 0
-Po 0 50995 31576 50694 31576 39 -1
-De 15 0 10 0 800
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 Po 0 57264 30043 57264 30233 39 -1
 De 15 0 126 0 0
 Po 0 57264 30233 57252 30245 39 -1
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 De 15 0 128 0 0
 Po 0 53461 24874 53457 24874 39 -1
 De 15 0 128 0 0
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 De 15 0 130 0 0
 Po 0 52930 27434 53796 27434 39 -1
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 De 15 0 132 0 0
 Po 0 53434 27634 54382 28582 39 -1
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 Po 0 59760 38366 59760 40121 39 -1
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 Po 0 57189 39354 57317 39482 39 -1
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 Po 0 52529 33001 52530 33001 39 -1
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 Po 0 52319 32791 52529 33001 39 -1
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 Po 0 49150 31654 50504 31654 39 -1
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 Po 0 49075 31579 49150 31654 39 -1
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 Po 3 49075 31579 49075 31579 157 -1
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 Po 0 49119 31535 49075 31579 39 -1
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 Po 0 49105 31338 49102 31335 39 -1
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 Po 0 51858 32756 51858 32630 39 -1
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 Po 3 53130 32795 53130 32795 157 -1
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 Po 0 51521 32004 51411 31894 39 -1
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 Po 0 51521 32761 51521 32004 39 -1
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 Po 0 51411 31894 51516 31999 39 -1
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 Po 0 49075 31925 49213 32063 39 -1
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 Po 3 49075 31925 49075 31925 157 -1
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 Po 0 49078 31922 49075 31925 39 -1
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 Po 0 52136 31053 52136 31032 39 -1
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 Po 0 51705 31826 52307 31224 39 -1
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 Po 0 49000 32874 50189 32874 39 -1
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 Po 0 49012 31740 51186 31740 39 -1
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 Po 0 48815 31937 49012 31740 39 -1
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 Po 0 49177 31142 49110 31075 39 -1
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 Po 0 49110 31075 49106 31075 39 -1
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 Po 3 49106 31075 49106 31075 157 -1
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 Po 0 49106 31075 49205 30976 39 -1
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 Po 0 49205 30976 50169 30976 39 -1
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 Po 0 51445 31248 51906 31709 39 -1
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 Po 0 49414 31142 49177 31142 39 -1
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 Po 0 51906 31709 51906 32151 39 -1
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 Po 0 53496 32579 53496 32791 39 -1
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 Po 0 53240 32323 53496 32579 39 -1
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 Po 0 52063 32323 53240 32323 39 -1
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 Po 0 53496 32791 53706 33001 39 -1
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 Po 0 51521 31142 51039 31142 39 -1
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 Po 0 53882 33587 54083 33788 39 -1
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 Po 0 53717 32603 53319 32205 39 -1
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 Po 0 53874 33587 53717 33430 39 -1
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 Po 0 49323 30642 50516 30642 39 -1
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 Po 0 49232 30945 49126 30839 39 -1
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 Po 0 52012 31633 51521 31142 39 -1
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 Po 0 52012 32110 52012 31633 39 -1
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-De 15 0 147 0 400
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 Po 0 51874 31815 52921 31815 39 -1
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 Po 0 51421 31362 51874 31815 39 -1
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-De 15 1 147 0 0
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 Po 0 48291 31606 48354 31669 39 -1
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 Po 0 48998 32967 51951 32967 39 -1
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 Po 0 48917 30964 48917 31650 39 -1
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-De 15 1 150 0 0
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-De 0 0 150 0 0
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-De 15 0 150 0 400
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-De 15 0 150 0 0
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 Po 0 52343 33961 52516 33788 39 -1
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 Po 0 52530 33788 52516 33788 39 -1
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 Po 0 49205 36142 49492 36142 39 -1
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 Po 0 49118 36055 49142 36079 39 -1
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 Po 3 49303 35319 49303 35319 157 -1
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 Po 0 49728 35319 49303 35319 39 -1
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 Po 0 52530 33788 52530 33789 39 -1
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 Po 0 49492 35945 49492 35134 39 -1
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 Po 0 49622 35004 49862 35004 39 -1
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 Po 0 50401 34465 50449 34465 39 -1
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 Po 3 51488 34457 51488 34457 157 -1
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 Po 0 51488 34457 51480 34465 39 -1
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 Po 0 51480 34465 50449 34465 39 -1
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 Po 0 50449 34465 50401 34465 39 -1
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 Po 0 52136 33809 52136 33788 39 -1
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 Po 0 52136 33788 52134 33788 39 -1
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 Po 0 50323 35165 51543 35165 39 -1
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 Po 3 51976 35165 51976 35165 157 -1
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 Po 0 51976 35165 52338 35165 39 -1
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 Po 0 49953 35535 50323 35165 39 -1
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 Po 0 48138 35535 49953 35535 39 -1
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 Po 0 47953 35618 48055 35618 39 -1
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 Po 0 47705 35866 47953 35618 39 -1
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 Po 0 52530 35357 52338 35165 39 -1
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 Po 0 51854 35287 51976 35165 39 -1
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 Po 0 51665 35287 51854 35287 39 -1
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 Po 0 50102 35713 50453 35362 39 -1
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 Po 0 47705 36197 47854 36197 39 -1
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 Po 0 48342 35713 50067 35713 39 -1
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 Po 0 48169 35886 48342 35713 39 -1
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 Po 0 48165 35886 48169 35886 39 -1
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 Po 0 50067 35713 50094 35713 39 -1
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 Po 0 50094 35713 50102 35713 39 -1
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 Po 0 51529 35361 52136 35361 39 -1
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 Po 0 51508 35382 51529 35361 39 -1
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 Po 3 51508 35382 51508 35382 157 -1
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 Po 0 51504 35382 51508 35382 39 -1
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 Po 0 52135 35362 52136 35361 39 -1
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 Po 0 49121 34106 50417 34106 39 -1
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 Po 0 49036 34019 49035 34020 39 -1
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 Po 3 49035 34020 49035 34020 157 -1
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 Po 0 49035 34020 49121 34106 39 -1
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 Po 0 53122 33992 53122 33996 39 -1
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 Po 0 53317 34182 53312 34182 39 -1
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 Po 0 53122 33992 53312 34182 39 -1
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 Po 0 52972 34146 52075 34146 39 -1
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 Po 0 49036 34019 49441 34019 39 -1
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 Po 0 49039 34276 51630 34276 39 -1
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 Po 0 49441 34216 49099 34216 39 -1
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 Po 3 49039 34276 49039 34276 157 -1
-De 15 1 174 0 0
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 Po 0 49099 34216 49039 34276 39 -1
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 Po 0 52561 34513 52724 34350 39 -1
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 Po 0 51867 34513 52561 34513 39 -1
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 Po 0 51630 34276 51867 34513 39 -1
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 Po 0 52892 34182 52923 34182 39 -1
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 Po 0 52724 34350 52892 34182 39 -1
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 Po 3 52724 34350 52724 34350 157 -1
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 Po 0 52713 34339 52724 34350 39 -1
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 Po 0 49421 32512 49177 32512 39 -1
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 Po 3 53512 33591 53512 33591 157 -1
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 Po 0 53512 33591 53709 33788 39 -1
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 Po 0 53709 33788 53711 33788 39 -1
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 Po 0 53307 33386 53512 33591 39 -1
-De 0 0 175 0 0
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 Po 0 52169 33386 53307 33386 39 -1
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 Po 0 51956 33173 52169 33386 39 -1
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 Po 0 51846 33173 51956 33173 39 -1
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 Po 3 51846 33173 51846 33173 157 -1
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 Po 0 51747 33173 51846 33173 39 -1
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 Po 0 51487 32913 51747 33173 39 -1
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 Po 0 50000 32913 51487 32913 39 -1
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 Po 0 49815 32728 50000 32913 39 -1
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 Po 0 49141 32728 49815 32728 39 -1
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 Po 0 49177 32512 49051 32638 39 -1
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 Po 0 51634 34638 51736 34638 39 -1
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 Po 0 51740 34634 52571 34634 39 -1
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 Po 0 51736 34638 51740 34634 39 -1
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 Po 0 48503 34055 48520 34055 39 -1
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 Po 0 52923 34588 52923 34574 39 -1
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 Po 0 52575 34638 52724 34787 39 -1
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+Po 0 53823 31642 53819 31638 79 -1
+De 15 0 244 0 0
+Po 0 52530 34968 52530 34979 79 -1
+De 15 0 244 0 800
+Po 0 52701 35150 52705 35150 79 -1
+De 0 0 244 0 0
+Po 3 52701 35150 52701 35150 157 -1
+De 15 1 244 0 0
+Po 0 52530 34979 52701 35150 79 -1
+De 15 0 244 0 0
+Po 0 52530 33395 52530 33329 79 -1
+De 15 0 244 0 800
+Po 3 52390 33189 52390 33189 157 -1
+De 15 1 244 0 0
+Po 0 52530 33329 52390 33189 79 -1
+De 15 0 244 0 0
+Po 0 52530 31820 52530 31844 79 -1
+De 15 0 244 0 800
+Po 0 52350 32024 52346 32024 79 -1
+De 0 0 244 0 0
+Po 3 52350 32024 52350 32024 157 -1
+De 15 1 244 0 0
+Po 0 52530 31844 52350 32024 79 -1
+De 15 0 244 0 0
+Po 0 47593 24659 47593 24502 79 -1
+De 15 0 244 0 800
+Po 0 47790 24479 47705 24394 79 -1
+De 15 0 244 0 0
+Po 0 47705 24394 47701 24394 79 -1
+De 15 0 244 0 0
+Po 3 47701 24394 47701 24394 157 -1
+De 15 1 244 0 0
+Po 0 47790 24479 47790 24659 79 -1
+De 15 0 244 0 400
+Po 0 47593 24502 47701 24394 79 -1
+De 15 0 244 0 0
+Po 0 47129 23858 47129 23808 79 -1
+De 0 0 244 0 800
+Po 0 47129 23808 47303 23634 79 -1
+De 0 0 244 0 0
+Po 0 46350 24257 46350 24055 79 -1
+De 15 0 244 0 800
+Po 3 46346 24051 46346 24051 157 -1
+De 15 1 244 0 0
+Po 0 46350 24055 46346 24051 79 -1
+De 15 0 244 0 0
+Po 0 47503 23642 47307 23642 79 -1
+De 15 0 244 0 800
+Po 0 47307 23642 47303 23638 79 -1
+De 15 0 244 0 0
+Po 0 47303 23638 47303 23634 79 -1
+De 15 0 244 0 0
+Po 3 47303 23634 47303 23634 157 -1
+De 15 1 244 0 0
+Po 0 47303 23634 47307 23634 79 -1
+De 0 0 244 0 0
+Po 0 47141 23445 47141 23846 79 -1
+De 0 0 244 0 800
+Po 0 47141 23846 47129 23858 79 -1
+De 0 0 244 0 400
+Po 0 60402 30245 60408 30245 79 -1
+De 15 0 244 0 800
+Po 0 60598 30055 60587 30055 79 -1
+De 0 0 244 0 0
+Po 3 60598 30055 60598 30055 157 -1
+De 15 1 244 0 0
+Po 0 60408 30245 60598 30055 79 -1
+De 15 0 244 0 0
+Po 0 57646 31820 57653 31820 79 -1
+De 15 0 244 0 800
+Po 3 57469 31697 57469 31697 157 -1
+De 15 1 244 0 0
+Po 0 57653 31820 57469 31697 79 -1
+De 15 0 244 0 0
+Po 0 56491 30173 56491 30487 79 -1
+De 0 0 244 0 800
+Po 0 56815 30811 56866 30811 79 -1
+De 0 0 244 0 0
+Po 0 56491 30487 56815 30811 79 -1
+De 0 0 244 0 0
+Po 0 56859 30639 56859 30804 79 -1
+De 15 0 244 0 800
+Po 0 56862 30815 56862 30823 79 -1
+De 0 0 244 0 0
+Po 0 56866 30811 56862 30815 79 -1
+De 0 0 244 0 0
+Po 3 56866 30811 56866 30811 157 -1
+De 15 1 244 0 0
+Po 0 56859 30804 56866 30811 79 -1
+De 15 0 244 0 0
+Po 0 60630 26054 60204 26054 79 -1
+De 15 0 244 0 800
+Po 0 60069 25919 59941 25919 79 -1
+De 0 0 244 0 400
+Po 0 60197 26047 60069 25919 79 -1
+De 0 0 244 0 0
+Po 3 60197 26047 60197 26047 157 -1
+De 15 1 244 0 0
+Po 0 60204 26054 60197 26047 79 -1
+De 15 0 244 0 0
+Po 0 59965 24371 59965 24173 79 -1
+De 0 0 244 0 800
+Po 0 59965 24173 59965 24169 79 -1
+De 3 0 244 0 0
+Po 3 59965 24173 59965 24173 157 -1
+De 15 1 244 0 0
+Po 0 52930 26054 53328 26054 79 -1
+De 15 0 244 0 800
+Po 0 53445 25846 53445 25997 79 -1
+De 0 0 244 0 400
+Po 3 53445 25846 53445 25846 157 -1
+De 15 1 244 0 0
+Po 0 53445 25937 53445 25846 79 -1
+De 15 0 244 0 0
+Po 0 53328 26054 53445 25937 79 -1
+De 15 0 244 0 0
+Po 0 53908 30142 53908 30285 79 -1
+De 0 0 244 0 800
+Po 0 53908 30285 53543 30650 79 -1
+De 0 0 244 0 0
+Po 0 55286 30639 55286 30631 79 -1
+De 15 0 244 0 800
+Po 3 55098 30443 55098 30443 157 -1
+De 15 1 244 0 0
+Po 0 55286 30631 55098 30443 79 -1
+De 15 0 244 0 0
+Po 0 53711 30639 53574 30639 79 -1
+De 15 0 244 0 800
+Po 0 53543 30650 53533 30650 79 -1
+De 0 0 244 0 0
+Po 3 53543 30650 53543 30650 157 -1
+De 15 1 244 0 0
+Po 0 53563 30650 53543 30650 39 -1
+De 15 0 244 0 0
+Po 0 53574 30639 53563 30650 39 -1
+De 15 0 244 0 0
+Po 0 48499 27453 48499 27229 79 -1
+De 0 0 244 0 800
+Po 3 48494 27224 48494 27224 157 -1
+De 15 1 244 0 0
+Po 0 48499 27229 48494 27224 79 -1
+De 0 0 244 0 0
+Po 0 47062 26567 46734 26567 79 -1
+De 15 0 244 0 800
+Po 3 46732 26565 46732 26565 157 -1
+De 15 1 244 0 0
+Po 0 46734 26567 46732 26565 79 -1
+De 15 0 244 0 0
+Po 0 47062 25584 46676 25584 79 -1
+De 15 0 244 0 800
+Po 3 46673 25591 46673 25591 157 -1
+De 15 1 244 0 0
+Po 0 46673 25587 46673 25591 79 -1
+De 15 0 244 0 0
+Po 0 46676 25584 46673 25587 79 -1
+De 15 0 244 0 0
+Po 0 50615 18560 50862 18560 79 -1
+De 0 0 244 0 800
+Po 3 50862 18560 50862 18560 157 -1
+De 15 1 244 0 0
+Po 0 50615 18560 50615 18117 79 -1
+De 0 0 244 0 800
+Po 0 50615 18117 50605 18107 79 -1
+De 0 0 244 0 400
+Po 0 49757 27885 49910 27885 79 -1
+De 15 0 244 0 800
+Po 0 49911 27884 49902 27884 79 -1
+De 0 0 244 0 0
+Po 3 49911 27884 49911 27884 157 -1
+De 15 1 244 0 0
+Po 0 49910 27885 49911 27884 79 -1
+De 15 0 244 0 0
+Po 0 48970 27885 48970 28156 79 -1
+De 15 0 244 0 800
+Po 0 48957 28169 48957 28189 79 -1
+De 0 0 244 0 0
+Po 0 48967 28159 48957 28169 79 -1
+De 0 0 244 0 0
+Po 3 48967 28159 48967 28159 157 -1
+De 15 1 244 0 0
+Po 0 48970 28156 48967 28159 79 -1
+De 15 0 244 0 0
+Po 0 47062 25190 46708 25190 39 -1
+De 15 0 247 0 800
+Po 0 46973 25193 47043 25263 39 -1
+De 0 0 247 0 400
+Po 0 46713 25193 46973 25193 39 -1
+De 0 0 247 0 0
+Po 0 46717 25161 46713 25193 39 -1
+De 0 0 247 0 0
+Po 3 46717 25161 46717 25161 157 -1
+De 15 1 247 0 0
+Po 0 46709 25191 46717 25161 39 -1
+De 15 0 247 0 0
+Po 0 46708 25190 46709 25191 39 -1
+De 15 0 247 0 0
+Po 0 50207 24130 50207 23890 39 -1
+De 0 0 248 0 800
+Po 0 50207 23890 51374 22723 39 -1
+De 0 0 248 0 400
 Po 0 48889 24124 48074 23309 39 -1
-De 0 0 245 0 800
+De 0 0 249 0 800
 Po 0 48074 23309 48074 22723 39 -1
-De 0 0 245 0 400
+De 0 0 249 0 400
 $EndTRACK
 $ZONE
 $EndZONE
diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp
index 075f51e..8043dd5 100644
--- a/kicad/xue-rnc/xue-rnc.cmp
+++ b/kicad/xue-rnc/xue-rnc.cmp
@@ -1,4 +1,4 @@
-Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Sun 22 Aug 2010 07:04:19 PM COT
+Cmp-Mod V01 Genere par PcbNew le Tue 24 Aug 2010 06:53:45 AM COT
 
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7F9F;
@@ -94,15 +94,15 @@ EndCmp
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2037;
 Reference = C14;
-ValeurCmp = 1uF;
-IdModule  = 0603;
+ValeurCmp = 100nF;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2039;
 Reference = C15;
-ValeurCmp = 470nF;
-IdModule  = 0603;
+ValeurCmp = 100nF;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
@@ -242,20 +242,20 @@ BeginCmp
 TimeStamp = /4C5F1EDC/4C6552BE;
 Reference = C35;
 ValeurCmp = 1uF;
-IdModule  = 0805;
+IdModule  = 0603;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C5F1EDC/4C6552BD;
 Reference = C36;
-ValeurCmp = 1uF;
-IdModule  = 0805;
+ValeurCmp = 100nF;
+IdModule  = 0402;
 EndCmp
 
 BeginCmp
 TimeStamp = /4C5F1EDC/4C6552BC;
 Reference = C37;
-ValeurCmp = 470nF;
+ValeurCmp = 100nF;
 IdModule  = 0402;
 EndCmp
 
@@ -595,6 +595,34 @@ ValeurCmp = 100nF;
 IdModule  = 0402;
 EndCmp
 
+BeginCmp
+TimeStamp = /4C5F1EDC/4C71C9C5;
+Reference = C86;
+ValeurCmp = 1uF;
+IdModule  = 0603;
+EndCmp
+
+BeginCmp
+TimeStamp = /4C5F1EDC/4C71C9C4;
+Reference = C87;
+ValeurCmp = 100nF;
+IdModule  = 0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /4C5F1EDC/4C71C9C3;
+Reference = C88;
+ValeurCmp = 100nF;
+IdModule  = 0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /4C5F1EDC/4C71C9BE;
+Reference = C89;
+ValeurCmp = 4.7nF;
+IdModule  = 0402;
+EndCmp
+
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2B55;
 Reference = F1;
@@ -603,7 +631,7 @@ IdModule  = 1210;
 EndCmp
 
 BeginCmp
-TimeStamp = /4C5F1EDC/4C6552BA;
+TimeStamp = /4C5F1EDC/4C71C9C1;
 Reference = F2;
 ValeurCmp = MICROSMD075F;
 IdModule  = 1210;
@@ -672,13 +700,6 @@ ValeurCmp = FB;
 IdModule  = 0603;
 EndCmp
 
-BeginCmp
-TimeStamp = /4C5F1EDC/4C6552B0;
-Reference = L6;
-ValeurCmp = FB;
-IdModule  = 0603;
-EndCmp
-
 BeginCmp
 TimeStamp = /4C5F1EDC/4C6552B1;
 Reference = L7;
@@ -700,6 +721,20 @@ ValeurCmp = 2.2uH;
 IdModule  = 1210;
 EndCmp
 
+BeginCmp
+TimeStamp = /4C5F1EDC/4C71C9B8;
+Reference = L10;
+ValeurCmp = FB;
+IdModule  = 0603;
+EndCmp
+
+BeginCmp
+TimeStamp = /4C5F1EDC/4C71C9B9;
+Reference = L11;
+ValeurCmp = FB;
+IdModule  = 0603;
+EndCmp
+
 BeginCmp
 TimeStamp = /4C4320F3/4C5D7F39;
 Reference = R1;
@@ -910,6 +945,13 @@ ValeurCmp = 330;
 IdModule  = 0402;
 EndCmp
 
+BeginCmp
+TimeStamp = /4C5F1EDC/4C71C9BD;
+Reference = R31;
+ValeurCmp = 1M;
+IdModule  = 0402;
+EndCmp
+
 BeginCmp
 TimeStamp = /4C431A63/4C69C6B2;
 Reference = RP1;
@@ -1120,6 +1162,13 @@ ValeurCmp = A7108;
 IdModule  = SOT23-5;
 EndCmp
 
+BeginCmp
+TimeStamp = /4C5F1EDC/4C71C9B0;
+Reference = U13;
+ValeurCmp = MIC2550-MLF;
+IdModule  = MLF16;
+EndCmp
+
 BeginCmp
 TimeStamp = /4C5F1EDC/4C5F2CA7;
 Reference = V1;
@@ -1148,4 +1197,18 @@ ValeurCmp = V0402MHS03;
 IdModule  = 0603;
 EndCmp
 
+BeginCmp
+TimeStamp = /4C5F1EDC/4C71C9BF;
+Reference = V5;
+ValeurCmp = V0402MHS03;
+IdModule  = 0603;
+EndCmp
+
+BeginCmp
+TimeStamp = /4C5F1EDC/4C71C9C0;
+Reference = V6;
+ValeurCmp = V0402MHS03;
+IdModule  = 0603;
+EndCmp
+
 EndListe
diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net
index 414ca94..7bfc362 100644
--- a/kicad/xue-rnc/xue-rnc.net
+++ b/kicad/xue-rnc/xue-rnc.net
@@ -1,4 +1,4 @@
-# EESchema Netlist Version 1.1 created  Mon 23 Aug 2010 10:34:45 PM COT
+# EESchema Netlist Version 1.1 created  Tue 24 Aug 2010 06:53:18 AM COT
 (
  ( /4C716A4D/4C716CAB $noname  J6 CONN_8X2 {Lib=CONN_8X2}
   (    1 /DBG_PRG/FPGA_TCK )
@@ -156,12 +156,12 @@
   (   CD ? )
   (    1 /FPGA_Spartan6/SD_DAT2 )
   (    2 /FPGA_Spartan6/SD_DAT3 )
-  (    3 /Non_volatile_memories/SD_CMD )
+  (    3 /FPGA_Spartan6/SD_CMD )
   (    4 +3.3V )
   (    5 /FPGA_Spartan6/SD_CLK )
   (    6 GND )
-  (    7 /FPGA_Spartan6/SD_DAT0 )
-  (    8 /FPGA_Spartan6/SD_DAT1 )
+  (    7 /Non_volatile_memories/SD_DAT0 )
+  (    8 /Non_volatile_memories/SD_DAT1 )
  )
  ( /4C4227FE/4B76F108 $noname  U5 NAND {Lib=HY27UG088G5M}
   (    1 ? )
@@ -171,7 +171,7 @@
   (    5 ? )
   (    6 /Non_volatile_memories/NF_RNB )
   (    7 /Non_volatile_memories/NF_RNB )
-  (    8 /FPGA_Spartan6/NF_RE_N )
+  (    8 /Non_volatile_memories/NF_RE_N )
   (    9 /Non_volatile_memories/NF_CS1_N )
   (   10 ? )
   (   11 ? )
@@ -195,7 +195,7 @@
   (   29 /FPGA_Spartan6/NF_D0 )
   (   30 /FPGA_Spartan6/NF_D1 )
   (   31 /Non_volatile_memories/NF_D2 )
-  (   32 /Non_volatile_memories/NF_D3 )
+  (   32 /FPGA_Spartan6/NF_D3 )
   (   33 ? )
   (   34 ? )
   (   35 ? )
@@ -205,7 +205,7 @@
   (   39 ? )
   (   40 ? )
   (   41 /FPGA_Spartan6/NF_D4 )
-  (   42 /FPGA_Spartan6/NF_D5 )
+  (   42 /Non_volatile_memories/NF_D5 )
   (   43 /FPGA_Spartan6/NF_D6 )
   (   44 /FPGA_Spartan6/NF_D7 )
   (   45 ? )
@@ -217,16 +217,16 @@
   (    1 +3.3V )
   (    2 GND )
  )
- ( /4C5F1EDC/4C71C9C4 0603  C87 1uF {Lib=C}
+ ( /4C5F1EDC/4C71C9C4 0402  C87 100nF {Lib=C}
   (    1 +3.3V )
   (    2 GND )
  )
- ( /4C5F1EDC/4C71C9C3 0402  C88 470nF {Lib=C}
+ ( /4C5F1EDC/4C71C9C3 0402  C88 100nF {Lib=C}
   (    1 +2.5V )
   (    2 GND )
  )
  ( /4C5F1EDC/4C71C9C1 1210  F2 MICROSMD075F {Lib=MICROSMD075F}
-  (    1 N-000415 )
+  (    1 N-000418 )
   (    2 +5V )
  )
  ( /4C5F1EDC/4C71C9C0 0603  V6 V0402MHS03 {Lib=V0402MHS03}
@@ -234,7 +234,7 @@
   (    2 GND )
  )
  ( /4C5F1EDC/4C71C9BF 0603  V5 V0402MHS03 {Lib=V0402MHS03}
-  (    1 N-000417 )
+  (    1 N-000420 )
   (    2 GND )
  )
  ( /4C5F1EDC/4C71C9BE 0402  C89 4.7nF {Lib=C}
@@ -250,7 +250,7 @@
   (    2 GND )
  )
  ( /4C5F1EDC/4C71C9B8 0603  L10 FB {Lib=INDUCTOR}
-  (    1 N-000415 )
+  (    1 N-000418 )
   (    2 ? )
  )
  ( /4C5F1EDC/4C71C9B0 MLF16  U13 MIC2550-MLF {Lib=MIC2550-MLF}
@@ -262,7 +262,7 @@
   (    7 GND )
   (    9 ? )
   (   10 N-000435 )
-  (   11 N-000417 )
+  (   11 N-000420 )
   (   12 +3.3V )
   (   14 +3.3V )
   (   15 +2.5V )
@@ -270,13 +270,13 @@
  ( /4C5F1EDC/4C71BA25 MLF16  U7 MIC2550-MLF {Lib=MIC2550-MLF}
   (    1 /USB/USBD_SPD )
   (    2 /FPGA_Spartan6/USBD_RCV )
-  (    3 /USB/USBD_VP )
-  (    4 /FPGA_Spartan6/USBD_VM )
+  (    3 /FPGA_Spartan6/USBD_VP )
+  (    4 /USB/USBD_VM )
   (    6 GND )
   (    7 GND )
-  (    9 /USB/USBD_OE_N )
-  (   10 N-000421 )
-  (   11 N-000422 )
+  (    9 /FPGA_Spartan6/USBD_OE_N )
+  (   10 /USB/USBD_D- )
+  (   11 /USB/USBD_D+ )
   (   12 +3.3V )
   (   14 +3.3V )
   (   15 +2.5V )
@@ -289,8 +289,8 @@
   (    6 GND )
   (    7 GND )
   (    9 /FPGA_Spartan6/USBA_OE_N )
-  (   10 N-000423 )
-  (   11 N-000424 )
+  (   10 /USB/USBA_D- )
+  (   11 /USB/USBA_D+ )
   (   12 +3.3V )
   (   14 +3.3V )
   (   15 +2.5V )
@@ -299,28 +299,28 @@
   (    1 +3.3V )
   (    2 GND )
  )
- ( /4C5F1EDC/4C6552BD $noname  C36 1uF {Lib=C}
+ ( /4C5F1EDC/4C6552BD 0402  C36 100nF {Lib=C}
   (    1 +3.3V )
   (    2 GND )
  )
- ( /4C5F1EDC/4C6552BC $noname  C37 470nF {Lib=C}
+ ( /4C5F1EDC/4C6552BC 0402  C37 100nF {Lib=C}
   (    1 +2.5V )
   (    2 GND )
  )
  ( /4C5F1EDC/4C6552B9 $noname  V4 V0402MHS03 {Lib=V0402MHS03}
-  (    1 N-000421 )
+  (    1 /USB/USBD_D- )
   (    2 GND )
  )
  ( /4C5F1EDC/4C6552B8 $noname  V3 V0402MHS03 {Lib=V0402MHS03}
-  (    1 N-000422 )
+  (    1 /USB/USBD_D+ )
   (    2 GND )
  )
  ( /4C5F1EDC/4C6552B7 $noname  C38 4.7nF {Lib=C}
-  (    1 N-000430 )
+  (    1 N-000429 )
   (    2 GND )
  )
  ( /4C5F1EDC/4C6552B6 $noname  R15 1M {Lib=R}
-  (    1 N-000430 )
+  (    1 N-000429 )
   (    2 GND )
  )
  ( /4C5F1EDC/4C6552B1 0603  L7 FB {Lib=INDUCTOR}
@@ -329,26 +329,26 @@
  )
  ( /4C5F1EDC/4C63F252 0603  L4 FB {Lib=INDUCTOR}
   (    1 N-000427 )
-  (    2 N-000425 )
+  (    2 N-000426 )
  )
  ( /4C5F1EDC/4C63F248 0603  L5 FB {Lib=INDUCTOR}
-  (    1 N-000426 )
+  (    1 N-000432 )
   (    2 GND )
  )
  ( /4C5F1EDC/4C5F2D27 $noname  R10 1M {Lib=R}
-  (    1 N-000428 )
+  (    1 N-000431 )
   (    2 GND )
  )
  ( /4C5F1EDC/4C5F2D1E $noname  C16 4.7nF {Lib=C}
-  (    1 N-000428 )
+  (    1 N-000431 )
   (    2 GND )
  )
  ( /4C5F1EDC/4C5F2CA7 0603  V1 V0402MHS03 {Lib=V0402MHS03}
-  (    1 N-000424 )
+  (    1 /USB/USBA_D+ )
   (    2 GND )
  )
  ( /4C5F1EDC/4C5F2CA3 0603  V2 V0402MHS03 {Lib=V0402MHS03}
-  (    1 N-000423 )
+  (    1 /USB/USBA_D- )
   (    2 GND )
  )
  ( /4C5F1EDC/4C5F2B55 $noname  F1 MICROSMD075F {Lib=MICROSMD075F}
@@ -356,20 +356,20 @@
   (    2 +5V )
  )
  ( /4C5F1EDC/4C5F23DD $noname  J5 USB-48204-0001 {Lib=USB-48204-0001}
-  (   S1 N-000428 )
-  (   S2 N-000428 )
-  (   S3 N-000428 )
-  (   S4 N-000428 )
-  (    1 N-000425 )
-  (    2 N-000423 )
-  (    3 N-000424 )
-  (    4 N-000426 )
+  (   S1 N-000431 )
+  (   S2 N-000431 )
+  (   S3 N-000431 )
+  (   S4 N-000431 )
+  (    1 N-000426 )
+  (    2 /USB/USBA_D- )
+  (    3 /USB/USBA_D+ )
+  (    4 N-000432 )
  )
- ( /4C5F1EDC/4C5F2039 $noname  C15 470nF {Lib=C}
+ ( /4C5F1EDC/4C5F2039 $noname  C15 100nF {Lib=C}
   (    1 +2.5V )
   (    2 GND )
  )
- ( /4C5F1EDC/4C5F2037 $noname  C14 1uF {Lib=C}
+ ( /4C5F1EDC/4C5F2037 0402  C14 100nF {Lib=C}
   (    1 +3.3V )
   (    2 GND )
  )
@@ -395,18 +395,18 @@
  )
  ( /4C431A63/4C6B216E 0402  R23 33 {Lib=R}
   (    1 /FPGA_Spartan6/R_M0_UDM )
-  (    2 /FPGA_Spartan6/M0_UDM )
+  (    2 /DDR_Banks/M0_UDM )
  )
  ( /4C431A63/4C6B216D 0402  R22 33 {Lib=R}
   (    1 /FPGA_Spartan6/R_M0_UDQS )
-  (    2 /FPGA_Spartan6/M0_UDQS )
+  (    2 /DDR_Banks/M0_UDQS )
  )
  ( /4C431A63/4C6B216B 0402  R24 33 {Lib=R}
   (    1 /FPGA_Spartan6/R_M0_CKE )
   (    2 /DDR_Banks/M0_CKE )
  )
  ( /4C431A63/4C6B1B90 0402  R21 120 {Lib=R}
-  (    1 /FPGA_Spartan6/M0_CLK )
+  (    1 /DDR_Banks/M0_CLK )
   (    2 /FPGA_Spartan6/M0_CLK# )
  )
  ( /4C431A63/4C6A0D58 R_PACK4-0402  RP14 R_PACK4 {Lib=R_PACK4}
@@ -414,10 +414,10 @@
   (    2 /FPGA_Spartan6/R_M0_A1 )
   (    3 /FPGA_Spartan6/R_M0_A2 )
   (    4 /FPGA_Spartan6/R_M0_A3 )
-  (    5 /DDR_Banks/M0_A3 )
+  (    5 /FPGA_Spartan6/M0_A3 )
   (    6 /FPGA_Spartan6/M0_A2 )
   (    7 /FPGA_Spartan6/M0_A1 )
-  (    8 /DDR_Banks/M0_A0 )
+  (    8 /FPGA_Spartan6/M0_A0 )
  )
  ( /4C431A63/4C6A0D57 R_PACK4-0402  RP15 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/R_M0_RAS# )
@@ -426,8 +426,8 @@
   (    4 /FPGA_Spartan6/R_M0_A10 )
   (    5 /FPGA_Spartan6/M0_A10 )
   (    6 /FPGA_Spartan6/M0_BA1 )
-  (    7 /FPGA_Spartan6/M0_BA0 )
-  (    8 /FPGA_Spartan6/M0_RAS# )
+  (    7 /DDR_Banks/M0_BA0 )
+  (    8 /DDR_Banks/M0_RAS# )
  )
  ( /4C431A63/4C6A0D56 R_PACK4-0402  RP16 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/R_M0_LDQS )
@@ -435,18 +435,18 @@
   (    3 /FPGA_Spartan6/R_M0_WE# )
   (    4 /FPGA_Spartan6/R_M0_CAS# )
   (    5 /FPGA_Spartan6/M0_CAS# )
-  (    6 /FPGA_Spartan6/M0_WE# )
-  (    7 /DDR_Banks/M0_LDM )
-  (    8 /DDR_Banks/M0_LDQS )
+  (    6 /DDR_Banks/M0_WE# )
+  (    7 /FPGA_Spartan6/M0_LDM )
+  (    8 /FPGA_Spartan6/M0_LDQS )
  )
  ( /4C431A63/4C6A0D55 R_PACK4-0402  RP17 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/R_M0_A7 )
   (    2 /FPGA_Spartan6/R_M0_A6 )
   (    3 /FPGA_Spartan6/R_M0_A5 )
   (    4 /FPGA_Spartan6/R_M0_A4 )
-  (    5 /DDR_Banks/M0_A4 )
-  (    6 /FPGA_Spartan6/M0_A5 )
-  (    7 /FPGA_Spartan6/M0_A6 )
+  (    5 /FPGA_Spartan6/M0_A4 )
+  (    6 /DDR_Banks/M0_A5 )
+  (    7 /DDR_Banks/M0_A6 )
   (    8 /FPGA_Spartan6/M0_A7 )
  )
  ( /4C431A63/4C6A0D54 R_PACK4-0402  RP18 R_PACK4 {Lib=R_PACK4}
@@ -454,20 +454,20 @@
   (    2 /FPGA_Spartan6/R_M0_A11 )
   (    3 /FPGA_Spartan6/R_M0_A9 )
   (    4 /FPGA_Spartan6/R_M0_A8 )
-  (    5 /FPGA_Spartan6/M0_A8 )
-  (    6 /DDR_Banks/M0_A9 )
-  (    7 /DDR_Banks/M0_A11 )
-  (    8 /FPGA_Spartan6/M0_A12 )
+  (    5 /DDR_Banks/M0_A8 )
+  (    6 /FPGA_Spartan6/M0_A9 )
+  (    7 /FPGA_Spartan6/M0_A11 )
+  (    8 /DDR_Banks/M0_A12 )
  )
  ( /4C431A63/4C69FCE8 R_PACK4-0402  RP12 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/R_M0_DQ4 )
   (    2 /FPGA_Spartan6/R_M0_DQ5 )
   (    3 /FPGA_Spartan6/R_M0_DQ6 )
   (    4 /FPGA_Spartan6/R_M0_DQ7 )
-  (    5 /DDR_Banks/M0_DQ7 )
+  (    5 /FPGA_Spartan6/M0_DQ7 )
   (    6 /FPGA_Spartan6/M0_DQ6 )
   (    7 /DDR_Banks/M0_DQ5 )
-  (    8 /DDR_Banks/M0_DQ4 )
+  (    8 /FPGA_Spartan6/M0_DQ4 )
  )
  ( /4C431A63/4C69FCE7 R_PACK4-0402  RP13 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/R_M0_DQ0 )
@@ -475,9 +475,9 @@
   (    3 /FPGA_Spartan6/R_M0_DQ2 )
   (    4 /FPGA_Spartan6/R_M0_DQ3 )
   (    5 /FPGA_Spartan6/M0_DQ3 )
-  (    6 /FPGA_Spartan6/M0_DQ2 )
-  (    7 /FPGA_Spartan6/M0_DQ1 )
-  (    8 /FPGA_Spartan6/M0_DQ0 )
+  (    6 /DDR_Banks/M0_DQ2 )
+  (    7 /DDR_Banks/M0_DQ1 )
+  (    8 /DDR_Banks/M0_DQ0 )
  )
  ( /4C431A63/4C69FCE6 R_PACK4-0402  RP11 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/R_M0_DQ8 )
@@ -485,31 +485,31 @@
   (    3 /FPGA_Spartan6/R_M0_DQ10 )
   (    4 /FPGA_Spartan6/R_M0_DQ11 )
   (    5 /FPGA_Spartan6/M0_DQ11 )
-  (    6 /DDR_Banks/M0_DQ10 )
+  (    6 /FPGA_Spartan6/M0_DQ10 )
   (    7 /FPGA_Spartan6/M0_DQ9 )
-  (    8 /FPGA_Spartan6/M0_DQ8 )
+  (    8 /DDR_Banks/M0_DQ8 )
  )
  ( /4C431A63/4C69FC19 R_PACK4-0402  RP10 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/R_M0_DQ12 )
   (    2 /FPGA_Spartan6/R_M0_DQ13 )
   (    3 /FPGA_Spartan6/R_M0_DQ14 )
   (    4 /FPGA_Spartan6/R_M0_DQ15 )
-  (    5 /FPGA_Spartan6/M0_DQ15 )
-  (    6 /DDR_Banks/M0_DQ14 )
+  (    5 /DDR_Banks/M0_DQ15 )
+  (    6 /FPGA_Spartan6/M0_DQ14 )
   (    7 /FPGA_Spartan6/M0_DQ13 )
   (    8 /FPGA_Spartan6/M0_DQ12 )
  )
  ( /4C431A63/4C69E7DD 0402  R19 33 {Lib=R}
   (    1 /FPGA_Spartan6/R_M1_UDQS )
-  (    2 /FPGA_Spartan6/M1_UDQS )
+  (    2 /DDR_Banks/M1_UDQS )
  )
  ( /4C431A63/4C69E92D 0402  R20 33 {Lib=R}
   (    1 /FPGA_Spartan6/R_M1_CS# )
-  (    2 /DDR_Banks/M1_CS# )
+  (    2 /FPGA_Spartan6/M1_CS# )
  )
  ( /4C431A63/4C69E7F8 0402  R17 33 {Lib=R}
   (    1 /FPGA_Spartan6/R_M1_CKE )
-  (    2 /FPGA_Spartan6/M1_CKE )
+  (    2 /DDR_Banks/M1_CKE )
  )
  ( /4C431A63/4C69E7C2 0402  R18 33 {Lib=R}
   (    1 /FPGA_Spartan6/R_M1_UDM )
@@ -517,8 +517,8 @@
  )
  ( /4C431A63/4C69E3A6 $noname  RP9 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/M1_DQ11 )
-  (    2 /FPGA_Spartan6/M1_DQ10 )
-  (    3 /DDR_Banks/M1_DQ9 )
+  (    2 /DDR_Banks/M1_DQ10 )
+  (    3 /FPGA_Spartan6/M1_DQ9 )
   (    4 /FPGA_Spartan6/M1_DQ8 )
   (    5 /FPGA_Spartan6/R_M1_DQ8 )
   (    6 /FPGA_Spartan6/R_M1_DQ9 )
@@ -529,21 +529,21 @@
   (    1 /FPGA_Spartan6/M1_DQ15 )
   (    2 /FPGA_Spartan6/M1_DQ14 )
   (    3 /FPGA_Spartan6/M1_DQ13 )
-  (    4 /FPGA_Spartan6/M1_DQ12 )
+  (    4 /DDR_Banks/M1_DQ12 )
   (    5 /FPGA_Spartan6/R_M1_DQ12 )
   (    6 /FPGA_Spartan6/R_M1_DQ13 )
   (    7 /FPGA_Spartan6/R_M1_DQ14 )
   (    8 /FPGA_Spartan6/R_M1_DQ15 )
  )
  ( /4C431A63/4C69DF7A 0402  R16 120 {Lib=R}
-  (    1 /DDR_Banks/M1_CLK# )
-  (    2 /FPGA_Spartan6/M1_CLK )
+  (    1 /FPGA_Spartan6/M1_CLK# )
+  (    2 /DDR_Banks/M1_CLK )
  )
  ( /4C431A63/4C69DC05 $noname  RP7 R_PACK4 {Lib=R_PACK4}
-  (    1 /FPGA_Spartan6/M1_A12 )
-  (    2 /DDR_Banks/M1_A11 )
-  (    3 /FPGA_Spartan6/M1_A9 )
-  (    4 /FPGA_Spartan6/M1_A8 )
+  (    1 /DDR_Banks/M1_A12 )
+  (    2 /FPGA_Spartan6/M1_A11 )
+  (    3 /DDR_Banks/M1_A9 )
+  (    4 /DDR_Banks/M1_A8 )
   (    5 /FPGA_Spartan6/R_M1_A8 )
   (    6 /FPGA_Spartan6/R_M1_A9 )
   (    7 /FPGA_Spartan6/R_M1_A11 )
@@ -551,8 +551,8 @@
  )
  ( /4C431A63/4C69DA8A $noname  RP6 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/M1_A7 )
-  (    2 /DDR_Banks/M1_A6 )
-  (    3 /FPGA_Spartan6/M1_A5 )
+  (    2 /FPGA_Spartan6/M1_A6 )
+  (    3 /DDR_Banks/M1_A5 )
   (    4 /FPGA_Spartan6/M1_A4 )
   (    5 ? )
   (    6 /FPGA_Spartan6/R_M1_A5 )
@@ -564,10 +564,10 @@
   (    2 /FPGA_Spartan6/R_M1_DQ1 )
   (    3 /FPGA_Spartan6/R_M1_DQ2 )
   (    4 /FPGA_Spartan6/R_M1_DQ3 )
-  (    5 /FPGA_Spartan6/M1_DQ3 )
+  (    5 /DDR_Banks/M1_DQ3 )
   (    6 /FPGA_Spartan6/M1_DQ2 )
   (    7 /FPGA_Spartan6/M1_DQ1 )
-  (    8 /DDR_Banks/M1_DQ0 )
+  (    8 /FPGA_Spartan6/M1_DQ0 )
  )
  ( /4C431A63/4C69D3A4 $noname  RP3 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/R_M1_LDQS )
@@ -575,8 +575,8 @@
   (    3 /FPGA_Spartan6/R_M1_WE# )
   (    4 /FPGA_Spartan6/R_M1_CAS# )
   (    5 /FPGA_Spartan6/M1_CAS# )
-  (    6 /DDR_Banks/M1_WE# )
-  (    7 /FPGA_Spartan6/M1_LDM )
+  (    6 /FPGA_Spartan6/M1_WE# )
+  (    7 /DDR_Banks/M1_LDM )
   (    8 /FPGA_Spartan6/M1_LDQS )
  )
  ( /4C431A63/4C69D3A3 $noname  RP4 R_PACK4 {Lib=R_PACK4}
@@ -585,9 +585,9 @@
   (    3 /FPGA_Spartan6/R_M1_DQ6 )
   (    4 /FPGA_Spartan6/R_M1_DQ7 )
   (    5 /FPGA_Spartan6/M1_DQ7 )
-  (    6 /FPGA_Spartan6/M1_DQ6 )
-  (    7 /FPGA_Spartan6/M1_DQ5 )
-  (    8 /DDR_Banks/M1_DQ4 )
+  (    6 /DDR_Banks/M1_DQ6 )
+  (    7 /DDR_Banks/M1_DQ5 )
+  (    8 /FPGA_Spartan6/M1_DQ4 )
  )
  ( /4C431A63/4C69CEE8 $noname  RP2 R_PACK4 {Lib=R_PACK4}
   (    1 /FPGA_Spartan6/R_M1_RAS# )
@@ -595,7 +595,7 @@
   (    3 /FPGA_Spartan6/R_M1_BA1 )
   (    4 /FPGA_Spartan6/R_M1_A10 )
   (    5 /FPGA_Spartan6/M1_A10 )
-  (    6 /DDR_Banks/M1_BA1 )
+  (    6 /FPGA_Spartan6/M1_BA1 )
   (    7 /DDR_Banks/M1_BA0 )
   (    8 /FPGA_Spartan6/M1_RAS# )
  )
@@ -606,8 +606,8 @@
   (    4 /FPGA_Spartan6/R_M1_A3 )
   (    5 /FPGA_Spartan6/M1_A3 )
   (    6 /FPGA_Spartan6/M1_A2 )
-  (    7 /DDR_Banks/M1_A1 )
-  (    8 /FPGA_Spartan6/M1_A0 )
+  (    7 /FPGA_Spartan6/M1_A1 )
+  (    8 /DDR_Banks/M1_A0 )
  )
  ( /4C431A63/4C656D9D $noname  C66 470nF {Lib=C}
   (    1 +2.5V )
@@ -770,8 +770,8 @@
   (  F21 /FPGA_Spartan6/R_M1_A0 )
   (  D21 /FPGA_Spartan6/R_M1_CKE )
   (  C21 +2.5V )
-  (  B21 ? )
-  (  A21 ? )
+  (  B21 /FPGA_Spartan6/USBD_VP )
+  (  A21 /FPGA_Spartan6/USBD_OE_N )
   (  W20 ? )
   (  V20 ? )
   (  U20 /FPGA_Spartan6/R_M1_DQ12 )
@@ -783,14 +783,14 @@
   (  L20 /FPGA_Spartan6/R_M1_LDQS )
   (  K20 /FPGA_Spartan6/R_M1_A5 )
   (  J20 /FPGA_Spartan6/R_M1_DQ4 )
-  (  H20 /FPGA_Spartan6/M1_CLK )
+  (  H20 /DDR_Banks/M1_CLK )
   (  G20 /FPGA_Spartan6/R_M1_A3 )
   (  F20 ? )
   (  E20 /FPGA_Spartan6/R_M1_A7 )
-  (  D20 ? )
+  (  D20 /USB/USBA_VM )
   (  C20 /FPGA_Spartan6/R_M1_A8 )
-  (  B20 /FPGA_Spartan6/USBA_OE_N )
-  (  A20 ? )
+  (  B20 /USB/USBD_SPD )
+  (  A20 /FPGA_Spartan6/USBD_RCV )
   (   P8 ? )
   (   M8 ? )
   (   K8 ? )
@@ -832,7 +832,7 @@
   (   L4 /FPGA_Spartan6/R_M0_LDM )
   (   K4 /FPGA_Spartan6/R_M0_CAS# )
   (   J4 /FPGA_Spartan6/R_M0_A6 )
-  (   H4 /FPGA_Spartan6/M0_CLK )
+  (   H4 /DDR_Banks/M0_CLK )
   (   G4 /FPGA_Spartan6/R_M0_A10 )
   (   F4 +2.5V )
   (   E4 ? )
@@ -856,48 +856,48 @@
   (   C3 ? )
   (   B3 ? )
   (  G10 +3.3V )
-  (  D10 /FPGA_Spartan6/ETH_TXD0 )
+  (  D10 /Ethernet_Phy/ETH_TXD0 )
   (  C10 /FPGA_Spartan6/ETH_TXD2 )
   (  B10 /FPGA_Spartan6/ETH_CRS )
-  (  A10 /FPGA_Spartan6/ETH_INT )
+  (  A10 /Ethernet_Phy/ETH_INT )
   (   E9 +3.3V )
-  (   D9 /FPGA_Spartan6/ETH_TXEN )
+  (   D9 /Ethernet_Phy/ETH_TXEN )
   (   C9 /Ethernet_Phy/ETH_TXD1 )
   (   A9 /Ethernet_Phy/ETH_COL )
   (   D8 /FPGA_Spartan6/ETH_TXER )
   (   C8 /FPGA_Spartan6/ETH_TXC )
-  (   B8 /Ethernet_Phy/ETH_RXER )
-  (   A8 /Ethernet_Phy/ETH_TXD3 )
+  (   B8 /FPGA_Spartan6/ETH_RXER )
+  (   A8 /FPGA_Spartan6/ETH_TXD3 )
   (   D7 /FPGA_Spartan6/ETH_MDC )
   (   C7 /FPGA_Spartan6/ETH_RESET_N )
   (   B7 +3.3V )
   (   A7 /FPGA_Spartan6/ETH_RXC )
   (   D6 /Ethernet_Phy/ETH_MDIO )
-  (   C6 /Ethernet_Phy/ETH_RXD2 )
-  (   B6 /Ethernet_Phy/ETH_RXD0 )
+  (   C6 /FPGA_Spartan6/ETH_RXD2 )
+  (   B6 /FPGA_Spartan6/ETH_RXD0 )
   (   A6 /FPGA_Spartan6/ETH_RXDV )
-  (   C5 /FPGA_Spartan6/ETH_RXD3 )
-  (   A5 /FPGA_Spartan6/ETH_RXD1 )
+  (   C5 /Ethernet_Phy/ETH_RXD3 )
+  (   A5 /Ethernet_Phy/ETH_RXD1 )
   (   B4 +3.3V )
-  (   A4 /FPGA_Spartan6/ETH_CLK )
+  (   A4 /Ethernet_Phy/ETH_CLK )
   (   A3 ? )
   (  U19 ? )
   (  T19 ? )
   (  R19 ? )
   (  P19 ? )
   (  B19 +3.3V )
-  (  B18 /FPGA_Spartan6/SD_DAT1 )
-  (  A18 /FPGA_Spartan6/SD_DAT0 )
+  (  B18 /Non_volatile_memories/SD_DAT1 )
+  (  A18 /Non_volatile_memories/SD_DAT0 )
   (  E17 +3.3V )
   (  D17 ? )
   (  C17 ? )
   (  A17 /FPGA_Spartan6/SD_CLK )
   (  E16 ? )
-  (  C16 /Non_volatile_memories/SD_CMD )
+  (  C16 /FPGA_Spartan6/SD_CMD )
   (  B16 /FPGA_Spartan6/SD_DAT3 )
   (  A16 /FPGA_Spartan6/SD_DAT2 )
   (  D15 /Non_volatile_memories/NF_CS1_N )
-  (  C15 /FPGA_Spartan6/NF_RE_N )
+  (  C15 /Non_volatile_memories/NF_RE_N )
   (  B15 +3.3V )
   (  A15 /Non_volatile_memories/NF_RNB )
   (  G14 +3.3V )
@@ -909,10 +909,10 @@
   (  C13 ? )
   (  A13 /Non_volatile_memories/NF_D2 )
   (  C12 /FPGA_Spartan6/NF_D0 )
-  (  B12 /Non_volatile_memories/NF_D3 )
+  (  B12 /FPGA_Spartan6/NF_D3 )
   (  A12 /FPGA_Spartan6/NF_D4 )
   (  D11 /FPGA_Spartan6/NF_D7 )
-  (  C11 /FPGA_Spartan6/NF_D5 )
+  (  C11 /Non_volatile_memories/NF_D5 )
   (  B11 +3.3V )
   (  A11 /FPGA_Spartan6/NF_D6 )
   (  J16 ? )
@@ -937,7 +937,7 @@
   (  E22 /FPGA_Spartan6/R_M1_A2 )
   (  D22 /FPGA_Spartan6/R_M1_A12 )
   (  C22 /FPGA_Spartan6/R_M1_A9 )
-  (  B22 ? )
+  (  B22 /USB/USBD_VM )
   (  W21 +2.5V )
   (  V21 /FPGA_Spartan6/R_M1_DQ14 )
   (  T21 /FPGA_Spartan6/R_M1_UDQS )
@@ -949,30 +949,30 @@
   (  M19 ? )
   (  L19 /FPGA_Spartan6/R_M1_LDM )
   (  K19 /FPGA_Spartan6/R_M1_A6 )
-  (  J19 /DDR_Banks/M1_CLK# )
+  (  J19 /FPGA_Spartan6/M1_CLK# )
   (  H19 /FPGA_Spartan6/R_M1_WE# )
   (  G19 /FPGA_Spartan6/R_M1_A10 )
   (  F19 /FPGA_Spartan6/R_M1_A11 )
   (  E19 +2.5V )
   (  D19 /USB/USBA_VP )
-  (  C19 /USB/USBA_VM )
+  (  C19 /FPGA_Spartan6/USBA_OE_N )
   (  U18 +2.5V )
-  (  P18 /FPGA_Spartan6/USBD_VM )
+  (  P18 ? )
   (  N18 +2.5V )
-  (  M18 /USB/USBD_SPD )
+  (  M18 ? )
   (  K18 ? )
   (  J18 +2.5V )
   (  H18 ? )
   (  F18 ? )
-  (  P17 /USB/USBD_VP )
-  (  M17 /FPGA_Spartan6/USBD_RCV )
+  (  P17 ? )
+  (  M17 ? )
   (  L17 ? )
   (  K17 /FPGA_Spartan6/R_M1_BA1 )
   (  J17 /FPGA_Spartan6/R_M1_BA0 )
   (  H17 ? )
   (  G17 ? )
   (  F17 /FPGA_Spartan6/USBA_RCV )
-  (  N16 /USB/USBD_OE_N )
+  (  N16 ? )
   (  M16 ? )
   (  L16 +2.5V )
   (  K16 ? )
@@ -1272,7 +1272,7 @@
   (    2 +3.3V )
  )
  ( /4C4320F3/4C5D7ECF $noname  R2 6.65K {Lib=R}
-  (    1 N-000401 )
+  (    1 N-000400 )
   (    2 GND )
  )
  ( /4C4320F3/4C5D7E43 $noname  C11 100nF {Lib=C}
@@ -1294,29 +1294,29 @@
  ( /4C4320F3/4C432132 $noname  U4 K8001 {Lib=K8001}
   (    1 /Ethernet_Phy/ETH_MDIO )
   (    2 /FPGA_Spartan6/ETH_MDC )
-  (    3 /FPGA_Spartan6/ETH_RXD3 )
-  (    4 /Ethernet_Phy/ETH_RXD2 )
-  (    5 /FPGA_Spartan6/ETH_RXD1 )
-  (    6 /Ethernet_Phy/ETH_RXD0 )
+  (    3 /Ethernet_Phy/ETH_RXD3 )
+  (    4 /FPGA_Spartan6/ETH_RXD2 )
+  (    5 /Ethernet_Phy/ETH_RXD1 )
+  (    6 /FPGA_Spartan6/ETH_RXD0 )
   (    7 +3.3V )
   (    8 GND )
   (    9 /FPGA_Spartan6/ETH_RXDV )
   (   10 /FPGA_Spartan6/ETH_RXC )
-  (   11 /Ethernet_Phy/ETH_RXER )
+  (   11 /FPGA_Spartan6/ETH_RXER )
   (   12 GND )
   (   13 +1.8V )
   (   14 /FPGA_Spartan6/ETH_TXER )
   (   15 /FPGA_Spartan6/ETH_TXC )
-  (   16 /FPGA_Spartan6/ETH_TXEN )
-  (   17 /FPGA_Spartan6/ETH_TXD0 )
+  (   16 /Ethernet_Phy/ETH_TXEN )
+  (   17 /Ethernet_Phy/ETH_TXD0 )
   (   18 /Ethernet_Phy/ETH_TXD1 )
   (   19 /FPGA_Spartan6/ETH_TXD2 )
-  (   20 /Ethernet_Phy/ETH_TXD3 )
+  (   20 /FPGA_Spartan6/ETH_TXD3 )
   (   21 /Ethernet_Phy/ETH_COL )
   (   22 /FPGA_Spartan6/ETH_CRS )
   (   23 GND )
   (   24 +3.3V )
-  (   25 /FPGA_Spartan6/ETH_INT )
+  (   25 /Ethernet_Phy/ETH_INT )
   (   26 /Ethernet_Phy/ETH_LED0 )
   (   27 /Ethernet_Phy/ETH_LED1 )
   (   28 ? )
@@ -1328,7 +1328,7 @@
   (   34 ? )
   (   35 GND )
   (   36 GND )
-  (   37 N-000401 )
+  (   37 N-000400 )
   (   38 /Ethernet_Phy/ETH_A3.3V )
   (   39 GND )
   (   40 /Ethernet_Phy/MAG_TX- )
@@ -1337,7 +1337,7 @@
   (   43 ? )
   (   44 GND )
   (   45 ? )
-  (   46 /FPGA_Spartan6/ETH_CLK )
+  (   46 /Ethernet_Phy/ETH_CLK )
   (   47 /Ethernet_Phy/ETH_PLL1.8V )
   (   48 /FPGA_Spartan6/ETH_RESET_N )
  )
@@ -1358,11 +1358,11 @@
   (    2 /Ethernet_Phy/MAG_RX+ )
  )
  ( /4C4320F3/4C5D71DB $noname  R8 220 {Lib=R}
-  (    1 N-000406 )
+  (    1 N-000405 )
   (    2 /Ethernet_Phy/ETH_LED1 )
  )
  ( /4C4320F3/4C5D719D $noname  R7 220 {Lib=R}
-  (    1 N-000405 )
+  (    1 N-000404 )
   (    2 /Ethernet_Phy/ETH_LED0 )
  )
  ( /4C4320F3/4C5D6F5A $noname  J4 RJ45-48025 {Lib=RJ45-48025}
@@ -1375,24 +1375,24 @@
   (    7 /Ethernet_Phy/MAG_RX+ )
   (    8 /Ethernet_Phy/MAG_RX- )
   (    9 +3.3V )
-  (   10 N-000405 )
+  (   10 N-000404 )
   (   11 +3.3V )
-  (   12 N-000406 )
+  (   12 N-000405 )
   (   13 /Ethernet_Phy/MAG_SHIELD )
   (   14 /Ethernet_Phy/MAG_SHIELD )
  )
  ( /4C421DD3/4C609C8E $noname  U3 MT46V32M16TG {Lib=MT46V32M16TG}
   (    1 +2.5V )
-  (    2 /DDR_Banks/M1_DQ0 )
+  (    2 /FPGA_Spartan6/M1_DQ0 )
   (    3 +2.5V )
   (    4 /FPGA_Spartan6/M1_DQ1 )
   (    5 /FPGA_Spartan6/M1_DQ2 )
   (    6 GND )
-  (    7 /FPGA_Spartan6/M1_DQ3 )
-  (    8 /DDR_Banks/M1_DQ4 )
+  (    7 /DDR_Banks/M1_DQ3 )
+  (    8 /FPGA_Spartan6/M1_DQ4 )
   (    9 +2.5V )
-  (   10 /FPGA_Spartan6/M1_DQ5 )
-  (   11 /FPGA_Spartan6/M1_DQ6 )
+  (   10 /DDR_Banks/M1_DQ5 )
+  (   11 /DDR_Banks/M1_DQ6 )
   (   12 GND )
   (   13 /FPGA_Spartan6/M1_DQ7 )
   (   14 ? )
@@ -1401,47 +1401,47 @@
   (   17 ? )
   (   18 +2.5V )
   (   19 ? )
-  (   20 /FPGA_Spartan6/M1_LDM )
-  (   21 /DDR_Banks/M1_WE# )
+  (   20 /DDR_Banks/M1_LDM )
+  (   21 /FPGA_Spartan6/M1_WE# )
   (   22 /FPGA_Spartan6/M1_CAS# )
   (   23 /FPGA_Spartan6/M1_RAS# )
-  (   24 /DDR_Banks/M1_CS# )
+  (   24 /FPGA_Spartan6/M1_CS# )
   (   25 ? )
   (   26 /DDR_Banks/M1_BA0 )
-  (   27 /DDR_Banks/M1_BA1 )
+  (   27 /FPGA_Spartan6/M1_BA1 )
   (   28 /FPGA_Spartan6/M1_A10 )
-  (   29 /FPGA_Spartan6/M1_A0 )
-  (   30 /DDR_Banks/M1_A1 )
+  (   29 /DDR_Banks/M1_A0 )
+  (   30 /FPGA_Spartan6/M1_A1 )
   (   31 /FPGA_Spartan6/M1_A2 )
   (   32 /FPGA_Spartan6/M1_A3 )
   (   33 +2.5V )
   (   34 GND )
   (   35 /FPGA_Spartan6/M1_A4 )
-  (   36 /FPGA_Spartan6/M1_A5 )
-  (   37 /DDR_Banks/M1_A6 )
+  (   36 /DDR_Banks/M1_A5 )
+  (   37 /FPGA_Spartan6/M1_A6 )
   (   38 /FPGA_Spartan6/M1_A7 )
-  (   39 /FPGA_Spartan6/M1_A8 )
-  (   40 /FPGA_Spartan6/M1_A9 )
-  (   41 /DDR_Banks/M1_A11 )
-  (   42 /FPGA_Spartan6/M1_A12 )
+  (   39 /DDR_Banks/M1_A8 )
+  (   40 /DDR_Banks/M1_A9 )
+  (   41 /FPGA_Spartan6/M1_A11 )
+  (   42 /DDR_Banks/M1_A12 )
   (   43 ? )
-  (   44 /DDR_Banks/M1_CLK# )
-  (   45 /FPGA_Spartan6/M1_CKE )
-  (   46 /FPGA_Spartan6/M1_CLK )
+  (   44 /FPGA_Spartan6/M1_CLK# )
+  (   45 /DDR_Banks/M1_CKE )
+  (   46 /DDR_Banks/M1_CLK )
   (   47 /FPGA_Spartan6/M1_UDM )
   (   48 GND )
   (   49 /DDR_Banks/M1_VREF )
   (   50 ? )
-  (   51 /FPGA_Spartan6/M1_UDQS )
+  (   51 /DDR_Banks/M1_UDQS )
   (   52 GND )
   (   53 ? )
   (   54 /FPGA_Spartan6/M1_DQ8 )
   (   55 +2.5V )
-  (   56 /DDR_Banks/M1_DQ9 )
-  (   57 /FPGA_Spartan6/M1_DQ10 )
+  (   56 /FPGA_Spartan6/M1_DQ9 )
+  (   57 /DDR_Banks/M1_DQ10 )
   (   58 GND )
   (   59 /FPGA_Spartan6/M1_DQ11 )
-  (   60 /FPGA_Spartan6/M1_DQ12 )
+  (   60 /DDR_Banks/M1_DQ12 )
   (   61 +2.5V )
   (   62 /FPGA_Spartan6/M1_DQ13 )
   (   63 /FPGA_Spartan6/M1_DQ14 )
@@ -1547,70 +1547,70 @@
  )
  ( /4C421DD3/4C609B99 $noname  U2 MT46V32M16TG {Lib=MT46V32M16TG}
   (    1 +2.5V )
-  (    2 /FPGA_Spartan6/M0_DQ0 )
+  (    2 /DDR_Banks/M0_DQ0 )
   (    3 +2.5V )
-  (    4 /FPGA_Spartan6/M0_DQ1 )
-  (    5 /FPGA_Spartan6/M0_DQ2 )
+  (    4 /DDR_Banks/M0_DQ1 )
+  (    5 /DDR_Banks/M0_DQ2 )
   (    6 GND )
   (    7 /FPGA_Spartan6/M0_DQ3 )
-  (    8 /DDR_Banks/M0_DQ4 )
+  (    8 /FPGA_Spartan6/M0_DQ4 )
   (    9 +2.5V )
   (   10 /DDR_Banks/M0_DQ5 )
   (   11 /FPGA_Spartan6/M0_DQ6 )
   (   12 GND )
-  (   13 /DDR_Banks/M0_DQ7 )
+  (   13 /FPGA_Spartan6/M0_DQ7 )
   (   14 ? )
   (   15 +2.5V )
-  (   16 /DDR_Banks/M0_LDQS )
+  (   16 /FPGA_Spartan6/M0_LDQS )
   (   17 ? )
   (   18 +2.5V )
   (   19 ? )
-  (   20 /DDR_Banks/M0_LDM )
-  (   21 /FPGA_Spartan6/M0_WE# )
+  (   20 /FPGA_Spartan6/M0_LDM )
+  (   21 /DDR_Banks/M0_WE# )
   (   22 /FPGA_Spartan6/M0_CAS# )
-  (   23 /FPGA_Spartan6/M0_RAS# )
+  (   23 /DDR_Banks/M0_RAS# )
   (   24 GND )
   (   25 ? )
-  (   26 /FPGA_Spartan6/M0_BA0 )
+  (   26 /DDR_Banks/M0_BA0 )
   (   27 /FPGA_Spartan6/M0_BA1 )
   (   28 /FPGA_Spartan6/M0_A10 )
-  (   29 /DDR_Banks/M0_A0 )
+  (   29 /FPGA_Spartan6/M0_A0 )
   (   30 /FPGA_Spartan6/M0_A1 )
   (   31 /FPGA_Spartan6/M0_A2 )
-  (   32 /DDR_Banks/M0_A3 )
+  (   32 /FPGA_Spartan6/M0_A3 )
   (   33 +2.5V )
   (   34 GND )
-  (   35 /DDR_Banks/M0_A4 )
-  (   36 /FPGA_Spartan6/M0_A5 )
-  (   37 /FPGA_Spartan6/M0_A6 )
+  (   35 /FPGA_Spartan6/M0_A4 )
+  (   36 /DDR_Banks/M0_A5 )
+  (   37 /DDR_Banks/M0_A6 )
   (   38 /FPGA_Spartan6/M0_A7 )
-  (   39 /FPGA_Spartan6/M0_A8 )
-  (   40 /DDR_Banks/M0_A9 )
-  (   41 /DDR_Banks/M0_A11 )
-  (   42 /FPGA_Spartan6/M0_A12 )
+  (   39 /DDR_Banks/M0_A8 )
+  (   40 /FPGA_Spartan6/M0_A9 )
+  (   41 /FPGA_Spartan6/M0_A11 )
+  (   42 /DDR_Banks/M0_A12 )
   (   43 ? )
   (   44 /FPGA_Spartan6/M0_CLK# )
   (   45 /DDR_Banks/M0_CKE )
-  (   46 /FPGA_Spartan6/M0_CLK )
-  (   47 /FPGA_Spartan6/M0_UDM )
+  (   46 /DDR_Banks/M0_CLK )
+  (   47 /DDR_Banks/M0_UDM )
   (   48 GND )
   (   49 /DDR_Banks/M0_VREF )
   (   50 ? )
-  (   51 /FPGA_Spartan6/M0_UDQS )
+  (   51 /DDR_Banks/M0_UDQS )
   (   52 GND )
   (   53 ? )
-  (   54 /FPGA_Spartan6/M0_DQ8 )
+  (   54 /DDR_Banks/M0_DQ8 )
   (   55 +2.5V )
   (   56 /FPGA_Spartan6/M0_DQ9 )
-  (   57 /DDR_Banks/M0_DQ10 )
+  (   57 /FPGA_Spartan6/M0_DQ10 )
   (   58 GND )
   (   59 /FPGA_Spartan6/M0_DQ11 )
   (   60 /FPGA_Spartan6/M0_DQ12 )
   (   61 +2.5V )
   (   62 /FPGA_Spartan6/M0_DQ13 )
-  (   63 /DDR_Banks/M0_DQ14 )
+  (   63 /FPGA_Spartan6/M0_DQ14 )
   (   64 GND )
-  (   65 /FPGA_Spartan6/M0_DQ15 )
+  (   65 /DDR_Banks/M0_DQ15 )
   (   66 GND )
  )
 )
@@ -2254,42 +2254,42 @@ Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO"
  U8 1
  U1 T5
 Net 2 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK"
- U8 6
  U1 AA21
+ U8 6
 Net 3 "/Non volatile memories/NF_RNB" "NF_RNB"
  U1 A15
- U5 7
  U5 6
-Net 4 "/FPGA Spartan6/NF_RE_N" "NF_RE_N"
- U5 8
+ U5 7
+Net 4 "/Non volatile memories/NF_RE_N" "NF_RE_N"
  U1 C15
+ U5 8
 Net 5 "/Non volatile memories/NF_CS1_N" "NF_CS1_N"
- U1 D15
  U5 9
+ U1 D15
 Net 6 "/Non volatile memories/NF_CLE" "NF_CLE"
- U5 16
  U1 B14
+ U5 16
 Net 7 "/Non volatile memories/NF_WE_N" "NF_WE_N"
- U1 C14
  U5 18
+ U1 C14
 Net 8 "/Ethernet Phy/ETH_COL" "ETH_COL"
- U1 A9
  U4 21
-Net 9 "/FPGA Spartan6/USBD_VM" "USBD_VM"
- U1 P18
+ U1 A9
+Net 9 "/USB/USBD_VM" "USBD_VM"
  U7 4
+ U1 B22
 Net 10 "/FPGA Spartan6/USBD_RCV" "USBD_RCV"
  U7 2
- U1 M17
-Net 11 "/USB/USBD_OE_N" "USBD_OE_N"
- U1 N16
+ U1 A20
+Net 11 "/FPGA Spartan6/USBD_OE_N" "USBD_OE_N"
+ U1 A21
  U7 9
 Net 12 "/USB/USBD_SPD" "USBD_SPD"
  U7 1
- U1 M18
-Net 13 "/USB/USBD_VP" "USBD_VP"
+ U1 B20
+Net 13 "/FPGA Spartan6/USBD_VP" "USBD_VP"
+ U1 B21
  U7 3
- U1 P17
 Net 14 "/FPGA Spartan6/ETH_TXC" "ETH_TXC"
  U4 15
  U1 C8
@@ -2300,203 +2300,204 @@ Net 16 "/FPGA Spartan6/USBA_SPD" "USBA_SPD"
  U1 F16
  U6 1
 Net 17 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N"
- U1 B20
+ U1 C19
  U6 9
 Net 18 "/FPGA Spartan6/USBA_RCV" "USBA_RCV"
- U1 F17
  U6 2
+ U1 F17
 Net 19 "/USB/USBA_VP" "USBA_VP"
  U1 D19
  U6 3
 Net 20 "/USB/USBA_VM" "USBA_VM"
- U1 C19
  U6 4
+ U1 D20
 Net 21 "/FPGA Spartan6/ETH_CRS" "ETH_CRS"
  U4 22
  U1 B10
-Net 22 "/Non volatile memories/SD_CMD" "SD_CMD"
- U1 C16
+Net 22 "/FPGA Spartan6/SD_CMD" "SD_CMD"
  J1 3
+ U1 C16
 Net 23 "/FPGA Spartan6/ETH_MDC" "ETH_MDC"
  U1 D7
  U4 2
 Net 24 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO"
+ U1 D6
  R1 1
  U4 1
- U1 D6
 Net 25 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N"
- U1 C7
  U4 48
+ U1 C7
 Net 26 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV"
- U1 A6
  U4 9
-Net 27 "/Ethernet Phy/ETH_RXER" "ETH_RXER"
+ U1 A6
+Net 27 "/FPGA Spartan6/ETH_RXER" "ETH_RXER"
  U4 11
  U1 B8
-Net 28 "/DDR Banks/M1_CS#" "M1_CS#"
+Net 28 "/FPGA Spartan6/M1_CS#" "M1_CS#"
  U3 24
  R20 2
 Net 29 "/FPGA Spartan6/M1_UDM" "M1_UDM"
- U3 47
  R18 2
+ U3 47
 Net 30 "/FPGA Spartan6/M1_LDQS" "M1_LDQS"
- U3 16
  RP3 8
-Net 31 "/FPGA Spartan6/M1_LDM" "M1_LDM"
+ U3 16
+Net 31 "/DDR Banks/M1_LDM" "M1_LDM"
  U3 20
  RP3 7
-Net 32 "/FPGA Spartan6/M1_UDQS" "M1_UDQS"
- R19 2
+Net 32 "/DDR Banks/M1_UDQS" "M1_UDQS"
  U3 51
-Net 33 "/FPGA Spartan6/M0_UDQS" "M0_UDQS"
+ R19 2
+Net 33 "/DDR Banks/M0_UDQS" "M0_UDQS"
  R22 2
  U2 51
-Net 34 "/DDR Banks/M0_LDM" "M0_LDM"
- U2 20
+Net 34 "/FPGA Spartan6/M0_LDM" "M0_LDM"
  RP16 7
-Net 35 "/FPGA Spartan6/M1_CKE" "M1_CKE"
- R17 2
+ U2 20
+Net 35 "/DDR Banks/M1_CKE" "M1_CKE"
  U3 45
-Net 36 "/FPGA Spartan6/M1_CLK" "M1_CLK"
+ R17 2
+Net 36 "/DDR Banks/M1_CLK" "M1_CLK"
  U3 46
- U1 H20
  R16 2
-Net 37 "/DDR Banks/M1_CLK#" "M1_CLK#"
+ U1 H20
+Net 37 "/FPGA Spartan6/M1_CLK#" "M1_CLK#"
  U3 44
  R16 1
  U1 J19
 Net 38 "GND" "GND"
- U1 E7
- C26 2
- C39 2
- C21 2
- C47 2
- U1 R5
- U1 L5
- U1 G5
- U1 B5
- U1 V4
- U1 D4
- C31 2
- C53 2
- C29 2
- C28 2
- C67 2
- C45 2
- C42 2
- C69 2
- C33 2
- U1 J13
- C54 2
- C23 2
- U1 U7
- C25 2
- U1 H7
- C24 2
- U3 58
- C34 2
- U5 36
- U1 A1
+ U8 4
+ C66 2
+ U2 52
+ C72 2
+ C73 2
+ U2 34
+ U2 24
  C71 2
+ C34 2
+ U3 58
  C70 2
- C64 2
- C50 2
- C27 2
- U1 U2
- U1 N2
- U1 J2
+ C39 2
+ C48 2
+ C45 2
+ C69 2
+ C54 2
+ C33 2
+ C23 2
+ C25 2
+ C24 2
+ C26 2
+ C21 2
+ C42 2
  C57 2
+ C27 2
  C60 2
  C63 2
- U1 E2
- U1 N21
- U1 U21
- C48 2
- U1 J21
- U1 P14
- U1 M14
- U5 13
- U1 K14
- U1 N13
- U1 L13
+ C40 2
  C43 2
- C41 2
  C75 1
  C52 2
  C46 2
- C44 2
  C49 2
  C32 2
  C51 2
  C30 2
  C74 2
- U1 AB1
- U1 K12
- U1 M12
- U1 P12
- U1 E21
- U1 A22
- U1 B13
- C40 2
- U1 N11
- U1 L11
- U1 J11
- U1 AA5
- U1 N15
- U1 J15
- U1 E15
- U1 V14
- U1 W16
- C65 2
+ C31 2
+ C53 2
+ C29 2
+ C41 2
+ C28 2
+ C67 2
+ U1 N17
+ C56 2
+ U1 D18
+ U1 G18
+ U1 L18
+ U1 R18
+ U1 W19
+ U1 AA9
+ U1 AB22
+ U1 AA13
+ U1 AA17
+ U1 U7
+ U1 W7
+ U1 B9
+ U1 J9
+ U1 L9
+ U1 N9
+ U1 K10
+ U1 M10
+ U1 P10
+ U1 V10
  C62 2
  C59 2
- U1 R18
- U1 L18
- U1 G18
- U1 D18
- U2 6
- C55 2
- U1 N17
- C68 2
+ U1 W16
  U1 B17
+ C44 2
+ U1 B13
+ U1 A22
+ U1 P12
+ U1 M12
+ U1 K12
+ U1 L13
+ U1 N13
+ U1 K14
+ U1 M14
+ U1 P14
+ U1 V14
+ U1 E15
+ U1 J15
+ U1 N15
+ U1 AA5
+ U1 AB1
+ U1 J11
+ U1 L11
+ U1 N11
+ U1 U21
+ U1 N21
+ U1 E21
+ U1 J21
+ U1 E11
+ U5 36
+ U1 A1
+ U1 E2
+ C50 2
+ U1 J2
+ U1 N2
+ U1 U2
+ U1 D4
+ U1 V4
+ U1 B5
+ U1 G5
+ U1 L5
+ U1 R5
+ C47 2
+ U1 E7
+ U1 H7
+ U1 J13
+ U5 13
+ C64 2
+ C61 2
+ R12 2
+ R14 2
+ C22 2
+ U2 12
+ U2 66
+ U2 64
+ C18 2
+ C20 2
  J1 CASE
  J1 CASE
  J1 CASE
  J1 COM
  J1 6
- U1 V10
- U2 52
- C73 2
- U2 12
- U1 P10
- U1 M10
- U1 K10
- U2 66
- U8 4
- C66 2
- C61 2
- U2 34
+ U2 6
  C58 2
- C56 2
- U2 24
- U1 E11
- U1 W7
- U1 AA17
- U1 AA13
- U1 AB22
- U1 AA9
- R12 2
- R14 2
- U1 W19
- C22 2
- U1 N9
- U2 64
- C18 2
- C72 2
- U1 L9
- U1 J9
- C20 2
- U1 B9
+ C55 2
+ C68 2
+ C65 2
+ R15 2
  C38 2
  V3 2
  V4 2
@@ -2504,11 +2505,11 @@ Net 38 "GND" "GND"
  C36 2
  C35 2
  L7 2
- R15 2
  U3 64
  U3 34
  U3 52
  C9 2
+ C6 2
  R31 2
  C89 2
  V5 2
@@ -2534,98 +2535,97 @@ Net 38 "GND" "GND"
  U10 PAD
  U13 6
  U13 7
- U7 6
  C13 2
  C14 2
+ C15 2
+ U7 6
  U7 7
  U6 6
  U6 7
- R10 2
  L5 2
- C15 2
  V2 2
  V1 2
  C16 2
- U4 12
+ R10 2
  U4 23
+ U4 12
+ C11 2
  C10 2
  C12 2
  R9 2
- U4 8
+ C7 2
  C5 2
  C3 2
  C1 2
  R2 2
- C11 2
  U4 44
  U4 35
  U4 36
+ U4 8
  C76 2
- U2 48
- U2 58
  C77 2
+ U2 58
+ U2 48
  U3 6
  J4 4
+ J4 5
+ U4 39
  U3 12
  U3 48
- C6 2
  C4 2
  C2 2
  C8 2
- C7 2
  U3 66
- J4 5
- U4 39
 Net 39 "/FPGA Spartan6/M0_CLK#" "M0_CLK#"
  R21 2
- U1 H3
  U2 44
-Net 40 "/FPGA Spartan6/M0_CLK" "M0_CLK"
- R21 1
+ U1 H3
+Net 40 "/DDR Banks/M0_CLK" "M0_CLK"
  U1 H4
  U2 46
+ R21 1
 Net 41 "/DDR Banks/M0_CKE" "M0_CKE"
  U2 45
  R24 2
 Net 42 "/FPGA Spartan6/M0_CAS#" "M0_CAS#"
  U2 22
  RP16 5
-Net 43 "/DDR Banks/M1_WE#" "M1_WE#"
+Net 43 "/FPGA Spartan6/M1_WE#" "M1_WE#"
  U3 21
  RP3 6
 Net 44 "/FPGA Spartan6/M1_RAS#" "M1_RAS#"
- RP2 8
  U3 23
-Net 45 "/FPGA Spartan6/M0_RAS#" "M0_RAS#"
+ RP2 8
+Net 45 "/DDR Banks/M0_RAS#" "M0_RAS#"
  RP15 8
  U2 23
-Net 46 "/FPGA Spartan6/M0_WE#" "M0_WE#"
+Net 46 "/DDR Banks/M0_WE#" "M0_WE#"
  RP16 6
  U2 21
-Net 47 "/FPGA Spartan6/ETH_INT" "ETH_INT"
+Net 47 "/Ethernet Phy/ETH_INT" "ETH_INT"
  U4 25
  U1 A10
-Net 48 "/FPGA Spartan6/ETH_CLK" "ETH_CLK"
+Net 48 "/Ethernet Phy/ETH_CLK" "ETH_CLK"
  U4 46
  U1 A4
 Net 49 "/FPGA Spartan6/ETH_TXER" "ETH_TXER"
- U1 D8
  U4 14
-Net 50 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN"
+ U1 D8
+Net 50 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN"
  U4 16
  U1 D9
-Net 51 "/DDR Banks/M0_LDQS" "M0_LDQS"
+Net 51 "/FPGA Spartan6/M0_LDQS" "M0_LDQS"
  RP16 8
  U2 16
-Net 52 "/FPGA Spartan6/M0_UDM" "M0_UDM"
+Net 52 "/DDR Banks/M0_UDM" "M0_UDM"
  U2 47
  R23 2
 Net 53 "/FPGA Spartan6/M1_CAS#" "M1_CAS#"
  U3 22
  RP3 5
 Net 54 "/FPGA Spartan6/NF_ALE" "NF_ALE"
- U5 17
  U1 A14
+ U5 17
 Net 55 "/FPGA Spartan6/SD_CLK" "SD_CLK"
  U1 A17
  J1 5
@@ -2639,8 +2639,8 @@ Net 58 "/DBG_PRG/FPGA_TDI" "FPGA_TDI"
  U1 E18
  J6 7
 Net 59 "/DBG_PRG/FPGA_TDO" "FPGA_TDO"
- U1 A19
  J6 5
+ U1 A19
 Net 64 "+2.5V" "+2.5V"
  R11 1
  C19 1
@@ -2649,6 +2649,7 @@ Net 64 "+2.5V" "+2.5V"
  U2 18
  U2 61
  U2 33
+ C23 1
  C22 1
  C33 1
  C28 1
@@ -2664,7 +2665,6 @@ Net 64 "+2.5V" "+2.5V"
  C26 1
  C24 1
  C25 1
- C23 1
  U1 N5
  U1 J5
  U1 C21
@@ -2727,351 +2727,351 @@ Net 64 "+2.5V" "+2.5V"
  U3 1
  C37 1
  U13 15
+ U7 15
  C15 1
  U6 15
- U7 15
  C88 1
  C77 1
- C68 1
- C59 1
- C62 1
- C65 1
  C56 1
+ C59 1
+ C68 1
+ C65 1
+ C62 1
 Net 67 "/DDR Banks/M0_VREF" "M0_VREF"
+ C17 2
+ U2 49
  R12 1
  R11 2
  C18 1
- C17 2
- U2 49
 Net 68 "/DDR Banks/M1_VREF" "M1_VREF"
  U3 49
  C20 1
  C19 2
- R14 1
  R13 2
+ R14 1
 Net 107 "+3.3V" "+3.3V"
- R6 1
- C72 1
- R1 2
- C11 1
- U4 24
- U1 B7
- U1 B4
- J1 4
  U1 B19
- U1 E17
- U1 B15
- U1 G14
- R5 1
+ C11 1
  J4 11
+ J4 9
+ R5 1
  C10 1
- C41 1
- R4 1
- R3 1
- U4 7
- C3 1
- U1 E9
- C1 1
- C73 1
- U5 37
- U5 19
+ U1 E17
+ J1 4
  U5 12
- U1 E13
- U1 Y20
- U1 B11
- U1 G10
+ C5 1
+ C3 1
+ C1 1
+ U1 B15
+ C72 1
+ U1 E9
+ U1 B7
+ J4 3
+ J4 6
+ R3 1
+ U1 B4
+ R4 1
+ R6 1
  R30 1
  R29 1
+ U5 19
+ U5 37
+ U1 Y20
+ U1 G14
+ R1 2
+ U1 E13
+ U4 24
+ U4 7
+ U1 B11
+ U1 G10
+ C41 1
+ U13 14
+ U13 12
+ U6 14
+ U6 12
+ U7 14
+ U7 12
+ C14 1
+ C13 1
+ C35 1
+ C36 1
  L8 1
  C74 1
- C86 1
- C87 1
- U13 12
- U13 14
- C36 1
- C35 1
- C13 1
- C14 1
- U7 12
- U7 14
- U6 12
- U6 14
- C79 1
- C80 1
- R26 1
- J4 9
- J4 6
- J4 3
- C44 1
  C81 1
- C5 1
- L2 1
- C47 1
- C50 1
  C75 2
+ R26 1
+ C80 1
+ C79 1
+ L2 1
+ C50 1
+ C86 1
+ C47 1
+ C87 1
+ C44 1
+ C73 1
 Net 108 "VCCO2" "VCCO2"
+ U1 AA19
+ U1 W5
+ U1 AA7
+ C67 1
  U8 8
  U1 V16
+ U1 AA3
+ U1 AA15
+ C69 1
+ U1 AA11
+ U1 T9
+ C64 1
  U1 T13
- U1 W5
  C55 1
  U1 V12
- U1 T9
- U1 AA7
- U1 AA15
- C58 1
- C67 1
- C64 1
- C69 1
- U1 AA3
  C61 1
+ C58 1
  U1 V8
- U1 AA11
- U1 AA19
-Net 110 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1"
- U1 K17
- RP2 3
-Net 111 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0"
+Net 110 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0"
  RP2 2
  U1 J17
-Net 112 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#"
- U1 H21
+Net 111 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#"
  RP2 1
-Net 113 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#"
- RP3 4
+ U1 H21
+Net 112 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#"
  U1 H22
-Net 114 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#"
- U1 H19
+ RP3 4
+Net 113 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#"
  RP3 3
-Net 115 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM"
- RP3 2
+ U1 H19
+Net 114 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM"
  U1 L19
-Net 116 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS"
- RP3 1
+ RP3 2
+Net 115 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS"
  U1 L20
+ RP3 1
+Net 116 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1"
+ RP2 3
+ U1 K17
 Net 125 "/FPGA Spartan6/R_M0_A3" "R_M0_A3"
- RP14 4
  U1 K6
+ RP14 4
 Net 127 "/FPGA Spartan6/R_M0_A7" "R_M0_A7"
- RP17 1
  U1 H6
+ RP17 1
 Net 132 "/FPGA Spartan6/R_M0_A2" "R_M0_A2"
  U1 H5
  RP14 3
 Net 142 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE"
  U1 D21
  R17 1
-Net 147 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12"
- RP8 5
+Net 145 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12"
  U1 U20
-Net 149 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10"
+ RP8 5
+Net 147 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10"
  U1 R20
  RP9 7
-Net 151 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0"
- U1 N20
+Net 149 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0"
  RP5 1
-Net 152 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM"
- R18 1
+ U1 N20
+Net 150 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM"
  U1 M20
-Net 153 "/FPGA Spartan6/R_M1_A5" "R_M1_A5"
- RP6 6
+ R18 1
+Net 151 "/FPGA Spartan6/R_M1_A5" "R_M1_A5"
  U1 K20
-Net 154 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4"
+ RP6 6
+Net 152 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4"
  RP4 1
  U1 J20
-Net 155 "/FPGA Spartan6/R_M1_A3" "R_M1_A3"
- U1 G20
+Net 153 "/FPGA Spartan6/R_M1_A3" "R_M1_A3"
  RP1 4
-Net 157 "/FPGA Spartan6/R_M1_A7" "R_M1_A7"
+ U1 G20
+Net 155 "/FPGA Spartan6/R_M1_A7" "R_M1_A7"
  U1 E20
  RP6 8
-Net 159 "/FPGA Spartan6/R_M1_A8" "R_M1_A8"
- RP7 5
+Net 156 "/FPGA Spartan6/R_M1_A8" "R_M1_A8"
  U1 C20
-Net 168 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2"
- U1 M2
- RP13 3
-Net 169 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6"
+ RP7 5
+Net 164 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6"
  RP12 3
  U1 K2
-Net 170 "/FPGA Spartan6/R_M0_A0" "R_M0_A0"
+Net 165 "/FPGA Spartan6/R_M0_A0" "R_M0_A0"
  RP14 1
  U1 H2
-Net 175 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15"
+Net 170 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15"
  U1 V1
  RP10 4
-Net 176 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13"
+Net 171 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13"
  RP10 2
  U1 U1
-Net 178 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11"
- U1 R1
+Net 173 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11"
  RP11 4
-Net 179 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9"
+ U1 R1
+Net 174 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9"
  RP11 2
  U1 P1
-Net 180 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1"
- U1 N1
+Net 175 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1"
  RP13 2
-Net 181 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3"
+ U1 N1
+Net 176 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3"
  U1 M1
  RP13 4
-Net 183 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7"
+Net 178 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7"
  U1 K1
  RP12 4
-Net 184 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5"
- U1 J1
+Net 179 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5"
  RP12 2
-Net 185 "/FPGA Spartan6/R_M0_A1" "R_M0_A1"
- U1 H1
+ U1 J1
+Net 180 "/FPGA Spartan6/R_M0_A1" "R_M0_A1"
  RP14 2
-Net 186 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1"
- U1 G1
+ U1 H1
+Net 181 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1"
  RP15 3
-Net 188 "/FPGA Spartan6/R_M0_A9" "R_M0_A9"
- RP18 3
+ U1 G1
+Net 183 "/FPGA Spartan6/R_M0_A9" "R_M0_A9"
  U1 E1
-Net 189 "/FPGA Spartan6/R_M0_A12" "R_M0_A12"
- RP18 1
+ RP18 3
+Net 184 "/FPGA Spartan6/R_M0_A12" "R_M0_A12"
  U1 D1
-Net 190 "/FPGA Spartan6/R_M0_A11" "R_M0_A11"
- RP18 2
+ RP18 1
+Net 185 "/FPGA Spartan6/R_M0_A11" "R_M0_A11"
  U1 C1
-Net 193 "/FPGA Spartan6/R_M0_A6" "R_M0_A6"
- U1 J4
+ RP18 2
+Net 189 "/FPGA Spartan6/R_M0_A6" "R_M0_A6"
  RP17 2
-Net 194 "/FPGA Spartan6/R_M0_A10" "R_M0_A10"
+ U1 J4
+Net 190 "/FPGA Spartan6/R_M0_A10" "R_M0_A10"
  RP15 4
  U1 G4
-Net 199 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12"
- U1 U3
+Net 195 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12"
  RP10 1
-Net 201 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10"
+ U1 U3
+Net 197 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10"
  RP11 3
  U1 R3
-Net 203 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0"
+Net 199 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0"
  U1 N3
  RP13 1
-Net 204 "/FPGA Spartan6/R_M0_A5" "R_M0_A5"
+Net 200 "/FPGA Spartan6/R_M0_A5" "R_M0_A5"
  RP17 3
  U1 K3
-Net 205 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4"
- U1 J3
+Net 201 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4"
  RP12 1
-Net 206 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0"
+ U1 J3
+Net 202 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0"
  RP15 2
  U1 G3
-Net 207 "/FPGA Spartan6/R_M0_A4" "R_M0_A4"
- RP17 4
+Net 203 "/FPGA Spartan6/R_M0_A4" "R_M0_A4"
  U1 F3
-Net 208 "/FPGA Spartan6/R_M0_A8" "R_M0_A8"
+ RP17 4
+Net 204 "/FPGA Spartan6/R_M0_A8" "R_M0_A8"
  RP18 4
  U1 E3
-Net 213 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14"
+Net 209 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14"
  RP10 3
  U1 V2
-Net 214 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8"
+Net 210 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8"
  RP11 1
  U1 P2
-Net 228 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15"
- U1 V22
+Net 211 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2"
+ RP13 3
+ U1 M2
+Net 225 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15"
  RP8 8
-Net 229 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13"
+ U1 V22
+Net 226 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13"
  RP8 6
  U1 U22
-Net 231 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11"
- U1 R22
+Net 228 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11"
  RP9 8
-Net 232 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9"
+ U1 R22
+Net 229 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9"
  U1 P22
  RP9 6
-Net 233 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1"
- RP5 2
+Net 230 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1"
  U1 N22
-Net 234 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3"
+ RP5 2
+Net 231 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3"
  RP5 4
  U1 M22
-Net 236 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7"
+Net 233 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7"
  U1 K22
  RP4 4
-Net 237 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5"
- U1 J22
+Net 234 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5"
  RP4 2
-Net 239 "/FPGA Spartan6/R_M1_A1" "R_M1_A1"
- U1 F22
+ U1 J22
+Net 236 "/FPGA Spartan6/R_M1_A1" "R_M1_A1"
  RP1 2
-Net 240 "/FPGA Spartan6/R_M1_A2" "R_M1_A2"
+ U1 F22
+Net 237 "/FPGA Spartan6/R_M1_A2" "R_M1_A2"
  RP1 3
  U1 E22
-Net 241 "/FPGA Spartan6/R_M1_A12" "R_M1_A12"
- U1 D22
+Net 238 "/FPGA Spartan6/R_M1_A12" "R_M1_A12"
  RP7 8
-Net 242 "/FPGA Spartan6/R_M1_A9" "R_M1_A9"
+ U1 D22
+Net 239 "/FPGA Spartan6/R_M1_A9" "R_M1_A9"
  RP7 6
  U1 C22
-Net 244 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14"
+Net 240 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14"
  RP8 7
  U1 V21
-Net 245 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8"
- RP9 5
+Net 241 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8"
  U1 P21
-Net 246 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2"
- U1 M21
+ RP9 5
+Net 242 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2"
  RP5 3
-Net 247 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6"
+ U1 M21
+Net 243 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6"
  U1 K21
  RP4 3
-Net 248 "/FPGA Spartan6/R_M1_A0" "R_M1_A0"
+Net 244 "/FPGA Spartan6/R_M1_A0" "R_M1_A0"
  U1 F21
  RP1 1
-Net 249 "/FPGA Spartan6/R_M1_A6" "R_M1_A6"
+Net 245 "/FPGA Spartan6/R_M1_A6" "R_M1_A6"
  RP6 7
  U1 K19
-Net 250 "/FPGA Spartan6/R_M1_A10" "R_M1_A10"
+Net 246 "/FPGA Spartan6/R_M1_A10" "R_M1_A10"
  RP2 4
  U1 G19
-Net 251 "/FPGA Spartan6/R_M1_A11" "R_M1_A11"
- RP7 7
+Net 247 "/FPGA Spartan6/R_M1_A11" "R_M1_A11"
  U1 F19
+ RP7 7
 Net 264 "" ""
  U1 Y22
  R30 2
 Net 381 "+1.2V" "+1.2V"
  C83 1
+ U1 J8
  U1 K13
  U1 M13
  U1 P13
- C84 1
  C76 1
- U1 J14
- U1 L14
- U1 N14
- U1 R14
- C39 1
- C42 1
- C45 1
- C48 1
- U1 J8
- R28 1
- L9 1
- C85 1
- U1 K9
- U1 M9
- U1 P9
- U1 J10
- U1 L10
+ C84 1
  U1 N10
+ U1 L10
+ U1 J10
+ U1 P9
+ U1 M9
+ U1 K9
+ U1 N12
  U1 K11
  U1 M11
  U1 P11
- U1 J12
+ C48 1
+ C45 1
  U1 L12
- U1 N12
+ U1 J12
+ C42 1
+ U1 J14
+ U1 L14
+ U1 N14
+ C39 1
+ U1 R14
+ C85 1
+ L9 1
+ R28 1
 Net 382 "" ""
  R29 2
  U1 AA1
 Net 383 "/FPGA Spartan6/R_M0_CAS#" "R_M0_CAS#"
- U1 K4
  RP16 4
+ U1 K4
 Net 384 "/FPGA Spartan6/R_M0_WE#" "R_M0_WE#"
  RP16 3
  U1 F2
@@ -3082,140 +3082,140 @@ Net 386 "/FPGA Spartan6/R_M0_LDQS" "R_M0_LDQS"
  RP16 1
  U1 L3
 Net 387 "/FPGA Spartan6/R_M0_UDM" "R_M0_UDM"
- R23 1
  U1 M3
-Net 388 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS"
- U1 T2
- R22 1
-Net 389 "/FPGA Spartan6/R_M0_CKE" "R_M0_CKE"
- R24 1
- U1 D2
-Net 390 "/FPGA Spartan6/R_M0_RAS#" "R_M0_RAS#"
+ R23 1
+Net 388 "/FPGA Spartan6/R_M0_RAS#" "R_M0_RAS#"
  U1 K5
  RP15 1
-Net 391 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#"
- U1 H16
- R20 1
-Net 392 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS"
+Net 389 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS"
+ R22 1
+ U1 T2
+Net 390 "/FPGA Spartan6/R_M0_CKE" "R_M0_CKE"
+ R24 1
+ U1 D2
+Net 391 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS"
  U1 T21
  R19 1
-Net 395 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
- U4 31
+Net 392 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#"
+ U1 H16
+ R20 1
+Net 393 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
  L1 2
+ U4 31
  L3 1
  C6 1
-Net 398 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
- R8 2
+Net 396 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
  U4 27
-Net 401 "" ""
+ R8 2
+Net 400 "" ""
  U4 37
  R2 1
 Net 403 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD"
- R9 1
- C12 1
  J4 14
  J4 13
-Net 404 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
- U4 26
- R7 2
-Net 405 "" ""
+ C12 1
+ R9 1
+Net 404 "" ""
  J4 10
  R7 1
-Net 406 "" ""
- R8 1
+Net 405 "" ""
  J4 12
+ R8 1
+Net 406 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
+ R7 2
+ U4 26
 Net 407 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
- L2 2
- C8 1
  C7 1
  U4 38
-Net 408 "+1.8V" "+1.8V"
- U4 13
- L1 1
- C4 1
- C2 1
+ L2 2
+ C8 1
+Net 408 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
+ U4 47
+ C9 1
+ L3 2
 Net 409 "/Ethernet Phy/MAG_TX-" "MAG_TX-"
+ R4 2
  U4 40
  J4 2
- R4 2
 Net 410 "/Ethernet Phy/MAG_RX-" "MAG_RX-"
- R6 2
- U4 32
  J4 8
-Net 411 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
- L3 2
- C9 1
- U4 47
-Net 412 "/Ethernet Phy/MAG_RX+" "MAG_RX+"
+ U4 32
+ R6 2
+Net 411 "/Ethernet Phy/MAG_RX+" "MAG_RX+"
  U4 33
  R5 2
  J4 7
-Net 413 "/Ethernet Phy/MAG_TX+" "MAG_TX+"
+Net 412 "/Ethernet Phy/MAG_TX+" "MAG_TX+"
  R3 2
  J4 1
  U4 41
-Net 415 "" ""
+Net 413 "+1.8V" "+1.8V"
+ U4 13
+ L1 1
+ C2 1
+ C4 1
+Net 417 "/USB/USBA_D-" "USBA_D-"
+ U6 10
+ V2 1
+ V2 1
+ J5 2
+Net 418 "" ""
  L10 1
  F2 1
-Net 416 "+5V" "+5V"
+Net 419 "+5V" "+5V"
  F1 2
  F2 2
-Net 417 "" ""
+Net 420 "" ""
+ V5 1
+ V5 1
  U13 11
- V5 1
- V5 1
-Net 421 "" ""
- V4 1
+Net 423 "/USB/USBD_D-" "USBD_D-"
  U7 10
  V4 1
-Net 422 "" ""
- V3 1
- V3 1
+ V4 1
+Net 424 "/USB/USBD_D+" "USBD_D+"
  U7 11
-Net 423 "" ""
- U6 10
- J5 2
- V2 1
- V2 1
-Net 424 "" ""
- J5 3
+ V3 1
+ V3 1
+Net 425 "/USB/USBA_D+" "USBA_D+"
+ V1 1
  U6 11
+ J5 3
  V1 1
- V1 1
-Net 425 "" ""
- L4 2
- J5 1
 Net 426 "" ""
- L5 1
- J5 4
+ J5 1
+ L4 2
 Net 427 "" ""
  F1 1
  L4 1
-Net 428 "" ""
- R10 1
- J5 S4
- J5 S3
- J5 S2
- J5 S1
- C16 1
-Net 430 "" ""
- C38 1
+Net 429 "" ""
  R15 1
+ C38 1
+Net 431 "" ""
+ J5 S4
+ C16 1
+ R10 1
+ J5 S1
+ J5 S2
+ J5 S3
+Net 432 "" ""
+ J5 4
+ L5 1
 Net 435 "" ""
+ V6 1
+ V6 1
  U13 10
- V6 1
- V6 1
 Net 436 "" ""
- C89 1
  R31 1
+ C89 1
 Net 437 "" ""
  U12 4
  C82 1
  U12 1
 Net 438 "" ""
- U12 5
  R27 1
  R28 2
+ U12 5
  C83 2
 Net 439 "" ""
  U11 1
@@ -3224,8 +3224,8 @@ Net 439 "" ""
 Net 440 "" ""
  U11 5
  C79 2
- R25 1
  R26 2
+ R25 1
 Net 450 "" ""
  L8 2
  U11 3
@@ -3233,30 +3233,30 @@ Net 469 "" ""
  U12 3
  L9 2
 Net 482 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3"
- U1 U13
  U8 7
+ U1 U13
 Net 483 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2"
- U1 U14
  U8 3
+ U1 U14
 Net 484 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1"
- U1 AA20
  U8 2
+ U1 AA20
 Net 485 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0"
- U1 AB20
  U8 5
+ U1 AB20
 Net 486 "/FPGA Spartan6/NF_D7" "NF_D7"
- U1 D11
  U5 44
+ U1 D11
 Net 487 "/FPGA Spartan6/NF_D6" "NF_D6"
  U5 43
  U1 A11
-Net 488 "/FPGA Spartan6/NF_D5" "NF_D5"
- U1 C11
+Net 488 "/Non volatile memories/NF_D5" "NF_D5"
  U5 42
+ U1 C11
 Net 489 "/FPGA Spartan6/NF_D4" "NF_D4"
  U5 41
  U1 A12
-Net 490 "/Non volatile memories/NF_D3" "NF_D3"
+Net 490 "/FPGA Spartan6/NF_D3" "NF_D3"
  U1 B12
  U5 32
 Net 491 "/Non volatile memories/NF_D2" "NF_D2"
@@ -3266,87 +3266,87 @@ Net 492 "/FPGA Spartan6/NF_D1" "NF_D1"
  U5 30
  U1 D14
 Net 493 "/FPGA Spartan6/NF_D0" "NF_D0"
- U5 29
  U1 C12
+ U5 29
 Net 494 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1"
- U1 C9
  U4 18
-Net 495 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0"
+ U1 C9
+Net 495 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0"
  U1 D10
  U4 17
-Net 496 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3"
+Net 496 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3"
  U1 C5
  U4 3
-Net 497 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2"
- U4 4
+Net 497 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2"
  U1 C6
-Net 498 "/FPGA Spartan6/ETH_RXD1" "ETH_RXD1"
+ U4 4
+Net 498 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1"
  U1 A5
  U4 5
-Net 499 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0"
+Net 499 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0"
  U1 B6
  U4 6
 Net 500 "/FPGA Spartan6/M0_BA1" "M0_BA1"
  RP15 6
  U2 27
-Net 501 "/FPGA Spartan6/M0_BA0" "M0_BA0"
- U2 26
+Net 501 "/DDR Banks/M0_BA0" "M0_BA0"
  RP15 7
-Net 502 "/DDR Banks/M1_BA1" "M1_BA1"
- RP2 6
+ U2 26
+Net 502 "/FPGA Spartan6/M1_BA1" "M1_BA1"
  U3 27
+ RP2 6
 Net 503 "/DDR Banks/M1_BA0" "M1_BA0"
- U3 26
  RP2 7
+ U3 26
 Net 504 "/FPGA Spartan6/M1_DQ15" "M1_DQ15"
  U3 65
  RP8 1
 Net 505 "/FPGA Spartan6/M1_DQ14" "M1_DQ14"
- U3 63
  RP8 2
+ U3 63
 Net 506 "/FPGA Spartan6/M1_DQ13" "M1_DQ13"
  U3 62
  RP8 3
-Net 507 "/FPGA Spartan6/M1_DQ12" "M1_DQ12"
+Net 507 "/DDR Banks/M1_DQ12" "M1_DQ12"
  U3 60
  RP8 4
 Net 508 "/FPGA Spartan6/M1_DQ11" "M1_DQ11"
- RP9 1
  U3 59
-Net 509 "/FPGA Spartan6/M1_DQ10" "M1_DQ10"
+ RP9 1
+Net 509 "/DDR Banks/M1_DQ10" "M1_DQ10"
  RP9 2
  U3 57
-Net 510 "/DDR Banks/M1_DQ9" "M1_DQ9"
+Net 510 "/FPGA Spartan6/M1_DQ9" "M1_DQ9"
  U3 56
  RP9 3
 Net 511 "/FPGA Spartan6/M1_DQ8" "M1_DQ8"
- RP9 4
  U3 54
+ RP9 4
 Net 512 "/FPGA Spartan6/M1_DQ7" "M1_DQ7"
  U3 13
  RP4 5
-Net 513 "/FPGA Spartan6/M1_DQ6" "M1_DQ6"
+Net 513 "/DDR Banks/M1_DQ6" "M1_DQ6"
  U3 11
  RP4 6
 Net 514 "/FPGA Spartan6/SD_DAT3" "SD_DAT3"
- J1 2
  U1 B16
+ J1 2
 Net 515 "/FPGA Spartan6/SD_DAT2" "SD_DAT2"
  U1 A16
  J1 1
-Net 516 "/FPGA Spartan6/SD_DAT1" "SD_DAT1"
+Net 516 "/Non volatile memories/SD_DAT1" "SD_DAT1"
  U1 B18
  J1 8
-Net 517 "/FPGA Spartan6/SD_DAT0" "SD_DAT0"
- U1 A18
+Net 517 "/Non volatile memories/SD_DAT0" "SD_DAT0"
  J1 7
-Net 518 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3"
+ U1 A18
+Net 518 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3"
  U1 A8
  U4 20
 Net 519 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2"
- U1 C10
  U4 19
-Net 520 "/FPGA Spartan6/M1_A5" "M1_A5"
+ U1 C10
+Net 520 "/DDR Banks/M1_A5" "M1_A5"
  U3 36
  RP6 3
 Net 521 "/FPGA Spartan6/M1_A4" "M1_A4"
@@ -3356,139 +3356,139 @@ Net 522 "/FPGA Spartan6/M1_A3" "M1_A3"
  U3 32
  RP1 5
 Net 523 "/FPGA Spartan6/M1_A2" "M1_A2"
- RP1 6
  U3 31
-Net 524 "/DDR Banks/M1_A1" "M1_A1"
- RP1 7
+ RP1 6
+Net 524 "/FPGA Spartan6/M1_A1" "M1_A1"
  U3 30
-Net 525 "/FPGA Spartan6/M1_A0" "M1_A0"
+ RP1 7
+Net 525 "/DDR Banks/M1_A0" "M1_A0"
  RP1 8
  U3 29
-Net 526 "/FPGA Spartan6/M0_A12" "M0_A12"
- RP18 8
+Net 526 "/DDR Banks/M0_A12" "M0_A12"
  U2 42
-Net 527 "/DDR Banks/M0_A11" "M0_A11"
- RP18 7
+ RP18 8
+Net 527 "/FPGA Spartan6/M0_A11" "M0_A11"
  U2 41
+ RP18 7
 Net 528 "/FPGA Spartan6/M0_A10" "M0_A10"
- U2 28
  RP15 5
-Net 529 "/DDR Banks/M0_A9" "M0_A9"
- RP18 6
+ U2 28
+Net 529 "/FPGA Spartan6/M0_A9" "M0_A9"
  U2 40
-Net 530 "/FPGA Spartan6/M0_A8" "M0_A8"
- RP18 5
+ RP18 6
+Net 530 "/DDR Banks/M0_A8" "M0_A8"
  U2 39
+ RP18 5
 Net 531 "/FPGA Spartan6/M0_A7" "M0_A7"
- RP17 8
  U2 38
-Net 532 "/FPGA Spartan6/M0_A6" "M0_A6"
- RP17 7
+ RP17 8
+Net 532 "/DDR Banks/M0_A6" "M0_A6"
  U2 37
-Net 533 "/FPGA Spartan6/M0_A5" "M0_A5"
- RP17 6
+ RP17 7
+Net 533 "/DDR Banks/M0_A5" "M0_A5"
  U2 36
-Net 534 "/DDR Banks/M0_A4" "M0_A4"
+ RP17 6
+Net 534 "/FPGA Spartan6/M0_A4" "M0_A4"
  U2 35
  RP17 5
-Net 535 "/FPGA Spartan6/M1_DQ5" "M1_DQ5"
- RP4 7
+Net 535 "/DDR Banks/M1_DQ5" "M1_DQ5"
  U3 10
-Net 536 "/DDR Banks/M1_DQ4" "M1_DQ4"
- RP4 8
+ RP4 7
+Net 536 "/FPGA Spartan6/M1_DQ4" "M1_DQ4"
  U3 8
-Net 537 "/FPGA Spartan6/M1_DQ3" "M1_DQ3"
+ RP4 8
+Net 537 "/DDR Banks/M1_DQ3" "M1_DQ3"
  RP5 5
  U3 7
 Net 538 "/FPGA Spartan6/M1_DQ2" "M1_DQ2"
  RP5 6
  U3 5
 Net 539 "/FPGA Spartan6/M1_DQ1" "M1_DQ1"
- RP5 7
  U3 4
-Net 540 "/DDR Banks/M1_DQ0" "M1_DQ0"
+ RP5 7
+Net 540 "/FPGA Spartan6/M1_DQ0" "M1_DQ0"
  RP5 8
  U3 2
-Net 541 "/FPGA Spartan6/M1_A12" "M1_A12"
+Net 541 "/DDR Banks/M1_A12" "M1_A12"
  RP7 1
  U3 42
-Net 542 "/DDR Banks/M1_A11" "M1_A11"
+Net 542 "/FPGA Spartan6/M1_A11" "M1_A11"
  RP7 2
  U3 41
 Net 543 "/FPGA Spartan6/M1_A10" "M1_A10"
  U3 28
  RP2 5
-Net 544 "/FPGA Spartan6/M1_A9" "M1_A9"
- RP7 3
+Net 544 "/DDR Banks/M1_A9" "M1_A9"
  U3 40
-Net 545 "/FPGA Spartan6/M1_A8" "M1_A8"
+ RP7 3
+Net 545 "/DDR Banks/M1_A8" "M1_A8"
  U3 39
  RP7 4
 Net 546 "/FPGA Spartan6/M1_A7" "M1_A7"
- RP6 1
  U3 38
-Net 547 "/DDR Banks/M1_A6" "M1_A6"
- RP6 2
+ RP6 1
+Net 547 "/FPGA Spartan6/M1_A6" "M1_A6"
  U3 37
-Net 548 "/DDR Banks/M0_A3" "M0_A3"
+ RP6 2
+Net 548 "/FPGA Spartan6/M0_A3" "M0_A3"
  U2 32
  RP14 5
 Net 549 "/FPGA Spartan6/M0_A2" "M0_A2"
- RP14 6
  U2 31
+ RP14 6
 Net 550 "/FPGA Spartan6/M0_A1" "M0_A1"
  RP14 7
  U2 30
-Net 551 "/DDR Banks/M0_A0" "M0_A0"
+Net 551 "/FPGA Spartan6/M0_A0" "M0_A0"
  RP14 8
  U2 29
-Net 552 "/FPGA Spartan6/M0_DQ15" "M0_DQ15"
+Net 552 "/DDR Banks/M0_DQ15" "M0_DQ15"
  RP10 5
  U2 65
-Net 553 "/DDR Banks/M0_DQ14" "M0_DQ14"
+Net 553 "/FPGA Spartan6/M0_DQ14" "M0_DQ14"
  U2 63
  RP10 6
 Net 554 "/FPGA Spartan6/M0_DQ13" "M0_DQ13"
- RP10 7
  U2 62
+ RP10 7
 Net 555 "/FPGA Spartan6/M0_DQ12" "M0_DQ12"
- U2 60
  RP10 8
+ U2 60
 Net 556 "/FPGA Spartan6/M0_DQ11" "M0_DQ11"
  U2 59
  RP11 5
-Net 557 "/DDR Banks/M0_DQ10" "M0_DQ10"
- U2 57
+Net 557 "/FPGA Spartan6/M0_DQ10" "M0_DQ10"
  RP11 6
+ U2 57
 Net 558 "/FPGA Spartan6/M0_DQ9" "M0_DQ9"
  RP11 7
  U2 56
-Net 559 "/FPGA Spartan6/M0_DQ8" "M0_DQ8"
+Net 559 "/DDR Banks/M0_DQ8" "M0_DQ8"
  RP11 8
  U2 54
-Net 560 "/DDR Banks/M0_DQ7" "M0_DQ7"
+Net 560 "/FPGA Spartan6/M0_DQ7" "M0_DQ7"
  RP12 5
  U2 13
 Net 561 "/FPGA Spartan6/M0_DQ6" "M0_DQ6"
- RP12 6
  U2 11
+ RP12 6
 Net 562 "/DDR Banks/M0_DQ5" "M0_DQ5"
  RP12 7
  U2 10
-Net 563 "/DDR Banks/M0_DQ4" "M0_DQ4"
+Net 563 "/FPGA Spartan6/M0_DQ4" "M0_DQ4"
  U2 8
  RP12 8
 Net 564 "/FPGA Spartan6/M0_DQ3" "M0_DQ3"
  RP13 5
  U2 7
-Net 565 "/FPGA Spartan6/M0_DQ2" "M0_DQ2"
+Net 565 "/DDR Banks/M0_DQ2" "M0_DQ2"
  RP13 6
  U2 5
-Net 566 "/FPGA Spartan6/M0_DQ1" "M0_DQ1"
- RP13 7
+Net 566 "/DDR Banks/M0_DQ1" "M0_DQ1"
  U2 4
-Net 567 "/FPGA Spartan6/M0_DQ0" "M0_DQ0"
- U2 2
+ RP13 7
+Net 567 "/DDR Banks/M0_DQ0" "M0_DQ0"
  RP13 8
+ U2 2
 }
 #End
diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro
index 9407401..69ca576 100644
--- a/kicad/xue-rnc/xue-rnc.pro
+++ b/kicad/xue-rnc/xue-rnc.pro
@@ -1,4 +1,4 @@
-update=Mon 23 Aug 2010 11:08:04 PM COT
+update=Tue 24 Aug 2010 06:57:27 AM COT
 version=1
 last_client=pcbnew
 [common]
diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch
index fd683eb..d38cccb 100644
--- a/kicad/xue-rnc/xue-rnc.sch
+++ b/kicad/xue-rnc/xue-rnc.sch
@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Mon 23 Aug 2010 10:36:19 PM COT
+EESchema Schematic File Version 2  date Tue 24 Aug 2010 06:53:07 AM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03