From 4110ee21c8ba513ef64b0c4f94a3074307c107ff Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Sat, 14 Aug 2010 08:23:56 -0500 Subject: [PATCH] fixed FPGA component bug --- kicad/xue-rnc/DRAM.sch | 2 +- kicad/xue-rnc/FPGA.sch | 218 +- kicad/xue-rnc/NV_MEMORIES.sch | 2 +- kicad/xue-rnc/USB.sch | 2 +- kicad/xue-rnc/eth_phy.sch | 2 +- kicad/xue-rnc/xue-rnc-cache.lib | 379 +-- kicad/xue-rnc/xue-rnc.brd | 1380 +++++------ kicad/xue-rnc/xue-rnc.net | 3836 +++++++++++++++++++------------ kicad/xue-rnc/xue-rnc.pro | 4 +- kicad/xue-rnc/xue-rnc.sch | 2 +- 10 files changed, 3364 insertions(+), 2463 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 8046548..cc450b0 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 08:20:37 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 581f4a0..1e88e06 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 08:20:37 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -67,11 +67,11 @@ Wire Bus Line Wire Bus Line 1550 7300 1550 7700 Wire Wire Line - 2700 7100 3300 7100 + 2700 7200 3300 7200 Wire Wire Line - 2700 8900 3300 8900 + 2700 9000 3300 9000 Wire Wire Line - 3300 6900 2600 6900 + 3300 7000 2600 7000 Wire Wire Line 18000 7650 17650 7650 Wire Wire Line @@ -269,11 +269,11 @@ Wire Wire Line Wire Wire Line 17650 6750 17800 6750 Wire Bus Line - 13300 3750 13400 3750 + 13300 3850 13400 3850 Wire Bus Line - 13400 3750 13400 3850 + 13400 3850 13400 3950 Wire Wire Line - 13500 3950 13900 3950 + 13500 4050 13900 4050 Wire Wire Line 12550 5100 12550 4850 Wire Wire Line @@ -347,15 +347,15 @@ Wire Wire Line Wire Bus Line 12150 2650 12250 2650 Wire Wire Line - 13500 2850 13900 2850 + 13500 2950 13900 2950 Wire Wire Line 18300 3650 18750 3650 Wire Wire Line 18750 5150 18300 5150 Wire Wire Line - 13900 4950 13550 4950 + 13900 5050 13550 5050 Wire Wire Line - 13550 5050 13900 5050 + 13550 5150 13900 5150 Wire Wire Line 7750 4800 7400 4800 Wire Wire Line @@ -365,15 +365,15 @@ Wire Wire Line Wire Wire Line 7400 5300 7700 5300 Wire Wire Line - 2800 3900 3200 3900 + 2800 4000 3200 4000 Wire Bus Line 1350 4900 1350 3300 Wire Bus Line 1350 3300 1250 3300 Wire Wire Line - 3200 3700 2750 3700 + 3200 3800 2750 3800 Wire Wire Line - 3200 3500 2750 3500 + 3200 3600 2750 3600 Wire Wire Line 12200 1650 11800 1650 Wire Wire Line @@ -401,7 +401,7 @@ Wire Wire Line Wire Wire Line 12200 2250 11800 2250 Wire Wire Line - 13900 4350 13550 4350 + 13900 4450 13550 4450 Connection ~ 5700 6350 Wire Wire Line 5700 6400 5700 6350 @@ -799,34 +799,34 @@ Connection ~ 5400 6350 Wire Wire Line 5600 6350 5600 6400 Connection ~ 5600 6350 -Wire Wire Line - 13900 4050 13500 4050 Wire Wire Line 13900 4150 13500 4150 +Wire Wire Line + 13900 4250 13500 4250 +Wire Wire Line + 13900 3850 13500 3850 Wire Wire Line 13900 3750 13500 3750 Wire Wire Line - 13900 3650 13500 3650 + 13900 3350 13500 3350 +Wire Wire Line + 13900 3450 13500 3450 Wire Wire Line 13900 3250 13500 3250 -Wire Wire Line - 13900 3350 13500 3350 Wire Wire Line 13900 3150 13500 3150 +Wire Wire Line + 13900 2850 13500 2850 Wire Wire Line 13900 3050 13500 3050 Wire Wire Line - 13900 2750 13500 2750 -Wire Wire Line - 13900 2950 13500 2950 -Wire Wire Line - 13900 4450 13500 4450 -Wire Wire Line - 13900 4650 13500 4650 + 13900 4550 13500 4550 Wire Wire Line 13900 4750 13500 4750 Wire Wire Line - 13900 4250 13550 4250 + 13900 4850 13500 4850 +Wire Wire Line + 13900 4350 13550 4350 Wire Bus Line 11700 2150 11700 900 Wire Bus Line @@ -892,33 +892,33 @@ Wire Wire Line Wire Wire Line 7800 4600 7400 4600 Wire Wire Line - 3200 3600 2750 3600 + 3200 3700 2750 3700 Wire Wire Line - 3200 3800 2750 3800 -Wire Wire Line - 3200 4400 2750 4400 -Wire Wire Line - 3200 4200 2750 4200 -Wire Wire Line - 3200 4100 2750 4100 -Wire Wire Line - 3200 4300 2750 4300 -Wire Wire Line - 3200 4700 2750 4700 + 3200 3900 2750 3900 Wire Wire Line 3200 4500 2750 4500 Wire Wire Line - 3200 4600 2750 4600 + 3200 4300 2750 4300 +Wire Wire Line + 3200 4200 2750 4200 +Wire Wire Line + 3200 4400 2750 4400 Wire Wire Line 3200 4800 2750 4800 +Wire Wire Line + 3200 4600 2750 4600 +Wire Wire Line + 3200 4700 2750 4700 +Wire Wire Line + 3200 4900 2750 4900 +Wire Wire Line + 3200 5500 2750 5500 +Wire Wire Line + 3200 5300 2750 5300 Wire Wire Line 3200 5400 2750 5400 Wire Wire Line 3200 5200 2750 5200 -Wire Wire Line - 3200 5300 2750 5300 -Wire Wire Line - 3200 5100 2750 5100 Wire Wire Line 1900 4100 1450 4100 Wire Wire Line @@ -952,7 +952,7 @@ Wire Wire Line Wire Wire Line 1900 4700 1450 4700 Wire Wire Line - 2800 4900 3200 4900 + 2800 5000 3200 5000 Wire Wire Line 7700 5400 7400 5400 Wire Wire Line @@ -962,9 +962,9 @@ Wire Wire Line Wire Wire Line 7750 4700 7400 4700 Wire Wire Line - 13550 4850 13900 4850 + 13550 4950 13900 4950 Wire Wire Line - 13550 3450 13900 3450 + 13550 3550 13900 3550 Wire Wire Line 18300 4650 18750 4650 Wire Bus Line @@ -1006,7 +1006,7 @@ Wire Wire Line Wire Wire Line 18300 1650 18400 1650 Wire Wire Line - 14200 6650 14250 6650 + 14200 8750 14250 8750 Wire Wire Line 14200 6850 14250 6850 Wire Wire Line @@ -1032,7 +1032,7 @@ Wire Bus Line Wire Bus Line 7900 4200 7900 4300 Wire Wire Line - 13900 3850 13500 3850 + 13900 3950 13500 3950 Wire Wire Line 17650 6650 17800 6650 Wire Wire Line @@ -1105,9 +1105,9 @@ Wire Wire Line Wire Wire Line 7300 6900 7900 6900 Wire Wire Line - 2700 9000 3300 9000 + 2700 9100 3300 9100 Wire Wire Line - 2700 7200 3300 7200 + 2700 7300 3300 7300 Wire Wire Line 1650 7600 2250 7600 Wire Wire Line @@ -1159,17 +1159,17 @@ Text Label 2200 7500 2 60 ~ 0 PROG_MISO0 Text Label 2200 7600 2 60 ~ 0 PROG_MISO1 -Text Label 3250 8900 2 60 ~ 0 -PROG_MISO2 Text Label 3250 9000 2 60 ~ 0 +PROG_MISO2 +Text Label 3250 9100 2 60 ~ 0 PROG_MISO3 -Text Label 3250 7200 2 60 ~ 0 +Text Label 3250 7300 2 60 ~ 0 PROG_MISO0 -Text Label 3250 7100 2 60 ~ 0 +Text Label 3250 7200 2 60 ~ 0 PROG_MISO1 Text HLabel 1450 7300 0 60 BiDi ~ 0 PROG_MISO[0..3] -Text HLabel 2600 6900 0 60 Output ~ 0 +Text HLabel 2600 7000 0 60 Output ~ 0 PROG_CCLK Text HLabel 7900 6900 2 60 Output ~ 0 PROG_CSO @@ -1654,14 +1654,14 @@ SD_CMD Text HLabel 18450 6750 2 60 BiDi ~ 0 SD_DAT[0..3] Entry Wire Line - 13400 3850 13500 3950 + 13400 3950 13500 4050 Entry Wire Line - 13400 3750 13500 3850 -Text Label 13850 3950 2 60 ~ 0 + 13400 3850 13500 3950 +Text Label 13850 4050 2 60 ~ 0 M1_BA1 -Text Label 13850 3850 2 60 ~ 0 +Text Label 13850 3950 2 60 ~ 0 M1_BA0 -Text HLabel 13300 3750 0 60 Output ~ 0 +Text HLabel 13300 3850 0 60 Output ~ 0 M1_BA[0..1] Entry Wire Line 7800 4400 7900 4300 @@ -1699,7 +1699,7 @@ Text HLabel 18400 1450 2 60 BiDi ~ 0 USBA_OE_N Text HLabel 18400 1350 2 60 BiDi ~ 0 USBA_SPD -Text HLabel 14200 8450 0 60 BiDi ~ 0 +Text HLabel 14200 6750 0 60 BiDi ~ 0 ETH_CLK Text HLabel 14200 8350 0 60 BiDi ~ 0 ETH_RXC @@ -1753,7 +1753,7 @@ Text HLabel 14200 6950 0 60 BiDi ~ 0 ETH_RESET_N Text HLabel 14200 6850 0 60 BiDi ~ 0 ETH_MDIO -Text HLabel 14200 6750 0 60 BiDi ~ 0 +Text HLabel 14200 8450 0 60 BiDi ~ 0 ETH_MDC Text Label 18400 4250 0 60 ~ 0 M1_DQ0 @@ -1855,11 +1855,11 @@ Text HLabel 12150 2650 0 60 BiDi ~ 0 M1_DQ[0..15] Text HLabel 1450 5700 0 60 Output ~ 0 M0_CS# -Text HLabel 2800 3900 0 60 Output ~ 0 +Text HLabel 2800 4000 0 60 Output ~ 0 M0_UDQS Text HLabel 7700 5500 2 60 Output ~ 0 M0_LDM -Text HLabel 2800 4900 0 60 Output ~ 0 +Text HLabel 2800 5000 0 60 Output ~ 0 M0_LDQS Text HLabel 7700 5600 2 60 Output ~ 0 M0_UDM @@ -1937,37 +1937,37 @@ Text Label 1550 4200 0 60 ~ 0 M0_DQ7 Text Label 1550 4100 0 60 ~ 0 M0_DQ6 -Text Label 2750 5100 0 60 ~ 0 -M0_DQ6 Text Label 2750 5200 0 60 ~ 0 -M0_DQ7 -Text Label 2750 5400 0 60 ~ 0 -M0_DQ5 +M0_DQ6 Text Label 2750 5300 0 60 ~ 0 +M0_DQ7 +Text Label 2750 5500 0 60 ~ 0 +M0_DQ5 +Text Label 2750 5400 0 60 ~ 0 M0_DQ4 -Text Label 2750 4700 0 60 ~ 0 -M0_DQ2 Text Label 2750 4800 0 60 ~ 0 +M0_DQ2 +Text Label 2750 4900 0 60 ~ 0 M0_DQ3 -Text Label 2750 4600 0 60 ~ 0 +Text Label 2750 4700 0 60 ~ 0 M0_DQ1 -Text Label 2750 4500 0 60 ~ 0 +Text Label 2750 4600 0 60 ~ 0 M0_DQ0 -Text Label 2750 4100 0 60 ~ 0 -M0_DQ10 Text Label 2750 4200 0 60 ~ 0 -M0_DQ11 -Text Label 2750 4400 0 60 ~ 0 -M0_DQ9 +M0_DQ10 Text Label 2750 4300 0 60 ~ 0 +M0_DQ11 +Text Label 2750 4500 0 60 ~ 0 +M0_DQ9 +Text Label 2750 4400 0 60 ~ 0 M0_DQ8 -Text Label 2750 3700 0 60 ~ 0 -M0_DQ12 Text Label 2750 3800 0 60 ~ 0 +M0_DQ12 +Text Label 2750 3900 0 60 ~ 0 M0_DQ13 -Text Label 2750 3600 0 60 ~ 0 +Text Label 2750 3700 0 60 ~ 0 M0_DQ15 -Text Label 2750 3500 0 60 ~ 0 +Text Label 2750 3600 0 60 ~ 0 M0_DQ14 Text Label 7450 4600 0 60 ~ 0 M0_A0 @@ -2079,15 +2079,15 @@ Entry Wire Line 11700 2050 11800 2150 Entry Wire Line 11700 2150 11800 2250 -Text HLabel 13550 4950 0 60 Output ~ 0 -M1_CAS# -Text HLabel 13500 2850 0 60 Output ~ 0 -M1_CKE -Text HLabel 13550 3450 0 60 Output ~ 0 -M1_WE# -Text HLabel 13550 4850 0 60 Output ~ 0 -M1_RAS# Text HLabel 13550 5050 0 60 Output ~ 0 +M1_CAS# +Text HLabel 13500 2950 0 60 Output ~ 0 +M1_CKE +Text HLabel 13550 3550 0 60 Output ~ 0 +M1_WE# +Text HLabel 13550 4950 0 60 Output ~ 0 +M1_RAS# +Text HLabel 13550 5150 0 60 Output ~ 0 M1_UDM Text HLabel 18750 4650 2 60 Output ~ 0 M1_LDQS @@ -2121,39 +2121,39 @@ Text Label 11900 1150 0 60 ~ 0 M1_A11 Text Label 11900 1050 0 60 ~ 0 M1_A12 -Text Label 13500 4750 0 60 ~ 0 +Text Label 13500 4850 0 60 ~ 0 M1_A6 -Text Label 13500 4650 0 60 ~ 0 +Text Label 13500 4750 0 60 ~ 0 M1_A5 -Text Label 13500 4450 0 60 ~ 0 +Text Label 13500 4550 0 60 ~ 0 M1_A3 -Text Label 13500 2950 0 60 ~ 0 -M1_A12 -Text Label 13500 2750 0 60 ~ 0 -M1_A11 Text Label 13500 3050 0 60 ~ 0 -M1_A8 +M1_A12 +Text Label 13500 2850 0 60 ~ 0 +M1_A11 Text Label 13500 3150 0 60 ~ 0 -M1_A9 -Text Label 13500 3350 0 60 ~ 0 -M1_A4 +M1_A8 Text Label 13500 3250 0 60 ~ 0 +M1_A9 +Text Label 13500 3450 0 60 ~ 0 +M1_A4 +Text Label 13500 3350 0 60 ~ 0 M1_A10 -Text Label 13500 3650 0 60 ~ 0 -M1_A7 Text Label 13500 3750 0 60 ~ 0 +M1_A7 +Text Label 13500 3850 0 60 ~ 0 M1_A2 -Text Label 13500 4150 0 60 ~ 0 +Text Label 13500 4250 0 60 ~ 0 M1_A1 -Text Label 13500 4050 0 60 ~ 0 +Text Label 13500 4150 0 60 ~ 0 M1_A0 Text HLabel 11300 900 0 60 Output ~ 0 M1_A[0..12] -Text HLabel 14200 6650 0 60 BiDi ~ 0 +Text HLabel 14200 8750 0 60 BiDi ~ 0 ETH_INT -Text HLabel 13550 4250 0 60 Output ~ 0 -M1_CLK Text HLabel 13550 4350 0 60 Output ~ 0 +M1_CLK +Text HLabel 13550 4450 0 60 Output ~ 0 M1_CLK# Text HLabel 7750 4800 2 60 Output ~ 0 M0_CLK diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 4df5c5c..c12fb0a 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 08:20:37 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index d39cc05..cf90c84 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 08:20:37 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index a0bf3db..eceb652 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 08:20:37 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 8357830..278025c 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Sat 14 Aug 2010 07:07:48 AM COT +EESchema-LIBRARY Version 2.3 Date: Sat 14 Aug 2010 08:20:37 AM COT # # +1.2V # @@ -465,18 +465,18 @@ F0 "U" 0 100 70 H V C CNN F1 "xc6slx45fgg484" 0 -100 70 H V C CNN DRAW S -1900 -2100 1900 2100 1 1 0 f -X IO_L20P_1 A20 -2200 1300 300 R 60 60 1 1 P -X IO_L1N_A24_VREF_1 B20 -2200 2000 300 R 60 60 1 1 P -X IO_L32P_A17_M1A8_1 C20 -2200 100 300 R 60 60 1 1 P -X IO_L29N_A22_M1A14_1 D20 -2200 600 300 R 60 60 1 1 P -X IO_L35P_A11_M1A7_1 E20 -2200 -500 300 R 60 60 1 1 P -X IO_L33N_A14_M1A4_1 F20 -2200 -200 300 R 60 60 1 1 P -X IO_L39P_M1A3_1 G20 -2200 -1300 300 R 60 60 1 1 P -X IO_L38P_A5_M1CLK_1 H20 -2200 -1100 300 R 60 60 1 1 P +X IO_L20P_1 A20 -2200 1200 300 R 60 60 1 1 P +X IO_L1N_A24_VREF_1 B20 -2200 1900 300 R 60 60 1 1 P +X IO_L32P_A17_M1A8_1 C20 -2200 0 300 R 60 60 1 1 P +X IO_L29N_A22_M1A14_1 D20 -2200 500 300 R 60 60 1 1 P +X IO_L35P_A11_M1A7_1 E20 -2200 -600 300 R 60 60 1 1 P +X IO_L33N_A14_M1A4_1 F20 -2200 -300 300 R 60 60 1 1 P +X IO_L39P_M1A3_1 G20 -2200 -1400 300 R 60 60 1 1 P +X IO_L38P_A5_M1CLK_1 H20 -2200 -1200 300 R 60 60 1 1 P X IO_L43P_GCLK5_M1DQ4_1 J20 2200 -1900 300 L 60 60 1 1 P -X IO_L40P_GCLK11_M1A5_1 K20 -2200 -1500 300 R 60 60 1 1 P +X IO_L40P_GCLK11_M1A5_1 K20 -2200 -1600 300 R 60 60 1 1 P X IO_L45P_A1_M1LDQS_1 L20 2200 -1500 300 L 60 60 1 1 P -X IO_L42P_GCLK7_M1UDM_1 M20 -2200 -1900 300 R 60 60 1 1 P +X IO_L42P_GCLK7_M1UDM_1 M20 -2200 -2000 300 R 60 60 1 1 P X IO_L47P_FWE_B_M1DQ0_1 N20 2200 -1100 300 L 60 60 1 1 P X IO_L59N_1 P20 2200 600 300 L 60 60 1 1 P X IO_L49P_M1DQ10_1 R20 2200 -700 300 L 60 60 1 1 P @@ -484,13 +484,13 @@ X IO_L74N_DOUT_BUSY_1 T20 2200 2000 300 L 60 60 1 1 P X IO_L51P_M1DQ12_1 U20 2200 -300 300 L 60 60 1 1 P X IO_L70N_1 V20 2200 1200 300 L 60 60 1 1 P X IO_L60P_1 W20 2200 700 300 L 60 60 1 1 P -X IO_L20N_1 A21 -2200 1200 300 R 60 60 1 1 P -X IO_L19P_1 B21 -2200 1500 300 R 60 60 1 1 P +X IO_L20N_1 A21 -2200 1100 300 R 60 60 1 1 P +X IO_L19P_1 B21 -2200 1400 300 R 60 60 1 1 P X VCCO_1 C21 -400 2400 300 D 60 60 1 1 P -X IO_L31P_A19_M1CKE_1 D21 -2200 300 300 R 60 60 1 1 P -X IO_L37P_A7_M1A0_1 F21 -2200 -900 300 R 60 60 1 1 P +X IO_L31P_A19_M1CKE_1 D21 -2200 200 300 R 60 60 1 1 P +X IO_L37P_A7_M1A0_1 F21 -2200 -1000 300 R 60 60 1 1 P X VCCO_1 G21 -300 2400 300 D 60 60 1 1 P -X IO_L41P_GCLK9_IRDY1_M1RASN_1 H21 -2200 -1700 300 R 60 60 1 1 P +X IO_L41P_GCLK9_IRDY1_M1RASN_1 H21 -2200 -1800 300 R 60 60 1 1 P X IO_L44P_A3_M1DQ6_1 K21 2200 -1700 300 L 60 60 1 1 P X VCCO_1 L21 0 2400 300 D 60 60 1 1 P X IO_L46P_FCS_B_M1DQ2_1 M21 2200 -1300 300 L 60 60 1 1 P @@ -499,13 +499,13 @@ X VCCO_1 R21 200 2400 300 D 60 60 1 1 P X IO_L50P_M1UDQS_1 T21 2200 -500 300 L 60 60 1 1 P X IO_L52P_M1DQ14_1 V21 2200 -100 300 L 60 60 1 1 P X VCCO_1 W21 -500 2400 300 D 60 60 1 1 P -X IO_L19N_1 B22 -2200 1400 300 R 60 60 1 1 P -X IO_L32N_A16_M1A9_1 C22 -2200 0 300 R 60 60 1 1 P -X IO_L31N_A18_M1A12_1 D22 -2200 200 300 R 60 60 1 1 P -X IO_L35N_A10_M1A2_1 E22 -2200 -600 300 R 60 60 1 1 P -X IO_L37N_A6_M1A1_1 F22 -2200 -1000 300 R 60 60 1 1 P -X IO_L39N_M1ODT_1 G22 -2200 -1400 300 R 60 60 1 1 P -X IO_L41N_GCLK8_M1CASN_1 H22 -2200 -1800 300 R 60 60 1 1 P +X IO_L19N_1 B22 -2200 1300 300 R 60 60 1 1 P +X IO_L32N_A16_M1A9_1 C22 -2200 -100 300 R 60 60 1 1 P +X IO_L31N_A18_M1A12_1 D22 -2200 100 300 R 60 60 1 1 P +X IO_L35N_A10_M1A2_1 E22 -2200 -700 300 R 60 60 1 1 P +X IO_L37N_A6_M1A1_1 F22 -2200 -1100 300 R 60 60 1 1 P +X IO_L39N_M1ODT_1 G22 -2200 -1500 300 R 60 60 1 1 P +X IO_L41N_GCLK8_M1CASN_1 H22 -2200 -1900 300 R 60 60 1 1 P X IO_L43N_GCLK4_M1DQ5_1 J22 2200 -1800 300 L 60 60 1 1 P X IO_L44N_A2_M1DQ7_1 K22 2200 -1600 300 L 60 60 1 1 P X IO_L45N_A0_M1LDQSN_1 L22 2200 -1400 300 L 60 60 1 1 P @@ -518,37 +518,38 @@ X IO_L51N_M1DQ13_1 U22 2200 -200 300 L 60 60 1 1 P X IO_L52N_M1DQ15_1 V22 2200 0 300 L 60 60 1 1 P X IO_L60N_1 W22 2200 800 300 L 60 60 1 1 P X IO_L58N_1 L15 2200 400 300 L 60 60 1 1 P -X IO_L10P_1 F16 -2200 1700 300 R 60 60 1 1 P -X IO_L9P_1 G16 -2200 1900 300 R 60 60 1 1 P -X IO_L28P_1 H16 -2200 900 300 R 60 60 1 1 P -X IO_L21N_1 J16 -2200 1000 300 R 60 60 1 1 P -X IO_L21P_1 K16 -2200 1100 300 R 60 60 1 1 P +X IO_L10P_1 F16 -2200 1600 300 R 60 60 1 1 P +X IO_L9P_1 G16 -2200 1800 300 R 60 60 1 1 P +X IO_L28P_1 H16 -2200 800 300 R 60 60 1 1 P +X IO_L21N_1 J16 -2200 900 300 R 60 60 1 1 P +X IO_L21P_1 K16 -2200 1000 300 R 60 60 1 1 P X VCCO_1 L16 -100 2400 300 D 60 60 1 1 P X IO_L58P_1 M16 2200 300 300 L 60 60 1 1 P X IO_L72N_1 N16 2200 1600 300 L 60 60 1 1 P -X IO_L10N_1 F17 -2200 1600 300 R 60 60 1 1 P -X IO_L9N_1 G17 -2200 1800 300 R 60 60 1 1 P -X IO_L28N_VREF_1 H17 -2200 800 300 R 60 60 1 1 P -X IO_L36P_A9_M1BA0_1 J17 -2200 -700 300 R 60 60 1 1 P -X IO_L36N_A8_M1BA1_1 K17 -2200 -800 300 R 60 60 1 1 P +X IO_L10N_1 F17 -2200 1500 300 R 60 60 1 1 P +X IO_L9N_1 G17 -2200 1700 300 R 60 60 1 1 P +X IO_L28N_VREF_1 H17 -2200 700 300 R 60 60 1 1 P +X IO_L36P_A9_M1BA0_1 J17 -2200 -800 300 R 60 60 1 1 P +X IO_L36N_A8_M1BA1_1 K17 -2200 -900 300 R 60 60 1 1 P X IO_L61P_1 L17 2200 900 300 L 60 60 1 1 P X IO_L71P_1 M17 2200 1300 300 L 60 60 1 1 P X IO_L72P_1 P17 2200 1500 300 L 60 60 1 1 P -X IO_L30P_A21_M1RESET_1 F18 -2200 500 300 R 60 60 1 1 P -X IO_L34N_A12_M1BA2_1 H18 -2200 -400 300 R 60 60 1 1 P +X IO_L30P_A21_M1RESET_1 F18 -2200 400 300 R 60 60 1 1 P +X IO_L34N_A12_M1BA2_1 H18 -2200 -500 300 R 60 60 1 1 P X VCCO_1 J18 -200 2400 300 D 60 60 1 1 P X IO_L61N_1 K18 2200 1000 300 L 60 60 1 1 P X IO_L71N_1 M18 2200 1400 300 L 60 60 1 1 P X VCCO_1 N18 100 2400 300 D 60 60 1 1 P X IO_L73P_1 P18 2200 1700 300 L 60 60 1 1 P X VCCO_1 U18 300 2400 300 D 60 60 1 1 P -X IO_L29P_A23_M1A13_1 D19 -2200 700 300 R 60 60 1 1 P +X IO_L1P_A25_1 C19 -2200 2000 300 R 60 60 1 1 P +X IO_L29P_A23_M1A13_1 D19 -2200 600 300 R 60 60 1 1 P X VCCO_1 E19 400 2400 300 D 60 60 1 1 P -X IO_L30N_A20_M1A11_1 F19 -2200 400 300 R 60 60 1 1 P -X IO_L33P_A15_M1A10_1 G19 -2200 -100 300 R 60 60 1 1 P -X IO_L34P_A13_M1WE_1 H19 -2200 -300 300 R 60 60 1 1 P -X IO_L38N_A4_M1CLKN_1 J19 -2200 -1200 300 R 60 60 1 1 P -X IO_L40N_GCLK10_M1A6_1 K19 -2200 -1600 300 R 60 60 1 1 P +X IO_L30N_A20_M1A11_1 F19 -2200 300 300 R 60 60 1 1 P +X IO_L33P_A15_M1A10_1 G19 -2200 -200 300 R 60 60 1 1 P +X IO_L34P_A13_M1WE_1 H19 -2200 -400 300 R 60 60 1 1 P +X IO_L38N_A4_M1CLKN_1 J19 -2200 -1300 300 R 60 60 1 1 P +X IO_L40N_GCLK10_M1A6_1 K19 -2200 -1700 300 R 60 60 1 1 P X IO_L42N_GCLK6_TRDY1_M1LDM_1 L19 2200 -2000 300 L 60 60 1 1 P X IO_L53P_1 M19 2200 100 300 L 60 60 1 1 P X IO_L53N_VREF_1 N19 2200 200 300 L 60 60 1 1 P @@ -557,34 +558,35 @@ X IO_L73N_1 R19 2200 1800 300 L 60 60 1 1 P X IO_L74P_AWAKE_1 T19 2200 1900 300 L 60 60 1 1 P X IO_L70P_1 U19 2200 1100 300 L 60 60 1 1 P S -1400 -1200 1400 1200 2 1 0 f -X IO_L1N_VREF_0 A4 -1700 1100 300 R 60 60 2 1 P +X IO_L1P_HSWAPEN_0 A3 -1700 1100 300 R 60 60 2 1 P +X IO_L1N_VREF_0 A4 -1700 1000 300 R 60 60 2 1 P X VCCO_0 B4 -500 1500 300 D 60 60 2 1 P -X IO_L2N_0 A5 -1700 900 300 R 60 60 2 1 P -X IO_L2P_0 C5 -1700 1000 300 R 60 60 2 1 P -X IO_L4N_0 A6 -1700 500 300 R 60 60 2 1 P -X IO_L4P_0 B6 -1700 600 300 R 60 60 2 1 P -X IO_L3N_0 C6 -1700 700 300 R 60 60 2 1 P -X IO_L3P_0 D6 -1700 800 300 R 60 60 2 1 P -X IO_L5N_0 A7 -1700 300 300 R 60 60 2 1 P +X IO_L2N_0 A5 -1700 800 300 R 60 60 2 1 P +X IO_L2P_0 C5 -1700 900 300 R 60 60 2 1 P +X IO_L4N_0 A6 -1700 400 300 R 60 60 2 1 P +X IO_L4P_0 B6 -1700 500 300 R 60 60 2 1 P +X IO_L3N_0 C6 -1700 600 300 R 60 60 2 1 P +X IO_L3P_0 D6 -1700 700 300 R 60 60 2 1 P +X IO_L5N_0 A7 -1700 200 300 R 60 60 2 1 P X VCCO_0 B7 -400 1500 300 D 60 60 2 1 P -X IO_L5P_0 C7 -1700 400 300 R 60 60 2 1 P -X IO_L32P_0 D7 -1700 -400 300 R 60 60 2 1 P -X IO_L6N_0 A8 -1700 100 300 R 60 60 2 1 P -X IO_L6P_0 B8 -1700 200 300 R 60 60 2 1 P -X IO_L7N_0 C8 -1700 -100 300 R 60 60 2 1 P -X IO_L32N_0 D8 -1700 -500 300 R 60 60 2 1 P -X IO_L8N_VREF_0 A9 -1700 -300 300 R 60 60 2 1 P -X IO_L8P_0 C9 -1700 -200 300 R 60 60 2 1 P -X IO_L7P_0 D9 -1700 0 300 R 60 60 2 1 P +X IO_L5P_0 C7 -1700 300 300 R 60 60 2 1 P +X IO_L32P_0 D7 -1700 -500 300 R 60 60 2 1 P +X IO_L6N_0 A8 -1700 0 300 R 60 60 2 1 P +X IO_L6P_0 B8 -1700 100 300 R 60 60 2 1 P +X IO_L7N_0 C8 -1700 -200 300 R 60 60 2 1 P +X IO_L32N_0 D8 -1700 -600 300 R 60 60 2 1 P +X IO_L8N_VREF_0 A9 -1700 -400 300 R 60 60 2 1 P +X IO_L8P_0 C9 -1700 -300 300 R 60 60 2 1 P +X IO_L7P_0 D9 -1700 -100 300 R 60 60 2 1 P X VCCO_0 E9 400 1500 300 D 60 60 2 1 P -X IO_L34N_GCLK18_0 A10 -1700 -900 300 R 60 60 2 1 P -X IO_L34P_GCLK19_0 B10 -1700 -800 300 R 60 60 2 1 P -X IO_L33N_0 C10 -1700 -700 300 R 60 60 2 1 P -X IO_L33P_0 D10 -1700 -600 300 R 60 60 2 1 P +X IO_L34N_GCLK18_0 A10 -1700 -1000 300 R 60 60 2 1 P +X IO_L34P_GCLK19_0 B10 -1700 -900 300 R 60 60 2 1 P +X IO_L33N_0 C10 -1700 -800 300 R 60 60 2 1 P +X IO_L33P_0 D10 -1700 -700 300 R 60 60 2 1 P X VCCO_0 G10 -100 1500 300 D 60 60 2 1 P X IO_L35N_GCLK16_0 A11 1700 -1100 300 L 60 60 2 1 P X VCCO_0 B11 100 1500 300 D 60 60 2 1 P -X IO_L35P_GCLK17_0 C11 -1700 -1000 300 R 60 60 2 1 P +X IO_L35P_GCLK17_0 C11 -1700 -1100 300 R 60 60 2 1 P X IO_L36P_GCLK15_0 D11 1700 -1000 300 L 60 60 2 1 P X IO_L37N_GCLK12_0 A12 1700 -700 300 L 60 60 2 1 P X IO_L37P_GCLK13_0 B12 1700 -800 300 L 60 60 2 1 P @@ -620,18 +622,18 @@ X IO_L52N_M3A9_3 E1 2100 -100 300 L 60 60 3 1 P X IO_L50N_M3BA2_3 F1 2100 -500 300 L 60 60 3 1 P X IO_L48N_M3BA1_3 G1 2100 -900 300 L 60 60 3 1 P X IO_L47N_M3A1_3 H1 2100 -1100 300 L 60 60 3 1 P -X IO_L41N_GCLK26_M3DQ5_3 J1 -2100 -2000 300 R 60 60 3 1 P -X IO_L40N_M3DQ7_3 K1 -2100 -1800 300 R 60 60 3 1 P -X IO_L39N_M3LDQSN_3 L1 -2100 -1600 300 R 60 60 3 1 P -X IO_L38N_M3DQ3_3 M1 -2100 -1400 300 R 60 60 3 1 P -X IO_L37N_M3DQ1_3 N1 -2100 -1200 300 R 60 60 3 1 P -X IO_L36N_M3DQ9_3 P1 -2100 -1000 300 R 60 60 3 1 P -X IO_L35N_M3DQ11_3 R1 -2100 -800 300 R 60 60 3 1 P -X IO_L34N_M3UDQSN_3 T1 -2100 -600 300 R 60 60 3 1 P -X IO_L33N_M3DQ13_3 U1 -2100 -400 300 R 60 60 3 1 P -X IO_L32N_M3DQ15_3 V1 -2100 -200 300 R 60 60 3 1 P -X IO_L2N_3 W1 -2100 2000 300 R 60 60 3 1 P -X IO_L1N_VREF_3 Y1 -2100 2200 300 R 60 60 3 1 P +X IO_L41N_GCLK26_M3DQ5_3 J1 -2100 -2100 300 R 60 60 3 1 P +X IO_L40N_M3DQ7_3 K1 -2100 -1900 300 R 60 60 3 1 P +X IO_L39N_M3LDQSN_3 L1 -2100 -1700 300 R 60 60 3 1 P +X IO_L38N_M3DQ3_3 M1 -2100 -1500 300 R 60 60 3 1 P +X IO_L37N_M3DQ1_3 N1 -2100 -1300 300 R 60 60 3 1 P +X IO_L36N_M3DQ9_3 P1 -2100 -1100 300 R 60 60 3 1 P +X IO_L35N_M3DQ11_3 R1 -2100 -900 300 R 60 60 3 1 P +X IO_L34N_M3UDQSN_3 T1 -2100 -700 300 R 60 60 3 1 P +X IO_L33N_M3DQ13_3 U1 -2100 -500 300 R 60 60 3 1 P +X IO_L32N_M3DQ15_3 V1 -2100 -300 300 R 60 60 3 1 P +X IO_L2N_3 W1 -2100 1900 300 R 60 60 3 1 P +X IO_L1N_VREF_3 Y1 -2100 2100 300 R 60 60 3 1 P X IO_L83P_3 A2 2100 2000 300 L 60 60 3 1 P X IO_L60P_3 B2 2100 1200 300 L 60 60 3 1 P X VCCO_3 C2 -200 2600 300 D 60 60 3 1 P @@ -639,14 +641,15 @@ X IO_L53P_M3CKE_3 D2 2100 0 300 L 60 60 3 1 P X IO_L50P_M3WE_3 F2 2100 -600 300 L 60 60 3 1 P X VCCO_3 G2 200 2600 300 D 60 60 3 1 P X IO_L47P_M3A0_3 H2 2100 -1200 300 L 60 60 3 1 P -X IO_L40P_M3DQ6_3 K2 -2100 -1700 300 R 60 60 3 1 P +X IO_L40P_M3DQ6_3 K2 -2100 -1800 300 R 60 60 3 1 P X VCCO_3 L2 -400 2600 300 D 60 60 3 1 P -X IO_L38P_M3DQ2_3 M2 -2100 -1300 300 R 60 60 3 1 P -X IO_L36P_M3DQ8_3 P2 -2100 -900 300 R 60 60 3 1 P +X IO_L38P_M3DQ2_3 M2 -2100 -1400 300 R 60 60 3 1 P +X IO_L36P_M3DQ8_3 P2 -2100 -1000 300 R 60 60 3 1 P X VCCO_3 R2 0 2600 300 D 60 60 3 1 P -X IO_L34P_M3UDQS_3 T2 -2100 -500 300 R 60 60 3 1 P -X IO_L32P_M3DQ14_3 V2 -2100 -100 300 R 60 60 3 1 P +X IO_L34P_M3UDQS_3 T2 -2100 -600 300 R 60 60 3 1 P +X IO_L32P_M3DQ14_3 V2 -2100 -200 300 R 60 60 3 1 P X VCCO_3 W2 -500 2600 300 D 60 60 3 1 P +X IO_L1P_3 Y2 -2100 2200 300 R 60 60 3 1 P X IO_L83N_VREF_3 B3 2100 2100 300 L 60 60 3 1 P X IO_L54P_M3RESET_3 C3 2100 200 300 L 60 60 3 1 P X IO_L81P_3 D3 2100 1600 300 L 60 60 3 1 P @@ -654,17 +657,17 @@ X IO_L52P_M3A8_3 E3 2100 -200 300 L 60 60 3 1 P X IO_L51N_M3A4_3 F3 2100 -300 300 L 60 60 3 1 P X IO_L48P_M3BA0_3 G3 2100 -1000 300 L 60 60 3 1 P X IO_L46N_M3CLKN_3 H3 2100 -1300 300 L 60 60 3 1 P -X IO_L41P_GCLK27_M3DQ4_3 J3 -2100 -1900 300 R 60 60 3 1 P +X IO_L41P_GCLK27_M3DQ4_3 J3 -2100 -2000 300 R 60 60 3 1 P X IO_L44P_GCLK21_M3A5_3 K3 2100 -1800 300 L 60 60 3 1 P -X IO_L39P_M3LDQS_3 L3 -2100 -1500 300 R 60 60 3 1 P +X IO_L39P_M3LDQS_3 L3 -2100 -1600 300 R 60 60 3 1 P X IO_L42P_GCLK25_TRDY2_M3UDM_3 M3 2100 -2200 300 L 60 60 3 1 P -X IO_L37P_M3DQ0_3 N3 -2100 -1100 300 R 60 60 3 1 P -X IO_L26P_3 P3 -2100 300 300 R 60 60 3 1 P -X IO_L35P_M3DQ10_3 R3 -2100 -700 300 R 60 60 3 1 P -X IO_L9N_3 T3 -2100 1400 300 R 60 60 3 1 P -X IO_L33P_M3DQ12_3 U3 -2100 -300 300 R 60 60 3 1 P -X IO_L10N_3 V3 -2100 1200 300 R 60 60 3 1 P -X IO_L2P_3 W3 -2100 2100 300 R 60 60 3 1 P +X IO_L37P_M3DQ0_3 N3 -2100 -1200 300 R 60 60 3 1 P +X IO_L26P_3 P3 -2100 200 300 R 60 60 3 1 P +X IO_L35P_M3DQ10_3 R3 -2100 -800 300 R 60 60 3 1 P +X IO_L9N_3 T3 -2100 1300 300 R 60 60 3 1 P +X IO_L33P_M3DQ12_3 U3 -2100 -400 300 R 60 60 3 1 P +X IO_L10N_3 V3 -2100 1100 300 R 60 60 3 1 P +X IO_L2P_3 W3 -2100 2000 300 R 60 60 3 1 P X IO_L81N_3 C4 2100 1700 300 L 60 60 3 1 P X IO_L58N_3 E4 2100 900 300 L 60 60 3 1 P X VCCO_3 F4 300 2600 300 D 60 60 3 1 P @@ -673,21 +676,21 @@ X IO_L46P_M3CLK_3 H4 2100 -1400 300 L 60 60 3 1 P X IO_L44N_GCLK20_M3A6_3 J4 2100 -1700 300 L 60 60 3 1 P X IO_L43N_GCLK22_IRDY2_M3CASN_3 K4 2100 -1900 300 L 60 60 3 1 P X IO_L42N_GCLK24_M3LDM_3 L4 2100 -2100 300 L 60 60 3 1 P -X IO_L31N_VREF_3 M4 -2100 0 300 R 60 60 3 1 P -X IO_L26N_3 N4 -2100 200 300 R 60 60 3 1 P -X IO_L24N_3 P4 -2100 600 300 R 60 60 3 1 P -X IO_L24P_3 R4 -2100 700 300 R 60 60 3 1 P -X IO_L9P_3 T4 -2100 1500 300 R 60 60 3 1 P -X IO_L10P_3 U4 -2100 1300 300 R 60 60 3 1 P +X IO_L31N_VREF_3 M4 -2100 -100 300 R 60 60 3 1 P +X IO_L26N_3 N4 -2100 100 300 R 60 60 3 1 P +X IO_L24N_3 P4 -2100 500 300 R 60 60 3 1 P +X IO_L24P_3 R4 -2100 600 300 R 60 60 3 1 P +X IO_L9P_3 T4 -2100 1400 300 R 60 60 3 1 P +X IO_L10P_3 U4 -2100 1200 300 R 60 60 3 1 P X IO_L58P_3 D5 2100 800 300 L 60 60 3 1 P X IO_L82P_3 E5 2100 1800 300 L 60 60 3 1 P X IO_L55N_M3A14_3 F5 2100 500 300 L 60 60 3 1 P X IO_L49N_M3A2_3 H5 2100 -700 300 L 60 60 3 1 P X VCCO_3 J5 500 2600 300 D 60 60 3 1 P X IO_L43P_GCLK23_M3RASN_3 K5 2100 -2000 300 L 60 60 3 1 P -X IO_L31P_3 M5 -2100 100 300 R 60 60 3 1 P +X IO_L31P_3 M5 -2100 0 300 R 60 60 3 1 P X VCCO_3 N5 -100 2600 300 D 60 60 3 1 P -X IO_L8N_3 P5 -2100 1600 300 R 60 60 3 1 P +X IO_L8N_3 P5 -2100 1500 300 R 60 60 3 1 P X VCCO_3 U5 100 2600 300 D 60 60 3 1 P X IO_L82N_3 E6 2100 1900 300 L 60 60 3 1 P X VCCO_3 F6 400 2600 300 D 60 60 3 1 P @@ -695,22 +698,22 @@ X IO_L55P_M3A13_3 G6 2100 400 300 L 60 60 3 1 P X IO_L49P_M3A7_3 H6 2100 -800 300 L 60 60 3 1 P X IO_L45N_M3ODT_3 J6 2100 -1500 300 L 60 60 3 1 P X IO_L45P_M3A3_3 K6 2100 -1600 300 L 60 60 3 1 P -X IO_L25N_3 L6 -2100 400 300 R 60 60 3 1 P -X IO_L25P_3 M6 -2100 500 300 R 60 60 3 1 P -X IO_L11P_3 N6 -2100 1100 300 R 60 60 3 1 P -X IO_L8P_3 P6 -2100 1700 300 R 60 60 3 1 P +X IO_L25N_3 L6 -2100 300 300 R 60 60 3 1 P +X IO_L25P_3 M6 -2100 400 300 R 60 60 3 1 P +X IO_L11P_3 N6 -2100 1000 300 R 60 60 3 1 P +X IO_L8P_3 P6 -2100 1600 300 R 60 60 3 1 P X IO_L80N_3 F7 2100 1500 300 L 60 60 3 1 P X IO_L80P_3 G7 2100 1400 300 L 60 60 3 1 P X IO_L59P_3 J7 2100 1000 300 L 60 60 3 1 P X IO_L57P_3 K7 2100 600 300 L 60 60 3 1 P X VCCO_3 L7 -300 2600 300 D 60 60 3 1 P -X IO_L23P_3 M7 -2100 900 300 R 60 60 3 1 P -X IO_L11N_3 N7 -2100 1000 300 R 60 60 3 1 P -X IO_L7N_3 P7 -2100 1800 300 R 60 60 3 1 P +X IO_L23P_3 M7 -2100 800 300 R 60 60 3 1 P +X IO_L11N_3 N7 -2100 900 300 R 60 60 3 1 P +X IO_L7N_3 P7 -2100 1700 300 R 60 60 3 1 P X IO_L59N_3 H8 2100 1100 300 L 60 60 3 1 P X IO_L57N_VREF_3 K8 2100 700 300 L 60 60 3 1 P -X IO_L23N_3 M8 -2100 800 300 R 60 60 3 1 P -X IO_L7P_3 P8 -2100 1900 300 R 60 60 3 1 P +X IO_L23N_3 M8 -2100 700 300 R 60 60 3 1 P +X IO_L7P_3 P8 -2100 1800 300 R 60 60 3 1 P S -1700 -2600 1700 2600 4 1 0 f X IO_L58P_2 Y3 2000 1100 300 L 60 60 4 1 P X IO_L62P_D5_2 W4 2000 1700 300 L 60 60 4 1 P @@ -748,80 +751,81 @@ X IO_L40N_2 T11 2000 -2000 300 L 60 60 4 1 P X IO_L42P_2 V11 2000 -1700 300 L 60 60 4 1 P X IO_L42N_2 W11 2000 -1600 300 L 60 60 4 1 P X IO_L32P_GCLK29_2 Y11 2000 -2300 300 L 60 60 4 1 P -X IO_L22P_2 T12 -2000 -1600 300 R 60 60 4 1 P -X IO_L22N_2 U12 -2000 -1700 300 R 60 60 4 1 P +X IO_L1P_CCLK_2 Y21 -2000 2500 300 R 60 60 4 1 P +X IO_L22P_2 T12 -2000 -1700 300 R 60 60 4 1 P +X IO_L22N_2 U12 -2000 -1800 300 R 60 60 4 1 P X VCCO_2 V12 -100 2900 300 D 60 60 4 1 P -X IO_L29P_GCLK3_2 W12 -2000 -2000 300 R 60 60 4 1 P -X IO_L29N_GCLK2_2 Y12 -2000 -2100 300 R 60 60 4 1 P +X IO_L29P_GCLK3_2 W12 -2000 -2100 300 R 60 60 4 1 P +X IO_L29N_GCLK2_2 Y12 -2000 -2200 300 R 60 60 4 1 P X IO_L64P_D8_2 AA2 2000 2100 300 L 60 60 4 1 P X IO_L64N_D9_2 AB2 2000 2200 300 L 60 60 4 1 P -X IO_L23N_2 R13 -2000 -1900 300 R 60 60 4 1 P +X IO_L23N_2 R13 -2000 -2000 300 R 60 60 4 1 P X VCCO_2 T13 -300 2900 300 D 60 60 4 1 P -X IO_L12N_D2_MISO3_2 U13 -2000 300 300 R 60 60 4 1 P -X IO_L18P_2 V13 -2000 -800 300 R 60 60 4 1 P -X IO_L18N_2 W13 -2000 -900 300 R 60 60 4 1 P -X IO_L30P_GCLK1_D13_2 Y13 -2000 -2200 300 R 60 60 4 1 P +X IO_L12N_D2_MISO3_2 U13 -2000 200 300 R 60 60 4 1 P +X IO_L18P_2 V13 -2000 -900 300 R 60 60 4 1 P +X IO_L18N_2 W13 -2000 -1000 300 R 60 60 4 1 P +X IO_L30P_GCLK1_D13_2 Y13 -2000 -2300 300 R 60 60 4 1 P X VCCO_2 AA3 0 2900 300 D 60 60 4 1 P X IO_L58N_2 AB3 2000 1200 300 L 60 60 4 1 P -X IO_L23P_2 T14 -2000 -1800 300 R 60 60 4 1 P -X IO_L12P_D1_MISO2_2 U14 -2000 400 300 R 60 60 4 1 P -X IO_L20P_2 W14 -2000 -1200 300 R 60 60 4 1 P -X IO_L20N_2 Y14 -2000 -1300 300 R 60 60 4 1 P +X IO_L23P_2 T14 -2000 -1900 300 R 60 60 4 1 P +X IO_L12P_D1_MISO2_2 U14 -2000 300 300 R 60 60 4 1 P +X IO_L20P_2 W14 -2000 -1300 300 R 60 60 4 1 P +X IO_L20N_2 Y14 -2000 -1400 300 R 60 60 4 1 P X IO_L57P_2 AA4 2000 900 300 L 60 60 4 1 P X IO_L57N_2 AB4 2000 1000 300 L 60 60 4 1 P -X IO_L10N_2 R15 -2000 700 300 R 60 60 4 1 P -X IO_L7N_2 T15 -2000 1300 300 R 60 60 4 1 P -X IO_L13P_M1_2 U15 -2000 200 300 R 60 60 4 1 P -X IO_L13N_D10_2 V15 -2000 100 300 R 60 60 4 1 P -X IO_L17N_2 W15 -2000 -700 300 R 60 60 4 1 P -X IO_L21P_2 Y15 -2000 -1400 300 R 60 60 4 1 P +X IO_L10N_2 R15 -2000 600 300 R 60 60 4 1 P +X IO_L7N_2 T15 -2000 1200 300 R 60 60 4 1 P +X IO_L13P_M1_2 U15 -2000 100 300 R 60 60 4 1 P +X IO_L13N_D10_2 V15 -2000 0 300 R 60 60 4 1 P +X IO_L17N_2 W15 -2000 -800 300 R 60 60 4 1 P +X IO_L21P_2 Y15 -2000 -1500 300 R 60 60 4 1 P X IO_L54N_2 AB5 2000 800 300 L 60 60 4 1 P -X IO_L10P_2 R16 -2000 800 300 R 60 60 4 1 P -X IO_L7P_2 T16 -2000 1400 300 R 60 60 4 1 P -X IO_L8N_2 U16 -2000 1100 300 R 60 60 4 1 P +X IO_L10P_2 R16 -2000 700 300 R 60 60 4 1 P +X IO_L7P_2 T16 -2000 1300 300 R 60 60 4 1 P +X IO_L8N_2 U16 -2000 1000 300 R 60 60 4 1 P X VCCO_2 V16 -400 2900 300 D 60 60 4 1 P -X IO_L17P_2 Y16 -2000 -600 300 R 60 60 4 1 P +X IO_L17P_2 Y16 -2000 -700 300 R 60 60 4 1 P X IO_L49P_D3_2 AA6 2000 -300 300 L 60 60 4 1 P X IO_L49N_D4_2 AB6 2000 -200 300 L 60 60 4 1 P -X IO_L4N_VREF_2 T17 -2000 1900 300 R 60 60 4 1 P -X IO_L8P_2 U17 -2000 1200 300 R 60 60 4 1 P -X IO_L11P_2 V17 -2000 600 300 R 60 60 4 1 P -X IO_L11N_2 W17 -2000 500 300 R 60 60 4 1 P -X IO_L15P_2 Y17 -2000 -200 300 R 60 60 4 1 P +X IO_L4N_VREF_2 T17 -2000 1800 300 R 60 60 4 1 P +X IO_L8P_2 U17 -2000 1100 300 R 60 60 4 1 P +X IO_L11P_2 V17 -2000 500 300 R 60 60 4 1 P +X IO_L11N_2 W17 -2000 400 300 R 60 60 4 1 P +X IO_L15P_2 Y17 -2000 -300 300 R 60 60 4 1 P X VCCO_2 AA7 500 2900 300 D 60 60 4 1 P X IO_L48N_RDWR_B_VREF_2 AB7 2000 -400 300 L 60 60 4 1 P -X IO_L4P_2 T18 -2000 2000 300 R 60 60 4 1 P -X IO_L9N_2 V18 -2000 900 300 R 60 60 4 1 P -X IO_L6P_2 W18 -2000 1600 300 R 60 60 4 1 P -X IO_L6N_2 Y18 -2000 1500 300 R 60 60 4 1 P +X IO_L4P_2 T18 -2000 1900 300 R 60 60 4 1 P +X IO_L9N_2 V18 -2000 800 300 R 60 60 4 1 P +X IO_L6P_2 W18 -2000 1500 300 R 60 60 4 1 P +X IO_L6N_2 Y18 -2000 1400 300 R 60 60 4 1 P X IO_L45P_2 AA8 2000 -1100 300 L 60 60 4 1 P X IO_L45N_2 AB8 2000 -1000 300 L 60 60 4 1 P -X IO_L9P_2 V19 -2000 1000 300 R 60 60 4 1 P -X IO_L5P_2 Y19 -2000 1800 300 R 60 60 4 1 P +X IO_L9P_2 V19 -2000 900 300 R 60 60 4 1 P +X IO_L5P_2 Y19 -2000 1700 300 R 60 60 4 1 P X IO_L43N_2 AB9 2000 -1400 300 L 60 60 4 1 P X IO_L41P_2 AA10 2000 -1900 300 L 60 60 4 1 P X IO_L41N_VREF_2 AB10 2000 -1800 300 L 60 60 4 1 P -X IO_L3P_D0_DIN_MISO_MISO1_2 AA20 -2000 2200 300 R 60 60 4 1 P -X IO_L3N_MOSI_CSI_B_MISO0_2 AB20 -2000 2100 300 R 60 60 4 1 P +X IO_L3P_D0_DIN_MISO_MISO1_2 AA20 -2000 2100 300 R 60 60 4 1 P +X IO_L3N_MOSI_CSI_B_MISO0_2 AB20 -2000 2000 300 R 60 60 4 1 P X VCCO_2 AA11 300 2900 300 D 60 60 4 1 P X IO_L32N_GCLK28_2 AB11 2000 -2200 300 L 60 60 4 1 P -X IO_L2P_CMPCLK_2 AA21 -2000 2400 300 R 60 60 4 1 P -X IO_L2N_CMPMOSI_2 AB21 -2000 2300 300 R 60 60 4 1 P +X IO_L2P_CMPCLK_2 AA21 -2000 2300 300 R 60 60 4 1 P +X IO_L2N_CMPMOSI_2 AB21 -2000 2200 300 R 60 60 4 1 P X IO_L31P_GCLK31_D14_2 AA12 2000 -2500 300 L 60 60 4 1 P X IO_L31N_GCLK30_D15_2 AB12 2000 -2400 300 L 60 60 4 1 P -X IO_L1N_M0_CMPMISO_2 AA22 -2000 2500 300 R 60 60 4 1 P -X IO_L30N_GCLK0_USERCCLK_2 AB13 -2000 -2300 300 R 60 60 4 1 P -X IO_L16P_2 AA14 -2000 -400 300 R 60 60 4 1 P -X IO_L16N_VREF_2 AB14 -2000 -500 300 R 60 60 4 1 P +X IO_L1N_M0_CMPMISO_2 AA22 -2000 2400 300 R 60 60 4 1 P +X IO_L30N_GCLK0_USERCCLK_2 AB13 -2000 -2400 300 R 60 60 4 1 P +X IO_L16P_2 AA14 -2000 -500 300 R 60 60 4 1 P +X IO_L16N_VREF_2 AB14 -2000 -600 300 R 60 60 4 1 P X VCCO_2 AA15 -500 2900 300 D 60 60 4 1 P -X IO_L21N_2 AB15 -2000 -1500 300 R 60 60 4 1 P -X IO_L19P_2 AA16 -2000 -1000 300 R 60 60 4 1 P -X IO_L19N_2 AB16 -2000 -1100 300 R 60 60 4 1 P -X IO_L15N_2 AB17 -2000 -300 300 R 60 60 4 1 P -X IO_L14P_D11_2 AA18 -2000 0 300 R 60 60 4 1 P -X IO_L14N_D12_2 AB18 -2000 -100 300 R 60 60 4 1 P +X IO_L21N_2 AB15 -2000 -1600 300 R 60 60 4 1 P +X IO_L19P_2 AA16 -2000 -1100 300 R 60 60 4 1 P +X IO_L19N_2 AB16 -2000 -1200 300 R 60 60 4 1 P +X IO_L15N_2 AB17 -2000 -400 300 R 60 60 4 1 P +X IO_L14P_D11_2 AA18 -2000 -100 300 R 60 60 4 1 P +X IO_L14N_D12_2 AB18 -2000 -200 300 R 60 60 4 1 P X VCCO_2 AA19 200 2900 300 D 60 60 4 1 P -X IO_L5N_2 AB19 -2000 1700 300 R 60 60 4 1 P +X IO_L5N_2 AB19 -2000 1600 300 R 60 60 4 1 P S -3200 -900 3200 900 5 1 0 f X GND A1 -2400 -1200 300 U 60 60 5 1 P X GND E2 800 -1200 300 U 60 60 5 1 P @@ -840,15 +844,15 @@ X GND E7 1200 -1200 300 U 60 60 5 1 P X GND H7 1800 -1200 300 U 60 60 5 1 P X GND U7 2100 -1200 300 U 60 60 5 1 P X GND W7 2700 -1200 300 U 60 60 5 1 P -X NC E8 -3500 100 300 R 60 60 5 1 P -X NC F8 -3500 -500 300 R 60 60 5 1 P -X NC G8 3500 -700 300 L 60 60 5 1 P +X NC E8 -3500 0 300 R 60 60 5 1 P +X NC F8 -3500 -600 300 R 60 60 5 1 P +X NC G8 3500 -600 300 L 60 60 5 1 P X VCCINT J8 600 1200 300 D 60 60 5 1 P X VCCAUX L8 -400 1200 300 D 60 60 5 1 P X VCCAUX N8 -600 1200 300 D 60 60 5 1 P X GND B9 -200 -1200 300 U 60 60 5 1 P -X NC F9 -3500 -600 300 R 60 60 5 1 P -X NC G9 3500 -600 300 L 60 60 5 1 P +X NC F9 -3500 -700 300 R 60 60 5 1 P +X NC G9 3500 -500 300 L 60 60 5 1 P X VCCAUX H9 -1700 1200 300 D 60 60 5 1 P X GND J9 -300 -1200 300 U 60 60 5 1 P X VCCINT K9 900 1200 300 D 60 60 5 1 P @@ -856,9 +860,9 @@ X GND L9 500 -1200 300 U 60 60 5 1 P X VCCINT M9 1500 1200 300 D 60 60 5 1 P X GND N9 2900 -1200 300 U 60 60 5 1 P X VCCINT P9 0 1200 300 D 60 60 5 1 P -X NC E10 -3500 400 300 R 60 60 5 1 P -X NC F10 -3500 0 300 R 60 60 5 1 P -X NC H10 3500 -500 300 L 60 60 5 1 P +X NC E10 -3500 300 300 R 60 60 5 1 P +X NC F10 -3500 -100 300 R 60 60 5 1 P +X NC H10 3500 -400 300 L 60 60 5 1 P X VCCINT J10 300 1200 300 D 60 60 5 1 P X GND K10 -2600 -1200 300 U 60 60 5 1 P X VCCINT L10 1000 1200 300 D 60 60 5 1 P @@ -867,10 +871,11 @@ X VCCINT N10 -300 1200 300 D 60 60 5 1 P X GND P10 -2900 -1200 300 U 60 60 5 1 P X VCCAUX R10 -500 1200 300 D 60 60 5 1 P X GND V10 -2800 -1200 300 U 60 60 5 1 P +X CMPCS_B_2 Y20 -3500 800 300 R 60 60 5 1 P X GND E11 400 -1200 300 U 60 60 5 1 P X VCCAUX F11 -1500 1200 300 D 60 60 5 1 P -X NC G11 -3500 -700 300 R 60 60 5 1 P -X NC H11 3500 -400 300 L 60 60 5 1 P +X NC G11 3500 -800 300 L 60 60 5 1 P +X NC H11 3500 -300 300 L 60 60 5 1 P X GND J11 2000 -1200 300 U 60 60 5 1 P X VCCINT K11 700 1200 300 D 60 60 5 1 P X GND L11 100 -1200 300 U 60 60 5 1 P @@ -882,13 +887,13 @@ X GND E21 1000 -1200 300 U 60 60 5 1 P X GND J21 2800 -1200 300 U 60 60 5 1 P X GND N21 1300 -1200 300 U 60 60 5 1 P X GND U21 -700 -1200 300 U 60 60 5 1 P -X PROGRAM_B_2 AA1 3500 200 300 L 60 60 5 1 P +X PROGRAM_B_2 AA1 3500 300 300 L 60 60 5 1 P X GND AB1 -1200 -1200 300 U 60 60 5 1 P -X NC D12 -3500 500 300 R 60 60 5 1 P -X NC E12 -3500 300 300 R 60 60 5 1 P -X NC F12 -3500 -100 300 R 60 60 5 1 P +X NC D12 -3500 400 300 R 60 60 5 1 P +X NC E12 -3500 200 300 R 60 60 5 1 P +X NC F12 -3500 -200 300 R 60 60 5 1 P X VCCAUX G12 -1100 1200 300 D 60 60 5 1 P -X NC H12 3500 -300 300 L 60 60 5 1 P +X NC H12 3500 -200 300 L 60 60 5 1 P X VCCINT J12 400 1200 300 D 60 60 5 1 P X GND K12 -100 -1200 300 U 60 60 5 1 P X VCCINT L12 1100 1200 300 D 60 60 5 1 P @@ -897,21 +902,21 @@ X VCCINT N12 200 1200 300 D 60 60 5 1 P X GND P12 1500 -1200 300 U 60 60 5 1 P X VCCAUX R12 -700 1200 300 D 60 60 5 1 P X GND A22 -2200 -1200 300 U 60 60 5 1 P -X DONE_2 Y22 -3500 800 300 R 60 60 5 1 P +X DONE_2 Y22 -3500 700 300 R 60 60 5 1 P X GND B13 -800 -1200 300 U 60 60 5 1 P -X NC D13 3500 100 300 L 60 60 5 1 P -X NC F13 -3500 -200 300 R 60 60 5 1 P -X NC G13 3500 -800 300 L 60 60 5 1 P -X NC H13 3500 -200 300 L 60 60 5 1 P +X NC D13 3500 200 300 L 60 60 5 1 P +X NC F13 -3500 -300 300 R 60 60 5 1 P +X NC G13 3500 -700 300 L 60 60 5 1 P +X NC H13 3500 -100 300 L 60 60 5 1 P X GND J13 2200 -1200 300 U 60 60 5 1 P X VCCINT K13 800 1200 300 D 60 60 5 1 P X GND L13 -2500 -1200 300 U 60 60 5 1 P X VCCINT M13 1400 1200 300 D 60 60 5 1 P X GND N13 -2300 -1200 300 U 60 60 5 1 P X VCCINT P13 -100 1200 300 D 60 60 5 1 P -X NC E14 -3500 200 300 R 60 60 5 1 P -X NC F14 -3500 -300 300 R 60 60 5 1 P -X NC H14 3500 -100 300 L 60 60 5 1 P +X NC E14 -3500 100 300 R 60 60 5 1 P +X NC F14 -3500 -400 300 R 60 60 5 1 P +X NC H14 3500 0 300 L 60 60 5 1 P X VCCINT J14 500 1200 300 D 60 60 5 1 P X GND K14 -1700 -1200 300 U 60 60 5 1 P X VCCINT L14 1200 1200 300 D 60 60 5 1 P @@ -921,28 +926,28 @@ X GND P14 -900 -1200 300 U 60 60 5 1 P X VCCINT R14 100 1200 300 D 60 60 5 1 P X GND V14 2300 -1200 300 U 60 60 5 1 P X GND E15 600 -1200 300 U 60 60 5 1 P -X NC F15 -3500 -400 300 R 60 60 5 1 P -X TCK G15 3500 400 300 L 60 60 5 1 P +X NC F15 -3500 -500 300 R 60 60 5 1 P +X TCK G15 3500 500 300 L 60 60 5 1 P X VCCAUX H15 -1000 1200 300 D 60 60 5 1 P X GND J15 2400 -1200 300 U 60 60 5 1 P X VCCAUX K15 -800 1200 300 D 60 60 5 1 P X VCCAUX M15 -1300 1200 300 D 60 60 5 1 P -X SUSPEND N15 3500 300 300 L 60 60 5 1 P -X NC P15 -3500 600 300 R 60 60 5 1 P +X SUSPEND N15 3500 400 300 L 60 60 5 1 P +X NC P15 -3500 500 300 R 60 60 5 1 P X GND AA5 -1600 -1200 300 U 60 60 5 1 P X VCCAUX D16 -900 1200 300 D 60 60 5 1 P -X NC P16 3500 0 300 L 60 60 5 1 P +X NC P16 3500 100 300 L 60 60 5 1 P X GND W16 2500 -1200 300 U 60 60 5 1 P X GND B17 -600 -1200 300 U 60 60 5 1 P X GND N17 1100 -1200 300 U 60 60 5 1 P -X NC R17 -3500 700 300 R 60 60 5 1 P -X TMS C18 3500 700 300 L 60 60 5 1 P +X NC R17 -3500 600 300 R 60 60 5 1 P +X TMS C18 3500 800 300 L 60 60 5 1 P X GND D18 0 -1200 300 U 60 60 5 1 P -X TDI E18 3500 500 300 L 60 60 5 1 P +X TDI E18 3500 600 300 L 60 60 5 1 P X GND G18 1400 -1200 300 U 60 60 5 1 P X GND L18 300 -1200 300 U 60 60 5 1 P X GND R18 1700 -1200 300 U 60 60 5 1 P -X TDO A19 3500 600 300 L 60 60 5 1 P +X TDO A19 3500 700 300 L 60 60 5 1 P X GND W19 -1900 -1200 300 U 60 60 5 1 P X GND AA9 -1400 -1200 300 U 60 60 5 1 P X GND AB22 -1000 -1200 300 U 60 60 5 1 P diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 0daf45e..e7c7257 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Sat 14 Aug 2010 07:26:51 AM COT +PCBNEW-BOARD Version 1 date Sat 14 Aug 2010 08:21:23 AM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -86,551 +86,551 @@ Na 4 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/DDR_Ban102" +Na 5 "/DDR_Banks/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Ban103" +Na 6 "/DDR_Banks/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Ban106" +Na 7 "/DDR_Banks/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Ban108" +Na 8 "/DDR_Banks/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Ban112" +Na 9 "/DDR_Banks/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Ban113" +Na 10 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Ban119" +Na 11 "/DDR_Banks/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Ban120" +Na 12 "/DDR_Banks/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Ban121" +Na 13 "/DDR_Banks/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Ban124" +Na 14 "/DDR_Banks/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Ban33" +Na 15 "/DDR_Banks/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Ban57" +Na 16 "/DDR_Banks/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Ban61" +Na 17 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Ban66" +Na 18 "/DDR_Banks/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Ban68" +Na 19 "/DDR_Banks/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Ban78" +Na 20 "/DDR_Banks/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Ban80" +Na 21 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Ban81" +Na 22 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Ban83" +Na 23 "/DDR_Banks/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Ban85" +Na 24 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Ban88" +Na 25 "/DDR_Banks/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Ban92" +Na 26 "/DDR_Banks/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Ban97" +Na 27 "/DDR_Banks/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Ban98" +Na 28 "/DDR_Banks/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Ban99" +Na 29 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M0_A0" +Na 30 "/DDR_Banks/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M0_A3" +Na 31 "/DDR_Banks/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M0_A8" +Na 32 "/DDR_Banks/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_A0" +Na 33 "/DDR_Banks/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/Etherne1" +Na 34 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/Etherne11" +Na 35 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/Etherne12" +Na 36 "/DDR_Banks/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/Etherne13" +Na 37 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/Etherne14" +Na 38 "/Ethernet_Phy/ETH_1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/Etherne15" +Na 39 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Etherne16" +Na 40 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Etherne17" +Na 41 "/Ethernet_Phy/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Etherne19" +Na 42 "/Ethernet_Phy/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Etherne2" +Na 43 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Etherne29" +Na 44 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Etherne3" +Na 45 "/Ethernet_Phy/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Etherne37" +Na 46 "/Ethernet_Phy/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Etherne39" +Na 47 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Etherne4" +Na 48 "/Ethernet_Phy/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Etherne49" +Na 49 "/Ethernet_Phy/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Etherne50" +Na 50 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Etherne52" +Na 51 "/Ethernet_Phy/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Sp10" +Na 52 "/Ethernet_Phy/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Sp100" +Na 53 "/Ethernet_Phy/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Sp101" +Na 54 "/Ethernet_Phy/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Sp104" +Na 55 "/Ethernet_Phy/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Sp105" +Na 56 "/FPGA_Spartan6/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Sp107" +Na 57 "/FPGA_Spartan6/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Sp109" +Na 58 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Sp110" +Na 59 "/FPGA_Spartan6/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Sp111" +Na 60 "/FPGA_Spartan6/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Sp114" +Na 61 "/FPGA_Spartan6/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Sp115" +Na 62 "/FPGA_Spartan6/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Sp116" +Na 63 "/FPGA_Spartan6/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Sp117" +Na 64 "/FPGA_Spartan6/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Sp118" +Na 65 "/FPGA_Spartan6/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Sp122" +Na 66 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Sp123" +Na 67 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Sp125" +Na 68 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Sp126" +Na 69 "/FPGA_Spartan6/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Sp127" +Na 70 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Sp128" +Na 71 "/FPGA_Spartan6/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Sp129" +Na 72 "/FPGA_Spartan6/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Sp130" +Na 73 "/FPGA_Spartan6/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Sp131" +Na 74 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Sp132" +Na 75 "/FPGA_Spartan6/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Sp133" +Na 76 "/FPGA_Spartan6/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Sp18" +Na 77 "/FPGA_Spartan6/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Sp23" +Na 78 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Sp24" +Na 79 "/FPGA_Spartan6/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Sp25" +Na 80 "/FPGA_Spartan6/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Sp26" +Na 81 "/FPGA_Spartan6/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Sp27" +Na 82 "/FPGA_Spartan6/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Sp28" +Na 83 "/FPGA_Spartan6/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Sp30" +Na 84 "/FPGA_Spartan6/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Sp32" +Na 85 "/FPGA_Spartan6/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Sp34" +Na 86 "/FPGA_Spartan6/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Sp35" +Na 87 "/FPGA_Spartan6/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Sp36" +Na 88 "/FPGA_Spartan6/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Sp38" +Na 89 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Sp41" +Na 90 "/FPGA_Spartan6/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Sp44" +Na 91 "/FPGA_Spartan6/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Sp45" +Na 92 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Sp46" +Na 93 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Sp47" +Na 94 "/FPGA_Spartan6/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Sp48" +Na 95 "/FPGA_Spartan6/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Sp51" +Na 96 "/FPGA_Spartan6/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Sp56" +Na 97 "/FPGA_Spartan6/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Sp58" +Na 98 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Sp59" +Na 99 "/FPGA_Spartan6/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Sp60" +Na 100 "/FPGA_Spartan6/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Sp62" +Na 101 "/FPGA_Spartan6/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Sp63" +Na 102 "/FPGA_Spartan6/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Sp64" +Na 103 "/FPGA_Spartan6/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Sp65" +Na 104 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Sp67" +Na 105 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Sp69" +Na 106 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Sp7" +Na 107 "/FPGA_Spartan6/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Sp70" +Na 108 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Sp71" +Na 109 "/FPGA_Spartan6/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Sp72" +Na 110 "/FPGA_Spartan6/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Sp73" +Na 111 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Sp74" +Na 112 "/FPGA_Spartan6/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Sp75" +Na 113 "/FPGA_Spartan6/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Sp76" +Na 114 "/FPGA_Spartan6/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Sp77" +Na 115 "/FPGA_Spartan6/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Sp79" +Na 116 "/FPGA_Spartan6/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Sp8" +Na 117 "/FPGA_Spartan6/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA_Sp82" +Na 118 "/FPGA_Spartan6/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Sp84" +Na 119 "/FPGA_Spartan6/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Sp86" +Na 120 "/FPGA_Spartan6/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Sp87" +Na 121 "/FPGA_Spartan6/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Sp89" +Na 122 "/FPGA_Spartan6/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Sp90" +Na 123 "/FPGA_Spartan6/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Sp91" +Na 124 "/FPGA_Spartan6/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Sp93" +Na 125 "/FPGA_Spartan6/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Sp94" +Na 126 "/FPGA_Spartan6/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Sp95" +Na 127 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Sp96" +Na 128 "/FPGA_Spartan6/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/Non_vol20" +Na 129 "/FPGA_Spartan6/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/Non_vol21" +Na 130 "/FPGA_Spartan6/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/Non_vol22" +Na 131 "/FPGA_Spartan6/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/Non_vol31" +Na 132 "/FPGA_Spartan6/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/Non_vol40" +Na 133 "/FPGA_Spartan6/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/Non_vol42" +Na 134 "/Non_volatile_memories/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/Non_vol43" +Na 135 "/Non_volatile_memories/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/Non_vol5" +Na 136 "/Non_volatile_memories/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/Non_vol53" +Na 137 "/Non_volatile_memories/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/Non_vol54" +Na 138 "/Non_volatile_memories/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/Non_vol55" +Na 139 "/Non_volatile_memories/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/Non_vol6" +Na 140 "/Non_volatile_memories/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/Non_vol9" +Na 141 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT @@ -670,95 +670,95 @@ Na 150 "N-000054" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "N-000147" +Na 151 "N-000149" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "N-000314" +Na 152 "N-000319" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "N-000315" +Na 153 "N-000320" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "N-000317" +Na 154 "N-000322" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "N-000318" +Na 155 "N-000323" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "N-000321" +Na 156 "N-000326" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "N-000326" +Na 157 "N-000331" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "N-000327" +Na 158 "N-000332" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "N-000328" +Na 159 "N-000333" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "N-000329" +Na 160 "N-000334" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "N-000331" +Na 161 "N-000336" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "N-000337" +Na 162 "N-000342" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "N-000338" +Na 163 "N-000343" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "N-000339" +Na 164 "N-000346" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "N-000345" +Na 165 "N-000350" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "N-000349" +Na 166 "N-000354" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "N-000350" +Na 167 "N-000355" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "N-000351" +Na 168 "N-000356" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "N-000352" +Na 169 "N-000357" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "N-000353" +Na 170 "N-000358" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "N-000354" +Na 171 "N-000359" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "N-000355" +Na 172 "N-000360" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "N-000356" +Na 173 "N-000361" St ~ $EndEQUIPOT $EQUIPOT @@ -779,143 +779,143 @@ AddNet "+1.2V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" -AddNet "/DDR_Ban102" -AddNet "/DDR_Ban103" -AddNet "/DDR_Ban106" -AddNet "/DDR_Ban108" -AddNet "/DDR_Ban112" -AddNet "/DDR_Ban113" -AddNet "/DDR_Ban119" -AddNet "/DDR_Ban120" -AddNet "/DDR_Ban121" -AddNet "/DDR_Ban124" -AddNet "/DDR_Ban33" -AddNet "/DDR_Ban57" -AddNet "/DDR_Ban61" -AddNet "/DDR_Ban66" -AddNet "/DDR_Ban68" -AddNet "/DDR_Ban78" -AddNet "/DDR_Ban80" -AddNet "/DDR_Ban81" -AddNet "/DDR_Ban83" -AddNet "/DDR_Ban85" -AddNet "/DDR_Ban88" -AddNet "/DDR_Ban92" -AddNet "/DDR_Ban97" -AddNet "/DDR_Ban98" -AddNet "/DDR_Ban99" -AddNet "/DDR_Banks/M0_A0" -AddNet "/DDR_Banks/M0_A3" -AddNet "/DDR_Banks/M0_A8" +AddNet "/DDR_Banks/M0_A1" +AddNet "/DDR_Banks/M0_A2" +AddNet "/DDR_Banks/M0_BA0" +AddNet "/DDR_Banks/M0_CKE" +AddNet "/DDR_Banks/M0_CLK" +AddNet "/DDR_Banks/M0_CLK#" +AddNet "/DDR_Banks/M0_DQ0" +AddNet "/DDR_Banks/M0_DQ10" +AddNet "/DDR_Banks/M0_DQ11" +AddNet "/DDR_Banks/M0_DQ13" +AddNet "/DDR_Banks/M0_DQ15" +AddNet "/DDR_Banks/M0_DQ3" +AddNet "/DDR_Banks/M0_DQ4" +AddNet "/DDR_Banks/M0_DQ7" +AddNet "/DDR_Banks/M0_UDM" +AddNet "/DDR_Banks/M0_UDQS" +AddNet "/DDR_Banks/M0_WE#" AddNet "/DDR_Banks/M1_A0" -AddNet "/Etherne1" -AddNet "/Etherne11" -AddNet "/Etherne12" -AddNet "/Etherne13" -AddNet "/Etherne14" -AddNet "/Etherne15" -AddNet "/Etherne16" -AddNet "/Etherne17" -AddNet "/Etherne19" -AddNet "/Etherne2" -AddNet "/Etherne29" -AddNet "/Etherne3" -AddNet "/Etherne37" -AddNet "/Etherne39" -AddNet "/Etherne4" -AddNet "/Etherne49" -AddNet "/Etherne50" -AddNet "/Etherne52" -AddNet "/FPGA_Sp10" -AddNet "/FPGA_Sp100" -AddNet "/FPGA_Sp101" -AddNet "/FPGA_Sp104" -AddNet "/FPGA_Sp105" -AddNet "/FPGA_Sp107" -AddNet "/FPGA_Sp109" -AddNet "/FPGA_Sp110" -AddNet "/FPGA_Sp111" -AddNet "/FPGA_Sp114" -AddNet "/FPGA_Sp115" -AddNet "/FPGA_Sp116" -AddNet "/FPGA_Sp117" -AddNet "/FPGA_Sp118" -AddNet "/FPGA_Sp122" -AddNet "/FPGA_Sp123" -AddNet "/FPGA_Sp125" -AddNet "/FPGA_Sp126" -AddNet "/FPGA_Sp127" -AddNet "/FPGA_Sp128" -AddNet "/FPGA_Sp129" -AddNet "/FPGA_Sp130" -AddNet "/FPGA_Sp131" -AddNet "/FPGA_Sp132" -AddNet "/FPGA_Sp133" -AddNet "/FPGA_Sp18" -AddNet "/FPGA_Sp23" -AddNet "/FPGA_Sp24" -AddNet "/FPGA_Sp25" -AddNet "/FPGA_Sp26" -AddNet "/FPGA_Sp27" -AddNet "/FPGA_Sp28" -AddNet "/FPGA_Sp30" -AddNet "/FPGA_Sp32" -AddNet "/FPGA_Sp34" -AddNet "/FPGA_Sp35" -AddNet "/FPGA_Sp36" -AddNet "/FPGA_Sp38" -AddNet "/FPGA_Sp41" -AddNet "/FPGA_Sp44" -AddNet "/FPGA_Sp45" -AddNet "/FPGA_Sp46" -AddNet "/FPGA_Sp47" -AddNet "/FPGA_Sp48" -AddNet "/FPGA_Sp51" -AddNet "/FPGA_Sp56" -AddNet "/FPGA_Sp58" -AddNet "/FPGA_Sp59" -AddNet "/FPGA_Sp60" -AddNet "/FPGA_Sp62" -AddNet "/FPGA_Sp63" -AddNet "/FPGA_Sp64" -AddNet "/FPGA_Sp65" -AddNet "/FPGA_Sp67" -AddNet "/FPGA_Sp69" -AddNet "/FPGA_Sp7" -AddNet "/FPGA_Sp70" -AddNet "/FPGA_Sp71" -AddNet "/FPGA_Sp72" -AddNet "/FPGA_Sp73" -AddNet "/FPGA_Sp74" -AddNet "/FPGA_Sp75" -AddNet "/FPGA_Sp76" -AddNet "/FPGA_Sp77" -AddNet "/FPGA_Sp79" -AddNet "/FPGA_Sp8" -AddNet "/FPGA_Sp82" -AddNet "/FPGA_Sp84" -AddNet "/FPGA_Sp86" -AddNet "/FPGA_Sp87" -AddNet "/FPGA_Sp89" -AddNet "/FPGA_Sp90" -AddNet "/FPGA_Sp91" -AddNet "/FPGA_Sp93" -AddNet "/FPGA_Sp94" -AddNet "/FPGA_Sp95" -AddNet "/FPGA_Sp96" -AddNet "/Non_vol20" -AddNet "/Non_vol21" -AddNet "/Non_vol22" -AddNet "/Non_vol31" -AddNet "/Non_vol40" -AddNet "/Non_vol42" -AddNet "/Non_vol43" -AddNet "/Non_vol5" -AddNet "/Non_vol53" -AddNet "/Non_vol54" -AddNet "/Non_vol55" -AddNet "/Non_vol6" -AddNet "/Non_vol9" +AddNet "/DDR_Banks/M1_A10" +AddNet "/DDR_Banks/M1_A5" +AddNet "/DDR_Banks/M1_A9" +AddNet "/DDR_Banks/M1_BA0" +AddNet "/DDR_Banks/M1_BA1" +AddNet "/DDR_Banks/M1_CKE" +AddNet "/DDR_Banks/M1_DQ10" +AddNet "/DDR_Banks/M1_DQ11" +AddNet "/DDR_Banks/M1_DQ13" +AddNet "/DDR_Banks/M1_DQ4" +AddNet "/DDR_Banks/M1_DQ5" +AddNet "/DDR_Banks/M1_RAS#" +AddNet "/DDR_Banks/M1_UDM" +AddNet "/DDR_Banks/M1_UDQS" +AddNet "/DDR_Banks/M1_WE#" +AddNet "/Ethernet_Phy/ETH_1.8V" +AddNet "/Ethernet_Phy/ETH_A1.8V" +AddNet "/Ethernet_Phy/ETH_A3.3V" +AddNet "/Ethernet_Phy/ETH_CLK" +AddNet "/Ethernet_Phy/ETH_COL" +AddNet "/Ethernet_Phy/ETH_LED0" +AddNet "/Ethernet_Phy/ETH_LED1" +AddNet "/Ethernet_Phy/ETH_MDC" +AddNet "/Ethernet_Phy/ETH_MDIO" +AddNet "/Ethernet_Phy/ETH_PLL1.8V" +AddNet "/Ethernet_Phy/ETH_RXC" +AddNet "/Ethernet_Phy/ETH_RXD0" +AddNet "/Ethernet_Phy/ETH_RXD1" +AddNet "/Ethernet_Phy/ETH_RXD2" +AddNet "/Ethernet_Phy/ETH_RXER" +AddNet "/Ethernet_Phy/ETH_TXD0" +AddNet "/Ethernet_Phy/ETH_TXD1" +AddNet "/Ethernet_Phy/ETH_TXD3" +AddNet "/FPGA_Spartan6/ETH_CRS" +AddNet "/FPGA_Spartan6/ETH_INT" +AddNet "/FPGA_Spartan6/ETH_RESET_N" +AddNet "/FPGA_Spartan6/ETH_RXD3" +AddNet "/FPGA_Spartan6/ETH_RXDV" +AddNet "/FPGA_Spartan6/ETH_TXC" +AddNet "/FPGA_Spartan6/ETH_TXD2" +AddNet "/FPGA_Spartan6/ETH_TXEN" +AddNet "/FPGA_Spartan6/ETH_TXER" +AddNet "/FPGA_Spartan6/M0_A0" +AddNet "/FPGA_Spartan6/M0_A10" +AddNet "/FPGA_Spartan6/M0_A11" +AddNet "/FPGA_Spartan6/M0_A12" +AddNet "/FPGA_Spartan6/M0_A3" +AddNet "/FPGA_Spartan6/M0_A4" +AddNet "/FPGA_Spartan6/M0_A5" +AddNet "/FPGA_Spartan6/M0_A6" +AddNet "/FPGA_Spartan6/M0_A7" +AddNet "/FPGA_Spartan6/M0_A8" +AddNet "/FPGA_Spartan6/M0_A9" +AddNet "/FPGA_Spartan6/M0_BA1" +AddNet "/FPGA_Spartan6/M0_CAS#" +AddNet "/FPGA_Spartan6/M0_DQ1" +AddNet "/FPGA_Spartan6/M0_DQ12" +AddNet "/FPGA_Spartan6/M0_DQ14" +AddNet "/FPGA_Spartan6/M0_DQ2" +AddNet "/FPGA_Spartan6/M0_DQ5" +AddNet "/FPGA_Spartan6/M0_DQ6" +AddNet "/FPGA_Spartan6/M0_DQ8" +AddNet "/FPGA_Spartan6/M0_DQ9" +AddNet "/FPGA_Spartan6/M0_LDM" +AddNet "/FPGA_Spartan6/M0_LDQS" +AddNet "/FPGA_Spartan6/M0_RAS#" +AddNet "/FPGA_Spartan6/M1_A1" +AddNet "/FPGA_Spartan6/M1_A11" +AddNet "/FPGA_Spartan6/M1_A12" +AddNet "/FPGA_Spartan6/M1_A2" +AddNet "/FPGA_Spartan6/M1_A3" +AddNet "/FPGA_Spartan6/M1_A4" +AddNet "/FPGA_Spartan6/M1_A6" +AddNet "/FPGA_Spartan6/M1_A7" +AddNet "/FPGA_Spartan6/M1_A8" +AddNet "/FPGA_Spartan6/M1_CAS#" +AddNet "/FPGA_Spartan6/M1_CLK" +AddNet "/FPGA_Spartan6/M1_CLK#" +AddNet "/FPGA_Spartan6/M1_DQ0" +AddNet "/FPGA_Spartan6/M1_DQ1" +AddNet "/FPGA_Spartan6/M1_DQ12" +AddNet "/FPGA_Spartan6/M1_DQ14" +AddNet "/FPGA_Spartan6/M1_DQ15" +AddNet "/FPGA_Spartan6/M1_DQ2" +AddNet "/FPGA_Spartan6/M1_DQ3" +AddNet "/FPGA_Spartan6/M1_DQ6" +AddNet "/FPGA_Spartan6/M1_DQ7" +AddNet "/FPGA_Spartan6/M1_DQ8" +AddNet "/FPGA_Spartan6/M1_DQ9" +AddNet "/FPGA_Spartan6/M1_LDM" +AddNet "/FPGA_Spartan6/M1_LDQS" +AddNet "/FPGA_Spartan6/NF_ALE" +AddNet "/FPGA_Spartan6/NF_CLE" +AddNet "/FPGA_Spartan6/NF_CS1_N" +AddNet "/FPGA_Spartan6/NF_D0" +AddNet "/FPGA_Spartan6/NF_D6" +AddNet "/FPGA_Spartan6/NF_D7" +AddNet "/FPGA_Spartan6/NF_RE_N" +AddNet "/FPGA_Spartan6/NF_RNB" +AddNet "/FPGA_Spartan6/PROG_CCLK" +AddNet "/FPGA_Spartan6/PROG_CSO" +AddNet "/FPGA_Spartan6/PROG_MISO0" +AddNet "/FPGA_Spartan6/PROG_MISO1" +AddNet "/FPGA_Spartan6/PROG_MISO2" +AddNet "/FPGA_Spartan6/PROG_MISO3" +AddNet "/FPGA_Spartan6/SD_CLK" +AddNet "/FPGA_Spartan6/SD_CMD" +AddNet "/FPGA_Spartan6/SD_DAT1" +AddNet "/FPGA_Spartan6/SD_DAT3" +AddNet "/FPGA_Spartan6/USBA_OE_N" +AddNet "/FPGA_Spartan6/USBA_RCV" +AddNet "/Non_volatile_memories/NF_D1" +AddNet "/Non_volatile_memories/NF_D2" +AddNet "/Non_volatile_memories/NF_D3" +AddNet "/Non_volatile_memories/NF_D4" +AddNet "/Non_volatile_memories/NF_D5" +AddNet "/Non_volatile_memories/NF_WE_N" +AddNet "/Non_volatile_memories/SD_DAT0" +AddNet "/Non_volatile_memories/SD_DAT2" AddNet "/USB/USBA_SPD" AddNet "/USB/USBA_VM" AddNet "/USB/USBA_VP" @@ -925,29 +925,29 @@ AddNet "N-000050" AddNet "N-000051" AddNet "N-000052" AddNet "N-000054" -AddNet "N-000147" -AddNet "N-000314" -AddNet "N-000315" -AddNet "N-000317" -AddNet "N-000318" -AddNet "N-000321" +AddNet "N-000149" +AddNet "N-000319" +AddNet "N-000320" +AddNet "N-000322" +AddNet "N-000323" AddNet "N-000326" -AddNet "N-000327" -AddNet "N-000328" -AddNet "N-000329" AddNet "N-000331" -AddNet "N-000337" -AddNet "N-000338" -AddNet "N-000339" -AddNet "N-000345" -AddNet "N-000349" +AddNet "N-000332" +AddNet "N-000333" +AddNet "N-000334" +AddNet "N-000336" +AddNet "N-000342" +AddNet "N-000343" +AddNet "N-000346" AddNet "N-000350" -AddNet "N-000351" -AddNet "N-000352" -AddNet "N-000353" AddNet "N-000354" AddNet "N-000355" AddNet "N-000356" +AddNet "N-000357" +AddNet "N-000358" +AddNet "N-000359" +AddNet "N-000360" +AddNet "N-000361" AddNet "VCCO2" $EndNCLASS $MODULE 1206 @@ -1020,70 +1020,70 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Etherne14" +Ne 41 "/Ethernet_Phy/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Etherne11" +Ne 58 "/FPGA_Spartan6/ETH_RESET_N" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Etherne15" +Ne 49 "/Ethernet_Phy/ETH_RXD0" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Etherne16" +Ne 52 "/Ethernet_Phy/ETH_RXER" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Etherne17" +Ne 63 "/FPGA_Spartan6/ETH_TXEN" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Sp18" +Ne 55 "/Ethernet_Phy/ETH_TXD3" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Etherne19" +Ne 57 "/FPGA_Spartan6/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/Non_vol20" +Ne 119 "/FPGA_Spartan6/NF_D7" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/Non_vol21" +Ne 136 "/Non_volatile_memories/NF_D3" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/Non_vol22" +Ne 134 "/Non_volatile_memories/NF_D1" Po 590 -4133 $EndPAD $PAD @@ -1097,28 +1097,28 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Sp23" +Ne 114 "/FPGA_Spartan6/NF_ALE" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Sp24" +Ne 121 "/FPGA_Spartan6/NF_RNB" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/Non_vol5" +Ne 141 "/Non_volatile_memories/SD_DAT2" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/Non_vol9" +Ne 140 "/Non_volatile_memories/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -1188,7 +1188,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Sp28" +Ne 50 "/Ethernet_Phy/ETH_RXD1" Po -2165 -3739 $EndPAD $PAD @@ -1202,7 +1202,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Etherne29" +Ne 64 "/FPGA_Spartan6/ETH_TXER" Po -1377 -3739 $EndPAD $PAD @@ -1216,7 +1216,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Sp30" +Ne 42 "/Ethernet_Phy/ETH_COL" Po -590 -3739 $EndPAD $PAD @@ -1230,7 +1230,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/Non_vol31" +Ne 137 "/Non_volatile_memories/NF_D4" Po 196 -3739 $EndPAD $PAD @@ -1258,7 +1258,7 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Sp32" +Ne 120 "/FPGA_Spartan6/NF_RE_N" Po 1771 -3739 $EndPAD $PAD @@ -1272,7 +1272,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Sp10" +Ne 130 "/FPGA_Spartan6/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1307,7 +1307,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Ban33" +Ne 67 "/FPGA_Spartan6/M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1335,42 +1335,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Sp34" +Ne 46 "/Ethernet_Phy/ETH_MDIO" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Sp35" +Ne 51 "/Ethernet_Phy/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Sp36" +Ne 60 "/FPGA_Spartan6/ETH_RXDV" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Etherne37" +Ne 54 "/Ethernet_Phy/ETH_TXD1" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Sp38" +Ne 62 "/FPGA_Spartan6/ETH_TXD2" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Etherne39" +Ne 56 "/FPGA_Spartan6/ETH_CRS" Po -590 -3346 $EndPAD $PAD @@ -1384,14 +1384,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/Non_vol40" +Ne 138 "/Non_volatile_memories/NF_D5" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Sp41" +Ne 135 "/Non_volatile_memories/NF_D2" Po 590 -3346 $EndPAD $PAD @@ -1405,21 +1405,21 @@ $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/Non_vol42" +Ne 139 "/Non_volatile_memories/NF_WE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/Non_vol43" +Ne 116 "/FPGA_Spartan6/NF_CS1_N" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/Non_vol6" +Ne 131 "/FPGA_Spartan6/SD_DAT3" Po 2165 -3346 $EndPAD $PAD @@ -1440,7 +1440,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Sp44" +Ne 97 "/FPGA_Spartan6/M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1454,21 +1454,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Sp45" +Ne 25 "/DDR_Banks/M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Sp46" +Ne 68 "/FPGA_Spartan6/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Sp47" +Ne 8 "/DDR_Banks/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1496,42 +1496,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Sp48" +Ne 59 "/FPGA_Spartan6/ETH_RXD3" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Etherne49" +Ne 61 "/FPGA_Spartan6/ETH_TXC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Etherne50" +Ne 48 "/Ethernet_Phy/ETH_RXC" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Sp51" +Ne 53 "/Ethernet_Phy/ETH_TXD0" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Etherne52" +Ne 45 "/Ethernet_Phy/ETH_MDC" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/Non_vol53" +Ne 118 "/FPGA_Spartan6/NF_D6" Po -196 -2952 $EndPAD $PAD @@ -1552,14 +1552,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/Non_vol54" +Ne 117 "/FPGA_Spartan6/NF_D0" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/Non_vol55" +Ne 115 "/FPGA_Spartan6/NF_CLE" Po 1377 -2952 $EndPAD $PAD @@ -1573,7 +1573,7 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Sp7" +Ne 129 "/FPGA_Spartan6/SD_CMD" Po 2165 -2952 $EndPAD $PAD @@ -1601,21 +1601,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Sp56" +Ne 28 "/DDR_Banks/M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Ban57" +Ne 91 "/FPGA_Spartan6/M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Sp58" +Ne 75 "/FPGA_Spartan6/M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -1629,7 +1629,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M0_A8" +Ne 74 "/FPGA_Spartan6/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1720,7 +1720,7 @@ $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Sp8" +Ne 128 "/FPGA_Spartan6/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -1748,7 +1748,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Sp59" +Ne 96 "/FPGA_Spartan6/M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -1762,7 +1762,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Sp60" +Ne 92 "/FPGA_Spartan6/M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -1776,14 +1776,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Ban61" +Ne 21 "/DDR_Banks/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Sp62" +Ne 70 "/FPGA_Spartan6/M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -1895,35 +1895,35 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Sp63" +Ne 90 "/FPGA_Spartan6/M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Sp64" +Ne 94 "/FPGA_Spartan6/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_A0" +Ne 22 "/DDR_Banks/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Sp65" +Ne 89 "/FPGA_Spartan6/M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Ban66" +Ne 76 "/FPGA_Spartan6/M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -1937,14 +1937,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Sp67" +Ne 7 "/DDR_Banks/M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Ban68" +Ne 66 "/FPGA_Spartan6/M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -2049,14 +2049,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Sp69" +Ne 23 "/DDR_Banks/M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Sp70" +Ne 93 "/FPGA_Spartan6/M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2077,42 +2077,42 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Sp71" +Ne 5 "/DDR_Banks/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M0_A0" +Ne 65 "/FPGA_Spartan6/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Sp72" +Ne 10 "/DDR_Banks/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Sp73" +Ne 9 "/DDR_Banks/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Sp74" +Ne 6 "/DDR_Banks/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Sp75" +Ne 73 "/FPGA_Spartan6/M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -2203,35 +2203,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Sp76" +Ne 37 "/DDR_Banks/M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Sp77" +Ne 99 "/FPGA_Spartan6/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Ban78" +Ne 34 "/DDR_Banks/M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Sp79" +Ne 98 "/FPGA_Spartan6/M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Ban80" +Ne 82 "/FPGA_Spartan6/M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -2245,14 +2245,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Ban81" +Ne 17 "/DDR_Banks/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Sp82" +Ne 72 "/FPGA_Spartan6/M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2343,7 +2343,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Ban83" +Ne 26 "/DDR_Banks/M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2357,14 +2357,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Sp84" +Ne 100 "/FPGA_Spartan6/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Ban85" +Ne 32 "/DDR_Banks/M1_DQ4" Po 3346 -983 $EndPAD $PAD @@ -2378,49 +2378,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Sp86" +Ne 33 "/DDR_Banks/M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Sp87" +Ne 18 "/DDR_Banks/M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Ban88" +Ne 83 "/FPGA_Spartan6/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Sp89" +Ne 71 "/FPGA_Spartan6/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Sp90" +Ne 77 "/FPGA_Spartan6/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Sp91" +Ne 88 "/FPGA_Spartan6/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M0_A3" +Ne 69 "/FPGA_Spartan6/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2497,7 +2497,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Ban92" +Ne 27 "/DDR_Banks/M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2511,28 +2511,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Sp93" +Ne 95 "/FPGA_Spartan6/M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Sp94" +Ne 24 "/DDR_Banks/M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Sp95" +Ne 108 "/FPGA_Spartan6/M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Sp96" +Ne 109 "/FPGA_Spartan6/M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2553,14 +2553,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Ban97" +Ne 87 "/FPGA_Spartan6/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Ban98" +Ne 86 "/FPGA_Spartan6/M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -2665,14 +2665,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Ban99" +Ne 112 "/FPGA_Spartan6/M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Sp100" +Ne 113 "/FPGA_Spartan6/M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -2693,21 +2693,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Sp101" +Ne 16 "/DDR_Banks/M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Ban102" +Ne 81 "/FPGA_Spartan6/M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Ban103" +Ne 19 "/DDR_Banks/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2826,28 +2826,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Sp104" +Ne 35 "/DDR_Banks/M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Sp105" +Ne 106 "/FPGA_Spartan6/M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Ban106" +Ne 107 "/FPGA_Spartan6/M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Sp107" +Ne 78 "/FPGA_Spartan6/M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -2861,7 +2861,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Ban108" +Ne 11 "/DDR_Banks/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -2952,7 +2952,7 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Sp109" +Ne 133 "/FPGA_Spartan6/USBA_RCV" Po 1771 590 $EndPAD $PAD @@ -2980,7 +2980,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Sp110" +Ne 101 "/FPGA_Spartan6/M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -2994,21 +2994,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Sp111" +Ne 102 "/FPGA_Spartan6/M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Ban112" +Ne 85 "/FPGA_Spartan6/M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Ban113" +Ne 84 "/FPGA_Spartan6/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3120,7 +3120,7 @@ $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Sp114" +Ne 132 "/FPGA_Spartan6/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -3141,21 +3141,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Sp115" +Ne 110 "/FPGA_Spartan6/M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Sp116" +Ne 111 "/FPGA_Spartan6/M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Sp117" +Ne 13 "/DDR_Banks/M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3169,7 +3169,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Sp118" +Ne 12 "/DDR_Banks/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3288,7 +3288,7 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Ban119" +Ne 29 "/DDR_Banks/M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3302,7 +3302,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Ban120" +Ne 30 "/DDR_Banks/M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3316,7 +3316,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Ban121" +Ne 20 "/DDR_Banks/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3337,7 +3337,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Sp122" +Ne 123 "/FPGA_Spartan6/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -3365,7 +3365,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po -983 1771 $EndPAD $PAD @@ -3393,7 +3393,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po 590 1771 $EndPAD $PAD @@ -3449,7 +3449,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Sp123" +Ne 36 "/DDR_Banks/M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3463,7 +3463,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Ban124" +Ne 14 "/DDR_Banks/M0_DQ13" Po -4133 2165 $EndPAD $PAD @@ -3477,7 +3477,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Sp125" +Ne 79 "/FPGA_Spartan6/M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3547,14 +3547,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Sp126" +Ne 127 "/FPGA_Spartan6/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Sp127" +Ne 126 "/FPGA_Spartan6/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -3596,7 +3596,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Sp128" +Ne 103 "/FPGA_Spartan6/M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -3610,21 +3610,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Sp129" +Ne 31 "/DDR_Banks/M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Sp130" +Ne 15 "/DDR_Banks/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Sp131" +Ne 80 "/FPGA_Spartan6/M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3666,7 +3666,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po -1377 2558 $EndPAD $PAD @@ -3694,7 +3694,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po 196 2558 $EndPAD $PAD @@ -3722,7 +3722,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po 1771 2558 $EndPAD $PAD @@ -3757,14 +3757,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Sp132" +Ne 104 "/FPGA_Spartan6/M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Sp133" +Ne 105 "/FPGA_Spartan6/M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -3799,7 +3799,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po -2558 2952 $EndPAD $PAD @@ -4093,7 +4093,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po -3346 3739 $EndPAD $PAD @@ -4121,7 +4121,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po -1771 3739 $EndPAD $PAD @@ -4149,7 +4149,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po -196 3739 $EndPAD $PAD @@ -4177,7 +4177,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po 1377 3739 $EndPAD $PAD @@ -4205,21 +4205,21 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000147" +Ne 151 "N-000149" Po 2952 3739 $EndPAD $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Sp25" +Ne 125 "/FPGA_Spartan6/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Sp26" +Ne 122 "/FPGA_Spartan6/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -4366,7 +4366,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Sp27" +Ne 124 "/FPGA_Spartan6/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -4409,21 +4409,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Etherne29" +Ne 52 "/Ethernet_Phy/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Etherne52" +Ne 48 "/Ethernet_Phy/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Etherne16" +Ne 60 "/FPGA_Spartan6/ETH_RXDV" Po -1613 491 $EndPAD $PAD @@ -4444,63 +4444,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Sp36" +Ne 49 "/Ethernet_Phy/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Etherne15" +Ne 50 "/Ethernet_Phy/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Sp28" +Ne 51 "/Ethernet_Phy/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Sp35" +Ne 59 "/FPGA_Spartan6/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Sp34" +Ne 45 "/Ethernet_Phy/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Etherne11" +Ne 46 "/Ethernet_Phy/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Sp48" +Ne 58 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Etherne4" +Ne 47 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Etherne39" +Ne 41 "/Ethernet_Phy/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -4535,14 +4535,14 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 154 "N-000317" +Ne 154 "N-000322" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 159 "N-000328" +Ne 159 "N-000333" Po 491 -1613 $EndPAD $PAD @@ -4556,35 +4556,35 @@ $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Etherne3" +Ne 40 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 157 "N-000326" +Ne 157 "N-000331" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Etherne14" +Ne 57 "/FPGA_Spartan6/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Etherne12" +Ne 43 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Etherne13" +Ne 44 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4612,21 +4612,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Etherne2" +Ne 39 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 158 "N-000327" +Ne 158 "N-000332" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 155 "N-000318" +Ne 155 "N-000323" Po 1613 -491 $EndPAD $PAD @@ -4654,70 +4654,70 @@ $PAD Sh "13" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Etherne1" +Ne 38 "/Ethernet_Phy/ETH_1.8V" Po -1082 1613 $EndPAD $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Etherne17" +Ne 64 "/FPGA_Spartan6/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Etherne50" +Ne 61 "/FPGA_Spartan6/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Sp51" +Ne 63 "/FPGA_Spartan6/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Etherne37" +Ne 53 "/Ethernet_Phy/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Sp38" +Ne 54 "/Ethernet_Phy/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Sp18" +Ne 62 "/FPGA_Spartan6/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Etherne49" +Ne 55 "/Ethernet_Phy/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Etherne19" +Ne 42 "/Ethernet_Phy/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Sp30" +Ne 56 "/FPGA_Spartan6/ETH_CRS" Po 688 1613 $EndPAD $PAD @@ -4995,28 +4995,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Sp24" +Ne 121 "/FPGA_Spartan6/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Sp24" +Ne 121 "/FPGA_Spartan6/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Sp32" +Ne 120 "/FPGA_Spartan6/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/Non_vol43" +Ne 116 "/FPGA_Spartan6/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -5065,21 +5065,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/Non_vol55" +Ne 115 "/FPGA_Spartan6/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Sp23" +Ne 114 "/FPGA_Spartan6/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/Non_vol42" +Ne 139 "/Non_volatile_memories/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -5156,28 +5156,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/Non_vol54" +Ne 117 "/FPGA_Spartan6/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/Non_vol22" +Ne 134 "/Non_volatile_memories/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Sp41" +Ne 135 "/Non_volatile_memories/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/Non_vol21" +Ne 136 "/Non_volatile_memories/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -5240,28 +5240,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/Non_vol31" +Ne 137 "/Non_volatile_memories/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/Non_vol40" +Ne 138 "/Non_volatile_memories/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/Non_vol53" +Ne 118 "/FPGA_Spartan6/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/Non_vol20" +Ne 119 "/FPGA_Spartan6/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -5314,21 +5314,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 136 "/Non_vol5" +Ne 141 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 140 "/Non_vol6" +Ne 131 "/FPGA_Spartan6/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 107 "/FPGA_Sp7" +Ne 129 "/FPGA_Spartan6/SD_CMD" Po -433 0 $EndPAD $PAD @@ -5342,7 +5342,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 117 "/FPGA_Sp8" +Ne 128 "/FPGA_Spartan6/SD_CLK" Po 433 0 $EndPAD $PAD @@ -5356,14 +5356,14 @@ $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 141 "/Non_vol9" +Ne 140 "/Non_volatile_memories/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 52 "/FPGA_Sp10" +Ne 130 "/FPGA_Spartan6/SD_DAT1" Po 1732 0 $EndPAD $PAD @@ -5411,35 +5411,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 152 "N-000314" +Ne 152 "N-000319" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 152 "N-000314" +Ne 152 "N-000319" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 152 "N-000314" +Ne 152 "N-000319" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 152 "N-000314" +Ne 152 "N-000319" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 154 "N-000317" +Ne 154 "N-000322" Po -1750 -2500 $EndPAD $PAD @@ -5460,14 +5460,14 @@ $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 155 "N-000318" +Ne 155 "N-000323" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 159 "N-000328" +Ne 159 "N-000333" Po -1250 -3500 $EndPAD $PAD @@ -5488,7 +5488,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 158 "N-000327" +Ne 158 "N-000332" Po 1750 -3500 $EndPAD $PAD @@ -5502,7 +5502,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 153 "N-000315" +Ne 153 "N-000320" Po -1150 -5400 $EndPAD $PAD @@ -5516,7 +5516,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 161 "N-000331" +Ne 161 "N-000336" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -5559,7 +5559,7 @@ $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 58 "/FPGA_Sp109" +Ne 133 "/FPGA_Spartan6/USBA_RCV" Po -255 -1112 $EndPAD $PAD @@ -5601,21 +5601,21 @@ $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 61 "/FPGA_Sp114" +Ne 132 "/FPGA_Spartan6/USBA_OE_N" Po 511 1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "N-000337" +Ne 162 "N-000342" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 173 "N-000356" +Ne 173 "N-000361" Po 0 1112 $EndPAD $PAD @@ -5665,7 +5665,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Sp110" +Ne 101 "/FPGA_Spartan6/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -5679,14 +5679,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Sp111" +Ne 102 "/FPGA_Spartan6/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Sp105" +Ne 106 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD @@ -5700,14 +5700,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Ban106" +Ne 107 "/FPGA_Spartan6/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Ban85" +Ne 32 "/DDR_Banks/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -5721,14 +5721,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Sp86" +Ne 33 "/DDR_Banks/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Sp95" +Ne 108 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -5742,7 +5742,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Sp96" +Ne 109 "/FPGA_Spartan6/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5763,7 +5763,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Sp100" +Ne 113 "/FPGA_Spartan6/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -5791,28 +5791,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Ban99" +Ne 112 "/FPGA_Spartan6/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Sp76" +Ne 37 "/DDR_Banks/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Sp79" +Ne 98 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Ban78" +Ne 34 "/DDR_Banks/M1_RAS#" Po 1535 2176 $EndPAD $PAD @@ -5833,49 +5833,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Ban83" +Ne 26 "/DDR_Banks/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Ban92" +Ne 27 "/DDR_Banks/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Sp69" +Ne 23 "/DDR_Banks/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_A0" +Ne 22 "/DDR_Banks/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Sp65" +Ne 89 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Sp60" +Ne 92 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Sp70" +Ne 93 "/FPGA_Spartan6/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -5896,56 +5896,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Sp64" +Ne 94 "/FPGA_Spartan6/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Sp94" +Ne 24 "/DDR_Banks/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Sp93" +Ne 95 "/FPGA_Spartan6/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Sp59" +Ne 96 "/FPGA_Spartan6/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Sp44" +Ne 97 "/FPGA_Spartan6/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Sp45" +Ne 25 "/DDR_Banks/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Sp63" +Ne 90 "/FPGA_Spartan6/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Ban57" +Ne 91 "/FPGA_Spartan6/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -5959,28 +5959,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Sp84" +Ne 100 "/FPGA_Spartan6/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Sp56" +Ne 28 "/DDR_Banks/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Sp77" +Ne 99 "/FPGA_Spartan6/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Sp104" +Ne 35 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD @@ -6008,7 +6008,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Sp123" +Ne 36 "/DDR_Banks/M1_UDQS" Po -255 -2176 $EndPAD $PAD @@ -6029,7 +6029,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Sp115" +Ne 110 "/FPGA_Spartan6/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6043,14 +6043,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Sp116" +Ne 111 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Ban119" +Ne 29 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -6064,14 +6064,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Ban120" +Ne 30 "/DDR_Banks/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Sp128" +Ne 103 "/FPGA_Spartan6/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6085,14 +6085,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Sp129" +Ne 31 "/DDR_Banks/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Sp132" +Ne 104 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -6106,7 +6106,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Sp133" +Ne 105 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -6142,7 +6142,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Ban108" +Ne 11 "/DDR_Banks/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -6156,14 +6156,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Sp107" +Ne 78 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Ban102" +Ne 81 "/FPGA_Spartan6/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -6177,14 +6177,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Sp101" +Ne 16 "/DDR_Banks/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Ban81" +Ne 17 "/DDR_Banks/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -6198,14 +6198,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Ban80" +Ne 82 "/FPGA_Spartan6/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Ban88" +Ne 83 "/FPGA_Spartan6/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -6219,7 +6219,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Sp87" +Ne 18 "/DDR_Banks/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -6240,7 +6240,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Ban97" +Ne 87 "/FPGA_Spartan6/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -6268,28 +6268,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Ban98" +Ne 86 "/FPGA_Spartan6/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Ban61" +Ne 21 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Sp90" +Ne 77 "/FPGA_Spartan6/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Sp91" +Ne 88 "/FPGA_Spartan6/M0_RAS#" Po 1535 2176 $EndPAD $PAD @@ -6310,49 +6310,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Sp67" +Ne 7 "/DDR_Banks/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Ban66" +Ne 76 "/FPGA_Spartan6/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Ban68" +Ne 66 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M0_A0" +Ne 65 "/FPGA_Spartan6/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Sp71" +Ne 5 "/DDR_Banks/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Sp74" +Ne 6 "/DDR_Banks/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M0_A3" +Ne 69 "/FPGA_Spartan6/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -6373,56 +6373,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Sp62" +Ne 70 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Sp89" +Ne 71 "/FPGA_Spartan6/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Sp82" +Ne 72 "/FPGA_Spartan6/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Sp75" +Ne 73 "/FPGA_Spartan6/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M0_A8" +Ne 74 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Sp58" +Ne 75 "/FPGA_Spartan6/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Ban33" +Ne 67 "/FPGA_Spartan6/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Sp46" +Ne 68 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6436,28 +6436,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Sp72" +Ne 10 "/DDR_Banks/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Sp47" +Ne 8 "/DDR_Banks/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Sp73" +Ne 9 "/DDR_Banks/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Ban103" +Ne 19 "/DDR_Banks/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -6485,7 +6485,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Ban121" +Ne 20 "/DDR_Banks/M0_UDQS" Po -255 -2176 $EndPAD $PAD @@ -6506,7 +6506,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Ban113" +Ne 84 "/FPGA_Spartan6/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6520,14 +6520,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Ban112" +Ne 85 "/FPGA_Spartan6/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Sp118" +Ne 12 "/DDR_Banks/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -6541,14 +6541,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Sp117" +Ne 13 "/DDR_Banks/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Sp125" +Ne 79 "/FPGA_Spartan6/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6562,14 +6562,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Ban124" +Ne 14 "/DDR_Banks/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Sp131" +Ne 80 "/FPGA_Spartan6/M0_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -6583,7 +6583,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Sp130" +Ne 15 "/DDR_Banks/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -6611,7 +6611,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 163 "N-000338" +Ne 163 "N-000343" Po -176 0 $EndPAD $PAD @@ -6639,7 +6639,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 152 "N-000314" +Ne 152 "N-000319" Po -176 0 $EndPAD $PAD @@ -6667,14 +6667,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 161 "N-000331" +Ne 161 "N-000336" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 37 "/Etherne13" +Ne 44 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6695,14 +6695,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 153 "N-000315" +Ne 153 "N-000320" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 36 "/Etherne12" +Ne 43 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6730,7 +6730,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 158 "N-000327" +Ne 158 "N-000332" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6758,7 +6758,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 155 "N-000318" +Ne 155 "N-000323" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6786,7 +6786,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 159 "N-000328" +Ne 159 "N-000333" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6814,7 +6814,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 154 "N-000317" +Ne 154 "N-000322" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6835,7 +6835,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 157 "N-000326" +Ne 157 "N-000331" Po -176 0 $EndPAD $PAD @@ -6863,7 +6863,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/Etherne11" +Ne 46 "/Ethernet_Phy/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -6891,7 +6891,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 163 "N-000338" +Ne 163 "N-000343" Po -176 0 $EndPAD $PAD @@ -6919,7 +6919,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 152 "N-000314" +Ne 152 "N-000319" Po -176 0 $EndPAD $PAD @@ -6987,30 +6987,30 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 49213 27756 1800 15 4C5FF890 4C5D8114 ~~ +Po 50591 27559 0 0 4C5FF890 4C5D8114 ~~ Li 0402 Sc 4C5D8114 AR /4C4320F3/4C5D8114 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C9" -T1 0 150 200 200 1800 40 N I 25 N"C" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 0 40 M V 20 N"C9" +T1 0 -150 200 200 0 40 M I 20 N"C" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 1800 +Sh "1" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 48 "/Etherne4" +At SMD N 00440001 +Ne 47 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 1800 +Sh "2" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 160 "N-000329" +At SMD N 00440001 +Ne 160 "N-000334" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7031,7 +7031,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 45 "/Etherne3" +Ne 40 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD @@ -7059,14 +7059,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/Etherne2" +Ne 39 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 160 "N-000329" +Ne 160 "N-000334" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7115,14 +7115,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 156 "N-000321" +Ne 156 "N-000326" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 160 "N-000329" +Ne 160 "N-000334" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7171,7 +7171,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/Etherne1" +Ne 38 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD @@ -7199,7 +7199,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 162 "N-000337" +Ne 162 "N-000342" Po -294 0 $EndPAD $PAD @@ -7227,7 +7227,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 173 "N-000356" +Ne 173 "N-000361" Po -294 0 $EndPAD $PAD @@ -7255,7 +7255,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 172 "N-000355" +Ne 172 "N-000360" Po -294 0 $EndPAD $PAD @@ -7283,7 +7283,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 172 "N-000355" +Ne 172 "N-000360" Po -294 0 $EndPAD $PAD @@ -7311,7 +7311,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 172 "N-000355" +Ne 172 "N-000360" Po -294 0 $EndPAD $PAD @@ -7339,7 +7339,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Etherne3" +Ne 40 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD @@ -7395,7 +7395,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 171 "N-000354" +Ne 171 "N-000359" Po -570 0 $EndPAD $PAD @@ -7428,56 +7428,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 170 "N-000353" +Ne 170 "N-000358" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 162 "N-000337" +Ne 162 "N-000342" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 173 "N-000356" +Ne 173 "N-000361" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 173 "N-000356" +Ne 173 "N-000361" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 163 "N-000338" +Ne 163 "N-000343" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 163 "N-000338" +Ne 163 "N-000343" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 163 "N-000338" +Ne 163 "N-000343" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 163 "N-000338" +Ne 163 "N-000343" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -8058,7 +8058,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "N-000349" +Ne 166 "N-000354" Po -294 0 $EndPAD $PAD @@ -8086,14 +8086,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "N-000354" +Ne 171 "N-000359" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "N-000353" +Ne 170 "N-000358" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8114,7 +8114,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "N-000339" +Ne 164 "N-000346" Po -294 0 $EndPAD $PAD @@ -8170,7 +8170,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "N-000352" +Ne 169 "N-000357" Po -176 0 $EndPAD $PAD @@ -8198,7 +8198,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "N-000352" +Ne 169 "N-000357" Po -176 0 $EndPAD $PAD @@ -8226,7 +8226,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "N-000351" +Ne 168 "N-000356" Po -176 0 $EndPAD $PAD @@ -8254,7 +8254,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "N-000350" +Ne 167 "N-000355" Po -294 0 $EndPAD $PAD @@ -8282,7 +8282,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "N-000345" +Ne 165 "N-000350" Po -294 0 $EndPAD $PAD @@ -8310,7 +8310,7 @@ $PAD Sh "1" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "N-000351" +Ne 168 "N-000356" Po -373 0 $EndPAD $PAD @@ -8338,7 +8338,7 @@ $PAD Sh "1" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "N-000351" +Ne 168 "N-000356" Po -373 0 $EndPAD $PAD @@ -8366,7 +8366,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 164 "N-000339" +Ne 164 "N-000346" Po -570 0 $EndPAD $PAD @@ -8465,14 +8465,14 @@ $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 167 "N-000350" +Ne 167 "N-000355" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 165 "N-000345" +Ne 165 "N-000350" Po 0 1112 $EndPAD $PAD @@ -9423,42 +9423,42 @@ $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Sp122" +Ne 123 "/FPGA_Spartan6/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Sp126" +Ne 127 "/FPGA_Spartan6/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Sp26" +Ne 122 "/FPGA_Spartan6/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Sp27" +Ne 124 "/FPGA_Spartan6/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Sp25" +Ne 125 "/FPGA_Spartan6/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Sp127" +Ne 126 "/FPGA_Spartan6/PROG_MISO2" Po 250 1050 $EndPAD $PAD @@ -9639,7 +9639,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Etherne3" +Ne 40 "/Ethernet_Phy/ETH_A3.3V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9660,42 +9660,42 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 156 "N-000321" +Ne 156 "N-000326" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/Etherne2" +Ne 39 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 49213 27362 0 15 4C5FF890 4C5D810A ~~ +Po 50591 27165 1800 0 4C5FF890 4C5D810A ~~ Li 0402 Sc 4C5D810A AR /4C4320F3/4C5D810A Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"L3" -T1 0 150 200 200 0 40 N I 25 N"INDUCTOR" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"L3" +T1 0 -150 200 200 1800 40 M I 20 N"INDUCTOR" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 43 "/Etherne2" +At SMD N 00440001 +Ne 39 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 48 "/Etherne4" +At SMD N 00440001 +Ne 47 "/Ethernet_Phy/ETH_PLL1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9745,7 +9745,7 @@ ZLayer 15 ZAux 4 N ZClearance 200 T ZMinThickness 100 -ZOptions 0 16 S 200 200 +ZOptions 0 16 F 200 200 ZCorner 67126 44685 0 ZCorner 67126 14567 0 ZCorner 45079 14567 0 diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index f307de1..3ad4ce4 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,1376 +1,1226 @@ -# EESchema Netlist Version 1.1 created Sat 14 Aug 2010 07:08:24 AM COT +# EESchema Netlist Version 1.1 created Sat 14 Aug 2010 08:20:44 AM COT ( - ( /4C4320F3/4C5D7F9F 0603 C1 1uF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D80ED 0402 C2 C - ( 1 /Etherne1 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA1 0402 C3 100nF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D80F0 0402 C4 C - ( 1 N-000321 ) - ( 2 N-000329 ) - ) - ( /4C4320F3/4C5D7FA3 0402 C5 100nF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D8104 0402 C6 C - ( 1 /Etherne2 ) - ( 2 N-000329 ) - ) - ( /4C4320F3/4C5D7FA5 0603 C7 1uF - ( 1 /Etherne3 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA7 0402 C8 100nF - ( 1 /Etherne3 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D8114 0402 C9 C - ( 1 /Etherne4 ) - ( 2 N-000329 ) - ) - ( /4C4320F3/4C5D7E41 0402 C10 100nF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E43 0402 C11 100nF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7DCB 0402 C12 47nF - ( 1 N-000314 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2033 0603 C13 1uF - ( 1 N-000355 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2037 0603 C14 1uF - ( 1 N-000355 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2039 0603 C15 470nF - ( 1 N-000355 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2D1E 0402 C16 4.7nF - ( 1 N-000338 ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CC73 0402 C17 100nF - ( 1 +2.5V ) - ( 2 N-000052 ) - ) - ( /4C421DD3/4C61CC96 0402 C18 100nF - ( 1 N-000052 ) - ( 2 N-000054 ) - ) - ( /4C421DD3/4C61CCE3 0402 C19 100nF - ( 1 +2.5V ) - ( 2 N-000051 ) - ) - ( /4C421DD3/4C61CCE2 0402 C20 100nF - ( 1 N-000051 ) - ( 2 N-000050 ) - ) - ( /4C421DD3/4C61CF2F 0603 C21 1uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CEB9 0402 C22 100nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CEF7 0402 C23 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF17 0402 C24 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF16 0402 C25 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF27 0402 C26 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA0 0603 C27 1uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA5 0402 C28 100nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA4 0402 C29 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA2 0402 C30 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA3 0402 C31 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA1 0402 C32 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61D151 1206 C33 10uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61D1D4 1206 C34 10uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552BE 0805 C35 1uF - ( 1 N-000351 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552BD 0805 C36 1uF - ( 1 N-000351 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552BC 0402 C37 470nF - ( 1 N-000351 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552B7 0402 C38 4.7nF - ( 1 N-000352 ) - ( 2 GND ) - ) - ( /4C431A63/4C656A80 1210 C39 100uF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656BF8 1210 C40 100uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CB7 1210 C41 100uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656ABD 0805 C42 4.7uF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656BF9 0805 C43 4.7uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CB9 0805 C44 4.7uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656AC0 0402 C45 470nF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C16 0805 C46 4.7uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CBA 0402 C47 470nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656AC2 0402 C48 470nF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C24 0402 C49 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CBB 0402 C50 470nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C27 0402 C51 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656BFA 0402 C52 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C49 0402 C53 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D97 1210 C54 100uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D43 1210 C55 100uF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656CF9 1210 C56 100uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D98 0805 C57 4.7uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D44 0805 C58 4.7uF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656CFA 0805 C59 4.7uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D99 0402 C60 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D45 0402 C61 470nF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656CFB 0402 C62 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D9A 0402 C63 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D46 0402 C64 470nF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656CFC 0402 C65 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D9D 0402 C66 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D49 0402 C67 470nF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656D08 0402 C68 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D53 0402 C69 470nF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C421DD3/4C65D2A9 0402 C70 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C65D28E 0402 C71 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C4227FE/4C65D661 0402 C72 100nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4227FE/4C65D67C 0402 C73 100nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4227FE/4C65D681 0603 C74 1uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2B55 1210 F1 MICROSMD075F - ( 1 N-000354 ) - ( 2 +5V ) - ) - ( /4C5F1EDC/4C6552BA 1210 F2 MICROSMD075F - ( 1 N-000339 ) - ( 2 +5V ) - ) - ( /4C4227FE/4B76F5E2 MICROSD-500901 J1 MICROSD - ( 1 /Non_vol5 ) - ( 2 /Non_vol6 ) - ( 3 /FPGA_Sp7 ) - ( 4 ? ) - ( 5 /FPGA_Sp8 ) - ( 6 GND ) - ( 7 /Non_vol9 ) - ( 8 /FPGA_Sp10 ) + ( /4C4227FE/4C65D681 0603 C74 1uF {Lib=CAP} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65D67C 0402 C73 100nF {Lib=CAP} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65D661 0402 C72 100nF {Lib=CAP} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB} + ( 1 /FPGA_Spartan6/PROG_CSO ) + ( 2 /FPGA_Spartan6/PROG_MISO1 ) + ( 3 /FPGA_Spartan6/PROG_MISO2 ) + ( 4 GND ) + ( 5 /FPGA_Spartan6/PROG_MISO0 ) + ( 6 /FPGA_Spartan6/PROG_CCLK ) + ( 7 /FPGA_Spartan6/PROG_MISO3 ) + ( 8 VCCO2 ) + ) + ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} ( CASE GND ) - ( CD ? ) - ( COM GND ) + ( COM GND ) + ( CD ? ) + ( 1 /Non_volatile_memories/SD_DAT2 ) + ( 2 /FPGA_Spartan6/SD_DAT3 ) + ( 3 /FPGA_Spartan6/SD_CMD ) + ( 4 ? ) + ( 5 /FPGA_Spartan6/SD_CLK ) + ( 6 GND ) + ( 7 /Non_volatile_memories/SD_DAT0 ) + ( 8 /FPGA_Spartan6/SD_DAT1 ) ) - ( /4C4320F3/4C5D6F5A SD-48025 J4 RJ45-48025 - ( 1 N-000317 ) - ( 2 N-000328 ) - ( 3 3.3V ) - ( 4 GND ) - ( 5 GND ) - ( 6 3.3V ) - ( 7 N-000318 ) - ( 8 N-000327 ) - ( 9 3.3V ) - ( 10 N-000315 ) - ( 11 3.3V ) - ( 12 N-000331 ) - ( 13 N-000314 ) - ( 14 N-000314 ) + ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 /FPGA_Spartan6/NF_RNB ) + ( 7 /FPGA_Spartan6/NF_RNB ) + ( 8 /FPGA_Spartan6/NF_RE_N ) + ( 9 /FPGA_Spartan6/NF_CS1_N ) + ( 10 ? ) + ( 11 ? ) + ( 12 3.3V ) + ( 13 GND ) + ( 14 ? ) + ( 15 ? ) + ( 16 /FPGA_Spartan6/NF_CLE ) + ( 17 /FPGA_Spartan6/NF_ALE ) + ( 18 /Non_volatile_memories/NF_WE_N ) + ( 19 3.3V ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 ? ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 ? ) + ( 29 /FPGA_Spartan6/NF_D0 ) + ( 30 /Non_volatile_memories/NF_D1 ) + ( 31 /Non_volatile_memories/NF_D2 ) + ( 32 /Non_volatile_memories/NF_D3 ) + ( 33 ? ) + ( 34 ? ) + ( 35 ? ) + ( 36 GND ) + ( 37 +3.3V ) + ( 38 ? ) + ( 39 ? ) + ( 40 ? ) + ( 41 /Non_volatile_memories/NF_D4 ) + ( 42 /Non_volatile_memories/NF_D5 ) + ( 43 /FPGA_Spartan6/NF_D6 ) + ( 44 /FPGA_Spartan6/NF_D7 ) + ( 45 ? ) + ( 46 ? ) + ( 47 ? ) + ( 48 ? ) ) - ( /4C5F1EDC/4C5F23DD USB-48204 J5 USB-48204-0001 - ( 1 N-000353 ) - ( 2 N-000337 ) - ( 3 N-000356 ) - ( 4 N-000349 ) - ( S1 N-000338 ) - ( S2 N-000338 ) - ( S3 N-000338 ) - ( S4 N-000338 ) + ( /4C5F1EDC/4C6552BF $noname U7 MIC2550AYTS {Lib=MIC2550AYTS} + ( 1 +2.5V ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 7 GND ) + ( 8 GND ) + ( 9 ? ) + ( 10 N-000355 ) + ( 11 N-000350 ) + ( 12 3.3V ) + ( 14 3.3V ) ) - ( /4C4320F3/4C5D80F3 0402 L1 INDUCTOR - ( 1 N-000321 ) - ( 2 /Etherne2 ) + ( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C} + ( 1 N-000356 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7FB7 0402 L2 FB - ( 1 3.3V ) - ( 2 /Etherne3 ) + ( /4C5F1EDC/4C6552BD $noname C36 1uF {Lib=C} + ( 1 N-000356 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D810A 0402 L3 INDUCTOR - ( 1 /Etherne2 ) - ( 2 /Etherne4 ) + ( /4C5F1EDC/4C6552BC $noname C37 470nF {Lib=C} + ( 1 N-000356 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C63F252 0603 L4 FB - ( 1 N-000354 ) - ( 2 N-000353 ) + ( /4C5F1EDC/4C6552BA $noname F2 MICROSMD075F {Lib=MICROSMD075F} + ( 1 N-000346 ) + ( 2 +5V ) ) - ( /4C5F1EDC/4C63F248 0603 L5 FB - ( 1 N-000349 ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000355 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B0 0603 L6 FB - ( 1 N-000339 ) - ( 2 ? ) + ( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000350 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B1 0603 L7 FB - ( 1 ? ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C} + ( 1 N-000357 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7F39 0402 R1 4.7K - ( 1 /Etherne11 ) - ( 2 3.3V ) + ( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R} + ( 1 N-000357 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7ECF 0402 R2 6.65K - ( 1 N-000326 ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} + ( 1 ? ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7AFE 0402 R3 49.9 - ( 1 3.3V ) - ( 2 N-000317 ) + ( /4C5F1EDC/4C6552B0 0603 L6 FB {Lib=INDUCTOR} + ( 1 N-000346 ) + ( 2 ? ) ) - ( /4C4320F3/4C5D7AFC 0402 R4 49.9 - ( 1 3.3V ) - ( 2 N-000328 ) + ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} + ( 1 N-000359 ) + ( 2 N-000358 ) ) - ( /4C4320F3/4C5D7AF7 0402 R5 49.9 - ( 1 3.3V ) - ( 2 N-000318 ) + ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} + ( 1 N-000354 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7AF9 0402 R6 49.9 - ( 1 3.3V ) - ( 2 N-000327 ) + ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} + ( 1 N-000343 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D719D 0402 R7 220 - ( 1 N-000315 ) - ( 2 /Etherne12 ) + ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} + ( 1 N-000343 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D71DB 0402 R8 220 - ( 1 N-000331 ) - ( 2 /Etherne13 ) + ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000361 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7DC4 0402 R9 1M - ( 1 N-000314 ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000342 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2D27 0402 R10 1M - ( 1 N-000338 ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} + ( 1 N-000359 ) + ( 2 +5V ) ) - ( /4C421DD3/4C61CD4A 0402 R11 1K_1% - ( 1 +2.5V ) - ( 2 N-000052 ) + ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} + ( S1 N-000343 ) + ( S2 N-000343 ) + ( S3 N-000343 ) + ( S4 N-000343 ) + ( 1 N-000358 ) + ( 2 N-000342 ) + ( 3 N-000361 ) + ( 4 N-000354 ) ) - ( /4C421DD3/4C61CDB5 0402 R12 1K_1% - ( 1 N-000052 ) - ( 2 N-000054 ) + ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} + ( 1 N-000360 ) + ( 2 GND ) ) - ( /4C421DD3/4C61CE31 0402 R13 1K_1% - ( 1 +2.5V ) - ( 2 N-000051 ) + ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} + ( 1 N-000360 ) + ( 2 GND ) ) - ( /4C421DD3/4C61CE30 0402 R14 1K_1% - ( 1 N-000051 ) - ( 2 N-000050 ) + ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} + ( 1 N-000360 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B6 0402 R15 1M - ( 1 N-000352 ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} + ( 1 +2.5V ) + ( 2 /USB/USBA_SPD ) + ( 3 /FPGA_Spartan6/USBA_RCV ) + ( 4 /USB/USBA_VP ) + ( 5 /USB/USBA_VM ) + ( 7 GND ) + ( 8 GND ) + ( 9 /FPGA_Spartan6/USBA_OE_N ) + ( 10 N-000342 ) + ( 11 N-000361 ) + ( 12 3.3V ) + ( 14 3.3V ) ) - ( /4C431A63/4C431E53 FGG484bga-p10 U1 XC6SLX45FGG484 - ( A1 GND ) - ( A2 ? ) - ( A4 /Etherne14 ) - ( A5 /Etherne11 ) - ( A6 /Etherne15 ) - ( A7 /Etherne16 ) - ( A8 /Etherne17 ) - ( A9 /FPGA_Sp18 ) - ( A10 /Etherne19 ) - ( A11 /Non_vol20 ) - ( A12 /Non_vol21 ) - ( A13 /Non_vol22 ) - ( A14 ? ) - ( A15 /FPGA_Sp23 ) - ( A16 /FPGA_Sp24 ) - ( A17 /Non_vol5 ) - ( A18 /Non_vol9 ) - ( A19 ? ) - ( A20 ? ) - ( A21 ? ) - ( A22 GND ) - ( AA1 ? ) - ( AA2 ? ) - ( AA3 N-000147 ) - ( AA4 ? ) - ( AA5 GND ) - ( AA6 ? ) - ( AA7 N-000147 ) - ( AA8 ? ) - ( AA9 GND ) - ( AA10 ? ) - ( AA11 N-000147 ) - ( AA12 ? ) - ( AA13 GND ) - ( AA14 ? ) - ( AA15 N-000147 ) - ( AA16 ? ) - ( AA17 GND ) - ( AA18 ? ) - ( AA19 N-000147 ) - ( AA20 /FPGA_Sp25 ) - ( AA21 /FPGA_Sp26 ) - ( AA22 ? ) - ( AB1 GND ) - ( AB2 ? ) - ( AB3 ? ) - ( AB4 ? ) - ( AB5 ? ) - ( AB6 ? ) - ( AB7 ? ) - ( AB8 ? ) - ( AB9 ? ) - ( AB10 ? ) - ( AB11 ? ) - ( AB12 ? ) - ( AB13 ? ) - ( AB14 ? ) - ( AB15 ? ) - ( AB16 ? ) - ( AB17 ? ) - ( AB18 ? ) + ( /4C431A63/4C656D9D $noname C66 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D9A $noname C63 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D99 $noname C60 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D98 $noname C57 4.7uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D97 $noname C54 100uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D53 $noname C69 470nF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D49 $noname C67 470nF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D46 $noname C64 470nF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D45 $noname C61 470nF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D44 $noname C58 4.7uF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D43 $noname C55 100uF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D08 $noname C68 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CFC $noname C65 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CFB $noname C62 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CFA $noname C59 4.7uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CF9 $noname C56 100uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CBB $noname C50 470nF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CBA $noname C47 470nF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CB9 $noname C44 4.7uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CB7 $noname C41 100uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C49 $noname C53 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C27 $noname C51 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C24 $noname C49 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C16 $noname C46 4.7uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656BFA $noname C52 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656BF9 $noname C43 4.7uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656BF8 $noname C40 100uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656AC2 $noname C48 470nF {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C656AC0 $noname C45 470nF {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C656ABD $noname C42 4.7uF {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C656A80 $noname C39 100uF {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} + ( H8 ? ) + ( P7 ? ) + ( N7 ? ) + ( M7 ? ) + ( L7 +2.5V ) + ( K7 ? ) + ( J7 ? ) + ( G7 ? ) + ( F7 ? ) + ( P6 ? ) + ( N6 ? ) + ( M6 ? ) + ( L6 ? ) + ( K6 /FPGA_Spartan6/M0_A3 ) + ( J6 ? ) + ( H6 /FPGA_Spartan6/M0_A7 ) + ( G6 ? ) + ( F6 +2.5V ) + ( E6 ? ) + ( U5 +2.5V ) + ( P5 ? ) + ( N5 +2.5V ) + ( M5 ? ) + ( K5 /FPGA_Spartan6/M0_RAS# ) + ( J5 +2.5V ) + ( H5 /DDR_Banks/M0_A2 ) + ( F5 ? ) + ( E5 ? ) + ( D5 ? ) + ( U4 ? ) + ( K21 /FPGA_Spartan6/M1_DQ6 ) + ( H21 /DDR_Banks/M1_RAS# ) + ( G21 +2.5V ) + ( F21 /DDR_Banks/M1_A0 ) + ( D21 /DDR_Banks/M1_CKE ) + ( C21 +2.5V ) + ( B21 ? ) + ( A21 ? ) + ( W20 ? ) + ( V20 ? ) + ( U20 /FPGA_Spartan6/M1_DQ12 ) + ( T20 ? ) + ( R20 /DDR_Banks/M1_DQ10 ) + ( P20 ? ) + ( N20 /FPGA_Spartan6/M1_DQ0 ) + ( M20 /DDR_Banks/M1_UDM ) + ( L20 /FPGA_Spartan6/M1_LDQS ) + ( K20 /DDR_Banks/M1_A5 ) + ( J20 /DDR_Banks/M1_DQ4 ) + ( H20 /FPGA_Spartan6/M1_CLK ) + ( G20 /FPGA_Spartan6/M1_A3 ) + ( F20 /FPGA_Spartan6/M1_A4 ) + ( E20 /FPGA_Spartan6/M1_A7 ) + ( D20 ? ) + ( C20 /FPGA_Spartan6/M1_A8 ) + ( B20 ? ) + ( A20 ? ) + ( P8 ? ) + ( M8 ? ) + ( K8 ? ) + ( Y2 ? ) + ( W2 +2.5V ) + ( V2 /FPGA_Spartan6/M0_DQ14 ) + ( T2 /DDR_Banks/M0_UDQS ) + ( R2 +2.5V ) + ( P2 /FPGA_Spartan6/M0_DQ8 ) + ( M2 /FPGA_Spartan6/M0_DQ2 ) + ( L2 +2.5V ) + ( K2 /FPGA_Spartan6/M0_DQ6 ) + ( H2 /FPGA_Spartan6/M0_A0 ) + ( G2 +2.5V ) + ( F2 /DDR_Banks/M0_WE# ) + ( D2 /DDR_Banks/M0_CKE ) + ( C2 +2.5V ) + ( B2 ? ) + ( A2 ? ) + ( Y1 ? ) + ( W1 ? ) + ( V1 /DDR_Banks/M0_DQ15 ) + ( U1 /DDR_Banks/M0_DQ13 ) + ( T1 ? ) + ( R1 /DDR_Banks/M0_DQ11 ) + ( P1 /FPGA_Spartan6/M0_DQ9 ) + ( N1 /FPGA_Spartan6/M0_DQ1 ) + ( M1 /DDR_Banks/M0_DQ3 ) + ( L1 ? ) + ( K1 /DDR_Banks/M0_DQ7 ) + ( J1 /FPGA_Spartan6/M0_DQ5 ) + ( H1 /DDR_Banks/M0_A1 ) + ( G1 /FPGA_Spartan6/M0_BA1 ) + ( T4 ? ) + ( R4 ? ) + ( P4 ? ) + ( N4 ? ) + ( M4 ? ) + ( L4 /FPGA_Spartan6/M0_LDM ) + ( K4 /FPGA_Spartan6/M0_CAS# ) + ( J4 /FPGA_Spartan6/M0_A6 ) + ( H4 /DDR_Banks/M0_CLK ) + ( G4 /FPGA_Spartan6/M0_A10 ) + ( F4 +2.5V ) + ( E4 ? ) + ( C4 ? ) + ( W3 ? ) + ( V3 ? ) + ( U3 /FPGA_Spartan6/M0_DQ12 ) + ( T3 ? ) + ( R3 /DDR_Banks/M0_DQ10 ) + ( P3 ? ) + ( N3 /DDR_Banks/M0_DQ0 ) + ( M3 /DDR_Banks/M0_UDM ) + ( L3 /FPGA_Spartan6/M0_LDQS ) + ( K3 /FPGA_Spartan6/M0_A5 ) + ( J3 /DDR_Banks/M0_DQ4 ) + ( H3 /DDR_Banks/M0_CLK# ) + ( G3 /DDR_Banks/M0_BA0 ) + ( F3 /FPGA_Spartan6/M0_A4 ) + ( E3 /FPGA_Spartan6/M0_A8 ) + ( D3 ? ) + ( C3 ? ) + ( B3 ? ) + ( G10 +3.3V ) + ( D10 /Ethernet_Phy/ETH_MDC ) + ( C10 /FPGA_Spartan6/ETH_CRS ) + ( B10 /Ethernet_Phy/ETH_COL ) + ( A10 /FPGA_Spartan6/ETH_INT ) + ( E9 +3.3V ) + ( D9 /Ethernet_Phy/ETH_TXD0 ) + ( C9 /FPGA_Spartan6/ETH_TXD2 ) + ( A9 /Ethernet_Phy/ETH_TXD3 ) + ( D8 /Ethernet_Phy/ETH_RXC ) + ( C8 /Ethernet_Phy/ETH_TXD1 ) + ( B8 /FPGA_Spartan6/ETH_TXER ) + ( A8 /FPGA_Spartan6/ETH_TXEN ) + ( D7 /FPGA_Spartan6/ETH_TXC ) + ( C7 /FPGA_Spartan6/ETH_RXDV ) + ( B7 +3.3V ) + ( A7 /Ethernet_Phy/ETH_RXER ) + ( D6 /FPGA_Spartan6/ETH_RXD3 ) + ( C6 /Ethernet_Phy/ETH_RXD2 ) + ( B6 /Ethernet_Phy/ETH_RXD1 ) + ( A6 /Ethernet_Phy/ETH_RXD0 ) + ( C5 /Ethernet_Phy/ETH_MDIO ) + ( A5 /FPGA_Spartan6/ETH_RESET_N ) + ( B4 +3.3V ) + ( A4 /Ethernet_Phy/ETH_CLK ) + ( A3 ? ) + ( U19 ? ) + ( T19 ? ) + ( R19 /USB/USBA_SPD ) + ( P19 ? ) + ( B19 +3.3V ) + ( B18 /FPGA_Spartan6/SD_DAT1 ) + ( A18 /Non_volatile_memories/SD_DAT0 ) + ( E17 +3.3V ) + ( D17 /FPGA_Spartan6/SD_CMD ) + ( C17 /FPGA_Spartan6/SD_DAT3 ) + ( A17 /Non_volatile_memories/SD_DAT2 ) + ( E16 /FPGA_Spartan6/SD_CLK ) + ( C16 /FPGA_Spartan6/NF_CS1_N ) + ( B16 /FPGA_Spartan6/NF_RE_N ) + ( A16 /FPGA_Spartan6/NF_RNB ) + ( D15 /FPGA_Spartan6/NF_CLE ) + ( C15 /Non_volatile_memories/NF_WE_N ) + ( B15 +3.3V ) + ( A15 /FPGA_Spartan6/NF_ALE ) + ( G14 +3.3V ) + ( D14 /FPGA_Spartan6/NF_D0 ) + ( C14 ? ) + ( B14 ? ) + ( A14 ? ) + ( E13 +3.3V ) + ( C13 /Non_volatile_memories/NF_D2 ) + ( A13 /Non_volatile_memories/NF_D1 ) + ( C12 /Non_volatile_memories/NF_D5 ) + ( B12 /Non_volatile_memories/NF_D4 ) + ( A12 /Non_volatile_memories/NF_D3 ) + ( D11 /FPGA_Spartan6/NF_D6 ) + ( C11 ? ) + ( B11 +3.3V ) + ( A11 /FPGA_Spartan6/NF_D7 ) + ( J16 ? ) + ( H16 ? ) + ( G16 ? ) + ( F16 ? ) + ( L15 ? ) + ( W22 ? ) + ( V22 /FPGA_Spartan6/M1_DQ15 ) + ( U22 /DDR_Banks/M1_DQ13 ) + ( T22 ? ) + ( R22 /DDR_Banks/M1_DQ11 ) + ( P22 /FPGA_Spartan6/M1_DQ9 ) + ( N22 /FPGA_Spartan6/M1_DQ1 ) + ( M22 /FPGA_Spartan6/M1_DQ3 ) + ( L22 ? ) + ( K22 /FPGA_Spartan6/M1_DQ7 ) + ( J22 /DDR_Banks/M1_DQ5 ) + ( H22 /FPGA_Spartan6/M1_CAS# ) + ( G22 ? ) + ( F22 /FPGA_Spartan6/M1_A1 ) + ( E22 /FPGA_Spartan6/M1_A2 ) + ( D22 /FPGA_Spartan6/M1_A12 ) + ( C22 /DDR_Banks/M1_A9 ) + ( B22 ? ) + ( W21 +2.5V ) + ( V21 /FPGA_Spartan6/M1_DQ14 ) + ( T21 /DDR_Banks/M1_UDQS ) + ( R21 +2.5V ) + ( P21 /FPGA_Spartan6/M1_DQ8 ) + ( M21 /FPGA_Spartan6/M1_DQ2 ) + ( L21 +2.5V ) + ( N19 ? ) + ( M19 ? ) + ( L19 /FPGA_Spartan6/M1_LDM ) + ( K19 /FPGA_Spartan6/M1_A6 ) + ( J19 /FPGA_Spartan6/M1_CLK# ) + ( H19 /DDR_Banks/M1_WE# ) + ( G19 /DDR_Banks/M1_A10 ) + ( F19 /FPGA_Spartan6/M1_A11 ) + ( E19 +2.5V ) + ( D19 ? ) + ( C19 ? ) + ( U18 +2.5V ) + ( P18 /FPGA_Spartan6/USBA_OE_N ) + ( N18 +2.5V ) + ( M18 /USB/USBA_VM ) + ( K18 ? ) + ( J18 +2.5V ) + ( H18 ? ) + ( F18 ? ) + ( P17 /USB/USBA_VP ) + ( M17 ? ) + ( L17 ? ) + ( K17 /DDR_Banks/M1_BA1 ) + ( J17 /DDR_Banks/M1_BA0 ) + ( H17 ? ) + ( G17 ? ) + ( F17 ? ) + ( N16 /FPGA_Spartan6/USBA_RCV ) + ( M16 ? ) + ( L16 +2.5V ) + ( K16 ? ) + ( J14 +1.2V ) + ( H14 ? ) + ( F14 ? ) + ( E14 ? ) + ( P13 +1.2V ) + ( N13 GND ) + ( M13 +1.2V ) + ( L13 GND ) + ( K13 +1.2V ) + ( J13 GND ) + ( H13 ? ) + ( G13 ? ) + ( F13 ? ) + ( D13 ? ) + ( B13 GND ) + ( Y22 ? ) + ( A22 GND ) + ( R12 +2.5V ) + ( P12 GND ) + ( N12 +1.2V ) + ( M12 GND ) + ( L12 +1.2V ) + ( K12 GND ) + ( J12 +1.2V ) + ( H12 ? ) + ( G12 +2.5V ) + ( F12 ? ) + ( E12 ? ) + ( D12 ? ) + ( AB1 GND ) + ( A19 ? ) + ( R18 GND ) + ( L18 GND ) + ( G18 GND ) + ( E18 ? ) + ( D18 GND ) + ( C18 ? ) + ( R17 ? ) + ( N17 GND ) + ( B17 GND ) + ( W16 GND ) + ( P16 ? ) + ( D16 +2.5V ) + ( AA5 GND ) + ( P15 ? ) + ( N15 ? ) + ( M15 +2.5V ) + ( K15 +2.5V ) + ( J15 GND ) + ( H15 +2.5V ) + ( G15 ? ) + ( F15 ? ) + ( E15 GND ) + ( V14 GND ) + ( R14 +1.2V ) + ( P14 GND ) + ( N14 +1.2V ) + ( M14 GND ) + ( L14 +1.2V ) + ( K14 GND ) + ( L9 GND ) + ( K9 +1.2V ) + ( J9 GND ) + ( H9 +2.5V ) + ( G9 ? ) + ( F9 ? ) + ( B9 GND ) + ( N8 +2.5V ) + ( L8 +2.5V ) + ( J8 +1.2V ) + ( G8 ? ) + ( F8 ? ) + ( E8 ? ) + ( W7 GND ) + ( U7 GND ) + ( H7 GND ) + ( E7 GND ) + ( V6 +2.5V ) + ( R6 +2.5V ) + ( R5 GND ) + ( L5 GND ) + ( G5 GND ) + ( B5 GND ) + ( V4 GND ) + ( D4 GND ) + ( U2 GND ) + ( N2 GND ) + ( J2 GND ) + ( E2 GND ) + ( A1 GND ) + ( AA1 ? ) + ( U21 GND ) + ( N21 GND ) + ( J21 GND ) + ( E21 GND ) + ( U11 +2.5V ) + ( P11 +1.2V ) + ( N11 GND ) + ( M11 +1.2V ) + ( L11 GND ) + ( K11 +1.2V ) + ( J11 GND ) + ( H11 ? ) + ( G11 ? ) + ( F11 +2.5V ) + ( E11 GND ) + ( Y20 ? ) + ( V10 GND ) + ( R10 +2.5V ) + ( P10 GND ) + ( N10 +1.2V ) + ( M10 GND ) + ( L10 +1.2V ) + ( K10 GND ) + ( J10 +1.2V ) + ( H10 ? ) + ( F10 ? ) + ( E10 ? ) + ( P9 +1.2V ) + ( N9 GND ) + ( M9 +1.2V ) + ( V19 ? ) + ( AB8 ? ) + ( AA8 ? ) + ( Y18 ? ) + ( W18 ? ) + ( V18 ? ) + ( T18 ? ) + ( AB7 ? ) + ( AA7 N-000149 ) + ( Y17 ? ) + ( W17 ? ) + ( V17 ? ) + ( U17 ? ) + ( T17 ? ) + ( AB6 ? ) + ( AA6 ? ) + ( Y16 ? ) + ( V16 N-000149 ) + ( U16 ? ) + ( T16 ? ) + ( R16 ? ) + ( AB5 ? ) + ( Y15 ? ) + ( W15 ? ) + ( V15 ? ) + ( U15 ? ) + ( T15 ? ) + ( R15 ? ) + ( AB4 ? ) + ( AA4 ? ) + ( F1 ? ) + ( E1 /FPGA_Spartan6/M0_A9 ) + ( D1 /FPGA_Spartan6/M0_A12 ) + ( C1 /FPGA_Spartan6/M0_A11 ) + ( B1 ? ) ( AB19 ? ) - ( AB20 /FPGA_Sp27 ) + ( AA19 N-000149 ) + ( AB18 ? ) + ( AA18 ? ) + ( AB17 ? ) + ( AB16 ? ) + ( AA16 ? ) + ( AB15 ? ) + ( AA15 N-000149 ) + ( AB14 ? ) + ( AA14 ? ) + ( AB13 ? ) + ( AA22 ? ) + ( AB12 ? ) + ( AA12 ? ) ( AB21 ? ) + ( AA21 /FPGA_Spartan6/PROG_CCLK ) + ( AB11 ? ) + ( AA11 N-000149 ) + ( AB20 /FPGA_Spartan6/PROG_MISO0 ) + ( AA20 /FPGA_Spartan6/PROG_MISO1 ) + ( AB10 ? ) + ( AA10 ? ) + ( AB9 ? ) + ( Y19 ? ) + ( V9 ? ) + ( U9 ? ) + ( T9 N-000149 ) + ( R9 ? ) + ( Y8 ? ) + ( W8 ? ) + ( V8 N-000149 ) + ( U8 ? ) + ( T8 ? ) + ( R8 ? ) + ( Y7 ? ) + ( V7 ? ) + ( T7 ? ) + ( R7 ? ) + ( Y6 ? ) + ( W6 ? ) + ( U6 ? ) + ( T6 ? ) + ( Y5 ? ) + ( W5 N-000149 ) + ( V5 ? ) + ( T5 /FPGA_Spartan6/PROG_CSO ) + ( Y4 ? ) + ( W4 ? ) + ( Y3 ? ) + ( AA17 GND ) + ( AA13 GND ) ( AB22 GND ) - ( B1 ? ) - ( B2 ? ) - ( B3 ? ) - ( B4 +3.3V ) - ( B5 GND ) - ( B6 /FPGA_Sp28 ) - ( B7 +3.3V ) - ( B8 /Etherne29 ) - ( B9 GND ) - ( B10 /FPGA_Sp30 ) - ( B11 +3.3V ) - ( B12 /Non_vol31 ) - ( B13 GND ) - ( B14 ? ) - ( B15 +3.3V ) - ( B16 /FPGA_Sp32 ) - ( B17 GND ) - ( B18 /FPGA_Sp10 ) - ( B19 +3.3V ) - ( B20 ? ) - ( B21 ? ) - ( B22 ? ) - ( C1 /DDR_Ban33 ) - ( C2 +2.5V ) - ( C3 ? ) - ( C4 ? ) - ( C5 /FPGA_Sp34 ) - ( C6 /FPGA_Sp35 ) - ( C7 /FPGA_Sp36 ) - ( C8 /Etherne37 ) - ( C9 /FPGA_Sp38 ) - ( C10 /Etherne39 ) - ( C11 ? ) - ( C12 /Non_vol40 ) - ( C13 /FPGA_Sp41 ) - ( C14 ? ) - ( C15 /Non_vol42 ) - ( C16 /Non_vol43 ) - ( C17 /Non_vol6 ) - ( C18 ? ) - ( C20 /FPGA_Sp44 ) - ( C21 +2.5V ) - ( C22 /FPGA_Sp45 ) - ( D1 /FPGA_Sp46 ) - ( D2 /FPGA_Sp47 ) - ( D3 ? ) - ( D4 GND ) - ( D5 ? ) - ( D6 /FPGA_Sp48 ) - ( D7 /Etherne49 ) - ( D8 /Etherne50 ) - ( D9 /FPGA_Sp51 ) - ( D10 /Etherne52 ) - ( D11 /Non_vol53 ) - ( D12 ? ) - ( D13 ? ) - ( D14 /Non_vol54 ) - ( D15 /Non_vol55 ) - ( D16 +2.5V ) - ( D17 /FPGA_Sp7 ) - ( D18 GND ) - ( D19 ? ) - ( D20 ? ) - ( D21 /FPGA_Sp56 ) - ( D22 /DDR_Ban57 ) - ( E1 /FPGA_Sp58 ) - ( E2 GND ) - ( E3 /DDR_Banks/M0_A8 ) - ( E4 ? ) - ( E5 ? ) - ( E6 ? ) - ( E7 GND ) - ( E8 ? ) - ( E9 +3.3V ) - ( E10 ? ) - ( E11 GND ) - ( E12 ? ) - ( E13 +3.3V ) - ( E14 ? ) - ( E15 GND ) - ( E16 /FPGA_Sp8 ) - ( E17 +3.3V ) - ( E18 ? ) - ( E19 +2.5V ) - ( E20 /FPGA_Sp59 ) - ( E21 GND ) - ( E22 /FPGA_Sp60 ) - ( F1 ? ) - ( F2 /DDR_Ban61 ) - ( F3 /FPGA_Sp62 ) - ( F4 +2.5V ) - ( F5 ? ) - ( F6 +2.5V ) - ( F7 ? ) - ( F8 ? ) - ( F9 ? ) - ( F10 ? ) - ( F11 +2.5V ) - ( F12 ? ) - ( F13 ? ) - ( F14 ? ) - ( F15 ? ) - ( F16 ? ) - ( F17 ? ) - ( F18 ? ) - ( F19 /FPGA_Sp63 ) - ( F20 /FPGA_Sp64 ) - ( F21 /DDR_Banks/M1_A0 ) - ( F22 /FPGA_Sp65 ) - ( G1 /DDR_Ban66 ) - ( G2 +2.5V ) - ( G3 /FPGA_Sp67 ) - ( G4 /DDR_Ban68 ) - ( G5 GND ) - ( G6 ? ) - ( G7 ? ) - ( G8 ? ) - ( G9 ? ) - ( G10 +3.3V ) - ( G11 ? ) - ( G12 +2.5V ) - ( G13 ? ) - ( G14 +3.3V ) - ( G15 ? ) - ( G16 ? ) - ( G17 ? ) - ( G18 GND ) - ( G19 /FPGA_Sp69 ) - ( G20 /FPGA_Sp70 ) - ( G21 +2.5V ) - ( G22 ? ) - ( H1 /FPGA_Sp71 ) - ( H2 /DDR_Banks/M0_A0 ) - ( H3 /FPGA_Sp72 ) - ( H4 /FPGA_Sp73 ) - ( H5 /FPGA_Sp74 ) - ( H6 /FPGA_Sp75 ) - ( H7 GND ) - ( H8 ? ) - ( H9 +2.5V ) - ( H10 ? ) - ( H11 ? ) - ( H12 ? ) - ( H13 ? ) - ( H14 ? ) - ( H15 +2.5V ) - ( H16 ? ) - ( H17 ? ) - ( H18 ? ) - ( H19 /FPGA_Sp76 ) - ( H20 /FPGA_Sp77 ) - ( H21 /DDR_Ban78 ) - ( H22 /FPGA_Sp79 ) - ( J1 /DDR_Ban80 ) - ( J2 GND ) - ( J3 /DDR_Ban81 ) - ( J4 /FPGA_Sp82 ) - ( J5 +2.5V ) - ( J6 ? ) - ( J7 ? ) - ( J8 +1.2V ) - ( J9 GND ) - ( J10 +1.2V ) - ( J11 GND ) - ( J12 +1.2V ) - ( J13 GND ) - ( J14 +1.2V ) - ( J15 GND ) - ( J16 ? ) - ( J17 /DDR_Ban83 ) - ( J18 +2.5V ) - ( J19 /FPGA_Sp84 ) - ( J20 /DDR_Ban85 ) - ( J21 GND ) - ( J22 /FPGA_Sp86 ) - ( K1 /FPGA_Sp87 ) - ( K2 /DDR_Ban88 ) - ( K3 /FPGA_Sp89 ) - ( K4 /FPGA_Sp90 ) - ( K5 /FPGA_Sp91 ) - ( K6 /DDR_Banks/M0_A3 ) - ( K7 ? ) - ( K8 ? ) - ( K9 +1.2V ) - ( K10 GND ) - ( K11 +1.2V ) - ( K12 GND ) - ( K13 +1.2V ) - ( K14 GND ) - ( K15 +2.5V ) - ( K16 ? ) - ( K17 /DDR_Ban92 ) - ( K18 ? ) - ( K19 /FPGA_Sp93 ) - ( K20 /FPGA_Sp94 ) - ( K21 /FPGA_Sp95 ) - ( K22 /FPGA_Sp96 ) - ( L1 ? ) - ( L2 +2.5V ) - ( L3 /DDR_Ban97 ) - ( L4 /DDR_Ban98 ) - ( L5 GND ) - ( L6 ? ) - ( L7 +2.5V ) - ( L8 +2.5V ) - ( L9 GND ) - ( L10 +1.2V ) - ( L11 GND ) - ( L12 +1.2V ) - ( L13 GND ) - ( L14 +1.2V ) - ( L15 ? ) - ( L16 +2.5V ) - ( L17 ? ) - ( L18 GND ) - ( L19 /DDR_Ban99 ) - ( L20 /FPGA_Sp100 ) - ( L21 +2.5V ) - ( L22 ? ) - ( M1 /FPGA_Sp101 ) - ( M2 /DDR_Ban102 ) - ( M3 /DDR_Ban103 ) - ( M4 ? ) - ( M5 ? ) - ( M6 ? ) - ( M7 ? ) - ( M8 ? ) - ( M9 +1.2V ) - ( M10 GND ) - ( M11 +1.2V ) - ( M12 GND ) - ( M13 +1.2V ) - ( M14 GND ) - ( M15 +2.5V ) - ( M16 ? ) - ( M17 ? ) - ( M18 /USB/USBA_VM ) - ( M19 ? ) - ( M20 /FPGA_Sp104 ) - ( M21 /FPGA_Sp105 ) - ( M22 /DDR_Ban106 ) - ( N1 /FPGA_Sp107 ) - ( N2 GND ) - ( N3 /DDR_Ban108 ) - ( N4 ? ) - ( N5 +2.5V ) - ( N6 ? ) - ( N7 ? ) - ( N8 +2.5V ) - ( N9 GND ) - ( N10 +1.2V ) - ( N11 GND ) - ( N12 +1.2V ) - ( N13 GND ) - ( N14 +1.2V ) - ( N15 ? ) - ( N16 /FPGA_Sp109 ) - ( N17 GND ) - ( N18 +2.5V ) - ( N19 ? ) - ( N20 /FPGA_Sp110 ) - ( N21 GND ) - ( N22 /FPGA_Sp111 ) - ( P1 /DDR_Ban112 ) - ( P2 /DDR_Ban113 ) - ( P3 ? ) - ( P4 ? ) - ( P5 ? ) - ( P6 ? ) - ( P7 ? ) - ( P8 ? ) - ( P9 +1.2V ) - ( P10 GND ) - ( P11 +1.2V ) - ( P12 GND ) - ( P13 +1.2V ) - ( P14 GND ) - ( P15 ? ) - ( P16 ? ) - ( P17 /USB/USBA_VP ) - ( P18 /FPGA_Sp114 ) - ( P19 ? ) - ( P20 ? ) - ( P21 /FPGA_Sp115 ) - ( P22 /FPGA_Sp116 ) - ( R1 /FPGA_Sp117 ) - ( R2 +2.5V ) - ( R3 /FPGA_Sp118 ) - ( R4 ? ) - ( R5 GND ) - ( R6 +2.5V ) - ( R7 ? ) - ( R8 ? ) - ( R9 ? ) - ( R10 +2.5V ) - ( R11 ? ) - ( R12 +2.5V ) - ( R13 ? ) - ( R14 +1.2V ) - ( R15 ? ) - ( R16 ? ) - ( R17 ? ) - ( R18 GND ) - ( R19 /USB/USBA_SPD ) - ( R20 /DDR_Ban119 ) - ( R21 +2.5V ) - ( R22 /DDR_Ban120 ) - ( T1 ? ) - ( T2 /DDR_Ban121 ) - ( T3 ? ) - ( T4 ? ) - ( T5 /FPGA_Sp122 ) - ( T6 ? ) - ( T7 ? ) - ( T8 ? ) - ( T9 N-000147 ) - ( T10 ? ) - ( T11 ? ) - ( T12 ? ) - ( T13 N-000147 ) - ( T14 ? ) - ( T15 ? ) - ( T16 ? ) - ( T17 ? ) - ( T18 ? ) - ( T19 ? ) - ( T20 ? ) - ( T21 /FPGA_Sp123 ) - ( T22 ? ) - ( U1 /DDR_Ban124 ) - ( U2 GND ) - ( U3 /FPGA_Sp125 ) - ( U4 ? ) - ( U5 +2.5V ) - ( U6 ? ) - ( U7 GND ) - ( U8 ? ) - ( U9 ? ) - ( U10 ? ) - ( U11 +2.5V ) - ( U12 ? ) - ( U13 /FPGA_Sp126 ) - ( U14 /FPGA_Sp127 ) - ( U15 ? ) - ( U16 ? ) - ( U17 ? ) - ( U18 +2.5V ) - ( U19 ? ) - ( U20 /FPGA_Sp128 ) - ( U21 GND ) - ( U22 /FPGA_Sp129 ) - ( V1 /FPGA_Sp130 ) - ( V2 /FPGA_Sp131 ) - ( V3 ? ) - ( V4 GND ) - ( V5 ? ) - ( V6 +2.5V ) - ( V7 ? ) - ( V8 N-000147 ) - ( V9 ? ) - ( V10 GND ) - ( V11 ? ) - ( V12 N-000147 ) - ( V13 ? ) - ( V14 GND ) - ( V15 ? ) - ( V16 N-000147 ) - ( V17 ? ) - ( V18 ? ) - ( V19 ? ) - ( V20 ? ) - ( V21 /FPGA_Sp132 ) - ( V22 /FPGA_Sp133 ) - ( W1 ? ) - ( W2 +2.5V ) - ( W3 ? ) - ( W4 ? ) - ( W5 N-000147 ) - ( W6 ? ) - ( W7 GND ) - ( W8 ? ) - ( W9 ? ) - ( W10 ? ) - ( W11 ? ) - ( W12 ? ) - ( W13 ? ) - ( W14 ? ) - ( W15 ? ) - ( W16 GND ) - ( W17 ? ) - ( W18 ? ) - ( W19 GND ) - ( W20 ? ) - ( W21 +2.5V ) - ( W22 ? ) - ( Y1 ? ) - ( Y3 ? ) - ( Y4 ? ) - ( Y5 ? ) - ( Y6 ? ) - ( Y7 ? ) - ( Y8 ? ) - ( Y9 ? ) - ( Y10 ? ) - ( Y11 ? ) - ( Y12 ? ) - ( Y13 ? ) - ( Y14 ? ) - ( Y15 ? ) - ( Y16 ? ) - ( Y17 ? ) - ( Y18 ? ) - ( Y19 ? ) - ( Y22 ? ) + ( AA9 GND ) + ( W19 GND ) + ( Y14 ? ) + ( W14 ? ) + ( U14 /FPGA_Spartan6/PROG_MISO2 ) + ( T14 ? ) + ( AB3 ? ) + ( AA3 N-000149 ) + ( Y13 ? ) + ( W13 ? ) + ( V13 ? ) + ( U13 /FPGA_Spartan6/PROG_MISO3 ) + ( T13 N-000149 ) + ( R13 ? ) + ( AB2 ? ) + ( AA2 ? ) + ( Y12 ? ) + ( W12 ? ) + ( V12 N-000149 ) + ( U12 ? ) + ( T12 ? ) + ( Y21 ? ) + ( Y11 ? ) + ( W11 ? ) + ( V11 ? ) + ( T11 ? ) + ( R11 ? ) + ( Y10 ? ) + ( W10 ? ) + ( U10 ? ) + ( T10 ? ) + ( Y9 ? ) + ( W9 ? ) ) - ( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG - ( 1 +2.5V ) - ( 2 /DDR_Ban108 ) - ( 3 +2.5V ) - ( 4 /FPGA_Sp107 ) - ( 5 /DDR_Ban102 ) - ( 6 GND ) - ( 7 /FPGA_Sp101 ) - ( 8 /DDR_Ban81 ) - ( 9 +2.5V ) - ( 10 /DDR_Ban80 ) - ( 11 /DDR_Ban88 ) - ( 12 GND ) - ( 13 /FPGA_Sp87 ) - ( 14 ? ) - ( 15 +2.5V ) - ( 16 /DDR_Ban97 ) - ( 17 ? ) - ( 18 +2.5V ) - ( 19 ? ) - ( 20 /DDR_Ban98 ) - ( 21 /DDR_Ban61 ) - ( 22 /FPGA_Sp90 ) - ( 23 /FPGA_Sp91 ) - ( 24 GND ) - ( 25 ? ) - ( 26 /FPGA_Sp67 ) - ( 27 /DDR_Ban66 ) - ( 28 /DDR_Ban68 ) - ( 29 /DDR_Banks/M0_A0 ) - ( 30 /FPGA_Sp71 ) - ( 31 /FPGA_Sp74 ) - ( 32 /DDR_Banks/M0_A3 ) - ( 33 +2.5V ) - ( 34 GND ) - ( 35 /FPGA_Sp62 ) - ( 36 /FPGA_Sp89 ) - ( 37 /FPGA_Sp82 ) - ( 38 /FPGA_Sp75 ) - ( 39 /DDR_Banks/M0_A8 ) - ( 40 /FPGA_Sp58 ) - ( 41 /DDR_Ban33 ) - ( 42 /FPGA_Sp46 ) - ( 43 ? ) - ( 44 /FPGA_Sp72 ) - ( 45 /FPGA_Sp47 ) - ( 46 /FPGA_Sp73 ) - ( 47 /DDR_Ban103 ) - ( 48 GND ) - ( 49 N-000052 ) - ( 50 ? ) - ( 51 /DDR_Ban121 ) - ( 52 GND ) - ( 53 ? ) - ( 54 /DDR_Ban113 ) - ( 55 +2.5V ) - ( 56 /DDR_Ban112 ) - ( 57 /FPGA_Sp118 ) - ( 58 GND ) - ( 59 /FPGA_Sp117 ) - ( 60 /FPGA_Sp125 ) - ( 61 +2.5V ) - ( 62 /DDR_Ban124 ) - ( 63 /FPGA_Sp131 ) - ( 64 GND ) - ( 65 /FPGA_Sp130 ) - ( 66 GND ) + ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} + ( 1 /Ethernet_Phy/ETH_PLL1.8V ) + ( 2 N-000334 ) ) - ( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG - ( 1 +2.5V ) - ( 2 /FPGA_Sp110 ) - ( 3 +2.5V ) - ( 4 /FPGA_Sp111 ) - ( 5 /FPGA_Sp105 ) - ( 6 GND ) - ( 7 /DDR_Ban106 ) - ( 8 /DDR_Ban85 ) - ( 9 +2.5V ) - ( 10 /FPGA_Sp86 ) - ( 11 /FPGA_Sp95 ) - ( 12 GND ) - ( 13 /FPGA_Sp96 ) - ( 14 ? ) - ( 15 +2.5V ) - ( 16 /FPGA_Sp100 ) - ( 17 ? ) - ( 18 +2.5V ) - ( 19 ? ) - ( 20 /DDR_Ban99 ) - ( 21 /FPGA_Sp76 ) - ( 22 /FPGA_Sp79 ) - ( 23 /DDR_Ban78 ) - ( 24 GND ) - ( 25 ? ) - ( 26 /DDR_Ban83 ) - ( 27 /DDR_Ban92 ) - ( 28 /FPGA_Sp69 ) - ( 29 /DDR_Banks/M1_A0 ) - ( 30 /FPGA_Sp65 ) - ( 31 /FPGA_Sp60 ) - ( 32 /FPGA_Sp70 ) - ( 33 +2.5V ) - ( 34 GND ) - ( 35 /FPGA_Sp64 ) - ( 36 /FPGA_Sp94 ) - ( 37 /FPGA_Sp93 ) - ( 38 /FPGA_Sp59 ) - ( 39 /FPGA_Sp44 ) - ( 40 /FPGA_Sp45 ) - ( 41 /FPGA_Sp63 ) - ( 42 /DDR_Ban57 ) - ( 43 ? ) - ( 44 /FPGA_Sp84 ) - ( 45 /FPGA_Sp56 ) - ( 46 /FPGA_Sp77 ) - ( 47 /FPGA_Sp104 ) - ( 48 GND ) - ( 49 N-000051 ) - ( 50 ? ) - ( 51 /FPGA_Sp123 ) - ( 52 GND ) - ( 53 ? ) - ( 54 /FPGA_Sp115 ) - ( 55 +2.5V ) - ( 56 /FPGA_Sp116 ) - ( 57 /DDR_Ban119 ) - ( 58 GND ) - ( 59 /DDR_Ban120 ) - ( 60 /FPGA_Sp128 ) - ( 61 +2.5V ) - ( 62 /FPGA_Sp129 ) - ( 63 /FPGA_Sp132 ) - ( 64 GND ) - ( 65 /FPGA_Sp133 ) - ( 66 GND ) + ( /4C4320F3/4C5D810A 0402 L3 INDUCTOR {Lib=INDUCTOR} + ( 1 /Ethernet_Phy/ETH_A1.8V ) + ( 2 /Ethernet_Phy/ETH_PLL1.8V ) ) - ( /4C4320F3/4C432132 LQFP48 U4 K8001 - ( 1 /Etherne11 ) - ( 2 /FPGA_Sp34 ) - ( 3 /FPGA_Sp35 ) - ( 4 /FPGA_Sp28 ) - ( 5 /Etherne15 ) - ( 6 /FPGA_Sp36 ) - ( 7 3.3V ) - ( 8 GND ) - ( 9 /Etherne16 ) - ( 10 /Etherne52 ) - ( 11 /Etherne29 ) - ( 12 GND ) - ( 13 /Etherne1 ) - ( 14 /Etherne17 ) - ( 15 /Etherne50 ) - ( 16 /FPGA_Sp51 ) - ( 17 /Etherne37 ) - ( 18 /FPGA_Sp38 ) - ( 19 /FPGA_Sp18 ) - ( 20 /Etherne49 ) - ( 21 /Etherne19 ) - ( 22 /FPGA_Sp30 ) - ( 23 GND ) - ( 24 3.3V ) - ( 25 /Etherne14 ) - ( 26 /Etherne12 ) - ( 27 /Etherne13 ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 /Etherne2 ) - ( 32 N-000327 ) - ( 33 N-000318 ) - ( 34 ? ) - ( 35 GND ) - ( 36 GND ) - ( 37 N-000326 ) - ( 38 /Etherne3 ) - ( 39 GND ) - ( 40 N-000328 ) - ( 41 N-000317 ) - ( 42 ? ) - ( 43 ? ) - ( 44 GND ) - ( 45 ? ) - ( 46 /Etherne39 ) - ( 47 /Etherne4 ) - ( 48 /FPGA_Sp48 ) + ( /4C4320F3/4C5D8104 $noname C6 C {Lib=C} + ( 1 /Ethernet_Phy/ETH_A1.8V ) + ( 2 N-000334 ) ) - ( /4C4227FE/4B76F108 NAND-48TSOP U5 NAND - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 /FPGA_Sp24 ) - ( 7 /FPGA_Sp24 ) - ( 8 /FPGA_Sp32 ) - ( 9 /Non_vol43 ) - ( 10 ? ) - ( 11 ? ) - ( 12 3.3V ) - ( 13 GND ) - ( 14 ? ) - ( 15 ? ) - ( 16 /Non_vol55 ) - ( 17 /FPGA_Sp23 ) - ( 18 /Non_vol42 ) - ( 19 3.3V ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 ? ) - ( 24 ? ) - ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 ? ) - ( 29 /Non_vol54 ) - ( 30 /Non_vol22 ) - ( 31 /FPGA_Sp41 ) - ( 32 /Non_vol21 ) - ( 33 ? ) - ( 34 ? ) - ( 35 ? ) - ( 36 GND ) - ( 37 +3.3V ) - ( 38 ? ) - ( 39 ? ) - ( 40 ? ) - ( 41 /Non_vol31 ) - ( 42 /Non_vol40 ) - ( 43 /Non_vol53 ) - ( 44 /Non_vol20 ) - ( 45 ? ) - ( 46 ? ) - ( 47 ? ) - ( 48 ? ) + ( /4C4320F3/4C5D80F3 0402 L1 INDUCTOR {Lib=INDUCTOR} + ( 1 N-000326 ) + ( 2 /Ethernet_Phy/ETH_A1.8V ) ) - ( /4C5F1EDC/4C5F2025 TSSOP-14 U6 MIC2550AYTS - ( 1 +2.5V ) - ( 2 /USB/USBA_SPD ) - ( 3 /FPGA_Sp109 ) - ( 4 /USB/USBA_VP ) - ( 5 /USB/USBA_VM ) - ( 7 GND ) - ( 8 GND ) - ( 9 /FPGA_Sp114 ) - ( 10 N-000337 ) - ( 11 N-000356 ) - ( 12 3.3V ) - ( 14 3.3V ) + ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} + ( 1 N-000326 ) + ( 2 N-000334 ) ) - ( /4C5F1EDC/4C6552BF TSSOP-14 U7 MIC2550AYTS - ( 1 +2.5V ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 7 GND ) - ( 8 GND ) - ( 9 ? ) - ( 10 N-000350 ) - ( 11 N-000345 ) - ( 12 3.3V ) - ( 14 3.3V ) + ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} + ( 1 /Ethernet_Phy/ETH_1.8V ) + ( 2 GND ) ) - ( /4C4227FE/4C65A75D SO8E U8 X25X64MB - ( 1 /FPGA_Sp122 ) - ( 2 /FPGA_Sp25 ) - ( 3 /FPGA_Sp127 ) - ( 4 GND ) - ( 5 /FPGA_Sp27 ) - ( 6 /FPGA_Sp26 ) - ( 7 /FPGA_Sp126 ) - ( 8 VCCO2 ) + ( /4C4320F3/4C5D7FB7 0402 L2 FB {Lib=INDUCTOR} + ( 1 3.3V ) + ( 2 /Ethernet_Phy/ETH_A3.3V ) ) - ( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 - ( 1 N-000356 ) - ( 2 GND ) + ( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C} + ( 1 /Ethernet_Phy/ETH_A3.3V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 - ( 1 N-000337 ) - ( 2 GND ) + ( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C} + ( 1 /Ethernet_Phy/ETH_A3.3V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B8 0603 V3 V0402MHS03 - ( 1 N-000345 ) - ( 2 GND ) + ( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B9 0603 V4 V0402MHS03 - ( 1 N-000350 ) - ( 2 GND ) + ( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} + ( 1 /Ethernet_Phy/ETH_MDIO ) + ( 2 3.3V ) + ) + ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} + ( 1 N-000331 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} + ( 1 N-000319 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} + ( 1 N-000319 ) + ( 2 GND ) + ) + ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} + ( 1 /Ethernet_Phy/ETH_MDIO ) + ( 2 /Ethernet_Phy/ETH_MDC ) + ( 3 /FPGA_Spartan6/ETH_RXD3 ) + ( 4 /Ethernet_Phy/ETH_RXD2 ) + ( 5 /Ethernet_Phy/ETH_RXD1 ) + ( 6 /Ethernet_Phy/ETH_RXD0 ) + ( 7 3.3V ) + ( 8 GND ) + ( 9 /FPGA_Spartan6/ETH_RXDV ) + ( 10 /Ethernet_Phy/ETH_RXC ) + ( 11 /Ethernet_Phy/ETH_RXER ) + ( 12 GND ) + ( 13 /Ethernet_Phy/ETH_1.8V ) + ( 14 /FPGA_Spartan6/ETH_TXER ) + ( 15 /FPGA_Spartan6/ETH_TXC ) + ( 16 /FPGA_Spartan6/ETH_TXEN ) + ( 17 /Ethernet_Phy/ETH_TXD0 ) + ( 18 /Ethernet_Phy/ETH_TXD1 ) + ( 19 /FPGA_Spartan6/ETH_TXD2 ) + ( 20 /Ethernet_Phy/ETH_TXD3 ) + ( 21 /Ethernet_Phy/ETH_COL ) + ( 22 /FPGA_Spartan6/ETH_CRS ) + ( 23 GND ) + ( 24 3.3V ) + ( 25 /FPGA_Spartan6/ETH_INT ) + ( 26 /Ethernet_Phy/ETH_LED0 ) + ( 27 /Ethernet_Phy/ETH_LED1 ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 /Ethernet_Phy/ETH_A1.8V ) + ( 32 N-000332 ) + ( 33 N-000323 ) + ( 34 ? ) + ( 35 GND ) + ( 36 GND ) + ( 37 N-000331 ) + ( 38 /Ethernet_Phy/ETH_A3.3V ) + ( 39 GND ) + ( 40 N-000333 ) + ( 41 N-000322 ) + ( 42 ? ) + ( 43 ? ) + ( 44 GND ) + ( 45 ? ) + ( 46 /Ethernet_Phy/ETH_CLK ) + ( 47 /Ethernet_Phy/ETH_PLL1.8V ) + ( 48 /FPGA_Spartan6/ETH_RESET_N ) + ) + ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} + ( 1 3.3V ) + ( 2 N-000322 ) + ) + ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} + ( 1 3.3V ) + ( 2 N-000333 ) + ) + ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} + ( 1 3.3V ) + ( 2 N-000332 ) + ) + ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} + ( 1 3.3V ) + ( 2 N-000323 ) + ) + ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} + ( 1 N-000336 ) + ( 2 /Ethernet_Phy/ETH_LED1 ) + ) + ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} + ( 1 N-000320 ) + ( 2 /Ethernet_Phy/ETH_LED0 ) + ) + ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} + ( 1 N-000322 ) + ( 2 N-000333 ) + ( 3 3.3V ) + ( 4 GND ) + ( 5 GND ) + ( 6 3.3V ) + ( 7 N-000323 ) + ( 8 N-000332 ) + ( 9 3.3V ) + ( 10 N-000320 ) + ( 11 3.3V ) + ( 12 N-000336 ) + ( 13 N-000319 ) + ( 14 N-000319 ) + ) + ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C65D28E 0402 C71 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61D1D4 1206 C34 10uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61D151 1206 C33 10uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R} + ( 1 +2.5V ) + ( 2 N-000051 ) + ) + ( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R} + ( 1 N-000051 ) + ( 2 N-000050 ) + ) + ( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R} + ( 1 N-000052 ) + ( 2 N-000054 ) + ) + ( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R} + ( 1 +2.5V ) + ( 2 N-000052 ) + ) + ( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 N-000051 ) + ) + ( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP} + ( 1 N-000051 ) + ( 2 N-000050 ) + ) + ( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP} + ( 1 N-000052 ) + ( 2 N-000054 ) + ) + ( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 N-000052 ) + ) + ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} + ( 1 +2.5V ) + ( 2 /FPGA_Spartan6/M1_DQ0 ) + ( 3 +2.5V ) + ( 4 /FPGA_Spartan6/M1_DQ1 ) + ( 5 /FPGA_Spartan6/M1_DQ2 ) + ( 6 GND ) + ( 7 /FPGA_Spartan6/M1_DQ3 ) + ( 8 /DDR_Banks/M1_DQ4 ) + ( 9 +2.5V ) + ( 10 /DDR_Banks/M1_DQ5 ) + ( 11 /FPGA_Spartan6/M1_DQ6 ) + ( 12 GND ) + ( 13 /FPGA_Spartan6/M1_DQ7 ) + ( 14 ? ) + ( 15 +2.5V ) + ( 16 /FPGA_Spartan6/M1_LDQS ) + ( 17 ? ) + ( 18 +2.5V ) + ( 19 ? ) + ( 20 /FPGA_Spartan6/M1_LDM ) + ( 21 /DDR_Banks/M1_WE# ) + ( 22 /FPGA_Spartan6/M1_CAS# ) + ( 23 /DDR_Banks/M1_RAS# ) + ( 24 GND ) + ( 25 ? ) + ( 26 /DDR_Banks/M1_BA0 ) + ( 27 /DDR_Banks/M1_BA1 ) + ( 28 /DDR_Banks/M1_A10 ) + ( 29 /DDR_Banks/M1_A0 ) + ( 30 /FPGA_Spartan6/M1_A1 ) + ( 31 /FPGA_Spartan6/M1_A2 ) + ( 32 /FPGA_Spartan6/M1_A3 ) + ( 33 +2.5V ) + ( 34 GND ) + ( 35 /FPGA_Spartan6/M1_A4 ) + ( 36 /DDR_Banks/M1_A5 ) + ( 37 /FPGA_Spartan6/M1_A6 ) + ( 38 /FPGA_Spartan6/M1_A7 ) + ( 39 /FPGA_Spartan6/M1_A8 ) + ( 40 /DDR_Banks/M1_A9 ) + ( 41 /FPGA_Spartan6/M1_A11 ) + ( 42 /FPGA_Spartan6/M1_A12 ) + ( 43 ? ) + ( 44 /FPGA_Spartan6/M1_CLK# ) + ( 45 /DDR_Banks/M1_CKE ) + ( 46 /FPGA_Spartan6/M1_CLK ) + ( 47 /DDR_Banks/M1_UDM ) + ( 48 GND ) + ( 49 N-000051 ) + ( 50 ? ) + ( 51 /DDR_Banks/M1_UDQS ) + ( 52 GND ) + ( 53 ? ) + ( 54 /FPGA_Spartan6/M1_DQ8 ) + ( 55 +2.5V ) + ( 56 /FPGA_Spartan6/M1_DQ9 ) + ( 57 /DDR_Banks/M1_DQ10 ) + ( 58 GND ) + ( 59 /DDR_Banks/M1_DQ11 ) + ( 60 /FPGA_Spartan6/M1_DQ12 ) + ( 61 +2.5V ) + ( 62 /DDR_Banks/M1_DQ13 ) + ( 63 /FPGA_Spartan6/M1_DQ14 ) + ( 64 GND ) + ( 65 /FPGA_Spartan6/M1_DQ15 ) + ( 66 GND ) + ) + ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} + ( 1 +2.5V ) + ( 2 /DDR_Banks/M0_DQ0 ) + ( 3 +2.5V ) + ( 4 /FPGA_Spartan6/M0_DQ1 ) + ( 5 /FPGA_Spartan6/M0_DQ2 ) + ( 6 GND ) + ( 7 /DDR_Banks/M0_DQ3 ) + ( 8 /DDR_Banks/M0_DQ4 ) + ( 9 +2.5V ) + ( 10 /FPGA_Spartan6/M0_DQ5 ) + ( 11 /FPGA_Spartan6/M0_DQ6 ) + ( 12 GND ) + ( 13 /DDR_Banks/M0_DQ7 ) + ( 14 ? ) + ( 15 +2.5V ) + ( 16 /FPGA_Spartan6/M0_LDQS ) + ( 17 ? ) + ( 18 +2.5V ) + ( 19 ? ) + ( 20 /FPGA_Spartan6/M0_LDM ) + ( 21 /DDR_Banks/M0_WE# ) + ( 22 /FPGA_Spartan6/M0_CAS# ) + ( 23 /FPGA_Spartan6/M0_RAS# ) + ( 24 GND ) + ( 25 ? ) + ( 26 /DDR_Banks/M0_BA0 ) + ( 27 /FPGA_Spartan6/M0_BA1 ) + ( 28 /FPGA_Spartan6/M0_A10 ) + ( 29 /FPGA_Spartan6/M0_A0 ) + ( 30 /DDR_Banks/M0_A1 ) + ( 31 /DDR_Banks/M0_A2 ) + ( 32 /FPGA_Spartan6/M0_A3 ) + ( 33 +2.5V ) + ( 34 GND ) + ( 35 /FPGA_Spartan6/M0_A4 ) + ( 36 /FPGA_Spartan6/M0_A5 ) + ( 37 /FPGA_Spartan6/M0_A6 ) + ( 38 /FPGA_Spartan6/M0_A7 ) + ( 39 /FPGA_Spartan6/M0_A8 ) + ( 40 /FPGA_Spartan6/M0_A9 ) + ( 41 /FPGA_Spartan6/M0_A11 ) + ( 42 /FPGA_Spartan6/M0_A12 ) + ( 43 ? ) + ( 44 /DDR_Banks/M0_CLK# ) + ( 45 /DDR_Banks/M0_CKE ) + ( 46 /DDR_Banks/M0_CLK ) + ( 47 /DDR_Banks/M0_UDM ) + ( 48 GND ) + ( 49 N-000052 ) + ( 50 ? ) + ( 51 /DDR_Banks/M0_UDQS ) + ( 52 GND ) + ( 53 ? ) + ( 54 /FPGA_Spartan6/M0_DQ8 ) + ( 55 +2.5V ) + ( 56 /FPGA_Spartan6/M0_DQ9 ) + ( 57 /DDR_Banks/M0_DQ10 ) + ( 58 GND ) + ( 59 /DDR_Banks/M0_DQ11 ) + ( 60 /FPGA_Spartan6/M0_DQ12 ) + ( 61 +2.5V ) + ( 62 /DDR_Banks/M0_DQ13 ) + ( 63 /FPGA_Spartan6/M0_DQ14 ) + ( 64 GND ) + ( 65 /DDR_Banks/M0_DQ15 ) + ( 66 GND ) ) ) * { Allowed footprints by component: -$component C1 +$component C74 SM* C? C1-1 $endlist -$component C2 +$component C73 SM* C? C1-1 $endlist -$component C3 - SM* - C? - C1-1 -$endlist -$component C4 - SM* - C? - C1-1 -$endlist -$component C5 - SM* - C? - C1-1 -$endlist -$component C6 - SM* - C? - C1-1 -$endlist -$component C7 - SM* - C? - C1-1 -$endlist -$component C8 - SM* - C? - C1-1 -$endlist -$component C9 - SM* - C? - C1-1 -$endlist -$component C10 - SM* - C? - C1-1 -$endlist -$component C11 - SM* - C? - C1-1 -$endlist -$component C12 - SM* - C? - C1-1 -$endlist -$component C13 - SM* - C? - C1-1 -$endlist -$component C14 - SM* - C? - C1-1 -$endlist -$component C15 - SM* - C? - C1-1 -$endlist -$component C16 - SM* - C? - C1-1 -$endlist -$component C17 - SM* - C? - C1-1 -$endlist -$component C18 - SM* - C? - C1-1 -$endlist -$component C19 - SM* - C? - C1-1 -$endlist -$component C20 - SM* - C? - C1-1 -$endlist -$component C21 - SM* - C? - C1-1 -$endlist -$component C22 - SM* - C? - C1-1 -$endlist -$component C23 - SM* - C? - C1-1 -$endlist -$component C24 - SM* - C? - C1-1 -$endlist -$component C25 - SM* - C? - C1-1 -$endlist -$component C26 - SM* - C? - C1-1 -$endlist -$component C27 - SM* - C? - C1-1 -$endlist -$component C28 - SM* - C? - C1-1 -$endlist -$component C29 - SM* - C? - C1-1 -$endlist -$component C30 - SM* - C? - C1-1 -$endlist -$component C31 - SM* - C? - C1-1 -$endlist -$component C32 - SM* - C? - C1-1 -$endlist -$component C33 - SM* - C? - C1-1 -$endlist -$component C34 +$component C72 SM* C? C1-1 @@ -1395,137 +1245,34 @@ $component C38 C? C1-1 $endlist -$component C39 +$component R15 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R10 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C16 SM* C? C1-1 $endlist -$component C40 +$component C15 SM* C? C1-1 $endlist -$component C41 +$component C14 SM* C? C1-1 $endlist -$component C42 - SM* - C? - C1-1 -$endlist -$component C43 - SM* - C? - C1-1 -$endlist -$component C44 - SM* - C? - C1-1 -$endlist -$component C45 - SM* - C? - C1-1 -$endlist -$component C46 - SM* - C? - C1-1 -$endlist -$component C47 - SM* - C? - C1-1 -$endlist -$component C48 - SM* - C? - C1-1 -$endlist -$component C49 - SM* - C? - C1-1 -$endlist -$component C50 - SM* - C? - C1-1 -$endlist -$component C51 - SM* - C? - C1-1 -$endlist -$component C52 - SM* - C? - C1-1 -$endlist -$component C53 - SM* - C? - C1-1 -$endlist -$component C54 - SM* - C? - C1-1 -$endlist -$component C55 - SM* - C? - C1-1 -$endlist -$component C56 - SM* - C? - C1-1 -$endlist -$component C57 - SM* - C? - C1-1 -$endlist -$component C58 - SM* - C? - C1-1 -$endlist -$component C59 - SM* - C? - C1-1 -$endlist -$component C60 - SM* - C? - C1-1 -$endlist -$component C61 - SM* - C? - C1-1 -$endlist -$component C62 - SM* - C? - C1-1 -$endlist -$component C63 - SM* - C? - C1-1 -$endlist -$component C64 - SM* - C? - C1-1 -$endlist -$component C65 +$component C13 SM* C? C1-1 @@ -1535,12 +1282,22 @@ $component C66 C? C1-1 $endlist -$component C67 +$component C63 SM* C? C1-1 $endlist -$component C68 +$component C60 + SM* + C? + C1-1 +$endlist +$component C57 + SM* + C? + C1-1 +$endlist +$component C54 SM* C? C1-1 @@ -1550,27 +1307,172 @@ $component C69 C? C1-1 $endlist -$component C70 +$component C67 SM* C? C1-1 $endlist -$component C71 +$component C64 SM* C? C1-1 $endlist -$component C72 +$component C61 SM* C? C1-1 $endlist -$component C73 +$component C58 SM* C? C1-1 $endlist -$component C74 +$component C55 + SM* + C? + C1-1 +$endlist +$component C68 + SM* + C? + C1-1 +$endlist +$component C65 + SM* + C? + C1-1 +$endlist +$component C62 + SM* + C? + C1-1 +$endlist +$component C59 + SM* + C? + C1-1 +$endlist +$component C56 + SM* + C? + C1-1 +$endlist +$component C50 + SM* + C? + C1-1 +$endlist +$component C47 + SM* + C? + C1-1 +$endlist +$component C44 + SM* + C? + C1-1 +$endlist +$component C41 + SM* + C? + C1-1 +$endlist +$component C53 + SM* + C? + C1-1 +$endlist +$component C51 + SM* + C? + C1-1 +$endlist +$component C49 + SM* + C? + C1-1 +$endlist +$component C46 + SM* + C? + C1-1 +$endlist +$component C52 + SM* + C? + C1-1 +$endlist +$component C43 + SM* + C? + C1-1 +$endlist +$component C40 + SM* + C? + C1-1 +$endlist +$component C48 + SM* + C? + C1-1 +$endlist +$component C45 + SM* + C? + C1-1 +$endlist +$component C42 + SM* + C? + C1-1 +$endlist +$component C39 + SM* + C? + C1-1 +$endlist +$component C9 + SM* + C? + C1-1 +$endlist +$component C6 + SM* + C? + C1-1 +$endlist +$component C4 + SM* + C? + C1-1 +$endlist +$component C2 + SM* + C? + C1-1 +$endlist +$component C8 + SM* + C? + C1-1 +$endlist +$component C7 + SM* + C? + C1-1 +$endlist +$component C5 + SM* + C? + C1-1 +$endlist +$component C3 + SM* + C? + C1-1 +$endlist +$component C1 SM* C? C1-1 @@ -1587,6 +1489,27 @@ $component R2 SM0805 R?-* $endlist +$component C11 + SM* + C? + C1-1 +$endlist +$component C10 + SM* + C? + C1-1 +$endlist +$component C12 + SM* + C? + C1-1 +$endlist +$component R9 + R? + SM0603 + SM0805 + R?-* +$endlist $component R3 R? SM0603 @@ -1599,19 +1522,13 @@ $component R4 SM0805 R?-* $endlist -$component R5 - R? - SM0603 - SM0805 - R?-* -$endlist $component R6 R? SM0603 SM0805 R?-* $endlist -$component R7 +$component R5 R? SM0603 SM0805 @@ -1623,29 +1540,91 @@ $component R8 SM0805 R?-* $endlist -$component R9 +$component R7 R? SM0603 SM0805 R?-* $endlist -$component R10 - R? - SM0603 - SM0805 - R?-* +$component C70 + SM* + C? + C1-1 $endlist -$component R11 - R? - SM0603 - SM0805 - R?-* +$component C71 + SM* + C? + C1-1 $endlist -$component R12 - R? - SM0603 - SM0805 - R?-* +$component C34 + SM* + C? + C1-1 +$endlist +$component C33 + SM* + C? + C1-1 +$endlist +$component C28 + SM* + C? + C1-1 +$endlist +$component C29 + SM* + C? + C1-1 +$endlist +$component C31 + SM* + C? + C1-1 +$endlist +$component C30 + SM* + C? + C1-1 +$endlist +$component C32 + SM* + C? + C1-1 +$endlist +$component C27 + SM* + C? + C1-1 +$endlist +$component C21 + SM* + C? + C1-1 +$endlist +$component C26 + SM* + C? + C1-1 +$endlist +$component C24 + SM* + C? + C1-1 +$endlist +$component C25 + SM* + C? + C1-1 +$endlist +$component C23 + SM* + C? + C1-1 +$endlist +$component C22 + SM* + C? + C1-1 $endlist $component R13 R? @@ -1659,11 +1638,928 @@ $component R14 SM0805 R?-* $endlist -$component R15 +$component R12 R? SM0603 SM0805 R?-* $endlist +$component R11 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C19 + SM* + C? + C1-1 +$endlist +$component C20 + SM* + C? + C1-1 +$endlist +$component C18 + SM* + C? + C1-1 +$endlist +$component C17 + SM* + C? + C1-1 +$endlist $endfootprintlist } +{ Pin List by Nets +Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" + U8 1 + U1 T5 +Net 2 "/FPGA Spartan6/NF_RE_N" "NF_RE_N" + U5 8 + U1 B16 +Net 3 "/FPGA Spartan6/NF_CS1_N" "NF_CS1_N" + U1 C16 + U5 9 +Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE" + U5 17 + U1 A15 +Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" + U1 D7 + U4 15 +Net 6 "/Ethernet Phy/ETH_RXC" "ETH_RXC" + U4 10 + U1 D8 +Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK" + U4 46 + U1 A4 +Net 8 "/USB/USBA_SPD" "USBA_SPD" + U6 2 + U1 R19 +Net 9 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" + U6 9 + U1 P18 +Net 10 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" + U6 3 + U1 N16 +Net 11 "/USB/USBA_VP" "USBA_VP" + U1 P17 + U6 4 +Net 12 "/USB/USBA_VM" "USBA_VM" + U1 M18 + U6 5 +Net 13 "/Ethernet Phy/ETH_COL" "ETH_COL" + U4 21 + U1 B10 +Net 14 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" + U4 22 + U1 C10 +Net 15 "/FPGA Spartan6/SD_CLK" "SD_CLK" + J1 5 + U1 E16 +Net 16 "/FPGA Spartan6/ETH_INT" "ETH_INT" + U4 25 + U1 A10 +Net 17 "/Ethernet Phy/ETH_MDC" "ETH_MDC" + U4 2 + U1 D10 +Net 18 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" + U4 1 + R1 1 + U1 C5 +Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" + U1 A5 + U4 48 +Net 20 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" + U1 C7 + U4 9 +Net 21 "/Ethernet Phy/ETH_RXER" "ETH_RXER" + U1 A7 + U4 11 +Net 22 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" + U4 14 + U1 B8 +Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" + U1 A8 + U4 16 +Net 24 "/DDR Banks/M1_UDM" "M1_UDM" + U3 47 + U1 M20 +Net 25 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" + U1 L20 + U3 16 +Net 26 "/FPGA Spartan6/M1_LDM" "M1_LDM" + U3 20 + U1 L19 +Net 27 "/DDR Banks/M1_UDQS" "M1_UDQS" + U3 51 + U1 T21 +Net 28 "/DDR Banks/M0_UDQS" "M0_UDQS" + U1 T2 + U2 51 +Net 29 "/FPGA Spartan6/M0_LDM" "M0_LDM" + U2 20 + U1 L4 +Net 30 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" + U3 22 + U1 H22 +Net 31 "/DDR Banks/M1_CKE" "M1_CKE" + U3 45 + U1 D21 +Net 32 "/FPGA Spartan6/M1_CLK" "M1_CLK" + U3 46 + U1 H20 +Net 33 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" + U1 J19 + U3 44 +Net 34 "GND" "GND" + U1 B13 + U1 A22 + U2 24 + U2 64 + U2 34 + C46 2 + C44 2 + C41 2 + C49 2 + U3 64 + C51 2 + U3 6 + C53 2 + C2 2 + C55 2 + C58 2 + U3 52 + U3 12 + C40 2 + U3 66 + C43 2 + C52 2 + C47 2 + C50 2 + C56 2 + C59 2 + C62 2 + C65 2 + C68 2 + U3 34 + U3 24 + U1 AB22 + U1 AA13 + U1 AA17 + U1 M14 + U1 P14 + U1 V14 + U1 E15 + U1 J15 + C72 2 + C73 2 + C74 2 + U8 4 + U2 12 + U1 J13 + U1 L13 + J1 6 + J1 COM + J1 CASE + J1 CASE + J1 CASE + U1 N13 + U1 K14 + C39 2 + C61 2 + U2 58 + U2 48 + C64 2 + C67 2 + C69 2 + U2 66 + C54 2 + C57 2 + C60 2 + U2 6 + C63 2 + C66 2 + U3 58 + U3 48 + U2 52 + U1 AB1 + U1 K12 + U1 M12 + U5 36 + U1 P12 + U1 B17 + U1 N17 + U1 D18 + U1 G18 + U1 L18 + U1 R18 + U1 W19 + U1 AA9 + C42 2 + C45 2 + C48 2 + U1 E21 + U5 13 + U1 J21 + U1 N21 + U1 U21 + C16 2 + U4 23 + V2 2 + C33 2 + C1 2 + C3 2 + C5 2 + C7 2 + C8 2 + R9 2 + C12 2 + U1 B9 + U4 44 + U1 J11 + U1 L11 + U1 N11 + U1 W7 + V3 2 + C38 2 + R15 2 + L5 2 + V1 2 + R2 2 + C34 2 + C71 2 + C70 2 + U1 J9 + C10 2 + U1 L9 + U1 W16 + C11 2 + U4 35 + U4 36 + U4 8 + U4 12 + C15 2 + U1 G5 + C13 2 + C14 2 + U6 7 + U1 E7 + U1 H7 + U1 R5 + U1 U7 + C22 2 + C23 2 + U1 K10 + R10 2 + C25 2 + C24 2 + U1 M10 + C26 2 + C21 2 + U1 P10 + U1 B5 + U1 V10 + U1 E11 + U6 8 + C27 2 + C32 2 + C30 2 + C31 2 + U1 L5 + C29 2 + C28 2 + L7 2 + U4 39 + U1 N2 + U1 J2 + U1 E2 + U1 A1 + U1 N9 + U1 D4 + U7 7 + U7 8 + U1 AA5 + J4 5 + C35 2 + C36 2 + C37 2 + V4 2 + U1 U2 + U1 V4 + J4 4 +Net 35 "/DDR Banks/M0_CLK#" "M0_CLK#" + U1 H3 + U2 44 +Net 36 "/DDR Banks/M0_CLK" "M0_CLK" + U1 H4 + U2 46 +Net 37 "/DDR Banks/M0_CKE" "M0_CKE" + U1 D2 + U2 45 +Net 38 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" + U1 K4 + U2 22 +Net 39 "/DDR Banks/M1_WE#" "M1_WE#" + U1 H19 + U3 21 +Net 40 "/DDR Banks/M1_RAS#" "M1_RAS#" + U3 23 + U1 H21 +Net 41 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" + U2 23 + U1 K5 +Net 42 "/DDR Banks/M0_WE#" "M0_WE#" + U2 21 + U1 F2 +Net 43 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" + U2 16 + U1 L3 +Net 44 "/DDR Banks/M0_UDM" "M0_UDM" + U1 M3 + U2 47 +Net 45 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" + U8 6 + U1 AA21 +Net 46 "/FPGA Spartan6/NF_RNB" "NF_RNB" + U1 A16 + U5 6 + U5 7 +Net 47 "/Non volatile memories/NF_WE_N" "NF_WE_N" + U1 C15 + U5 18 +Net 48 "/FPGA Spartan6/NF_CLE" "NF_CLE" + U1 D15 + U5 16 +Net 49 "/FPGA Spartan6/SD_CMD" "SD_CMD" + J1 3 + U1 D17 +Net 50 "" "" + R14 2 + C20 2 +Net 51 "" "" + U3 49 + R13 2 + R14 1 + C19 2 + C20 1 +Net 52 "" "" + C18 1 + C17 2 + R11 2 + R12 1 + U2 49 +Net 53 "+2.5V" "+2.5V" + U1 M15 + U1 N5 + U1 J5 + U1 D16 + U1 C2 + U1 W2 + U1 R2 + U1 L2 + U1 R6 + U1 V6 + U1 U18 + U1 N18 + U1 J18 + U1 E19 + U1 W21 + U1 R21 + U1 R10 + U1 L21 + U1 F11 + U1 G21 + U1 L16 + U1 L8 + U1 N8 + U1 H9 + U1 G2 + C70 1 + C71 1 + C34 1 + C33 1 + U6 1 + U7 1 + C21 1 + C26 1 + C24 1 + C25 1 + C23 1 + C22 1 + R13 1 + C28 1 + C29 1 + C31 1 + C30 1 + C32 1 + C27 1 + U1 U5 + U1 F6 + U1 F4 + U1 C21 + U1 L7 + U1 G12 + U1 U11 + U2 61 + C66 1 + U2 1 + C63 1 + U2 3 + C60 1 + C57 1 + U2 9 + C54 1 + U2 18 + U2 33 + U1 K15 + U1 H15 + U3 18 + U3 61 + U3 33 + C68 1 + C65 1 + C62 1 + C59 1 + C56 1 + U2 15 + U2 55 + U3 3 + C53 1 + U3 9 + C51 1 + U1 R12 + C49 1 + C46 1 + C40 1 + C43 1 + U3 55 + C52 1 + U3 15 + U3 1 + C17 1 + C19 1 + R11 1 +Net 54 "" "" + C18 2 + R12 2 +Net 99 "3.3V" "3.3V" + C10 1 + C11 1 + J4 3 + J4 6 + J4 9 + J4 11 + R5 1 + C5 1 + C3 1 + C1 1 + R1 2 + U4 24 + U4 7 + U7 14 + U7 12 + U6 12 + U6 14 + R3 1 + R4 1 + R6 1 + L2 1 + U5 19 + U5 12 +Net 100 "VCCO2" "VCCO2" + C64 1 + C61 1 + C55 1 + C58 1 + U8 8 + C69 1 + C67 1 +Net 101 "+3.3V" "+3.3V" + C73 1 + C74 1 + C72 1 + U1 B4 + C44 1 + C47 1 + C50 1 + U1 B7 + U1 B15 + U1 G14 + U1 E13 + U1 B11 + U1 G10 + U1 B19 + U5 37 + U1 E9 + C41 1 + U1 E17 +Net 149 "" "" + U1 AA19 + U1 AA15 + U1 T9 + U1 V8 + U1 AA11 + U1 W5 + U1 T13 + U1 AA7 + U1 AA3 + U1 V12 + U1 V16 +Net 237 "+1.2V" "+1.2V" + C48 1 + C45 1 + C42 1 + C39 1 + U1 R14 + U1 J10 + U1 L10 + U1 N10 + U1 K11 + U1 M11 + U1 J8 + U1 K9 + U1 M9 + U1 P9 + U1 J12 + U1 L12 + U1 N12 + U1 P11 + U1 J14 + U1 K13 + U1 N14 + U1 M13 + U1 L14 + U1 P13 +Net 319 "" "" + J4 14 + J4 13 + C12 1 + R9 1 +Net 320 "" "" + R7 1 + J4 10 +Net 321 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + R7 2 + U4 26 +Net 322 "" "" + J4 1 + U4 41 + R3 2 +Net 323 "" "" + U4 33 + R5 2 + J4 7 +Net 324 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + L3 1 + C6 1 + L1 2 + U4 31 +Net 325 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" + U4 13 + C2 1 +Net 326 "" "" + C4 1 + L1 1 +Net 327 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + U4 38 + C8 1 + L2 2 + C7 1 +Net 328 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + U4 47 + L3 2 + C9 1 +Net 331 "" "" + R2 1 + U4 37 +Net 332 "" "" + U4 32 + J4 8 + R6 2 +Net 333 "" "" + U4 40 + J4 2 + R4 2 +Net 334 "" "" + C4 2 + C6 2 + C9 2 +Net 335 "/Ethernet Phy/ETH_LED1" "ETH_LED1" + R8 2 + U4 27 +Net 336 "" "" + J4 12 + R8 1 +Net 342 "" "" + V2 1 + J5 2 + U6 10 + V2 1 +Net 343 "" "" + C16 1 + R10 1 + J5 S4 + J5 S3 + J5 S1 + J5 S2 +Net 345 "+5V" "+5V" + F1 2 + F2 2 +Net 346 "" "" + L6 1 + F2 1 +Net 350 "" "" + V3 1 + V3 1 + U7 11 +Net 354 "" "" + J5 4 + L5 1 +Net 355 "" "" + V4 1 + U7 10 + V4 1 +Net 356 "" "" + C36 1 + C35 1 + C37 1 +Net 357 "" "" + C38 1 + R15 1 +Net 358 "" "" + L4 2 + J5 1 +Net 359 "" "" + F1 1 + L4 1 +Net 360 "" "" + C15 1 + C14 1 + C13 1 +Net 361 "" "" + V1 1 + J5 3 + V1 1 + U6 11 +Net 362 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" + U8 7 + U1 U13 +Net 363 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" + U8 3 + U1 U14 +Net 364 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" + U8 2 + U1 AA20 +Net 365 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" + U8 5 + U1 AB20 +Net 366 "/FPGA Spartan6/NF_D7" "NF_D7" + U5 44 + U1 A11 +Net 367 "/FPGA Spartan6/NF_D6" "NF_D6" + U5 43 + U1 D11 +Net 368 "/Non volatile memories/NF_D5" "NF_D5" + U5 42 + U1 C12 +Net 369 "/Non volatile memories/NF_D4" "NF_D4" + U5 41 + U1 B12 +Net 370 "/Non volatile memories/NF_D3" "NF_D3" + U5 32 + U1 A12 +Net 371 "/Non volatile memories/NF_D2" "NF_D2" + U5 31 + U1 C13 +Net 372 "/Non volatile memories/NF_D1" "NF_D1" + U1 A13 + U5 30 +Net 373 "/FPGA Spartan6/NF_D0" "NF_D0" + U5 29 + U1 D14 +Net 374 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" + U1 A9 + U4 20 +Net 375 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" + U4 19 + U1 C9 +Net 376 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" + U4 18 + U1 C8 +Net 377 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" + U1 D9 + U4 17 +Net 378 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" + U1 D6 + U4 3 +Net 379 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" + U1 C6 + U4 4 +Net 380 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" + U4 5 + U1 B6 +Net 381 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" + U4 6 + U1 A6 +Net 382 "/FPGA Spartan6/M0_BA1" "M0_BA1" + U2 27 + U1 G1 +Net 383 "/DDR Banks/M0_BA0" "M0_BA0" + U2 26 + U1 G3 +Net 384 "/DDR Banks/M1_BA1" "M1_BA1" + U3 27 + U1 K17 +Net 385 "/DDR Banks/M1_BA0" "M1_BA0" + U1 J17 + U3 26 +Net 386 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" + U1 V22 + U3 65 +Net 387 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" + U1 V21 + U3 63 +Net 388 "/DDR Banks/M1_DQ13" "M1_DQ13" + U1 U22 + U3 62 +Net 389 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" + U1 U20 + U3 60 +Net 390 "/DDR Banks/M1_DQ11" "M1_DQ11" + U1 R22 + U3 59 +Net 391 "/DDR Banks/M1_DQ10" "M1_DQ10" + U1 R20 + U3 57 +Net 392 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" + U1 C17 + J1 2 +Net 393 "/Non volatile memories/SD_DAT2" "SD_DAT2" + U1 A17 + J1 1 +Net 394 "/FPGA Spartan6/SD_DAT1" "SD_DAT1" + U1 B18 + J1 8 +Net 395 "/Non volatile memories/SD_DAT0" "SD_DAT0" + J1 7 + U1 A18 +Net 396 "/FPGA Spartan6/M1_A7" "M1_A7" + U3 38 + U1 E20 +Net 397 "/FPGA Spartan6/M1_A6" "M1_A6" + U3 37 + U1 K19 +Net 398 "/DDR Banks/M1_A5" "M1_A5" + U3 36 + U1 K20 +Net 399 "/FPGA Spartan6/M1_A4" "M1_A4" + U1 F20 + U3 35 +Net 400 "/FPGA Spartan6/M1_A3" "M1_A3" + U1 G20 + U3 32 +Net 401 "/FPGA Spartan6/M1_A2" "M1_A2" + U3 31 + U1 E22 +Net 402 "/FPGA Spartan6/M1_A1" "M1_A1" + U1 F22 + U3 30 +Net 403 "/DDR Banks/M1_A0" "M1_A0" + U1 F21 + U3 29 +Net 404 "/FPGA Spartan6/M0_A12" "M0_A12" + U2 42 + U1 D1 +Net 405 "/FPGA Spartan6/M0_A11" "M0_A11" + U2 41 + U1 C1 +Net 406 "/FPGA Spartan6/M0_A10" "M0_A10" + U1 G4 + U2 28 +Net 407 "/FPGA Spartan6/M0_A9" "M0_A9" + U1 E1 + U2 40 +Net 408 "/FPGA Spartan6/M0_A8" "M0_A8" + U1 E3 + U2 39 +Net 409 "/FPGA Spartan6/M0_A7" "M0_A7" + U2 38 + U1 H6 +Net 410 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" + U3 56 + U1 P22 +Net 411 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" + U3 54 + U1 P21 +Net 412 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" + U3 13 + U1 K22 +Net 413 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" + U1 K21 + U3 11 +Net 414 "/DDR Banks/M1_DQ5" "M1_DQ5" + U3 10 + U1 J22 +Net 415 "/DDR Banks/M1_DQ4" "M1_DQ4" + U1 J20 + U3 8 +Net 416 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" + U3 7 + U1 M22 +Net 417 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" + U3 5 + U1 M21 +Net 418 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" + U1 N22 + U3 4 +Net 419 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" + U3 2 + U1 N20 +Net 420 "/FPGA Spartan6/M1_A12" "M1_A12" + U3 42 + U1 D22 +Net 421 "/FPGA Spartan6/M1_A11" "M1_A11" + U3 41 + U1 F19 +Net 422 "/DDR Banks/M1_A10" "M1_A10" + U3 28 + U1 G19 +Net 423 "/DDR Banks/M1_A9" "M1_A9" + U3 40 + U1 C22 +Net 424 "/FPGA Spartan6/M1_A8" "M1_A8" + U1 C20 + U3 39 +Net 425 "/DDR Banks/M0_DQ3" "M0_DQ3" + U2 7 + U1 M1 +Net 426 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" + U1 M2 + U2 5 +Net 427 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" + U2 4 + U1 N1 +Net 428 "/DDR Banks/M0_DQ0" "M0_DQ0" + U2 2 + U1 N3 +Net 429 "/FPGA Spartan6/M0_A6" "M0_A6" + U1 J4 + U2 37 +Net 430 "/FPGA Spartan6/M0_A5" "M0_A5" + U1 K3 + U2 36 +Net 431 "/FPGA Spartan6/M0_A4" "M0_A4" + U1 F3 + U2 35 +Net 432 "/FPGA Spartan6/M0_A3" "M0_A3" + U2 32 + U1 K6 +Net 433 "/DDR Banks/M0_A2" "M0_A2" + U2 31 + U1 H5 +Net 434 "/DDR Banks/M0_A1" "M0_A1" + U1 H1 + U2 30 +Net 435 "/FPGA Spartan6/M0_A0" "M0_A0" + U2 29 + U1 H2 +Net 436 "/DDR Banks/M0_DQ15" "M0_DQ15" + U2 65 + U1 V1 +Net 437 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" + U2 63 + U1 V2 +Net 438 "/DDR Banks/M0_DQ13" "M0_DQ13" + U2 62 + U1 U1 +Net 439 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" + U1 U3 + U2 60 +Net 440 "/DDR Banks/M0_DQ11" "M0_DQ11" + U2 59 + U1 R1 +Net 441 "/DDR Banks/M0_DQ10" "M0_DQ10" + U2 57 + U1 R3 +Net 442 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" + U1 P1 + U2 56 +Net 443 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" + U1 P2 + U2 54 +Net 444 "/DDR Banks/M0_DQ7" "M0_DQ7" + U2 13 + U1 K1 +Net 445 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" + U2 11 + U1 K2 +Net 446 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" + U1 J1 + U2 10 +Net 447 "/DDR Banks/M0_DQ4" "M0_DQ4" + U1 J3 + U2 8 +} +#End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 0416fa9..036dcaf 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Sat 14 Aug 2010 07:09:03 AM COT +update=Sat 14 Aug 2010 08:21:23 AM COT version=1 last_client=pcbnew [common] @@ -88,7 +88,7 @@ LibName39=atmel LibName40=contrib LibName41=valves LibName42=../library/pasives-connectors -LibName43=/home/afc/devel/Qi/xue/kicad/library/x25x64mb +LibName43=../library/x25x64mb [pcbnew] version=1 PadDrlX=0 diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index b999a06..3fca0a4 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 08:20:37 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001