diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index a06d792..8513531 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT +EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT LIBS:power LIBS:device LIBS:transistors @@ -45,9 +45,9 @@ Comment3 "" Comment4 "" $EndDescr Wire Bus Line - 10150 5100 10250 5100 + 10250 5100 10150 5100 Wire Bus Line - 10150 3150 10150 5100 + 10150 5100 10150 3150 Wire Bus Line 1900 4250 1900 5100 Wire Wire Line diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 20d63bf..0b75782 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT +EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT LIBS:power LIBS:device LIBS:transistors @@ -44,426 +44,872 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Text HLabel 1250 3300 0 60 BiDi ~ 0 +M0_DQ[0..15] +Wire Bus Line + 1350 4900 1350 3300 +Wire Bus Line + 1350 3300 1250 3300 Wire Wire Line - 10650 4400 10350 4400 + 3200 3700 2750 3700 Wire Wire Line - 10650 4300 10350 4300 + 3200 3500 2750 3500 Wire Wire Line - 7400 4700 7700 4700 -Connection ~ 7900 6300 + 14750 2150 14350 2150 Wire Wire Line - 7900 6350 7900 6300 -Connection ~ 7700 6300 + 14750 2250 14350 2250 Wire Wire Line - 7700 6350 7700 6300 -Connection ~ 7500 6300 + 14750 2450 14350 2450 Wire Wire Line - 7500 6350 7500 6300 -Connection ~ 7300 6300 + 14750 2650 14350 2650 Wire Wire Line - 7300 6350 7300 6300 + 14750 1550 14350 1550 Wire Wire Line - 7100 6350 7100 6300 -Connection ~ 13900 6300 + 14750 1650 14350 1650 Wire Wire Line - 13900 6350 13900 6300 -Connection ~ 13700 6300 + 14750 1950 14350 1950 Wire Wire Line - 13700 6300 13700 6350 -Connection ~ 13500 6300 + 14750 1850 14350 1850 Wire Wire Line - 13500 6350 13500 6300 -Connection ~ 14100 6300 + 14750 2350 14350 2350 Wire Wire Line - 14100 6350 14100 6300 + 14750 1750 14350 1750 Wire Wire Line - 14300 6350 14300 6300 + 14750 2050 14350 2050 Wire Wire Line - 14300 6300 13400 6300 + 14750 2550 14350 2550 Wire Wire Line - 13400 6300 13400 6350 -Connection ~ 13150 750 + 14750 2750 14350 2750 Wire Wire Line - 13150 800 13150 750 -Connection ~ 12950 750 + 15950 4850 15600 4850 Wire Wire Line - 12950 800 12950 750 -Connection ~ 12750 750 -Connection ~ 12550 750 + 12050 6950 12200 6950 Wire Wire Line - 12550 800 12550 750 + 7400 4800 7700 4800 +Connection ~ 8000 6300 Wire Wire Line - 13250 800 13250 750 + 8000 6350 8000 6300 +Connection ~ 7800 6300 Wire Wire Line - 13250 750 12350 750 + 7800 6350 7800 6300 +Connection ~ 7600 6300 Wire Wire Line - 12350 750 12350 800 -Connection ~ 5100 750 + 7600 6350 7600 6300 +Connection ~ 7400 6300 Wire Wire Line - 5100 800 5100 750 -Connection ~ 4900 750 + 7400 6350 7400 6300 +Connection ~ 7200 6300 Wire Wire Line - 4900 800 4900 750 -Connection ~ 5600 750 + 7200 6350 7200 6300 Wire Wire Line - 5600 800 5600 750 -Connection ~ 5400 750 + 8100 6350 8100 6300 Wire Wire Line - 5400 800 5400 750 + 8100 6300 7100 6300 +Connection ~ 13800 6300 Wire Wire Line - 5800 800 5800 750 + 13800 6350 13800 6300 +Connection ~ 13600 6300 Wire Wire Line - 5800 750 4800 750 + 13600 6350 13600 6300 +Connection ~ 14000 6300 Wire Wire Line - 4800 750 4800 800 -Connection ~ 16250 15550 + 14000 6350 14000 6300 +Connection ~ 14200 6300 Wire Wire Line - 16250 15450 16250 15550 -Connection ~ 16050 15550 -Wire Wire Line - 16050 15450 16050 15550 -Connection ~ 15850 15550 -Wire Wire Line - 15850 15450 15850 15550 -Connection ~ 15650 15550 -Wire Wire Line - 15650 15450 15650 15550 -Wire Wire Line - 15550 15450 15550 15550 -Connection ~ 15450 15550 -Connection ~ 14850 15550 -Wire Wire Line - 14850 15450 14850 15550 -Connection ~ 14650 15550 -Wire Wire Line - 14650 15450 14650 15550 -Connection ~ 14450 15550 -Wire Wire Line - 14450 15450 14450 15550 -Connection ~ 14250 15550 -Wire Wire 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+Text Label 1550 3600 0 60 ~ 0 +M0_DQ1 +Text Label 1550 3800 0 60 ~ 0 +M0_DQ3 +Text Label 1550 3700 0 60 ~ 0 +M0_DQ2 +Text Label 1550 3900 0 60 ~ 0 +M0_DQ4 +Text Label 1550 4000 0 60 ~ 0 +M0_DQ5 +Text Label 1550 4200 0 60 ~ 0 +M0_DQ7 +Text Label 1550 4100 0 60 ~ 0 +M0_DQ6 +Text Label 2750 5100 0 60 ~ 0 +M0_DQ6 +Text Label 2750 5200 0 60 ~ 0 +M0_DQ7 +Text Label 2750 5400 0 60 ~ 0 +M0_DQ5 +Text Label 2750 5300 0 60 ~ 0 +M0_DQ4 +Text Label 2750 4700 0 60 ~ 0 +M0_DQ2 +Text Label 2750 4800 0 60 ~ 0 +M0_DQ3 +Text Label 2750 4600 0 60 ~ 0 +M0_DQ1 +Text Label 2750 4500 0 60 ~ 0 +M0_DQ0 +Text Label 2750 4100 0 60 ~ 0 +M0_DQ10 +Text Label 2750 4200 0 60 ~ 0 +M0_DQ11 +Text Label 2750 4400 0 60 ~ 0 +M0_DQ9 +Text Label 2750 4300 0 60 ~ 0 +M0_DQ8 +Text Label 2750 3700 0 60 ~ 0 +M0_DQ12 +Text Label 2750 3800 0 60 ~ 0 +M0_DQ13 +Text Label 2750 3600 0 60 ~ 0 +M0_DQ15 +Text Label 2750 3500 0 60 ~ 0 +M0_DQ14 +Text Label 7450 4600 0 60 ~ 0 +M0_A0 +Text Label 7450 5100 0 60 ~ 0 +M0_A6 +Text Label 7450 5200 0 60 ~ 0 +M0_A5 +Text Label 7450 4100 0 60 ~ 0 +M0_A2 +Text Label 7450 4300 0 60 ~ 0 +M0_BA1 +Text Label 7450 4200 0 60 ~ 0 +M0_A7 +Text Label 7450 4400 0 60 ~ 0 +M0_BA0 +Text Label 7450 4500 0 60 ~ 0 +M0_A1 +Text Label 7450 3300 0 60 ~ 0 +M0_A12 +Text Label 7450 3100 0 60 ~ 0 +M0_A11 +Text Label 7450 3500 0 60 ~ 0 +M0_A9 +Text Label 7450 3600 0 60 ~ 0 +M0_A8 +Text Label 7450 3800 0 60 ~ 0 +M0_A10 +Text Label 7450 5000 0 60 ~ 0 +M0_A3 +Text Label 7450 3700 0 60 ~ 0 +M0_A4 +Text HLabel 8750 1650 0 60 Output ~ 0 +M0_A[0..12] +Text Label 9350 1800 0 60 ~ 0 +M0_A12 +Text Label 9350 1900 0 60 ~ 0 +M0_A11 +Text Label 9350 2200 0 60 ~ 0 +M0_A8 +Text Label 9350 2100 0 60 ~ 0 +M0_A9 +Text Label 9350 2600 0 60 ~ 0 +M0_A4 +Text Label 9350 2000 0 60 ~ 0 +M0_A10 +Text Label 9350 2300 0 60 ~ 0 +M0_A7 +Text Label 9350 2800 0 60 ~ 0 +M0_A2 +Text Label 9350 3000 0 60 ~ 0 +M0_A0 +Text Label 9350 2900 0 60 ~ 0 +M0_A1 +Text Label 9350 2700 0 60 ~ 0 +M0_A3 +Text Label 9350 2400 0 60 ~ 0 +M0_A6 +Text Label 9350 2500 0 60 ~ 0 +M0_A5 +Entry Wire Line + 9150 2900 9250 3000 +Entry Wire Line + 9150 2800 9250 2900 +Entry Wire Line + 9150 2700 9250 2800 +Entry Wire Line + 9150 2600 9250 2700 +Entry Wire Line + 9150 2500 9250 2600 +Entry Wire Line + 9150 2400 9250 2500 +Entry Wire Line + 9150 2300 9250 2400 +Entry Wire Line + 9150 2200 9250 2300 +Entry Wire Line + 9150 2100 9250 2200 +Entry Wire Line + 9150 2000 9250 2100 +Entry Wire Line + 9150 1900 9250 2000 +Entry Wire Line + 9150 1800 9250 1900 +Entry Wire Line + 9150 1700 9250 1800 +Entry Wire Line + 14250 1450 14350 1550 +Entry Wire Line + 14250 1550 14350 1650 +Entry Wire Line + 14250 1650 14350 1750 +Entry Wire Line + 14250 1750 14350 1850 +Entry Wire Line + 14250 1850 14350 1950 +Entry Wire Line + 14250 1950 14350 2050 +Entry Wire Line + 14250 2050 14350 2150 +Entry Wire Line + 14250 2150 14350 2250 +Entry Wire Line + 14250 2250 14350 2350 +Entry Wire Line + 14250 2350 14350 2450 +Entry Wire Line + 14250 2450 14350 2550 +Entry Wire Line + 14250 2550 14350 2650 +Entry Wire Line + 14250 2650 14350 2750 +Text Label 14450 2250 0 60 ~ 0 +M1_A5 +Text Label 14450 2150 0 60 ~ 0 +M1_A6 +Text Label 14450 2450 0 60 ~ 0 +M1_A3 +Text Label 14450 2650 0 60 ~ 0 +M1_A1 +Text Label 14450 2750 0 60 ~ 0 +M1_A0 +Text Label 14450 2550 0 60 ~ 0 +M1_A2 +Text Label 14450 2050 0 60 ~ 0 +M1_A7 +Text Label 14450 1750 0 60 ~ 0 +M1_A10 +Text Label 14450 2350 0 60 ~ 0 +M1_A4 +Text Label 14450 1850 0 60 ~ 0 +M1_A9 +Text Label 14450 1950 0 60 ~ 0 +M1_A8 +Text Label 14450 1650 0 60 ~ 0 +M1_A11 +Text Label 14450 1550 0 60 ~ 0 +M1_A12 +Text Label 15550 5250 0 60 ~ 0 +M1_A6 +Text Label 15550 5150 0 60 ~ 0 +M1_A5 +Text Label 15550 4950 0 60 ~ 0 +M1_A3 +Text Label 15550 3450 0 60 ~ 0 +M1_A12 +Text Label 15550 3250 0 60 ~ 0 +M1_A11 +Text Label 15550 3550 0 60 ~ 0 +M1_A8 +Text Label 15550 3650 0 60 ~ 0 +M1_A9 +Text Label 15550 3850 0 60 ~ 0 +M1_A4 +Text Label 15550 3750 0 60 ~ 0 +M1_A10 +Text Label 15550 4150 0 60 ~ 0 +M1_A7 +Text Label 15550 4250 0 60 ~ 0 +M1_A2 +Text Label 15550 4650 0 60 ~ 0 +M1_A1 +Text Label 15550 4550 0 60 ~ 0 +M1_A0 +Text HLabel 13850 1400 0 60 Output ~ 0 +M1_A[0..12] Text HLabel 12050 6950 0 60 Input ~ 0 ETH_INT -Text HLabel 10350 4300 0 60 Output ~ 0 +Text HLabel 15600 4750 0 60 Output ~ 0 M1_CLK -Text HLabel 10350 4400 0 60 Output ~ 0 +Text HLabel 15600 4850 0 60 Output ~ 0 M1_CLK# Text HLabel 7700 4800 2 60 Output ~ 0 M0_CLK @@ -508,10 +954,10 @@ $EndComp $Comp L XC6SLX45FGG484 U1 U 1 1 4C431E37 -P 12850 3200 -F 0 "U1" H 12850 3300 70 0000 C CNN -F 1 "XC6SLX45FGG484" H 12850 3100 70 0000 C CNN - 1 12850 3200 +P 18150 3650 +F 0 "U1" H 18150 3750 70 0000 C CNN +F 1 "XC6SLX45FGG484" H 18150 3550 70 0000 C CNN + 1 18150 3650 1 0 0 -1 $EndComp $Comp diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 000c08a..d07d6cb 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT +EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT LIBS:power LIBS:device LIBS:transistors diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 131f385..3557baa 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT +EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT LIBS:power LIBS:device LIBS:transistors diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index fb4a56b..a351a89 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Tue 03 Aug 2010 09:21:21 PM COT +EESchema-LIBRARY Version 2.3 Date: Wed 04 Aug 2010 12:20:40 PM COT # # GND # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 278435e..f5d91ff 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Tue 03 Aug 2010 09:08:55 PM COT +PCBNEW-BOARD Version 1 date Wed 04 Aug 2010 12:21:45 PM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -6,15 +6,15 @@ $GENERAL LayerCount 4 Ly 1FFF8007 EnabledLayers 1FFF8007 -Links 183 -NoConn 183 -Di 28207 5405 54077 31125 +Links 225 +NoConn 225 +Di 28232 5405 47187 31125 Ndraw 0 Ntrack 0 Nzone 0 BoardThickness 630 Nmodule 6 -Nnets 19 +Nnets 61 $EndGENERAL $SHEETDESCR @@ -68,75 +68,243 @@ Na 0 "" St ~ $EndEQUIPOT $EQUIPOT -Na 1 "/DDR_Banks/M0_CLK" +Na 1 "/DDR_Banks/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 2 "/DDR_Banks/M0_CLK#" +Na 2 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 3 "/DDR_Banks/M1_CLK" +Na 3 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 4 "/Ethernet_Phy/ETH_INT" +Na 4 "/DDR_Banks/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/FPGA_Spartan6/M1_CLK#" +Na 5 "/DDR_Banks/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/Non_volatile_memories/FRB_N" +Na 6 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "3.3V" +Na 7 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "GND" +Na 8 "/DDR_Banks/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "N-000030" +Na 9 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "N-000036" +Na 10 "/DDR_Banks/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "N-000108" +Na 11 "/DDR_Banks/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "N-000109" +Na 12 "/DDR_Banks/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "N-000110" +Na 13 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "N-000111" +Na 14 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "N-000112" +Na 15 "/FPGA_Spartan6/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "N-000113" +Na 16 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "N-000453" +Na 17 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "N-000454" +Na 18 "/FPGA_Spartan6/M0_A12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 19 "/FPGA_Spartan6/M0_A2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 20 "/FPGA_Spartan6/M0_A3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 21 "/FPGA_Spartan6/M0_A4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 22 "/FPGA_Spartan6/M0_A5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 23 "/FPGA_Spartan6/M0_A6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 24 "/FPGA_Spartan6/M0_A7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 25 "/FPGA_Spartan6/M0_A9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 26 "/FPGA_Spartan6/M0_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 27 "/FPGA_Spartan6/M0_DQ0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 28 "/FPGA_Spartan6/M0_DQ10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 29 "/FPGA_Spartan6/M0_DQ11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 30 "/FPGA_Spartan6/M0_DQ12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 31 "/FPGA_Spartan6/M0_DQ13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 32 "/FPGA_Spartan6/M0_DQ14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 33 "/FPGA_Spartan6/M0_DQ15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 34 "/FPGA_Spartan6/M0_DQ3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 35 "/FPGA_Spartan6/M0_DQ5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 36 "/FPGA_Spartan6/M0_DQ6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 37 "/FPGA_Spartan6/M0_DQ7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 38 "/FPGA_Spartan6/M0_DQ8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 39 "/FPGA_Spartan6/M0_DQ9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 40 "/FPGA_Spartan6/M1_A10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 41 "/FPGA_Spartan6/M1_A11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 42 "/FPGA_Spartan6/M1_A2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 43 "/FPGA_Spartan6/M1_A4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 44 "/FPGA_Spartan6/M1_A5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 45 "/FPGA_Spartan6/M1_A7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 46 "/FPGA_Spartan6/M1_A8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 47 "/FPGA_Spartan6/M1_CLK#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 48 "/Non_volatile_memories/FRB_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 49 "3.3V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 50 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 51 "N-000036" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 52 "N-000040" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 53 "N-000130" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 54 "N-000138" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 55 "N-000169" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 56 "N-000170" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 57 "N-000171" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 58 "N-000172" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 59 "N-000411" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 60 "N-000412" St ~ $EndEQUIPOT $NCLASS @@ -149,24 +317,66 @@ ViaDrill 250 uViaDia 200 uViaDrill 50 AddNet "" -AddNet "/DDR_Banks/M0_CLK" +AddNet "/DDR_Banks/M0_A1" +AddNet "/DDR_Banks/M0_A8" AddNet "/DDR_Banks/M0_CLK#" +AddNet "/DDR_Banks/M0_DQ1" +AddNet "/DDR_Banks/M0_DQ2" +AddNet "/DDR_Banks/M0_DQ4" +AddNet "/DDR_Banks/M1_A0" +AddNet "/DDR_Banks/M1_A1" +AddNet "/DDR_Banks/M1_A12" +AddNet "/DDR_Banks/M1_A3" +AddNet "/DDR_Banks/M1_A6" +AddNet "/DDR_Banks/M1_A9" AddNet "/DDR_Banks/M1_CLK" AddNet "/Ethernet_Phy/ETH_INT" +AddNet "/FPGA_Spartan6/M0_A0" +AddNet "/FPGA_Spartan6/M0_A10" +AddNet "/FPGA_Spartan6/M0_A11" +AddNet "/FPGA_Spartan6/M0_A12" +AddNet "/FPGA_Spartan6/M0_A2" +AddNet "/FPGA_Spartan6/M0_A3" +AddNet "/FPGA_Spartan6/M0_A4" +AddNet "/FPGA_Spartan6/M0_A5" +AddNet "/FPGA_Spartan6/M0_A6" +AddNet "/FPGA_Spartan6/M0_A7" +AddNet "/FPGA_Spartan6/M0_A9" +AddNet "/FPGA_Spartan6/M0_CLK" +AddNet "/FPGA_Spartan6/M0_DQ0" +AddNet "/FPGA_Spartan6/M0_DQ10" +AddNet "/FPGA_Spartan6/M0_DQ11" +AddNet "/FPGA_Spartan6/M0_DQ12" +AddNet "/FPGA_Spartan6/M0_DQ13" +AddNet "/FPGA_Spartan6/M0_DQ14" +AddNet "/FPGA_Spartan6/M0_DQ15" +AddNet "/FPGA_Spartan6/M0_DQ3" +AddNet "/FPGA_Spartan6/M0_DQ5" +AddNet "/FPGA_Spartan6/M0_DQ6" +AddNet "/FPGA_Spartan6/M0_DQ7" +AddNet "/FPGA_Spartan6/M0_DQ8" +AddNet "/FPGA_Spartan6/M0_DQ9" +AddNet "/FPGA_Spartan6/M1_A10" +AddNet "/FPGA_Spartan6/M1_A11" +AddNet "/FPGA_Spartan6/M1_A2" +AddNet "/FPGA_Spartan6/M1_A4" +AddNet "/FPGA_Spartan6/M1_A5" +AddNet "/FPGA_Spartan6/M1_A7" +AddNet "/FPGA_Spartan6/M1_A8" AddNet "/FPGA_Spartan6/M1_CLK#" AddNet "/Non_volatile_memories/FRB_N" AddNet "3.3V" AddNet "GND" -AddNet "N-000030" AddNet "N-000036" -AddNet "N-000108" -AddNet "N-000109" -AddNet "N-000110" -AddNet "N-000111" -AddNet "N-000112" -AddNet "N-000113" -AddNet "N-000453" -AddNet "N-000454" +AddNet "N-000040" +AddNet "N-000130" +AddNet "N-000138" +AddNet "N-000169" +AddNet "N-000170" +AddNet "N-000171" +AddNet "N-000172" +AddNet "N-000411" +AddNet "N-000412" $EndNCLASS $MODULE FGG484bga-p10 Po 38000 14500 0 15 4C4325AE 4C4328D9 ~~ @@ -189,7 +399,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -4133 -4133 $EndPAD $PAD @@ -217,7 +427,7 @@ $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/Ethernet_Phy/ETH_INT" +Ne 14 "/Ethernet_Phy/ETH_INT" Po -2558 -4133 $EndPAD $PAD @@ -336,7 +546,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 4133 -4133 $EndPAD $PAD @@ -364,14 +574,14 @@ $PAD Sh "B4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "N-000109" +Ne 54 "N-000138" Po -2952 -3739 $EndPAD $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -2558 -3739 $EndPAD $PAD @@ -385,7 +595,7 @@ $PAD Sh "B7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "N-000109" +Ne 54 "N-000138" Po -1771 -3739 $EndPAD $PAD @@ -399,7 +609,7 @@ $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -983 -3739 $EndPAD $PAD @@ -413,7 +623,7 @@ $PAD Sh "B11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "N-000109" +Ne 54 "N-000138" Po -196 -3739 $EndPAD $PAD @@ -427,7 +637,7 @@ $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 590 -3739 $EndPAD $PAD @@ -441,7 +651,7 @@ $PAD Sh "B15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "N-000109" +Ne 54 "N-000138" Po 1377 -3739 $EndPAD $PAD @@ -455,7 +665,7 @@ $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 2165 -3739 $EndPAD $PAD @@ -469,7 +679,7 @@ $PAD Sh "B19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "N-000109" +Ne 54 "N-000138" Po 2952 -3739 $EndPAD $PAD @@ -497,14 +707,14 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 17 "/FPGA_Spartan6/M0_A11" Po -4133 -3346 $EndPAD $PAD Sh "C2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -3739 -3346 $EndPAD $PAD @@ -630,28 +840,28 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 46 "/FPGA_Spartan6/M1_A8" Po 3346 -3346 $EndPAD $PAD Sh "C21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "N-000110" +Ne 53 "N-000130" Po 3739 -3346 $EndPAD $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 12 "/DDR_Banks/M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 18 "/FPGA_Spartan6/M0_A12" Po -4133 -2952 $EndPAD $PAD @@ -672,7 +882,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -2952 -2952 $EndPAD $PAD @@ -756,7 +966,7 @@ $PAD Sh "D16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po 1771 -2952 $EndPAD $PAD @@ -770,7 +980,7 @@ $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 2558 -2952 $EndPAD $PAD @@ -798,28 +1008,28 @@ $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 9 "/DDR_Banks/M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 25 "/FPGA_Spartan6/M0_A9" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 2 "/DDR_Banks/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -847,7 +1057,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -1771 -2558 $EndPAD $PAD @@ -861,7 +1071,7 @@ $PAD Sh "E9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "N-000109" +Ne 54 "N-000138" Po -983 -2558 $EndPAD $PAD @@ -875,7 +1085,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -196 -2558 $EndPAD $PAD @@ -889,7 +1099,7 @@ $PAD Sh "E13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "N-000109" +Ne 54 "N-000138" Po 590 -2558 $EndPAD $PAD @@ -903,7 +1113,7 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 1377 -2558 $EndPAD $PAD @@ -917,7 +1127,7 @@ $PAD Sh "E17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "N-000109" +Ne 54 "N-000138" Po 2165 -2558 $EndPAD $PAD @@ -931,28 +1141,28 @@ $PAD Sh "E19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "N-000110" +Ne 53 "N-000130" Po 2952 -2558 $EndPAD $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 45 "/FPGA_Spartan6/M1_A7" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 42 "/FPGA_Spartan6/M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -973,14 +1183,14 @@ $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 21 "/FPGA_Spartan6/M0_A4" Po -3346 -2165 $EndPAD $PAD Sh "F4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -2952 -2165 $EndPAD $PAD @@ -994,7 +1204,7 @@ $PAD Sh "F6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -2165 -2165 $EndPAD $PAD @@ -1029,7 +1239,7 @@ $PAD Sh "F11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po -196 -2165 $EndPAD $PAD @@ -1085,28 +1295,28 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 41 "/FPGA_Spartan6/M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 43 "/FPGA_Spartan6/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 7 "/DDR_Banks/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 8 "/DDR_Banks/M1_A1" Po 4133 -2165 $EndPAD $PAD @@ -1120,7 +1330,7 @@ $PAD Sh "G2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -3739 -1771 $EndPAD $PAD @@ -1134,14 +1344,14 @@ $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 16 "/FPGA_Spartan6/M0_A10" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -2558 -1771 $EndPAD $PAD @@ -1176,7 +1386,7 @@ $PAD Sh "G10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "N-000109" +Ne 54 "N-000138" Po -590 -1771 $EndPAD $PAD @@ -1190,7 +1400,7 @@ $PAD Sh "G12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po 196 -1771 $EndPAD $PAD @@ -1204,7 +1414,7 @@ $PAD Sh "G14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "N-000109" +Ne 54 "N-000138" Po 983 -1771 $EndPAD $PAD @@ -1232,28 +1442,28 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 40 "/FPGA_Spartan6/M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 10 "/DDR_Banks/M1_A3" Po 3346 -1771 $EndPAD $PAD Sh "G21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "N-000110" +Ne 53 "N-000130" Po 3739 -1771 $EndPAD $PAD @@ -1267,49 +1477,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 1 "/DDR_Banks/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 15 "/FPGA_Spartan6/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/DDR_Banks/M0_CLK#" +Ne 3 "/DDR_Banks/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "/DDR_Banks/M0_CLK" +Ne 26 "/FPGA_Spartan6/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 19 "/FPGA_Spartan6/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 24 "/FPGA_Spartan6/M0_A7" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -1771 -1377 $EndPAD $PAD @@ -1323,7 +1533,7 @@ $PAD Sh "H9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po -983 -1377 $EndPAD $PAD @@ -1365,7 +1575,7 @@ $PAD Sh "H15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po 1377 -1377 $EndPAD $PAD @@ -1400,7 +1610,7 @@ $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/DDR_Banks/M1_CLK" +Ne 13 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD @@ -1421,35 +1631,35 @@ $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 35 "/FPGA_Spartan6/M0_DQ5" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 6 "/DDR_Banks/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 23 "/FPGA_Spartan6/M0_A6" Po -2952 -983 $EndPAD $PAD Sh "J5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -2558 -983 $EndPAD $PAD @@ -1470,56 +1680,56 @@ $PAD Sh "J8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po -1377 -983 $EndPAD $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -983 -983 $EndPAD $PAD Sh "J10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po -590 -983 $EndPAD $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -196 -983 $EndPAD $PAD Sh "J12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po 196 -983 $EndPAD $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 590 -983 $EndPAD $PAD Sh "J14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po 983 -983 $EndPAD $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 1377 -983 $EndPAD $PAD @@ -1540,14 +1750,14 @@ $PAD Sh "J18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "N-000110" +Ne 53 "N-000130" Po 2558 -983 $EndPAD $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/FPGA_Spartan6/M1_CLK#" +Ne 47 "/FPGA_Spartan6/M1_CLK#" Po 2952 -983 $EndPAD $PAD @@ -1561,7 +1771,7 @@ $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 3739 -983 $EndPAD $PAD @@ -1575,21 +1785,21 @@ $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 37 "/FPGA_Spartan6/M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 36 "/FPGA_Spartan6/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 22 "/FPGA_Spartan6/M0_A5" Po -3346 -590 $EndPAD $PAD @@ -1610,7 +1820,7 @@ $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 20 "/FPGA_Spartan6/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -1631,49 +1841,49 @@ $PAD Sh "K9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po -983 -590 $EndPAD $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -590 -590 $EndPAD $PAD Sh "K11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po -196 -590 $EndPAD $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 196 -590 $EndPAD $PAD Sh "K13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po 590 -590 $EndPAD $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 983 -590 $EndPAD $PAD Sh "K15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po 1377 -590 $EndPAD $PAD @@ -1701,14 +1911,14 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 11 "/DDR_Banks/M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 44 "/FPGA_Spartan6/M1_A5" Po 3346 -590 $EndPAD $PAD @@ -1736,7 +1946,7 @@ $PAD Sh "L2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -3739 -196 $EndPAD $PAD @@ -1757,7 +1967,7 @@ $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -2558 -196 $EndPAD $PAD @@ -1771,56 +1981,56 @@ $PAD Sh "L7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -1771 -196 $EndPAD $PAD Sh "L8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po -1377 -196 $EndPAD $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -983 -196 $EndPAD $PAD Sh "L10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po -590 -196 $EndPAD $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -196 -196 $EndPAD $PAD Sh "L12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po 196 -196 $EndPAD $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 590 -196 $EndPAD $PAD Sh "L14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po 983 -196 $EndPAD $PAD @@ -1834,7 +2044,7 @@ $PAD Sh "L16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "N-000110" +Ne 53 "N-000130" Po 1771 -196 $EndPAD $PAD @@ -1848,7 +2058,7 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 2558 -196 $EndPAD $PAD @@ -1869,7 +2079,7 @@ $PAD Sh "L21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "N-000110" +Ne 53 "N-000130" Po 3739 -196 $EndPAD $PAD @@ -1883,14 +2093,14 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 34 "/FPGA_Spartan6/M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 5 "/DDR_Banks/M0_DQ2" Po -3739 196 $EndPAD $PAD @@ -1939,49 +2149,49 @@ $PAD Sh "M9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po -983 196 $EndPAD $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -590 196 $EndPAD $PAD Sh "M11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po -196 196 $EndPAD $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 196 196 $EndPAD $PAD Sh "M13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po 590 196 $EndPAD $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 983 196 $EndPAD $PAD Sh "M15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po 1377 196 $EndPAD $PAD @@ -2037,21 +2247,21 @@ $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 4 "/DDR_Banks/M0_DQ1" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 27 "/FPGA_Spartan6/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -2065,7 +2275,7 @@ $PAD Sh "N5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -2558 590 $EndPAD $PAD @@ -2086,49 +2296,49 @@ $PAD Sh "N8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po -1377 590 $EndPAD $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -983 590 $EndPAD $PAD Sh "N10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po -590 590 $EndPAD $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -196 590 $EndPAD $PAD Sh "N12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po 196 590 $EndPAD $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 590 590 $EndPAD $PAD Sh "N14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po 983 590 $EndPAD $PAD @@ -2149,14 +2359,14 @@ $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 2165 590 $EndPAD $PAD Sh "N18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "N-000110" +Ne 53 "N-000130" Po 2558 590 $EndPAD $PAD @@ -2177,7 +2387,7 @@ $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 3739 590 $EndPAD $PAD @@ -2191,14 +2401,14 @@ $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 39 "/FPGA_Spartan6/M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 38 "/FPGA_Spartan6/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -2247,42 +2457,42 @@ $PAD Sh "P9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po -983 983 $EndPAD $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -590 983 $EndPAD $PAD Sh "P11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po -196 983 $EndPAD $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 196 983 $EndPAD $PAD Sh "P13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po 590 983 $EndPAD $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 983 983 $EndPAD $PAD @@ -2345,21 +2555,21 @@ $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 29 "/FPGA_Spartan6/M0_DQ11" Po -4133 1377 $EndPAD $PAD Sh "R2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -3739 1377 $EndPAD $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 28 "/FPGA_Spartan6/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -2373,14 +2583,14 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -2558 1377 $EndPAD $PAD Sh "R6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po -2165 1377 $EndPAD $PAD @@ -2408,7 +2618,7 @@ $PAD Sh "R10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po -590 1377 $EndPAD $PAD @@ -2422,7 +2632,7 @@ $PAD Sh "R12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po 196 1377 $EndPAD $PAD @@ -2436,7 +2646,7 @@ $PAD Sh "R14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "N-000113" +Ne 57 "N-000171" Po 983 1377 $EndPAD $PAD @@ -2464,7 +2674,7 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 2558 1377 $EndPAD $PAD @@ -2485,7 +2695,7 @@ $PAD Sh "R21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "N-000110" +Ne 53 "N-000130" Po 3739 1377 $EndPAD $PAD @@ -2555,7 +2765,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po -983 1771 $EndPAD $PAD @@ -2583,7 +2793,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po 590 1771 $EndPAD $PAD @@ -2653,21 +2863,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 31 "/FPGA_Spartan6/M0_DQ13" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 30 "/FPGA_Spartan6/M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -2681,7 +2891,7 @@ $PAD Sh "U5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -2558 2165 $EndPAD $PAD @@ -2695,7 +2905,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -1771 2165 $EndPAD $PAD @@ -2723,7 +2933,7 @@ $PAD Sh "U11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po -196 2165 $EndPAD $PAD @@ -2772,7 +2982,7 @@ $PAD Sh "U18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "N-000110" +Ne 53 "N-000130" Po 2558 2165 $EndPAD $PAD @@ -2793,7 +3003,7 @@ $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 3739 2165 $EndPAD $PAD @@ -2807,14 +3017,14 @@ $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 33 "/FPGA_Spartan6/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 32 "/FPGA_Spartan6/M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -2828,7 +3038,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -2952 2558 $EndPAD $PAD @@ -2842,7 +3052,7 @@ $PAD Sh "V6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "N-000112" +Ne 58 "N-000172" Po -2165 2558 $EndPAD $PAD @@ -2856,7 +3066,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po -1377 2558 $EndPAD $PAD @@ -2870,7 +3080,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -590 2558 $EndPAD $PAD @@ -2884,7 +3094,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po 196 2558 $EndPAD $PAD @@ -2898,7 +3108,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 983 2558 $EndPAD $PAD @@ -2912,7 +3122,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po 1771 2558 $EndPAD $PAD @@ -2968,7 +3178,7 @@ $PAD Sh "W2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "N-000111" +Ne 56 "N-000170" Po -3739 2952 $EndPAD $PAD @@ -2989,7 +3199,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po -2558 2952 $EndPAD $PAD @@ -3003,7 +3213,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -1771 2952 $EndPAD $PAD @@ -3066,7 +3276,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 1771 2952 $EndPAD $PAD @@ -3087,7 +3297,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 2952 2952 $EndPAD $PAD @@ -3101,7 +3311,7 @@ $PAD Sh "W21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "N-000110" +Ne 53 "N-000130" Po 3739 2952 $EndPAD $PAD @@ -3283,7 +3493,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po -3346 3739 $EndPAD $PAD @@ -3297,7 +3507,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -2558 3739 $EndPAD $PAD @@ -3311,7 +3521,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po -1771 3739 $EndPAD $PAD @@ -3325,7 +3535,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -983 3739 $EndPAD $PAD @@ -3339,7 +3549,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po -196 3739 $EndPAD $PAD @@ -3353,7 +3563,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 590 3739 $EndPAD $PAD @@ -3367,7 +3577,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po 1377 3739 $EndPAD $PAD @@ -3381,7 +3591,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 2165 3739 $EndPAD $PAD @@ -3395,7 +3605,7 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "N-000108" +Ne 55 "N-000169" Po 2952 3739 $EndPAD $PAD @@ -3423,7 +3633,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -4133 4133 $EndPAD $PAD @@ -3570,7 +3780,7 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 @@ -3592,7 +3802,7 @@ $PAD Sh "12" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "N-000453" +Ne 59 "N-000411" Po -1613 1082 $EndPAD $PAD @@ -3620,14 +3830,14 @@ $PAD Sh "8" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "N-000453" +Ne 59 "N-000411" Po -1613 295 $EndPAD $PAD Sh "7" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "N-000454" +Ne 60 "N-000412" Po -1613 98 $EndPAD $PAD @@ -3683,7 +3893,7 @@ $PAD Sh "47" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "N-000454" +Ne 60 "N-000412" Po -885 -1613 $EndPAD $PAD @@ -3704,7 +3914,7 @@ $PAD Sh "44" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "N-000453" +Ne 59 "N-000411" Po -295 -1613 $EndPAD $PAD @@ -3739,14 +3949,14 @@ $PAD Sh "39" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "N-000453" +Ne 59 "N-000411" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "N-000454" +Ne 60 "N-000412" Po 885 -1613 $EndPAD $PAD @@ -3760,7 +3970,7 @@ $PAD Sh "25" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/Ethernet_Phy/ETH_INT" +Ne 14 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD @@ -3802,7 +4012,7 @@ $PAD Sh "31" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "N-000454" +Ne 60 "N-000412" Po 1613 -98 $EndPAD $PAD @@ -3830,21 +4040,21 @@ $PAD Sh "35" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "N-000453" +Ne 59 "N-000411" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "N-000453" +Ne 59 "N-000411" Po 1613 -1082 $EndPAD $PAD Sh "13" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "N-000454" +Ne 60 "N-000412" Po -1082 1613 $EndPAD $PAD @@ -3914,14 +4124,14 @@ $PAD Sh "23" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "N-000453" +Ne 59 "N-000411" Po 885 1613 $EndPAD $PAD Sh "24" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "N-000454" +Ne 60 "N-000412" Po 1082 1613 $EndPAD $EndMODULE LQFP48 @@ -4014,7 +4224,7 @@ $PAD Sh "CASE" R 620 540 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 8 "GND" +Ne 50 "GND" Po 2690 -200 $EndPAD $PAD @@ -4035,21 +4245,21 @@ $PAD Sh "CASE" R 460 860 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 8 "GND" +Ne 50 "GND" Po 3050 -3980 $EndPAD $PAD Sh "CASE" R 460 860 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 8 "GND" +Ne 50 "GND" Po -3050 -3980 $EndPAD $PAD Sh "COM" R 460 540 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 8 "GND" +Ne 50 "GND" Po -3060 -200 $EndPAD $EndMODULE MICROSD @@ -4313,14 +4523,14 @@ $PAD Sh "6" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/Non_volatile_memories/FRB_N" +Ne 48 "/Non_volatile_memories/FRB_N" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/Non_volatile_memories/FRB_N" +Ne 48 "/Non_volatile_memories/FRB_N" Po -1090 3850 $EndPAD $PAD @@ -4355,14 +4565,14 @@ $PAD Sh "12" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "3.3V" +Ne 49 "3.3V" Po -100 3850 $EndPAD $PAD Sh "13" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 100 3850 $EndPAD $PAD @@ -4404,7 +4614,7 @@ $PAD Sh "19" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "3.3V" +Ne 49 "3.3V" Po 1280 3850 $EndPAD $PAD @@ -4523,14 +4733,14 @@ $PAD Sh "36" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 100 -3850 $EndPAD $PAD Sh "37" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "3.3V" +Ne 49 "3.3V" Po -100 -3850 $EndPAD $PAD @@ -4612,442 +4822,442 @@ Po -2270 -3850 $EndPAD $EndMODULE NAND-48TSOP $MODULE 60fbga_ddr -Po 30315 11614 0 15 4C58C755 4C58CB97 ~~ +Po 30906 13780 1800 15 4C58C755 4C58CB97 ~~ Li 60fbga_ddr Sc 4C58CB97 AR /4C421DD3/4C58C847 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"U2" -T1 0 150 200 200 0 40 N I 25 N"MT46V32M16FN" +T0 0 -150 200 200 1800 40 N V 25 N"U2" +T1 0 150 200 200 1800 40 N I 25 N"MT46V32M16FN" DC -1771 -2283 -1771 -2362 39 21 DS -1968 2460 -1968 -2460 39 21 DS -1968 -2460 1968 -2460 39 21 DS 1968 -2460 1968 2460 39 21 DS 1968 2460 -1968 2460 39 21 $PAD -Sh "A1" O 157 158 0 0 0 +Sh "A1" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -1259 -2165 $EndPAD $PAD -Sh "A9" O 157 158 0 0 0 +Sh "A9" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 10 "N-000036" +Ne 52 "N-000040" Po 1259 -2165 $EndPAD $PAD -Sh "B1" O 157 158 0 0 0 +Sh "B1" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 32 "/FPGA_Spartan6/M0_DQ14" Po -1259 -1771 $EndPAD $PAD -Sh "B9" O 157 158 0 0 0 +Sh "B9" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 4 "/DDR_Banks/M0_DQ1" Po 1259 -1771 $EndPAD $PAD -Sh "C1" O 157 157 0 0 0 +Sh "C1" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 30 "/FPGA_Spartan6/M0_DQ12" Po -1259 -1377 $EndPAD $PAD -Sh "C9" O 157 157 0 0 0 +Sh "C9" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 34 "/FPGA_Spartan6/M0_DQ3" Po 1259 -1377 $EndPAD $PAD -Sh "D1" O 157 157 0 0 0 +Sh "D1" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 28 "/FPGA_Spartan6/M0_DQ10" Po -1259 -983 $EndPAD $PAD -Sh "D9" O 157 157 0 0 0 +Sh "D9" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 35 "/FPGA_Spartan6/M0_DQ5" Po 1259 -983 $EndPAD $PAD -Sh "E1" O 157 158 0 0 0 +Sh "E1" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 38 "/FPGA_Spartan6/M0_DQ8" Po -1259 -590 $EndPAD $PAD -Sh "E9" O 157 158 0 0 0 +Sh "E9" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 37 "/FPGA_Spartan6/M0_DQ7" Po 1259 -590 $EndPAD $PAD -Sh "F1" O 157 157 0 0 0 +Sh "F1" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -1259 -196 $EndPAD $PAD -Sh "F9" O 157 157 0 0 0 +Sh "F9" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1259 -196 $EndPAD $PAD -Sh "A2" O 157 158 0 0 0 +Sh "A2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 33 "/FPGA_Spartan6/M0_DQ15" Po -944 -2165 $EndPAD $PAD -Sh "A3" O 157 158 0 0 0 +Sh "A3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -629 -2165 $EndPAD $PAD -Sh "A7" O 157 158 0 0 0 +Sh "A7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 10 "N-000036" +Ne 52 "N-000040" Po 629 -2165 $EndPAD $PAD -Sh "A8" O 157 158 0 0 0 +Sh "A8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 27 "/FPGA_Spartan6/M0_DQ0" Po 944 -2165 $EndPAD $PAD -Sh "B2" O 157 158 0 0 0 +Sh "B2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 10 "N-000036" +Ne 52 "N-000040" Po -944 -1771 $EndPAD $PAD -Sh "B3" O 157 158 0 0 0 +Sh "B3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 31 "/FPGA_Spartan6/M0_DQ13" Po -629 -1771 $EndPAD $PAD -Sh "B7" O 157 158 0 0 0 +Sh "B7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 5 "/DDR_Banks/M0_DQ2" Po 629 -1771 $EndPAD $PAD -Sh "B8" O 157 158 0 0 0 +Sh "B8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 944 -1771 $EndPAD $PAD -Sh "C2" O 157 157 0 0 0 +Sh "C2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -944 -1377 $EndPAD $PAD -Sh "C3" O 157 157 0 0 0 +Sh "C3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 29 "/FPGA_Spartan6/M0_DQ11" Po -629 -1377 $EndPAD $PAD -Sh "C7" O 157 157 0 0 0 +Sh "C7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 6 "/DDR_Banks/M0_DQ4" Po 629 -1377 $EndPAD $PAD -Sh "C8" O 157 157 0 0 0 +Sh "C8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 10 "N-000036" +Ne 52 "N-000040" Po 944 -1377 $EndPAD $PAD -Sh "D2" O 157 157 0 0 0 +Sh "D2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 10 "N-000036" +Ne 52 "N-000040" Po -944 -983 $EndPAD $PAD -Sh "D3" O 157 157 0 0 0 +Sh "D3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 39 "/FPGA_Spartan6/M0_DQ9" Po -629 -983 $EndPAD $PAD -Sh "D7" O 157 157 0 0 0 +Sh "D7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 36 "/FPGA_Spartan6/M0_DQ6" Po 629 -983 $EndPAD $PAD -Sh "D8" O 157 157 0 0 0 +Sh "D8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 944 -983 $EndPAD $PAD -Sh "E2" O 157 158 0 0 0 +Sh "E2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -944 -590 $EndPAD $PAD -Sh "E3" O 157 158 0 0 0 +Sh "E3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -629 -590 $EndPAD $PAD -Sh "E7" O 157 158 0 0 0 +Sh "E7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 629 -590 $EndPAD $PAD -Sh "E8" O 157 158 0 0 0 +Sh "E8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 10 "N-000036" +Ne 52 "N-000040" Po 944 -590 $EndPAD $PAD -Sh "F2" O 157 157 0 0 0 +Sh "F2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -944 -196 $EndPAD $PAD -Sh "F3" O 157 157 0 0 0 +Sh "F3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -629 -196 $EndPAD $PAD -Sh "F7" O 157 157 0 0 0 +Sh "F7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 629 -196 $EndPAD $PAD -Sh "F8" O 157 157 0 0 0 +Sh "F8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 10 "N-000036" +Ne 52 "N-000040" Po 944 -196 $EndPAD $PAD -Sh "G2" O 157 157 0 0 0 +Sh "G2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 1 "/DDR_Banks/M0_CLK" +Ne 26 "/FPGA_Spartan6/M0_CLK" Po -944 196 $EndPAD $PAD -Sh "G3" O 157 157 0 0 0 +Sh "G3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/DDR_Banks/M0_CLK#" +Ne 3 "/DDR_Banks/M0_CLK#" Po -629 196 $EndPAD $PAD -Sh "G7" O 157 157 0 0 0 +Sh "G7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 629 196 $EndPAD $PAD -Sh "G8" O 157 157 0 0 0 +Sh "G8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 944 196 $EndPAD $PAD -Sh "H2" O 157 158 0 0 0 +Sh "H2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 18 "/FPGA_Spartan6/M0_A12" Po -944 590 $EndPAD $PAD -Sh "H3" O 157 158 0 0 0 +Sh "H3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -629 590 $EndPAD $PAD -Sh "H7" O 157 158 0 0 0 +Sh "H7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 629 590 $EndPAD $PAD -Sh "H8" O 157 158 0 0 0 +Sh "H8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 944 590 $EndPAD $PAD -Sh "J2" O 157 157 0 0 0 +Sh "J2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 17 "/FPGA_Spartan6/M0_A11" Po -944 983 $EndPAD $PAD -Sh "J3" O 157 157 0 0 0 +Sh "J3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 25 "/FPGA_Spartan6/M0_A9" Po -629 983 $EndPAD $PAD -Sh "J7" O 157 157 0 0 0 +Sh "J7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 629 983 $EndPAD $PAD -Sh "J8" O 157 157 0 0 0 +Sh "J8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 944 983 $EndPAD $PAD -Sh "K2" O 157 157 0 0 0 +Sh "K2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 2 "/DDR_Banks/M0_A8" Po -944 1377 $EndPAD $PAD -Sh "K3" O 157 157 0 0 0 +Sh "K3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 24 "/FPGA_Spartan6/M0_A7" Po -629 1377 $EndPAD $PAD -Sh "K7" O 157 157 0 0 0 +Sh "K7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 15 "/FPGA_Spartan6/M0_A0" Po 629 1377 $EndPAD $PAD -Sh "K8" O 157 157 0 0 0 +Sh "K8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 16 "/FPGA_Spartan6/M0_A10" Po 944 1377 $EndPAD $PAD -Sh "L2" O 157 158 0 0 0 +Sh "L2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 23 "/FPGA_Spartan6/M0_A6" Po -944 1771 $EndPAD $PAD -Sh "L3" O 157 158 0 0 0 +Sh "L3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 22 "/FPGA_Spartan6/M0_A5" Po -629 1771 $EndPAD $PAD -Sh "L7" O 157 158 0 0 0 +Sh "L7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 19 "/FPGA_Spartan6/M0_A2" Po 629 1771 $EndPAD $PAD -Sh "L8" O 157 158 0 0 0 +Sh "L8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 1 "/DDR_Banks/M0_A1" Po 944 1771 $EndPAD $PAD -Sh "M2" O 157 158 0 0 0 +Sh "M2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 21 "/FPGA_Spartan6/M0_A4" Po -944 2165 $EndPAD $PAD -Sh "M3" O 157 158 0 0 0 +Sh "M3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -629 2165 $EndPAD $PAD -Sh "M7" O 157 158 0 0 0 +Sh "M7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 10 "N-000036" +Ne 52 "N-000040" Po 629 2165 $EndPAD $PAD -Sh "M8" O 157 158 0 0 0 +Sh "M8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 20 "/FPGA_Spartan6/M0_A3" Po 944 2165 $EndPAD $EndMODULE 60fbga_ddr $MODULE 60fbga_ddr -Po 51969 11417 0 15 4C58C755 4C58CB99 ~~ +Po 45079 12795 0 15 4C58C755 4C58CB99 ~~ Li 60fbga_ddr Sc 4C58CB99 AR /4C421DD3/4C58CA3A @@ -5064,14 +5274,14 @@ $PAD Sh "A1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -1259 -2165 $EndPAD $PAD Sh "A9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "N-000030" +Ne 51 "N-000036" Po 1259 -2165 $EndPAD $PAD @@ -5155,14 +5365,14 @@ $PAD Sh "A3" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -629 -2165 $EndPAD $PAD Sh "A7" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "N-000030" +Ne 51 "N-000036" Po 629 -2165 $EndPAD $PAD @@ -5176,7 +5386,7 @@ $PAD Sh "B2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "N-000030" +Ne 51 "N-000036" Po -944 -1771 $EndPAD $PAD @@ -5197,14 +5407,14 @@ $PAD Sh "B8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 944 -1771 $EndPAD $PAD Sh "C2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -944 -1377 $EndPAD $PAD @@ -5225,14 +5435,14 @@ $PAD Sh "C8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "N-000030" +Ne 51 "N-000036" Po 944 -1377 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "N-000030" +Ne 51 "N-000036" Po -944 -983 $EndPAD $PAD @@ -5253,14 +5463,14 @@ $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po 944 -983 $EndPAD $PAD Sh "E2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -944 -590 $EndPAD $PAD @@ -5281,14 +5491,14 @@ $PAD Sh "E8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "N-000030" +Ne 51 "N-000036" Po 944 -590 $EndPAD $PAD Sh "F2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -944 -196 $EndPAD $PAD @@ -5309,21 +5519,21 @@ $PAD Sh "F8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "N-000030" +Ne 51 "N-000036" Po 944 -196 $EndPAD $PAD Sh "G2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/DDR_Banks/M1_CLK" +Ne 13 "/DDR_Banks/M1_CLK" Po -944 196 $EndPAD $PAD Sh "G3" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/FPGA_Spartan6/M1_CLK#" +Ne 47 "/FPGA_Spartan6/M1_CLK#" Po -629 196 $EndPAD $PAD @@ -5344,7 +5554,7 @@ $PAD Sh "H2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 9 "/DDR_Banks/M1_A12" Po -944 590 $EndPAD $PAD @@ -5372,14 +5582,14 @@ $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 41 "/FPGA_Spartan6/M1_A11" Po -944 983 $EndPAD $PAD Sh "J3" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 12 "/DDR_Banks/M1_A9" Po -629 983 $EndPAD $PAD @@ -5400,84 +5610,84 @@ $PAD Sh "K2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 46 "/FPGA_Spartan6/M1_A8" Po -944 1377 $EndPAD $PAD Sh "K3" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 45 "/FPGA_Spartan6/M1_A7" Po -629 1377 $EndPAD $PAD Sh "K7" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 7 "/DDR_Banks/M1_A0" Po 629 1377 $EndPAD $PAD Sh "K8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 40 "/FPGA_Spartan6/M1_A10" Po 944 1377 $EndPAD $PAD Sh "L2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 11 "/DDR_Banks/M1_A6" Po -944 1771 $EndPAD $PAD Sh "L3" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 44 "/FPGA_Spartan6/M1_A5" Po -629 1771 $EndPAD $PAD Sh "L7" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 42 "/FPGA_Spartan6/M1_A2" Po 629 1771 $EndPAD $PAD Sh "L8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 8 "/DDR_Banks/M1_A1" Po 944 1771 $EndPAD $PAD Sh "M2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 43 "/FPGA_Spartan6/M1_A4" Po -944 2165 $EndPAD $PAD Sh "M3" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "GND" +Ne 50 "GND" Po -629 2165 $EndPAD $PAD Sh "M7" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "N-000030" +Ne 51 "N-000036" Po 629 2165 $EndPAD $PAD Sh "M8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 10 "/DDR_Banks/M1_A3" Po 944 2165 $EndPAD $EndMODULE 60fbga_ddr diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 543d8d0..f1fce85 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,4 +1,4 @@ -# EESchema Netlist Version 1.1 created Tue 03 Aug 2010 09:06:55 PM COT +# EESchema Netlist Version 1.1 created Wed 04 Aug 2010 12:20:48 PM COT ( ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} ( 1 ? ) @@ -7,13 +7,13 @@ ( 4 ? ) ( 5 ? ) ( 6 ? ) - ( 7 N-000454 ) - ( 8 N-000453 ) + ( 7 N-000412 ) + ( 8 N-000411 ) ( 9 ? ) ( 10 ? ) ( 11 ? ) - ( 12 N-000453 ) - ( 13 N-000454 ) + ( 12 N-000411 ) + ( 13 N-000412 ) ( 14 ? ) ( 15 ? ) ( 16 ? ) @@ -23,38 +23,38 @@ ( 20 ? ) ( 21 ? ) ( 22 ? ) - ( 23 N-000453 ) - ( 24 N-000454 ) + ( 23 N-000411 ) + ( 24 N-000412 ) ( 25 /Ethernet_Phy/ETH_INT ) ( 26 ? ) ( 27 ? ) ( 28 ? ) ( 29 ? ) ( 30 ? ) - ( 31 N-000454 ) + ( 31 N-000412 ) ( 32 ? ) ( 33 ? ) ( 34 ? ) - ( 35 N-000453 ) - ( 36 N-000453 ) + ( 35 N-000411 ) + ( 36 N-000411 ) ( 37 ? ) - ( 38 N-000454 ) - ( 39 N-000453 ) + ( 38 N-000412 ) + ( 39 N-000411 ) ( 40 ? ) ( 41 ? ) ( 42 ? ) ( 43 ? ) - ( 44 N-000453 ) + ( 44 N-000411 ) ( 45 ? ) ( 46 ? ) - ( 47 N-000454 ) + ( 47 N-000412 ) ( 48 ? ) ) ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} ( P7 ? ) ( N7 ? ) ( M7 ? ) - ( L7 N-000111 ) + ( L7 N-000170 ) ( K7 ? ) ( J7 ? ) ( G7 ? ) @@ -63,28 +63,28 @@ ( N6 ? ) ( M6 ? ) ( L6 ? ) - ( K6 ? ) + ( K6 /FPGA_Spartan6/M0_A3 ) ( J6 ? ) - ( H6 ? ) + ( H6 /FPGA_Spartan6/M0_A7 ) ( G6 ? ) - ( F6 N-000111 ) + ( F6 N-000170 ) ( E6 ? ) - ( U5 N-000111 ) + ( U5 N-000170 ) ( P5 ? ) - ( N5 N-000111 ) + ( N5 N-000170 ) ( M5 ? ) ( K5 ? ) - ( J5 N-000111 ) - ( H5 ? ) + ( J5 N-000170 ) + ( H5 /FPGA_Spartan6/M0_A2 ) ( F5 ? ) ( E5 ? ) ( D5 ? ) ( U4 ? ) ( H21 ? ) - ( G21 N-000110 ) - ( F21 ? ) + ( G21 N-000130 ) + ( F21 /DDR_Banks/M1_A0 ) ( D21 ? ) - ( C21 N-000110 ) + ( C21 N-000130 ) ( B21 ? ) ( A21 ? ) ( W20 ? ) @@ -96,14 +96,14 @@ ( N20 ? ) ( M20 ? ) ( L20 ? ) - ( K20 ? ) + ( K20 /FPGA_Spartan6/M1_A5 ) ( J20 ? ) ( H20 /DDR_Banks/M1_CLK ) - ( G20 ? ) - ( F20 ? ) - ( E20 ? ) + ( G20 /DDR_Banks/M1_A3 ) + ( F20 /FPGA_Spartan6/M1_A4 ) + ( E20 /FPGA_Spartan6/M1_A7 ) ( D20 ? ) - ( C20 ? ) + ( C20 /FPGA_Spartan6/M1_A8 ) ( B20 ? ) ( A20 ? ) ( P8 ? ) @@ -111,34 +111,34 @@ ( K8 ? ) ( H8 ? ) ( B3 ? ) - ( W2 N-000111 ) - ( V2 ? ) + ( W2 N-000170 ) + ( V2 /FPGA_Spartan6/M0_DQ14 ) ( T2 ? ) - ( R2 N-000111 ) - ( P2 ? ) - ( M2 ? ) - ( L2 N-000111 ) - ( K2 ? ) - ( H2 ? ) - ( G2 N-000111 ) + ( R2 N-000170 ) + ( P2 /FPGA_Spartan6/M0_DQ8 ) + ( M2 /DDR_Banks/M0_DQ2 ) + ( L2 N-000170 ) + ( K2 /FPGA_Spartan6/M0_DQ6 ) + ( H2 /FPGA_Spartan6/M0_A0 ) + ( G2 N-000170 ) ( F2 ? ) ( D2 ? ) - ( C2 N-000111 ) + ( C2 N-000170 ) ( B2 ? ) ( A2 ? ) ( Y1 ? ) ( W1 ? ) - ( V1 ? ) - ( U1 ? ) + ( V1 /FPGA_Spartan6/M0_DQ15 ) + ( U1 /FPGA_Spartan6/M0_DQ13 ) ( T1 ? ) - ( R1 ? ) - ( P1 ? ) - ( N1 ? ) - ( M1 ? ) + ( R1 /FPGA_Spartan6/M0_DQ11 ) + ( P1 /FPGA_Spartan6/M0_DQ9 ) + ( N1 /DDR_Banks/M0_DQ1 ) + ( M1 /FPGA_Spartan6/M0_DQ3 ) ( L1 ? ) - ( K1 ? ) - ( J1 ? ) - ( H1 ? ) + ( K1 /FPGA_Spartan6/M0_DQ7 ) + ( J1 /FPGA_Spartan6/M0_DQ5 ) + ( H1 /DDR_Banks/M0_A1 ) ( G1 ? ) ( T4 ? ) ( R4 ? ) @@ -147,35 +147,35 @@ ( M4 ? ) ( L4 ? ) ( K4 ? ) - ( J4 ? ) - ( H4 /DDR_Banks/M0_CLK ) - ( G4 ? ) - ( F4 N-000111 ) + ( J4 /FPGA_Spartan6/M0_A6 ) + ( H4 /FPGA_Spartan6/M0_CLK ) + ( G4 /FPGA_Spartan6/M0_A10 ) + ( F4 N-000170 ) ( E4 ? ) ( C4 ? ) ( W3 ? ) ( V3 ? ) - ( U3 ? ) + ( U3 /FPGA_Spartan6/M0_DQ12 ) ( T3 ? ) - ( R3 ? ) + ( R3 /FPGA_Spartan6/M0_DQ10 ) ( P3 ? ) - ( N3 ? ) + ( N3 /FPGA_Spartan6/M0_DQ0 ) ( M3 ? ) ( L3 ? ) - ( K3 ? ) - ( J3 ? ) + ( K3 /FPGA_Spartan6/M0_A5 ) + ( J3 /DDR_Banks/M0_DQ4 ) ( H3 /DDR_Banks/M0_CLK# ) ( G3 ? ) - ( F3 ? ) - ( E3 ? ) + ( F3 /FPGA_Spartan6/M0_A4 ) + ( E3 /DDR_Banks/M0_A8 ) ( D3 ? ) ( C3 ? ) - ( G10 N-000109 ) + ( G10 N-000138 ) ( D10 ? ) ( C10 ? ) ( B10 ? ) ( A10 ? ) - ( E9 N-000109 ) + ( E9 N-000138 ) ( D9 ? ) ( C9 ? ) ( A9 ? ) @@ -185,7 +185,7 @@ ( A8 ? ) ( D7 ? ) ( C7 ? ) - ( B7 N-000109 ) + ( B7 N-000138 ) ( A7 ? ) ( D6 ? ) ( C6 ? ) @@ -193,17 +193,17 @@ ( A6 ? ) ( C5 ? ) ( A5 /Ethernet_Phy/ETH_INT ) - ( B4 N-000109 ) + ( B4 N-000138 ) ( A4 ? ) ( U19 ? ) ( T19 ? ) ( R19 ? ) ( P19 ? ) ( N19 ? ) - ( B19 N-000109 ) + ( B19 N-000138 ) ( B18 ? ) ( A18 ? ) - ( E17 N-000109 ) + ( E17 N-000138 ) ( D17 ? ) ( C17 ? ) ( A17 ? ) @@ -213,14 +213,14 @@ ( A16 ? ) ( D15 ? ) ( C15 ? ) - ( B15 N-000109 ) + ( B15 N-000138 ) ( A15 ? ) - ( G14 N-000109 ) + ( G14 N-000138 ) ( D14 ? ) ( C14 ? ) ( B14 ? ) ( A14 ? ) - ( E13 N-000109 ) + ( E13 N-000138 ) ( C13 ? ) ( A13 ? ) ( C12 ? ) @@ -228,7 +228,7 @@ ( A12 ? ) ( D11 ? ) ( C11 ? ) - ( B11 N-000109 ) + ( B11 N-000138 ) ( A11 ? ) ( H16 ? ) ( G16 ? ) @@ -247,34 +247,34 @@ ( J22 ? ) ( H22 ? ) ( G22 ? ) - ( F22 ? ) - ( E22 ? ) - ( D22 ? ) - ( C22 ? ) + ( F22 /DDR_Banks/M1_A1 ) + ( E22 /FPGA_Spartan6/M1_A2 ) + ( D22 /DDR_Banks/M1_A12 ) + ( C22 /DDR_Banks/M1_A9 ) ( B22 ? ) - ( W21 N-000110 ) + ( W21 N-000130 ) ( V21 ? ) ( T21 ? ) - ( R21 N-000110 ) + ( R21 N-000130 ) ( P21 ? ) ( M21 ? ) - ( L21 N-000110 ) + ( L21 N-000130 ) ( K21 ? ) ( M19 ? ) ( L19 ? ) - ( K19 ? ) + ( K19 /DDR_Banks/M1_A6 ) ( J19 /FPGA_Spartan6/M1_CLK# ) ( H19 ? ) - ( G19 ? ) - ( F19 ? ) - ( E19 N-000110 ) + ( G19 /FPGA_Spartan6/M1_A10 ) + ( F19 /FPGA_Spartan6/M1_A11 ) + ( E19 N-000130 ) ( D19 ? ) - ( U18 N-000110 ) + ( U18 N-000130 ) ( P18 ? ) - ( N18 N-000110 ) + ( N18 N-000130 ) ( M18 ? ) ( K18 ? ) - ( J18 N-000110 ) + ( J18 N-000130 ) ( H18 ? ) ( F18 ? ) ( P17 ? ) @@ -287,18 +287,18 @@ ( F17 ? ) ( N16 ? ) ( M16 ? ) - ( L16 N-000110 ) + ( L16 N-000130 ) ( K16 ? ) ( J16 ? ) - ( J14 N-000113 ) + ( J14 N-000171 ) ( H14 ? ) ( F14 ? ) ( E14 ? ) - ( P13 N-000113 ) + ( P13 N-000171 ) ( N13 GND ) - ( M13 N-000113 ) + ( M13 N-000171 ) ( L13 GND ) - ( K13 N-000113 ) + ( K13 N-000171 ) ( J13 GND ) ( H13 ? ) ( G13 ? ) @@ -307,15 +307,15 @@ ( B13 GND ) ( Y22 ? ) ( A22 GND ) - ( R12 N-000112 ) + ( R12 N-000172 ) ( P12 GND ) - ( N12 N-000113 ) + ( N12 N-000171 ) ( M12 GND ) - ( L12 N-000113 ) + ( L12 N-000171 ) ( K12 GND ) - ( J12 N-000113 ) + ( J12 N-000171 ) ( H12 ? ) - ( G12 N-000112 ) + ( G12 N-000172 ) ( F12 ? ) ( E12 ? ) ( D12 ? ) @@ -332,34 +332,34 @@ ( B17 GND ) ( W16 GND ) ( P16 ? ) - ( D16 N-000112 ) + ( D16 N-000172 ) ( AA5 GND ) ( P15 ? ) ( N15 ? ) - ( M15 N-000112 ) - ( K15 N-000112 ) + ( M15 N-000172 ) + ( K15 N-000172 ) ( J15 GND ) - ( H15 N-000112 ) + ( H15 N-000172 ) ( G15 ? ) ( F15 ? ) ( E15 GND ) ( V14 GND ) - ( R14 N-000113 ) + ( R14 N-000171 ) ( P14 GND ) - ( N14 N-000113 ) + ( N14 N-000171 ) ( M14 GND ) - ( L14 N-000113 ) + ( L14 N-000171 ) ( K14 GND ) ( L9 GND ) - ( K9 N-000113 ) + ( K9 N-000171 ) ( J9 GND ) - ( H9 N-000112 ) + ( H9 N-000172 ) ( G9 ? ) ( F9 ? ) ( B9 GND ) - ( N8 N-000112 ) - ( L8 N-000112 ) - ( J8 N-000113 ) + ( N8 N-000172 ) + ( L8 N-000172 ) + ( J8 N-000171 ) ( G8 ? ) ( F8 ? ) ( E8 ? ) @@ -367,8 +367,8 @@ ( U7 GND ) ( H7 GND ) ( E7 GND ) - ( V6 N-000112 ) - ( R6 N-000112 ) + ( V6 N-000172 ) + ( R6 N-000172 ) ( R5 GND ) ( L5 GND ) ( G5 GND ) @@ -385,31 +385,31 @@ ( N21 GND ) ( J21 GND ) ( E21 GND ) - ( U11 N-000112 ) - ( P11 N-000113 ) + ( U11 N-000172 ) + ( P11 N-000171 ) ( N11 GND ) - ( M11 N-000113 ) + ( M11 N-000171 ) ( L11 GND ) - ( K11 N-000113 ) + ( K11 N-000171 ) ( J11 GND ) ( H11 ? ) ( G11 ? ) - ( F11 N-000112 ) + ( F11 N-000172 ) ( E11 GND ) ( V10 GND ) - ( R10 N-000112 ) + ( R10 N-000172 ) ( P10 GND ) - ( N10 N-000113 ) + ( N10 N-000171 ) ( M10 GND ) - ( L10 N-000113 ) + ( L10 N-000171 ) ( K10 GND ) - ( J10 N-000113 ) + ( J10 N-000171 ) ( H10 ? ) ( F10 ? ) ( E10 ? ) - ( P9 N-000113 ) + ( P9 N-000171 ) ( N9 GND ) - ( M9 N-000113 ) + ( M9 N-000171 ) ( V19 ? ) ( AB8 ? ) ( AA8 ? ) @@ -418,7 +418,7 @@ ( V18 ? ) ( T18 ? ) ( AB7 ? ) - ( AA7 N-000108 ) + ( AA7 N-000169 ) ( Y17 ? ) ( W17 ? ) ( V17 ? ) @@ -427,7 +427,7 @@ ( AB6 ? ) ( AA6 ? ) ( Y16 ? ) - ( V16 N-000108 ) + ( V16 N-000169 ) ( U16 ? ) ( T16 ? ) ( R16 ? ) @@ -441,19 +441,19 @@ ( AB4 ? ) ( AA4 ? ) ( F1 ? ) - ( E1 ? ) - ( D1 ? ) - ( C1 ? ) + ( E1 /FPGA_Spartan6/M0_A9 ) + ( D1 /FPGA_Spartan6/M0_A12 ) + ( C1 /FPGA_Spartan6/M0_A11 ) ( B1 ? ) ( AB19 ? ) - ( AA19 N-000108 ) + ( AA19 N-000169 ) ( AB18 ? ) ( AA18 ? ) ( AB17 ? ) ( AB16 ? ) ( AA16 ? ) ( AB15 ? ) - ( AA15 N-000108 ) + ( AA15 N-000169 ) ( AB14 ? ) ( AA14 ? ) ( AB13 ? ) @@ -463,7 +463,7 @@ ( AB21 ? ) ( AA21 ? ) ( AB11 ? ) - ( AA11 N-000108 ) + ( AA11 N-000169 ) ( AB20 ? ) ( AA20 ? ) ( AB10 ? ) @@ -472,11 +472,11 @@ ( Y19 ? ) ( V9 ? ) ( U9 ? ) - ( T9 N-000108 ) + ( T9 N-000169 ) ( R9 ? ) ( Y8 ? ) ( W8 ? ) - ( V8 N-000108 ) + ( V8 N-000169 ) ( U8 ? ) ( T8 ? ) ( R8 ? ) @@ -489,7 +489,7 @@ ( U6 ? ) ( T6 ? ) ( Y5 ? ) - ( W5 N-000108 ) + ( W5 N-000169 ) ( V5 ? ) ( T5 ? ) ( Y4 ? ) @@ -505,18 +505,18 @@ ( U14 ? ) ( T14 ? ) ( AB3 ? ) - ( AA3 N-000108 ) + ( AA3 N-000169 ) ( Y13 ? ) ( W13 ? ) ( V13 ? ) ( U13 ? ) - ( T13 N-000108 ) + ( T13 N-000169 ) ( R13 ? ) ( AB2 ? ) ( AA2 ? ) ( Y12 ? ) ( W12 ? ) - ( V12 N-000108 ) + ( V12 N-000169 ) ( U12 ? ) ( T12 ? ) ( Y11 ? ) @@ -595,68 +595,6 @@ ( 48 ? ) ) ( /4C421DD3/4C58CA3A 60fbga_ddr U3 MT46V32M16FN {Lib=MT46V32M16FN} - ( A7 N-000030 ) - ( B7 ? ) - ( C7 ? ) - ( D7 ? ) - ( E7 ? ) - ( F7 ? ) - ( G7 ? ) - ( H7 ? ) - ( J7 ? ) - ( K7 ? ) - ( L7 ? ) - ( M7 N-000030 ) - ( A8 ? ) - ( B8 GND ) - ( C8 N-000030 ) - ( D8 GND ) - ( E8 N-000030 ) - ( F8 N-000030 ) - ( G8 ? ) - ( H8 ? ) - ( J8 ? ) - ( K8 ? ) - ( L8 ? ) - ( M8 ? ) - ( A9 N-000030 ) - ( B9 ? ) - ( C9 ? ) - ( D9 ? ) - ( E9 ? ) - ( F9 ? ) - ( A1 GND ) - ( B1 ? ) - ( C1 ? ) - ( D1 ? ) - ( E1 ? ) - ( F1 ? ) - ( A2 ? ) - ( B2 N-000030 ) - ( C2 GND ) - ( D2 N-000030 ) - ( E2 GND ) - ( F2 GND ) - ( G2 /DDR_Banks/M1_CLK ) - ( H2 ? ) - ( J2 ? ) - ( K2 ? ) - ( L2 ? ) - ( M2 ? ) - ( A3 GND ) - ( B3 ? ) - ( C3 ? ) - ( D3 ? ) - ( E3 ? ) - ( F3 ? ) - ( G3 /FPGA_Spartan6/M1_CLK# ) - ( H3 ? ) - ( J3 ? ) - ( K3 ? ) - ( L3 ? ) - ( M3 GND ) - ) - ( /4C421DD3/4C58C847 60fbga_ddr U2 MT46V32M16FN {Lib=MT46V32M16FN} ( A7 N-000036 ) ( B7 ? ) ( C7 ? ) @@ -666,8 +604,8 @@ ( G7 ? ) ( H7 ? ) ( J7 ? ) - ( K7 ? ) - ( L7 ? ) + ( K7 /DDR_Banks/M1_A0 ) + ( L7 /FPGA_Spartan6/M1_A2 ) ( M7 N-000036 ) ( A8 ? ) ( B8 GND ) @@ -678,9 +616,9 @@ ( G8 ? ) ( H8 ? ) ( J8 ? ) - ( K8 ? ) - ( L8 ? ) - ( M8 ? ) + ( K8 /FPGA_Spartan6/M1_A10 ) + ( L8 /DDR_Banks/M1_A1 ) + ( M8 /DDR_Banks/M1_A3 ) ( A9 N-000036 ) ( B9 ? ) ( C9 ? ) @@ -699,246 +637,434 @@ ( D2 N-000036 ) ( E2 GND ) ( F2 GND ) - ( G2 /DDR_Banks/M0_CLK ) - ( H2 ? ) - ( J2 ? ) - ( K2 ? ) - ( L2 ? ) - ( M2 ? ) + ( G2 /DDR_Banks/M1_CLK ) + ( H2 /DDR_Banks/M1_A12 ) + ( J2 /FPGA_Spartan6/M1_A11 ) + ( K2 /FPGA_Spartan6/M1_A8 ) + ( L2 /DDR_Banks/M1_A6 ) + ( M2 /FPGA_Spartan6/M1_A4 ) ( A3 GND ) ( B3 ? ) ( C3 ? ) ( D3 ? ) ( E3 ? ) ( F3 ? ) + ( G3 /FPGA_Spartan6/M1_CLK# ) + ( H3 ? ) + ( J3 /DDR_Banks/M1_A9 ) + ( K3 /FPGA_Spartan6/M1_A7 ) + ( L3 /FPGA_Spartan6/M1_A5 ) + ( M3 GND ) + ) + ( /4C421DD3/4C58C847 60fbga_ddr U2 MT46V32M16FN {Lib=MT46V32M16FN} + ( A7 N-000040 ) + ( B7 /DDR_Banks/M0_DQ2 ) + ( C7 /DDR_Banks/M0_DQ4 ) + ( D7 /FPGA_Spartan6/M0_DQ6 ) + ( E7 ? ) + ( F7 ? ) + ( G7 ? ) + ( H7 ? ) + ( J7 ? ) + ( K7 /FPGA_Spartan6/M0_A0 ) + ( L7 /FPGA_Spartan6/M0_A2 ) + ( M7 N-000040 ) + ( A8 /FPGA_Spartan6/M0_DQ0 ) + ( B8 GND ) + ( C8 N-000040 ) + ( D8 GND ) + ( E8 N-000040 ) + ( F8 N-000040 ) + ( G8 ? ) + ( H8 ? ) + ( J8 ? ) + ( K8 /FPGA_Spartan6/M0_A10 ) + ( L8 /DDR_Banks/M0_A1 ) + ( M8 /FPGA_Spartan6/M0_A3 ) + ( A9 N-000040 ) + ( B9 /DDR_Banks/M0_DQ1 ) + ( C9 /FPGA_Spartan6/M0_DQ3 ) + ( D9 /FPGA_Spartan6/M0_DQ5 ) + ( E9 /FPGA_Spartan6/M0_DQ7 ) + ( F9 ? ) + ( A1 GND ) + ( B1 /FPGA_Spartan6/M0_DQ14 ) + ( C1 /FPGA_Spartan6/M0_DQ12 ) + ( D1 /FPGA_Spartan6/M0_DQ10 ) + ( E1 /FPGA_Spartan6/M0_DQ8 ) + ( F1 ? ) + ( A2 /FPGA_Spartan6/M0_DQ15 ) + ( B2 N-000040 ) + ( C2 GND ) + ( D2 N-000040 ) + ( E2 GND ) + ( F2 GND ) + ( G2 /FPGA_Spartan6/M0_CLK ) + ( H2 /FPGA_Spartan6/M0_A12 ) + ( J2 /FPGA_Spartan6/M0_A11 ) + ( K2 /DDR_Banks/M0_A8 ) + ( L2 /FPGA_Spartan6/M0_A6 ) + ( M2 /FPGA_Spartan6/M0_A4 ) + ( A3 GND ) + ( B3 /FPGA_Spartan6/M0_DQ13 ) + ( C3 /FPGA_Spartan6/M0_DQ11 ) + ( D3 /FPGA_Spartan6/M0_DQ9 ) + ( E3 ? ) + ( F3 ? ) ( G3 /DDR_Banks/M0_CLK# ) ( H3 ? ) - ( J3 ? ) - ( K3 ? ) - ( L3 ? ) + ( J3 /FPGA_Spartan6/M0_A9 ) + ( K3 /FPGA_Spartan6/M0_A7 ) + ( L3 /FPGA_Spartan6/M0_A5 ) ( M3 GND ) ) ) * { Pin List by Nets -Net 17 "/DDR Banks/M1_CLK" "M1_CLK" +Net 25 "/DDR Banks/M1_CLK" "M1_CLK" U1 H20 U3 G2 -Net 18 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" - U3 G3 +Net 26 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" U1 J19 -Net 19 "/DDR Banks/M0_CLK" "M0_CLK" - U1 H4 + U3 G3 +Net 27 "/FPGA Spartan6/M0_CLK" "M0_CLK" U2 G2 -Net 20 "/DDR Banks/M0_CLK#" "M0_CLK#" - U1 H3 + U1 H4 +Net 28 "/DDR Banks/M0_CLK#" "M0_CLK#" U2 G3 -Net 21 "/Ethernet Phy/ETH_INT" "ETH_INT" - U1 A5 + U1 H3 +Net 29 "/Ethernet Phy/ETH_INT" "ETH_INT" U4 25 -Net 30 "" "" + U1 A5 +Net 36 "" "" + U3 M7 + U3 A7 U3 C8 - U3 A9 U3 E8 U3 F8 - U3 A7 - U3 M7 U3 B2 U3 D2 -Net 35 "GND" "GND" - U1 B5 - U1 V4 - U1 D4 - U1 G5 - U1 N2 - U1 U2 - U5 13 + U3 A9 +Net 39 "GND" "GND" + U1 A1 + U1 B9 U5 36 + U5 13 J1 CASE J1 CASE J1 CASE J1 COM - U2 A3 - U2 F2 - U2 E2 - U2 C2 - U2 A1 - U2 D8 - U2 B8 - U2 M3 - U1 L5 - U1 R5 - U1 E7 - U1 H7 - U1 U7 U1 W7 - U1 B9 - U1 J2 - U1 E2 - U1 A1 - U1 V14 - U1 P14 - U1 M14 - U1 N13 - U1 L13 - U1 AA17 - U1 P10 - U1 V10 - U1 E11 + U1 U7 + U1 H7 U1 J11 U1 L11 - U1 AA13 U1 N11 - U1 N17 - U1 D18 - U1 G18 - U1 AB22 - U1 AA9 - U1 W19 - U1 R18 - U1 L18 + U2 M3 U1 E21 U1 J21 U1 N21 U1 U21 - U1 AB1 + U2 B8 + U2 D8 U1 K12 - U1 M12 - U1 P12 - U1 A22 - U1 B13 - U1 J13 - U1 J9 - U1 L9 + U1 E15 + U1 V14 + U1 P14 U1 N9 U1 K10 - U1 M10 + U1 M14 U1 K14 + U1 M10 + U1 P10 + U2 E2 + U2 F2 + U1 V10 + U2 A3 + U1 N13 + U1 L13 + U1 E7 + U1 R5 + U1 L5 + U1 G5 + U1 B5 + U1 J13 + U2 A1 + U1 B13 + U1 A22 + U1 P12 + U2 C2 + U1 AB1 + U1 J9 + U1 L9 + U1 M12 + U1 E11 + U1 D18 + U1 N17 U1 B17 U1 W16 U1 AA5 U1 J15 - U1 E15 - U3 M3 + U1 J2 + U1 AA17 + U1 AA13 + U1 AB22 + U1 AA9 + U1 W19 + U1 R18 + U1 E2 + U1 V4 + U1 D4 + U1 U2 + U1 N2 + U1 L18 + U1 G18 + U3 A3 + U3 F2 + U3 E2 + U3 C2 U3 A1 U3 D8 U3 B8 - U3 C2 - U3 E2 - U3 F2 - U3 A3 -Net 36 "" "" + U3 M3 +Net 40 "" "" + U2 A7 + U2 A9 U2 M7 U2 C8 U2 E8 U2 F8 - U2 D2 U2 B2 - U2 A7 - U2 A9 -Net 91 "3.3V" "3.3V" + U2 D2 +Net 45 "3.3V" "3.3V" U5 19 U5 12 U5 37 -Net 100 "/Non volatile memories/FRB_N" "FRB_N" - U5 7 +Net 49 "/Non volatile memories/FRB_N" "FRB_N" U5 6 -Net 108 "" "" - U1 V12 - U1 V16 - U1 T13 - U1 T9 - U1 W5 - U1 AA15 - U1 AA19 - U1 V8 - U1 AA7 - U1 AA3 - U1 AA11 -Net 109 "" "" - U1 B4 - U1 E17 - U1 B19 - U1 B11 - U1 G10 - U1 E13 - U1 E9 - U1 G14 - U1 B15 - U1 B7 -Net 110 "" "" - U1 L16 - U1 C21 + U5 7 +Net 130 "" "" U1 W21 - U1 G21 - U1 L21 U1 R21 + U1 L21 + U1 L16 + U1 G21 + U1 C21 + U1 E19 U1 J18 U1 N18 U1 U18 - U1 E19 -Net 111 "" "" +Net 138 "" "" + U1 B4 + U1 B7 + U1 E13 + U1 G14 + U1 B15 + U1 B11 + U1 G10 + U1 E9 + U1 B19 + U1 E17 +Net 169 "" "" + U1 AA7 + U1 V16 + U1 AA3 + U1 AA19 + U1 AA11 + U1 AA15 + U1 W5 + U1 V12 + U1 T13 + U1 V8 + U1 T9 +Net 170 "" "" U1 L7 + U1 J5 + U1 N5 + U1 R2 + U1 L2 + U1 G2 + U1 C2 + U1 F4 U1 F6 U1 U5 - U1 N5 - U1 C2 - U1 J5 - U1 G2 - U1 L2 - U1 R2 - U1 F4 U1 W2 -Net 112 "" "" - U1 G12 - U1 N8 - U1 L8 - U1 D16 - U1 M15 - U1 F11 - U1 K15 - U1 V6 - U1 R6 - U1 H15 - U1 R12 - U1 R10 - U1 H9 - U1 U11 -Net 113 "" "" - U1 J10 - U1 L10 +Net 171 "" "" + U1 K13 U1 N10 - U1 K11 + U1 L10 + U1 J10 + U1 P9 + U1 M9 + U1 K9 + U1 M13 U1 P13 + U1 J14 + U1 L14 + U1 N14 + U1 R14 + U1 J12 + U1 L12 + U1 N12 + U1 J8 U1 P11 U1 M11 - U1 M13 - U1 N14 - U1 K9 - U1 K13 - U1 R14 - U1 N12 - U1 L12 - U1 L14 - U1 J12 - U1 J8 - U1 M9 - U1 J14 - U1 P9 -Net 453 "" "" - U4 35 - U4 36 + U1 K11 +Net 172 "" "" + U1 U11 + U1 H9 + U1 F11 + U1 R10 + U1 D16 + U1 M15 + U1 K15 + U1 H15 + U1 N8 + U1 L8 + U1 V6 + U1 R6 + U1 R12 + U1 G12 +Net 411 "" "" U4 39 - U4 8 U4 12 - U4 23 U4 44 -Net 454 "" "" + U4 36 + U4 23 + U4 8 + U4 35 +Net 412 "" "" U4 7 - U4 47 - U4 38 - U4 31 U4 13 + U4 31 + U4 38 + U4 47 U4 24 +Net 422 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" + U1 K1 + U2 E9 +Net 423 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" + U1 P2 + U2 E1 +Net 424 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" + U1 P1 + U2 D3 +Net 425 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" + U1 R3 + U2 D1 +Net 426 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" + U1 R1 + U2 C3 +Net 427 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" + U2 C1 + U1 U3 +Net 428 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" + U2 B3 + U1 U1 +Net 429 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" + U1 V2 + U2 B1 +Net 430 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" + U1 V1 + U2 A2 +Net 431 "/FPGA Spartan6/M0_A0" "M0_A0" + U2 K7 + U1 H2 +Net 432 "/DDR Banks/M0_A1" "M0_A1" + U2 L8 + U1 H1 +Net 433 "/FPGA Spartan6/M0_A2" "M0_A2" + U1 H5 + U2 L7 +Net 434 "/FPGA Spartan6/M0_A3" "M0_A3" + U2 M8 + U1 K6 +Net 435 "/FPGA Spartan6/M0_A4" "M0_A4" + U2 M2 + U1 F3 +Net 436 "/FPGA Spartan6/M0_A5" "M0_A5" + U1 K3 + U2 L3 +Net 437 "/FPGA Spartan6/M0_A6" "M0_A6" + U2 L2 + U1 J4 +Net 438 "/FPGA Spartan6/M0_A7" "M0_A7" + U2 K3 + U1 H6 +Net 439 "/DDR Banks/M0_A8" "M0_A8" + U1 E3 + U2 K2 +Net 440 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" + U2 A8 + U1 N3 +Net 441 "/DDR Banks/M0_DQ1" "M0_DQ1" + U2 B9 + U1 N1 +Net 442 "/DDR Banks/M0_DQ2" "M0_DQ2" + U1 M2 + U2 B7 +Net 443 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" + U1 M1 + U2 C9 +Net 444 "/DDR Banks/M0_DQ4" "M0_DQ4" + U1 J3 + U2 C7 +Net 445 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" + U2 D9 + U1 J1 +Net 446 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" + U2 D7 + U1 K2 +Net 447 "/DDR Banks/M1_A9" "M1_A9" + U3 J3 + U1 C22 +Net 448 "/FPGA Spartan6/M1_A10" "M1_A10" + U3 K8 + U1 G19 +Net 449 "/FPGA Spartan6/M1_A11" "M1_A11" + U1 F19 + U3 J2 +Net 450 "/DDR Banks/M1_A12" "M1_A12" + U3 H2 + U1 D22 +Net 467 "/FPGA Spartan6/M0_A9" "M0_A9" + U1 E1 + U2 J3 +Net 468 "/FPGA Spartan6/M0_A10" "M0_A10" + U1 G4 + U2 K8 +Net 469 "/FPGA Spartan6/M0_A11" "M0_A11" + U1 C1 + U2 J2 +Net 470 "/FPGA Spartan6/M0_A12" "M0_A12" + U2 H2 + U1 D1 +Net 471 "/DDR Banks/M1_A0" "M1_A0" + U1 F21 + U3 K7 +Net 472 "/DDR Banks/M1_A1" "M1_A1" + U1 F22 + U3 L8 +Net 473 "/FPGA Spartan6/M1_A2" "M1_A2" + U1 E22 + U3 L7 +Net 474 "/DDR Banks/M1_A3" "M1_A3" + U1 G20 + U3 M8 +Net 475 "/FPGA Spartan6/M1_A4" "M1_A4" + U1 F20 + U3 M2 +Net 476 "/FPGA Spartan6/M1_A5" "M1_A5" + U1 K20 + U3 L3 +Net 477 "/DDR Banks/M1_A6" "M1_A6" + U3 L2 + U1 K19 +Net 478 "/FPGA Spartan6/M1_A7" "M1_A7" + U1 E20 + U3 K3 +Net 479 "/FPGA Spartan6/M1_A8" "M1_A8" + U3 K2 + U1 C20 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 49c1cf0..3af98fb 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Tue 03 Aug 2010 09:21:55 PM COT +update=Wed 04 Aug 2010 07:51:52 PM COT version=1 last_client=pcbnew [general] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 78d5afd..79714f3 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 03 Aug 2010 09:21:21 PM COT +EESchema Schematic File Version 2 date Wed 04 Aug 2010 12:20:40 PM COT LIBS:power LIBS:device LIBS:transistors @@ -44,24 +44,24 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Bus Line + 2750 3350 4000 3350 Wire Wire Line - 4000 2300 2750 2300 + 2750 2200 4000 2200 +Wire Wire Line + 2750 4250 4000 4250 +Wire Bus Line + 2750 3250 4000 3250 +Wire Bus Line + 4000 3250 4000 3300 +Wire Wire Line + 7800 4550 7350 4550 Wire Wire Line 2750 4350 4000 4350 Wire Wire Line - 7800 4550 7350 4550 + 4000 2300 2750 2300 Wire Bus Line - 4000 3300 4000 3250 -Wire Bus Line - 4000 3250 2750 3250 -Wire Bus Line - 4000 1200 4000 1150 -Wire Wire Line - 2750 4250 4000 4250 -Wire Wire Line - 2750 2200 4000 2200 -Wire Bus Line - 4000 1150 2750 1150 + 2750 1250 4000 1250 $Sheet S 7800 4450 1450 2200 U 4C4320F3 @@ -93,6 +93,9 @@ F3 "M1_CLK#" O L 4000 2300 60 F4 "M0_CLK" O L 4000 4250 60 F5 "M0_CLK#" O L 4000 4350 60 F6 "ETH_INT" I R 7350 4550 60 +F7 "M0_A[0..12]" O L 4000 3350 60 +F8 "M1_A[0..12]" O L 4000 1250 60 +F9 "M0_DQ[0..15]" B L 4000 3250 60 $EndSheet $Sheet S 8700 900 1150 1850