From 5b6c73e5f5d070bbe71c47ec0c95d3e91885651d Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Fri, 12 Nov 2010 18:46:48 -0500 Subject: [PATCH] labels overlaped to pads has been fixed --- kicad/xue-rnc/DBG_PRG.sch | 5 +- kicad/xue-rnc/DRAM.sch | 5 +- kicad/xue-rnc/FPGA_0_2_PROG.sch | 5 +- kicad/xue-rnc/FPGA_1_3.sch | 5 +- kicad/xue-rnc/NV_MEMORIES.sch | 5 +- kicad/xue-rnc/PSU.sch | 5 +- kicad/xue-rnc/USB.sch | 7 +- kicad/xue-rnc/eth_phy.sch | 8 +- kicad/xue-rnc/expantion.sch | 5 +- kicad/xue-rnc/sensor.sch | 5 +- kicad/xue-rnc/sensor_psu.sch | 5 +- kicad/xue-rnc/xue-rnc-cache.lib | 12 +- kicad/xue-rnc/xue-rnc.brd | 19721 +++++++++++++++--------------- kicad/xue-rnc/xue-rnc.cmp | 8 +- kicad/xue-rnc/xue-rnc.net | 550 +- kicad/xue-rnc/xue-rnc.pro | 12 +- kicad/xue-rnc/xue-rnc.sch | 5 +- 17 files changed, 10211 insertions(+), 10157 deletions(-) diff --git a/kicad/xue-rnc/DBG_PRG.sch b/kicad/xue-rnc/DBG_PRG.sch index fee4345..5cd0881 100644 --- a/kicad/xue-rnc/DBG_PRG.sch +++ b/kicad/xue-rnc/DBG_PRG.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 7 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 017c0cf..661fab2 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 9 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/FPGA_0_2_PROG.sch b/kicad/xue-rnc/FPGA_0_2_PROG.sch index c3bf1c4..07faac8 100644 --- a/kicad/xue-rnc/FPGA_0_2_PROG.sch +++ b/kicad/xue-rnc/FPGA_0_2_PROG.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 5 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/FPGA_1_3.sch b/kicad/xue-rnc/FPGA_1_3.sch index 9d1eafd..8be79fa 100644 --- a/kicad/xue-rnc/FPGA_1_3.sch +++ b/kicad/xue-rnc/FPGA_1_3.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 6 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 86fe96c..44619e2 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 9 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index 4eea628..1153339 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 8 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 7bdf7a5..937d7f0 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 10 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" @@ -667,6 +666,7 @@ U 1 1 4C6552B6 P 5650 6900 F 0 "R15" V 5730 6900 50 0000 C CNN F 1 "1M" V 5650 6900 50 0000 C CNN +F 2 "0603" H 5650 6900 60 0001 C CNN 1 5650 6900 1 0 0 -1 $EndComp @@ -809,6 +809,7 @@ U 1 1 4C5F2D27 P 6100 3250 F 0 "R10" V 6180 3250 50 0000 C CNN F 1 "1M" V 6100 3250 50 0000 C CNN +F 2 "0603" H 6100 3250 60 0001 C CNN 1 6100 3250 1 0 0 -1 $EndComp diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 1eb1e58..e7ca58b 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 8 12 +Sheet 11 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" @@ -584,6 +583,7 @@ U 1 1 4C5D7DC4 P 10500 6250 F 0 "R9" V 10580 6250 50 0000 C CNN F 1 "1M" V 10500 6250 50 0000 C CNN +F 2 "0603" H 10500 6250 60 0001 C CNN 1 10500 6250 1 0 0 -1 $EndComp diff --git a/kicad/xue-rnc/expantion.sch b/kicad/xue-rnc/expantion.sch index 3f62f76..e5e6fc2 100644 --- a/kicad/xue-rnc/expantion.sch +++ b/kicad/xue-rnc/expantion.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 2 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/sensor.sch b/kicad/xue-rnc/sensor.sch index c1f1bc1..294bd85 100644 --- a/kicad/xue-rnc/sensor.sch +++ b/kicad/xue-rnc/sensor.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 3 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/sensor_psu.sch b/kicad/xue-rnc/sensor_psu.sch index c36feaf..1026d0f 100644 --- a/kicad/xue-rnc/sensor_psu.sch +++ b/kicad/xue-rnc/sensor_psu.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 4 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index a0ace91..b2632f5 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Sun 07 Nov 2010 12:36:16 PM COT +EESchema-LIBRARY Version 2.3 Date: Fri 12 Nov 2010 06:20:49 PM COT # # +1.2V # @@ -236,8 +236,7 @@ X P22 22 400 200 300 L 60 30 1 1 P I X P32 32 400 -300 300 L 60 30 1 1 P I X P42 42 400 -800 300 L 60 30 1 1 P I X P13 13 -400 600 300 R 60 30 1 1 P I -X P23 23 -400 100 300 R 60 30 1 1 P I -X P23 23 -400 100 300 R 60 30 1 1 P I +X P23 23 -400 100 300 R 50 50 1 1 I I X P33 33 -400 -400 300 R 60 30 1 1 P I X P43 43 -400 -900 300 R 60 30 1 1 P I X P14 14 400 600 300 L 60 30 1 1 P I @@ -245,7 +244,7 @@ X P24 24 400 100 300 L 60 30 1 1 P I X P34 34 400 -400 300 L 60 30 1 1 P I X P44 44 400 -900 300 L 60 30 1 1 P I X P15 15 -400 500 300 R 60 30 1 1 P I -X ~ 25 -400 0 300 R 60 30 1 1 P I +X P25 25 -400 0 300 R 50 50 1 1 I I X P35 35 -400 -500 300 R 60 30 1 1 P I X P45 45 -400 -1000 300 R 60 30 1 1 P I X P16 16 400 500 300 L 60 30 1 1 P I @@ -400,7 +399,7 @@ DEF ~GND #PWR 0 0 Y Y 1 F P F0 "#PWR" 0 0 30 H I C CNN F1 "GND" 0 -70 30 H I C CNN DRAW -P 4 0 1 4 -50 0 0 -50 50 0 -50 0 N +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N X GND 1 0 0 0 U 30 30 1 1 W N ENDDRAW ENDDEF @@ -756,9 +755,10 @@ $FPLIST R? SM0603 SM0805 + R?-* $ENDFPLIST DRAW -S -40 150 40 -150 0 1 8 N +S -40 150 40 -150 0 1 12 N X ~ 1 0 250 100 D 60 60 1 1 P X ~ 2 0 -250 100 U 60 60 1 1 P ENDDRAW diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index bcc6788..33c9f90 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,6 +1,6 @@ -PCBNEW-BOARD Version 1 date Thu 11 Nov 2010 02:21:41 PM COT +PCBNEW-BOARD Version 1 date Fri 12 Nov 2010 06:44:22 PM COT -# Created by Pcbnew(2010-11-03 BZR 2592)-testing +# Created by Pcbnew(2010-10-01 BZR 2513)-testing $GENERAL LayerCount 6 @@ -8,9 +8,9 @@ Ly 1FFF801F EnabledLayers 13FF801F Links 1097 NoConn 0 -Di 45224 12863 67005 52832 +Di 45598 12844 67005 52832 Ndraw 6 -Ntrack 7377 +Ntrack 7382 Nzone 0 BoardThickness 630 Nmodule 318 @@ -20,7 +20,7 @@ $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "11 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 "" @@ -139,63 +139,63 @@ Na 15 "/DBG_PRG/AVR_RST" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DBG_PRG/FPGA_TCK" +Na 16 "/DBG_PRG/AVR_SCK" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DBG_PRG/FPGA_TDI" +Na 17 "/DBG_PRG/FPGA_TCK" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DBG_PRG/FPGA_TDO" +Na 18 "/DBG_PRG/FPGA_TDI" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DBG_PRG/FPGA_TMS" +Na 19 "/DBG_PRG/FPGA_TDO" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DBG_PRG/FTDI_USB_DM" +Na 20 "/DBG_PRG/FPGA_TMS" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DBG_PRG/FTDI_USB_DP" +Na 21 "/DBG_PRG/FTDI_USB_DM" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DBG_PRG/USB_CASE_FTDI" +Na 22 "/DBG_PRG/FTDI_USB_DP" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DBG_PRG/VCC_USB" +Na 23 "/DBG_PRG/USB_CASE_FTDI" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M0_A12" +Na 24 "/DBG_PRG/VCC_USB" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M0_A2" +Na 25 "/DDR_Banks/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M0_A5" +Na 26 "/DDR_Banks/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M0_A6" +Na 27 "/DDR_Banks/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M0_A9" +Na 28 "/DDR_Banks/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M0_CAS#" +Na 29 "/DDR_Banks/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M0_CKE" +Na 30 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT @@ -203,11 +203,11 @@ Na 31 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M0_DQ10" +Na 32 "/DDR_Banks/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M0_DQ2" +Na 33 "/DDR_Banks/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT @@ -215,7 +215,7 @@ Na 34 "/DDR_Banks/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M0_DQ8" +Na 35 "/DDR_Banks/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT @@ -227,19 +227,19 @@ Na 37 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M0_UDM" +Na 38 "/DDR_Banks/M0_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/DDR_Banks/M0_UDQS" +Na 39 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/DDR_Banks/M0_VREF" +Na 40 "/DDR_Banks/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/DDR_Banks/M1_A0" +Na 41 "/DDR_Banks/M1_A11" St ~ $EndEQUIPOT $EQUIPOT @@ -247,7 +247,7 @@ Na 42 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/DDR_Banks/M1_A2" +Na 43 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT @@ -255,87 +255,87 @@ Na 44 "/DDR_Banks/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/DDR_Banks/M1_A9" +Na 45 "/DDR_Banks/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/DDR_Banks/M1_CLK" +Na 46 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/DDR_Banks/M1_CLK#" +Na 47 "/DDR_Banks/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/DDR_Banks/M1_CS#" +Na 48 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/DDR_Banks/M1_DQ0" +Na 49 "/DDR_Banks/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/DDR_Banks/M1_DQ12" +Na 50 "/DDR_Banks/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/DDR_Banks/M1_DQ3" +Na 51 "/DDR_Banks/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/DDR_Banks/M1_DQ4" +Na 52 "/DDR_Banks/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/DDR_Banks/M1_DQ5" +Na 53 "/DDR_Banks/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/DDR_Banks/M1_LDQS" +Na 54 "/DDR_Banks/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/DDR_Banks/M1_UDM" +Na 55 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/DDR_Banks/M1_VREF" +Na 56 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/DDR_Banks/M1_WE#" +Na 57 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/Ethernet_Phy/ETH_A1.8V" +Na 58 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/Ethernet_Phy/ETH_A3.3V" +Na 59 "/DDR_Banks/M1_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/Ethernet_Phy/ETH_CLK" +Na 60 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/Ethernet_Phy/ETH_COL" +Na 61 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/Ethernet_Phy/ETH_INT" +Na 62 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/Ethernet_Phy/ETH_LED0" +Na 63 "/Ethernet_Phy/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/Ethernet_Phy/ETH_LED1" +Na 64 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/Ethernet_Phy/ETH_MDC" +Na 65 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT @@ -343,23 +343,23 @@ Na 66 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/Ethernet_Phy/ETH_RXD0" +Na 67 "/Ethernet_Phy/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/Ethernet_Phy/ETH_RXD1" +Na 68 "/Ethernet_Phy/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/Ethernet_Phy/ETH_RXD2" +Na 69 "/Ethernet_Phy/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/Ethernet_Phy/ETH_RXD3" +Na 70 "/Ethernet_Phy/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/Ethernet_Phy/ETH_RXER" +Na 71 "/Ethernet_Phy/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT @@ -383,135 +383,135 @@ Na 76 "/Ethernet_Phy/MAG_TX-" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS" +Na 77 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" +Na 78 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" +Na 79 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" +Na 80 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV" +Na 81 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" +Na 82 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" +Na 83 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" +Na 84 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" +Na 85 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" +Na 86 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" +Na 87 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER" +Na 88 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" +Na 89 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" +Na 90 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" +Na 91 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" +Na 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_15" +Na 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" +Na 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_30" +Na 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32" +Na 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" +Na 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_28" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" +Na 98 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" +Na 99 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" +Na 100 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_34" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_45" +Na 101 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_38" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" +Na 102 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" +Na 103 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_49" +Na 104 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_5" +Na 105 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50" +Na 106 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_51" +Na 107 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52" +Na 108 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_53" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56" +Na 109 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_54" St ~ $EndEQUIPOT $EQUIPOT @@ -519,67 +519,67 @@ Na 110 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_57" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_58" +Na 111 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6" +Na 112 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_60" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_60" +Na 113 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_62" +Na 114 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_63" +Na 115 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_7" +Na 116 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" +Na 117 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0" +Na 118 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1" +Na 119 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10" +Na 120 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11" +Na 121 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" +Na 122 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5" +Na 123 "/FPGA,_Port0,_Port2,_PROG_IF/IS_I2C_ADDR" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" +Na 124 "/FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" +Na 125 "/FPGA,_Port0,_Port2,_PROG_IF/IS_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N" +Na 126 "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" St ~ $EndEQUIPOT $EQUIPOT @@ -587,11 +587,11 @@ Na 127 "/FPGA,_Port0,_Port2,_PROG_IF/IS_SDA" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA,_Port0,_Port2,_PROG_IF/NF_ALE" +Na 128 "/FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CLE" +Na 129 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT @@ -603,27 +603,27 @@ Na 131 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" +Na 132 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" +Na 133 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" +Na 134 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" +Na 135 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" +Na 136 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" +Na 137 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT @@ -655,27 +655,27 @@ Na 144 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/FPGA,_Port0,_Port2,_PROG_IF/SD_CLK" +Na 145 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/FPGA,_Port0,_Port2,_PROG_IF/SD_CMD" +Na 146 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" +Na 147 "/FPGA_GPIOS/FPGA_BANK0_IO_1" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT3" +Na 148 "/FPGA_GPIOS/FPGA_BANK0_IO_10" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/FPGA_GPIOS/FPGA_BANK0_IO_10" +Na 149 "/FPGA_GPIOS/FPGA_BANK0_IO_14" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/FPGA_GPIOS/FPGA_BANK0_IO_17" +Na 150 "/FPGA_GPIOS/FPGA_BANK0_IO_15" St ~ $EndEQUIPOT $EQUIPOT @@ -687,659 +687,659 @@ Na 152 "/FPGA_GPIOS/FPGA_BANK0_IO_2" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/FPGA_GPIOS/FPGA_BANK0_IO_20" +Na 153 "/FPGA_GPIOS/FPGA_BANK0_IO_22" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/FPGA_GPIOS/FPGA_BANK0_IO_21" +Na 154 "/FPGA_GPIOS/FPGA_BANK0_IO_24" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/FPGA_GPIOS/FPGA_BANK0_IO_24" +Na 155 "/FPGA_GPIOS/FPGA_BANK0_IO_25" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/FPGA_GPIOS/FPGA_BANK0_IO_25" +Na 156 "/FPGA_GPIOS/FPGA_BANK0_IO_27" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/FPGA_GPIOS/FPGA_BANK0_IO_27" +Na 157 "/FPGA_GPIOS/FPGA_BANK0_IO_3" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/FPGA_GPIOS/FPGA_BANK0_IO_28" +Na 158 "/FPGA_GPIOS/FPGA_BANK0_IO_30" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/FPGA_GPIOS/FPGA_BANK0_IO_29" +Na 159 "/FPGA_GPIOS/FPGA_BANK0_IO_32" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/FPGA_GPIOS/FPGA_BANK0_IO_3" +Na 160 "/FPGA_GPIOS/FPGA_BANK0_IO_36" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/FPGA_GPIOS/FPGA_BANK0_IO_34" +Na 161 "/FPGA_GPIOS/FPGA_BANK0_IO_44" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/FPGA_GPIOS/FPGA_BANK0_IO_38" +Na 162 "/FPGA_GPIOS/FPGA_BANK0_IO_45" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/FPGA_GPIOS/FPGA_BANK0_IO_39" +Na 163 "/FPGA_GPIOS/FPGA_BANK0_IO_47" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/FPGA_GPIOS/FPGA_BANK0_IO_43" +Na 164 "/FPGA_GPIOS/FPGA_BANK0_IO_49" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/FPGA_GPIOS/FPGA_BANK0_IO_46" +Na 165 "/FPGA_GPIOS/FPGA_BANK0_IO_5" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/FPGA_GPIOS/FPGA_BANK0_IO_53" +Na 166 "/FPGA_GPIOS/FPGA_BANK0_IO_50" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/FPGA_GPIOS/FPGA_BANK0_IO_54" +Na 167 "/FPGA_GPIOS/FPGA_BANK0_IO_51" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/FPGA_GPIOS/FPGA_BANK0_IO_8" +Na 168 "/FPGA_GPIOS/FPGA_BANK0_IO_56" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" +Na 169 "/FPGA_GPIOS/FPGA_BANK0_IO_58" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" +Na 170 "/FPGA_GPIOS/FPGA_BANK0_IO_62" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A10" +Na 171 "/FPGA_GPIOS/FPGA_BANK0_IO_63" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A11" +Na 172 "/FPGA_GPIOS/FPGA_BANK0_IO_7" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" +Na 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A4" +Na 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" +Na 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A8" +Na 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0" +Na 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" +Na 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" +Na 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 180 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" +Na 180 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" +Na 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11" +Na 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" +Na 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" +Na 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" +Na 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" +Na 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" +Na 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" +Na 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5" +Na 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" +Na 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9" +Na 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" +Na 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" +Na 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" +Na 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" +Na 195 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A11" +Na 196 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" +Na 197 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" +Na 198 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" +Na 199 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" +Na 200 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 201 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" +Na 201 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 202 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" +Na 202 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 203 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1" +Na 203 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 204 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" +Na 204 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 205 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" +Na 205 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 206 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" +Na 206 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 207 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" +Na 207 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 208 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" +Na 208 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 209 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" +Na 209 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 210 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14" +Na 210 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 211 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15" +Na 211 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 212 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" +Na 212 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 213 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" +Na 213 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 214 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7" +Na 214 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 215 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" +Na 215 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 216 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9" +Na 216 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 217 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_LDM" +Na 217 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 218 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS#" +Na 218 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 219 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" +Na 219 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 220 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0" +Na 220 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 221 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1" +Na 221 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 222 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10" +Na 222 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 223 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11" +Na 223 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 224 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12" +Na 224 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 225 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2" +Na 225 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 226 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3" +Na 226 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 227 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4" +Na 227 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 228 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5" +Na 228 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 229 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6" +Na 229 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 230 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7" +Na 230 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 231 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8" +Na 231 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 232 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9" +Na 232 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 233 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0" +Na 233 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 234 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1" +Na 234 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 235 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS#" +Na 235 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 236 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE" +Na 236 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 237 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0" +Na 237 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 238 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1" +Na 238 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 239 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10" +Na 239 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 240 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11" +Na 240 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 241 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12" +Na 241 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 242 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13" +Na 242 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 243 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14" +Na 243 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 244 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15" +Na 244 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 245 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2" +Na 245 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 246 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3" +Na 246 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 247 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4" +Na 247 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 248 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5" +Na 248 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 249 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6" +Na 249 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 250 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7" +Na 250 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 251 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8" +Na 251 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 252 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9" +Na 252 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 253 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM" +Na 253 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 254 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS" +Na 254 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 255 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS#" +Na 255 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 256 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM" +Na 256 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 257 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS" +Na 257 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 258 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE#" +Na 258 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 259 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0" +Na 259 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 260 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1" +Na 260 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 261 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10" +Na 261 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 262 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11" +Na 262 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 263 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12" +Na 263 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 264 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2" +Na 264 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 265 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3" +Na 265 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 266 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4" +Na 266 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 267 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5" +Na 267 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 268 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6" +Na 268 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 269 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7" +Na 269 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 270 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8" +Na 270 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 271 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9" +Na 271 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 272 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0" +Na 272 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 273 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1" +Na 273 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 274 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS#" +Na 274 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 275 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE" +Na 275 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 276 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS#" +Na 276 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 277 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0" +Na 277 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 278 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1" +Na 278 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 279 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10" +Na 279 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 280 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11" +Na 280 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 281 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12" +Na 281 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 282 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13" +Na 282 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 283 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14" +Na 283 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 284 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15" +Na 284 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 285 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2" +Na 285 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 286 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3" +Na 286 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 287 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4" +Na 287 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 288 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5" +Na 288 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 289 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6" +Na 289 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 290 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7" +Na 290 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 291 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8" +Na 291 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 292 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9" +Na 292 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 293 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM" +Na 293 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 294 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS" +Na 294 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 295 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS#" +Na 295 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 296 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM" +Na 296 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 297 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS" +Na 297 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 298 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE#" +Na 298 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 299 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV" +Na 299 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 300 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N" +Na 300 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 301 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" +Na 301 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 302 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" +Na 302 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 303 "/Image_Sensor/+1.8_VDD" +Na 303 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 304 "/Image_Sensor/IS_DOUT2" +Na 304 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 305 "/Image_Sensor/IS_DOUT4" +Na 305 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 306 "/Image_Sensor/IS_DOUT6" +Na 306 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 307 "/Image_Sensor/IS_DOUT7" +Na 307 "/Image_Sensor/+1.8_VDD" St ~ $EndEQUIPOT $EQUIPOT -Na 308 "/Image_Sensor/IS_DOUT8" +Na 308 "/Image_Sensor/IS_DOUT0" St ~ $EndEQUIPOT $EQUIPOT -Na 309 "/Image_Sensor/IS_EXTCLK" +Na 309 "/Image_Sensor/IS_DOUT11" St ~ $EndEQUIPOT $EQUIPOT -Na 310 "/Image_Sensor/IS_FLASH" +Na 310 "/Image_Sensor/IS_DOUT4" St ~ $EndEQUIPOT $EQUIPOT -Na 311 "/Image_Sensor/IS_I2C_ADDR" +Na 311 "/Image_Sensor/IS_DOUT5" St ~ $EndEQUIPOT $EQUIPOT -Na 312 "/Image_Sensor/IS_LINE" +Na 312 "/Image_Sensor/IS_DOUT6" St ~ $EndEQUIPOT $EQUIPOT -Na 313 "/Image_Sensor/IS_PIXEL" +Na 313 "/Image_Sensor/IS_DOUT7" St ~ $EndEQUIPOT $EQUIPOT -Na 314 "/Image_Sensor/IS_RESET_N" +Na 314 "/Image_Sensor/IS_EXTCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 315 "/Image_Sensor/IS_SCL" +Na 315 "/Image_Sensor/IS_LINE" St ~ $EndEQUIPOT $EQUIPOT -Na 316 "/Image_Sensor/IS_STANDBY" +Na 316 "/Image_Sensor/IS_OE_N" St ~ $EndEQUIPOT $EQUIPOT @@ -1351,123 +1351,123 @@ Na 318 "/Image_Sensor/IS_TRIGGER" St ~ $EndEQUIPOT $EQUIPOT -Na 319 "/Non_volatile_memories/NF_CS1_N" +Na 319 "/Non_volatile_memories/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 320 "/Non_volatile_memories/NF_D0" +Na 320 "/Non_volatile_memories/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 321 "/Non_volatile_memories/NF_RNB" +Na 321 "/Non_volatile_memories/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 322 "/Non_volatile_memories/SD_DAT0" +Na 322 "/Non_volatile_memories/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 323 "/Non_volatile_memories/SD_DAT1" +Na 323 "/Non_volatile_memories/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 324 "/PSU/1.2V_EN" +Na 324 "/Non_volatile_memories/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 325 "/PSU/2.5V_EN" +Na 325 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 326 "/PSU/3.3V_EN" +Na 326 "/Non_volatile_memories/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 327 "/PSU/5V_EN" +Na 327 "/PSU/1.2V_EN" St ~ $EndEQUIPOT $EQUIPOT -Na 328 "/PSU/AVR_SCK" +Na 328 "/PSU/2.5V_EN" St ~ $EndEQUIPOT $EQUIPOT -Na 329 "/PSU/Iout_1.2" +Na 329 "/PSU/3.3V_EN" St ~ $EndEQUIPOT $EQUIPOT -Na 330 "/PSU/SW_1.2" +Na 330 "/PSU/5V_EN" St ~ $EndEQUIPOT $EQUIPOT -Na 331 "/PSU/SW_2.5" +Na 331 "/PSU/Iout_1.2" St ~ $EndEQUIPOT $EQUIPOT -Na 332 "/PSU/SW_3.3" +Na 332 "/PSU/SW_1.2" St ~ $EndEQUIPOT $EQUIPOT -Na 333 "/PSU/VFB1.2" +Na 333 "/PSU/SW_2.5" St ~ $EndEQUIPOT $EQUIPOT -Na 334 "/PSU/VFB2.5" +Na 334 "/PSU/SW_3.3" St ~ $EndEQUIPOT $EQUIPOT -Na 335 "/PSU/VFB3.3" +Na 335 "/PSU/VFB1.2" St ~ $EndEQUIPOT $EQUIPOT -Na 336 "/PSU/VFB5.0" +Na 336 "/PSU/VFB2.5" St ~ $EndEQUIPOT $EQUIPOT -Na 337 "/PSU/VIN_DC-DC-1.2" +Na 337 "/PSU/VFB3.3" St ~ $EndEQUIPOT $EQUIPOT -Na 338 "/PSU/VIN_DC-DC-3.3" +Na 338 "/PSU/VFB5.0" St ~ $EndEQUIPOT $EQUIPOT -Na 339 "/PSU/VIN_DC-DC-5.0" +Na 339 "/PSU/VIN_DC-DC-1.2" St ~ $EndEQUIPOT $EQUIPOT -Na 340 "/PSU/lout_2.5" +Na 340 "/PSU/VIN_DC-DC-3.3" St ~ $EndEQUIPOT $EQUIPOT -Na 341 "/PSU/lout_3.3" +Na 341 "/PSU/VIN_DC-DC-5.0" St ~ $EndEQUIPOT $EQUIPOT -Na 342 "/PSU/lout_5.0" +Na 342 "/PSU/lout_2.5" St ~ $EndEQUIPOT $EQUIPOT -Na 343 "/USB/USBA_D+" +Na 343 "/PSU/lout_3.3" St ~ $EndEQUIPOT $EQUIPOT -Na 344 "/USB/USBA_D-" +Na 344 "/PSU/lout_5.0" St ~ $EndEQUIPOT $EQUIPOT -Na 345 "/USB/USBA_OE_N" +Na 345 "/USB/USBA_D+" St ~ $EndEQUIPOT $EQUIPOT -Na 346 "/USB/USBA_SPD" +Na 346 "/USB/USBA_D-" St ~ $EndEQUIPOT $EQUIPOT -Na 347 "/USB/USBA_VM" +Na 347 "/USB/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 348 "/USB/USBA_VP" +Na 348 "/USB/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT @@ -1479,7 +1479,7 @@ Na 350 "/USB/USBD_D-" St ~ $EndEQUIPOT $EQUIPOT -Na 351 "/USB/USBD_RCV" +Na 351 "/USB/USBD_VM" St ~ $EndEQUIPOT $EQUIPOT @@ -1503,11 +1503,11 @@ Na 356 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 357 "N-000137" +Na 357 "N-000139" St ~ $EndEQUIPOT $EQUIPOT -Na 358 "N-000138" +Na 358 "N-000140" St ~ $EndEQUIPOT $EQUIPOT @@ -1747,6 +1747,7 @@ AddNet "/DBG_PRG/5V_USB" AddNet "/DBG_PRG/AVR_MISO" AddNet "/DBG_PRG/AVR_MOSI" AddNet "/DBG_PRG/AVR_RST" +AddNet "/DBG_PRG/AVR_SCK" AddNet "/DBG_PRG/FPGA_TCK" AddNet "/DBG_PRG/FPGA_TDI" AddNet "/DBG_PRG/FPGA_TDO" @@ -1755,120 +1756,114 @@ AddNet "/DBG_PRG/FTDI_USB_DM" AddNet "/DBG_PRG/FTDI_USB_DP" AddNet "/DBG_PRG/USB_CASE_FTDI" AddNet "/DBG_PRG/VCC_USB" -AddNet "/DDR_Banks/M0_A12" +AddNet "/DDR_Banks/M0_A10" +AddNet "/DDR_Banks/M0_A11" AddNet "/DDR_Banks/M0_A2" +AddNet "/DDR_Banks/M0_A4" AddNet "/DDR_Banks/M0_A5" -AddNet "/DDR_Banks/M0_A6" -AddNet "/DDR_Banks/M0_A9" -AddNet "/DDR_Banks/M0_CAS#" -AddNet "/DDR_Banks/M0_CKE" +AddNet "/DDR_Banks/M0_A8" AddNet "/DDR_Banks/M0_CLK#" -AddNet "/DDR_Banks/M0_DQ10" -AddNet "/DDR_Banks/M0_DQ2" +AddNet "/DDR_Banks/M0_DQ1" +AddNet "/DDR_Banks/M0_DQ5" AddNet "/DDR_Banks/M0_DQ7" -AddNet "/DDR_Banks/M0_DQ8" +AddNet "/DDR_Banks/M0_DQ9" AddNet "/DDR_Banks/M0_LDM" AddNet "/DDR_Banks/M0_LDQS" -AddNet "/DDR_Banks/M0_UDM" -AddNet "/DDR_Banks/M0_UDQS" AddNet "/DDR_Banks/M0_VREF" AddNet "/DDR_Banks/M1_A0" +AddNet "/DDR_Banks/M1_A1" +AddNet "/DDR_Banks/M1_A11" AddNet "/DDR_Banks/M1_A12" -AddNet "/DDR_Banks/M1_A2" +AddNet "/DDR_Banks/M1_A5" AddNet "/DDR_Banks/M1_A7" -AddNet "/DDR_Banks/M1_A9" -AddNet "/DDR_Banks/M1_CLK" +AddNet "/DDR_Banks/M1_BA1" AddNet "/DDR_Banks/M1_CLK#" -AddNet "/DDR_Banks/M1_CS#" AddNet "/DDR_Banks/M1_DQ0" -AddNet "/DDR_Banks/M1_DQ12" -AddNet "/DDR_Banks/M1_DQ3" -AddNet "/DDR_Banks/M1_DQ4" -AddNet "/DDR_Banks/M1_DQ5" +AddNet "/DDR_Banks/M1_DQ10" +AddNet "/DDR_Banks/M1_DQ11" +AddNet "/DDR_Banks/M1_DQ13" +AddNet "/DDR_Banks/M1_DQ14" +AddNet "/DDR_Banks/M1_DQ15" +AddNet "/DDR_Banks/M1_DQ2" +AddNet "/DDR_Banks/M1_DQ7" +AddNet "/DDR_Banks/M1_LDM" AddNet "/DDR_Banks/M1_LDQS" +AddNet "/DDR_Banks/M1_RAS#" AddNet "/DDR_Banks/M1_UDM" AddNet "/DDR_Banks/M1_VREF" AddNet "/DDR_Banks/M1_WE#" AddNet "/Ethernet_Phy/ETH_A1.8V" AddNet "/Ethernet_Phy/ETH_A3.3V" -AddNet "/Ethernet_Phy/ETH_CLK" -AddNet "/Ethernet_Phy/ETH_COL" -AddNet "/Ethernet_Phy/ETH_INT" +AddNet "/Ethernet_Phy/ETH_CRS" AddNet "/Ethernet_Phy/ETH_LED0" AddNet "/Ethernet_Phy/ETH_LED1" -AddNet "/Ethernet_Phy/ETH_MDC" AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/ETH_RXD0" -AddNet "/Ethernet_Phy/ETH_RXD1" +AddNet "/Ethernet_Phy/ETH_RXC" AddNet "/Ethernet_Phy/ETH_RXD2" -AddNet "/Ethernet_Phy/ETH_RXD3" AddNet "/Ethernet_Phy/ETH_RXER" -AddNet "/Ethernet_Phy/MAG_RX+" -AddNet "/Ethernet_Phy/MAG_RX-" -AddNet "/Ethernet_Phy/MAG_SHIELD" -AddNet "/Ethernet_Phy/MAG_TX+" -AddNet "/Ethernet_Phy/MAG_TX-" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS" +AddNet "/Ethernet_Phy/ETH_TXD2" +AddNet "/Ethernet_Phy/ETH_TXER" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_INT" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_15" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_30" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_28" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_34" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_38" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_45" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_49" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_5" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_51" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_53" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_54" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_57" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_58" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_60" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_62" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_63" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_7" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_I2C_ADDR" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_RESET_N" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_SDA" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_ALE" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_CLE" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D1" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D2" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO" @@ -1876,80 +1871,82 @@ AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/SD_CLK" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/SD_CMD" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT3" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT1" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_1" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_10" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_17" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_14" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_15" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_18" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_2" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_20" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_21" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_22" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_24" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_25" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_27" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_28" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_29" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_3" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_34" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_38" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_39" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_43" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_46" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_53" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_54" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_8" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_30" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_32" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_36" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_44" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_45" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_47" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_49" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_5" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_50" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_51" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_56" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_58" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_62" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_63" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_7" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A10" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A11" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A12" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A4" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A6" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A8" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS#" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A11" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A2" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CS#" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_LDM" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS#" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1" @@ -2030,36 +2027,36 @@ AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS#" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE#" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" AddNet "/Image_Sensor/+1.8_VDD" -AddNet "/Image_Sensor/IS_DOUT2" +AddNet "/Image_Sensor/IS_DOUT0" +AddNet "/Image_Sensor/IS_DOUT11" AddNet "/Image_Sensor/IS_DOUT4" +AddNet "/Image_Sensor/IS_DOUT5" AddNet "/Image_Sensor/IS_DOUT6" AddNet "/Image_Sensor/IS_DOUT7" -AddNet "/Image_Sensor/IS_DOUT8" AddNet "/Image_Sensor/IS_EXTCLK" -AddNet "/Image_Sensor/IS_FLASH" -AddNet "/Image_Sensor/IS_I2C_ADDR" AddNet "/Image_Sensor/IS_LINE" -AddNet "/Image_Sensor/IS_PIXEL" -AddNet "/Image_Sensor/IS_RESET_N" -AddNet "/Image_Sensor/IS_SCL" -AddNet "/Image_Sensor/IS_STANDBY" +AddNet "/Image_Sensor/IS_OE_N" AddNet "/Image_Sensor/IS_TEST" AddNet "/Image_Sensor/IS_TRIGGER" -AddNet "/Non_volatile_memories/NF_CS1_N" +AddNet "/Non_volatile_memories/NF_ALE" +AddNet "/Non_volatile_memories/NF_CLE" AddNet "/Non_volatile_memories/NF_D0" -AddNet "/Non_volatile_memories/NF_RNB" -AddNet "/Non_volatile_memories/SD_DAT0" -AddNet "/Non_volatile_memories/SD_DAT1" +AddNet "/Non_volatile_memories/NF_D3" +AddNet "/Non_volatile_memories/SD_CLK" +AddNet "/Non_volatile_memories/SD_CMD" +AddNet "/Non_volatile_memories/SD_DAT2" +AddNet "/Non_volatile_memories/SD_DAT3" AddNet "/PSU/1.2V_EN" AddNet "/PSU/2.5V_EN" AddNet "/PSU/3.3V_EN" AddNet "/PSU/5V_EN" -AddNet "/PSU/AVR_SCK" AddNet "/PSU/Iout_1.2" AddNet "/PSU/SW_2.5" AddNet "/PSU/VFB1.2" @@ -2072,18 +2069,14 @@ AddNet "/PSU/VIN_DC-DC-5.0" AddNet "/PSU/lout_2.5" AddNet "/PSU/lout_3.3" AddNet "/PSU/lout_5.0" -AddNet "/USB/USBA_OE_N" -AddNet "/USB/USBA_SPD" +AddNet "/USB/USBA_RCV" AddNet "/USB/USBA_VM" -AddNet "/USB/USBA_VP" -AddNet "/USB/USBD_RCV" +AddNet "/USB/USBD_VM" AddNet "/USB/USBD_VP" AddNet "/USB/USB_CASE_DEV" AddNet "/USB/USB_CASE_HOST" -AddNet "AGND" -AddNet "GND" -AddNet "N-000137" -AddNet "N-000138" +AddNet "N-000139" +AddNet "N-000140" AddNet "N-000147" AddNet "N-000150" AddNet "N-000151" @@ -2170,6 +2163,21 @@ uViaDia 197 uViaDrill 79 $EndNCLASS $NCLASS +Name "ETH" +Desc "" +Clearance 98 +TrackWidth 79 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +AddNet "/Ethernet_Phy/MAG_RX+" +AddNet "/Ethernet_Phy/MAG_RX-" +AddNet "/Ethernet_Phy/MAG_SHIELD" +AddNet "/Ethernet_Phy/MAG_TX+" +AddNet "/Ethernet_Phy/MAG_TX-" +$EndNCLASS +$NCLASS Name "POWER" Desc "" Clearance 59 @@ -2184,6 +2192,8 @@ AddNet "+3.3V" AddNet "+5V" AddNet "/PSU/SW_1.2" AddNet "/PSU/SW_3.3" +AddNet "AGND" +AddNet "GND" $EndNCLASS $NCLASS Name "SDIO" @@ -2251,63 +2261,63 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/Ethernet_Phy/ETH_CLK" +Ne 77 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/Ethernet_Phy/ETH_RXD1" +Ne 84 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV" +Ne 86 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" +Ne 67 "/Ethernet_Phy/ETH_RXC" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" +Ne 90 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/Ethernet_Phy/ETH_COL" +Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/Ethernet_Phy/ETH_INT" +Ne 79 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" +Ne 134 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" +Ne 132 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" Po 196 -4133 $EndPAD $PAD @@ -2321,56 +2331,56 @@ $PAD Sh "A14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA,_Port0,_Port2,_PROG_IF/NF_ALE" +Ne 319 "/Non_volatile_memories/NF_ALE" Po 983 -4133 $EndPAD $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 321 "/Non_volatile_memories/NF_RNB" +Ne 137 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" +Ne 325 "/Non_volatile_memories/SD_DAT2" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA,_Port0,_Port2,_PROG_IF/SD_CLK" +Ne 323 "/Non_volatile_memories/SD_CLK" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 322 "/Non_volatile_memories/SD_DAT0" +Ne 145 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0" Po 2558 -4133 $EndPAD $PAD Sh "A19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DBG_PRG/FPGA_TDO" +Ne 19 "/DBG_PRG/FPGA_TDO" Po 2952 -4133 $EndPAD $PAD Sh "A20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 351 "/USB/USBD_RCV" +Ne 305 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV" Po 3346 -4133 $EndPAD $PAD Sh "A21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 300 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N" +Ne 304 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N" Po 3739 -4133 $EndPAD $PAD @@ -2419,7 +2429,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/Ethernet_Phy/ETH_RXD0" +Ne 83 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" Po -2165 -3739 $EndPAD $PAD @@ -2433,7 +2443,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/Ethernet_Phy/ETH_RXER" +Ne 69 "/Ethernet_Phy/ETH_RXER" Po -1377 -3739 $EndPAD $PAD @@ -2447,7 +2457,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS" +Ne 63 "/Ethernet_Phy/ETH_CRS" Po -590 -3739 $EndPAD $PAD @@ -2461,7 +2471,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" +Ne 322 "/Non_volatile_memories/NF_D3" Po 196 -3739 $EndPAD $PAD @@ -2475,7 +2485,7 @@ $PAD Sh "B14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CLE" +Ne 320 "/Non_volatile_memories/NF_CLE" Po 983 -3739 $EndPAD $PAD @@ -2489,7 +2499,7 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT3" +Ne 326 "/Non_volatile_memories/SD_DAT3" Po 1771 -3739 $EndPAD $PAD @@ -2503,7 +2513,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 323 "/Non_volatile_memories/SD_DAT1" +Ne 146 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -2517,7 +2527,7 @@ $PAD Sh "B20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 301 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" +Ne 306 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" Po 3346 -3739 $EndPAD $PAD @@ -2531,14 +2541,14 @@ $PAD Sh "B22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 302 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" +Ne 351 "/USB/USBD_VM" Po 4133 -3739 $EndPAD $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 223 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11" +Ne 225 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -2566,56 +2576,56 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/Ethernet_Phy/ETH_RXD3" +Ne 85 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/Ethernet_Phy/ETH_RXD2" +Ne 68 "/Ethernet_Phy/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" +Ne 82 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" +Ne 87 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" +Ne 89 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" +Ne 70 "/Ethernet_Phy/ETH_TXD2" Po -590 -3346 $EndPAD $PAD Sh "C11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" +Ne 133 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" Po -196 -3346 $EndPAD $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 320 "/Non_volatile_memories/NF_D0" +Ne 321 "/Non_volatile_memories/NF_D0" Po 196 -3346 $EndPAD $PAD @@ -2636,14 +2646,14 @@ $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" +Ne 136 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA,_Port0,_Port2,_PROG_IF/SD_CMD" +Ne 324 "/Non_volatile_memories/SD_CMD" Po 1771 -3346 $EndPAD $PAD @@ -2657,21 +2667,21 @@ $PAD Sh "C18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DBG_PRG/FPGA_TMS" +Ne 20 "/DBG_PRG/FPGA_TMS" Po 2558 -3346 $EndPAD $PAD Sh "C19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 345 "/USB/USBA_OE_N" +Ne 301 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N" Po 2952 -3346 $EndPAD $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 270 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8" +Ne 272 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -2685,21 +2695,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 271 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9" +Ne 273 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 224 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12" +Ne 226 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 236 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE" +Ne 238 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -2727,42 +2737,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" +Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/Ethernet_Phy/ETH_MDC" +Ne 80 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER" +Ne 71 "/Ethernet_Phy/ETH_TXER" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" +Ne 91 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" +Ne 88 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" +Ne 135 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" Po -196 -2952 $EndPAD $PAD @@ -2790,7 +2800,7 @@ $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 319 "/Non_volatile_memories/NF_CS1_N" +Ne 129 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N" Po 1377 -2952 $EndPAD $PAD @@ -2818,35 +2828,35 @@ $PAD Sh "D19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 348 "/USB/USBA_VP" +Ne 303 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP" Po 2952 -2952 $EndPAD $PAD Sh "D20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 347 "/USB/USBA_VM" +Ne 348 "/USB/USBA_VM" Po 3346 -2952 $EndPAD $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 275 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE" +Ne 277 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 263 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12" +Ne 265 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 232 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9" +Ne 234 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -2860,7 +2870,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8" +Ne 233 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -2965,7 +2975,7 @@ $PAD Sh "E18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DBG_PRG/FPGA_TDI" +Ne 18 "/DBG_PRG/FPGA_TDI" Po 2558 -2558 $EndPAD $PAD @@ -2979,7 +2989,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 269 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7" +Ne 271 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -2993,7 +3003,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 264 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2" +Ne 266 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -3007,14 +3017,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 258 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE#" +Ne 260 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 227 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4" +Ne 229 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -3105,14 +3115,14 @@ $PAD Sh "F16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 346 "/USB/USBA_SPD" +Ne 302 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD" Po 1771 -2165 $EndPAD $PAD Sh "F17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 299 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV" +Ne 347 "/USB/USBA_RCV" Po 2165 -2165 $EndPAD $PAD @@ -3126,35 +3136,35 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 262 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11" +Ne 264 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 266 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4" +Ne 268 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 259 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0" +Ne 261 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 260 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1" +Ne 262 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 234 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1" +Ne 236 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -3168,14 +3178,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 233 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0" +Ne 235 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10" +Ne 224 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -3252,7 +3262,7 @@ $PAD Sh "G15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DBG_PRG/FPGA_TCK" +Ne 17 "/DBG_PRG/FPGA_TCK" Po 1377 -1771 $EndPAD $PAD @@ -3280,14 +3290,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 261 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10" +Ne 263 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 265 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3" +Ne 267 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -3308,14 +3318,14 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1" +Ne 223 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 220 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0" +Ne 222 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0" Po -3739 -1377 $EndPAD $PAD @@ -3329,21 +3339,21 @@ $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" +Ne 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 225 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2" +Ne 227 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 230 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7" +Ne 232 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -3413,7 +3423,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 276 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS#" +Ne 278 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -3434,35 +3444,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 298 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE#" +Ne 300 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/DDR_Banks/M1_CLK" +Ne 211 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 295 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS#" +Ne 297 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 274 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS#" +Ne 276 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 248 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5" +Ne 250 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -3476,14 +3486,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 247 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4" +Ne 249 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6" +Ne 231 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6" Po -2952 -983 $EndPAD $PAD @@ -3574,7 +3584,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 272 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0" +Ne 274 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -3588,14 +3598,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/DDR_Banks/M1_CLK#" +Ne 46 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 287 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4" +Ne 289 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD @@ -3609,49 +3619,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 288 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5" +Ne 290 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 250 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7" +Ne 252 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 249 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6" +Ne 251 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 228 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5" +Ne 230 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 235 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS#" +Ne 237 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 255 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS#" +Ne 257 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 226 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3" +Ne 228 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3" Po -2165 -590 $EndPAD $PAD @@ -3728,7 +3738,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 273 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1" +Ne 275 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -3742,28 +3752,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 268 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6" +Ne 270 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 267 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5" +Ne 269 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 289 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6" +Ne 291 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 290 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7" +Ne 292 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -3784,14 +3794,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 254 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS" +Ne 256 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 253 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM" +Ne 255 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -3896,14 +3906,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 293 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM" +Ne 295 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 294 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS" +Ne 296 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -3924,21 +3934,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 246 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3" +Ne 248 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2" +Ne 247 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 256 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM" +Ne 258 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM" Po -3346 196 $EndPAD $PAD @@ -4057,28 +4067,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 296 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM" +Ne 298 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 285 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2" +Ne 287 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 286 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3" +Ne 288 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 238 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1" +Ne 240 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -4092,7 +4102,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 237 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0" +Ne 239 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -4211,7 +4221,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 277 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0" +Ne 279 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -4225,21 +4235,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 278 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1" +Ne 280 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 252 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9" +Ne 254 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8" +Ne 253 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -4372,21 +4382,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 291 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8" +Ne 293 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 292 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9" +Ne 294 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 240 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11" +Ne 242 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -4400,7 +4410,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 239 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10" +Ne 241 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -4442,7 +4452,7 @@ $PAD Sh "R9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_58" +Ne 169 "/FPGA_GPIOS/FPGA_BANK0_IO_58" Po -983 1377 $EndPAD $PAD @@ -4491,7 +4501,7 @@ $PAD Sh "R16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" +Ne 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" Po 1771 1377 $EndPAD $PAD @@ -4519,7 +4529,7 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 279 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10" +Ne 281 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -4533,7 +4543,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 280 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11" +Ne 282 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -4547,7 +4557,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS" +Ne 259 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -4582,14 +4592,14 @@ $PAD Sh "T7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_60" +Ne 112 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_60" Po -1771 1771 $EndPAD $PAD Sh "T8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/FPGA_GPIOS/FPGA_BANK0_IO_53" +Ne 108 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_53" Po -1377 1771 $EndPAD $PAD @@ -4617,7 +4627,7 @@ $PAD Sh "T12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_GPIOS/FPGA_BANK0_IO_34" +Ne 100 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_34" Po 196 1771 $EndPAD $PAD @@ -4631,21 +4641,21 @@ $PAD Sh "T14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" +Ne 160 "/FPGA_GPIOS/FPGA_BANK0_IO_36" Po 983 1771 $EndPAD $PAD Sh "T15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_7" +Ne 172 "/FPGA_GPIOS/FPGA_BANK0_IO_7" Po 1377 1771 $EndPAD $PAD Sh "T16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6" +Ne 111 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6" Po 1771 1771 $EndPAD $PAD @@ -4659,7 +4669,7 @@ $PAD Sh "T18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" +Ne 147 "/FPGA_GPIOS/FPGA_BANK0_IO_1" Po 2558 1771 $EndPAD $PAD @@ -4680,7 +4690,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 297 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS" +Ne 299 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -4694,7 +4704,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 242 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13" +Ne 244 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13" Po -4133 2165 $EndPAD $PAD @@ -4708,7 +4718,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 241 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12" +Ne 243 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -4729,7 +4739,7 @@ $PAD Sh "U6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_62" +Ne 170 "/FPGA_GPIOS/FPGA_BANK0_IO_62" Po -2165 2165 $EndPAD $PAD @@ -4743,21 +4753,21 @@ $PAD Sh "U8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/FPGA_GPIOS/FPGA_BANK0_IO_54" +Ne 109 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_54" Po -1377 2165 $EndPAD $PAD Sh "U9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_51" +Ne 167 "/FPGA_GPIOS/FPGA_BANK0_IO_51" Po -983 2165 $EndPAD $PAD Sh "U10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56" +Ne 168 "/FPGA_GPIOS/FPGA_BANK0_IO_56" Po -590 2165 $EndPAD $PAD @@ -4799,14 +4809,14 @@ $PAD Sh "U16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" +Ne 114 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" Po 1771 2165 $EndPAD $PAD Sh "U17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/FPGA_GPIOS/FPGA_BANK0_IO_8" +Ne 113 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8" Po 2165 2165 $EndPAD $PAD @@ -4827,7 +4837,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 281 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12" +Ne 283 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -4841,21 +4851,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 282 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13" +Ne 284 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 244 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15" +Ne 246 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 243 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14" +Ne 245 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -4876,7 +4886,7 @@ $PAD Sh "V5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_63" +Ne 171 "/FPGA_GPIOS/FPGA_BANK0_IO_63" Po -2558 2558 $EndPAD $PAD @@ -4890,7 +4900,7 @@ $PAD Sh "V7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_49" +Ne 164 "/FPGA_GPIOS/FPGA_BANK0_IO_49" Po -1771 2558 $EndPAD $PAD @@ -4904,7 +4914,7 @@ $PAD Sh "V9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52" +Ne 107 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52" Po -983 2558 $EndPAD $PAD @@ -4918,7 +4928,7 @@ $PAD Sh "V11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/FPGA_GPIOS/FPGA_BANK0_IO_43" +Ne 104 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" Po -196 2558 $EndPAD $PAD @@ -4946,7 +4956,7 @@ $PAD Sh "V15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/FPGA_GPIOS/FPGA_BANK0_IO_17" +Ne 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" Po 1377 2558 $EndPAD $PAD @@ -4960,21 +4970,21 @@ $PAD Sh "V17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" +Ne 149 "/FPGA_GPIOS/FPGA_BANK0_IO_14" Po 2165 2558 $EndPAD $PAD Sh "V18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" +Ne 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" Po 2558 2558 $EndPAD $PAD Sh "V19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_GPIOS/FPGA_BANK0_IO_10" +Ne 148 "/FPGA_GPIOS/FPGA_BANK0_IO_10" Po 2952 2558 $EndPAD $PAD @@ -4988,14 +4998,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 283 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14" +Ne 285 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 284 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15" +Ne 286 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -5051,56 +5061,56 @@ $PAD Sh "W8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" +Ne 106 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" Po -1377 2952 $EndPAD $PAD Sh "W9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50" +Ne 166 "/FPGA_GPIOS/FPGA_BANK0_IO_50" Po -983 2952 $EndPAD $PAD Sh "W10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/FPGA_GPIOS/FPGA_BANK0_IO_46" +Ne 105 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46" Po -590 2952 $EndPAD $PAD Sh "W11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" +Ne 161 "/FPGA_GPIOS/FPGA_BANK0_IO_44" Po -196 2952 $EndPAD $PAD Sh "W12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 309 "/Image_Sensor/IS_EXTCLK" +Ne 314 "/Image_Sensor/IS_EXTCLK" Po 196 2952 $EndPAD $PAD Sh "W13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_GPIOS/FPGA_BANK0_IO_27" +Ne 156 "/FPGA_GPIOS/FPGA_BANK0_IO_27" Po 590 2952 $EndPAD $PAD Sh "W14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_30" +Ne 158 "/FPGA_GPIOS/FPGA_BANK0_IO_30" Po 983 2952 $EndPAD $PAD Sh "W15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/FPGA_GPIOS/FPGA_BANK0_IO_25" +Ne 155 "/FPGA_GPIOS/FPGA_BANK0_IO_25" Po 1377 2952 $EndPAD $PAD @@ -5114,7 +5124,7 @@ $PAD Sh "W17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_15" +Ne 150 "/FPGA_GPIOS/FPGA_BANK0_IO_15" Po 2165 2952 $EndPAD $PAD @@ -5177,70 +5187,70 @@ $PAD Sh "Y4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N" +Ne 316 "/Image_Sensor/IS_OE_N" Po -2952 3346 $EndPAD $PAD Sh "Y5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 316 "/Image_Sensor/IS_STANDBY" +Ne 128 "/FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY" Po -2558 3346 $EndPAD $PAD Sh "Y6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10" +Ne 116 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10" Po -2165 3346 $EndPAD $PAD Sh "Y7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" +Ne 120 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" Po -1771 3346 $EndPAD $PAD Sh "Y8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 306 "/Image_Sensor/IS_DOUT6" +Ne 312 "/Image_Sensor/IS_DOUT6" Po -1377 3346 $EndPAD $PAD Sh "Y9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_45" +Ne 162 "/FPGA_GPIOS/FPGA_BANK0_IO_45" Po -983 3346 $EndPAD $PAD Sh "Y10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" +Ne 163 "/FPGA_GPIOS/FPGA_BANK0_IO_47" Po -590 3346 $EndPAD $PAD Sh "Y11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" +Ne 103 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" Po -196 3346 $EndPAD $PAD Sh "Y12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 315 "/Image_Sensor/IS_SCL" +Ne 126 "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" Po 196 3346 $EndPAD $PAD Sh "Y13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_GPIOS/FPGA_BANK0_IO_38" +Ne 101 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_38" Po 590 3346 $EndPAD $PAD @@ -5254,35 +5264,35 @@ $PAD Sh "Y15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32" +Ne 159 "/FPGA_GPIOS/FPGA_BANK0_IO_32" Po 1377 3346 $EndPAD $PAD Sh "Y16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/FPGA_GPIOS/FPGA_BANK0_IO_24" +Ne 154 "/FPGA_GPIOS/FPGA_BANK0_IO_24" Po 1771 3346 $EndPAD $PAD Sh "Y17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_GPIOS/FPGA_BANK0_IO_20" +Ne 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20" Po 2165 3346 $EndPAD $PAD Sh "Y18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_5" +Ne 165 "/FPGA_GPIOS/FPGA_BANK0_IO_5" Po 2558 3346 $EndPAD $PAD Sh "Y19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/FPGA_GPIOS/FPGA_BANK0_IO_3" +Ne 157 "/FPGA_GPIOS/FPGA_BANK0_IO_3" Po 2952 3346 $EndPAD $PAD @@ -5317,7 +5327,7 @@ $PAD Sh "AA2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 312 "/Image_Sensor/IS_LINE" +Ne 315 "/Image_Sensor/IS_LINE" Po -3739 3739 $EndPAD $PAD @@ -5359,7 +5369,7 @@ $PAD Sh "AA8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "/Image_Sensor/IS_DOUT7" +Ne 313 "/Image_Sensor/IS_DOUT7" Po -1377 3739 $EndPAD $PAD @@ -5373,7 +5383,7 @@ $PAD Sh "AA10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 305 "/Image_Sensor/IS_DOUT4" +Ne 310 "/Image_Sensor/IS_DOUT4" Po -590 3739 $EndPAD $PAD @@ -5387,7 +5397,7 @@ $PAD Sh "AA12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1" +Ne 115 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1" Po 196 3739 $EndPAD $PAD @@ -5401,7 +5411,7 @@ $PAD Sh "AA14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" +Ne 153 "/FPGA_GPIOS/FPGA_BANK0_IO_22" Po 983 3739 $EndPAD $PAD @@ -5415,7 +5425,7 @@ $PAD Sh "AA16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_GPIOS/FPGA_BANK0_IO_28" +Ne 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_28" Po 1771 3739 $EndPAD $PAD @@ -5471,84 +5481,84 @@ $PAD Sh "AB2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" +Ne 122 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" Po -3739 4133 $EndPAD $PAD Sh "AB3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 310 "/Image_Sensor/IS_FLASH" +Ne 121 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" Po -3346 4133 $EndPAD $PAD Sh "AB4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 311 "/Image_Sensor/IS_I2C_ADDR" +Ne 123 "/FPGA,_Port0,_Port2,_PROG_IF/IS_I2C_ADDR" Po -2952 4133 $EndPAD $PAD Sh "AB5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 314 "/Image_Sensor/IS_RESET_N" +Ne 125 "/FPGA,_Port0,_Port2,_PROG_IF/IS_RESET_N" Po -2558 4133 $EndPAD $PAD Sh "AB6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 313 "/Image_Sensor/IS_PIXEL" +Ne 124 "/FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL" Po -2165 4133 $EndPAD $PAD Sh "AB7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11" +Ne 309 "/Image_Sensor/IS_DOUT11" Po -1771 4133 $EndPAD $PAD Sh "AB8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 308 "/Image_Sensor/IS_DOUT8" +Ne 119 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8" Po -1377 4133 $EndPAD $PAD Sh "AB9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5" +Ne 311 "/Image_Sensor/IS_DOUT5" Po -983 4133 $EndPAD $PAD Sh "AB10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" +Ne 118 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" Po -590 4133 $EndPAD $PAD Sh "AB11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 304 "/Image_Sensor/IS_DOUT2" +Ne 117 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2" Po -196 4133 $EndPAD $PAD Sh "AB12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0" +Ne 308 "/Image_Sensor/IS_DOUT0" Po 196 4133 $EndPAD $PAD Sh "AB13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/FPGA_GPIOS/FPGA_BANK0_IO_39" +Ne 102 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39" Po 590 4133 $EndPAD $PAD @@ -5562,21 +5572,21 @@ $PAD Sh "AB15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" +Ne 99 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" Po 1377 4133 $EndPAD $PAD Sh "AB16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/FPGA_GPIOS/FPGA_BANK0_IO_29" +Ne 98 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29" Po 1771 4133 $EndPAD $PAD Sh "AB17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_GPIOS/FPGA_BANK0_IO_21" +Ne 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" Po 2165 4133 $EndPAD $PAD @@ -5640,7 +5650,7 @@ $PAD Sh "1" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 325 "/PSU/2.5V_EN" +Ne 328 "/PSU/2.5V_EN" Po -393 491 $EndPAD $PAD @@ -5661,14 +5671,14 @@ $PAD Sh "9" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 334 "/PSU/VFB2.5" +Ne 336 "/PSU/VFB2.5" Po -196 -491 $EndPAD $PAD Sh "3" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 331 "/PSU/SW_2.5" +Ne 333 "/PSU/SW_2.5" Po 0 491 $EndPAD $PAD @@ -5682,7 +5692,7 @@ $PAD Sh "4" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 331 "/PSU/SW_2.5" +Ne 333 "/PSU/SW_2.5" Po 196 491 $EndPAD $PAD @@ -5780,14 +5790,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 256 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM" +Ne 258 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M0_UDM" +Ne 198 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5808,14 +5818,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 257 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS" +Ne 259 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M0_UDQS" +Ne 199 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5836,14 +5846,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 236 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE" +Ne 238 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Banks/M0_CKE" +Ne 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5864,7 +5874,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" +Ne 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" Po -176 0 $EndPAD $PAD @@ -5890,56 +5900,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 220 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0" +Ne 222 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 221 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1" +Ne 223 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 225 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2" +Ne 227 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 226 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3" +Ne 228 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" +Ne 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M0_A2" +Ne 27 "/DDR_Banks/M0_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" +Ne 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" +Ne 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5958,56 +5968,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 255 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS#" +Ne 257 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 233 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0" +Ne 235 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 234 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1" +Ne 236 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 222 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10" +Ne 224 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A10" +Ne 25 "/DDR_Banks/M0_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" +Ne 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0" +Ne 180 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" +Ne 197 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6026,56 +6036,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 230 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7" +Ne 232 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6" +Ne 231 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 228 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5" +Ne 230 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 227 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4" +Ne 229 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A4" +Ne 28 "/DDR_Banks/M0_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Banks/M0_A5" +Ne 29 "/DDR_Banks/M0_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Banks/M0_A6" +Ne 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" +Ne 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6094,56 +6104,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 224 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12" +Ne 226 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 223 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11" +Ne 225 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 232 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9" +Ne 234 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8" +Ne 233 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A8" +Ne 30 "/DDR_Banks/M0_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M0_A9" +Ne 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 172 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A11" +Ne 26 "/DDR_Banks/M0_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Banks/M0_A12" +Ne 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6162,28 +6172,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 247 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4" +Ne 249 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 248 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5" +Ne 250 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 249 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6" +Ne 251 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 250 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7" +Ne 252 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7" Po 295 -177 $EndPAD $PAD @@ -6197,21 +6207,21 @@ $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" +Ne 195 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5" +Ne 33 "/DDR_Banks/M0_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" +Ne 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6230,56 +6240,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 237 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0" +Ne 239 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 238 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1" +Ne 240 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 245 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2" +Ne 247 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 246 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3" +Ne 248 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" +Ne 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M0_DQ2" +Ne 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" +Ne 32 "/DDR_Banks/M0_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 180 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" +Ne 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6298,56 +6308,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 251 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8" +Ne 253 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 252 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9" +Ne 254 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ9" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 239 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10" +Ne 241 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 240 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11" +Ne 242 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11" +Ne 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Banks/M0_DQ10" +Ne 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9" +Ne 35 "/DDR_Banks/M0_DQ9" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/DDR_Banks/M0_DQ8" +Ne 196 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6366,67 +6376,67 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 241 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12" +Ne 243 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 242 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13" +Ne 244 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 243 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14" +Ne 245 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 244 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15" +Ne 246 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" +Ne 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" +Ne 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" +Ne 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" +Ne 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 $MODULE MLF20m1 -Po 59571 22413 900 15 4C811AD1 4C85911B ~~ +Po 59571 22413 900 15 4CDDC08F 4C85911B ~~ Li MLF20m1 Sc 4C85911B AR /4C69ED5F/4C69EE11 Op 0 0 0 At SMD -T0 1026 -701 200 200 900 40 N V 25 N"U9" +T0 -1040 16 200 200 1800 40 N V 25 N"U9" T1 0 150 200 200 900 40 N I 25 N"ATTINY24A-MLF" DC -866 -866 -866 -944 39 21 DS -787 787 -787 -787 39 21 @@ -6465,28 +6475,28 @@ $PAD Sh "15" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 327 "/PSU/5V_EN" +Ne 330 "/PSU/5V_EN" Po -393 688 $EndPAD $PAD Sh "1" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 328 "/PSU/AVR_SCK" +Ne 16 "/DBG_PRG/AVR_SCK" Po -393 -688 $EndPAD $PAD Sh "14" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 342 "/PSU/lout_5.0" +Ne 344 "/PSU/lout_5.0" Po -196 688 $EndPAD $PAD Sh "2" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 329 "/PSU/Iout_1.2" +Ne 331 "/PSU/Iout_1.2" Po -196 -688 $EndPAD $PAD @@ -6500,35 +6510,35 @@ $PAD Sh "3" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 324 "/PSU/1.2V_EN" +Ne 327 "/PSU/1.2V_EN" Po 0 -688 $EndPAD $PAD Sh "12" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 325 "/PSU/2.5V_EN" +Ne 328 "/PSU/2.5V_EN" Po 196 688 $EndPAD $PAD Sh "4" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "/PSU/lout_3.3" +Ne 343 "/PSU/lout_3.3" Po 196 -688 $EndPAD $PAD Sh "11" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 340 "/PSU/lout_2.5" +Ne 342 "/PSU/lout_2.5" Po 393 688 $EndPAD $PAD Sh "5" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 326 "/PSU/3.3V_EN" +Ne 329 "/PSU/3.3V_EN" Po 393 -688 $EndPAD $PAD @@ -6619,14 +6629,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 297 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS" +Ne 299 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 219 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" +Ne 221 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6647,14 +6657,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 276 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS#" +Ne 278 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 48 "/DDR_Banks/M1_CS#" +Ne 212 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6675,14 +6685,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 275 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE" +Ne 277 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 205 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" +Ne 210 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6703,14 +6713,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 296 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM" +Ne 298 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 55 "/DDR_Banks/M1_UDM" +Ne 58 "/DDR_Banks/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6729,56 +6739,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 211 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15" +Ne 52 "/DDR_Banks/M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 210 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14" +Ne 51 "/DDR_Banks/M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 209 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" +Ne 50 "/DDR_Banks/M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 50 "/DDR_Banks/M1_DQ12" +Ne 214 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 281 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12" +Ne 283 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 282 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13" +Ne 284 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 283 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14" +Ne 285 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 284 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15" +Ne 286 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6797,56 +6807,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 208 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" +Ne 49 "/DDR_Banks/M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 207 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" +Ne 48 "/DDR_Banks/M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 216 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9" +Ne 220 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 215 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" +Ne 219 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 291 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8" +Ne 293 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 292 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9" +Ne 294 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 279 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10" +Ne 281 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 280 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11" +Ne 282 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6867,14 +6877,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/DDR_Banks/M1_CLK#" +Ne 46 "/DDR_Banks/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/DDR_Banks/M1_CLK" +Ne 211 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6900,49 +6910,49 @@ $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 196 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A11" +Ne 41 "/DDR_Banks/M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 45 "/DDR_Banks/M1_A9" +Ne 207 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" +Ne 206 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 270 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8" +Ne 272 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 271 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9" +Ne 273 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 262 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11" +Ne 264 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 263 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12" +Ne 265 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6968,49 +6978,49 @@ $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 200 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" +Ne 205 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 199 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" +Ne 43 "/DDR_Banks/M1_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 198 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" +Ne 204 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 266 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4" +Ne 268 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 267 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5" +Ne 269 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 268 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6" +Ne 270 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 269 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7" +Ne 271 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -7029,56 +7039,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 277 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0" +Ne 279 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 278 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1" +Ne 280 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 285 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2" +Ne 287 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 286 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3" +Ne 288 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 51 "/DDR_Banks/M1_DQ3" +Ne 215 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 212 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" +Ne 53 "/DDR_Banks/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 206 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" +Ne 213 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 49 "/DDR_Banks/M1_DQ0" +Ne 47 "/DDR_Banks/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -7097,56 +7107,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 287 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4" +Ne 289 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 288 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5" +Ne 290 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 289 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6" +Ne 291 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 290 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7" +Ne 292 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 214 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7" +Ne 54 "/DDR_Banks/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 213 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" +Ne 218 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 53 "/DDR_Banks/M1_DQ5" +Ne 217 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 52 "/DDR_Banks/M1_DQ4" +Ne 216 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -7165,56 +7175,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 295 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS#" +Ne 297 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 272 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0" +Ne 274 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 273 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1" +Ne 275 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 261 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10" +Ne 263 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 195 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" +Ne 201 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 203 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1" +Ne 45 "/DDR_Banks/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 202 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" +Ne 208 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 218 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS#" +Ne 57 "/DDR_Banks/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -7233,56 +7243,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 259 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0" +Ne 261 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 260 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1" +Ne 262 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 264 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2" +Ne 266 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 265 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3" +Ne 267 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 197 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" +Ne 203 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/DDR_Banks/M1_A2" +Ne 202 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" +Ne 40 "/DDR_Banks/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/DDR_Banks/M1_A0" +Ne 39 "/DDR_Banks/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -7331,7 +7341,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 58 "/Ethernet_Phy/ETH_A1.8V" +Ne 61 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD @@ -7366,7 +7376,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 58 "/Ethernet_Phy/ETH_A1.8V" +Ne 61 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7511,7 +7521,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE SO8E -Po 58516 40232 2700 15 4CB499C6 4C65A75D ~~ +Po 58516 40232 2700 15 4CDDC03D 4C65A75D ~~ Li SO8E Cd module CMS SOJ 8 pins etroit Kw CMS SOJ @@ -7519,7 +7529,7 @@ Sc 4C65A75D AR /4C4227FE/4C65A75D Op 0 0 0 At SMD -T0 1323 469 315 315 3600 60 N V 21 N"U8" +T0 1181 24 315 315 3600 60 N V 21 N"U8" T1 0 400 350 350 2700 60 N I 21 N"X25X64MB" DS -1050 700 -1050 750 50 21 DS -1050 750 1050 750 50 21 @@ -7649,13 +7659,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 1210 -Po 55165 39594 1800 15 4C5FF890 4C656A80 ~~ +Po 55165 39594 1800 15 4CDDC037 4C656A80 ~~ Li 1210 Sc 4C656A80 AR /4C7BC2B2/4C656A80 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C39" +T0 4 -756 200 200 1800 40 N V 25 N"C39" T1 0 150 200 200 1800 40 N I 25 N"100uF" DS -798 542 -798 -542 50 21 DS -798 -542 798 -542 50 21 @@ -7705,13 +7715,13 @@ Po 570 0 $EndPAD $EndMODULE 1210 $MODULE 1210 -Po 51807 24819 900 15 4C5FF890 4C656CB7 ~~ +Po 51807 24819 900 15 4CDDC1A3 4C656CB7 ~~ Li 1210 Sc 4C656CB7 AR /4C7BC2B2/4C656CB7 Op 0 0 0 At SMD -T0 0 -150 200 200 900 40 N V 25 N"C41" +T0 36 -701 200 200 900 40 N V 25 N"C41" T1 0 150 200 200 900 40 N I 25 N"100uF" DS -798 542 -798 -542 50 21 DS -798 -542 798 -542 50 21 @@ -7733,13 +7743,13 @@ Po 570 0 $EndPAD $EndMODULE 1210 $MODULE 1210 -Po 61654 39882 0 15 4C5FF890 4C656D97 ~~ +Po 61654 39882 0 15 4CDDBFCB 4C656D97 ~~ Li 1210 Sc 4C656D97 AR /4C7BC2B2/4C656D97 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C54" +T0 -20 -662 200 200 0 40 N V 25 N"C54" T1 0 150 200 200 0 40 N I 25 N"100uF" DS -798 542 -798 -542 50 21 DS -798 -542 798 -542 50 21 @@ -7761,13 +7771,13 @@ Po 570 0 $EndPAD $EndMODULE 1210 $MODULE 1210 -Po 52700 39580 1800 15 4C5FF890 4CD36481 ~~ +Po 52700 39580 1800 15 4CDDC030 4CD36481 ~~ Li 1210 Sc 4CD36481 AR /4C7BC2B2/4C656D43 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C55" +T0 19 -747 200 200 1800 40 N V 25 N"C55" T1 0 150 200 200 1800 40 N I 25 N"100uF" DS -798 542 -798 -542 50 21 DS -798 -542 798 -542 50 21 @@ -7789,13 +7799,13 @@ Po 570 0 $EndPAD $EndMODULE 1210 $MODULE 1210 -Po 47000 29400 0 15 4C5FF890 4C656CF9 ~~ +Po 47000 29400 0 15 4CDDC2D7 4C656CF9 ~~ Li 1210 Sc 4C656CF9 AR /4C7BC2B2/4C656CF9 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C56" +T0 -12 -750 200 200 0 40 N V 25 N"C56" T1 0 150 200 200 0 40 N I 25 N"100uF" DS -798 542 -798 -542 50 21 DS -798 -542 798 -542 50 21 @@ -7873,13 +7883,13 @@ Po 373 0 $EndPAD $EndMODULE 0805 $MODULE 0805 -Po 60402 29224 0 15 4C5FF890 4C656CB9 ~~ +Po 60402 29224 0 15 4CDDC1D9 4C656CB9 ~~ Li 0805 Sc 4C656CB9 AR /4C7BC2B2/4C656CB9 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 21 N"C44" +T0 909 158 200 200 0 40 N V 21 N"C44" T1 0 150 200 200 0 40 N I 21 N"4.7uF" DS -561 305 -561 -305 50 21 DS -561 -305 561 -305 50 21 @@ -8573,13 +8583,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0603 -Po 60185 17402 2700 15 4C7AAF6E 4C6552B1 ~~ +Po 60185 17402 2700 15 4CDDC188 4C6552B1 ~~ Li 0603 Sc 4C6552B1 AR /4C5F1EDC/4C6552B1 Op 0 0 0 At SMD -T0 43 -370 200 200 2700 40 N V 25 N"L7" +T0 232 382 200 200 2700 40 N V 25 N"L7" T1 0 150 200 200 2700 40 N I 25 N"FB" DS -443 227 -443 -227 50 21 DS -443 -227 443 -227 50 21 @@ -8673,7 +8683,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 56 "/DDR_Banks/M1_VREF" +Ne 59 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD @@ -9044,7 +9054,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 56 "/DDR_Banks/M1_VREF" +Ne 59 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9065,7 +9075,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/DDR_Banks/M0_VREF" +Ne 38 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD @@ -9100,7 +9110,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/DDR_Banks/M0_VREF" +Ne 38 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9128,7 +9138,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 56 "/DDR_Banks/M1_VREF" +Ne 59 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9149,7 +9159,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 56 "/DDR_Banks/M1_VREF" +Ne 59 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD @@ -9177,7 +9187,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/DDR_Banks/M0_VREF" +Ne 38 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD @@ -9212,7 +9222,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/DDR_Banks/M0_VREF" +Ne 38 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9245,14 +9255,14 @@ $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 344 "/USB/USBA_D-" +Ne 346 "/USB/USBA_D-" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 343 "/USB/USBA_D+" +Ne 345 "/USB/USBA_D+" Po 0 -787 $EndPAD $PAD @@ -9320,13 +9330,13 @@ Po 570 0 $EndPAD $EndMODULE 1210 $MODULE 0603 -Po 47209 23642 0 15 4CD0CAEF 4C5D7F9F ~~ +Po 47209 23642 0 15 4CDDC207 4CDDBD18 ~~ Li 0603 -Sc 4C5D7F9F +Sc 4CDDBD18 AR /4C4320F3/4C5D7F9F Op 0 0 0 At SMD -T0 669 141 200 200 0 40 N V 25 N"C1" +T0 665 31 200 200 0 40 N V 25 N"C1" T1 0 150 200 200 0 40 N I 25 N"1uF" DS -443 227 -443 -227 50 21 DS -443 -227 443 -227 50 21 @@ -9348,13 +9358,13 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 46350 24551 900 15 4CD0CAE4 4C5D7FA5 ~~ +Po 46350 24551 900 15 4CDDC203 4C5D7FA5 ~~ Li 0603 Sc 4C5D7FA5 AR /4C4320F3/4C5D7FA5 Op 0 0 0 At SMD -T0 -677 -102 200 200 900 40 N V 25 N"C7" +T0 -689 -23 200 200 900 40 N V 25 N"C7" T1 0 150 200 200 900 40 N I 25 N"1uF" DS -443 227 -443 -227 50 21 DS -443 -227 443 -227 50 21 @@ -9364,7 +9374,7 @@ $PAD Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/Ethernet_Phy/ETH_A3.3V" +Ne 62 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD @@ -9420,7 +9430,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 343 "/USB/USBA_D+" +Ne 345 "/USB/USBA_D+" Po -294 0 $EndPAD $PAD @@ -9448,7 +9458,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 344 "/USB/USBA_D-" +Ne 346 "/USB/USBA_D-" Po -294 0 $EndPAD $PAD @@ -9588,7 +9598,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 58 "/Ethernet_Phy/ETH_A1.8V" +Ne 61 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD @@ -9600,13 +9610,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 47490 25089 900 0 4CDB6CA9 4C5D7FA7 ~~ +Po 47490 25089 900 0 4CDDC3B4 4C5D7FA7 ~~ Li 0402 Sc 4C5D7FA7 AR /4C4320F3/4C5D7FA7 Op 0 0 0 At SMD -T0 -151 349 200 200 900 40 M V 20 N"C8" +T0 140 392 200 200 1800 40 M V 20 N"C8" T1 0 -150 200 200 900 40 M I 20 N"100nF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -9616,7 +9626,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 59 "/Ethernet_Phy/ETH_A3.3V" +Ne 62 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD @@ -9656,13 +9666,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 49659 25484 1800 0 4C5FF890 4C5D7E41 ~~ +Po 49659 25484 1800 0 4CDDC39B 4C5D7E41 ~~ Li 0402 Sc 4C5D7E41 AR /4C4320F3/4C5D7E41 Op 0 0 0 At SMD -T0 0 150 200 200 1800 40 M V 20 N"C10" +T0 -187 -319 200 200 1800 40 M V 20 N"C10" T1 0 -150 200 200 1800 40 M I 20 N"100nF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -9728,7 +9738,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" +Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -9740,13 +9750,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 47043 25087 900 0 4CDB6CB3 4C5D7ECF ~~ +Po 47043 25087 900 0 4CDDC3AB 4C5D7ECF ~~ Li 0402 Sc 4C5D7ECF AR /4C4320F3/4C5D7ECF Op 0 0 0 At SMD -T0 -157 -319 200 200 900 40 M V 20 N"R2" +T0 130 -393 200 200 1800 40 M V 20 N"R2" T1 0 -150 200 200 900 40 M I 20 N"6.65K" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -9756,7 +9766,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 358 "N-000138" +Ne 358 "N-000140" Po -176 0 $EndPAD $PAD @@ -9824,7 +9834,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 47279 20272 0 0 4CDB6C81 4C5D7AF7 ~~ +Po 47957 19858 0 0 4CDB6C81 4C5D7AF7 ~~ Li 0402 Sc 4C5D7AF7 AR /4C4320F3/4C5D7AF7 @@ -9896,14 +9906,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 357 "N-000137" +Ne 357 "N-000139" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 63 "/Ethernet_Phy/ETH_LED0" +Ne 64 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9931,7 +9941,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 64 "/Ethernet_Phy/ETH_LED1" +Ne 65 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9960,7 +9970,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 180 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" +Ne 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -9974,14 +9984,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" +Ne 32 "/DDR_Banks/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M0_DQ2" +Ne 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -9995,14 +10005,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" +Ne 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" +Ne 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -10016,14 +10026,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5" +Ne 33 "/DDR_Banks/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" +Ne 195 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -10093,21 +10103,21 @@ $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" +Ne 200 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M0_CAS#" +Ne 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" +Ne 197 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" Po 1535 2176 $EndPAD $PAD @@ -10128,49 +10138,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0" +Ne 180 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" +Ne 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A10" +Ne 25 "/DDR_Banks/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" +Ne 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" +Ne 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M0_A2" +Ne 27 "/DDR_Banks/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" +Ne 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -10191,56 +10201,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A4" +Ne 28 "/DDR_Banks/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M0_A5" +Ne 29 "/DDR_Banks/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M0_A6" +Ne 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" +Ne 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A8" +Ne 30 "/DDR_Banks/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M0_A9" +Ne 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A11" +Ne 26 "/DDR_Banks/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M0_A12" +Ne 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -10261,21 +10271,21 @@ $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M0_CKE" +Ne 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" +Ne 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M0_UDM" +Ne 198 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -10289,7 +10299,7 @@ $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/DDR_Banks/M0_VREF" +Ne 38 "/DDR_Banks/M0_VREF" Po 255 -2176 $EndPAD $PAD @@ -10303,7 +10313,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M0_UDQS" +Ne 199 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS" Po -255 -2176 $EndPAD $PAD @@ -10324,7 +10334,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M0_DQ8" +Ne 196 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10338,14 +10348,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9" +Ne 35 "/DDR_Banks/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M0_DQ10" +Ne 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -10359,14 +10369,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11" +Ne 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" +Ne 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10380,14 +10390,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" +Ne 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" +Ne 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10401,7 +10411,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" +Ne 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10437,7 +10447,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/DDR_Banks/M1_DQ0" +Ne 47 "/DDR_Banks/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -10451,14 +10461,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 206 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" +Ne 213 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 212 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" +Ne 53 "/DDR_Banks/M1_DQ2" Po -3070 2176 $EndPAD $PAD @@ -10472,14 +10482,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/DDR_Banks/M1_DQ3" +Ne 215 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/DDR_Banks/M1_DQ4" +Ne 216 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -10493,14 +10503,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/DDR_Banks/M1_DQ5" +Ne 217 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 213 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" +Ne 218 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -10514,7 +10524,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 214 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7" +Ne 54 "/DDR_Banks/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -10535,7 +10545,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/DDR_Banks/M1_LDQS" +Ne 56 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -10563,35 +10573,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_LDM" +Ne 55 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/DDR_Banks/M1_WE#" +Ne 60 "/DDR_Banks/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 204 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" +Ne 209 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 218 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS#" +Ne 57 "/DDR_Banks/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/DDR_Banks/M1_CS#" +Ne 212 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -10605,49 +10615,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 202 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" +Ne 208 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 203 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1" +Ne 45 "/DDR_Banks/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 195 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" +Ne 201 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/DDR_Banks/M1_A0" +Ne 39 "/DDR_Banks/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" +Ne 40 "/DDR_Banks/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/DDR_Banks/M1_A2" +Ne 202 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 197 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" +Ne 203 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -10668,21 +10678,21 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 198 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" +Ne 204 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 199 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" +Ne 43 "/DDR_Banks/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 200 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" +Ne 205 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" Po 3326 -2176 $EndPAD $PAD @@ -10696,21 +10706,21 @@ $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" +Ne 206 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/DDR_Banks/M1_A9" +Ne 207 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 196 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A11" +Ne 41 "/DDR_Banks/M1_A11" Po 2303 -2176 $EndPAD $PAD @@ -10731,28 +10741,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/DDR_Banks/M1_CLK#" +Ne 46 "/DDR_Banks/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 205 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" +Ne 210 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/DDR_Banks/M1_CLK" +Ne 211 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/DDR_Banks/M1_UDM" +Ne 58 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD @@ -10766,7 +10776,7 @@ $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/DDR_Banks/M1_VREF" +Ne 59 "/DDR_Banks/M1_VREF" Po 255 -2176 $EndPAD $PAD @@ -10780,7 +10790,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 219 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" +Ne 221 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" Po -255 -2176 $EndPAD $PAD @@ -10801,7 +10811,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 215 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" +Ne 219 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10815,14 +10825,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 216 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9" +Ne 220 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 207 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" +Ne 48 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -10836,14 +10846,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 208 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" +Ne 49 "/DDR_Banks/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/DDR_Banks/M1_DQ12" +Ne 214 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10857,14 +10867,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 209 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" +Ne 50 "/DDR_Banks/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 210 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14" +Ne 51 "/DDR_Banks/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10878,7 +10888,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 211 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15" +Ne 52 "/DDR_Banks/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10996,7 +11006,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 357 "N-000137" +Ne 357 "N-000139" Po -1150 -5400 $EndPAD $PAD @@ -11015,12 +11025,12 @@ Po 2150 -5400 $EndPAD $EndMODULE SD-48025 $MODULE MICROSD-500901 -Po 62024 16291 0 0 4C5F34DA 4B76F5E2 ~~ +Po 62024 16291 0 0 4CDDC503 4B76F5E2 ~~ Li MICROSD-500901 Sc 4B76F5E2 AR /4C4227FE/4B76F5E2 Op 0 0 0 -T0 -160 652 157 157 0 20 M V 20 N"J1" +T0 3409 1099 394 394 0 39 M V 20 N"J1" T1 0 -118 118 118 1800 20 M I 20 N"MICROSD" DS -2709 -1675 -2709 507 60 20 DS -2707 -3095 -2707 -2747 60 20 @@ -11035,21 +11045,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 147 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" +Ne 325 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 148 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT3" +Ne 326 "/Non_volatile_memories/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 146 "/FPGA,_Port0,_Port2,_PROG_IF/SD_CMD" +Ne 324 "/Non_volatile_memories/SD_CMD" Po -433 0 $EndPAD $PAD @@ -11063,7 +11073,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 145 "/FPGA,_Port0,_Port2,_PROG_IF/SD_CLK" +Ne 323 "/Non_volatile_memories/SD_CLK" Po 433 0 $EndPAD $PAD @@ -11077,14 +11087,14 @@ $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 322 "/Non_volatile_memories/SD_DAT0" +Ne 145 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 323 "/Non_volatile_memories/SD_DAT1" +Ne 146 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT1" Po 1732 0 $EndPAD $PAD @@ -11117,12 +11127,12 @@ Po 2707 -2244 $EndPAD $EndMODULE MICROSD-500901 $MODULE NAND-48TSOP -Po 56780 26154 900 15 4C812695 4B76F108 ~~ +Po 56780 26154 900 15 4CDDC1BA 4B76F108 ~~ Li NAND-48TSOP Sc 4B76F108 AR /4C4227FE/4B76F108 Op 0 0 0 -T0 2603 -3197 157 157 0 20 N V 21 N"U5" +T0 2607 -2485 394 394 1800 39 N V 21 N"U5" T1 0 118 118 118 -900 20 N I 21 N"NAND" DS -2470 3900 -2470 -3900 60 24 DS -2470 -3900 2430 -3900 60 24 @@ -11376,28 +11386,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 321 "/Non_volatile_memories/NF_RNB" +Ne 137 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 321 "/Non_volatile_memories/NF_RNB" +Ne 137 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" +Ne 136 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 319 "/Non_volatile_memories/NF_CS1_N" +Ne 129 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -11446,14 +11456,14 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CLE" +Ne 320 "/Non_volatile_memories/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA,_Port0,_Port2,_PROG_IF/NF_ALE" +Ne 319 "/Non_volatile_memories/NF_ALE" Po 880 3850 $EndPAD $PAD @@ -11537,7 +11547,7 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 320 "/Non_volatile_memories/NF_D0" +Ne 321 "/Non_volatile_memories/NF_D0" Po 1470 -3850 $EndPAD $PAD @@ -11558,7 +11568,7 @@ $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" +Ne 322 "/Non_volatile_memories/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -11621,28 +11631,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" +Ne 132 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" +Ne 133 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" +Ne 134 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" +Ne 135 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -11675,13 +11685,13 @@ Po -2270 -3850 $EndPAD $EndMODULE NAND-48TSOP $MODULE LQFP48 -Po 48675 26272 900 15 4C433D64 4C432132 ~~ +Po 48675 26272 900 15 4CDDC2CD 4C432132 ~~ Li LQFP48 Sc 4C432132 AR /4C4320F3/4C432132 Op 0 0 0 At SMD -T0 0 -150 200 200 900 40 N V 25 N"U4" +T0 1689 1687 394 394 900 40 N V 25 N"U4" T1 0 150 200 200 900 40 N I 25 N"K8001" DC -1574 -1574 -1574 -1653 39 21 DS -1377 -1377 -1377 1377 39 21 @@ -11699,21 +11709,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/Ethernet_Phy/ETH_RXER" +Ne 69 "/Ethernet_Phy/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" +Ne 67 "/Ethernet_Phy/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV" +Ne 86 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV" Po -1613 491 $EndPAD $PAD @@ -11734,49 +11744,49 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/Ethernet_Phy/ETH_RXD0" +Ne 83 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/Ethernet_Phy/ETH_RXD1" +Ne 84 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/Ethernet_Phy/ETH_RXD2" +Ne 68 "/Ethernet_Phy/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/Ethernet_Phy/ETH_RXD3" +Ne 85 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/Ethernet_Phy/ETH_MDC" +Ne 80 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" +Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" +Ne 82 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD @@ -11790,7 +11800,7 @@ $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/Ethernet_Phy/ETH_CLK" +Ne 77 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -11846,35 +11856,35 @@ $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/Ethernet_Phy/ETH_A3.3V" +Ne 62 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 358 "N-000138" +Ne 358 "N-000140" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/Ethernet_Phy/ETH_INT" +Ne 79 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/Ethernet_Phy/ETH_LED0" +Ne 64 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/Ethernet_Phy/ETH_LED1" +Ne 65 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -11902,7 +11912,7 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/Ethernet_Phy/ETH_A1.8V" +Ne 61 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD @@ -11951,63 +11961,63 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER" +Ne 71 "/Ethernet_Phy/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" +Ne 87 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" +Ne 91 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" +Ne 88 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" +Ne 89 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" +Ne 70 "/Ethernet_Phy/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" +Ne 90 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/Ethernet_Phy/ETH_COL" +Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS" +Ne 63 "/Ethernet_Phy/ETH_CRS" Po 688 1613 $EndPAD $PAD @@ -12026,13 +12036,13 @@ Po 1082 1613 $EndPAD $EndMODULE LQFP48 $MODULE 1206 -Po 63750 39693 1800 15 4C5FF890 4C61D1D4 ~~ +Po 63750 39693 1800 15 4CDDBFD3 4C61D1D4 ~~ Li 1206 Sc 4C61D1D4 AR /4C421DD3/4C61D1D4 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C34" +T0 96 -590 200 200 1800 40 N V 25 N"C34" T1 0 150 200 200 1800 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -12054,14 +12064,14 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE SOT23-5 -Po 63665 25239 900 15 4C7AAFBC 4C6D2BAF ~~ +Po 63665 25239 900 15 4CDDC076 4C6D2BAF ~~ Li SOT23-5 Cd SOT23-5 Sc 4C6D2BAF AR /4C69ED5F/4C6D2AA5 Op 0 0 0 At SMD -T0 818 20 300 250 1800 50 N V 21 N"U11" +T0 -773 -31 300 250 1800 50 N V 21 N"U11" T1 0 150 300 250 900 50 N I 21 N"A7108" DS 600 -350 600 350 50 21 DS 600 350 -600 350 50 21 @@ -12071,21 +12081,21 @@ $PAD Sh "1" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 326 "/PSU/3.3V_EN" +Ne 329 "/PSU/3.3V_EN" Po -375 500 $EndPAD $PAD Sh "3" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 332 "/PSU/SW_3.3" +Ne 334 "/PSU/SW_3.3" Po 375 500 $EndPAD $PAD Sh "5" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 335 "/PSU/VFB3.3" +Ne 337 "/PSU/VFB3.3" Po -375 -500 $EndPAD $PAD @@ -12099,7 +12109,7 @@ $PAD Sh "4" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 338 "/PSU/VIN_DC-DC-3.3" +Ne 340 "/PSU/VIN_DC-DC-3.3" Po 375 -500 $EndPAD $SHAPE3D @@ -12110,14 +12120,14 @@ Ro 0.000000 0.000000 0.000000 $EndSHAPE3D $EndMODULE SOT23-5 $MODULE SOT23-5 -Po 63661 27289 900 15 4C7AAFC4 4C6D2BB1 ~~ +Po 63661 27289 900 15 4CDDC071 4C6D2BB1 ~~ Li SOT23-5 Cd SOT23-5 Sc 4C6D2BB1 AR /4C69ED5F/4C6D2AE0 Op 0 0 0 At SMD -T0 801 12 300 250 1800 50 N V 21 N"U12" +T0 -794 12 300 250 1800 50 N V 21 N"U12" T1 -63 -264 300 250 900 50 N I 21 N"A7108" DS 600 -350 600 350 50 21 DS 600 350 -600 350 50 21 @@ -12127,21 +12137,21 @@ $PAD Sh "1" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 324 "/PSU/1.2V_EN" +Ne 327 "/PSU/1.2V_EN" Po -375 500 $EndPAD $PAD Sh "3" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 330 "/PSU/SW_1.2" +Ne 332 "/PSU/SW_1.2" Po 375 500 $EndPAD $PAD Sh "5" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 333 "/PSU/VFB1.2" +Ne 335 "/PSU/VFB1.2" Po -375 -500 $EndPAD $PAD @@ -12155,7 +12165,7 @@ $PAD Sh "4" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 337 "/PSU/VIN_DC-DC-1.2" +Ne 339 "/PSU/VIN_DC-DC-1.2" Po 375 -500 $EndPAD $SHAPE3D @@ -12189,7 +12199,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 335 "/PSU/VFB3.3" +Ne 337 "/PSU/VFB3.3" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12210,7 +12220,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 335 "/PSU/VFB3.3" +Ne 337 "/PSU/VFB3.3" Po -176 0 $EndPAD $PAD @@ -12245,7 +12255,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 335 "/PSU/VFB3.3" +Ne 337 "/PSU/VFB3.3" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12329,7 +12339,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 333 "/PSU/VFB1.2" +Ne 335 "/PSU/VFB1.2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12350,7 +12360,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 333 "/PSU/VFB1.2" +Ne 335 "/PSU/VFB1.2" Po -176 0 $EndPAD $PAD @@ -12385,7 +12395,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 333 "/PSU/VFB1.2" +Ne 335 "/PSU/VFB1.2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12406,7 +12416,7 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 338 "/PSU/VIN_DC-DC-3.3" +Ne 340 "/PSU/VIN_DC-DC-3.3" Po -373 0 $EndPAD $PAD @@ -12434,7 +12444,7 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 337 "/PSU/VIN_DC-DC-1.2" +Ne 339 "/PSU/VIN_DC-DC-1.2" Po -373 0 $EndPAD $PAD @@ -12502,13 +12512,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1210 -Po 65039 25321 900 15 4C7AB0B9 4C6D3108 ~~ +Po 65039 25321 900 15 4CDDC055 4C6D3108 ~~ Li 1210 Sc 4C6D3108 AR /4C69ED5F/4C6D2E6A Op 0 0 0 At SMD -T0 -667 -696 200 200 900 40 N V 25 N"L8" +T0 -41 713 200 200 900 40 N V 25 N"L8" T1 0 150 200 200 900 40 N I 25 N"2.2uH" DS -798 542 -798 -542 50 21 DS -798 -542 798 -542 50 21 @@ -12525,18 +12535,18 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 332 "/PSU/SW_3.3" +Ne 334 "/PSU/SW_3.3" Po 570 0 $EndPAD $EndMODULE 1210 $MODULE 1210 -Po 65102 27289 900 15 4C7AB0B2 4C6D310A ~~ +Po 65102 27289 900 15 4CDDC059 4C6D310A ~~ Li 1210 Sc 4C6D310A AR /4C69ED5F/4C6D2FD1 Op 0 0 0 At SMD -T0 -672 -673 200 200 900 40 N V 25 N"L9" +T0 6 725 200 200 900 40 N V 25 N"L9" T1 0 150 200 200 900 40 N I 25 N"2.2uH" DS -798 542 -798 -542 50 21 DS -798 -542 798 -542 50 21 @@ -12553,7 +12563,7 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 330 "/PSU/SW_1.2" +Ne 332 "/PSU/SW_1.2" Po 570 0 $EndPAD $EndMODULE 1210 @@ -12581,7 +12591,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 59 "/Ethernet_Phy/ETH_A3.3V" +Ne 62 "/Ethernet_Phy/ETH_A3.3V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -12673,7 +12683,7 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 301 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" +Ne 306 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" Po -295 491 $EndPAD $PAD @@ -12687,7 +12697,7 @@ $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 351 "/USB/USBD_RCV" +Ne 305 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV" Po -98 491 $EndPAD $PAD @@ -12708,14 +12718,14 @@ $PAD Sh "9" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 300 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N" +Ne 304 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N" Po 295 -491 $EndPAD $PAD Sh "4" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 302 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" +Ne 351 "/USB/USBD_VM" Po 295 491 $EndPAD $PAD @@ -12807,7 +12817,7 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 346 "/USB/USBA_SPD" +Ne 302 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD" Po -295 491 $EndPAD $PAD @@ -12821,7 +12831,7 @@ $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 299 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV" +Ne 347 "/USB/USBA_RCV" Po -98 491 $EndPAD $PAD @@ -12835,21 +12845,21 @@ $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 348 "/USB/USBA_VP" +Ne 303 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP" Po 98 491 $EndPAD $PAD Sh "9" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 345 "/USB/USBA_OE_N" +Ne 301 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N" Po 295 -491 $EndPAD $PAD Sh "4" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 347 "/USB/USBA_VM" +Ne 348 "/USB/USBA_VM" Po 295 491 $EndPAD $PAD @@ -13162,12 +13172,12 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE ZX62D-B-5P8 -Po 62598 16157 1800 15 4BAADC40 4CB9D6F7 ~~ +Po 62598 16157 1800 15 4CDDC156 4CB9D6F7 ~~ Li ZX62D-B-5P8 Sc 4CB9D6F7 AR /4C5F1EDC/4C75F027 Op 0 0 0 -T0 446 -852 157 157 1800 20 N V 21 N"J7" +T0 -1650 -678 394 394 1800 39 N V 21 N"J7" T1 550 -500 118 118 1800 20 N I 21 N"ZX62D-B-5P8" DS -1690 2970 -1760 2970 100 21 DS -1760 2970 -1760 -630 100 21 @@ -13274,7 +13284,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 329 "/PSU/Iout_1.2" +Ne 331 "/PSU/Iout_1.2" Po -176 0 $EndPAD $PAD @@ -13302,7 +13312,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "/PSU/lout_3.3" +Ne 343 "/PSU/lout_3.3" Po -176 0 $EndPAD $PAD @@ -13314,13 +13324,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 1206 -Po 61677 26517 900 15 4C7C40B0 4C7712F5 ~~ +Po 61677 26517 900 15 4CDDC1EA 4C7712F5 ~~ Li 1206 Sc 4C7712F5 AR /4C69ED5F/4C770713 Op 0 0 0 At SMD -T0 -571 -523 200 200 900 40 N V 25 N"R34" +T0 -1113 114 200 200 900 40 N V 25 N"R34" T1 0 150 200 200 900 40 N I 25 N"R" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -13330,7 +13340,7 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 337 "/PSU/VIN_DC-DC-1.2" +Ne 339 "/PSU/VIN_DC-DC-1.2" Po -570 0 $EndPAD $PAD @@ -13358,7 +13368,7 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 338 "/PSU/VIN_DC-DC-3.3" +Ne 340 "/PSU/VIN_DC-DC-3.3" Po -570 0 $EndPAD $PAD @@ -13394,7 +13404,7 @@ $PAD Sh "6" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 337 "/PSU/VIN_DC-DC-1.2" +Ne 339 "/PSU/VIN_DC-DC-1.2" Po -196 153 $EndPAD $PAD @@ -13415,7 +13425,7 @@ $PAD Sh "3" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 329 "/PSU/Iout_1.2" +Ne 331 "/PSU/Iout_1.2" Po 196 -153 $EndPAD $PAD @@ -13451,7 +13461,7 @@ $PAD Sh "6" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 338 "/PSU/VIN_DC-DC-3.3" +Ne 340 "/PSU/VIN_DC-DC-3.3" Po -196 153 $EndPAD $PAD @@ -13472,7 +13482,7 @@ $PAD Sh "3" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "/PSU/lout_3.3" +Ne 343 "/PSU/lout_3.3" Po 196 -153 $EndPAD $PAD @@ -13501,7 +13511,7 @@ $PAD Sh "6" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 339 "/PSU/VIN_DC-DC-5.0" +Ne 341 "/PSU/VIN_DC-DC-5.0" Po -375 -500 $EndPAD $PAD @@ -13515,14 +13525,14 @@ $PAD Sh "4" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 327 "/PSU/5V_EN" +Ne 330 "/PSU/5V_EN" Po 375 -500 $EndPAD $PAD Sh "3" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 336 "/PSU/VFB5.0" +Ne 338 "/PSU/VFB5.0" Po 375 500 $EndPAD $PAD @@ -13563,14 +13573,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 327 "/PSU/5V_EN" +Ne 330 "/PSU/5V_EN" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 339 "/PSU/VIN_DC-DC-5.0" +Ne 341 "/PSU/VIN_DC-DC-5.0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13598,7 +13608,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 336 "/PSU/VFB5.0" +Ne 338 "/PSU/VFB5.0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13619,7 +13629,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 336 "/PSU/VFB5.0" +Ne 338 "/PSU/VFB5.0" Po -176 0 $EndPAD $PAD @@ -13654,7 +13664,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 336 "/PSU/VFB5.0" +Ne 338 "/PSU/VFB5.0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13703,7 +13713,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 342 "/PSU/lout_5.0" +Ne 344 "/PSU/lout_5.0" Po -176 0 $EndPAD $PAD @@ -13731,7 +13741,7 @@ $PAD Sh "1" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 339 "/PSU/VIN_DC-DC-5.0" +Ne 341 "/PSU/VIN_DC-DC-5.0" Po -373 0 $EndPAD $PAD @@ -13787,7 +13797,7 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 339 "/PSU/VIN_DC-DC-5.0" +Ne 341 "/PSU/VIN_DC-DC-5.0" Po -570 0 $EndPAD $PAD @@ -13822,7 +13832,7 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 339 "/PSU/VIN_DC-DC-5.0" +Ne 341 "/PSU/VIN_DC-DC-5.0" Po 570 0 $EndPAD $EndMODULE 1210 @@ -13851,7 +13861,7 @@ $PAD Sh "6" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 339 "/PSU/VIN_DC-DC-5.0" +Ne 341 "/PSU/VIN_DC-DC-5.0" Po -196 153 $EndPAD $PAD @@ -13872,7 +13882,7 @@ $PAD Sh "3" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 342 "/PSU/lout_5.0" +Ne 344 "/PSU/lout_5.0" Po 196 -153 $EndPAD $PAD @@ -13884,13 +13894,13 @@ Po 196 153 $EndPAD $EndMODULE MLP6 $MODULE 0402 -Po 63942 19789 1800 0 4C7FDA00 4C7C4FF3 ~~ +Po 63942 19789 1800 0 4CDDC48B 4C7C4FF3 ~~ Li 0402 Sc 4C7C4FF3 AR /4C69ED5F/4C7C4CEF Op 0 0 0 At SMD -T0 -4 338 200 200 1800 40 M V 20 N"R43" +T0 36 285 200 200 1800 40 M V 20 N"R43" T1 0 -150 200 200 1800 40 M I 20 N"51K" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -13907,18 +13917,18 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 334 "/PSU/VFB2.5" +Ne 336 "/PSU/VFB2.5" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 63930 19120 0 0 4C7FD9BC 4C7C4FF5 ~~ +Po 63930 19120 0 0 4CDDC49A 4C7C4FF5 ~~ Li 0402 Sc 4C7C4FF5 AR /4C69ED5F/4C7C4CEE Op 0 0 0 At SMD -T0 -20 308 200 200 0 40 M V 20 N"R42" +T0 -44 -309 200 200 0 40 M V 20 N"R42" T1 0 -150 200 200 0 40 M I 20 N"24K" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -13928,7 +13938,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 334 "/PSU/VFB2.5" +Ne 336 "/PSU/VFB2.5" Po -176 0 $EndPAD $PAD @@ -13956,7 +13966,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 325 "/PSU/2.5V_EN" +Ne 328 "/PSU/2.5V_EN" Po -176 0 $EndPAD $PAD @@ -14024,13 +14034,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 63926 20439 1800 0 4C7FD9BF 4C7C4FFD ~~ +Po 63926 20439 1800 0 4CDDC496 4C7C4FFD ~~ Li 0402 Sc 4C7C4FFD AR /4C69ED5F/4C7C4CEC Op 0 0 0 At SMD -T0 -4 314 200 200 1800 40 M V 20 N"C101" +T0 13 -333 200 200 1800 40 M V 20 N"C101" T1 0 -150 200 200 1800 40 M I 20 N"22pF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -14047,7 +14057,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 334 "/PSU/VFB2.5" +Ne 336 "/PSU/VFB2.5" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14080,13 +14090,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 1206 -Po 65005 20052 900 0 4C7FDAC8 4C7C5000 ~~ +Po 65005 20052 900 0 4CDDC4B9 4C7C5000 ~~ Li 1206 Sc 4C7C5000 AR /4C69ED5F/4C7C4CED Op 0 0 0 At SMD -T0 405 556 200 200 900 40 M V 20 N"C102" +T0 942 11 200 200 1800 40 M V 20 N"C102" T1 0 -150 200 200 900 40 M I 20 N"10uF" DS -798 -384 -798 384 50 20 DS -798 384 798 384 50 20 @@ -14159,18 +14169,18 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 331 "/PSU/SW_2.5" +Ne 333 "/PSU/SW_2.5" Po 570 0 $EndPAD $EndMODULE 1210 $MODULE 0402 -Po 61982 20497 1800 0 4C7FD912 4C7D0382 ~~ +Po 61982 20497 1800 0 4CDDC4A7 4C7D0382 ~~ Li 0402 Sc 4C7D0382 AR /4C69ED5F/4C7D02E1 Op 0 0 0 At SMD -T0 504 -15 200 200 2700 40 M V 20 N"R44" +T0 25 -373 200 200 1800 40 M V 20 N"R44" T1 0 -150 200 200 1800 40 M I 20 N"R" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -14180,7 +14190,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 340 "/PSU/lout_2.5" +Ne 342 "/PSU/lout_2.5" Po -176 0 $EndPAD $PAD @@ -14265,7 +14275,7 @@ $PAD Sh "3" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 340 "/PSU/lout_2.5" +Ne 342 "/PSU/lout_2.5" Po 196 -153 $EndPAD $PAD @@ -14377,7 +14387,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 344 "/USB/USBA_D-" +Ne 346 "/USB/USBA_D-" Po -176 0 $EndPAD $PAD @@ -14405,7 +14415,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 343 "/USB/USBA_D+" +Ne 345 "/USB/USBA_D+" Po -176 0 $EndPAD $PAD @@ -14496,7 +14506,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 343 "/USB/USBA_D+" +Ne 345 "/USB/USBA_D+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14524,7 +14534,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 343 "/USB/USBA_D+" +Ne 345 "/USB/USBA_D+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14552,67 +14562,11 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 344 "/USB/USBA_D-" +Ne 346 "/USB/USBA_D-" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 1206 -Po 59083 14673 2700 15 4CDB6C19 4C7D382C ~~ -Li 1206 -Sc 4C7D382C -AR /4C5F1EDC/4C6552B6 -Op 0 0 0 -At SMD -T0 540 548 200 200 2700 40 N V 25 N"R15" -T1 0 150 200 200 2700 40 N I 25 N"1M" -DS -798 384 -798 -384 50 21 -DS -798 -384 798 -384 50 21 -DS 798 -384 798 384 50 21 -DS 798 384 -798 384 50 21 -$PAD -Sh "1" R 355 668 0 0 2700 -Dr 0 0 0 -At SMD N 00888000 -Ne 353 "/USB/USB_CASE_DEV" -Po -570 0 -$EndPAD -$PAD -Sh "2" R 355 668 0 0 2700 -Dr 0 0 0 -At SMD N 00888000 -Ne 356 "GND" -Po 570 0 -$EndPAD -$EndMODULE 1206 -$MODULE 1206 -Po 59059 16535 900 15 4CDB6C14 4C7D382E ~~ -Li 1206 -Sc 4C7D382E -AR /4C5F1EDC/4C5F2D27 -Op 0 0 0 -At SMD -T0 -528 -524 200 200 900 40 N V 25 N"R10" -T1 0 150 200 200 900 40 N I 25 N"1M" -DS -798 384 -798 -384 50 21 -DS -798 -384 798 -384 50 21 -DS 798 -384 798 384 50 21 -DS 798 384 -798 384 50 21 -$PAD -Sh "1" R 355 668 0 0 900 -Dr 0 0 0 -At SMD N 00888000 -Ne 354 "/USB/USB_CASE_HOST" -Po -570 0 -$EndPAD -$PAD -Sh "2" R 355 668 0 0 900 -Dr 0 0 0 -At SMD N 00888000 -Ne 356 "GND" -Po 570 0 -$EndPAD -$EndMODULE 1206 -$MODULE 1206 Po 65539 13949 0 15 4CDB6C0D 4C7D3830 ~~ Li 1206 Sc 4C7D3830 @@ -14669,13 +14623,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 0402 -Po 62697 27480 900 15 4C81268C 4C7FD4BD ~~ +Po 62697 27480 900 15 4CDDC066 4C7FD4BD ~~ Li 0402 Sc 4C7FD4BD AR /4C69ED5F/4C7FC041 Op 0 0 0 At SMD -T0 -473 71 200 200 1800 40 N V 25 N"R58" +T0 -492 -122 200 200 1800 40 N V 25 N"R58" T1 0 150 200 200 900 40 N I 25 N"1M" DS -305 168 -305 -168 50 21 DS -305 -168 305 -168 50 21 @@ -14685,14 +14639,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 324 "/PSU/1.2V_EN" +Ne 327 "/PSU/1.2V_EN" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 337 "/PSU/VIN_DC-DC-1.2" +Ne 339 "/PSU/VIN_DC-DC-1.2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14725,13 +14679,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 62717 25441 900 15 4C812A73 4C7FD4C1 ~~ +Po 62717 25441 900 15 4CDDC06A 4C7FD4C1 ~~ Li 0402 Sc 4C7FD4C1 AR /4C69ED5F/4C7FC13A Op 0 0 0 At SMD -T0 -512 51 200 200 1800 40 N V 25 N"R56" +T0 -520 -123 200 200 1800 40 N V 25 N"R56" T1 0 150 200 200 900 40 N I 25 N"R" DS -305 168 -305 -168 50 21 DS -305 -168 305 -168 50 21 @@ -14741,14 +14695,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 326 "/PSU/3.3V_EN" +Ne 329 "/PSU/3.3V_EN" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 338 "/PSU/VIN_DC-DC-3.3" +Ne 340 "/PSU/VIN_DC-DC-3.3" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14781,34 +14735,6 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 1206 -Po 45803 19031 2700 15 4CDB6C30 4C8934E6 ~~ -Li 1206 -Sc 4C8934E6 -AR /4C4320F3/4C5D7DC4 -Op 0 0 0 -At SMD -T0 -1007 -43 200 200 3600 40 N V 21 N"R9" -T1 0 150 200 200 2700 40 N I 21 N"1M" -DS -798 384 -798 -384 50 21 -DS -798 -384 798 -384 50 21 -DS 798 -384 798 384 50 21 -DS 798 384 -798 384 50 21 -$PAD -Sh "1" R 355 668 0 0 2700 -Dr 0 0 0 -At SMD N 00888000 -Ne 74 "/Ethernet_Phy/MAG_SHIELD" -Po -570 0 -$EndPAD -$PAD -Sh "2" R 355 668 0 0 2700 -Dr 0 0 0 -At SMD N 00888000 -Ne 356 "GND" -Po 570 0 -$EndPAD -$EndMODULE 1206 -$MODULE 1206 Po 54602 18996 2700 15 4CDB6C27 4C8934E8 ~~ Li 1206 Sc 4C8934E8 @@ -14837,13 +14763,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 0402 -Po 60916 42005 1800 0 4CAA859D 4C9E33E4 ~~ +Po 60916 42005 1800 0 4CDDC69C 4C9E33E4 ~~ Li 0402 Sc 4C9E33E4 AR /4C9E2B0F/4C9E2B95 Op 0 0 0 At SMD -T0 4 366 200 200 1800 40 M V 20 N"C125" +T0 -127 312 200 200 1800 40 M V 20 N"C125" T1 0 -150 200 200 1800 40 M I 20 N"22pF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -14893,13 +14819,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 60219 42430 1800 0 4CAA85A5 4C9E33EC ~~ +Po 60219 42430 1800 0 4CDDC695 4C9E33EC ~~ Li 0402 Sc 4C9E33EC AR /4C9E2B0F/4C9E2B91 Op 0 0 0 At SMD -T0 12 -322 200 200 1800 40 M V 20 N"C121" +T0 73 -373 200 200 1800 40 M V 20 N"C121" T1 0 -150 200 200 1800 40 M I 20 N"10nF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -14965,7 +14891,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 303 "/Image_Sensor/+1.8_VDD" +Ne 307 "/Image_Sensor/+1.8_VDD" Po -176 0 $EndPAD $PAD @@ -15117,13 +15043,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 1206 -Po 61751 42608 900 15 4CAA85D9 4C9E33FD ~~ +Po 61751 42608 900 15 4CDDBFA9 4C9E33FD ~~ Li 1206 Sc 4C9E33FD AR /4C9E2B0F/4C9E2B94 Op 0 0 0 At SMD -T0 -968 27 200 200 1800 40 N V 25 N"C128" +T0 1269 147 200 200 900 40 N V 25 N"C128" T1 0 150 200 200 900 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -15173,13 +15099,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 60668 41348 1800 15 4CAA85C5 4C9E3403 ~~ +Po 60668 41348 1800 15 4CDDBFB6 4C9E3403 ~~ Li 1206 Sc 4C9E3403 AR /4C9E2B0F/4C9E2B90 Op 0 0 0 At SMD -T0 -960 27 200 200 2700 40 N V 25 N"C118" +T0 46 549 200 200 1800 40 N V 25 N"C118" T1 0 150 200 200 1800 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -15201,13 +15127,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 65205 44823 1800 15 4CAA84F4 4C9E3405 ~~ +Po 65205 44823 1800 15 4CDDBF2D 4C9E3405 ~~ Li 1206 Sc 4C9E3405 AR /4C9E2B0F/4C9E2B86 Op 0 0 0 At SMD -T0 -989 -47 200 200 2700 40 N V 25 N"C117" +T0 -220 512 200 200 1800 40 N V 25 N"C117" T1 0 150 200 200 1800 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -15229,13 +15155,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 61737 47314 1800 15 4CC06D3A 4C9E3407 ~~ +Po 61737 47314 1800 15 4CDDBE49 4C9E3407 ~~ Li 1206 Sc 4C9E3407 AR /4C9E2B0F/4C9E2BA6 Op 0 0 0 At SMD -T0 -972 -99 200 200 2700 40 N V 25 N"C116" +T0 1213 113 200 200 1800 40 N V 25 N"C116" T1 0 150 200 200 1800 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -15245,7 +15171,7 @@ $PAD Sh "1" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 303 "/Image_Sensor/+1.8_VDD" +Ne 307 "/Image_Sensor/+1.8_VDD" Po -570 0 $EndPAD $PAD @@ -15257,13 +15183,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 64985 47845 900 15 4CC06D99 4C9E3409 ~~ +Po 64985 47845 900 15 4CDDBF20 4C9E3409 ~~ Li 1206 Sc 4C9E3409 AR /4C9E2B0F/4C9E2B70 Op 0 0 0 At SMD -T0 943 -9 200 200 1800 40 N V 25 N"C115" +T0 -25 1381 200 200 900 40 N V 25 N"C115" T1 0 150 200 200 900 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -15313,13 +15239,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 60386 48390 2700 15 4CAA83C3 4C9E340D ~~ +Po 60386 48390 2700 15 4CDDBDD2 4C9E340D ~~ Li 1206 Sc 4C9E340D AR /4C9E2B0F/4C9E2BAA Op 0 0 0 At SMD -T0 -981 8 200 200 3600 40 N V 25 N"C107" +T0 71 520 200 200 2700 40 N V 25 N"C107" T1 0 150 200 200 2700 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -15341,13 +15267,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 63409 46587 1800 15 4CC06D30 4C9E340F ~~ +Po 63409 46587 1800 15 4CDDBE58 4C9E340F ~~ Li 1206 Sc 4C9E340F AR /4C9E2B0F/4C9E2B6C Op 0 0 0 At SMD -T0 437 -826 200 200 2700 40 N V 25 N"C106" +T0 543 -826 200 200 2700 40 N V 25 N"C106" T1 0 150 200 200 1800 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -15397,13 +15323,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE SOT23_6 -Po 60727 42497 1800 15 4CAA85DC 4C9E3413 ~~ +Po 60727 42497 1800 15 4CDDBF91 4C9E3413 ~~ Li SOT23_6 Kw SOT23_5 Sc 4C9E3413 AR /4C9E2B0F/4C9E2B96 Op 0 0 0 -T0 -16 -918 300 300 1800 30 N V 21 N"U23" +T0 1050 -27 300 300 1800 39 N V 21 N"U23" T1 25 0 197 197 1800 30 N I 21 N"TPS793XX" DS -200 300 -500 100 50 21 DS 500 300 -525 300 50 21 @@ -15523,13 +15449,13 @@ Ro 0.000000 0.000000 -180.000000 $EndSHAPE3D $EndMODULE SOT23_6 $MODULE SOT23_6 -Po 61686 48338 2700 15 4CAA82B0 4C9E3417 ~~ +Po 61686 48338 2700 15 4CDDBE24 4C9E3417 ~~ Li SOT23_6 Kw SOT23_5 Sc 4C9E3417 AR /4C9E2B0F/4C9E2BA4 Op 0 0 0 -T0 0 -944 300 300 2700 30 N V 21 N"U20" +T0 839 -3 300 300 3600 39 N V 21 N"U20" T1 25 0 197 197 2700 30 N I 21 N"TPS793XX" DS -200 300 -500 100 50 21 DS 500 300 -525 300 50 21 @@ -15540,7 +15466,7 @@ $PAD Sh "6" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 303 "/Image_Sensor/+1.8_VDD" +Ne 307 "/Image_Sensor/+1.8_VDD" Po -375 -500 $EndPAD $PAD @@ -15586,13 +15512,13 @@ Ro 0.000000 0.000000 -180.000000 $EndSHAPE3D $EndMODULE SOT23_6 $MODULE SOT23_6 -Po 63953 47786 1800 15 4CAA8121 4C9E3419 ~~ +Po 63953 47786 1800 15 4CDDBF3D 4C9E3419 ~~ Li SOT23_6 Kw SOT23_5 Sc 4C9E3419 AR /4C9E2B0F/4C9E2B72 Op 0 0 0 -T0 -79 -929 300 300 1800 30 N V 21 N"U19" +T0 87 -1025 300 300 1800 39 N V 21 N"U19" T1 25 0 197 197 1800 30 N I 21 N"TPS793XX" DS -200 300 -500 100 50 21 DS 500 300 -525 300 50 21 @@ -15649,13 +15575,13 @@ Ro 0.000000 0.000000 -180.000000 $EndSHAPE3D $EndMODULE SOT23_6 $MODULE SOT23_6 -Po 62036 45061 1800 15 4CAA7EEA 4C9E341B ~~ +Po 62036 45061 1800 15 4CDDBF7A 4CDDBF84 ~~ Li SOT23_6 Kw SOT23_5 -Sc 4C9E341B +Sc 4CDDBF84 AR /4C9E2B0F/4C9E2848 Op 0 0 0 -T0 32 -901 300 300 1800 30 N V 21 N"U18" +T0 772 -6 300 300 2700 39 N V 21 N"U18" T1 25 0 197 197 1800 30 N I 21 N"TPS793XX" DS -200 300 -500 100 50 21 DS 500 300 -525 300 50 21 @@ -15712,13 +15638,13 @@ Ro 0.000000 0.000000 -180.000000 $EndSHAPE3D $EndMODULE SOT23_6 $MODULE 0402 -Po 60219 41997 1800 0 4CAA85B7 4C9E3502 ~~ +Po 60219 41997 1800 0 4CDDC6A5 4C9E3502 ~~ Li 0402 Sc 4C9E3502 AR /4C9E2B0F/4C9E2B92 Op 0 0 0 At SMD -T0 19 370 200 200 1800 40 M V 20 N"R68" +T0 34 324 200 200 1800 40 M V 20 N"R68" T1 0 -150 200 200 1800 40 M I 20 N"R" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -15740,13 +15666,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 60908 42426 1800 0 4CAA858F 4C9E3504 ~~ +Po 60908 42426 1800 0 4CDDC68E 4C9E3504 ~~ Li 0402 Sc 4C9E3504 AR /4C9E2B0F/4C9E2B93 Op 0 0 0 At SMD -T0 -32 -303 200 200 1800 40 M V 20 N"R67" +T0 -57 -377 200 200 1800 40 M V 20 N"R67" T1 0 -150 200 200 1800 40 M I 20 N"R" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -15868,7 +15794,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 303 "/Image_Sensor/+1.8_VDD" +Ne 307 "/Image_Sensor/+1.8_VDD" Po -176 0 $EndPAD $PAD @@ -16120,7 +16046,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 303 "/Image_Sensor/+1.8_VDD" +Ne 307 "/Image_Sensor/+1.8_VDD" Po -176 0 $EndPAD $PAD @@ -16148,7 +16074,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 303 "/Image_Sensor/+1.8_VDD" +Ne 307 "/Image_Sensor/+1.8_VDD" Po -176 0 $EndPAD $PAD @@ -16176,7 +16102,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 303 "/Image_Sensor/+1.8_VDD" +Ne 307 "/Image_Sensor/+1.8_VDD" Po -176 0 $EndPAD $PAD @@ -16300,13 +16226,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 1206 -Po 65626 49134 1800 15 4CC06DA9 4C9E6463 ~~ +Po 65626 49134 1800 15 4CDDBE9A 4C9E6463 ~~ Li 1206 Sc 4C9E6463 AR /4C9E2AF4/4C9E3C70 Op 0 0 0 At SMD -T0 -1004 0 200 200 2700 40 N V 25 N"C144" +T0 -571 -579 200 200 1800 40 N V 25 N"C144" T1 0 150 200 200 1800 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -16328,13 +16254,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 61718 46474 1800 15 4CC06C72 4C9E6465 ~~ +Po 61718 46474 1800 15 4CDDBE54 4C9E6465 ~~ Li 1206 Sc 4C9E6465 AR /4C9E2AF4/4C9E3C5E Op 0 0 0 At SMD -T0 958 -38 200 200 2700 40 N V 25 N"C139" +T0 1194 33 200 200 1800 40 N V 25 N"C139" T1 0 150 200 200 1800 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -16344,7 +16270,7 @@ $PAD Sh "1" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 303 "/Image_Sensor/+1.8_VDD" +Ne 307 "/Image_Sensor/+1.8_VDD" Po -570 0 $EndPAD $PAD @@ -16384,13 +16310,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 65835 47836 900 15 4CAB2FE1 4C9E6469 ~~ +Po 65835 47836 900 15 4CDDBF1D 4C9E6469 ~~ Li 1206 Sc 4C9E6469 AR /4C9E2AF4/4C9E3C26 Op 0 0 0 At SMD -T0 -464 555 200 200 900 40 N V 25 N"C132" +T0 -34 830 200 200 900 40 N V 25 N"C132" T1 0 150 200 200 900 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -16412,13 +16338,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 62596 42608 900 15 4CAB2F02 4C9E646B ~~ +Po 62596 42608 900 15 4CDDBFAE 4C9E646B ~~ Li 1206 Sc 4C9E646B AR /4C9E2AF4/4C9E3C04 Op 0 0 0 At SMD -T0 965 0 200 200 1800 40 N V 25 N"C130" +T0 1285 140 200 200 900 40 N V 25 N"C130" T1 0 150 200 200 900 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -16440,12 +16366,12 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE iLCC-48 -Po 55743 45496 2700 15 4CDC4198 4C9E76D2 ~~ +Po 55743 45496 2700 15 4CDDBDBC 4C9E76D2 ~~ Li iLCC-48 Sc 4C9E76D2 AR /4C9E2AF4/4C9E3B7C Op 0 0 0 -T0 2358 7 276 276 3600 69 N V 21 N"U24" +T0 2374 798 276 276 3600 69 N V 21 N"U24" T1 2370 -37 276 276 3600 69 N I 21 N"MT9M033" DS -264 -2370 -150 -2173 59 21 DS -150 -2173 -24 -2370 59 21 @@ -16458,7 +16384,7 @@ $PAD Sh "19" R 196 303 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 303 "/Image_Sensor/+1.8_VDD" +Ne 307 "/Image_Sensor/+1.8_VDD" Po -1515 1816 $EndPAD $PAD @@ -16479,21 +16405,21 @@ $PAD Sh "22" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 316 "/Image_Sensor/IS_STANDBY" +Ne 128 "/FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY" Po -688 1771 $EndPAD $PAD Sh "23" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N" +Ne 316 "/Image_Sensor/IS_OE_N" Po -413 1771 $EndPAD $PAD Sh "24" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 311 "/Image_Sensor/IS_I2C_ADDR" +Ne 123 "/FPGA,_Port0,_Port2,_PROG_IF/IS_I2C_ADDR" Po -137 1771 $EndPAD $PAD @@ -16507,7 +16433,7 @@ $PAD Sh "26" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 310 "/Image_Sensor/IS_FLASH" +Ne 121 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" Po 413 1771 $EndPAD $PAD @@ -16521,14 +16447,14 @@ $PAD Sh "28" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" +Ne 122 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" Po 964 1771 $EndPAD $PAD Sh "29" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 312 "/Image_Sensor/IS_LINE" +Ne 315 "/Image_Sensor/IS_LINE" Po 1240 1771 $EndPAD $PAD @@ -16640,49 +16566,49 @@ $PAD Sh "45" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0" +Ne 308 "/Image_Sensor/IS_DOUT0" Po 964 -1771 $EndPAD $PAD Sh "46" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1" +Ne 115 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1" Po 688 -1771 $EndPAD $PAD Sh "47" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 304 "/Image_Sensor/IS_DOUT2" +Ne 117 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2" Po 413 -1771 $EndPAD $PAD Sh "48" R 196 592 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" +Ne 118 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" Po 137 -1673 $EndPAD $PAD Sh "1" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 305 "/Image_Sensor/IS_DOUT4" +Ne 310 "/Image_Sensor/IS_DOUT4" Po -137 -1771 $EndPAD $PAD Sh "2" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5" +Ne 311 "/Image_Sensor/IS_DOUT5" Po -413 -1771 $EndPAD $PAD Sh "3" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 306 "/Image_Sensor/IS_DOUT6" +Ne 312 "/Image_Sensor/IS_DOUT6" Po -688 -1771 $EndPAD $PAD @@ -16696,7 +16622,7 @@ $PAD Sh "5" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 309 "/Image_Sensor/IS_EXTCLK" +Ne 314 "/Image_Sensor/IS_EXTCLK" Po -1240 -1771 $EndPAD $PAD @@ -16710,35 +16636,35 @@ $PAD Sh "7" R 196 303 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "/Image_Sensor/IS_DOUT7" +Ne 313 "/Image_Sensor/IS_DOUT7" Po -1816 -1515 $EndPAD $PAD Sh "8" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 308 "/Image_Sensor/IS_DOUT8" +Ne 119 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8" Po -1771 -1240 $EndPAD $PAD Sh "9" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" +Ne 120 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" Po -1771 -964 $EndPAD $PAD Sh "10" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10" +Ne 116 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10" Po -1771 -688 $EndPAD $PAD Sh "11" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11" +Ne 309 "/Image_Sensor/IS_DOUT11" Po -1771 -413 $EndPAD $PAD @@ -16752,21 +16678,21 @@ $PAD Sh "13" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 313 "/Image_Sensor/IS_PIXEL" +Ne 124 "/FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL" Po -1771 137 $EndPAD $PAD Sh "14" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 303 "/Image_Sensor/+1.8_VDD" +Ne 307 "/Image_Sensor/+1.8_VDD" Po -1771 413 $EndPAD $PAD Sh "15" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 315 "/Image_Sensor/IS_SCL" +Ne 126 "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" Po -1771 688 $EndPAD $PAD @@ -16780,7 +16706,7 @@ $PAD Sh "17" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 314 "/Image_Sensor/IS_RESET_N" +Ne 125 "/FPGA,_Port0,_Port2,_PROG_IF/IS_RESET_N" Po -1771 1240 $EndPAD $PAD @@ -16848,13 +16774,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46976 43047 900 15 4CBB56A2 4CB9E51E ~~ +Po 46976 43047 900 15 4CDDC007 4CB9E51E ~~ Li 0402 Sc 4CB9E51E AR /4C716A4D/4CB9C9A3 Op 0 0 0 At SMD -T0 -229 461 200 200 1800 40 N V 21 N"R74" +T0 -461 150 200 200 1800 40 N V 21 N"R74" T1 -55 181 200 200 900 40 N I 21 N"470" DS -305 168 -305 -168 50 21 DS -305 -168 305 -168 50 21 @@ -16864,7 +16790,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DBG_PRG/VCC_USB" +Ne 24 "/DBG_PRG/VCC_USB" Po -176 0 $EndPAD $PAD @@ -16899,7 +16825,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/DBG_PRG/VCC_USB" +Ne 24 "/DBG_PRG/VCC_USB" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16955,7 +16881,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DBG_PRG/FTDI_USB_DP" +Ne 22 "/DBG_PRG/FTDI_USB_DP" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16983,7 +16909,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DBG_PRG/FTDI_USB_DM" +Ne 21 "/DBG_PRG/FTDI_USB_DM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -17011,18 +16937,18 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DBG_PRG/VCC_USB" +Ne 24 "/DBG_PRG/VCC_USB" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 50016 47717 0 15 4C5FF890 4CB9E52A ~~ +Po 50016 47717 0 15 4CDDBD81 4CB9E52A ~~ Li 0402 Sc 4CB9E52A AR /4C716A4D/4CB9CA50 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 21 N"FB1" +T0 0 381 200 200 0 40 N V 21 N"FB1" T1 0 150 200 200 0 40 N I 21 N"FILTER" DS -305 168 -305 -168 50 21 DS -305 -168 305 -168 50 21 @@ -17044,13 +16970,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 47091 42512 1800 15 4CBB54FB 4CB9E52C ~~ +Po 47091 42512 1800 15 4CDDC019 4CB9E52C ~~ Li 0402 Sc 4CB9E52C AR /4C716A4D/4CB9C996 Op 0 0 0 At SMD -T0 -16 339 200 200 1800 40 N V 21 N"C151" +T0 150 571 200 200 2700 40 N V 21 N"C151" T1 0 150 200 200 1800 40 N I 21 N"100nF" DS -305 168 -305 -168 50 21 DS -305 -168 305 -168 50 21 @@ -17184,13 +17110,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0603 -Po 46504 42709 900 15 4CBB567E 4CB9E535 ~~ +Po 46504 42709 900 15 4CDDC011 4CB9E535 ~~ Li 0603 Sc 4CB9E535 AR /4C716A4D/4CB9D9A7 Op 0 0 0 At SMD -T0 342 -382 200 200 900 40 N V 21 N"C150" +T0 823 12 200 200 900 40 N V 21 N"C150" T1 0 150 200 200 900 40 N I 21 N"10uF" DS -443 227 -443 -227 50 21 DS -443 -227 443 -227 50 21 @@ -17200,7 +17126,7 @@ $PAD Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DBG_PRG/VCC_USB" +Ne 24 "/DBG_PRG/VCC_USB" Po -294 0 $EndPAD $PAD @@ -17212,13 +17138,13 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 1206 -Po 50465 48945 0 15 4CBB56B2 4CB9E536 ~~ +Po 50465 48945 0 15 4CDDBDB4 4CB9E536 ~~ Li 1206 Sc 4CB9E536 AR /4C716A4D/4CB9D313 Op 0 0 0 At SMD -T0 1102 -197 200 200 0 40 N V 25 N"R69" +T0 47 642 200 200 0 40 N V 25 N"R69" T1 0 150 200 200 0 40 N I 25 N"1M" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -17228,7 +17154,7 @@ $PAD Sh "1" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DBG_PRG/USB_CASE_FTDI" +Ne 23 "/DBG_PRG/USB_CASE_FTDI" Po -570 0 $EndPAD $PAD @@ -17256,7 +17182,7 @@ $PAD Sh "1" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DBG_PRG/USB_CASE_FTDI" +Ne 23 "/DBG_PRG/USB_CASE_FTDI" Po -570 0 $EndPAD $PAD @@ -17341,14 +17267,14 @@ $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DBG_PRG/VCC_USB" +Ne 24 "/DBG_PRG/VCC_USB" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DBG_PRG/VCC_USB" +Ne 24 "/DBG_PRG/VCC_USB" Po -1613 -688 $EndPAD $PAD @@ -17411,7 +17337,7 @@ $PAD Sh "42" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DBG_PRG/VCC_USB" +Ne 24 "/DBG_PRG/VCC_USB" Po 98 -1613 $EndPAD $PAD @@ -17425,7 +17351,7 @@ $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 328 "/PSU/AVR_SCK" +Ne 16 "/DBG_PRG/AVR_SCK" Po 491 -1613 $EndPAD $PAD @@ -17593,38 +17519,38 @@ $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DBG_PRG/FPGA_TMS" +Ne 20 "/DBG_PRG/FPGA_TMS" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DBG_PRG/FPGA_TDO" +Ne 19 "/DBG_PRG/FPGA_TDO" Po 688 1613 $EndPAD $PAD Sh "23" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DBG_PRG/FPGA_TDI" +Ne 18 "/DBG_PRG/FPGA_TDI" Po 885 1613 $EndPAD $PAD Sh "24" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DBG_PRG/FPGA_TCK" +Ne 17 "/DBG_PRG/FPGA_TCK" Po 1082 1613 $EndPAD $EndMODULE LQFP48 $MODULE ZX62D-B-5P8 -Po 48827 46575 2700 15 4BAADC40 4CB9E55A ~~ +Po 48827 46575 2700 15 4CDDC7F1 4CDDC83D ~~ Li ZX62D-B-5P8 -Sc 4CB9E55A +Sc 4CDDC83D AR /4C716A4D/4CB9D311 Op 0 0 0 -T0 446 -852 157 157 2700 20 N V 21 N"J8" +T0 134 -1098 394 394 2700 39 N V 21 N"J8" T1 550 -500 118 118 2700 20 N I 21 N"ZX62D-B-5P8" DS -1690 2970 -1760 2970 100 21 DS -1760 2970 -1760 -630 100 21 @@ -17647,14 +17573,14 @@ $PAD Sh "2" R 200 620 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DBG_PRG/FTDI_USB_DM" +Ne 21 "/DBG_PRG/FTDI_USB_DM" Po 310 0 $EndPAD $PAD Sh "3" R 200 620 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DBG_PRG/FTDI_USB_DP" +Ne 22 "/DBG_PRG/FTDI_USB_DP" Po 630 0 $EndPAD $PAD @@ -17689,39 +17615,39 @@ $PAD Sh "8" R 860 900 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DBG_PRG/USB_CASE_FTDI" +Ne 23 "/DBG_PRG/USB_CASE_FTDI" Po -1070 140 $EndPAD $PAD Sh "6" R 860 900 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DBG_PRG/USB_CASE_FTDI" +Ne 23 "/DBG_PRG/USB_CASE_FTDI" Po 2320 2310 $EndPAD $PAD Sh "7" R 860 900 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DBG_PRG/USB_CASE_FTDI" +Ne 23 "/DBG_PRG/USB_CASE_FTDI" Po -1070 2310 $EndPAD $PAD Sh "9" R 860 900 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DBG_PRG/USB_CASE_FTDI" +Ne 23 "/DBG_PRG/USB_CASE_FTDI" Po 2320 140 $EndPAD $EndMODULE ZX62D-B-5P8 $MODULE header25x2_smd_2mm -Po 56260 51142 0 0 4CBAF958 4CBAFFD7 ~~ +Po 56260 51142 0 0 4CDDC57B 4CBAFFD7 ~~ Li header25x2_smd_2mm Sc 4CBAFFD7 AR /4CB0D95D/4CBAFE50 Op 0 0 0 At SMD -T0 0 150 200 200 0 40 M V 20 N"P1" +T0 8933 -1784 394 394 0 40 M V 20 N"P1" T1 0 -150 200 200 0 40 M I 20 N"CONN_25X2" DC 9645 -1771 9645 -1574 78 20 DS 10039 1377 10039 -1377 39 20 @@ -17732,7 +17658,7 @@ $PAD Sh "1" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/FPGA_GPIOS/FPGA_BANK0_IO_8" +Ne 113 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8" Po 9448 -747 $EndPAD $PAD @@ -17753,63 +17679,63 @@ $PAD Sh "7" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/FPGA_GPIOS/FPGA_BANK0_IO_10" +Ne 148 "/FPGA_GPIOS/FPGA_BANK0_IO_10" Po 7086 -747 $EndPAD $PAD Sh "9" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 90 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" +Ne 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" Po 6299 -747 $EndPAD $PAD Sh "11" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 105 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_5" +Ne 165 "/FPGA_GPIOS/FPGA_BANK0_IO_5" Po 5511 -747 $EndPAD $PAD Sh "13" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/FPGA_GPIOS/FPGA_BANK0_IO_17" +Ne 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" Po 4724 -747 $EndPAD $PAD Sh "15" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/FPGA_GPIOS/FPGA_BANK0_IO_20" +Ne 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20" Po 3936 -747 $EndPAD $PAD Sh "17" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/FPGA_GPIOS/FPGA_BANK0_IO_28" +Ne 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_28" Po 3149 -747 $EndPAD $PAD Sh "19" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" +Ne 153 "/FPGA_GPIOS/FPGA_BANK0_IO_22" Po 2362 -747 $EndPAD $PAD Sh "21" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/FPGA_GPIOS/FPGA_BANK0_IO_27" +Ne 156 "/FPGA_GPIOS/FPGA_BANK0_IO_27" Po 1574 -747 $EndPAD $PAD Sh "23" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/FPGA_GPIOS/FPGA_BANK0_IO_39" +Ne 102 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39" Po 787 -747 $EndPAD $PAD @@ -17823,119 +17749,119 @@ $PAD Sh "27" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 116 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_7" +Ne 172 "/FPGA_GPIOS/FPGA_BANK0_IO_7" Po -787 -747 $EndPAD $PAD Sh "29" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 91 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" +Ne 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" Po -1574 -747 $EndPAD $PAD Sh "31" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 100 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" +Ne 161 "/FPGA_GPIOS/FPGA_BANK0_IO_44" Po -2362 -747 $EndPAD $PAD Sh "33" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 102 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" +Ne 163 "/FPGA_GPIOS/FPGA_BANK0_IO_47" Po -3149 -747 $EndPAD $PAD Sh "35" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 101 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_45" +Ne 162 "/FPGA_GPIOS/FPGA_BANK0_IO_45" Po -3936 -747 $EndPAD $PAD Sh "37" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 108 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52" +Ne 107 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52" Po -4724 -747 $EndPAD $PAD Sh "39" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 109 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56" +Ne 168 "/FPGA_GPIOS/FPGA_BANK0_IO_56" Po -5511 -747 $EndPAD $PAD Sh "41" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_51" +Ne 167 "/FPGA_GPIOS/FPGA_BANK0_IO_51" Po -6299 -747 $EndPAD $PAD Sh "43" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/FPGA_GPIOS/FPGA_BANK0_IO_54" +Ne 109 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_54" Po -7086 -747 $EndPAD $PAD Sh "45" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 115 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_63" +Ne 171 "/FPGA_GPIOS/FPGA_BANK0_IO_63" Po -7873 -747 $EndPAD $PAD Sh "47" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/FPGA_GPIOS/FPGA_BANK0_IO_53" +Ne 108 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_53" Po -8661 -747 $EndPAD $PAD Sh "49" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 111 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_58" +Ne 169 "/FPGA_GPIOS/FPGA_BANK0_IO_58" Po -9448 -747 $EndPAD $PAD Sh "2" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 89 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" +Ne 147 "/FPGA_GPIOS/FPGA_BANK0_IO_1" Po 9448 747 $EndPAD $PAD Sh "4" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 117 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" +Ne 114 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" Po 8661 747 $EndPAD $PAD Sh "6" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" +Ne 149 "/FPGA_GPIOS/FPGA_BANK0_IO_14" Po 7873 747 $EndPAD $PAD Sh "8" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_15" +Ne 150 "/FPGA_GPIOS/FPGA_BANK0_IO_15" Po 7086 747 $EndPAD $PAD Sh "10" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 160 "/FPGA_GPIOS/FPGA_BANK0_IO_3" +Ne 157 "/FPGA_GPIOS/FPGA_BANK0_IO_3" Po 6299 747 $EndPAD $PAD @@ -17949,119 +17875,119 @@ $PAD Sh "14" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 154 "/FPGA_GPIOS/FPGA_BANK0_IO_21" +Ne 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" Po 4724 747 $EndPAD $PAD Sh "16" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 155 "/FPGA_GPIOS/FPGA_BANK0_IO_24" +Ne 154 "/FPGA_GPIOS/FPGA_BANK0_IO_24" Po 3936 747 $EndPAD $PAD Sh "18" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 159 "/FPGA_GPIOS/FPGA_BANK0_IO_29" +Ne 98 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29" Po 3149 747 $EndPAD $PAD Sh "20" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_30" +Ne 158 "/FPGA_GPIOS/FPGA_BANK0_IO_30" Po 2362 747 $EndPAD $PAD Sh "22" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 156 "/FPGA_GPIOS/FPGA_BANK0_IO_25" +Ne 155 "/FPGA_GPIOS/FPGA_BANK0_IO_25" Po 1574 747 $EndPAD $PAD Sh "24" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" +Ne 99 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" Po 787 747 $EndPAD $PAD Sh "26" R 392 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32" +Ne 159 "/FPGA_GPIOS/FPGA_BANK0_IO_32" Po 0 747 $EndPAD $PAD Sh "28" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 112 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6" +Ne 111 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6" Po -787 747 $EndPAD $PAD Sh "30" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 98 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" +Ne 160 "/FPGA_GPIOS/FPGA_BANK0_IO_36" Po -1574 747 $EndPAD $PAD Sh "32" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 99 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" +Ne 103 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" Po -2362 747 $EndPAD $PAD Sh "34" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 164 "/FPGA_GPIOS/FPGA_BANK0_IO_43" +Ne 104 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" Po -3149 747 $EndPAD $PAD Sh "36" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 165 "/FPGA_GPIOS/FPGA_BANK0_IO_46" +Ne 105 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46" Po -3936 747 $EndPAD $PAD Sh "38" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 106 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50" +Ne 166 "/FPGA_GPIOS/FPGA_BANK0_IO_50" Po -4724 747 $EndPAD $PAD Sh "40" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 103 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" +Ne 106 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" Po -5511 747 $EndPAD $PAD Sh "42" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 161 "/FPGA_GPIOS/FPGA_BANK0_IO_34" +Ne 100 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_34" Po -6299 747 $EndPAD $PAD Sh "44" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 104 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_49" +Ne 164 "/FPGA_GPIOS/FPGA_BANK0_IO_49" Po -7086 747 $EndPAD $PAD Sh "46" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 114 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_62" +Ne 170 "/FPGA_GPIOS/FPGA_BANK0_IO_62" Po -7873 747 $EndPAD $PAD @@ -18075,7 +18001,7 @@ $PAD Sh "50" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 113 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_60" +Ne 112 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_60" Po -9448 747 $EndPAD $PAD @@ -18255,13 +18181,13 @@ Po -9448 747 $EndPAD $EndMODULE header25x2_smd_2mm $MODULE 0402 -Po 65631 42388 0 0 4CC09630 4CC0955F ~~ +Po 65631 42388 0 0 4CDDC670 4CC0955F ~~ Li 0402 Sc 4CC0955F AR /4C69ED5F/4CC0947F Op 0 0 0 At SMD -T0 0 307 200 200 0 40 M V 20 N"R78" +T0 204 344 200 200 0 40 M V 20 N"R78" T1 0 -150 200 200 0 40 M I 20 N"R" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -18283,13 +18209,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 64966 41999 0 0 4CC0962D 4CC09561 ~~ +Po 64966 41999 0 0 4CDDC67C 4CC09561 ~~ Li 0402 Sc 4CC09561 AR /4C69ED5F/4CC09480 Op 0 0 0 At SMD -T0 -27 -385 200 200 0 40 M V 20 N"R77" +T0 -210 -408 200 200 0 40 M V 20 N"R77" T1 0 -150 200 200 0 40 M I 20 N"R" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -18311,13 +18237,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 64966 42392 0 0 4CC0966E 4CC09563 ~~ +Po 64966 42392 0 0 4CDDC673 4CC09563 ~~ Li 0402 Sc 4CC09563 AR /4C69ED5F/4CC09482 Op 0 0 0 At SMD -T0 -12 300 200 200 0 40 M V 20 N"C154" +T0 -92 372 200 200 0 40 M V 20 N"C154" T1 0 -150 200 200 0 40 M I 20 N"22pF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -18339,13 +18265,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 65635 41999 0 0 4CC0964A 4CC09565 ~~ +Po 65635 41999 0 0 4CDDC666 4CC09565 ~~ Li 0402 Sc 4CC09565 AR /4C69ED5F/4CC0947E Op 0 0 0 At SMD -T0 28 -354 200 200 0 40 M V 20 N"C153" +T0 251 -377 200 200 0 40 M V 20 N"C153" T1 0 -150 200 200 0 40 M I 20 N"10nF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 @@ -18367,13 +18293,13 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 1206 -Po 64183 41857 2700 15 4CC095DB 4CC09566 ~~ +Po 64183 41857 2700 15 4CDDBFDC 4CC09566 ~~ Li 1206 Sc 4CC09566 AR /4C69ED5F/4CC09481 Op 0 0 0 At SMD -T0 -409 578 200 200 2700 40 N V 25 N"C155" +T0 -74 569 200 200 2700 40 N V 25 N"C155" T1 0 150 200 200 2700 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -18395,13 +18321,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1206 -Po 65281 43144 0 15 4CC095D8 4CC09568 ~~ +Po 65281 43144 0 15 4CDDBFF8 4CC09568 ~~ Li 1206 Sc 4CC09568 AR /4C69ED5F/4CC0947D Op 0 0 0 At SMD -T0 480 512 200 200 0 40 N V 25 N"C152" +T0 199 565 200 200 0 40 N V 25 N"C152" T1 0 150 200 200 0 40 N I 25 N"10uF" DS -798 384 -798 -384 50 21 DS -798 -384 798 -384 50 21 @@ -18423,13 +18349,13 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE SOT23_6 -Po 65151 41955 0 15 4CC095F2 4CC09569 ~~ +Po 65151 41955 0 15 4CDDBFF2 4CC09569 ~~ Li SOT23_6 Kw SOT23_5 Sc 4CC09569 AR /4C69ED5F/4CC09483 Op 0 0 0 -T0 661 8 197 197 900 30 N V 21 N"U25" +T0 766 -227 197 197 900 39 N V 21 N"U25" T1 25 0 197 197 0 30 N I 21 N"TPS793XX" DS -200 300 -500 100 50 21 DS 500 300 -525 300 50 21 @@ -18502,7 +18428,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 254 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS" +Ne 256 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS" Po -176 0 $EndPAD $PAD @@ -18530,7 +18456,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 253 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM" +Ne 255 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM" Po -176 0 $EndPAD $PAD @@ -18558,14 +18484,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 258 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE#" +Ne 260 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" +Ne 200 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -18586,14 +18512,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 235 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS#" +Ne 237 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/DDR_Banks/M0_CAS#" +Ne 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -18614,14 +18540,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 294 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS" +Ne 296 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 54 "/DDR_Banks/M1_LDQS" +Ne 56 "/DDR_Banks/M1_LDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -18642,14 +18568,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 293 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM" +Ne 295 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 217 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_LDM" +Ne 55 "/DDR_Banks/M1_LDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -18670,14 +18596,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 298 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE#" +Ne 300 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 57 "/DDR_Banks/M1_WE#" +Ne 60 "/DDR_Banks/M1_WE#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -18698,24 +18624,24 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 274 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS#" +Ne 276 "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 204 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" +Ne 209 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE CRYSTAL -Po 48709 41650 0 0 4CB9DFD5 4CD34A13 ~~ +Po 48709 41650 0 0 4CDDC55B 4CD34A13 ~~ Li CRYSTAL Sc 4CD34A13 AR /4C716A4D/4CD349DF Op 0 0 0 -T0 417 1173 280 180 0 45 M V 20 N"X1" +T0 1531 374 394 394 0 45 M V 20 N"X1" T1 394 -961 600 600 0 120 M I 20 N"FXO-HC536R" DC 0 -433 -59 -423 30 20 DS -374 955 -374 -325 30 20 @@ -18752,13 +18678,13 @@ Po 0 630 $EndPAD $EndMODULE CRYSTAL $MODULE 0402 -Po 59768 47606 2700 15 4C5FF890 4CD34B13 ~~ +Po 59768 47606 2700 15 4CDDBDC6 4CD34B13 ~~ Li 0402 Sc 4CD34B13 AR /4C9E2B0F/4CD34ACB Op 0 0 0 At SMD -T0 0 -150 200 200 2700 40 N V 25 N"FB3" +T0 8 343 200 200 2700 40 N V 25 N"FB3" T1 0 150 200 200 2700 40 N I 25 N"FILTER" DS -305 168 -305 -168 50 21 DS -305 -168 305 -168 50 21 @@ -18808,12 +18734,12 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE CRYSTAL -Po 53311 40102 1800 0 4CD364B3 4CD34E74 ~~ +Po 53311 40102 1800 0 4CDDC543 4CD34E74 ~~ Li CRYSTAL Sc 4CD34E74 AR /4C7BC2B2/4CD34D72 Op 0 0 0 -T0 1091 -540 280 180 1800 45 M V 20 N"X2" +T0 386 -650 394 394 1800 45 M V 20 N"X2" T1 394 -961 600 600 1800 120 M I 20 N"FXO-HC536R" DC 0 -433 -59 -423 30 20 DS -374 955 -374 -325 30 20 @@ -18838,7 +18764,7 @@ $PAD Sh "3" R 551 453 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/FPGA_GPIOS/FPGA_BANK0_IO_38" +Ne 101 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_38" Po 866 630 $EndPAD $PAD @@ -19159,6 +19085,90 @@ Ne 0 "" Po 0 3937 $EndPAD $EndMODULE M12-HLD-001 +$MODULE 0603 +Po 46984 19717 2700 0 4C5FF890 4C8934E6 ~~ +Li 0603 +Sc 4C8934E6 +AR /4C4320F3/4C5D7DC4 +Op 0 0 0 +At SMD +T0 0 150 200 200 2700 40 M V 20 N"R9" +T1 0 -150 200 200 2700 40 M I 20 N"1M" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 74 "/Ethernet_Phy/MAG_SHIELD" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 356 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 58717 18953 0 0 4CDDCF7E 4C7D382E ~~ +Li 0603 +Sc 4C7D382E +AR /4C5F1EDC/4C5F2D27 +Op 0 0 0 +At SMD +T0 -36 417 200 200 0 40 M V 20 N"R10" +T1 0 -150 200 200 0 40 M I 20 N"1M" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 354 "/USB/USB_CASE_HOST" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 356 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 58862 14728 2700 15 4CDDD070 4C7D382C ~~ +Li 0603 +Sc 4C7D382C +AR /4C5F1EDC/4C6552B6 +Op 0 0 0 +At SMD +T0 -11 382 200 200 2700 40 N V 25 N"R15" +T1 0 150 200 200 2700 40 N I 25 N"1M" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 353 "/USB/USB_CASE_DEV" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 356 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 $COTATION Ge 0 25 0 Va 39410 @@ -20658,6 +20668,20 @@ Po 0 61192 42997 61373 43178 157 -1 De 15 0 7 0 0 Po 0 61373 43178 61751 43178 157 -1 De 15 0 7 0 400 +Po 0 47103 20863 47103 21093 118 -1 +De 0 0 8 0 800 +Po 3 47102 21094 47102 21094 157 -1 +De 15 1 8 0 0 +Po 0 47103 21093 47102 21094 118 -1 +De 0 0 8 0 0 +Po 0 47781 19858 47781 20136 118 -1 +De 0 0 8 0 800 +Po 0 47783 20138 47787 20138 118 -1 +De 15 0 8 0 0 +Po 3 47783 20138 47783 20138 157 -1 +De 15 1 8 0 0 +Po 0 47781 20136 47783 20138 118 -1 +De 0 0 8 0 0 Po 0 51134 39723 51134 39973 79 -1 De 0 0 8 0 800 Po 0 55150 40358 56650 40358 79 -1 @@ -21172,18 +21196,6 @@ Po 0 53556 30142 53556 30233 79 -1 De 0 0 8 0 800 Po 0 53556 30233 53317 30472 79 -1 De 0 0 8 0 0 -Po 0 47103 20272 47103 20511 79 -1 -De 0 0 8 0 800 -Po 0 47103 20611 47059 20567 79 -1 -De 0 0 8 0 0 -Po 0 47059 20567 47047 20567 79 -1 -De 0 0 8 0 0 -Po 3 47047 20567 47047 20567 157 -1 -De 15 1 8 0 0 -Po 0 47103 20611 47103 20863 79 -1 -De 0 0 8 0 400 -Po 0 47103 20511 47047 20567 79 -1 -De 0 0 8 0 0 Po 0 56073 30639 56062 30639 79 -1 De 15 0 8 0 800 Po 0 55876 30453 55886 30463 79 -1 @@ -21782,348 +21794,368 @@ Po 0 60772 22291 60772 22075 39 -1 De 15 0 15 0 0 Po 0 60772 22075 60219 21522 39 -1 De 15 0 15 0 0 +Po 0 58883 22806 58840 22806 39 -1 +De 15 0 16 0 800 +Po 0 46110 41276 46331 41497 39 -1 +De 15 0 16 0 0 +Po 0 46331 41497 47639 41497 39 -1 +De 15 0 16 0 400 +Po 0 55625 23343 58173 23343 39 -1 +De 2 0 16 0 0 +Po 0 48869 29049 51366 26552 39 -1 +De 2 0 16 0 0 +Po 0 51366 26552 51366 25205 39 -1 +De 2 0 16 0 0 +Po 0 51366 25205 53228 23343 39 -1 +De 2 0 16 0 0 +Po 0 53228 23343 55625 23343 39 -1 +De 2 0 16 0 0 +Po 0 46031 30591 47573 29049 39 -1 +De 2 0 16 0 0 +Po 0 46031 41205 46031 30591 39 -1 +De 2 0 16 0 0 +Po 0 46102 41276 46031 41205 39 -1 +De 2 0 16 0 0 +Po 3 46102 41276 46102 41276 157 -1 +De 15 1 16 0 0 +Po 0 47573 29049 48869 29049 39 -1 +De 2 0 16 0 0 +Po 3 58445 23071 58445 23071 157 -1 +De 15 1 16 0 0 +Po 0 58173 23343 58445 23071 39 -1 +De 2 0 16 0 0 +Po 0 46102 41276 46110 41276 39 -1 +De 15 0 16 0 0 +Po 0 58575 23071 58445 23071 39 -1 +De 15 0 16 0 0 +Po 0 58840 22806 58575 23071 39 -1 +De 15 0 16 0 0 Po 0 62162 29228 60850 29228 39 -1 -De 3 0 16 0 0 +De 3 0 17 0 0 Po 0 50865 40906 51138 40906 39 -1 -De 15 0 16 0 800 -Po 0 65067 29228 62162 29228 39 -1 -De 3 0 16 0 0 -Po 0 66157 30318 65067 29228 39 -1 -De 3 0 16 0 0 -Po 0 66157 39225 66157 30318 39 -1 -De 3 0 16 0 0 -Po 0 65500 39882 66157 39225 39 -1 -De 3 0 16 0 0 -Po 0 60272 39882 65500 39882 39 -1 -De 3 0 16 0 0 -Po 0 59713 40441 60272 39882 39 -1 -De 3 0 16 0 0 -Po 0 51682 40441 59713 40441 39 -1 -De 3 0 16 0 0 -Po 0 51217 40906 51682 40441 39 -1 -De 3 0 16 0 0 -Po 3 51217 40906 51217 40906 157 -1 -De 15 1 16 0 0 -Po 0 51138 40906 51217 40906 39 -1 -De 15 0 16 0 0 -Po 0 57964 32610 57799 32445 39 -1 -De 3 0 16 0 0 -Po 0 58417 32610 57964 32610 39 -1 -De 3 0 16 0 0 -Po 0 58818 32209 58417 32610 39 -1 -De 3 0 16 0 0 -Po 0 59220 32209 58818 32209 39 -1 -De 3 0 16 0 0 -Po 0 59606 31823 59220 32209 39 -1 -De 3 0 16 0 0 -Po 0 59606 30472 59606 31823 39 -1 -De 3 0 16 0 0 -Po 0 60850 29228 59606 30472 39 -1 -De 3 0 16 0 0 -Po 3 57799 32445 57799 32445 157 -1 -De 15 1 16 0 0 -Po 0 57646 32598 57799 32445 39 -1 -De 15 0 16 0 0 -Po 0 57646 32607 57646 32598 39 -1 -De 15 0 16 0 800 -Po 0 59024 32004 59122 32004 39 -1 -De 3 0 17 0 0 -Po 0 58840 31820 59024 32004 39 -1 -De 15 0 17 0 0 -Po 3 59024 32004 59024 32004 157 -1 -De 15 1 17 0 0 -Po 0 58827 31820 58840 31820 39 -1 De 15 0 17 0 800 -Po 0 51219 41103 50865 41103 39 -1 -De 15 0 17 0 400 -Po 0 65100 29147 62227 29147 39 -1 +Po 0 65067 29228 62162 29228 39 -1 De 3 0 17 0 0 -Po 0 66238 30285 65100 29147 39 -1 +Po 0 66157 30318 65067 29228 39 -1 De 3 0 17 0 0 -Po 0 66238 39258 66238 30285 39 -1 +Po 0 66157 39225 66157 30318 39 -1 De 3 0 17 0 0 -Po 0 65533 39963 66238 39258 39 -1 +Po 0 65500 39882 66157 39225 39 -1 De 3 0 17 0 0 -Po 0 60324 39963 65533 39963 39 -1 +Po 0 60272 39882 65500 39882 39 -1 De 3 0 17 0 0 -Po 0 59756 40531 60324 39963 39 -1 +Po 0 59713 40441 60272 39882 39 -1 De 3 0 17 0 0 -Po 0 51791 40531 59756 40531 39 -1 +Po 0 51682 40441 59713 40441 39 -1 De 3 0 17 0 0 -Po 0 51413 40909 51791 40531 39 -1 +Po 0 51217 40906 51682 40441 39 -1 De 3 0 17 0 0 -Po 3 51413 40909 51413 40909 157 -1 +Po 3 51217 40906 51217 40906 157 -1 De 15 1 17 0 0 -Po 0 51219 41103 51413 40909 39 -1 +Po 0 51138 40906 51217 40906 39 -1 De 15 0 17 0 0 -Po 0 60778 29147 62227 29147 39 -1 +Po 0 57964 32610 57799 32445 39 -1 De 3 0 17 0 0 -Po 0 59488 30437 60778 29147 39 -1 +Po 0 58417 32610 57964 32610 39 -1 De 3 0 17 0 0 -Po 0 59488 30528 59488 30437 39 -1 +Po 0 58818 32209 58417 32610 39 -1 De 3 0 17 0 0 -Po 0 59193 30823 59488 30528 39 -1 +Po 0 59220 32209 58818 32209 39 -1 De 3 0 17 0 0 -Po 0 59193 31933 59193 30823 39 -1 +Po 0 59606 31823 59220 32209 39 -1 De 3 0 17 0 0 -Po 0 59122 32004 59193 31933 39 -1 +Po 0 59606 30472 59606 31823 39 -1 De 3 0 17 0 0 -Po 0 62311 29066 60237 29066 39 -1 +Po 0 60850 29228 59606 30472 39 -1 +De 3 0 17 0 0 +Po 3 57799 32445 57799 32445 157 -1 +De 15 1 17 0 0 +Po 0 57646 32598 57799 32445 39 -1 +De 15 0 17 0 0 +Po 0 57646 32607 57646 32598 39 -1 +De 15 0 17 0 800 +Po 0 59024 32004 59122 32004 39 -1 De 3 0 18 0 0 -Po 0 59221 30082 59366 29937 59 -1 +Po 0 58840 31820 59024 32004 39 -1 De 15 0 18 0 0 -Po 3 59366 29937 59366 29937 157 -1 +Po 3 59024 32004 59024 32004 157 -1 De 15 1 18 0 0 -Po 0 59221 30245 59221 30082 59 -1 +Po 0 58827 31820 58840 31820 39 -1 De 15 0 18 0 800 -Po 0 59791 40610 60357 40044 39 -1 -De 3 0 18 0 0 -Po 0 60357 40044 65566 40044 39 -1 -De 3 0 18 0 0 -Po 0 65566 40044 66319 39291 39 -1 -De 3 0 18 0 0 -Po 0 66319 39291 66319 30252 39 -1 -De 3 0 18 0 0 -Po 0 66319 30252 65133 29066 39 -1 -De 3 0 18 0 0 -Po 0 62331 29066 62311 29066 39 -1 -De 3 0 18 0 0 -Po 0 65133 29066 62331 29066 39 -1 -De 3 0 18 0 0 -Po 0 51220 41300 50865 41300 39 -1 +Po 0 51219 41103 50865 41103 39 -1 De 15 0 18 0 400 -Po 0 57215 40612 57217 40610 39 -1 +Po 0 65100 29147 62227 29147 39 -1 De 3 0 18 0 0 -Po 0 51908 40612 57215 40612 39 -1 +Po 0 66238 30285 65100 29147 39 -1 De 3 0 18 0 0 -Po 0 51614 40906 51908 40612 39 -1 +Po 0 66238 39258 66238 30285 39 -1 De 3 0 18 0 0 -Po 3 51614 40906 51614 40906 157 -1 +Po 0 65533 39963 66238 39258 39 -1 +De 3 0 18 0 0 +Po 0 60324 39963 65533 39963 39 -1 +De 3 0 18 0 0 +Po 0 59756 40531 60324 39963 39 -1 +De 3 0 18 0 0 +Po 0 51791 40531 59756 40531 39 -1 +De 3 0 18 0 0 +Po 0 51413 40909 51791 40531 39 -1 +De 3 0 18 0 0 +Po 3 51413 40909 51413 40909 157 -1 De 15 1 18 0 0 -Po 0 51220 41300 51614 40906 39 -1 +Po 0 51219 41103 51413 40909 39 -1 De 15 0 18 0 0 -Po 0 57217 40610 59791 40610 39 -1 +Po 0 60778 29147 62227 29147 39 -1 De 3 0 18 0 0 -Po 0 60237 29066 59366 29937 39 -1 +Po 0 59488 30437 60778 29147 39 -1 De 3 0 18 0 0 -Po 0 59221 30245 59239 30245 59 -1 -De 15 0 18 0 800 -Po 0 60828 40125 65599 40125 39 -1 +Po 0 59488 30528 59488 30437 39 -1 +De 3 0 18 0 0 +Po 0 59193 30823 59488 30528 39 -1 +De 3 0 18 0 0 +Po 0 59193 31933 59193 30823 39 -1 +De 3 0 18 0 0 +Po 0 59122 32004 59193 31933 39 -1 +De 3 0 18 0 0 +Po 0 62311 29066 60237 29066 39 -1 De 3 0 19 0 0 -Po 0 65599 40125 66400 39324 39 -1 -De 3 0 19 0 0 -Po 0 62388 28985 60070 28985 39 -1 -De 3 0 19 0 0 -Po 0 51227 41497 51811 40913 39 -1 +Po 0 59221 30082 59366 29937 59 -1 De 15 0 19 0 0 -Po 3 51811 40913 51811 40913 157 -1 +Po 3 59366 29937 59366 29937 157 -1 De 15 1 19 0 0 -Po 0 51811 40913 51909 40815 39 -1 -De 3 0 19 0 0 -Po 0 51909 40815 57236 40815 39 -1 -De 3 0 19 0 0 -Po 0 57236 40815 57437 41016 39 -1 -De 3 0 19 0 0 -Po 0 57437 41016 59937 41016 39 -1 -De 3 0 19 0 0 -Po 0 59937 41016 60828 40125 39 -1 -De 3 0 19 0 0 -Po 0 66400 39324 66400 30219 39 -1 -De 3 0 19 0 0 -Po 0 66400 30219 65166 28985 39 -1 -De 3 0 19 0 0 -Po 0 65166 28985 62388 28985 39 -1 -De 3 0 19 0 0 -Po 0 50865 41497 51227 41497 39 -1 +Po 0 59221 30245 59221 30082 59 -1 De 15 0 19 0 800 -Po 0 60070 28985 60071 28984 39 -1 +Po 0 59791 40610 60357 40044 39 -1 De 3 0 19 0 0 -Po 0 59134 29925 59134 30638 39 -1 +Po 0 60357 40044 65566 40044 39 -1 De 3 0 19 0 0 -Po 0 59134 30638 58965 30807 39 -1 +Po 0 65566 40044 66319 39291 39 -1 De 3 0 19 0 0 -Po 0 58827 31027 58965 30807 39 -1 -De 15 0 19 0 0 -Po 3 58965 30807 58965 30807 157 -1 -De 15 1 19 0 0 -Po 0 58827 31027 58827 31032 39 -1 +Po 0 66319 39291 66319 30252 39 -1 +De 3 0 19 0 0 +Po 0 66319 30252 65133 29066 39 -1 +De 3 0 19 0 0 +Po 0 62331 29066 62311 29066 39 -1 +De 3 0 19 0 0 +Po 0 65133 29066 62331 29066 39 -1 +De 3 0 19 0 0 +Po 0 51220 41300 50865 41300 39 -1 De 15 0 19 0 400 -Po 0 59209 29846 59209 29850 39 -1 +Po 0 57215 40612 57217 40610 39 -1 De 3 0 19 0 0 -Po 0 59209 29850 59134 29925 39 -1 +Po 0 51908 40612 57215 40612 39 -1 De 3 0 19 0 0 -Po 0 59134 29925 59138 29921 59 -1 +Po 0 51614 40906 51908 40612 39 -1 De 3 0 19 0 0 -Po 0 59209 29846 60071 28984 39 -1 +Po 3 51614 40906 51614 40906 157 -1 +De 15 1 19 0 0 +Po 0 51220 41300 51614 40906 39 -1 +De 15 0 19 0 0 +Po 0 57217 40610 59791 40610 39 -1 De 3 0 19 0 0 -Po 0 59213 29842 59209 29846 59 -1 +Po 0 60237 29066 59366 29937 39 -1 De 3 0 19 0 0 -Po 0 49815 45381 49815 46917 39 -1 +Po 0 59221 30245 59239 30245 59 -1 +De 15 0 19 0 800 +Po 0 60828 40125 65599 40125 39 -1 +De 3 0 20 0 0 +Po 0 65599 40125 66400 39324 39 -1 +De 3 0 20 0 0 +Po 0 62388 28985 60070 28985 39 -1 +De 3 0 20 0 0 +Po 0 51227 41497 51811 40913 39 -1 +De 15 0 20 0 0 +Po 3 51811 40913 51811 40913 157 -1 +De 15 1 20 0 0 +Po 0 51811 40913 51909 40815 39 -1 +De 3 0 20 0 0 +Po 0 51909 40815 57236 40815 39 -1 +De 3 0 20 0 0 +Po 0 57236 40815 57437 41016 39 -1 +De 3 0 20 0 0 +Po 0 57437 41016 59937 41016 39 -1 +De 3 0 20 0 0 +Po 0 59937 41016 60828 40125 39 -1 +De 3 0 20 0 0 +Po 0 66400 39324 66400 30219 39 -1 +De 3 0 20 0 0 +Po 0 66400 30219 65166 28985 39 -1 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18738 53041 18738 53177 18738 53471 18738 53607 18738 53861 18738 54875 18738 -45941 18818 46624 18818 +46212 18818 46624 18818 46761 18818 46897 18818 47351 18818 47487 18818 47622 18818 52824 18818 52961 18818 53097 18818 53551 18818 53687 18818 53822 18818 54875 18818 -45941 18898 46817 18898 +46212 18898 46817 18898 47431 18898 53017 18898 53631 18898 54875 18898 -45941 18978 46788 18978 +46213 18978 46788 18978 47459 18978 52988 18978 53659 18978 54875 18978 -45941 19058 46904 19058 +46213 19058 46904 19058 47341 19058 53104 19058 53541 19058 54875 19058 -45941 19138 54875 19138 -45941 19218 46190 19218 -46378 19218 54875 19218 +46214 19138 54875 19138 +46214 19218 54875 19218 $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE @@ -60756,28 +60755,18 @@ ZCorner 53988 17354 0 ZCorner 53988 13370 0 ZCorner 46436 13370 0 ZCorner 46436 17382 0 -ZCorner 45472 18346 0 -ZCorner 45472 19335 1 +ZCorner 46161 17689 0 +ZCorner 46165 19331 1 $POLYSCORNERS -54879 19285 0 0 +54879 19284 0 0 54879 18315 0 0 53938 17374 0 0 53938 13618 0 0 46486 13618 0 0 -46486 17402 0 0 -45941 17947 0 0 -45941 19285 0 0 -46083 19285 0 0 -46104 19265 0 0 -46150 19234 0 0 -46202 19213 0 0 -46257 19203 0 0 -46313 19203 0 0 -46368 19214 0 0 -46419 19236 0 0 -46465 19267 0 0 -46483 19285 0 0 -46697 19285 0 1 +46486 17401 0 0 +46211 17708 0 0 +46214 19281 0 0 +46697 19281 0 1 46697 18882 0 0 46628 18824 0 0 46598 18766 0 0 @@ -60789,8 +60778,8 @@ $POLYSCORNERS 46697 18164 0 0 47056 18523 0 0 46697 18882 0 1 -46697 19285 0 0 -47149 19285 0 1 +46697 19281 0 0 +47149 19281 0 1 47149 19102 0 0 47036 19096 0 0 46925 19068 0 0 @@ -60802,8 +60791,8 @@ $POLYSCORNERS 47367 19049 0 0 47260 19087 0 0 47149 19102 0 1 -47149 19285 0 0 -47551 19285 0 1 +47149 19281 0 0 +47551 19281 0 1 47551 18882 0 0 47192 18523 0 0 47124 18455 0 0 @@ -60863,8 +60852,8 @@ $POLYSCORNERS 47669 18722 0 0 47620 18824 0 0 47551 18882 0 1 -47551 19285 0 0 -48636 19285 0 1 +47551 19281 0 0 +48636 19281 0 1 48636 17917 0 0 48042 17323 0 0 48636 16729 0 0 @@ -60876,8 +60865,8 @@ $POLYSCORNERS 48820 17661 0 0 48738 17819 0 0 48636 17917 0 1 -48636 19285 0 0 -51812 19285 0 1 +48636 19281 0 0 +51812 19282 0 1 51812 17917 0 0 51710 17819 0 0 51636 17679 0 0 @@ -60889,8 +60878,8 @@ $POLYSCORNERS 51812 16729 0 0 52406 17323 0 0 51812 17917 0 1 -51812 19285 0 0 -52897 19285 0 1 +51812 19282 0 0 +52897 19283 0 1 52897 18882 0 0 52828 18824 0 0 52798 18766 0 0 @@ -60950,8 +60939,8 @@ $POLYSCORNERS 53324 18455 0 0 53256 18523 0 0 52897 18882 0 1 -52897 19285 0 0 -53349 19285 0 1 +52897 19283 0 0 +53349 19283 0 1 53349 19102 0 0 53236 19096 0 0 53125 19068 0 0 @@ -60963,8 +60952,8 @@ $POLYSCORNERS 53567 19049 0 0 53460 19087 0 0 53349 19102 0 1 -53349 19285 0 0 -53751 19285 0 1 +53349 19283 0 0 +53751 19283 0 1 53751 18882 0 0 53392 18523 0 0 53751 18164 0 0 @@ -60976,7 +60965,7 @@ $POLYSCORNERS 53869 18722 0 0 53820 18824 0 0 53751 18882 0 1 -53751 19285 1 0 +53751 19283 1 0 $endPOLYSCORNERS $FILLSEGMENTS 46486 13618 53938 13618 @@ -61085,62 +61074,62 @@ $FILLSEGMENTS 48879 17378 51568 17378 52351 17378 52597 17378 53379 17378 53942 17378 -46430 17458 47077 17458 +46434 17458 47077 17458 47771 17458 47907 17458 48041 17458 48177 17458 48871 17458 51577 17458 52271 17458 52407 17458 52541 17458 52677 17458 53371 17458 54022 17458 -46350 17538 47091 17538 +46363 17538 47091 17538 47691 17538 47827 17538 48121 17538 48257 17538 48855 17538 51591 17538 52191 17538 52327 17538 52621 17538 52757 17538 53355 17538 54102 17538 -46270 17618 47116 17618 +46291 17618 47116 17618 47611 17618 47747 17618 48201 17618 48337 17618 48832 17618 51616 17618 52111 17618 52247 17618 52701 17618 52837 17618 53332 17618 54182 17618 -46190 17698 47146 17698 +46219 17698 47146 17698 47531 17698 47667 17698 48281 17698 48417 17698 48800 17698 51646 17698 52031 17698 52167 17698 52781 17698 52917 17698 53300 17698 54262 17698 -46110 17778 47188 17778 +46212 17778 47188 17778 47451 17778 47587 17778 48361 17778 48497 17778 48759 17778 51688 17778 51951 17778 52087 17778 52861 17778 52997 17778 53259 17778 54342 17778 -46030 17858 47250 17858 +46212 17858 47250 17858 47371 17858 47507 17858 48441 17858 48577 17858 48697 17858 51750 17858 51871 17858 52007 17858 52941 17858 53077 17858 53197 17858 54422 17858 -45950 17938 47427 17938 +46212 17938 47427 17938 48521 17938 51927 17938 53021 17938 54502 17938 -45941 18018 46841 18018 +46212 18018 46841 18018 47408 18018 47412 18018 48536 18018 51911 18018 53035 18018 53040 18018 53607 18018 54582 18018 -45941 18098 46767 18098 +46212 18098 46767 18098 47481 18098 47499 18098 48449 18098 51999 18098 52949 18098 52967 18098 53681 18098 54662 18098 -45941 18178 46681 18178 +46212 18178 46681 18178 46711 18178 46847 18178 47533 18178 47537 18178 47568 18178 47667 18178 @@ -61149,64 +61138,63 @@ $FILLSEGMENTS 52911 18178 52915 18178 53601 18178 53737 18178 53768 18178 54742 18178 -45941 18258 46611 18258 +46213 18258 46611 18258 46791 18258 46927 18258 47639 18258 52811 18258 53521 18258 53657 18258 53839 18258 54822 18258 -45941 18338 46576 18338 +46213 18338 46576 18338 46871 18338 47007 18338 47671 18338 52776 18338 53441 18338 53577 18338 53871 18338 54879 18338 -45941 18418 46556 18418 +46213 18418 46556 18418 46951 18418 47087 18418 47693 18418 52756 18418 53361 18418 53497 18418 53893 18418 54879 18418 -45941 18498 46548 18498 +46213 18498 46548 18498 47031 18498 47167 18498 47703 18498 52748 18498 53281 18498 53417 18498 53903 18498 54879 18498 -45941 18578 46549 18578 +46213 18578 46549 18578 47001 18578 47247 18578 47698 18578 52749 18578 53201 18578 53447 18578 53898 18578 54879 18578 -45941 18658 46559 18658 +46213 18658 46559 18658 46921 18658 47057 18658 47191 18658 47327 18658 47685 18658 52759 18658 53121 18658 53257 18658 53391 18658 53527 18658 53885 18658 54879 18658 -45941 18738 46588 18738 +46213 18738 46588 18738 46841 18738 46977 18738 47271 18738 47407 18738 47661 18738 52788 18738 53041 18738 53177 18738 53471 18738 53607 18738 53861 18738 54879 18738 -45941 18818 46624 18818 +46214 18818 46624 18818 46761 18818 46897 18818 47351 18818 47487 18818 47622 18818 52824 18818 52961 18818 53097 18818 53551 18818 53687 18818 53822 18818 54879 18818 -45941 18898 46817 18898 +46214 18898 46817 18898 47431 18898 53017 18898 53631 18898 54879 18898 -45941 18978 46788 18978 +46214 18978 46788 18978 47459 18978 52988 18978 53659 18978 54879 18978 -45941 19058 46904 19058 +46214 19058 46904 19058 47341 19058 53104 19058 53541 19058 54879 19058 -45941 19138 54879 19138 -45941 19218 46190 19218 -46378 19218 54879 19218 +46214 19138 54879 19138 +46214 19218 54879 19218 $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE @@ -61216,34 +61204,17 @@ ZAux 8 E ZClearance 157 T ZMinThickness 100 ZOptions 1 32 F 39 197 +ZCorner 46185 19339 0 ZCorner 54929 19335 0 ZCorner 54929 18291 0 ZCorner 53988 17350 0 ZCorner 53988 13370 0 ZCorner 46440 13370 0 ZCorner 46440 17378 0 -ZCorner 45472 18346 0 -ZCorner 45472 19335 1 +ZCorner 46154 17689 1 $POLYSCORNERS -54879 19285 0 0 -54879 18311 0 0 -53938 17370 0 0 -53938 13618 0 0 -46490 13618 0 0 -46490 17398 0 0 -45941 17947 0 0 -45941 19285 0 0 -46083 19285 0 0 -46104 19265 0 0 -46150 19234 0 0 -46202 19213 0 0 -46257 19203 0 0 -46313 19203 0 0 -46368 19214 0 0 -46419 19236 0 0 -46465 19267 0 0 -46483 19285 0 0 -46697 19285 0 1 +46234 19288 0 0 +46697 19287 0 1 46697 18882 0 0 46628 18824 0 0 46598 18766 0 0 @@ -61255,8 +61226,8 @@ $POLYSCORNERS 46697 18164 0 0 47056 18523 0 0 46697 18882 0 1 -46697 19285 0 0 -47149 19285 0 1 +46697 19287 0 0 +47149 19287 0 1 47149 19102 0 0 47036 19096 0 0 46925 19068 0 0 @@ -61268,8 +61239,8 @@ $POLYSCORNERS 47367 19049 0 0 47260 19087 0 0 47149 19102 0 1 -47149 19285 0 0 -47551 19285 0 1 +47149 19287 0 0 +47551 19287 0 1 47551 18882 0 0 47192 18523 0 0 47124 18455 0 0 @@ -61329,8 +61300,8 @@ $POLYSCORNERS 47669 18722 0 0 47620 18824 0 0 47551 18882 0 1 -47551 19285 0 0 -48636 19285 0 1 +47551 19287 0 0 +48636 19287 0 1 48636 17917 0 0 48042 17323 0 0 48636 16729 0 0 @@ -61342,8 +61313,8 @@ $POLYSCORNERS 48820 17661 0 0 48738 17819 0 0 48636 17917 0 1 -48636 19285 0 0 -51812 19285 0 1 +48636 19287 0 0 +51812 19286 0 1 51812 17917 0 0 51710 17819 0 0 51636 17679 0 0 @@ -61355,7 +61326,7 @@ $POLYSCORNERS 51812 16729 0 0 52406 17323 0 0 51812 17917 0 1 -51812 19285 0 0 +51812 19286 0 0 52897 19285 0 1 52897 18882 0 0 52828 18824 0 0 @@ -61442,7 +61413,14 @@ $POLYSCORNERS 53869 18722 0 0 53820 18824 0 0 53751 18882 0 1 -53751 19285 1 0 +53751 19285 0 0 +54879 19285 0 0 +54879 18311 0 0 +53938 17370 0 0 +53938 13618 0 0 +46490 13618 0 0 +46490 17397 0 0 +46204 17708 1 0 $endPOLYSCORNERS $FILLSEGMENTS 46490 13618 53938 13618 @@ -61551,62 +61529,62 @@ $FILLSEGMENTS 48879 17378 51568 17378 52351 17378 52597 17378 53379 17378 53946 17378 -46430 17458 47077 17458 +46433 17458 47077 17458 47771 17458 47907 17458 48041 17458 48177 17458 48871 17458 51577 17458 52271 17458 52407 17458 52541 17458 52677 17458 53371 17458 54026 17458 -46350 17538 47091 17538 +46360 17538 47091 17538 47691 17538 47827 17538 48121 17538 48257 17538 48855 17538 51591 17538 52191 17538 52327 17538 52621 17538 52757 17538 53355 17538 54106 17538 -46270 17618 47116 17618 +46286 17618 47116 17618 47611 17618 47747 17618 48201 17618 48337 17618 48832 17618 51616 17618 52111 17618 52247 17618 52701 17618 52837 17618 53332 17618 54186 17618 -46190 17698 47146 17698 +46213 17698 47146 17698 47531 17698 47667 17698 48281 17698 48417 17698 48800 17698 51646 17698 52031 17698 52167 17698 52781 17698 52917 17698 53300 17698 54266 17698 -46110 17778 47188 17778 +46206 17778 47188 17778 47451 17778 47587 17778 48361 17778 48497 17778 48759 17778 51688 17778 51951 17778 52087 17778 52861 17778 52997 17778 53259 17778 54346 17778 -46030 17858 47250 17858 +46207 17858 47250 17858 47371 17858 47507 17858 48441 17858 48577 17858 48697 17858 51750 17858 51871 17858 52007 17858 52941 17858 53077 17858 53197 17858 54426 17858 -45950 17938 47427 17938 +46209 17938 47427 17938 48521 17938 51927 17938 53021 17938 54506 17938 -45941 18018 46841 18018 +46210 18018 46841 18018 47408 18018 47412 18018 48536 18018 51911 18018 53035 18018 53040 18018 53607 18018 54586 18018 -45941 18098 46767 18098 +46212 18098 46767 18098 47481 18098 47499 18098 48449 18098 51999 18098 52949 18098 52967 18098 53681 18098 54666 18098 -45941 18178 46681 18178 +46213 18178 46681 18178 46711 18178 46847 18178 47533 18178 47537 18178 47568 18178 47667 18178 @@ -61615,68 +61593,67 @@ $FILLSEGMENTS 52911 18178 52915 18178 53601 18178 53737 18178 53768 18178 54746 18178 -45941 18258 46611 18258 +46215 18258 46611 18258 46791 18258 46927 18258 47639 18258 52811 18258 53521 18258 53657 18258 53839 18258 54826 18258 -45941 18338 46576 18338 +46216 18338 46576 18338 46871 18338 47007 18338 47671 18338 52776 18338 53441 18338 53577 18338 53871 18338 54879 18338 -45941 18418 46556 18418 +46218 18418 46556 18418 46951 18418 47087 18418 47693 18418 52756 18418 53361 18418 53497 18418 53893 18418 54879 18418 -45941 18498 46548 18498 +46219 18498 46548 18498 47031 18498 47167 18498 47703 18498 52748 18498 53281 18498 53417 18498 53903 18498 54879 18498 -45941 18578 46549 18578 +46221 18578 46549 18578 47001 18578 47247 18578 47698 18578 52749 18578 53201 18578 53447 18578 53898 18578 54879 18578 -45941 18658 46559 18658 +46223 18658 46559 18658 46921 18658 47057 18658 47191 18658 47327 18658 47685 18658 52759 18658 53121 18658 53257 18658 53391 18658 53527 18658 53885 18658 54879 18658 -45941 18738 46588 18738 +46224 18738 46588 18738 46841 18738 46977 18738 47271 18738 47407 18738 47661 18738 52788 18738 53041 18738 53177 18738 53471 18738 53607 18738 53861 18738 54879 18738 -45941 18818 46624 18818 +46226 18818 46624 18818 46761 18818 46897 18818 47351 18818 47487 18818 47622 18818 52824 18818 52961 18818 53097 18818 53551 18818 53687 18818 53822 18818 54879 18818 -45941 18898 46817 18898 +46227 18898 46817 18898 47431 18898 53017 18898 53631 18898 54879 18898 -45941 18978 46788 18978 +46229 18978 46788 18978 47459 18978 52988 18978 53659 18978 54879 18978 -45941 19058 46904 19058 +46230 19058 46904 19058 47341 19058 53104 19058 53541 19058 54879 19058 -45941 19138 54879 19138 -45941 19218 46190 19218 -46378 19218 54879 19218 +46232 19138 54879 19138 +46233 19218 54879 19218 $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4CBB57E6 22 "/DBG_PRG/USB_CASE_FTDI" +ZInfo 4CBB57E6 23 "/DBG_PRG/USB_CASE_FTDI" ZLayer 15 ZAux 9 E ZClearance 59 T diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp index 7712db8..8942412 100644 --- a/kicad/xue-rnc/xue-rnc.cmp +++ b/kicad/xue-rnc/xue-rnc.cmp @@ -1,4 +1,4 @@ -Cmp-Mod V01 Created by CvPCB (2010-11-03 BZR 2592)-testing date = Thu 11 Nov 2010 02:14:40 PM COT +Cmp-Mod V01 Genere par PcbNew le Fri 12 Nov 2010 06:24:04 PM COT BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; @@ -1250,14 +1250,14 @@ BeginCmp TimeStamp = /4C4320F3/4C5D7DC4; Reference = R9; ValeurCmp = 1M; -IdModule = 1206; +IdModule = 0603; EndCmp BeginCmp TimeStamp = /4C5F1EDC/4C5F2D27; Reference = R10; ValeurCmp = 1M; -IdModule = 1206; +IdModule = 0603; EndCmp BeginCmp @@ -1292,7 +1292,7 @@ BeginCmp TimeStamp = /4C5F1EDC/4C6552B6; Reference = R15; ValeurCmp = 1M; -IdModule = 1206; +IdModule = 0603; EndCmp BeginCmp diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 5408e86..0017bb8 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,4 +1,4 @@ -# EESchema Netlist Version 1.1 created Thu 11 Nov 2010 02:14:40 PM COT +# EESchema Netlist Version 1.1 created Fri 12 Nov 2010 06:21:08 PM COT ( ( /4C4320F3/4C5D7F9F 0603 C1 1uF ( 1 +3.3V ) @@ -648,7 +648,7 @@ ( 37 /DBG_PRG/AVR_RST ) ( 38 /DBG_PRG/AVR_MISO ) ( 39 /DBG_PRG/AVR_MOSI ) - ( 40 /PSU/AVR_SCK ) + ( 40 /DBG_PRG/AVR_SCK ) ( 41 ? ) ( 42 /DBG_PRG/VCC_USB ) ( 43 N-000227 ) @@ -659,14 +659,14 @@ ( 48 ? ) ) ( /4C4227FE/4B76F5E2 MICROSD-500901 J1 MICROSD - ( 1 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2 ) - ( 2 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT3 ) - ( 3 /FPGA,_Port0,_Port2,_PROG_IF/SD_CMD ) + ( 1 /Non_volatile_memories/SD_DAT2 ) + ( 2 /Non_volatile_memories/SD_DAT3 ) + ( 3 /Non_volatile_memories/SD_CMD ) ( 4 +3.3V ) - ( 5 /FPGA,_Port0,_Port2,_PROG_IF/SD_CLK ) + ( 5 /Non_volatile_memories/SD_CLK ) ( 6 GND ) - ( 7 /Non_volatile_memories/SD_DAT0 ) - ( 8 /Non_volatile_memories/SD_DAT1 ) + ( 7 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0 ) + ( 8 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT1 ) ( CASE GND ) ( CD ? ) ( COM GND ) @@ -681,7 +681,7 @@ ( 7 /Ethernet_Phy/MAG_RX+ ) ( 8 /Ethernet_Phy/MAG_RX- ) ( 9 +3.3V ) - ( 10 N-000137 ) + ( 10 N-000139 ) ( 11 +3.3V ) ( 12 N-000147 ) ( 13 /Ethernet_Phy/MAG_SHIELD ) @@ -764,55 +764,55 @@ ( 2 ? ) ) ( /4CB0D95D/4CBAFE50 header25x2_smd_2mm P1 CONN_25X2 - ( 1 /FPGA_GPIOS/FPGA_BANK0_IO_8 ) - ( 2 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1 ) + ( 1 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8 ) + ( 2 /FPGA_GPIOS/FPGA_BANK0_IO_1 ) ( 3 GND ) ( 4 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9 ) ( 5 VCCO2 ) - ( 6 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14 ) + ( 6 /FPGA_GPIOS/FPGA_BANK0_IO_14 ) ( 7 /FPGA_GPIOS/FPGA_BANK0_IO_10 ) - ( 8 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_15 ) + ( 8 /FPGA_GPIOS/FPGA_BANK0_IO_15 ) ( 9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11 ) ( 10 /FPGA_GPIOS/FPGA_BANK0_IO_3 ) - ( 11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_5 ) + ( 11 /FPGA_GPIOS/FPGA_BANK0_IO_5 ) ( 12 /FPGA_GPIOS/FPGA_BANK0_IO_18 ) - ( 13 /FPGA_GPIOS/FPGA_BANK0_IO_17 ) - ( 14 /FPGA_GPIOS/FPGA_BANK0_IO_21 ) - ( 15 /FPGA_GPIOS/FPGA_BANK0_IO_20 ) + ( 13 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17 ) + ( 14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21 ) + ( 15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20 ) ( 16 /FPGA_GPIOS/FPGA_BANK0_IO_24 ) - ( 17 /FPGA_GPIOS/FPGA_BANK0_IO_28 ) - ( 18 /FPGA_GPIOS/FPGA_BANK0_IO_29 ) - ( 19 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22 ) - ( 20 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_30 ) + ( 17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_28 ) + ( 18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29 ) + ( 19 /FPGA_GPIOS/FPGA_BANK0_IO_22 ) + ( 20 /FPGA_GPIOS/FPGA_BANK0_IO_30 ) ( 21 /FPGA_GPIOS/FPGA_BANK0_IO_27 ) ( 22 /FPGA_GPIOS/FPGA_BANK0_IO_25 ) - ( 23 /FPGA_GPIOS/FPGA_BANK0_IO_39 ) + ( 23 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39 ) ( 24 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33 ) ( 25 /FPGA_GPIOS/FPGA_BANK0_IO_2 ) - ( 26 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32 ) - ( 27 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_7 ) + ( 26 /FPGA_GPIOS/FPGA_BANK0_IO_32 ) + ( 27 /FPGA_GPIOS/FPGA_BANK0_IO_7 ) ( 28 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6 ) ( 29 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12 ) - ( 30 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36 ) - ( 31 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44 ) + ( 30 /FPGA_GPIOS/FPGA_BANK0_IO_36 ) + ( 31 /FPGA_GPIOS/FPGA_BANK0_IO_44 ) ( 32 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40 ) - ( 33 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47 ) - ( 34 /FPGA_GPIOS/FPGA_BANK0_IO_43 ) - ( 35 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_45 ) - ( 36 /FPGA_GPIOS/FPGA_BANK0_IO_46 ) + ( 33 /FPGA_GPIOS/FPGA_BANK0_IO_47 ) + ( 34 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43 ) + ( 35 /FPGA_GPIOS/FPGA_BANK0_IO_45 ) + ( 36 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46 ) ( 37 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52 ) - ( 38 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50 ) - ( 39 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56 ) + ( 38 /FPGA_GPIOS/FPGA_BANK0_IO_50 ) + ( 39 /FPGA_GPIOS/FPGA_BANK0_IO_56 ) ( 40 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48 ) - ( 41 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_51 ) - ( 42 /FPGA_GPIOS/FPGA_BANK0_IO_34 ) - ( 43 /FPGA_GPIOS/FPGA_BANK0_IO_54 ) - ( 44 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_49 ) - ( 45 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_63 ) - ( 46 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_62 ) - ( 47 /FPGA_GPIOS/FPGA_BANK0_IO_53 ) + ( 41 /FPGA_GPIOS/FPGA_BANK0_IO_51 ) + ( 42 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_34 ) + ( 43 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_54 ) + ( 44 /FPGA_GPIOS/FPGA_BANK0_IO_49 ) + ( 45 /FPGA_GPIOS/FPGA_BANK0_IO_63 ) + ( 46 /FPGA_GPIOS/FPGA_BANK0_IO_62 ) + ( 47 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_53 ) ( 48 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_57 ) - ( 49 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_58 ) + ( 49 /FPGA_GPIOS/FPGA_BANK0_IO_58 ) ( 50 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_60 ) ) ( /4C4320F3/4C5D7F39 0402 R1 4.7K @@ -820,7 +820,7 @@ ( 2 +3.3V ) ) ( /4C4320F3/4C5D7ECF 0402 R2 6.65K - ( 1 N-000138 ) + ( 1 N-000140 ) ( 2 GND ) ) ( /4C4320F3/4C5D7AFE 0402 R3 49.9 @@ -840,18 +840,18 @@ ( 2 /Ethernet_Phy/MAG_RX- ) ) ( /4C4320F3/4C5D719D 0402 R7 220 - ( 1 N-000137 ) + ( 1 N-000139 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D71DB 0402 R8 220 ( 1 N-000147 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) - ( /4C4320F3/4C5D7DC4 1206 R9 1M + ( /4C4320F3/4C5D7DC4 0603 R9 1M ( 1 /Ethernet_Phy/MAG_SHIELD ) ( 2 GND ) ) - ( /4C5F1EDC/4C5F2D27 1206 R10 1M + ( /4C5F1EDC/4C5F2D27 0603 R10 1M ( 1 /USB/USB_CASE_HOST ) ( 2 GND ) ) @@ -871,13 +871,13 @@ ( 1 /DDR_Banks/M1_VREF ) ( 2 GND ) ) - ( /4C5F1EDC/4C6552B6 1206 R15 1M + ( /4C5F1EDC/4C6552B6 0603 R15 1M ( 1 /USB/USB_CASE_DEV ) ( 2 GND ) ) ( /4C7BC2A2/4C69DF7A 0402 R16 120 ( 1 /DDR_Banks/M1_CLK# ) - ( 2 /DDR_Banks/M1_CLK ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK ) ) ( /4C7BC2A2/4C69E7F8 0402 R17 33 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE ) @@ -893,7 +893,7 @@ ) ( /4C7BC2A2/4C69E92D 0402 R20 33 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS# ) - ( 2 /DDR_Banks/M1_CS# ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CS# ) ) ( /4C7BC2A2/4C6B1B90 0402 R21 120 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK ) @@ -901,15 +901,15 @@ ) ( /4C7BC2A2/4C6B216D 0402 R22 33 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS ) - ( 2 /DDR_Banks/M0_UDQS ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS ) ) ( /4C7BC2A2/4C6B216E 0402 R23 33 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM ) - ( 2 /DDR_Banks/M0_UDM ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM ) ) ( /4C7BC2A2/4C6B216B 0402 R24 33 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE ) - ( 2 /DDR_Banks/M0_CKE ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE ) ) ( /4C69ED5F/4C6D2DBC 0402 R25 200K ( 1 /PSU/VFB3.3 ) @@ -1137,7 +1137,7 @@ ) ( /4C7BC2A2/4CCF27AA 0402 R81 33 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM ) - ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDM ) + ( 2 /DDR_Banks/M1_LDM ) ) ( /4C7BC2A2/4CCF27A8 0402 R82 33 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDQS ) @@ -1145,7 +1145,7 @@ ) ( /4C7BC2A2/4CCF2733 0402 R83 33 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS# ) - ( 2 /DDR_Banks/M0_CAS# ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS# ) ) ( /4C7BC2A2/4CCF272F 0402 R84 33 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE# ) @@ -1165,8 +1165,8 @@ ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A3 ) - ( 6 /DDR_Banks/M1_A2 ) - ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A1 ) + ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A2 ) + ( 7 /DDR_Banks/M1_A1 ) ( 8 /DDR_Banks/M1_A0 ) ) ( /4C7BC2A2/4C69CEE8 R_PACK4-0402 RP2 R_PACK4 @@ -1175,34 +1175,34 @@ ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A10 ) - ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1 ) + ( 6 /DDR_Banks/M1_BA1 ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0 ) - ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS# ) + ( 8 /DDR_Banks/M1_RAS# ) ) ( /4C7BC2A2/4C69D3A3 R_PACK4-0402 RP4 R_PACK4 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4 ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7 ) - ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7 ) + ( 5 /DDR_Banks/M1_DQ7 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6 ) - ( 7 /DDR_Banks/M1_DQ5 ) - ( 8 /DDR_Banks/M1_DQ4 ) + ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4 ) ) ( /4C7BC2A2/4C69D3A9 R_PACK4-0402 RP5 R_PACK4 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ0 ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ1 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ2 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ3 ) - ( 5 /DDR_Banks/M1_DQ3 ) - ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2 ) + ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3 ) + ( 6 /DDR_Banks/M1_DQ2 ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1 ) ( 8 /DDR_Banks/M1_DQ0 ) ) ( /4C7BC2A2/4C69DA8A R_PACK4-0402 RP6 R_PACK4 ( 1 /DDR_Banks/M1_A7 ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A6 ) - ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A5 ) + ( 3 /DDR_Banks/M1_A5 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A4 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A5 ) @@ -1211,8 +1211,8 @@ ) ( /4C7BC2A2/4C69DC05 R_PACK4-0402 RP7 R_PACK4 ( 1 /DDR_Banks/M1_A12 ) - ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A11 ) - ( 3 /DDR_Banks/M1_A9 ) + ( 2 /DDR_Banks/M1_A11 ) + ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A9 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A8 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9 ) @@ -1220,18 +1220,18 @@ ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12 ) ) ( /4C7BC2A2/4C69E299 R_PACK4-0402 RP8 R_PACK4 - ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15 ) - ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14 ) - ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13 ) - ( 4 /DDR_Banks/M1_DQ12 ) + ( 1 /DDR_Banks/M1_DQ15 ) + ( 2 /DDR_Banks/M1_DQ14 ) + ( 3 /DDR_Banks/M1_DQ13 ) + ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13 ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14 ) ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15 ) ) ( /4C7BC2A2/4C69E3A6 R_PACK4-0402 RP9 R_PACK4 - ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11 ) - ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10 ) + ( 1 /DDR_Banks/M1_DQ11 ) + ( 2 /DDR_Banks/M1_DQ10 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8 ) @@ -1255,9 +1255,9 @@ ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11 ) - ( 6 /DDR_Banks/M0_DQ10 ) - ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9 ) - ( 8 /DDR_Banks/M0_DQ8 ) + ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10 ) + ( 7 /DDR_Banks/M0_DQ9 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8 ) ) ( /4C7BC2A2/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4 ) @@ -1266,7 +1266,7 @@ ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7 ) ( 5 /DDR_Banks/M0_DQ7 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6 ) - ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5 ) + ( 7 /DDR_Banks/M0_DQ5 ) ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4 ) ) ( /4C7BC2A2/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 @@ -1275,8 +1275,8 @@ ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ2 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ3 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3 ) - ( 6 /DDR_Banks/M0_DQ2 ) - ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1 ) + ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2 ) + ( 7 /DDR_Banks/M0_DQ1 ) ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0 ) ) ( /4C7BC2A2/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 @@ -1294,7 +1294,7 @@ ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10 ) - ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A10 ) + ( 5 /DDR_Banks/M0_A10 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1 ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0 ) ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS# ) @@ -1304,9 +1304,9 @@ ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4 ) - ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A4 ) + ( 5 /DDR_Banks/M0_A4 ) ( 6 /DDR_Banks/M0_A5 ) - ( 7 /DDR_Banks/M0_A6 ) + ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A6 ) ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A7 ) ) ( /4C7BC2A2/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 @@ -1314,10 +1314,10 @@ ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A9 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A8 ) - ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A8 ) - ( 6 /DDR_Banks/M0_A9 ) - ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A11 ) - ( 8 /DDR_Banks/M0_A12 ) + ( 5 /DDR_Banks/M0_A8 ) + ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A9 ) + ( 7 /DDR_Banks/M0_A11 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A12 ) ) ( /4C716A4D/4CB9DD95 TP40R TP1 CONN_1 ( 1 N-000235 ) @@ -1371,23 +1371,23 @@ ( A1 GND ) ( A2 ? ) ( A3 GND ) - ( A4 /Ethernet_Phy/ETH_CLK ) - ( A5 /Ethernet_Phy/ETH_RXD1 ) + ( A4 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK ) + ( A5 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1 ) ( A6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV ) - ( A7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC ) + ( A7 /Ethernet_Phy/ETH_RXC ) ( A8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3 ) - ( A9 /Ethernet_Phy/ETH_COL ) - ( A10 /Ethernet_Phy/ETH_INT ) + ( A9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_COL ) + ( A10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_INT ) ( A11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D6 ) ( A12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D4 ) ( A13 /FPGA,_Port0,_Port2,_PROG_IF/NF_D2 ) - ( A14 /FPGA,_Port0,_Port2,_PROG_IF/NF_ALE ) - ( A15 /Non_volatile_memories/NF_RNB ) - ( A16 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2 ) - ( A17 /FPGA,_Port0,_Port2,_PROG_IF/SD_CLK ) - ( A18 /Non_volatile_memories/SD_DAT0 ) + ( A14 /Non_volatile_memories/NF_ALE ) + ( A15 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB ) + ( A16 /Non_volatile_memories/SD_DAT2 ) + ( A17 /Non_volatile_memories/SD_CLK ) + ( A18 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0 ) ( A19 /DBG_PRG/FPGA_TDO ) - ( A20 /USB/USBD_RCV ) + ( A20 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV ) ( A21 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N ) ( A22 GND ) ( AA1 N-000401 ) @@ -1403,9 +1403,9 @@ ( AA11 VCCO2 ) ( AA12 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1 ) ( AA13 GND ) - ( AA14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22 ) + ( AA14 /FPGA_GPIOS/FPGA_BANK0_IO_22 ) ( AA15 VCCO2 ) - ( AA16 /FPGA_GPIOS/FPGA_BANK0_IO_28 ) + ( AA16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_28 ) ( AA17 GND ) ( AA18 /FPGA_GPIOS/FPGA_BANK0_IO_18 ) ( AA19 VCCO2 ) @@ -1414,21 +1414,21 @@ ( AA22 VCCO2 ) ( AB1 GND ) ( AB2 /FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME ) - ( AB3 /Image_Sensor/IS_FLASH ) - ( AB4 /Image_Sensor/IS_I2C_ADDR ) - ( AB5 /Image_Sensor/IS_RESET_N ) - ( AB6 /Image_Sensor/IS_PIXEL ) - ( AB7 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11 ) - ( AB8 /Image_Sensor/IS_DOUT8 ) - ( AB9 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5 ) + ( AB3 /FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH ) + ( AB4 /FPGA,_Port0,_Port2,_PROG_IF/IS_I2C_ADDR ) + ( AB5 /FPGA,_Port0,_Port2,_PROG_IF/IS_RESET_N ) + ( AB6 /FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL ) + ( AB7 /Image_Sensor/IS_DOUT11 ) + ( AB8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8 ) + ( AB9 /Image_Sensor/IS_DOUT5 ) ( AB10 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3 ) - ( AB11 /Image_Sensor/IS_DOUT2 ) - ( AB12 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0 ) - ( AB13 /FPGA_GPIOS/FPGA_BANK0_IO_39 ) + ( AB11 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2 ) + ( AB12 /Image_Sensor/IS_DOUT0 ) + ( AB13 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39 ) ( AB14 ? ) ( AB15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33 ) - ( AB16 /FPGA_GPIOS/FPGA_BANK0_IO_29 ) - ( AB17 /FPGA_GPIOS/FPGA_BANK0_IO_21 ) + ( AB16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29 ) + ( AB17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21 ) ( AB18 ? ) ( AB19 ? ) ( AB20 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO0 ) @@ -1439,42 +1439,42 @@ ( B3 ? ) ( B4 +3.3V ) ( B5 GND ) - ( B6 /Ethernet_Phy/ETH_RXD0 ) + ( B6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 ) ( B7 +3.3V ) ( B8 /Ethernet_Phy/ETH_RXER ) ( B9 GND ) - ( B10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS ) + ( B10 /Ethernet_Phy/ETH_CRS ) ( B11 +3.3V ) - ( B12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D3 ) + ( B12 /Non_volatile_memories/NF_D3 ) ( B13 GND ) - ( B14 /FPGA,_Port0,_Port2,_PROG_IF/NF_CLE ) + ( B14 /Non_volatile_memories/NF_CLE ) ( B15 +3.3V ) - ( B16 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT3 ) + ( B16 /Non_volatile_memories/SD_DAT3 ) ( B17 GND ) - ( B18 /Non_volatile_memories/SD_DAT1 ) + ( B18 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT1 ) ( B19 +3.3V ) ( B20 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD ) ( B21 /USB/USBD_VP ) - ( B22 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM ) + ( B22 /USB/USBD_VM ) ( C1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A11 ) ( C2 +2.5V ) ( C3 ? ) ( C4 ? ) - ( C5 /Ethernet_Phy/ETH_RXD3 ) + ( C5 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3 ) ( C6 /Ethernet_Phy/ETH_RXD2 ) ( C7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N ) ( C8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC ) ( C9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1 ) - ( C10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2 ) + ( C10 /Ethernet_Phy/ETH_TXD2 ) ( C11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 ) ( C12 /Non_volatile_memories/NF_D0 ) ( C13 ? ) ( C14 /FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N ) ( C15 /FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N ) - ( C16 /FPGA,_Port0,_Port2,_PROG_IF/SD_CMD ) + ( C16 /Non_volatile_memories/SD_CMD ) ( C17 ? ) ( C18 /DBG_PRG/FPGA_TMS ) - ( C19 /USB/USBA_OE_N ) + ( C19 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N ) ( C20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8 ) ( C21 +2.5V ) ( C22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9 ) @@ -1484,19 +1484,19 @@ ( D4 GND ) ( D5 ? ) ( D6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO ) - ( D7 /Ethernet_Phy/ETH_MDC ) - ( D8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER ) + ( D7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC ) + ( D8 /Ethernet_Phy/ETH_TXER ) ( D9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN ) ( D10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 ) ( D11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D7 ) ( D12 ? ) ( D13 ? ) ( D14 /FPGA,_Port0,_Port2,_PROG_IF/NF_D1 ) - ( D15 /Non_volatile_memories/NF_CS1_N ) + ( D15 /FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N ) ( D16 +2.5V ) ( D17 ? ) ( D18 GND ) - ( D19 /USB/USBA_VP ) + ( D19 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP ) ( D20 /USB/USBA_VM ) ( D21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE ) ( D22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A12 ) @@ -1537,8 +1537,8 @@ ( F13 ? ) ( F14 ? ) ( F15 ? ) - ( F16 /USB/USBA_SPD ) - ( F17 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV ) + ( F16 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD ) + ( F17 /USB/USBA_RCV ) ( F18 ? ) ( F19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11 ) ( F20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4 ) @@ -1585,7 +1585,7 @@ ( H17 ? ) ( H18 ? ) ( H19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE# ) - ( H20 /DDR_Banks/M1_CLK ) + ( H20 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK ) ( H21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS# ) ( H22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS# ) ( J1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ5 ) @@ -1728,7 +1728,7 @@ ( R6 +2.5V ) ( R7 ? ) ( R8 ? ) - ( R9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_58 ) + ( R9 /FPGA_GPIOS/FPGA_BANK0_IO_58 ) ( R10 +2.5V ) ( R11 ? ) ( R12 +2.5V ) @@ -1749,17 +1749,17 @@ ( T5 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO ) ( T6 ? ) ( T7 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_60 ) - ( T8 /FPGA_GPIOS/FPGA_BANK0_IO_53 ) + ( T8 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_53 ) ( T9 VCCO2 ) ( T10 ? ) ( T11 ? ) - ( T12 /FPGA_GPIOS/FPGA_BANK0_IO_34 ) + ( T12 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_34 ) ( T13 VCCO2 ) - ( T14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36 ) - ( T15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_7 ) + ( T14 /FPGA_GPIOS/FPGA_BANK0_IO_36 ) + ( T15 /FPGA_GPIOS/FPGA_BANK0_IO_7 ) ( T16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_6 ) ( T17 /FPGA_GPIOS/FPGA_BANK0_IO_2 ) - ( T18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1 ) + ( T18 /FPGA_GPIOS/FPGA_BANK0_IO_1 ) ( T19 ? ) ( T20 ? ) ( T21 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS ) @@ -1769,18 +1769,18 @@ ( U3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12 ) ( U4 ? ) ( U5 +2.5V ) - ( U6 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_62 ) + ( U6 /FPGA_GPIOS/FPGA_BANK0_IO_62 ) ( U7 GND ) - ( U8 /FPGA_GPIOS/FPGA_BANK0_IO_54 ) - ( U9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_51 ) - ( U10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56 ) + ( U8 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_54 ) + ( U9 /FPGA_GPIOS/FPGA_BANK0_IO_51 ) + ( U10 /FPGA_GPIOS/FPGA_BANK0_IO_56 ) ( U11 +2.5V ) ( U12 ? ) ( U13 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3 ) ( U14 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 ) ( U15 GND ) ( U16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9 ) - ( U17 /FPGA_GPIOS/FPGA_BANK0_IO_8 ) + ( U17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8 ) ( U18 +2.5V ) ( U19 ? ) ( U20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12 ) @@ -1790,19 +1790,19 @@ ( V2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14 ) ( V3 ? ) ( V4 GND ) - ( V5 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_63 ) + ( V5 /FPGA_GPIOS/FPGA_BANK0_IO_63 ) ( V6 +2.5V ) - ( V7 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_49 ) + ( V7 /FPGA_GPIOS/FPGA_BANK0_IO_49 ) ( V8 VCCO2 ) ( V9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_52 ) ( V10 GND ) - ( V11 /FPGA_GPIOS/FPGA_BANK0_IO_43 ) + ( V11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43 ) ( V12 VCCO2 ) ( V13 ? ) ( V14 GND ) - ( V15 /FPGA_GPIOS/FPGA_BANK0_IO_17 ) + ( V15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17 ) ( V16 VCCO2 ) - ( V17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14 ) + ( V17 /FPGA_GPIOS/FPGA_BANK0_IO_14 ) ( V18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11 ) ( V19 /FPGA_GPIOS/FPGA_BANK0_IO_10 ) ( V20 ? ) @@ -1816,15 +1816,15 @@ ( W6 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_57 ) ( W7 GND ) ( W8 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48 ) - ( W9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50 ) - ( W10 /FPGA_GPIOS/FPGA_BANK0_IO_46 ) - ( W11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44 ) + ( W9 /FPGA_GPIOS/FPGA_BANK0_IO_50 ) + ( W10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46 ) + ( W11 /FPGA_GPIOS/FPGA_BANK0_IO_44 ) ( W12 /Image_Sensor/IS_EXTCLK ) ( W13 /FPGA_GPIOS/FPGA_BANK0_IO_27 ) - ( W14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_30 ) + ( W14 /FPGA_GPIOS/FPGA_BANK0_IO_30 ) ( W15 /FPGA_GPIOS/FPGA_BANK0_IO_25 ) ( W16 GND ) - ( W17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_15 ) + ( W17 /FPGA_GPIOS/FPGA_BANK0_IO_15 ) ( W18 ? ) ( W19 GND ) ( W20 ? ) @@ -1833,21 +1833,21 @@ ( Y1 ? ) ( Y2 ? ) ( Y3 /Image_Sensor/IS_TRIGGER ) - ( Y4 /FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N ) - ( Y5 /Image_Sensor/IS_STANDBY ) + ( Y4 /Image_Sensor/IS_OE_N ) + ( Y5 /FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY ) ( Y6 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10 ) ( Y7 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9 ) ( Y8 /Image_Sensor/IS_DOUT6 ) - ( Y9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_45 ) - ( Y10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47 ) + ( Y9 /FPGA_GPIOS/FPGA_BANK0_IO_45 ) + ( Y10 /FPGA_GPIOS/FPGA_BANK0_IO_47 ) ( Y11 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40 ) - ( Y12 /Image_Sensor/IS_SCL ) - ( Y13 /FPGA_GPIOS/FPGA_BANK0_IO_38 ) + ( Y12 /FPGA,_Port0,_Port2,_PROG_IF/IS_SCL ) + ( Y13 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_38 ) ( Y14 ? ) - ( Y15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32 ) + ( Y15 /FPGA_GPIOS/FPGA_BANK0_IO_32 ) ( Y16 /FPGA_GPIOS/FPGA_BANK0_IO_24 ) - ( Y17 /FPGA_GPIOS/FPGA_BANK0_IO_20 ) - ( Y18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_5 ) + ( Y17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20 ) + ( Y18 /FPGA_GPIOS/FPGA_BANK0_IO_5 ) ( Y19 /FPGA_GPIOS/FPGA_BANK0_IO_3 ) ( Y20 +3.3V ) ( Y21 ? ) @@ -1857,13 +1857,13 @@ ( 1 +2.5V ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1 ) - ( 5 /DDR_Banks/M0_DQ2 ) + ( 4 /DDR_Banks/M0_DQ1 ) + ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2 ) ( 6 GND ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3 ) ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4 ) ( 9 +2.5V ) - ( 10 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5 ) + ( 10 /DDR_Banks/M0_DQ5 ) ( 11 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6 ) ( 12 GND ) ( 13 /DDR_Banks/M0_DQ7 ) @@ -1875,42 +1875,42 @@ ( 19 ? ) ( 20 /DDR_Banks/M0_LDM ) ( 21 /FPGA_Port_1,_Port_3_DDR,_USB/M0_WE# ) - ( 22 /DDR_Banks/M0_CAS# ) + ( 22 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS# ) ( 23 /FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA0 ) ( 27 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1 ) - ( 28 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A10 ) + ( 28 /DDR_Banks/M0_A10 ) ( 29 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A0 ) ( 30 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A1 ) ( 31 /DDR_Banks/M0_A2 ) ( 32 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A4 ) + ( 35 /DDR_Banks/M0_A4 ) ( 36 /DDR_Banks/M0_A5 ) - ( 37 /DDR_Banks/M0_A6 ) + ( 37 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A6 ) ( 38 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A7 ) - ( 39 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A8 ) - ( 40 /DDR_Banks/M0_A9 ) - ( 41 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A11 ) - ( 42 /DDR_Banks/M0_A12 ) + ( 39 /DDR_Banks/M0_A8 ) + ( 40 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A9 ) + ( 41 /DDR_Banks/M0_A11 ) + ( 42 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A12 ) ( 43 ? ) ( 44 /DDR_Banks/M0_CLK# ) - ( 45 /DDR_Banks/M0_CKE ) + ( 45 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE ) ( 46 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK ) - ( 47 /DDR_Banks/M0_UDM ) + ( 47 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM ) ( 48 GND ) ( 49 /DDR_Banks/M0_VREF ) ( 50 ? ) - ( 51 /DDR_Banks/M0_UDQS ) + ( 51 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M0_DQ8 ) + ( 54 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9 ) - ( 57 /DDR_Banks/M0_DQ10 ) + ( 56 /DDR_Banks/M0_DQ9 ) + ( 57 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10 ) ( 58 GND ) ( 59 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ11 ) ( 60 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12 ) @@ -1926,48 +1926,48 @@ ( 2 /DDR_Banks/M1_DQ0 ) ( 3 +2.5V ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1 ) - ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2 ) + ( 5 /DDR_Banks/M1_DQ2 ) ( 6 GND ) - ( 7 /DDR_Banks/M1_DQ3 ) - ( 8 /DDR_Banks/M1_DQ4 ) + ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4 ) ( 9 +2.5V ) - ( 10 /DDR_Banks/M1_DQ5 ) + ( 10 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5 ) ( 11 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7 ) + ( 13 /DDR_Banks/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /DDR_Banks/M1_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDM ) + ( 20 /DDR_Banks/M1_LDM ) ( 21 /DDR_Banks/M1_WE# ) ( 22 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS# ) - ( 23 /FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS# ) - ( 24 /DDR_Banks/M1_CS# ) + ( 23 /DDR_Banks/M1_RAS# ) + ( 24 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CS# ) ( 25 ? ) ( 26 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0 ) - ( 27 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1 ) + ( 27 /DDR_Banks/M1_BA1 ) ( 28 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A10 ) ( 29 /DDR_Banks/M1_A0 ) - ( 30 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A1 ) - ( 31 /DDR_Banks/M1_A2 ) + ( 30 /DDR_Banks/M1_A1 ) + ( 31 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A2 ) ( 32 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A4 ) - ( 36 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A5 ) + ( 36 /DDR_Banks/M1_A5 ) ( 37 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A6 ) ( 38 /DDR_Banks/M1_A7 ) ( 39 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A8 ) - ( 40 /DDR_Banks/M1_A9 ) - ( 41 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A11 ) + ( 40 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A9 ) + ( 41 /DDR_Banks/M1_A11 ) ( 42 /DDR_Banks/M1_A12 ) ( 43 ? ) ( 44 /DDR_Banks/M1_CLK# ) ( 45 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE ) - ( 46 /DDR_Banks/M1_CLK ) + ( 46 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK ) ( 47 /DDR_Banks/M1_UDM ) ( 48 GND ) ( 49 /DDR_Banks/M1_VREF ) @@ -1978,43 +1978,43 @@ ( 54 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8 ) ( 55 +2.5V ) ( 56 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ9 ) - ( 57 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10 ) + ( 57 /DDR_Banks/M1_DQ10 ) ( 58 GND ) - ( 59 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11 ) - ( 60 /DDR_Banks/M1_DQ12 ) + ( 59 /DDR_Banks/M1_DQ11 ) + ( 60 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12 ) ( 61 +2.5V ) - ( 62 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13 ) - ( 63 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ14 ) + ( 62 /DDR_Banks/M1_DQ13 ) + ( 63 /DDR_Banks/M1_DQ14 ) ( 64 GND ) - ( 65 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15 ) + ( 65 /DDR_Banks/M1_DQ15 ) ( 66 GND ) ) ( /4C4320F3/4C432132 LQFP48 U4 K8001 ( 1 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO ) - ( 2 /Ethernet_Phy/ETH_MDC ) - ( 3 /Ethernet_Phy/ETH_RXD3 ) + ( 2 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC ) + ( 3 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3 ) ( 4 /Ethernet_Phy/ETH_RXD2 ) - ( 5 /Ethernet_Phy/ETH_RXD1 ) - ( 6 /Ethernet_Phy/ETH_RXD0 ) + ( 5 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1 ) + ( 6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 ) ( 7 +3.3V ) ( 8 GND ) ( 9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXDV ) - ( 10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC ) + ( 10 /Ethernet_Phy/ETH_RXC ) ( 11 /Ethernet_Phy/ETH_RXER ) ( 12 GND ) ( 13 +1.8V ) - ( 14 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER ) + ( 14 /Ethernet_Phy/ETH_TXER ) ( 15 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC ) ( 16 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN ) ( 17 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 ) ( 18 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1 ) - ( 19 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2 ) + ( 19 /Ethernet_Phy/ETH_TXD2 ) ( 20 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3 ) - ( 21 /Ethernet_Phy/ETH_COL ) - ( 22 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CRS ) + ( 21 /FPGA,_Port0,_Port2,_PROG_IF/ETH_COL ) + ( 22 /Ethernet_Phy/ETH_CRS ) ( 23 GND ) ( 24 +3.3V ) - ( 25 /Ethernet_Phy/ETH_INT ) + ( 25 /FPGA,_Port0,_Port2,_PROG_IF/ETH_INT ) ( 26 /Ethernet_Phy/ETH_LED0 ) ( 27 /Ethernet_Phy/ETH_LED1 ) ( 28 ? ) @@ -2026,7 +2026,7 @@ ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000138 ) + ( 37 N-000140 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) ( 40 /Ethernet_Phy/MAG_TX- ) @@ -2035,7 +2035,7 @@ ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 /Ethernet_Phy/ETH_CLK ) + ( 46 /FPGA,_Port0,_Port2,_PROG_IF/ETH_CLK ) ( 47 /Ethernet_Phy/ETH_PLL1.8V ) ( 48 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N ) ) @@ -2045,18 +2045,18 @@ ( 3 ? ) ( 4 ? ) ( 5 ? ) - ( 6 /Non_volatile_memories/NF_RNB ) - ( 7 /Non_volatile_memories/NF_RNB ) + ( 6 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB ) + ( 7 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB ) ( 8 /FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N ) - ( 9 /Non_volatile_memories/NF_CS1_N ) + ( 9 /FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N ) ( 10 ? ) ( 11 ? ) ( 12 +3.3V ) ( 13 GND ) ( 14 ? ) ( 15 ? ) - ( 16 /FPGA,_Port0,_Port2,_PROG_IF/NF_CLE ) - ( 17 /FPGA,_Port0,_Port2,_PROG_IF/NF_ALE ) + ( 16 /Non_volatile_memories/NF_CLE ) + ( 17 /Non_volatile_memories/NF_ALE ) ( 18 /FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N ) ( 19 +3.3V ) ( 20 ? ) @@ -2071,7 +2071,7 @@ ( 29 /Non_volatile_memories/NF_D0 ) ( 30 /FPGA,_Port0,_Port2,_PROG_IF/NF_D1 ) ( 31 /FPGA,_Port0,_Port2,_PROG_IF/NF_D2 ) - ( 32 /FPGA,_Port0,_Port2,_PROG_IF/NF_D3 ) + ( 32 /Non_volatile_memories/NF_D3 ) ( 33 ? ) ( 34 ? ) ( 35 ? ) @@ -2090,13 +2090,13 @@ ( 48 ? ) ) ( /4C5F1EDC/4C71BA1D MLF16 U6 MIC2550-MLF - ( 1 /USB/USBA_SPD ) - ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV ) - ( 3 /USB/USBA_VP ) + ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD ) + ( 2 /USB/USBA_RCV ) + ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP ) ( 4 /USB/USBA_VM ) ( 6 GND ) ( 7 GND ) - ( 9 /USB/USBA_OE_N ) + ( 9 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N ) ( 10 N-000154 ) ( 11 N-000153 ) ( 12 +3.3V ) @@ -2105,9 +2105,9 @@ ) ( /4C5F1EDC/4C71BA25 MLF16 U7 MIC2550-MLF ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD ) - ( 2 /USB/USBD_RCV ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV ) ( 3 /USB/USBD_VP ) - ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM ) + ( 4 /USB/USBD_VM ) ( 6 GND ) ( 7 GND ) ( 9 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_OE_N ) @@ -2128,7 +2128,7 @@ ( 8 VCCO2 ) ) ( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF - ( 1 /PSU/AVR_SCK ) + ( 1 /DBG_PRG/AVR_SCK ) ( 2 /PSU/Iout_1.2 ) ( 3 /PSU/1.2V_EN ) ( 4 /PSU/lout_3.3 ) @@ -2255,31 +2255,31 @@ ) ( /4C9E2AF4/4C9E3B7C iLCC-48 U24 MT9M033 ( 1 /Image_Sensor/IS_DOUT4 ) - ( 2 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5 ) + ( 2 /Image_Sensor/IS_DOUT5 ) ( 3 /Image_Sensor/IS_DOUT6 ) ( 4 +2.8_VDDPLL ) ( 5 /Image_Sensor/IS_EXTCLK ) ( 6 GND ) ( 7 /Image_Sensor/IS_DOUT7 ) - ( 8 /Image_Sensor/IS_DOUT8 ) + ( 8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8 ) ( 9 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9 ) ( 10 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10 ) - ( 11 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11 ) + ( 11 /Image_Sensor/IS_DOUT11 ) ( 12 +2.8_VDDIO ) - ( 13 /Image_Sensor/IS_PIXEL ) + ( 13 /FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL ) ( 14 /Image_Sensor/+1.8_VDD ) - ( 15 /Image_Sensor/IS_SCL ) + ( 15 /FPGA,_Port0,_Port2,_PROG_IF/IS_SCL ) ( 16 /FPGA,_Port0,_Port2,_PROG_IF/IS_SDA ) - ( 17 /Image_Sensor/IS_RESET_N ) + ( 17 /FPGA,_Port0,_Port2,_PROG_IF/IS_RESET_N ) ( 18 +2.8_VDDIO ) ( 19 /Image_Sensor/+1.8_VDD ) ( 20 ? ) ( 21 ? ) - ( 22 /Image_Sensor/IS_STANDBY ) - ( 23 /FPGA,_Port0,_Port2,_PROG_IF/IS_OE_N ) - ( 24 /Image_Sensor/IS_I2C_ADDR ) + ( 22 /FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY ) + ( 23 /Image_Sensor/IS_OE_N ) + ( 24 /FPGA,_Port0,_Port2,_PROG_IF/IS_I2C_ADDR ) ( 25 /Image_Sensor/IS_TEST ) - ( 26 /Image_Sensor/IS_FLASH ) + ( 26 /FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH ) ( 27 /Image_Sensor/IS_TRIGGER ) ( 28 /FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME ) ( 29 /Image_Sensor/IS_LINE ) @@ -2298,9 +2298,9 @@ ( 42 ? ) ( 43 ? ) ( 44 GND ) - ( 45 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0 ) + ( 45 /Image_Sensor/IS_DOUT0 ) ( 46 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT1 ) - ( 47 /Image_Sensor/IS_DOUT2 ) + ( 47 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT2 ) ( 48 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3 ) ) ( /4C69ED5F/4CC09483 SOT23_6 U25 TPS793XX @@ -2336,7 +2336,7 @@ ( /4C7BC2B2/4CD34D72 CRYSTAL X2 FXO-HC536R ( 1 ? ) ( 2 GND ) - ( 3 /FPGA_GPIOS/FPGA_BANK0_IO_38 ) + ( 3 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_38 ) ( 4 VCCO2 ) ) ) @@ -3068,431 +3068,517 @@ $component R1 R? SM0603 SM0805 + R?-* $endlist $component R2 R? SM0603 SM0805 + R?-* $endlist $component R3 R? SM0603 SM0805 + R?-* $endlist $component R4 R? SM0603 SM0805 + R?-* $endlist $component R5 R? SM0603 SM0805 + R?-* $endlist $component R6 R? SM0603 SM0805 + R?-* $endlist $component R7 R? SM0603 SM0805 + R?-* $endlist $component R8 R? SM0603 SM0805 + R?-* $endlist $component R9 R? SM0603 SM0805 + R?-* $endlist $component R10 R? SM0603 SM0805 + R?-* $endlist $component R11 R? SM0603 SM0805 + R?-* $endlist $component R12 R? SM0603 SM0805 + R?-* $endlist $component R13 R? SM0603 SM0805 + R?-* $endlist $component R14 R? SM0603 SM0805 + R?-* $endlist $component R15 R? SM0603 SM0805 + R?-* $endlist $component R16 R? SM0603 SM0805 + R?-* $endlist $component R17 R? SM0603 SM0805 + R?-* $endlist $component R18 R? SM0603 SM0805 + R?-* $endlist $component R19 R? SM0603 SM0805 + R?-* $endlist $component R20 R? SM0603 SM0805 + R?-* $endlist $component R21 R? SM0603 SM0805 + R?-* $endlist $component R22 R? SM0603 SM0805 + R?-* $endlist $component R23 R? SM0603 SM0805 + R?-* $endlist $component R24 R? SM0603 SM0805 + R?-* $endlist $component R25 R? SM0603 SM0805 + R?-* $endlist $component R26 R? SM0603 SM0805 + R?-* $endlist $component R27 R? SM0603 SM0805 + R?-* $endlist $component R28 R? SM0603 SM0805 + R?-* $endlist $component R29 R? SM0603 SM0805 + R?-* $endlist $component R30 R? SM0603 SM0805 + R?-* $endlist $component R31 R? SM0603 SM0805 + R?-* $endlist $component R32 R? SM0603 SM0805 + R?-* $endlist $component R33 R? SM0603 SM0805 + R?-* $endlist $component R34 R? SM0603 SM0805 + R?-* $endlist $component R35 R? SM0603 SM0805 + R?-* $endlist $component R36 R? SM0603 SM0805 + R?-* $endlist $component R37 R? SM0603 SM0805 + R?-* $endlist $component R38 R? SM0603 SM0805 + R?-* $endlist $component R39 R? SM0603 SM0805 + R?-* $endlist $component R40 R? SM0603 SM0805 + R?-* $endlist $component R41 R? SM0603 SM0805 + R?-* $endlist $component R42 R? SM0603 SM0805 + R?-* $endlist $component R43 R? SM0603 SM0805 + R?-* $endlist $component R44 R? SM0603 SM0805 + R?-* $endlist $component R45 R? SM0603 SM0805 + R?-* $endlist $component R46 R? SM0603 SM0805 + R?-* $endlist $component R47 R? SM0603 SM0805 + R?-* $endlist $component R48 R? SM0603 SM0805 + R?-* $endlist $component R49 R? SM0603 SM0805 + R?-* $endlist $component R50 R? SM0603 SM0805 + R?-* $endlist $component R51 R? SM0603 SM0805 + R?-* $endlist $component R52 R? SM0603 SM0805 + R?-* $endlist $component R53 R? SM0603 SM0805 + R?-* $endlist $component R54 R? SM0603 SM0805 + R?-* $endlist $component R55 R? SM0603 SM0805 + R?-* $endlist $component R56 R? SM0603 SM0805 + R?-* $endlist $component R57 R? SM0603 SM0805 + R?-* $endlist $component R58 R? SM0603 SM0805 + R?-* $endlist $component R59 R? SM0603 SM0805 + R?-* $endlist $component R60 R? SM0603 SM0805 + R?-* $endlist $component R61 R? SM0603 SM0805 + R?-* $endlist $component R62 R? SM0603 SM0805 + R?-* $endlist $component R63 R? SM0603 SM0805 + R?-* $endlist $component R64 R? SM0603 SM0805 + R?-* $endlist $component R65 R? SM0603 SM0805 + R?-* $endlist $component R66 R? SM0603 SM0805 + R?-* $endlist $component R67 R? SM0603 SM0805 + R?-* $endlist $component R68 R? SM0603 SM0805 + R?-* $endlist $component R69 R? SM0603 SM0805 + R?-* $endlist $component R70 R? SM0603 SM0805 + R?-* $endlist $component R71 R? SM0603 SM0805 + R?-* $endlist $component R72 R? SM0603 SM0805 + R?-* $endlist $component R73 R? SM0603 SM0805 + R?-* $endlist $component R74 R? SM0603 SM0805 + R?-* $endlist $component R75 R? SM0603 SM0805 + R?-* $endlist $component R76 R? SM0603 SM0805 + R?-* $endlist $component R77 R? SM0603 SM0805 + R?-* $endlist $component R78 R? SM0603 SM0805 + R?-* $endlist $component R79 R? SM0603 SM0805 + R?-* $endlist $component R80 R? SM0603 SM0805 + R?-* $endlist $component R81 R? SM0603 SM0805 + R?-* $endlist $component R82 R? SM0603 SM0805 + R?-* $endlist $component R83 R? SM0603 SM0805 + R?-* $endlist $component R84 R? SM0603 SM0805 + R?-* $endlist $component R85 R? SM0603 SM0805 + R?-* $endlist $component R86 R? SM0603 SM0805 + R?-* $endlist $endfootprintlist } diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 543fb1e..0542ea9 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,6 +1,6 @@ -update=Thu 11 Nov 2010 02:21:55 PM COT +update=Fri 12 Nov 2010 06:44:24 PM COT version=1 -last_client=kicad +last_client=pcbnew [common] NetDir= [eeschema] @@ -88,12 +88,14 @@ LibName48=../library/reg102 LibName49=../library/mt9m033 LibName50=../library/m12-tu400a LibName51=../library/ft2232c -LibName52=/home/juan64bits/emQbit/xue/kicad/library/fxo-hc536r +LibName52=../library/fxo-hc536r [cvpcb] version=1 NetIExt=net [cvpcb/libraries] EquName1=devcms +[general] +version=1 [pcbnew] version=1 PadDrlX=0 @@ -153,6 +155,4 @@ LibName36=../modules/CRYSTAL LibName37=../modules/TP40R LibName38=../modules/TP66R LibName39=../modules/header25x2_smd_2mm -LibName40=/home/juan64bits/emQbit/xue/kicad/modules/M12-HLD-001 -[general] -version=1 +LibName40=../modules/M12-HLD-001 diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 6410c34..dcf1c7a 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT +EESchema Schematic File Version 2 date Fri 12 Nov 2010 06:20:49 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -50,14 +50,13 @@ LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:ft2232c -LIBS:fxo-hc536r LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 1 12 Title "" -Date "7 nov 2010" +Date "12 nov 2010" Rev "" Comp "" Comment1 ""