From 5c25d1c0152747bc0790a3b5bdb0f100e4162a97 Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Mon, 16 Aug 2010 23:30:34 -0500 Subject: [PATCH] DDR0 termaintor placement --- kicad/xue-rnc/DRAM.sch | 2 +- kicad/xue-rnc/FPGA.sch | 576 +++++--- kicad/xue-rnc/NV_MEMORIES.sch | 2 +- kicad/xue-rnc/PSU.sch | 2 +- kicad/xue-rnc/USB.sch | 2 +- kicad/xue-rnc/eth_phy.sch | 2 +- kicad/xue-rnc/xue-rnc-cache.lib | 2 +- kicad/xue-rnc/xue-rnc.brd | 2319 ++++++++++++++++++------------- kicad/xue-rnc/xue-rnc.net | 1840 ++++++++++++------------ kicad/xue-rnc/xue-rnc.pro | 2 +- kicad/xue-rnc/xue-rnc.sch | 2 +- 11 files changed, 2738 insertions(+), 2013 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 4335db3..d3c1c56 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 11:27:48 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 70546b8..fac9461 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 11:27:48 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,6 +58,106 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Wire Line + 10200 5200 10700 5200 +Wire Wire Line + 10700 5000 10200 5000 +Wire Wire Line + 10700 4500 10200 4500 +Wire Wire Line + 10700 4300 10200 4300 +Wire Wire Line + 10700 4100 10200 4100 +Wire Wire Line + 10700 3700 10200 3700 +Wire Wire Line + 10700 3500 10200 3500 +Wire Wire Line + 10700 3100 10200 3100 +Wire Wire Line + 3300 3250 3750 3250 +Wire Wire Line + 2800 2050 2900 2050 +Wire Wire Line + 2800 1950 2900 1950 +Wire Wire Line + 3300 1550 3800 1550 +Wire Wire Line + 3800 1850 3300 1850 +Wire Wire Line + 3750 1350 3300 1350 +Wire Wire Line + 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H 4750 900 40 0000 C CNN +F 2 "R_PACK4-0402" H 4750 950 60 0001 C CNN + 1 4750 950 -1 0 0 1 $EndComp Entry Wire Line @@ -2348,12 +2564,6 @@ Text Label 15100 1850 2 60 ~ 0 R_M1_BA1 Text HLabel 13650 1750 0 60 Output ~ 0 M1_BA[0..1] -Entry Wire Line - 10600 4400 10700 4300 -Entry Wire Line - 10600 4300 10700 4200 -Text HLabel 10850 4200 2 60 Output ~ 0 -M0_BA[0..1] Text HLabel 15750 3950 0 60 Output ~ 0 M1_CS# $Comp @@ -2614,89 +2824,89 @@ R_M0_DQ15 Text Label 5400 3600 0 60 ~ 0 R_M0_DQ14 Text Label 10250 4600 0 60 ~ 0 -M0_A0 +R_M0_A0 Text Label 10250 5100 0 60 ~ 0 -M0_A6 +R_M0_A6 Text Label 10250 5200 0 60 ~ 0 -M0_A5 +R_M0_A5 Text Label 10250 4100 0 60 ~ 0 -M0_A2 +R_M0_A2 Text Label 10250 4300 0 60 ~ 0 -M0_BA1 +R_M0_BA1 Text Label 10250 4200 0 60 ~ 0 -M0_A7 +R_M0_A7 Text Label 10250 4400 0 60 ~ 0 -M0_BA0 +R_M0_BA0 Text Label 10250 4500 0 60 ~ 0 -M0_A1 +R_M0_A1 Text Label 10250 3300 0 60 ~ 0 -M0_A12 +R_M0_A12 Text Label 10250 3100 0 60 ~ 0 -M0_A11 +R_M0_A11 Text Label 10250 3500 0 60 ~ 0 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0 60 ~ 0 +Text Label 1350 2350 0 60 ~ 0 M0_A3 -Text Label 1650 2050 0 60 ~ 0 +Text Label 1350 2050 0 60 ~ 0 M0_A6 -Text Label 1650 2150 0 60 ~ 0 +Text Label 1350 2150 0 60 ~ 0 M0_A5 Entry Wire Line - 1450 2550 1550 2650 + 1150 2550 1250 2650 Entry Wire Line - 1450 2450 1550 2550 + 1150 2450 1250 2550 Entry Wire Line - 1450 2350 1550 2450 + 1150 2350 1250 2450 Entry Wire Line - 1450 2250 1550 2350 + 1150 2250 1250 2350 Entry Wire Line - 1450 2150 1550 2250 + 1150 2150 1250 2250 Entry Wire Line - 1450 2050 1550 2150 + 1150 2050 1250 2150 Entry Wire Line - 1450 1950 1550 2050 + 1150 1950 1250 2050 Entry Wire Line - 1450 1850 1550 1950 + 1150 1850 1250 1950 Entry Wire Line - 1450 1750 1550 1850 + 1150 1750 1250 1850 Entry Wire Line - 1450 1650 1550 1750 + 1150 1650 1250 1750 Entry Wire Line - 1450 1550 1550 1650 + 1150 1550 1250 1650 Entry Wire Line - 1450 1450 1550 1550 + 1150 1450 1250 1550 Entry Wire Line - 1450 1350 1550 1450 + 1150 1350 1250 1450 Entry Wire Line 12450 850 12550 950 Entry Wire Line diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 9582c01..8534d3d 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 11:27:48 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index 553ca10..53c01dd 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 11:27:48 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index ba7bcc0..5e28f61 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 11:27:48 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 5f7ac1d..194e44a 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 11:27:48 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 1702d98..edfaf8c 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Mon 16 Aug 2010 10:43:45 PM COT +EESchema-LIBRARY Version 2.3 Date: Mon 16 Aug 2010 11:27:48 PM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index a86968f..ccc3781 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Mon 16 Aug 2010 10:47:34 PM COT +PCBNEW-BOARD Version 1 date Mon 16 Aug 2010 11:30:16 PM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -6,15 +6,15 @@ $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 1FFF801F -Links 611 -NoConn 611 +Links 631 +NoConn 631 Di 45200 13510 70149 50668 Ndraw 7 Ntrack 0 Nzone 0 BoardThickness 630 -Nmodule 133 -Nnets 223 +Nmodule 138 +Nnets 238 $EndGENERAL $SHEETDESCR @@ -90,347 +90,347 @@ Na 5 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A0" +Na 6 "/DDR_Banks/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_A10" +Na 7 "/DDR_Banks/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_BA1" +Na 8 "/DDR_Banks/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_CKE" +Na 9 "/DDR_Banks/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_CLK" +Na 10 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_CLK#" +Na 11 "/DDR_Banks/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_DQ0" +Na 12 "/DDR_Banks/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_DQ1" +Na 13 "/DDR_Banks/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_DQ10" +Na 14 "/DDR_Banks/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_DQ12" +Na 15 "/DDR_Banks/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_DQ14" +Na 16 "/DDR_Banks/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_DQ2" +Na 17 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_DQ4" +Na 18 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_DQ6" +Na 19 "/DDR_Banks/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M0_DQ8" +Na 20 "/DDR_Banks/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M0_DQ9" +Na 21 "/DDR_Banks/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M0_UDQS" +Na 22 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M0_WE#" +Na 23 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_A0" +Na 24 "/DDR_Banks/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_A1" +Na 25 "/DDR_Banks/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_A5" +Na 26 "/DDR_Banks/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_A7" +Na 27 "/DDR_Banks/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_A8" +Na 28 "/DDR_Banks/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_BA0" +Na 29 "/DDR_Banks/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_BA1" +Na 30 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_CAS#" +Na 31 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_CKE" +Na 32 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_CLK#" +Na 33 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_CS#" +Na 34 "/DDR_Banks/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_DQ10" +Na 35 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/DDR_Banks/M1_DQ11" +Na 36 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/DDR_Banks/M1_DQ7" +Na 37 "/Ethernet_Phy/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M1_DQ9" +Na 38 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/DDR_Banks/M1_LDM" +Na 39 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/DDR_Banks/M1_LDQS" +Na 40 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/DDR_Banks/M1_UDM" +Na 41 "/Ethernet_Phy/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/DDR_Banks/M1_UDQS" +Na 42 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_A1.8V" +Na 43 "/Ethernet_Phy/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_A3.3V" +Na 44 "/Ethernet_Phy/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_COL" +Na 45 "/Ethernet_Phy/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_LED0" +Na 46 "/FPGA_Spartan6/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_LED1" +Na 47 "/FPGA_Spartan6/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_PLL1.8V" +Na 48 "/FPGA_Spartan6/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_RXC" +Na 49 "/FPGA_Spartan6/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/ETH_RXD0" +Na 50 "/FPGA_Spartan6/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Ethernet_Phy/ETH_RXD1" +Na 51 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/Ethernet_Phy/ETH_RXD2" +Na 52 "/FPGA_Spartan6/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/Ethernet_Phy/ETH_RXD3" +Na 53 "/FPGA_Spartan6/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/Ethernet_Phy/ETH_RXER" +Na 54 "/FPGA_Spartan6/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/Ethernet_Phy/ETH_TXD3" +Na 55 "/FPGA_Spartan6/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/Ethernet_Phy/ETH_TXER" +Na 56 "/FPGA_Spartan6/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/ETH_CLK" +Na 57 "/FPGA_Spartan6/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/ETH_CRS" +Na 58 "/FPGA_Spartan6/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/ETH_INT" +Na 59 "/FPGA_Spartan6/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/ETH_MDC" +Na 60 "/FPGA_Spartan6/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/ETH_MDIO" +Na 61 "/FPGA_Spartan6/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/ETH_RESET_N" +Na 62 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/ETH_RXDV" +Na 63 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/ETH_TXC" +Na 64 "/FPGA_Spartan6/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/ETH_TXD0" +Na 65 "/FPGA_Spartan6/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/ETH_TXD1" +Na 66 "/FPGA_Spartan6/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/ETH_TXD2" +Na 67 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/ETH_TXEN" +Na 68 "/FPGA_Spartan6/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_A1" +Na 69 "/FPGA_Spartan6/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_A11" +Na 70 "/FPGA_Spartan6/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_A12" +Na 71 "/FPGA_Spartan6/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_A2" +Na 72 "/FPGA_Spartan6/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_A3" +Na 73 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_A4" +Na 74 "/FPGA_Spartan6/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_A5" +Na 75 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_A6" +Na 76 "/FPGA_Spartan6/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_A7" +Na 77 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_A8" +Na 78 "/FPGA_Spartan6/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_A9" +Na 79 "/FPGA_Spartan6/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_BA0" +Na 80 "/FPGA_Spartan6/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_CAS#" +Na 81 "/FPGA_Spartan6/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_DQ11" +Na 82 "/FPGA_Spartan6/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_DQ13" +Na 83 "/FPGA_Spartan6/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_DQ15" +Na 84 "/FPGA_Spartan6/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M0_DQ3" +Na 85 "/FPGA_Spartan6/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M0_DQ5" +Na 86 "/FPGA_Spartan6/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M0_DQ7" +Na 87 "/FPGA_Spartan6/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M0_LDM" +Na 88 "/FPGA_Spartan6/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M0_LDQS" +Na 89 "/FPGA_Spartan6/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M0_RAS#" +Na 90 "/FPGA_Spartan6/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M0_UDM" +Na 91 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT @@ -442,59 +442,59 @@ Na 93 "/FPGA_Spartan6/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_A12" +Na 94 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_A2" +Na 95 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_A3" +Na 96 "/FPGA_Spartan6/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_A4" +Na 97 "/FPGA_Spartan6/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_A6" +Na 98 "/FPGA_Spartan6/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_A9" +Na 99 "/FPGA_Spartan6/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_CLK" +Na 100 "/FPGA_Spartan6/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_DQ0" +Na 101 "/FPGA_Spartan6/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_DQ1" +Na 102 "/FPGA_Spartan6/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_DQ12" +Na 103 "/FPGA_Spartan6/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_DQ13" +Na 104 "/FPGA_Spartan6/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ14" +Na 105 "/FPGA_Spartan6/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_DQ15" +Na 106 "/FPGA_Spartan6/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_DQ2" +Na 107 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT @@ -506,11 +506,11 @@ Na 109 "/FPGA_Spartan6/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_DQ5" +Na 110 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_DQ6" +Na 111 "/FPGA_Spartan6/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT @@ -518,7 +518,7 @@ Na 112 "/FPGA_Spartan6/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_RAS#" +Na 113 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT @@ -526,435 +526,495 @@ Na 114 "/FPGA_Spartan6/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/NF_CLE" +Na 115 "/FPGA_Spartan6/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/NF_CS1_N" +Na 116 "/FPGA_Spartan6/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Spartan6/NF_D1" +Na 117 "/FPGA_Spartan6/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA_Spartan6/NF_D2" +Na 118 "/FPGA_Spartan6/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/NF_D5" +Na 119 "/FPGA_Spartan6/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Spartan6/NF_D7" +Na 120 "/FPGA_Spartan6/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Spartan6/NF_RE_N" +Na 121 "/FPGA_Spartan6/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Spartan6/NF_RNB" +Na 122 "/FPGA_Spartan6/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Spartan6/NF_WE_N" +Na 123 "/FPGA_Spartan6/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Spartan6/PROG_CCLK" +Na 124 "/FPGA_Spartan6/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Spartan6/PROG_CSO" +Na 125 "/FPGA_Spartan6/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Spartan6/PROG_MISO0" +Na 126 "/FPGA_Spartan6/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Spartan6/PROG_MISO1" +Na 127 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Spartan6/PROG_MISO2" +Na 128 "/FPGA_Spartan6/R_M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/FPGA_Spartan6/PROG_MISO3" +Na 129 "/FPGA_Spartan6/R_M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/FPGA_Spartan6/R_M0_DQ0" +Na 130 "/FPGA_Spartan6/R_M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/FPGA_Spartan6/R_M0_DQ1" +Na 131 "/FPGA_Spartan6/R_M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/FPGA_Spartan6/R_M0_DQ10" +Na 132 "/FPGA_Spartan6/R_M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/FPGA_Spartan6/R_M0_DQ11" +Na 133 "/FPGA_Spartan6/R_M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/FPGA_Spartan6/R_M0_DQ12" +Na 134 "/FPGA_Spartan6/R_M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/FPGA_Spartan6/R_M0_DQ13" +Na 135 "/FPGA_Spartan6/R_M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/FPGA_Spartan6/R_M0_DQ14" +Na 136 "/FPGA_Spartan6/R_M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/FPGA_Spartan6/R_M0_DQ15" +Na 137 "/FPGA_Spartan6/R_M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/FPGA_Spartan6/R_M0_DQ2" +Na 138 "/FPGA_Spartan6/R_M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/FPGA_Spartan6/R_M0_DQ3" +Na 139 "/FPGA_Spartan6/R_M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/FPGA_Spartan6/R_M0_DQ4" +Na 140 "/FPGA_Spartan6/R_M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/FPGA_Spartan6/R_M0_DQ5" +Na 141 "/FPGA_Spartan6/R_M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/FPGA_Spartan6/R_M0_DQ6" +Na 142 "/FPGA_Spartan6/R_M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/FPGA_Spartan6/R_M0_DQ7" +Na 143 "/FPGA_Spartan6/R_M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/FPGA_Spartan6/R_M0_DQ8" +Na 144 "/FPGA_Spartan6/R_M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/FPGA_Spartan6/R_M0_DQ9" +Na 145 "/FPGA_Spartan6/R_M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/FPGA_Spartan6/R_M1_A0" +Na 146 "/FPGA_Spartan6/R_M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/FPGA_Spartan6/R_M1_A1" +Na 147 "/FPGA_Spartan6/R_M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/FPGA_Spartan6/R_M1_A10" +Na 148 "/FPGA_Spartan6/R_M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/FPGA_Spartan6/R_M1_A11" +Na 149 "/FPGA_Spartan6/R_M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/FPGA_Spartan6/R_M1_A12" +Na 150 "/FPGA_Spartan6/R_M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/FPGA_Spartan6/R_M1_A2" +Na 151 "/FPGA_Spartan6/R_M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/FPGA_Spartan6/R_M1_A3" +Na 152 "/FPGA_Spartan6/R_M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/FPGA_Spartan6/R_M1_A5" +Na 153 "/FPGA_Spartan6/R_M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/FPGA_Spartan6/R_M1_A6" +Na 154 "/FPGA_Spartan6/R_M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/FPGA_Spartan6/R_M1_A7" +Na 155 "/FPGA_Spartan6/R_M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/FPGA_Spartan6/R_M1_A8" +Na 156 "/FPGA_Spartan6/R_M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/FPGA_Spartan6/R_M1_A9" +Na 157 "/FPGA_Spartan6/R_M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/FPGA_Spartan6/R_M1_BA0" +Na 158 "/FPGA_Spartan6/R_M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/FPGA_Spartan6/R_M1_BA1" +Na 159 "/FPGA_Spartan6/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/FPGA_Spartan6/R_M1_CAS#" +Na 160 "/FPGA_Spartan6/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/FPGA_Spartan6/R_M1_CKE" +Na 161 "/FPGA_Spartan6/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/FPGA_Spartan6/R_M1_CS#" +Na 162 "/FPGA_Spartan6/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/FPGA_Spartan6/R_M1_DQ0" +Na 163 "/FPGA_Spartan6/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/FPGA_Spartan6/R_M1_DQ1" +Na 164 "/FPGA_Spartan6/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/FPGA_Spartan6/R_M1_DQ10" +Na 165 "/FPGA_Spartan6/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/FPGA_Spartan6/R_M1_DQ11" +Na 166 "/FPGA_Spartan6/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/FPGA_Spartan6/R_M1_DQ12" +Na 167 "/FPGA_Spartan6/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/FPGA_Spartan6/R_M1_DQ13" +Na 168 "/FPGA_Spartan6/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/FPGA_Spartan6/R_M1_DQ14" +Na 169 "/FPGA_Spartan6/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/FPGA_Spartan6/R_M1_DQ15" +Na 170 "/FPGA_Spartan6/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/FPGA_Spartan6/R_M1_DQ2" +Na 171 "/FPGA_Spartan6/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/FPGA_Spartan6/R_M1_DQ3" +Na 172 "/FPGA_Spartan6/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/FPGA_Spartan6/R_M1_DQ4" +Na 173 "/FPGA_Spartan6/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/FPGA_Spartan6/R_M1_DQ5" +Na 174 "/FPGA_Spartan6/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/FPGA_Spartan6/R_M1_DQ6" +Na 175 "/FPGA_Spartan6/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/FPGA_Spartan6/R_M1_DQ7" +Na 176 "/FPGA_Spartan6/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/FPGA_Spartan6/R_M1_DQ8" +Na 177 "/FPGA_Spartan6/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/FPGA_Spartan6/R_M1_DQ9" +Na 178 "/FPGA_Spartan6/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/FPGA_Spartan6/R_M1_LDM" +Na 179 "/FPGA_Spartan6/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 180 "/FPGA_Spartan6/R_M1_LDQS" +Na 180 "/FPGA_Spartan6/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/FPGA_Spartan6/R_M1_RAS#" +Na 181 "/FPGA_Spartan6/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/FPGA_Spartan6/R_M1_UDM" +Na 182 "/FPGA_Spartan6/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/FPGA_Spartan6/R_M1_UDQS" +Na 183 "/FPGA_Spartan6/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/FPGA_Spartan6/R_M1_WE#" +Na 184 "/FPGA_Spartan6/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "/FPGA_Spartan6/SD_DAT3" +Na 185 "/FPGA_Spartan6/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "/FPGA_Spartan6/USBA_VP" +Na 186 "/FPGA_Spartan6/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "/Non_volatile_memories/NF_ALE" +Na 187 "/FPGA_Spartan6/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "/Non_volatile_memories/NF_D0" +Na 188 "/FPGA_Spartan6/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "/Non_volatile_memories/NF_D3" +Na 189 "/FPGA_Spartan6/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "/Non_volatile_memories/NF_D4" +Na 190 "/FPGA_Spartan6/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "/Non_volatile_memories/NF_D6" +Na 191 "/FPGA_Spartan6/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "/Non_volatile_memories/SD_CLK" +Na 192 "/FPGA_Spartan6/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "/Non_volatile_memories/SD_CMD" +Na 193 "/FPGA_Spartan6/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "/Non_volatile_memories/SD_DAT0" +Na 194 "/FPGA_Spartan6/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "/Non_volatile_memories/SD_DAT1" +Na 195 "/FPGA_Spartan6/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "/Non_volatile_memories/SD_DAT2" +Na 196 "/FPGA_Spartan6/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "/USB/USBA_OE_N" +Na 197 "/FPGA_Spartan6/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "/USB/USBA_RCV" +Na 198 "/FPGA_Spartan6/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "/USB/USBA_SPD" +Na 199 "/FPGA_Spartan6/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "/USB/USBA_VM" +Na 200 "/FPGA_Spartan6/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 201 "GND" +Na 201 "/FPGA_Spartan6/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 202 "N-000058" +Na 202 "/FPGA_Spartan6/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 203 "N-000059" +Na 203 "/Non_volatile_memories/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 204 "N-000374" +Na 204 "/Non_volatile_memories/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 205 "N-000377" +Na 205 "/Non_volatile_memories/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 206 "N-000386" +Na 206 "/Non_volatile_memories/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 207 "N-000387" +Na 207 "/Non_volatile_memories/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 208 "N-000388" +Na 208 "/Non_volatile_memories/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 209 "N-000389" +Na 209 "/Non_volatile_memories/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 210 "N-000390" +Na 210 "/Non_volatile_memories/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 211 "N-000392" +Na 211 "/Non_volatile_memories/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 212 "N-000399" +Na 212 "/Non_volatile_memories/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 213 "N-000400" +Na 213 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 214 "N-000401" +Na 214 "/USB/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 215 "N-000402" +Na 215 "/USB/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 216 "N-000405" +Na 216 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 217 "N-000406" +Na 217 "N-000058" St ~ $EndEQUIPOT $EQUIPOT -Na 218 "N-000407" +Na 218 "N-000059" St ~ $EndEQUIPOT $EQUIPOT -Na 219 "N-000408" +Na 219 "N-000394" St ~ $EndEQUIPOT $EQUIPOT -Na 220 "N-000409" +Na 220 "N-000397" St ~ $EndEQUIPOT $EQUIPOT -Na 221 "N-000410" +Na 221 "N-000406" St ~ $EndEQUIPOT $EQUIPOT -Na 222 "VCCO2" +Na 222 "N-000407" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 223 "N-000408" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 224 "N-000409" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 225 "N-000410" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 226 "N-000412" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 227 "N-000419" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 228 "N-000420" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 229 "N-000421" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 230 "N-000422" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 231 "N-000425" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 232 "N-000426" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 233 "N-000427" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 234 "N-000428" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 235 "N-000429" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 236 "N-000430" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 237 "VCCO2" St ~ $EndEQUIPOT $NCLASS @@ -972,121 +1032,119 @@ AddNet "+1.8V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" -AddNet "/DDR_Banks/M0_A0" -AddNet "/DDR_Banks/M0_A10" -AddNet "/DDR_Banks/M0_BA1" -AddNet "/DDR_Banks/M0_CKE" -AddNet "/DDR_Banks/M0_CLK" -AddNet "/DDR_Banks/M0_CLK#" +AddNet "/DDR_Banks/M0_A11" +AddNet "/DDR_Banks/M0_A12" +AddNet "/DDR_Banks/M0_A3" +AddNet "/DDR_Banks/M0_A4" +AddNet "/DDR_Banks/M0_A7" +AddNet "/DDR_Banks/M0_BA0" +AddNet "/DDR_Banks/M0_CAS#" AddNet "/DDR_Banks/M0_DQ0" -AddNet "/DDR_Banks/M0_DQ1" -AddNet "/DDR_Banks/M0_DQ10" AddNet "/DDR_Banks/M0_DQ12" -AddNet "/DDR_Banks/M0_DQ14" -AddNet "/DDR_Banks/M0_DQ2" -AddNet "/DDR_Banks/M0_DQ4" -AddNet "/DDR_Banks/M0_DQ6" -AddNet "/DDR_Banks/M0_DQ8" -AddNet "/DDR_Banks/M0_DQ9" -AddNet "/DDR_Banks/M0_UDQS" -AddNet "/DDR_Banks/M0_WE#" +AddNet "/DDR_Banks/M0_DQ13" +AddNet "/DDR_Banks/M0_DQ7" AddNet "/DDR_Banks/M1_A0" -AddNet "/DDR_Banks/M1_A1" -AddNet "/DDR_Banks/M1_A5" -AddNet "/DDR_Banks/M1_A7" -AddNet "/DDR_Banks/M1_A8" +AddNet "/DDR_Banks/M1_A12" +AddNet "/DDR_Banks/M1_A4" AddNet "/DDR_Banks/M1_BA0" -AddNet "/DDR_Banks/M1_BA1" AddNet "/DDR_Banks/M1_CAS#" -AddNet "/DDR_Banks/M1_CKE" +AddNet "/DDR_Banks/M1_CLK" AddNet "/DDR_Banks/M1_CLK#" -AddNet "/DDR_Banks/M1_CS#" -AddNet "/DDR_Banks/M1_DQ10" -AddNet "/DDR_Banks/M1_DQ11" -AddNet "/DDR_Banks/M1_DQ7" -AddNet "/DDR_Banks/M1_DQ9" +AddNet "/DDR_Banks/M1_DQ0" +AddNet "/DDR_Banks/M1_DQ1" +AddNet "/DDR_Banks/M1_DQ14" +AddNet "/DDR_Banks/M1_DQ15" +AddNet "/DDR_Banks/M1_DQ2" +AddNet "/DDR_Banks/M1_DQ5" AddNet "/DDR_Banks/M1_LDM" AddNet "/DDR_Banks/M1_LDQS" +AddNet "/DDR_Banks/M1_RAS#" AddNet "/DDR_Banks/M1_UDM" AddNet "/DDR_Banks/M1_UDQS" AddNet "/Ethernet_Phy/ETH_A1.8V" AddNet "/Ethernet_Phy/ETH_A3.3V" -AddNet "/Ethernet_Phy/ETH_COL" +AddNet "/Ethernet_Phy/ETH_CLK" AddNet "/Ethernet_Phy/ETH_LED0" AddNet "/Ethernet_Phy/ETH_LED1" AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/ETH_RXC" AddNet "/Ethernet_Phy/ETH_RXD0" AddNet "/Ethernet_Phy/ETH_RXD1" -AddNet "/Ethernet_Phy/ETH_RXD2" -AddNet "/Ethernet_Phy/ETH_RXD3" -AddNet "/Ethernet_Phy/ETH_RXER" +AddNet "/Ethernet_Phy/ETH_TXC" AddNet "/Ethernet_Phy/ETH_TXD3" -AddNet "/Ethernet_Phy/ETH_TXER" -AddNet "/FPGA_Spartan6/ETH_CLK" +AddNet "/Ethernet_Phy/ETH_TXEN" +AddNet "/FPGA_Spartan6/ETH_COL" AddNet "/FPGA_Spartan6/ETH_CRS" AddNet "/FPGA_Spartan6/ETH_INT" AddNet "/FPGA_Spartan6/ETH_MDC" AddNet "/FPGA_Spartan6/ETH_MDIO" AddNet "/FPGA_Spartan6/ETH_RESET_N" +AddNet "/FPGA_Spartan6/ETH_RXC" +AddNet "/FPGA_Spartan6/ETH_RXD2" +AddNet "/FPGA_Spartan6/ETH_RXD3" AddNet "/FPGA_Spartan6/ETH_RXDV" -AddNet "/FPGA_Spartan6/ETH_TXC" +AddNet "/FPGA_Spartan6/ETH_RXER" AddNet "/FPGA_Spartan6/ETH_TXD0" AddNet "/FPGA_Spartan6/ETH_TXD1" AddNet "/FPGA_Spartan6/ETH_TXD2" -AddNet "/FPGA_Spartan6/ETH_TXEN" +AddNet "/FPGA_Spartan6/ETH_TXER" +AddNet "/FPGA_Spartan6/M0_A0" AddNet "/FPGA_Spartan6/M0_A1" -AddNet "/FPGA_Spartan6/M0_A11" -AddNet "/FPGA_Spartan6/M0_A12" +AddNet "/FPGA_Spartan6/M0_A10" AddNet "/FPGA_Spartan6/M0_A2" -AddNet "/FPGA_Spartan6/M0_A3" -AddNet "/FPGA_Spartan6/M0_A4" AddNet "/FPGA_Spartan6/M0_A5" AddNet "/FPGA_Spartan6/M0_A6" -AddNet "/FPGA_Spartan6/M0_A7" AddNet "/FPGA_Spartan6/M0_A8" AddNet "/FPGA_Spartan6/M0_A9" -AddNet "/FPGA_Spartan6/M0_BA0" -AddNet "/FPGA_Spartan6/M0_CAS#" +AddNet "/FPGA_Spartan6/M0_BA1" +AddNet "/FPGA_Spartan6/M0_CKE" +AddNet "/FPGA_Spartan6/M0_CLK" +AddNet "/FPGA_Spartan6/M0_CLK#" +AddNet "/FPGA_Spartan6/M0_DQ1" +AddNet "/FPGA_Spartan6/M0_DQ10" AddNet "/FPGA_Spartan6/M0_DQ11" -AddNet "/FPGA_Spartan6/M0_DQ13" +AddNet "/FPGA_Spartan6/M0_DQ14" AddNet "/FPGA_Spartan6/M0_DQ15" +AddNet "/FPGA_Spartan6/M0_DQ2" AddNet "/FPGA_Spartan6/M0_DQ3" +AddNet "/FPGA_Spartan6/M0_DQ4" AddNet "/FPGA_Spartan6/M0_DQ5" -AddNet "/FPGA_Spartan6/M0_DQ7" +AddNet "/FPGA_Spartan6/M0_DQ6" +AddNet "/FPGA_Spartan6/M0_DQ8" +AddNet "/FPGA_Spartan6/M0_DQ9" AddNet "/FPGA_Spartan6/M0_LDM" AddNet "/FPGA_Spartan6/M0_LDQS" AddNet "/FPGA_Spartan6/M0_RAS#" AddNet "/FPGA_Spartan6/M0_UDM" +AddNet "/FPGA_Spartan6/M0_UDQS" +AddNet "/FPGA_Spartan6/M0_WE#" +AddNet "/FPGA_Spartan6/M1_A1" AddNet "/FPGA_Spartan6/M1_A10" AddNet "/FPGA_Spartan6/M1_A11" -AddNet "/FPGA_Spartan6/M1_A12" AddNet "/FPGA_Spartan6/M1_A2" AddNet "/FPGA_Spartan6/M1_A3" -AddNet "/FPGA_Spartan6/M1_A4" +AddNet "/FPGA_Spartan6/M1_A5" AddNet "/FPGA_Spartan6/M1_A6" +AddNet "/FPGA_Spartan6/M1_A7" +AddNet "/FPGA_Spartan6/M1_A8" AddNet "/FPGA_Spartan6/M1_A9" -AddNet "/FPGA_Spartan6/M1_CLK" -AddNet "/FPGA_Spartan6/M1_DQ0" -AddNet "/FPGA_Spartan6/M1_DQ1" +AddNet "/FPGA_Spartan6/M1_BA1" +AddNet "/FPGA_Spartan6/M1_CKE" +AddNet "/FPGA_Spartan6/M1_CS#" +AddNet "/FPGA_Spartan6/M1_DQ10" +AddNet "/FPGA_Spartan6/M1_DQ11" AddNet "/FPGA_Spartan6/M1_DQ12" AddNet "/FPGA_Spartan6/M1_DQ13" -AddNet "/FPGA_Spartan6/M1_DQ14" -AddNet "/FPGA_Spartan6/M1_DQ15" -AddNet "/FPGA_Spartan6/M1_DQ2" AddNet "/FPGA_Spartan6/M1_DQ3" AddNet "/FPGA_Spartan6/M1_DQ4" -AddNet "/FPGA_Spartan6/M1_DQ5" AddNet "/FPGA_Spartan6/M1_DQ6" +AddNet "/FPGA_Spartan6/M1_DQ7" AddNet "/FPGA_Spartan6/M1_DQ8" -AddNet "/FPGA_Spartan6/M1_RAS#" +AddNet "/FPGA_Spartan6/M1_DQ9" AddNet "/FPGA_Spartan6/M1_WE#" -AddNet "/FPGA_Spartan6/NF_CLE" -AddNet "/FPGA_Spartan6/NF_CS1_N" -AddNet "/FPGA_Spartan6/NF_D1" -AddNet "/FPGA_Spartan6/NF_D2" -AddNet "/FPGA_Spartan6/NF_D5" -AddNet "/FPGA_Spartan6/NF_D7" +AddNet "/FPGA_Spartan6/NF_ALE" +AddNet "/FPGA_Spartan6/NF_D0" +AddNet "/FPGA_Spartan6/NF_D4" +AddNet "/FPGA_Spartan6/NF_D6" AddNet "/FPGA_Spartan6/NF_RE_N" AddNet "/FPGA_Spartan6/NF_RNB" AddNet "/FPGA_Spartan6/NF_WE_N" @@ -1096,6 +1154,21 @@ AddNet "/FPGA_Spartan6/PROG_MISO0" AddNet "/FPGA_Spartan6/PROG_MISO1" AddNet "/FPGA_Spartan6/PROG_MISO2" AddNet "/FPGA_Spartan6/PROG_MISO3" +AddNet "/FPGA_Spartan6/R_M0_A0" +AddNet "/FPGA_Spartan6/R_M0_A1" +AddNet "/FPGA_Spartan6/R_M0_A10" +AddNet "/FPGA_Spartan6/R_M0_A11" +AddNet "/FPGA_Spartan6/R_M0_A12" +AddNet "/FPGA_Spartan6/R_M0_A2" +AddNet "/FPGA_Spartan6/R_M0_A3" +AddNet "/FPGA_Spartan6/R_M0_A4" +AddNet "/FPGA_Spartan6/R_M0_A5" +AddNet "/FPGA_Spartan6/R_M0_A6" +AddNet "/FPGA_Spartan6/R_M0_A7" +AddNet "/FPGA_Spartan6/R_M0_A8" +AddNet "/FPGA_Spartan6/R_M0_A9" +AddNet "/FPGA_Spartan6/R_M0_BA0" +AddNet "/FPGA_Spartan6/R_M0_BA1" AddNet "/FPGA_Spartan6/R_M0_DQ0" AddNet "/FPGA_Spartan6/R_M0_DQ1" AddNet "/FPGA_Spartan6/R_M0_DQ10" @@ -1151,43 +1224,45 @@ AddNet "/FPGA_Spartan6/R_M1_RAS#" AddNet "/FPGA_Spartan6/R_M1_UDM" AddNet "/FPGA_Spartan6/R_M1_UDQS" AddNet "/FPGA_Spartan6/R_M1_WE#" +AddNet "/FPGA_Spartan6/SD_DAT0" AddNet "/FPGA_Spartan6/SD_DAT3" +AddNet "/FPGA_Spartan6/USBA_OE_N" +AddNet "/FPGA_Spartan6/USBA_SPD" AddNet "/FPGA_Spartan6/USBA_VP" -AddNet "/Non_volatile_memories/NF_ALE" -AddNet "/Non_volatile_memories/NF_D0" +AddNet "/Non_volatile_memories/NF_CLE" +AddNet "/Non_volatile_memories/NF_CS1_N" +AddNet "/Non_volatile_memories/NF_D1" +AddNet "/Non_volatile_memories/NF_D2" AddNet "/Non_volatile_memories/NF_D3" -AddNet "/Non_volatile_memories/NF_D4" -AddNet "/Non_volatile_memories/NF_D6" +AddNet "/Non_volatile_memories/NF_D5" +AddNet "/Non_volatile_memories/NF_D7" AddNet "/Non_volatile_memories/SD_CLK" AddNet "/Non_volatile_memories/SD_CMD" -AddNet "/Non_volatile_memories/SD_DAT0" AddNet "/Non_volatile_memories/SD_DAT1" AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "/USB/USBA_OE_N" AddNet "/USB/USBA_RCV" -AddNet "/USB/USBA_SPD" AddNet "/USB/USBA_VM" AddNet "GND" AddNet "N-000058" AddNet "N-000059" -AddNet "N-000374" -AddNet "N-000377" -AddNet "N-000386" -AddNet "N-000387" -AddNet "N-000388" -AddNet "N-000389" -AddNet "N-000390" -AddNet "N-000392" -AddNet "N-000399" -AddNet "N-000400" -AddNet "N-000401" -AddNet "N-000402" -AddNet "N-000405" +AddNet "N-000394" +AddNet "N-000397" AddNet "N-000406" AddNet "N-000407" AddNet "N-000408" AddNet "N-000409" AddNet "N-000410" +AddNet "N-000412" +AddNet "N-000419" +AddNet "N-000420" +AddNet "N-000421" +AddNet "N-000422" +AddNet "N-000425" +AddNet "N-000426" +AddNet "N-000427" +AddNet "N-000428" +AddNet "N-000429" +AddNet "N-000430" AddNet "VCCO2" $EndNCLASS $MODULE 1206 @@ -1214,14 +1289,14 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 570 0 $EndPAD $EndMODULE 1206 $MODULE FGG484bga-p10 -Po 56269 34378 0 15 4C4325AE 4C431E53 ~~ +Po 56269 34378 0 15 4C4325AE 4C6A0A06 ~~ Li FGG484bga-p10 -Sc 4C431E53 +Sc 4C6A0A06 AR /4C431A63/4C431E53 Op 0 0 0 At SMD @@ -1239,7 +1314,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -4133 -4133 $EndPAD $PAD @@ -1260,70 +1335,70 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_CLK" +Ne 37 "/Ethernet_Phy/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_RESET_N" +Ne 51 "/FPGA_Spartan6/ETH_RESET_N" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_RXD0" +Ne 41 "/Ethernet_Phy/ETH_RXD0" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_RXER" +Ne 56 "/FPGA_Spartan6/ETH_RXER" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/ETH_TXEN" +Ne 45 "/Ethernet_Phy/ETH_TXEN" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/ETH_TXD3" +Ne 44 "/Ethernet_Phy/ETH_TXD3" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_INT" +Ne 48 "/FPGA_Spartan6/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/NF_D7" +Ne 209 "/Non_volatile_memories/NF_D7" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/Non_volatile_memories/NF_D3" +Ne 207 "/Non_volatile_memories/NF_D3" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_D1" +Ne 205 "/Non_volatile_memories/NF_D1" Po 590 -4133 $EndPAD $PAD @@ -1337,28 +1412,28 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/Non_volatile_memories/NF_ALE" +Ne 115 "/FPGA_Spartan6/NF_ALE" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_RNB" +Ne 120 "/FPGA_Spartan6/NF_RNB" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 196 "/Non_volatile_memories/SD_DAT2" +Ne 213 "/Non_volatile_memories/SD_DAT2" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 194 "/Non_volatile_memories/SD_DAT0" +Ne 198 "/FPGA_Spartan6/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -1386,7 +1461,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 4133 -4133 $EndPAD $PAD @@ -1421,14 +1496,14 @@ $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2558 -3739 $EndPAD $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXD1" +Ne 42 "/Ethernet_Phy/ETH_RXD1" Po -2165 -3739 $EndPAD $PAD @@ -1442,21 +1517,21 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/Ethernet_Phy/ETH_TXER" +Ne 60 "/FPGA_Spartan6/ETH_TXER" Po -1377 -3739 $EndPAD $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -983 -3739 $EndPAD $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_COL" +Ne 46 "/FPGA_Spartan6/ETH_COL" Po -590 -3739 $EndPAD $PAD @@ -1470,14 +1545,14 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/Non_volatile_memories/NF_D4" +Ne 117 "/FPGA_Spartan6/NF_D4" Po 196 -3739 $EndPAD $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 590 -3739 $EndPAD $PAD @@ -1498,21 +1573,21 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/NF_RE_N" +Ne 119 "/FPGA_Spartan6/NF_RE_N" Po 1771 -3739 $EndPAD $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 2165 -3739 $EndPAD $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 195 "/Non_volatile_memories/SD_DAT1" +Ne 212 "/Non_volatile_memories/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1547,7 +1622,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A11" +Ne 131 "/FPGA_Spartan6/R_M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1575,42 +1650,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_MDIO" +Ne 50 "/FPGA_Spartan6/ETH_MDIO" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_RXD2" +Ne 53 "/FPGA_Spartan6/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_RXDV" +Ne 55 "/FPGA_Spartan6/ETH_RXDV" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/ETH_TXD1" +Ne 58 "/FPGA_Spartan6/ETH_TXD1" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/ETH_TXD2" +Ne 59 "/FPGA_Spartan6/ETH_TXD2" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_CRS" +Ne 47 "/FPGA_Spartan6/ETH_CRS" Po -590 -3346 $EndPAD $PAD @@ -1624,14 +1699,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/NF_D5" +Ne 208 "/Non_volatile_memories/NF_D5" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/NF_D2" +Ne 206 "/Non_volatile_memories/NF_D2" Po 590 -3346 $EndPAD $PAD @@ -1645,21 +1720,21 @@ $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/NF_WE_N" +Ne 121 "/FPGA_Spartan6/NF_WE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_CS1_N" +Ne 204 "/Non_volatile_memories/NF_CS1_N" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "/FPGA_Spartan6/SD_DAT3" +Ne 199 "/FPGA_Spartan6/SD_DAT3" Po 2165 -3346 $EndPAD $PAD @@ -1680,7 +1755,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/FPGA_Spartan6/R_M1_A8" +Ne 169 "/FPGA_Spartan6/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1694,21 +1769,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_Spartan6/R_M1_A9" +Ne 170 "/FPGA_Spartan6/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A12" +Ne 132 "/FPGA_Spartan6/R_M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_CKE" +Ne 70 "/FPGA_Spartan6/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1722,7 +1797,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1736,42 +1811,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_RXD3" +Ne 54 "/FPGA_Spartan6/ETH_RXD3" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_TXC" +Ne 43 "/Ethernet_Phy/ETH_TXC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_RXC" +Ne 52 "/FPGA_Spartan6/ETH_RXC" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/ETH_TXD0" +Ne 57 "/FPGA_Spartan6/ETH_TXD0" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_MDC" +Ne 49 "/FPGA_Spartan6/ETH_MDC" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/Non_volatile_memories/NF_D6" +Ne 118 "/FPGA_Spartan6/NF_D6" Po -196 -2952 $EndPAD $PAD @@ -1792,14 +1867,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/Non_volatile_memories/NF_D0" +Ne 116 "/FPGA_Spartan6/NF_D0" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_CLE" +Ne 203 "/Non_volatile_memories/NF_CLE" Po 1377 -2952 $EndPAD $PAD @@ -1813,14 +1888,14 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 193 "/Non_volatile_memories/SD_CMD" +Ne 211 "/Non_volatile_memories/SD_CMD" Po 2165 -2952 $EndPAD $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 2558 -2952 $EndPAD $PAD @@ -1841,35 +1916,35 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_Spartan6/R_M1_CKE" +Ne 174 "/FPGA_Spartan6/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/FPGA_Spartan6/R_M1_A12" +Ne 163 "/FPGA_Spartan6/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_A9" +Ne 140 "/FPGA_Spartan6/R_M0_A9" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_A8" +Ne 139 "/FPGA_Spartan6/R_M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1897,7 +1972,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -1771 -2558 $EndPAD $PAD @@ -1925,7 +2000,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -196 -2558 $EndPAD $PAD @@ -1953,14 +2028,14 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 1377 -2558 $EndPAD $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 192 "/Non_volatile_memories/SD_CLK" +Ne 210 "/Non_volatile_memories/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -1988,21 +2063,21 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/FPGA_Spartan6/R_M1_A7" +Ne 168 "/FPGA_Spartan6/R_M1_A7" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/FPGA_Spartan6/R_M1_A2" +Ne 164 "/FPGA_Spartan6/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -2016,14 +2091,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M0_WE#" +Ne 90 "/FPGA_Spartan6/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_A4" +Ne 135 "/FPGA_Spartan6/R_M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -2135,7 +2210,7 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_Spartan6/R_M1_A11" +Ne 162 "/FPGA_Spartan6/R_M1_A11" Po 2952 -2165 $EndPAD $PAD @@ -2149,21 +2224,21 @@ $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA_Spartan6/R_M1_A0" +Ne 159 "/FPGA_Spartan6/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA_Spartan6/R_M1_A1" +Ne 160 "/FPGA_Spartan6/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_BA1" +Ne 142 "/FPGA_Spartan6/R_M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -2177,21 +2252,21 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_BA0" +Ne 141 "/FPGA_Spartan6/R_M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A10" +Ne 130 "/FPGA_Spartan6/R_M0_A10" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2558 -1771 $EndPAD $PAD @@ -2282,21 +2357,21 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA_Spartan6/R_M1_A10" +Ne 161 "/FPGA_Spartan6/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/FPGA_Spartan6/R_M1_A3" +Ne 165 "/FPGA_Spartan6/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2317,49 +2392,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A1" +Ne 129 "/FPGA_Spartan6/R_M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A0" +Ne 128 "/FPGA_Spartan6/R_M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_CLK#" +Ne 72 "/FPGA_Spartan6/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_CLK" +Ne 71 "/FPGA_Spartan6/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_A2" +Ne 133 "/FPGA_Spartan6/R_M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_A7" +Ne 138 "/FPGA_Spartan6/R_M0_A7" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -1771 -1377 $EndPAD $PAD @@ -2422,7 +2497,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_Spartan6/R_M1_CS#" +Ne 175 "/FPGA_Spartan6/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -2443,56 +2518,56 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/FPGA_Spartan6/R_M1_WE#" +Ne 197 "/FPGA_Spartan6/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_CLK" +Ne 22 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/FPGA_Spartan6/R_M1_RAS#" +Ne 194 "/FPGA_Spartan6/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/FPGA_Spartan6/R_M1_CAS#" +Ne 173 "/FPGA_Spartan6/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/FPGA_Spartan6/R_M0_DQ5" +Ne 154 "/FPGA_Spartan6/R_M0_DQ5" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/FPGA_Spartan6/R_M0_DQ4" +Ne 153 "/FPGA_Spartan6/R_M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_A6" +Ne 137 "/FPGA_Spartan6/R_M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2527,7 +2602,7 @@ $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -983 -983 $EndPAD $PAD @@ -2541,7 +2616,7 @@ $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -196 -983 $EndPAD $PAD @@ -2555,7 +2630,7 @@ $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 590 -983 $EndPAD $PAD @@ -2569,7 +2644,7 @@ $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 1377 -983 $EndPAD $PAD @@ -2583,7 +2658,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_Spartan6/R_M1_BA0" +Ne 171 "/FPGA_Spartan6/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2597,70 +2672,70 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_CLK#" +Ne 23 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/FPGA_Spartan6/R_M1_DQ4" +Ne 186 "/FPGA_Spartan6/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/FPGA_Spartan6/R_M1_DQ5" +Ne 187 "/FPGA_Spartan6/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/FPGA_Spartan6/R_M0_DQ7" +Ne 156 "/FPGA_Spartan6/R_M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/FPGA_Spartan6/R_M0_DQ6" +Ne 155 "/FPGA_Spartan6/R_M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_A5" +Ne 136 "/FPGA_Spartan6/R_M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_CAS#" +Ne 12 "/DDR_Banks/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M0_RAS#" +Ne 87 "/FPGA_Spartan6/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_A3" +Ne 134 "/FPGA_Spartan6/R_M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2688,7 +2763,7 @@ $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -590 -590 $EndPAD $PAD @@ -2702,7 +2777,7 @@ $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 196 -590 $EndPAD $PAD @@ -2716,7 +2791,7 @@ $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 983 -590 $EndPAD $PAD @@ -2737,7 +2812,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/FPGA_Spartan6/R_M1_BA1" +Ne 172 "/FPGA_Spartan6/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2751,28 +2826,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_Spartan6/R_M1_A6" +Ne 167 "/FPGA_Spartan6/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_Spartan6/R_M1_A5" +Ne 166 "/FPGA_Spartan6/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/FPGA_Spartan6/R_M1_DQ6" +Ne 188 "/FPGA_Spartan6/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/FPGA_Spartan6/R_M1_DQ7" +Ne 189 "/FPGA_Spartan6/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2793,21 +2868,21 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M0_LDQS" +Ne 86 "/FPGA_Spartan6/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_LDM" +Ne 85 "/FPGA_Spartan6/M0_LDM" Po -2952 -196 $EndPAD $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2558 -196 $EndPAD $PAD @@ -2835,7 +2910,7 @@ $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -983 -196 $EndPAD $PAD @@ -2849,7 +2924,7 @@ $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -196 -196 $EndPAD $PAD @@ -2863,7 +2938,7 @@ $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 590 -196 $EndPAD $PAD @@ -2898,21 +2973,21 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/FPGA_Spartan6/R_M1_LDM" +Ne 192 "/FPGA_Spartan6/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 180 "/FPGA_Spartan6/R_M1_LDQS" +Ne 193 "/FPGA_Spartan6/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -2933,21 +3008,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/FPGA_Spartan6/R_M0_DQ3" +Ne 152 "/FPGA_Spartan6/R_M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/FPGA_Spartan6/R_M0_DQ2" +Ne 151 "/FPGA_Spartan6/R_M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M0_UDM" +Ne 88 "/FPGA_Spartan6/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2996,7 +3071,7 @@ $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -590 196 $EndPAD $PAD @@ -3010,7 +3085,7 @@ $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 196 196 $EndPAD $PAD @@ -3024,7 +3099,7 @@ $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 983 196 $EndPAD $PAD @@ -3052,7 +3127,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 200 "/USB/USBA_VM" +Ne 215 "/USB/USBA_VM" Po 2558 196 $EndPAD $PAD @@ -3066,42 +3141,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/FPGA_Spartan6/R_M1_UDM" +Ne 195 "/FPGA_Spartan6/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/FPGA_Spartan6/R_M1_DQ2" +Ne 184 "/FPGA_Spartan6/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/FPGA_Spartan6/R_M1_DQ3" +Ne 185 "/FPGA_Spartan6/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/R_M0_DQ1" +Ne 144 "/FPGA_Spartan6/R_M0_DQ1" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/R_M0_DQ0" +Ne 143 "/FPGA_Spartan6/R_M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -3143,7 +3218,7 @@ $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -983 590 $EndPAD $PAD @@ -3157,7 +3232,7 @@ $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -196 590 $EndPAD $PAD @@ -3171,7 +3246,7 @@ $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 590 590 $EndPAD $PAD @@ -3192,14 +3267,14 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 198 "/USB/USBA_RCV" +Ne 214 "/USB/USBA_RCV" Po 1771 590 $EndPAD $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 2165 590 $EndPAD $PAD @@ -3220,35 +3295,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/FPGA_Spartan6/R_M1_DQ0" +Ne 176 "/FPGA_Spartan6/R_M1_DQ0" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/FPGA_Spartan6/R_M1_DQ1" +Ne 177 "/FPGA_Spartan6/R_M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA_Spartan6/R_M0_DQ9" +Ne 158 "/FPGA_Spartan6/R_M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/FPGA_Spartan6/R_M0_DQ8" +Ne 157 "/FPGA_Spartan6/R_M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3304,7 +3379,7 @@ $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -590 983 $EndPAD $PAD @@ -3318,7 +3393,7 @@ $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 196 983 $EndPAD $PAD @@ -3332,7 +3407,7 @@ $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 983 983 $EndPAD $PAD @@ -3353,14 +3428,14 @@ $PAD Sh "P17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 186 "/FPGA_Spartan6/USBA_VP" +Ne 202 "/FPGA_Spartan6/USBA_VP" Po 2165 983 $EndPAD $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 197 "/USB/USBA_OE_N" +Ne 200 "/FPGA_Spartan6/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -3381,21 +3456,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/FPGA_Spartan6/R_M1_DQ8" +Ne 190 "/FPGA_Spartan6/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/FPGA_Spartan6/R_M1_DQ9" +Ne 191 "/FPGA_Spartan6/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Spartan6/R_M0_DQ11" +Ne 146 "/FPGA_Spartan6/R_M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3409,7 +3484,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Spartan6/R_M0_DQ10" +Ne 145 "/FPGA_Spartan6/R_M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3423,7 +3498,7 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2558 1377 $EndPAD $PAD @@ -3514,21 +3589,21 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 2558 1377 $EndPAD $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 199 "/USB/USBA_SPD" +Ne 201 "/FPGA_Spartan6/USBA_SPD" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/FPGA_Spartan6/R_M1_DQ10" +Ne 178 "/FPGA_Spartan6/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3542,7 +3617,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/FPGA_Spartan6/R_M1_DQ11" +Ne 179 "/FPGA_Spartan6/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3556,7 +3631,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_UDQS" +Ne 89 "/FPGA_Spartan6/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3577,7 +3652,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/PROG_CSO" +Ne 123 "/FPGA_Spartan6/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -3605,7 +3680,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -983 1771 $EndPAD $PAD @@ -3633,7 +3708,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po 590 1771 $EndPAD $PAD @@ -3689,7 +3764,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/FPGA_Spartan6/R_M1_UDQS" +Ne 196 "/FPGA_Spartan6/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3703,21 +3778,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_Spartan6/R_M0_DQ13" +Ne 148 "/FPGA_Spartan6/R_M0_DQ13" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Spartan6/R_M0_DQ12" +Ne 147 "/FPGA_Spartan6/R_M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3745,7 +3820,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -1771 2165 $EndPAD $PAD @@ -3787,14 +3862,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/PROG_MISO3" +Ne 127 "/FPGA_Spartan6/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/PROG_MISO2" +Ne 126 "/FPGA_Spartan6/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -3836,35 +3911,35 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/FPGA_Spartan6/R_M1_DQ12" +Ne 180 "/FPGA_Spartan6/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/FPGA_Spartan6/R_M1_DQ13" +Ne 181 "/FPGA_Spartan6/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA_Spartan6/R_M0_DQ15" +Ne 150 "/FPGA_Spartan6/R_M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_Spartan6/R_M0_DQ14" +Ne 149 "/FPGA_Spartan6/R_M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3878,7 +3953,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2952 2558 $EndPAD $PAD @@ -3906,7 +3981,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -1377 2558 $EndPAD $PAD @@ -3920,7 +3995,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -590 2558 $EndPAD $PAD @@ -3934,7 +4009,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po 196 2558 $EndPAD $PAD @@ -3948,7 +4023,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 983 2558 $EndPAD $PAD @@ -3962,7 +4037,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po 1771 2558 $EndPAD $PAD @@ -3997,14 +4072,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/FPGA_Spartan6/R_M1_DQ14" +Ne 182 "/FPGA_Spartan6/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/FPGA_Spartan6/R_M1_DQ15" +Ne 183 "/FPGA_Spartan6/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -4039,7 +4114,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -2558 2952 $EndPAD $PAD @@ -4053,7 +4128,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -1771 2952 $EndPAD $PAD @@ -4116,7 +4191,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 1771 2952 $EndPAD $PAD @@ -4137,7 +4212,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 2952 2952 $EndPAD $PAD @@ -4333,7 +4408,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -3346 3739 $EndPAD $PAD @@ -4347,7 +4422,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2558 3739 $EndPAD $PAD @@ -4361,7 +4436,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -1771 3739 $EndPAD $PAD @@ -4375,7 +4450,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -983 3739 $EndPAD $PAD @@ -4389,7 +4464,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -196 3739 $EndPAD $PAD @@ -4403,7 +4478,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 590 3739 $EndPAD $PAD @@ -4417,7 +4492,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po 1377 3739 $EndPAD $PAD @@ -4431,7 +4506,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 2165 3739 $EndPAD $PAD @@ -4445,21 +4520,21 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po 2952 3739 $EndPAD $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/PROG_MISO1" +Ne 125 "/FPGA_Spartan6/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/PROG_CCLK" +Ne 122 "/FPGA_Spartan6/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -4473,7 +4548,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -4133 4133 $EndPAD $PAD @@ -4606,7 +4681,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/PROG_MISO0" +Ne 124 "/FPGA_Spartan6/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -4620,7 +4695,7 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 @@ -4642,35 +4717,35 @@ $PAD Sh "12" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -1613 1082 $EndPAD $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_RXER" +Ne 56 "/FPGA_Spartan6/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_RXC" +Ne 52 "/FPGA_Spartan6/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_RXDV" +Ne 55 "/FPGA_Spartan6/ETH_RXDV" Po -1613 491 $EndPAD $PAD Sh "8" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -1613 295 $EndPAD $PAD @@ -4684,63 +4759,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_RXD0" +Ne 41 "/Ethernet_Phy/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXD1" +Ne 42 "/Ethernet_Phy/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_RXD2" +Ne 53 "/FPGA_Spartan6/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_RXD3" +Ne 54 "/FPGA_Spartan6/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_MDC" +Ne 49 "/FPGA_Spartan6/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_MDIO" +Ne 50 "/FPGA_Spartan6/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_RESET_N" +Ne 51 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 40 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_CLK" +Ne 37 "/Ethernet_Phy/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -4754,7 +4829,7 @@ $PAD Sh "44" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -295 -1613 $EndPAD $PAD @@ -4775,56 +4850,56 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 206 "N-000386" +Ne 221 "N-000406" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 208 "N-000388" +Ne 223 "N-000408" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_A3.3V" +Ne 36 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 204 "N-000374" +Ne 219 "N-000394" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_INT" +Ne 48 "/FPGA_Spartan6/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_LED0" +Ne 38 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_LED1" +Ne 39 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4852,21 +4927,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_A1.8V" +Ne 35 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 209 "N-000389" +Ne 224 "N-000409" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 207 "N-000387" +Ne 222 "N-000407" Po 1613 -491 $EndPAD $PAD @@ -4880,14 +4955,14 @@ $PAD Sh "35" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 1613 -1082 $EndPAD $PAD @@ -4901,70 +4976,70 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/Ethernet_Phy/ETH_TXER" +Ne 60 "/FPGA_Spartan6/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_TXC" +Ne 43 "/Ethernet_Phy/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/ETH_TXEN" +Ne 45 "/Ethernet_Phy/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/ETH_TXD0" +Ne 57 "/FPGA_Spartan6/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/ETH_TXD1" +Ne 58 "/FPGA_Spartan6/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/ETH_TXD2" +Ne 59 "/FPGA_Spartan6/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/ETH_TXD3" +Ne 44 "/Ethernet_Phy/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_COL" +Ne 46 "/FPGA_Spartan6/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_CRS" +Ne 47 "/FPGA_Spartan6/ETH_CRS" Po 688 1613 $EndPAD $PAD Sh "23" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 885 1613 $EndPAD $PAD @@ -5235,28 +5310,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_RNB" +Ne 120 "/FPGA_Spartan6/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_RNB" +Ne 120 "/FPGA_Spartan6/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/NF_RE_N" +Ne 119 "/FPGA_Spartan6/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_CS1_N" +Ne 204 "/Non_volatile_memories/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -5284,7 +5359,7 @@ $PAD Sh "13" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 100 3850 $EndPAD $PAD @@ -5305,21 +5380,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_CLE" +Ne 203 "/Non_volatile_memories/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/Non_volatile_memories/NF_ALE" +Ne 115 "/FPGA_Spartan6/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/NF_WE_N" +Ne 121 "/FPGA_Spartan6/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -5396,28 +5471,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/Non_volatile_memories/NF_D0" +Ne 116 "/FPGA_Spartan6/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_D1" +Ne 205 "/Non_volatile_memories/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/NF_D2" +Ne 206 "/Non_volatile_memories/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/Non_volatile_memories/NF_D3" +Ne 207 "/Non_volatile_memories/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -5445,7 +5520,7 @@ $PAD Sh "36" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 100 -3850 $EndPAD $PAD @@ -5480,28 +5555,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/Non_volatile_memories/NF_D4" +Ne 117 "/FPGA_Spartan6/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/NF_D5" +Ne 208 "/Non_volatile_memories/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/Non_volatile_memories/NF_D6" +Ne 118 "/FPGA_Spartan6/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/NF_D7" +Ne 209 "/Non_volatile_memories/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -5554,21 +5629,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 196 "/Non_volatile_memories/SD_DAT2" +Ne 213 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 185 "/FPGA_Spartan6/SD_DAT3" +Ne 199 "/FPGA_Spartan6/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 193 "/Non_volatile_memories/SD_CMD" +Ne 211 "/Non_volatile_memories/SD_CMD" Po -433 0 $EndPAD $PAD @@ -5582,56 +5657,56 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 192 "/Non_volatile_memories/SD_CLK" +Ne 210 "/Non_volatile_memories/SD_CLK" Po 433 0 $EndPAD $PAD Sh "6" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 866 0 $EndPAD $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 194 "/Non_volatile_memories/SD_DAT0" +Ne 198 "/FPGA_Spartan6/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 195 "/Non_volatile_memories/SD_DAT1" +Ne 212 "/Non_volatile_memories/SD_DAT1" Po 1732 0 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po -2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po -2707 -2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 2707 -2244 $EndPAD $EndMODULE MICROSD-500901 @@ -5651,35 +5726,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 211 "N-000392" +Ne 226 "N-000412" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 211 "N-000392" +Ne 226 "N-000412" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 211 "N-000392" +Ne 226 "N-000412" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 211 "N-000392" +Ne 226 "N-000412" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 206 "N-000386" +Ne 221 "N-000406" Po -1750 -2500 $EndPAD $PAD @@ -5693,28 +5768,28 @@ $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 201 "GND" +Ne 216 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 207 "N-000387" +Ne 222 "N-000407" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 208 "N-000388" +Ne 223 "N-000408" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 201 "GND" +Ne 216 "GND" Po -250 -3500 $EndPAD $PAD @@ -5728,7 +5803,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 209 "N-000389" +Ne 224 "N-000409" Po 1750 -3500 $EndPAD $PAD @@ -5742,7 +5817,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 210 "N-000390" +Ne 225 "N-000410" Po -1150 -5400 $EndPAD $PAD @@ -5756,7 +5831,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 205 "N-000377" +Ne 220 "N-000397" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -5792,28 +5867,28 @@ $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 199 "/USB/USBA_SPD" +Ne 201 "/FPGA_Spartan6/USBA_SPD" Po -511 -1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 198 "/USB/USBA_RCV" +Ne 214 "/USB/USBA_RCV" Po -255 -1112 $EndPAD $PAD Sh "4" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 186 "/FPGA_Spartan6/USBA_VP" +Ne 202 "/FPGA_Spartan6/USBA_VP" Po 0 -1112 $EndPAD $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 200 "/USB/USBA_VM" +Ne 215 "/USB/USBA_VM" Po 255 -1112 $EndPAD $PAD @@ -5827,35 +5902,35 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 767 -1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 767 1112 $EndPAD $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 197 "/USB/USBA_OE_N" +Ne 200 "/FPGA_Spartan6/USBA_OE_N" Po 511 1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 212 "N-000399" +Ne 227 "N-000419" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 218 "N-000407" +Ne 233 "N-000427" Po 0 1112 $EndPAD $PAD @@ -5905,7 +5980,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ0" +Ne 24 "/DDR_Banks/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -5919,21 +5994,21 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ1" +Ne 25 "/DDR_Banks/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ2" +Ne 28 "/DDR_Banks/M1_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2814 2176 $EndPAD $PAD @@ -5961,28 +6036,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ5" +Ne 29 "/DDR_Banks/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_DQ6" +Ne 110 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/DDR_Banks/M1_DQ7" +Ne 111 "/FPGA_Spartan6/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -6003,7 +6078,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/DDR_Banks/M1_LDQS" +Ne 31 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -6031,7 +6106,7 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M1_LDM" +Ne 30 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD @@ -6045,21 +6120,21 @@ $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_CAS#" +Ne 21 "/DDR_Banks/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_RAS#" +Ne 32 "/DDR_Banks/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_CS#" +Ne 103 "/FPGA_Spartan6/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -6073,14 +6148,14 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_BA0" +Ne 20 "/DDR_Banks/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_BA1" +Ne 101 "/FPGA_Spartan6/M1_BA1" Po 2558 2176 $EndPAD $PAD @@ -6094,28 +6169,28 @@ $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A0" +Ne 17 "/DDR_Banks/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A1" +Ne 91 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A2" +Ne 94 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_A3" +Ne 95 "/FPGA_Spartan6/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -6129,49 +6204,49 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_A4" +Ne 19 "/DDR_Banks/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_A5" +Ne 96 "/FPGA_Spartan6/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_A6" +Ne 97 "/FPGA_Spartan6/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_A7" +Ne 98 "/FPGA_Spartan6/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_A8" +Ne 99 "/FPGA_Spartan6/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_A9" +Ne 100 "/FPGA_Spartan6/M1_A9" Po 2558 -2176 $EndPAD $PAD @@ -6185,7 +6260,7 @@ $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A12" +Ne 18 "/DDR_Banks/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -6199,42 +6274,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_CLK#" +Ne 23 "/DDR_Banks/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_CKE" +Ne 102 "/FPGA_Spartan6/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_CLK" +Ne 22 "/DDR_Banks/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/DDR_Banks/M1_UDM" +Ne 33 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 202 "N-000058" +Ne 217 "N-000058" Po 255 -2176 $EndPAD $PAD @@ -6248,14 +6323,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/DDR_Banks/M1_UDQS" +Ne 34 "/DDR_Banks/M1_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -511 -2176 $EndPAD $PAD @@ -6283,35 +6358,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_DQ9" +Ne 113 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_DQ10" +Ne 104 "/FPGA_Spartan6/M1_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_DQ11" +Ne 105 "/FPGA_Spartan6/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ12" +Ne 106 "/FPGA_Spartan6/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6325,35 +6400,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ13" +Ne 107 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ14" +Ne 26 "/DDR_Banks/M1_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ15" +Ne 27 "/DDR_Banks/M1_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -6382,7 +6457,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_DQ0" +Ne 13 "/DDR_Banks/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -6396,35 +6471,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ1" +Ne 73 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ2" +Ne 78 "/FPGA_Spartan6/M0_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ3" +Ne 79 "/FPGA_Spartan6/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_DQ4" +Ne 80 "/FPGA_Spartan6/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -6438,28 +6513,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ5" +Ne 81 "/FPGA_Spartan6/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_DQ6" +Ne 82 "/FPGA_Spartan6/M0_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_DQ7" +Ne 16 "/DDR_Banks/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -6480,7 +6555,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M0_LDQS" +Ne 86 "/FPGA_Spartan6/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -6508,35 +6583,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_LDM" +Ne 85 "/FPGA_Spartan6/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M0_WE#" +Ne 90 "/FPGA_Spartan6/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_CAS#" +Ne 12 "/DDR_Banks/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M0_RAS#" +Ne 87 "/FPGA_Spartan6/M0_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 1791 2176 $EndPAD $PAD @@ -6550,49 +6625,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_BA0" +Ne 11 "/DDR_Banks/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_BA1" +Ne 69 "/FPGA_Spartan6/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A10" +Ne 63 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A0" +Ne 61 "/FPGA_Spartan6/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A1" +Ne 62 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_A2" +Ne 64 "/FPGA_Spartan6/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_A3" +Ne 8 "/DDR_Banks/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -6606,63 +6681,63 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_A4" +Ne 9 "/DDR_Banks/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_A5" +Ne 65 "/FPGA_Spartan6/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_A6" +Ne 66 "/FPGA_Spartan6/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_A7" +Ne 10 "/DDR_Banks/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_A8" +Ne 67 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_A9" +Ne 68 "/FPGA_Spartan6/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A11" +Ne 6 "/DDR_Banks/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A12" +Ne 7 "/DDR_Banks/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6676,42 +6751,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_CLK#" +Ne 72 "/FPGA_Spartan6/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_CKE" +Ne 70 "/FPGA_Spartan6/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_CLK" +Ne 71 "/FPGA_Spartan6/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M0_UDM" +Ne 88 "/FPGA_Spartan6/M0_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 203 "N-000059" +Ne 218 "N-000059" Po 255 -2176 $EndPAD $PAD @@ -6725,14 +6800,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_UDQS" +Ne 89 "/FPGA_Spartan6/M0_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -511 -2176 $EndPAD $PAD @@ -6746,7 +6821,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_DQ8" +Ne 83 "/FPGA_Spartan6/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6760,35 +6835,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_DQ9" +Ne 84 "/FPGA_Spartan6/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ10" +Ne 74 "/FPGA_Spartan6/M0_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ11" +Ne 75 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ12" +Ne 14 "/DDR_Banks/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6802,35 +6877,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ13" +Ne 15 "/DDR_Banks/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ14" +Ne 76 "/FPGA_Spartan6/M0_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ15" +Ne 77 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -6851,14 +6926,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 214 "N-000401" +Ne 229 "N-000421" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6879,14 +6954,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 211 "N-000392" +Ne 226 "N-000412" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6907,14 +6982,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 205 "N-000377" +Ne 220 "N-000397" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/ETH_LED1" +Ne 39 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6935,14 +7010,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 210 "N-000390" +Ne 225 "N-000410" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/Ethernet_Phy/ETH_LED0" +Ne 38 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6970,7 +7045,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 209 "N-000389" +Ne 224 "N-000409" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6998,7 +7073,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 207 "N-000387" +Ne 222 "N-000407" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7026,7 +7101,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 208 "N-000388" +Ne 223 "N-000408" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7054,7 +7129,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 206 "N-000386" +Ne 221 "N-000406" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7075,14 +7150,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 204 "N-000374" +Ne 219 "N-000394" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7103,7 +7178,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 61 "/FPGA_Spartan6/ETH_MDIO" +Ne 50 "/FPGA_Spartan6/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -7131,14 +7206,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 214 "N-000401" +Ne 229 "N-000421" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7159,14 +7234,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 211 "N-000392" +Ne 226 "N-000412" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7194,7 +7269,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7222,7 +7297,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7243,14 +7318,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 48 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 40 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7271,14 +7346,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 44 "/Ethernet_Phy/ETH_A3.3V" +Ne 36 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7299,14 +7374,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/Ethernet_Phy/ETH_A1.8V" +Ne 35 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7334,7 +7409,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7362,7 +7437,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7390,7 +7465,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7418,7 +7493,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7439,14 +7514,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 212 "N-000399" +Ne 227 "N-000419" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7467,14 +7542,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 218 "N-000407" +Ne 233 "N-000427" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7502,7 +7577,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7530,7 +7605,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7558,7 +7633,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7579,14 +7654,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_A3.3V" +Ne 36 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7614,7 +7689,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7635,7 +7710,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 216 "N-000405" +Ne 231 "N-000425" Po -570 0 $EndPAD $PAD @@ -7668,56 +7743,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 217 "N-000406" +Ne 232 "N-000426" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 212 "N-000399" +Ne 227 "N-000419" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 218 "N-000407" +Ne 233 "N-000427" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 218 "N-000407" +Ne 233 "N-000427" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 214 "N-000401" +Ne 229 "N-000421" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 214 "N-000401" +Ne 229 "N-000421" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 214 "N-000401" +Ne 229 "N-000421" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 214 "N-000401" +Ne 229 "N-000421" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -7745,7 +7820,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 203 "N-000059" +Ne 218 "N-000059" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7766,14 +7841,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 203 "N-000059" +Ne 218 "N-000059" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7794,14 +7869,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 202 "N-000058" +Ne 217 "N-000058" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7829,7 +7904,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 202 "N-000058" +Ne 217 "N-000058" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7857,7 +7932,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 203 "N-000059" +Ne 218 "N-000059" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7878,14 +7953,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 203 "N-000059" +Ne 218 "N-000059" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7913,7 +7988,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 202 "N-000058" +Ne 217 "N-000058" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7941,7 +8016,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7969,7 +8044,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7997,7 +8072,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8025,7 +8100,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8053,7 +8128,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8081,7 +8156,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8109,7 +8184,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8137,7 +8212,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8165,7 +8240,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8193,7 +8268,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8221,7 +8296,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8249,7 +8324,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8270,14 +8345,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 202 "N-000058" +Ne 217 "N-000058" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8298,14 +8373,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 213 "N-000400" +Ne 228 "N-000420" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8326,14 +8401,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 216 "N-000405" +Ne 231 "N-000425" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 217 "N-000406" +Ne 232 "N-000426" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8354,7 +8429,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 215 "N-000402" +Ne 230 "N-000422" Po -294 0 $EndPAD $PAD @@ -8389,7 +8464,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8410,14 +8485,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 221 "N-000410" +Ne 236 "N-000430" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8438,14 +8513,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 221 "N-000410" +Ne 236 "N-000430" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8473,7 +8548,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8494,14 +8569,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 219 "N-000408" +Ne 234 "N-000428" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8522,14 +8597,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 220 "N-000409" +Ne 235 "N-000429" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8557,7 +8632,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -8585,7 +8660,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -8606,7 +8681,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 215 "N-000402" +Ne 230 "N-000422" Po -570 0 $EndPAD $PAD @@ -8684,14 +8759,14 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 767 -1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 767 1112 $EndPAD $PAD @@ -8705,14 +8780,14 @@ $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 219 "N-000408" +Ne 234 "N-000428" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 220 "N-000409" +Ne 235 "N-000429" Po 0 1112 $EndPAD $PAD @@ -8754,14 +8829,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8789,7 +8864,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8810,14 +8885,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8845,7 +8920,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8873,7 +8948,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8894,14 +8969,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8929,7 +9004,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8957,7 +9032,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8978,14 +9053,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9013,12 +9088,12 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 54510 34490 1800 0 4C697413 4C656C49 ~~ +Po 54528 34449 1800 0 4C697413 4C656C49 ~~ Li 0402 Sc 4C656C49 AR /4C431A63/4C656C49 @@ -9041,7 +9116,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9069,7 +9144,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9097,7 +9172,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9125,7 +9200,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9153,7 +9228,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9181,7 +9256,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9209,7 +9284,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9237,7 +9312,7 @@ $PAD Sh "2" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9258,14 +9333,14 @@ $PAD Sh "1" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9293,7 +9368,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9321,7 +9396,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9349,7 +9424,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9377,7 +9452,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9405,7 +9480,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9433,7 +9508,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9454,14 +9529,14 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9489,7 +9564,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9517,7 +9592,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9545,7 +9620,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9573,7 +9648,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9601,7 +9676,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9629,7 +9704,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -9656,56 +9731,56 @@ $PAD Sh "8" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 222 "VCCO2" +Ne 237 "VCCO2" Po -750 -1050 $EndPAD $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/PROG_CSO" +Ne 123 "/FPGA_Spartan6/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/PROG_MISO3" +Ne 127 "/FPGA_Spartan6/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/PROG_CCLK" +Ne 122 "/FPGA_Spartan6/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/PROG_MISO0" +Ne 124 "/FPGA_Spartan6/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/PROG_MISO1" +Ne 125 "/FPGA_Spartan6/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/PROG_MISO2" +Ne 126 "/FPGA_Spartan6/PROG_MISO2" Po 250 1050 $EndPAD $PAD Sh "4" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 750 1050 $EndPAD $SHAPE3D @@ -9739,7 +9814,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9767,7 +9842,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9795,7 +9870,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9823,7 +9898,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9851,7 +9926,7 @@ $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9879,7 +9954,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 44 "/Ethernet_Phy/ETH_A3.3V" +Ne 36 "/Ethernet_Phy/ETH_A3.3V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9907,7 +9982,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/Ethernet_Phy/ETH_A1.8V" +Ne 35 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9928,14 +10003,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/Ethernet_Phy/ETH_A1.8V" +Ne 35 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 48 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 40 "/Ethernet_Phy/ETH_PLL1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9956,7 +10031,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -176 0 $EndPAD $PAD @@ -9982,56 +10057,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 146 "/FPGA_Spartan6/R_M1_A0" +Ne 159 "/FPGA_Spartan6/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 147 "/FPGA_Spartan6/R_M1_A1" +Ne 160 "/FPGA_Spartan6/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 151 "/FPGA_Spartan6/R_M1_A2" +Ne 164 "/FPGA_Spartan6/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 152 "/FPGA_Spartan6/R_M1_A3" +Ne 165 "/FPGA_Spartan6/R_M1_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 96 "/FPGA_Spartan6/M1_A3" +Ne 95 "/FPGA_Spartan6/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/FPGA_Spartan6/M1_A2" +Ne 94 "/FPGA_Spartan6/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M1_A1" +Ne 91 "/FPGA_Spartan6/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Banks/M1_A0" +Ne 17 "/DDR_Banks/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10050,28 +10125,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/FPGA_Spartan6/R_M1_RAS#" +Ne 194 "/FPGA_Spartan6/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/FPGA_Spartan6/R_M1_BA0" +Ne 171 "/FPGA_Spartan6/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/FPGA_Spartan6/R_M1_BA1" +Ne 172 "/FPGA_Spartan6/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 148 "/FPGA_Spartan6/R_M1_A10" +Ne 161 "/FPGA_Spartan6/R_M1_A10" Po 295 -177 $EndPAD $PAD @@ -10085,21 +10160,21 @@ $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Banks/M1_BA1" +Ne 101 "/FPGA_Spartan6/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/DDR_Banks/M1_BA0" +Ne 20 "/DDR_Banks/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 113 "/FPGA_Spartan6/M1_RAS#" +Ne 32 "/DDR_Banks/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10118,49 +10193,49 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 173 "/FPGA_Spartan6/R_M1_DQ4" +Ne 186 "/FPGA_Spartan6/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 174 "/FPGA_Spartan6/R_M1_DQ5" +Ne 187 "/FPGA_Spartan6/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 175 "/FPGA_Spartan6/R_M1_DQ6" +Ne 188 "/FPGA_Spartan6/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 176 "/FPGA_Spartan6/R_M1_DQ7" +Ne 189 "/FPGA_Spartan6/R_M1_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 37 "/DDR_Banks/M1_DQ7" +Ne 111 "/FPGA_Spartan6/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 111 "/FPGA_Spartan6/M1_DQ6" +Ne 110 "/FPGA_Spartan6/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 110 "/FPGA_Spartan6/M1_DQ5" +Ne 29 "/DDR_Banks/M1_DQ5" Po -98 177 $EndPAD $PAD @@ -10186,35 +10261,35 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 180 "/FPGA_Spartan6/R_M1_LDQS" +Ne 193 "/FPGA_Spartan6/R_M1_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 179 "/FPGA_Spartan6/R_M1_LDM" +Ne 192 "/FPGA_Spartan6/R_M1_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/FPGA_Spartan6/R_M1_WE#" +Ne 197 "/FPGA_Spartan6/R_M1_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/FPGA_Spartan6/R_M1_CAS#" +Ne 173 "/FPGA_Spartan6/R_M1_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/DDR_Banks/M1_CAS#" +Ne 21 "/DDR_Banks/M1_CAS#" Po 295 177 $EndPAD $PAD @@ -10228,14 +10303,14 @@ $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M1_LDM" +Ne 30 "/DDR_Banks/M1_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/DDR_Banks/M1_LDQS" +Ne 31 "/DDR_Banks/M1_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10254,28 +10329,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/FPGA_Spartan6/R_M1_DQ0" +Ne 176 "/FPGA_Spartan6/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/FPGA_Spartan6/R_M1_DQ1" +Ne 177 "/FPGA_Spartan6/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/FPGA_Spartan6/R_M1_DQ2" +Ne 184 "/FPGA_Spartan6/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 172 "/FPGA_Spartan6/R_M1_DQ3" +Ne 185 "/FPGA_Spartan6/R_M1_DQ3" Po 295 -177 $EndPAD $PAD @@ -10289,21 +10364,21 @@ $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/FPGA_Spartan6/M1_DQ2" +Ne 28 "/DDR_Banks/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 102 "/FPGA_Spartan6/M1_DQ1" +Ne 25 "/DDR_Banks/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 101 "/FPGA_Spartan6/M1_DQ0" +Ne 24 "/DDR_Banks/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10322,21 +10397,21 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/FPGA_Spartan6/R_M1_A7" +Ne 168 "/FPGA_Spartan6/R_M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 154 "/FPGA_Spartan6/R_M1_A6" +Ne 167 "/FPGA_Spartan6/R_M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/FPGA_Spartan6/R_M1_A5" +Ne 166 "/FPGA_Spartan6/R_M1_A5" Po 98 -177 $EndPAD $PAD @@ -10350,28 +10425,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 97 "/FPGA_Spartan6/M1_A4" +Ne 19 "/DDR_Banks/M1_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Banks/M1_A5" +Ne 96 "/FPGA_Spartan6/M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 98 "/FPGA_Spartan6/M1_A6" +Ne 97 "/FPGA_Spartan6/M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Banks/M1_A7" +Ne 98 "/FPGA_Spartan6/M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10390,42 +10465,42 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/FPGA_Spartan6/R_M1_A12" +Ne 163 "/FPGA_Spartan6/R_M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/FPGA_Spartan6/R_M1_A11" +Ne 162 "/FPGA_Spartan6/R_M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/FPGA_Spartan6/R_M1_A9" +Ne 170 "/FPGA_Spartan6/R_M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/FPGA_Spartan6/R_M1_A8" +Ne 169 "/FPGA_Spartan6/R_M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M1_A8" +Ne 99 "/FPGA_Spartan6/M1_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 99 "/FPGA_Spartan6/M1_A9" +Ne 100 "/FPGA_Spartan6/M1_A9" Po 98 177 $EndPAD $PAD @@ -10439,7 +10514,7 @@ $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/FPGA_Spartan6/M1_A12" +Ne 18 "/DDR_Banks/M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10460,14 +10535,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_CLK#" +Ne 23 "/DDR_Banks/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 100 "/FPGA_Spartan6/M1_CLK" +Ne 22 "/DDR_Banks/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10486,28 +10561,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/FPGA_Spartan6/R_M1_DQ11" +Ne 179 "/FPGA_Spartan6/R_M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/FPGA_Spartan6/R_M1_DQ10" +Ne 178 "/FPGA_Spartan6/R_M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 178 "/FPGA_Spartan6/R_M1_DQ9" +Ne 191 "/FPGA_Spartan6/R_M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 177 "/FPGA_Spartan6/R_M1_DQ8" +Ne 190 "/FPGA_Spartan6/R_M1_DQ8" Po 295 -177 $EndPAD $PAD @@ -10521,21 +10596,21 @@ $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_DQ9" +Ne 113 "/FPGA_Spartan6/M1_DQ9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/DDR_Banks/M1_DQ10" +Ne 104 "/FPGA_Spartan6/M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 36 "/DDR_Banks/M1_DQ11" +Ne 105 "/FPGA_Spartan6/M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10554,56 +10629,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/FPGA_Spartan6/R_M1_DQ15" +Ne 183 "/FPGA_Spartan6/R_M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/FPGA_Spartan6/R_M1_DQ14" +Ne 182 "/FPGA_Spartan6/R_M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/FPGA_Spartan6/R_M1_DQ13" +Ne 181 "/FPGA_Spartan6/R_M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/FPGA_Spartan6/R_M1_DQ12" +Ne 180 "/FPGA_Spartan6/R_M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/FPGA_Spartan6/M1_DQ12" +Ne 106 "/FPGA_Spartan6/M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/FPGA_Spartan6/M1_DQ13" +Ne 107 "/FPGA_Spartan6/M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 105 "/FPGA_Spartan6/M1_DQ14" +Ne 26 "/DDR_Banks/M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 106 "/FPGA_Spartan6/M1_DQ15" +Ne 27 "/DDR_Banks/M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10624,14 +10699,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/FPGA_Spartan6/R_M1_UDM" +Ne 195 "/FPGA_Spartan6/R_M1_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/DDR_Banks/M1_UDM" +Ne 33 "/DDR_Banks/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10652,14 +10727,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/FPGA_Spartan6/R_M1_CKE" +Ne 174 "/FPGA_Spartan6/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Banks/M1_CKE" +Ne 102 "/FPGA_Spartan6/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10680,14 +10755,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/FPGA_Spartan6/R_M1_CS#" +Ne 175 "/FPGA_Spartan6/R_M1_CS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/DDR_Banks/M1_CS#" +Ne 103 "/FPGA_Spartan6/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10708,14 +10783,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/FPGA_Spartan6/R_M1_UDQS" +Ne 196 "/FPGA_Spartan6/R_M1_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/DDR_Banks/M1_UDQS" +Ne 34 "/DDR_Banks/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10737,28 +10812,28 @@ $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po -235 -235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 235 -235 $EndPAD $PAD @@ -10870,7 +10945,7 @@ $PAD Sh "8" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "GND" +Ne 216 "GND" Po 688 0 $EndPAD $PAD @@ -10917,56 +10992,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 134 "/FPGA_Spartan6/R_M0_DQ12" +Ne 147 "/FPGA_Spartan6/R_M0_DQ12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 135 "/FPGA_Spartan6/R_M0_DQ13" +Ne 148 "/FPGA_Spartan6/R_M0_DQ13" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 136 "/FPGA_Spartan6/R_M0_DQ14" +Ne 149 "/FPGA_Spartan6/R_M0_DQ14" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 137 "/FPGA_Spartan6/R_M0_DQ15" +Ne 150 "/FPGA_Spartan6/R_M0_DQ15" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Spartan6/M0_DQ15" +Ne 77 "/FPGA_Spartan6/M0_DQ15" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 16 "/DDR_Banks/M0_DQ14" +Ne 76 "/FPGA_Spartan6/M0_DQ14" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 83 "/FPGA_Spartan6/M0_DQ13" +Ne 15 "/DDR_Banks/M0_DQ13" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 15 "/DDR_Banks/M0_DQ12" +Ne 14 "/DDR_Banks/M0_DQ12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10985,56 +11060,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/FPGA_Spartan6/R_M0_DQ8" +Ne 157 "/FPGA_Spartan6/R_M0_DQ8" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 145 "/FPGA_Spartan6/R_M0_DQ9" +Ne 158 "/FPGA_Spartan6/R_M0_DQ9" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 132 "/FPGA_Spartan6/R_M0_DQ10" +Ne 145 "/FPGA_Spartan6/R_M0_DQ10" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 133 "/FPGA_Spartan6/R_M0_DQ11" +Ne 146 "/FPGA_Spartan6/R_M0_DQ11" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 82 "/FPGA_Spartan6/M0_DQ11" +Ne 75 "/FPGA_Spartan6/M0_DQ11" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 14 "/DDR_Banks/M0_DQ10" +Ne 74 "/FPGA_Spartan6/M0_DQ10" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 21 "/DDR_Banks/M0_DQ9" +Ne 84 "/FPGA_Spartan6/M0_DQ9" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/DDR_Banks/M0_DQ8" +Ne 83 "/FPGA_Spartan6/M0_DQ8" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -11053,56 +11128,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 130 "/FPGA_Spartan6/R_M0_DQ0" +Ne 143 "/FPGA_Spartan6/R_M0_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 131 "/FPGA_Spartan6/R_M0_DQ1" +Ne 144 "/FPGA_Spartan6/R_M0_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 138 "/FPGA_Spartan6/R_M0_DQ2" +Ne 151 "/FPGA_Spartan6/R_M0_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 139 "/FPGA_Spartan6/R_M0_DQ3" +Ne 152 "/FPGA_Spartan6/R_M0_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 85 "/FPGA_Spartan6/M0_DQ3" +Ne 79 "/FPGA_Spartan6/M0_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 17 "/DDR_Banks/M0_DQ2" +Ne 78 "/FPGA_Spartan6/M0_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 13 "/DDR_Banks/M0_DQ1" +Ne 73 "/FPGA_Spartan6/M0_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 12 "/DDR_Banks/M0_DQ0" +Ne 13 "/DDR_Banks/M0_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -11121,56 +11196,396 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 140 "/FPGA_Spartan6/R_M0_DQ4" +Ne 153 "/FPGA_Spartan6/R_M0_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 141 "/FPGA_Spartan6/R_M0_DQ5" +Ne 154 "/FPGA_Spartan6/R_M0_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/FPGA_Spartan6/R_M0_DQ6" +Ne 155 "/FPGA_Spartan6/R_M0_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/FPGA_Spartan6/R_M0_DQ7" +Ne 156 "/FPGA_Spartan6/R_M0_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 87 "/FPGA_Spartan6/M0_DQ7" +Ne 16 "/DDR_Banks/M0_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 19 "/DDR_Banks/M0_DQ6" +Ne 82 "/FPGA_Spartan6/M0_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 86 "/FPGA_Spartan6/M0_DQ5" +Ne 81 "/FPGA_Spartan6/M0_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Banks/M0_DQ4" +Ne 80 "/FPGA_Spartan6/M0_DQ4" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 48819 32087 0 0 4C69A686 4C6A0EC0 ~~ +Li R_PACK4-0402 +Sc 4C6A0EC0 +AR /4C431A63/4C6A0D54 +Op 0 0 0 +T0 117 451 197 197 0 49 M V 20 N"RP18" +T1 68 -436 157 157 0 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 132 "/FPGA_Spartan6/R_M0_A12" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 131 "/FPGA_Spartan6/R_M0_A11" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 140 "/FPGA_Spartan6/R_M0_A9" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 139 "/FPGA_Spartan6/R_M0_A8" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 67 "/FPGA_Spartan6/M0_A8" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 68 "/FPGA_Spartan6/M0_A9" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "/DDR_Banks/M0_A11" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 7 "/DDR_Banks/M0_A12" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 48622 31299 0 0 4C69A686 4C6A0EC2 ~~ +Li R_PACK4-0402 +Sc 4C6A0EC2 +AR /4C431A63/4C6A0D55 +Op 0 0 0 +T0 117 451 197 197 0 49 M V 20 N"RP17" +T1 68 -436 157 157 0 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 138 "/FPGA_Spartan6/R_M0_A7" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 137 "/FPGA_Spartan6/R_M0_A6" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 136 "/FPGA_Spartan6/R_M0_A5" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 135 "/FPGA_Spartan6/R_M0_A4" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 9 "/DDR_Banks/M0_A4" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 65 "/FPGA_Spartan6/M0_A5" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 66 "/FPGA_Spartan6/M0_A6" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 10 "/DDR_Banks/M0_A7" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 50000 33465 900 0 4C69A686 4C6A0EC4 ~~ +Li R_PACK4-0402 +Sc 4C6A0EC4 +AR /4C431A63/4C6A0D56 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP16" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 12 "/DDR_Banks/M0_CAS#" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 90 "/FPGA_Spartan6/M0_WE#" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 85 "/FPGA_Spartan6/M0_LDM" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 86 "/FPGA_Spartan6/M0_LDQS" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 50000 32283 900 0 4C69A686 4C6A0EC6 ~~ +Li R_PACK4-0402 +Sc 4C6A0EC6 +AR /4C431A63/4C6A0D57 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP15" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 141 "/FPGA_Spartan6/R_M0_BA0" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 142 "/FPGA_Spartan6/R_M0_BA1" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 130 "/FPGA_Spartan6/R_M0_A10" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 63 "/FPGA_Spartan6/M0_A10" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 69 "/FPGA_Spartan6/M0_BA1" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 11 "/DDR_Banks/M0_BA0" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 87 "/FPGA_Spartan6/M0_RAS#" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 50000 31299 900 0 4C69A686 4C6A0EC8 ~~ +Li R_PACK4-0402 +Sc 4C6A0EC8 +AR /4C431A63/4C6A0D58 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP14" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 128 "/FPGA_Spartan6/R_M0_A0" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 129 "/FPGA_Spartan6/R_M0_A1" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 133 "/FPGA_Spartan6/R_M0_A2" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 134 "/FPGA_Spartan6/R_M0_A3" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 8 "/DDR_Banks/M0_A3" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 64 "/FPGA_Spartan6/M0_A2" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 62 "/FPGA_Spartan6/M0_A1" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 61 "/FPGA_Spartan6/M0_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 4c667d9..5006a04 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,4 +1,4 @@ -# EESchema Netlist Version 1.1 created Mon 16 Aug 2010 10:43:52 PM COT +# EESchema Netlist Version 1.1 created Mon 16 Aug 2010 11:28:07 PM COT ( ( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF} ( PAD GND ) @@ -59,7 +59,7 @@ ( 4 +3.3V ) ( 5 /Non_volatile_memories/SD_CLK ) ( 6 GND ) - ( 7 /Non_volatile_memories/SD_DAT0 ) + ( 7 /FPGA_Spartan6/SD_DAT0 ) ( 8 /Non_volatile_memories/SD_DAT1 ) ) ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} @@ -71,15 +71,15 @@ ( 6 /FPGA_Spartan6/NF_RNB ) ( 7 /FPGA_Spartan6/NF_RNB ) ( 8 /FPGA_Spartan6/NF_RE_N ) - ( 9 /FPGA_Spartan6/NF_CS1_N ) + ( 9 /Non_volatile_memories/NF_CS1_N ) ( 10 ? ) ( 11 ? ) ( 12 +3.3V ) ( 13 GND ) ( 14 ? ) ( 15 ? ) - ( 16 /FPGA_Spartan6/NF_CLE ) - ( 17 /Non_volatile_memories/NF_ALE ) + ( 16 /Non_volatile_memories/NF_CLE ) + ( 17 /FPGA_Spartan6/NF_ALE ) ( 18 /FPGA_Spartan6/NF_WE_N ) ( 19 +3.3V ) ( 20 ? ) @@ -91,9 +91,9 @@ ( 26 ? ) ( 27 ? ) ( 28 ? ) - ( 29 /Non_volatile_memories/NF_D0 ) - ( 30 /FPGA_Spartan6/NF_D1 ) - ( 31 /FPGA_Spartan6/NF_D2 ) + ( 29 /FPGA_Spartan6/NF_D0 ) + ( 30 /Non_volatile_memories/NF_D1 ) + ( 31 /Non_volatile_memories/NF_D2 ) ( 32 /Non_volatile_memories/NF_D3 ) ( 33 ? ) ( 34 ? ) @@ -103,10 +103,10 @@ ( 38 ? ) ( 39 ? ) ( 40 ? ) - ( 41 /Non_volatile_memories/NF_D4 ) - ( 42 /FPGA_Spartan6/NF_D5 ) - ( 43 /Non_volatile_memories/NF_D6 ) - ( 44 /FPGA_Spartan6/NF_D7 ) + ( 41 /FPGA_Spartan6/NF_D4 ) + ( 42 /Non_volatile_memories/NF_D5 ) + ( 43 /FPGA_Spartan6/NF_D6 ) + ( 44 /Non_volatile_memories/NF_D7 ) ( 45 ? ) ( 46 ? ) ( 47 ? ) @@ -121,8 +121,8 @@ ( 7 GND ) ( 8 GND ) ( 9 ? ) - ( 10 N-000408 ) - ( 11 N-000409 ) + ( 10 N-000428 ) + ( 11 N-000429 ) ( 12 +3.3V ) ( 14 +3.3V ) ) @@ -139,23 +139,23 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552BA $noname F2 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000402 ) + ( 1 N-000422 ) ( 2 +5V ) ) ( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000408 ) + ( 1 N-000428 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000409 ) + ( 1 N-000429 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C} - ( 1 N-000410 ) + ( 1 N-000430 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R} - ( 1 N-000410 ) + ( 1 N-000430 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} @@ -163,46 +163,46 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552B0 0603 L6 FB {Lib=INDUCTOR} - ( 1 N-000402 ) + ( 1 N-000422 ) ( 2 ? ) ) ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000405 ) - ( 2 N-000406 ) + ( 1 N-000425 ) + ( 2 N-000426 ) ) ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000400 ) + ( 1 N-000420 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000401 ) + ( 1 N-000421 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000401 ) + ( 1 N-000421 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000407 ) + ( 1 N-000427 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000399 ) + ( 1 N-000419 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000405 ) + ( 1 N-000425 ) ( 2 +5V ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000401 ) - ( S2 N-000401 ) - ( S3 N-000401 ) - ( S4 N-000401 ) - ( 1 N-000406 ) - ( 2 N-000399 ) - ( 3 N-000407 ) - ( 4 N-000400 ) + ( S1 N-000421 ) + ( S2 N-000421 ) + ( S3 N-000421 ) + ( S4 N-000421 ) + ( 1 N-000426 ) + ( 2 N-000419 ) + ( 3 N-000427 ) + ( 4 N-000420 ) ) ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} ( 1 +2.5V ) @@ -218,27 +218,77 @@ ) ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) - ( 2 /USB/USBA_SPD ) + ( 2 /FPGA_Spartan6/USBA_SPD ) ( 3 /USB/USBA_RCV ) ( 4 /FPGA_Spartan6/USBA_VP ) ( 5 /USB/USBA_VM ) ( 7 GND ) ( 8 GND ) - ( 9 /USB/USBA_OE_N ) - ( 10 N-000399 ) - ( 11 N-000407 ) + ( 9 /FPGA_Spartan6/USBA_OE_N ) + ( 10 N-000419 ) + ( 11 N-000427 ) ( 12 +3.3V ) ( 14 +3.3V ) ) + ( /4C431A63/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_A0 ) + ( 2 /FPGA_Spartan6/R_M0_A1 ) + ( 3 /FPGA_Spartan6/R_M0_A2 ) + ( 4 /FPGA_Spartan6/R_M0_A3 ) + ( 5 /DDR_Banks/M0_A3 ) + ( 6 /FPGA_Spartan6/M0_A2 ) + ( 7 /FPGA_Spartan6/M0_A1 ) + ( 8 /FPGA_Spartan6/M0_A0 ) + ) + ( /4C431A63/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4} + ( 1 ? ) + ( 2 /FPGA_Spartan6/R_M0_BA0 ) + ( 3 /FPGA_Spartan6/R_M0_BA1 ) + ( 4 /FPGA_Spartan6/R_M0_A10 ) + ( 5 /FPGA_Spartan6/M0_A10 ) + ( 6 /FPGA_Spartan6/M0_BA1 ) + ( 7 /DDR_Banks/M0_BA0 ) + ( 8 /FPGA_Spartan6/M0_RAS# ) + ) + ( /4C431A63/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 {Lib=R_PACK4} + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 /DDR_Banks/M0_CAS# ) + ( 6 /FPGA_Spartan6/M0_WE# ) + ( 7 /FPGA_Spartan6/M0_LDM ) + ( 8 /FPGA_Spartan6/M0_LDQS ) + ) + ( /4C431A63/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_A7 ) + ( 2 /FPGA_Spartan6/R_M0_A6 ) + ( 3 /FPGA_Spartan6/R_M0_A5 ) + ( 4 /FPGA_Spartan6/R_M0_A4 ) + ( 5 /DDR_Banks/M0_A4 ) + ( 6 /FPGA_Spartan6/M0_A5 ) + ( 7 /FPGA_Spartan6/M0_A6 ) + ( 8 /DDR_Banks/M0_A7 ) + ) + ( /4C431A63/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_A12 ) + ( 2 /FPGA_Spartan6/R_M0_A11 ) + ( 3 /FPGA_Spartan6/R_M0_A9 ) + ( 4 /FPGA_Spartan6/R_M0_A8 ) + ( 5 /FPGA_Spartan6/M0_A8 ) + ( 6 /FPGA_Spartan6/M0_A9 ) + ( 7 /DDR_Banks/M0_A11 ) + ( 8 /DDR_Banks/M0_A12 ) + ) ( /4C431A63/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_DQ4 ) ( 2 /FPGA_Spartan6/R_M0_DQ5 ) ( 3 /FPGA_Spartan6/R_M0_DQ6 ) ( 4 /FPGA_Spartan6/R_M0_DQ7 ) - ( 5 /FPGA_Spartan6/M0_DQ7 ) - ( 6 /DDR_Banks/M0_DQ6 ) + ( 5 /DDR_Banks/M0_DQ7 ) + ( 6 /FPGA_Spartan6/M0_DQ6 ) ( 7 /FPGA_Spartan6/M0_DQ5 ) - ( 8 /DDR_Banks/M0_DQ4 ) + ( 8 /FPGA_Spartan6/M0_DQ4 ) ) ( /4C431A63/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_DQ0 ) @@ -246,8 +296,8 @@ ( 3 /FPGA_Spartan6/R_M0_DQ2 ) ( 4 /FPGA_Spartan6/R_M0_DQ3 ) ( 5 /FPGA_Spartan6/M0_DQ3 ) - ( 6 /DDR_Banks/M0_DQ2 ) - ( 7 /DDR_Banks/M0_DQ1 ) + ( 6 /FPGA_Spartan6/M0_DQ2 ) + ( 7 /FPGA_Spartan6/M0_DQ1 ) ( 8 /DDR_Banks/M0_DQ0 ) ) ( /4C431A63/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4} @@ -256,9 +306,9 @@ ( 3 /FPGA_Spartan6/R_M0_DQ10 ) ( 4 /FPGA_Spartan6/R_M0_DQ11 ) ( 5 /FPGA_Spartan6/M0_DQ11 ) - ( 6 /DDR_Banks/M0_DQ10 ) - ( 7 /DDR_Banks/M0_DQ9 ) - ( 8 /DDR_Banks/M0_DQ8 ) + ( 6 /FPGA_Spartan6/M0_DQ10 ) + ( 7 /FPGA_Spartan6/M0_DQ9 ) + ( 8 /FPGA_Spartan6/M0_DQ8 ) ) ( /4C431A63/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_DQ12 ) @@ -266,8 +316,8 @@ ( 3 /FPGA_Spartan6/R_M0_DQ14 ) ( 4 /FPGA_Spartan6/R_M0_DQ15 ) ( 5 /FPGA_Spartan6/M0_DQ15 ) - ( 6 /DDR_Banks/M0_DQ14 ) - ( 7 /FPGA_Spartan6/M0_DQ13 ) + ( 6 /FPGA_Spartan6/M0_DQ14 ) + ( 7 /DDR_Banks/M0_DQ13 ) ( 8 /DDR_Banks/M0_DQ12 ) ) ( /4C431A63/4C69E7DD 0402 R19 33 {Lib=R} @@ -276,11 +326,11 @@ ) ( /4C431A63/4C69E92D 0402 R20 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CS# ) - ( 2 /DDR_Banks/M1_CS# ) + ( 2 /FPGA_Spartan6/M1_CS# ) ) ( /4C431A63/4C69E7F8 0402 R17 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CKE ) - ( 2 /DDR_Banks/M1_CKE ) + ( 2 /FPGA_Spartan6/M1_CKE ) ) ( /4C431A63/4C69E7C2 0402 R18 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_UDM ) @@ -292,9 +342,9 @@ ( 3 /FPGA_Spartan6/R_M1_DQ9 ) ( 4 /FPGA_Spartan6/R_M1_DQ8 ) ( 5 /FPGA_Spartan6/M1_DQ8 ) - ( 6 /DDR_Banks/M1_DQ9 ) - ( 7 /DDR_Banks/M1_DQ10 ) - ( 8 /DDR_Banks/M1_DQ11 ) + ( 6 /FPGA_Spartan6/M1_DQ9 ) + ( 7 /FPGA_Spartan6/M1_DQ10 ) + ( 8 /FPGA_Spartan6/M1_DQ11 ) ) ( /4C431A63/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ15 ) @@ -303,32 +353,32 @@ ( 4 /FPGA_Spartan6/R_M1_DQ12 ) ( 5 /FPGA_Spartan6/M1_DQ12 ) ( 6 /FPGA_Spartan6/M1_DQ13 ) - ( 7 /FPGA_Spartan6/M1_DQ14 ) - ( 8 /FPGA_Spartan6/M1_DQ15 ) + ( 7 /DDR_Banks/M1_DQ14 ) + ( 8 /DDR_Banks/M1_DQ15 ) ) ( /4C431A63/4C69DF7A 0402 R16 120 {Lib=R} ( 1 /DDR_Banks/M1_CLK# ) - ( 2 /FPGA_Spartan6/M1_CLK ) + ( 2 /DDR_Banks/M1_CLK ) ) ( /4C431A63/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A12 ) ( 2 /FPGA_Spartan6/R_M1_A11 ) ( 3 /FPGA_Spartan6/R_M1_A9 ) ( 4 /FPGA_Spartan6/R_M1_A8 ) - ( 5 /DDR_Banks/M1_A8 ) + ( 5 /FPGA_Spartan6/M1_A8 ) ( 6 /FPGA_Spartan6/M1_A9 ) ( 7 /FPGA_Spartan6/M1_A11 ) - ( 8 /FPGA_Spartan6/M1_A12 ) + ( 8 /DDR_Banks/M1_A12 ) ) ( /4C431A63/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A7 ) ( 2 /FPGA_Spartan6/R_M1_A6 ) ( 3 /FPGA_Spartan6/R_M1_A5 ) ( 4 ? ) - ( 5 /FPGA_Spartan6/M1_A4 ) - ( 6 /DDR_Banks/M1_A5 ) + ( 5 /DDR_Banks/M1_A4 ) + ( 6 /FPGA_Spartan6/M1_A5 ) ( 7 /FPGA_Spartan6/M1_A6 ) - ( 8 /DDR_Banks/M1_A7 ) + ( 8 /FPGA_Spartan6/M1_A7 ) ) ( /4C431A63/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ0 ) @@ -336,9 +386,9 @@ ( 3 /FPGA_Spartan6/R_M1_DQ2 ) ( 4 /FPGA_Spartan6/R_M1_DQ3 ) ( 5 /FPGA_Spartan6/M1_DQ3 ) - ( 6 /FPGA_Spartan6/M1_DQ2 ) - ( 7 /FPGA_Spartan6/M1_DQ1 ) - ( 8 /FPGA_Spartan6/M1_DQ0 ) + ( 6 /DDR_Banks/M1_DQ2 ) + ( 7 /DDR_Banks/M1_DQ1 ) + ( 8 /DDR_Banks/M1_DQ0 ) ) ( /4C431A63/4C69D3A4 $noname RP3 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_LDQS ) @@ -355,9 +405,9 @@ ( 2 /FPGA_Spartan6/R_M1_DQ5 ) ( 3 /FPGA_Spartan6/R_M1_DQ6 ) ( 4 /FPGA_Spartan6/R_M1_DQ7 ) - ( 5 /DDR_Banks/M1_DQ7 ) + ( 5 /FPGA_Spartan6/M1_DQ7 ) ( 6 /FPGA_Spartan6/M1_DQ6 ) - ( 7 /FPGA_Spartan6/M1_DQ5 ) + ( 7 /DDR_Banks/M1_DQ5 ) ( 8 /FPGA_Spartan6/M1_DQ4 ) ) ( /4C431A63/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4} @@ -366,9 +416,9 @@ ( 3 /FPGA_Spartan6/R_M1_BA1 ) ( 4 /FPGA_Spartan6/R_M1_A10 ) ( 5 /FPGA_Spartan6/M1_A10 ) - ( 6 /DDR_Banks/M1_BA1 ) + ( 6 /FPGA_Spartan6/M1_BA1 ) ( 7 /DDR_Banks/M1_BA0 ) - ( 8 /FPGA_Spartan6/M1_RAS# ) + ( 8 /DDR_Banks/M1_RAS# ) ) ( /4C431A63/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A0 ) @@ -377,7 +427,7 @@ ( 4 /FPGA_Spartan6/R_M1_A3 ) ( 5 /FPGA_Spartan6/M1_A3 ) ( 6 /FPGA_Spartan6/M1_A2 ) - ( 7 /DDR_Banks/M1_A1 ) + ( 7 /FPGA_Spartan6/M1_A1 ) ( 8 /DDR_Banks/M1_A0 ) ) ( /4C431A63/4C656D9D $noname C66 470nF {Lib=C} @@ -518,9 +568,9 @@ ( N6 ? ) ( M6 ? ) ( L6 ? ) - ( K6 /FPGA_Spartan6/M0_A3 ) + ( K6 /FPGA_Spartan6/R_M0_A3 ) ( J6 ? ) - ( H6 /FPGA_Spartan6/M0_A7 ) + ( H6 /FPGA_Spartan6/R_M0_A7 ) ( G6 ? ) ( F6 +2.5V ) ( E6 ? ) @@ -530,7 +580,7 @@ ( M5 ? ) ( K5 /FPGA_Spartan6/M0_RAS# ) ( J5 +2.5V ) - ( H5 /FPGA_Spartan6/M0_A2 ) + ( H5 /FPGA_Spartan6/R_M0_A2 ) ( F5 ? ) ( E5 ? ) ( D5 ? ) @@ -554,7 +604,7 @@ ( L20 /FPGA_Spartan6/R_M1_LDQS ) ( K20 /FPGA_Spartan6/R_M1_A5 ) ( J20 /FPGA_Spartan6/R_M1_DQ4 ) - ( H20 /FPGA_Spartan6/M1_CLK ) + ( H20 /DDR_Banks/M1_CLK ) ( G20 /FPGA_Spartan6/R_M1_A3 ) ( F20 ? ) ( E20 /FPGA_Spartan6/R_M1_A7 ) @@ -568,16 +618,16 @@ ( Y2 ? ) ( W2 +2.5V ) ( V2 /FPGA_Spartan6/R_M0_DQ14 ) - ( T2 /DDR_Banks/M0_UDQS ) + ( T2 /FPGA_Spartan6/M0_UDQS ) ( R2 +2.5V ) ( P2 /FPGA_Spartan6/R_M0_DQ8 ) ( M2 /FPGA_Spartan6/R_M0_DQ2 ) ( L2 +2.5V ) ( K2 /FPGA_Spartan6/R_M0_DQ6 ) - ( H2 /DDR_Banks/M0_A0 ) + ( H2 /FPGA_Spartan6/R_M0_A0 ) ( G2 +2.5V ) - ( F2 /DDR_Banks/M0_WE# ) - ( D2 /DDR_Banks/M0_CKE ) + ( F2 /FPGA_Spartan6/M0_WE# ) + ( D2 /FPGA_Spartan6/M0_CKE ) ( C2 +2.5V ) ( B2 ? ) ( A2 ? ) @@ -593,18 +643,18 @@ ( L1 ? ) ( K1 /FPGA_Spartan6/R_M0_DQ7 ) ( J1 /FPGA_Spartan6/R_M0_DQ5 ) - ( H1 /FPGA_Spartan6/M0_A1 ) - ( G1 /DDR_Banks/M0_BA1 ) + ( H1 /FPGA_Spartan6/R_M0_A1 ) + ( G1 /FPGA_Spartan6/R_M0_BA1 ) ( T4 ? ) ( R4 ? ) ( P4 ? ) ( N4 ? ) ( M4 ? ) ( L4 /FPGA_Spartan6/M0_LDM ) - ( K4 /FPGA_Spartan6/M0_CAS# ) - ( J4 /FPGA_Spartan6/M0_A6 ) - ( H4 /DDR_Banks/M0_CLK ) - ( G4 /DDR_Banks/M0_A10 ) + ( K4 /DDR_Banks/M0_CAS# ) + ( J4 /FPGA_Spartan6/R_M0_A6 ) + ( H4 /FPGA_Spartan6/M0_CLK ) + ( G4 /FPGA_Spartan6/R_M0_A10 ) ( F4 +2.5V ) ( E4 ? ) ( C4 ? ) @@ -617,75 +667,75 @@ ( N3 /FPGA_Spartan6/R_M0_DQ0 ) ( M3 /FPGA_Spartan6/M0_UDM ) ( L3 /FPGA_Spartan6/M0_LDQS ) - ( K3 /FPGA_Spartan6/M0_A5 ) + ( K3 /FPGA_Spartan6/R_M0_A5 ) ( J3 /FPGA_Spartan6/R_M0_DQ4 ) - ( H3 /DDR_Banks/M0_CLK# ) - ( G3 /FPGA_Spartan6/M0_BA0 ) - ( F3 /FPGA_Spartan6/M0_A4 ) - ( E3 /FPGA_Spartan6/M0_A8 ) + ( H3 /FPGA_Spartan6/M0_CLK# ) + ( G3 /FPGA_Spartan6/R_M0_BA0 ) + ( F3 /FPGA_Spartan6/R_M0_A4 ) + ( E3 /FPGA_Spartan6/R_M0_A8 ) ( D3 ? ) ( C3 ? ) ( B3 ? ) ( G10 +3.3V ) ( D10 /FPGA_Spartan6/ETH_MDC ) ( C10 /FPGA_Spartan6/ETH_CRS ) - ( B10 /Ethernet_Phy/ETH_COL ) + ( B10 /FPGA_Spartan6/ETH_COL ) ( A10 /FPGA_Spartan6/ETH_INT ) ( E9 +3.3V ) ( D9 /FPGA_Spartan6/ETH_TXD0 ) ( C9 /FPGA_Spartan6/ETH_TXD2 ) ( A9 /Ethernet_Phy/ETH_TXD3 ) - ( D8 /Ethernet_Phy/ETH_RXC ) + ( D8 /FPGA_Spartan6/ETH_RXC ) ( C8 /FPGA_Spartan6/ETH_TXD1 ) - ( B8 /Ethernet_Phy/ETH_TXER ) - ( A8 /FPGA_Spartan6/ETH_TXEN ) - ( D7 /FPGA_Spartan6/ETH_TXC ) + ( B8 /FPGA_Spartan6/ETH_TXER ) + ( A8 /Ethernet_Phy/ETH_TXEN ) + ( D7 /Ethernet_Phy/ETH_TXC ) ( C7 /FPGA_Spartan6/ETH_RXDV ) ( B7 +3.3V ) - ( A7 /Ethernet_Phy/ETH_RXER ) - ( D6 /Ethernet_Phy/ETH_RXD3 ) - ( C6 /Ethernet_Phy/ETH_RXD2 ) + ( A7 /FPGA_Spartan6/ETH_RXER ) + ( D6 /FPGA_Spartan6/ETH_RXD3 ) + ( C6 /FPGA_Spartan6/ETH_RXD2 ) ( B6 /Ethernet_Phy/ETH_RXD1 ) ( A6 /Ethernet_Phy/ETH_RXD0 ) ( C5 /FPGA_Spartan6/ETH_MDIO ) ( A5 /FPGA_Spartan6/ETH_RESET_N ) ( B4 +3.3V ) - ( A4 /FPGA_Spartan6/ETH_CLK ) + ( A4 /Ethernet_Phy/ETH_CLK ) ( A3 ? ) ( U19 ? ) ( T19 ? ) - ( R19 /USB/USBA_SPD ) + ( R19 /FPGA_Spartan6/USBA_SPD ) ( P19 ? ) ( B19 +3.3V ) ( B18 /Non_volatile_memories/SD_DAT1 ) - ( A18 /Non_volatile_memories/SD_DAT0 ) + ( A18 /FPGA_Spartan6/SD_DAT0 ) ( E17 +3.3V ) ( D17 /Non_volatile_memories/SD_CMD ) ( C17 /FPGA_Spartan6/SD_DAT3 ) ( A17 /Non_volatile_memories/SD_DAT2 ) ( E16 /Non_volatile_memories/SD_CLK ) - ( C16 /FPGA_Spartan6/NF_CS1_N ) + ( C16 /Non_volatile_memories/NF_CS1_N ) ( B16 /FPGA_Spartan6/NF_RE_N ) ( A16 /FPGA_Spartan6/NF_RNB ) - ( D15 /FPGA_Spartan6/NF_CLE ) + ( D15 /Non_volatile_memories/NF_CLE ) ( C15 /FPGA_Spartan6/NF_WE_N ) ( B15 +3.3V ) - ( A15 /Non_volatile_memories/NF_ALE ) + ( A15 /FPGA_Spartan6/NF_ALE ) ( G14 +3.3V ) - ( D14 /Non_volatile_memories/NF_D0 ) + ( D14 /FPGA_Spartan6/NF_D0 ) ( C14 ? ) ( B14 ? ) ( A14 ? ) ( E13 +3.3V ) - ( C13 /FPGA_Spartan6/NF_D2 ) - ( A13 /FPGA_Spartan6/NF_D1 ) - ( C12 /FPGA_Spartan6/NF_D5 ) - ( B12 /Non_volatile_memories/NF_D4 ) + ( C13 /Non_volatile_memories/NF_D2 ) + ( A13 /Non_volatile_memories/NF_D1 ) + ( C12 /Non_volatile_memories/NF_D5 ) + ( B12 /FPGA_Spartan6/NF_D4 ) ( A12 /Non_volatile_memories/NF_D3 ) - ( D11 /Non_volatile_memories/NF_D6 ) + ( D11 /FPGA_Spartan6/NF_D6 ) ( C11 ? ) ( B11 +3.3V ) - ( A11 /FPGA_Spartan6/NF_D7 ) + ( A11 /Non_volatile_memories/NF_D7 ) ( J16 ? ) ( H16 /FPGA_Spartan6/R_M1_CS# ) ( G16 ? ) @@ -728,7 +778,7 @@ ( D19 ? ) ( C19 ? ) ( U18 +2.5V ) - ( P18 /USB/USBA_OE_N ) + ( P18 /FPGA_Spartan6/USBA_OE_N ) ( N18 +2.5V ) ( M18 /USB/USBA_VM ) ( K18 ? ) @@ -899,9 +949,9 @@ ( AB4 ? ) ( AA4 ? ) ( F1 ? ) - ( E1 /FPGA_Spartan6/M0_A9 ) - ( D1 /FPGA_Spartan6/M0_A12 ) - ( C1 /FPGA_Spartan6/M0_A11 ) + ( E1 /FPGA_Spartan6/R_M0_A9 ) + ( D1 /FPGA_Spartan6/R_M0_A12 ) + ( C1 /FPGA_Spartan6/R_M0_A11 ) ( B1 ? ) ( AB19 ? ) ( AA19 VCCO2 ) @@ -1043,7 +1093,7 @@ ( 2 +3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000374 ) + ( 1 N-000394 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} @@ -1055,35 +1105,35 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000392 ) + ( 1 N-000412 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000392 ) + ( 1 N-000412 ) ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} ( 1 /FPGA_Spartan6/ETH_MDIO ) ( 2 /FPGA_Spartan6/ETH_MDC ) - ( 3 /Ethernet_Phy/ETH_RXD3 ) - ( 4 /Ethernet_Phy/ETH_RXD2 ) + ( 3 /FPGA_Spartan6/ETH_RXD3 ) + ( 4 /FPGA_Spartan6/ETH_RXD2 ) ( 5 /Ethernet_Phy/ETH_RXD1 ) ( 6 /Ethernet_Phy/ETH_RXD0 ) ( 7 +3.3V ) ( 8 GND ) ( 9 /FPGA_Spartan6/ETH_RXDV ) - ( 10 /Ethernet_Phy/ETH_RXC ) - ( 11 /Ethernet_Phy/ETH_RXER ) + ( 10 /FPGA_Spartan6/ETH_RXC ) + ( 11 /FPGA_Spartan6/ETH_RXER ) ( 12 GND ) ( 13 +1.8V ) - ( 14 /Ethernet_Phy/ETH_TXER ) - ( 15 /FPGA_Spartan6/ETH_TXC ) - ( 16 /FPGA_Spartan6/ETH_TXEN ) + ( 14 /FPGA_Spartan6/ETH_TXER ) + ( 15 /Ethernet_Phy/ETH_TXC ) + ( 16 /Ethernet_Phy/ETH_TXEN ) ( 17 /FPGA_Spartan6/ETH_TXD0 ) ( 18 /FPGA_Spartan6/ETH_TXD1 ) ( 19 /FPGA_Spartan6/ETH_TXD2 ) ( 20 /Ethernet_Phy/ETH_TXD3 ) - ( 21 /Ethernet_Phy/ETH_COL ) + ( 21 /FPGA_Spartan6/ETH_COL ) ( 22 /FPGA_Spartan6/ETH_CRS ) ( 23 GND ) ( 24 +3.3V ) @@ -1094,78 +1144,78 @@ ( 29 ? ) ( 30 ? ) ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000389 ) - ( 33 N-000387 ) + ( 32 N-000409 ) + ( 33 N-000407 ) ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000374 ) + ( 37 N-000394 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) - ( 40 N-000388 ) - ( 41 N-000386 ) + ( 40 N-000408 ) + ( 41 N-000406 ) ( 42 ? ) ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 /FPGA_Spartan6/ETH_CLK ) + ( 46 /Ethernet_Phy/ETH_CLK ) ( 47 /Ethernet_Phy/ETH_PLL1.8V ) ( 48 /FPGA_Spartan6/ETH_RESET_N ) ) ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000386 ) + ( 2 N-000406 ) ) ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000388 ) + ( 2 N-000408 ) ) ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000389 ) + ( 2 N-000409 ) ) ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000387 ) + ( 2 N-000407 ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000377 ) + ( 1 N-000397 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000390 ) + ( 1 N-000410 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000386 ) - ( 2 N-000388 ) + ( 1 N-000406 ) + ( 2 N-000408 ) ( 3 +3.3V ) ( 4 GND ) ( 5 GND ) ( 6 +3.3V ) - ( 7 N-000387 ) - ( 8 N-000389 ) + ( 7 N-000407 ) + ( 8 N-000409 ) ( 9 +3.3V ) - ( 10 N-000390 ) + ( 10 N-000410 ) ( 11 +3.3V ) - ( 12 N-000377 ) - ( 13 N-000392 ) - ( 14 N-000392 ) + ( 12 N-000397 ) + ( 13 N-000412 ) + ( 14 N-000412 ) ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /FPGA_Spartan6/M1_DQ0 ) + ( 2 /DDR_Banks/M1_DQ0 ) ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M1_DQ1 ) - ( 5 /FPGA_Spartan6/M1_DQ2 ) + ( 4 /DDR_Banks/M1_DQ1 ) + ( 5 /DDR_Banks/M1_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M1_DQ3 ) ( 8 /FPGA_Spartan6/M1_DQ4 ) ( 9 +2.5V ) - ( 10 /FPGA_Spartan6/M1_DQ5 ) + ( 10 /DDR_Banks/M1_DQ5 ) ( 11 /FPGA_Spartan6/M1_DQ6 ) ( 12 GND ) - ( 13 /DDR_Banks/M1_DQ7 ) + ( 13 /FPGA_Spartan6/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /DDR_Banks/M1_LDQS ) @@ -1175,30 +1225,30 @@ ( 20 /DDR_Banks/M1_LDM ) ( 21 /FPGA_Spartan6/M1_WE# ) ( 22 /DDR_Banks/M1_CAS# ) - ( 23 /FPGA_Spartan6/M1_RAS# ) - ( 24 /DDR_Banks/M1_CS# ) + ( 23 /DDR_Banks/M1_RAS# ) + ( 24 /FPGA_Spartan6/M1_CS# ) ( 25 ? ) ( 26 /DDR_Banks/M1_BA0 ) - ( 27 /DDR_Banks/M1_BA1 ) + ( 27 /FPGA_Spartan6/M1_BA1 ) ( 28 /FPGA_Spartan6/M1_A10 ) ( 29 /DDR_Banks/M1_A0 ) - ( 30 /DDR_Banks/M1_A1 ) + ( 30 /FPGA_Spartan6/M1_A1 ) ( 31 /FPGA_Spartan6/M1_A2 ) ( 32 /FPGA_Spartan6/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /FPGA_Spartan6/M1_A4 ) - ( 36 /DDR_Banks/M1_A5 ) + ( 35 /DDR_Banks/M1_A4 ) + ( 36 /FPGA_Spartan6/M1_A5 ) ( 37 /FPGA_Spartan6/M1_A6 ) - ( 38 /DDR_Banks/M1_A7 ) - ( 39 /DDR_Banks/M1_A8 ) + ( 38 /FPGA_Spartan6/M1_A7 ) + ( 39 /FPGA_Spartan6/M1_A8 ) ( 40 /FPGA_Spartan6/M1_A9 ) ( 41 /FPGA_Spartan6/M1_A11 ) - ( 42 /FPGA_Spartan6/M1_A12 ) + ( 42 /DDR_Banks/M1_A12 ) ( 43 ? ) ( 44 /DDR_Banks/M1_CLK# ) - ( 45 /DDR_Banks/M1_CKE ) - ( 46 /FPGA_Spartan6/M1_CLK ) + ( 45 /FPGA_Spartan6/M1_CKE ) + ( 46 /DDR_Banks/M1_CLK ) ( 47 /DDR_Banks/M1_UDM ) ( 48 GND ) ( 49 N-000058 ) @@ -1208,16 +1258,16 @@ ( 53 ? ) ( 54 /FPGA_Spartan6/M1_DQ8 ) ( 55 +2.5V ) - ( 56 /DDR_Banks/M1_DQ9 ) - ( 57 /DDR_Banks/M1_DQ10 ) + ( 56 /FPGA_Spartan6/M1_DQ9 ) + ( 57 /FPGA_Spartan6/M1_DQ10 ) ( 58 GND ) - ( 59 /DDR_Banks/M1_DQ11 ) + ( 59 /FPGA_Spartan6/M1_DQ11 ) ( 60 /FPGA_Spartan6/M1_DQ12 ) ( 61 +2.5V ) ( 62 /FPGA_Spartan6/M1_DQ13 ) - ( 63 /FPGA_Spartan6/M1_DQ14 ) + ( 63 /DDR_Banks/M1_DQ14 ) ( 64 GND ) - ( 65 /FPGA_Spartan6/M1_DQ15 ) + ( 65 /DDR_Banks/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} @@ -1320,16 +1370,16 @@ ( 1 +2.5V ) ( 2 /DDR_Banks/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /DDR_Banks/M0_DQ1 ) - ( 5 /DDR_Banks/M0_DQ2 ) + ( 4 /FPGA_Spartan6/M0_DQ1 ) + ( 5 /FPGA_Spartan6/M0_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M0_DQ3 ) - ( 8 /DDR_Banks/M0_DQ4 ) + ( 8 /FPGA_Spartan6/M0_DQ4 ) ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M0_DQ5 ) - ( 11 /DDR_Banks/M0_DQ6 ) + ( 11 /FPGA_Spartan6/M0_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Spartan6/M0_DQ7 ) + ( 13 /DDR_Banks/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /FPGA_Spartan6/M0_LDQS ) @@ -1337,49 +1387,49 @@ ( 18 +2.5V ) ( 19 ? ) ( 20 /FPGA_Spartan6/M0_LDM ) - ( 21 /DDR_Banks/M0_WE# ) - ( 22 /FPGA_Spartan6/M0_CAS# ) + ( 21 /FPGA_Spartan6/M0_WE# ) + ( 22 /DDR_Banks/M0_CAS# ) ( 23 /FPGA_Spartan6/M0_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 /FPGA_Spartan6/M0_BA0 ) - ( 27 /DDR_Banks/M0_BA1 ) - ( 28 /DDR_Banks/M0_A10 ) - ( 29 /DDR_Banks/M0_A0 ) + ( 26 /DDR_Banks/M0_BA0 ) + ( 27 /FPGA_Spartan6/M0_BA1 ) + ( 28 /FPGA_Spartan6/M0_A10 ) + ( 29 /FPGA_Spartan6/M0_A0 ) ( 30 /FPGA_Spartan6/M0_A1 ) ( 31 /FPGA_Spartan6/M0_A2 ) - ( 32 /FPGA_Spartan6/M0_A3 ) + ( 32 /DDR_Banks/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /FPGA_Spartan6/M0_A4 ) + ( 35 /DDR_Banks/M0_A4 ) ( 36 /FPGA_Spartan6/M0_A5 ) ( 37 /FPGA_Spartan6/M0_A6 ) - ( 38 /FPGA_Spartan6/M0_A7 ) + ( 38 /DDR_Banks/M0_A7 ) ( 39 /FPGA_Spartan6/M0_A8 ) ( 40 /FPGA_Spartan6/M0_A9 ) - ( 41 /FPGA_Spartan6/M0_A11 ) - ( 42 /FPGA_Spartan6/M0_A12 ) + ( 41 /DDR_Banks/M0_A11 ) + ( 42 /DDR_Banks/M0_A12 ) ( 43 ? ) - ( 44 /DDR_Banks/M0_CLK# ) - ( 45 /DDR_Banks/M0_CKE ) - ( 46 /DDR_Banks/M0_CLK ) + ( 44 /FPGA_Spartan6/M0_CLK# ) + ( 45 /FPGA_Spartan6/M0_CKE ) + ( 46 /FPGA_Spartan6/M0_CLK ) ( 47 /FPGA_Spartan6/M0_UDM ) ( 48 GND ) ( 49 N-000059 ) ( 50 ? ) - ( 51 /DDR_Banks/M0_UDQS ) + ( 51 /FPGA_Spartan6/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M0_DQ8 ) + ( 54 /FPGA_Spartan6/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /DDR_Banks/M0_DQ9 ) - ( 57 /DDR_Banks/M0_DQ10 ) + ( 56 /FPGA_Spartan6/M0_DQ9 ) + ( 57 /FPGA_Spartan6/M0_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M0_DQ11 ) ( 60 /DDR_Banks/M0_DQ12 ) ( 61 +2.5V ) - ( 62 /FPGA_Spartan6/M0_DQ13 ) - ( 63 /DDR_Banks/M0_DQ14 ) + ( 62 /DDR_Banks/M0_DQ13 ) + ( 63 /FPGA_Spartan6/M0_DQ14 ) ( 64 GND ) ( 65 /FPGA_Spartan6/M0_DQ15 ) ( 66 GND ) @@ -1886,328 +1936,333 @@ $endfootprintlist } { Pin List by Nets Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" - U1 T5 U8 1 + U1 T5 Net 2 "/FPGA Spartan6/NF_RE_N" "NF_RE_N" U5 8 U1 B16 -Net 3 "/FPGA Spartan6/NF_CS1_N" "NF_CS1_N" - U1 C16 +Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" U5 9 -Net 4 "/Non volatile memories/NF_ALE" "NF_ALE" - U5 17 + U1 C16 +Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE" U1 A15 -Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" - U4 15 + U5 17 +Net 5 "/Ethernet Phy/ETH_TXC" "ETH_TXC" U1 D7 -Net 6 "/Ethernet Phy/ETH_RXC" "ETH_RXC" - U4 10 + U4 15 +Net 6 "/FPGA Spartan6/ETH_RXC" "ETH_RXC" U1 D8 -Net 7 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" + U4 10 +Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK" U1 A4 U4 46 -Net 8 "/USB/USBA_SPD" "USBA_SPD" +Net 8 "/FPGA Spartan6/USBA_SPD" "USBA_SPD" U1 R19 U6 2 -Net 9 "/USB/USBA_OE_N" "USBA_OE_N" +Net 9 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" U6 9 U1 P18 Net 10 "/USB/USBA_RCV" "USBA_RCV" U6 3 U1 N16 Net 11 "/FPGA Spartan6/USBA_VP" "USBA_VP" - U6 4 U1 P17 + U6 4 Net 12 "/USB/USBA_VM" "USBA_VM" - U6 5 U1 M18 -Net 13 "/Ethernet Phy/ETH_COL" "ETH_COL" - U1 B10 + U6 5 +Net 13 "/FPGA Spartan6/ETH_COL" "ETH_COL" U4 21 + U1 B10 Net 14 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" U1 C10 U4 22 Net 15 "/Non volatile memories/SD_CLK" "SD_CLK" - J1 5 U1 E16 + J1 5 Net 16 "/FPGA Spartan6/ETH_INT" "ETH_INT" - U1 A10 U4 25 + U1 A10 Net 17 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" - U4 2 U1 D10 + U4 2 Net 18 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" + U4 1 R1 1 U1 C5 - U4 1 Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" - U1 A5 U4 48 + U1 A5 Net 20 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" - U1 C7 U4 9 -Net 21 "/Ethernet Phy/ETH_RXER" "ETH_RXER" + U1 C7 +Net 21 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" U1 A7 U4 11 -Net 22 "/Ethernet Phy/ETH_TXER" "ETH_TXER" - U4 14 +Net 22 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" U1 B8 -Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" + U4 14 +Net 23 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" U1 A8 U4 16 -Net 24 "/DDR Banks/M1_CS#" "M1_CS#" +Net 24 "/FPGA Spartan6/M1_CS#" "M1_CS#" U3 24 R20 2 Net 25 "/DDR Banks/M1_UDM" "M1_UDM" - R18 2 U3 47 + R18 2 Net 26 "/DDR Banks/M1_LDQS" "M1_LDQS" RP3 8 U3 16 Net 27 "/DDR Banks/M1_LDM" "M1_LDM" - U3 20 RP3 7 + U3 20 Net 28 "/DDR Banks/M1_UDQS" "M1_UDQS" R19 2 U3 51 -Net 29 "/DDR Banks/M0_UDQS" "M0_UDQS" +Net 29 "/FPGA Spartan6/M0_UDQS" "M0_UDQS" U1 T2 U2 51 Net 30 "/FPGA Spartan6/M0_LDM" "M0_LDM" U1 L4 + RP16 7 U2 20 Net 31 "/DDR Banks/M1_CAS#" "M1_CAS#" U3 22 RP3 5 -Net 32 "/DDR Banks/M1_CKE" "M1_CKE" - R17 2 +Net 32 "/FPGA Spartan6/M1_CKE" "M1_CKE" U3 45 -Net 33 "/FPGA Spartan6/M1_CLK" "M1_CLK" + R17 2 +Net 33 "/DDR Banks/M1_CLK" "M1_CLK" U1 H20 - R16 2 U3 46 + R16 2 Net 34 "/DDR Banks/M1_CLK#" "M1_CLK#" U3 44 - R16 1 U1 J19 + R16 1 Net 35 "GND" "GND" C32 2 - U4 36 - U4 35 - C27 2 - U4 44 - C29 2 - C5 2 - C3 2 - C1 2 - C31 2 - U4 23 - C30 2 - C6 2 - C9 2 - C2 2 U2 48 + C27 2 U2 58 - C4 2 - C8 2 - C7 2 - U4 8 - U4 12 - U1 L11 - U1 N11 - C57 2 - U1 E21 - U1 J21 - U1 N21 - U1 U21 - U1 AB1 - U1 B9 - U1 J9 - C54 2 - U1 L9 - U1 P10 - C69 2 - U1 M10 - U1 K10 + C23 2 + C22 2 + C33 2 + C28 2 + C29 2 + C31 2 + C30 2 + U1 L13 U5 13 - C67 2 - U1 N9 - C75 1 - U1 E7 - J1 6 - U1 H7 - U1 U7 - U1 W7 - C61 2 - C64 2 - C66 2 - C63 2 - U1 V10 - U1 E11 - U1 J11 - C60 2 - C41 2 - C74 2 - C40 2 - C43 2 - C52 2 - C46 2 - U5 36 - C49 2 - C51 2 - U8 4 - C53 2 - C62 2 - C59 2 - C73 2 - C72 2 - C56 2 - C50 2 - C47 2 - C44 2 - C39 2 - U2 34 - U2 24 - C42 2 - C45 2 - C48 2 - U2 52 - U2 12 + U1 N13 U1 K14 U1 M14 - U2 66 - C65 2 U1 P14 U1 V14 U1 E15 - U2 64 U1 J15 - C18 2 U1 AA5 - C20 2 - U1 W16 - U1 B17 - C28 2 - C33 2 - C22 2 - C23 2 - C25 2 - C24 2 - C26 2 - C21 2 - C34 2 - C71 2 - C70 2 - U1 AB22 - U1 AA13 - U1 AA17 - U1 A1 - U1 E2 - U1 J2 U1 N2 U1 U2 U1 D4 U1 V4 U1 B5 U1 G5 - J1 CASE - J1 CASE - J1 CASE - J1 COM U1 L5 U1 R5 + U1 E7 + U1 H7 + U5 36 + U1 U7 + U1 P10 + U1 V10 + U1 E11 + U1 J11 + U1 L11 + U1 N11 + U1 W16 + U1 B17 U1 N17 U1 D18 - R12 2 - U1 K12 - U1 M12 - C68 2 - U1 P12 - R14 2 - U1 A22 - U1 B13 - U1 J13 - U1 L13 - C55 2 - U1 N13 - C58 2 U1 G18 U1 L18 U1 R18 U1 W19 U1 AA9 + U1 AB22 + U1 AA13 + U1 AA17 + U1 W7 + U1 B9 + U1 J9 + U1 J2 + U1 E2 + U1 A1 + C75 1 + C74 2 + U8 4 + C73 2 + C72 2 + C34 2 + C71 2 + C70 2 + C25 2 + C24 2 + C26 2 + C21 2 + J1 CASE + J1 CASE + J1 CASE + J1 COM + J1 6 + U1 E21 + U1 J21 + U1 N21 + U1 U21 + U1 AB1 + U1 K12 + U1 M12 + U1 P12 + U1 A22 + U1 B13 + U1 J13 + U1 L9 + U1 N9 + U1 K10 + U1 M10 + U2 34 + U2 24 + U2 52 + U2 12 + U2 66 + U2 64 + C18 2 + C20 2 + R12 2 + R14 2 U2 6 + C48 2 + C45 2 + C42 2 + C39 2 + J4 4 + U4 39 + R2 2 + C11 2 + C10 2 + C12 2 + R9 2 + C4 2 + C2 2 + C8 2 + C7 2 + C5 2 + C3 2 + C1 2 + J4 5 + C9 2 + C6 2 + U3 64 + U4 23 + U4 36 + U4 35 + U4 44 + U4 8 + U4 12 + V1 2 + C16 2 + R10 2 + U9 PAD + U9 8 + L7 2 + R15 2 + C38 2 V3 2 V4 2 C37 2 C36 2 C35 2 - L7 2 - R15 2 - C38 2 - U9 PAD - U9 8 + L5 2 + U6 8 + U6 7 C13 2 C14 2 C15 2 V2 2 U7 8 U7 7 - V1 2 - C16 2 - R10 2 - L5 2 - U6 8 - U6 7 - U4 39 - J4 5 - J4 4 - R2 2 - C11 2 - C10 2 - C12 2 - R9 2 - U3 66 - U3 12 - U3 64 + C58 2 + C61 2 + C64 2 + C56 2 + C59 2 + C62 2 + U3 6 + C40 2 + C43 2 + C52 2 + C46 2 + C49 2 + C51 2 + C53 2 + C67 2 + C69 2 + C54 2 + C57 2 U3 34 U3 52 U3 58 U3 48 - U3 6 -Net 36 "/DDR Banks/M0_CLK#" "M0_CLK#" - U1 H3 + U3 66 + U3 12 + C41 2 + C44 2 + C47 2 + C50 2 + C55 2 + C60 2 + C68 2 + C63 2 + C66 2 + C65 2 +Net 36 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" U2 44 -Net 37 "/DDR Banks/M0_CLK" "M0_CLK" + U1 H3 +Net 37 "/FPGA Spartan6/M0_CLK" "M0_CLK" U2 46 U1 H4 -Net 38 "/DDR Banks/M0_CKE" "M0_CKE" - U1 D2 +Net 38 "/FPGA Spartan6/M0_CKE" "M0_CKE" U2 45 -Net 39 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" - U1 K4 + U1 D2 +Net 39 "/DDR Banks/M0_CAS#" "M0_CAS#" + RP16 5 U2 22 + U1 K4 Net 40 "/FPGA Spartan6/M1_WE#" "M1_WE#" - RP3 6 U3 21 -Net 41 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" - U3 23 + RP3 6 +Net 41 "/DDR Banks/M1_RAS#" "M1_RAS#" RP2 8 + U3 23 Net 42 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" - U2 23 U1 K5 -Net 43 "/DDR Banks/M0_WE#" "M0_WE#" - U2 21 + U2 23 + RP15 8 +Net 43 "/FPGA Spartan6/M0_WE#" "M0_WE#" U1 F2 + RP16 6 + U2 21 Net 44 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" + RP16 8 U2 16 U1 L3 Net 45 "/FPGA Spartan6/M0_UDM" "M0_UDM" U1 M3 U2 47 Net 46 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" - U1 AA21 U8 6 + U1 AA21 Net 47 "/FPGA Spartan6/NF_RNB" "NF_RNB" U1 A16 U5 6 @@ -2215,729 +2270,774 @@ Net 47 "/FPGA Spartan6/NF_RNB" "NF_RNB" Net 48 "/FPGA Spartan6/NF_WE_N" "NF_WE_N" U5 18 U1 C15 -Net 49 "/FPGA Spartan6/NF_CLE" "NF_CLE" - U5 16 +Net 49 "/Non volatile memories/NF_CLE" "NF_CLE" U1 D15 + U5 16 Net 50 "/Non volatile memories/SD_CMD" "SD_CMD" - J1 3 U1 D17 + J1 3 Net 56 "+2.5V" "+2.5V" - U1 C2 - U1 L16 - U1 J18 - U1 G21 - U1 L21 - U1 R21 + C21 1 C33 1 C22 1 C23 1 C25 1 C24 1 C26 1 - C21 1 - C34 1 - C71 1 - C70 1 - U2 33 - U2 61 - U2 18 - U1 W21 - U1 N18 - U1 U18 - U1 E19 - C27 1 - C32 1 - C30 1 - C31 1 - C29 1 C28 1 - C37 1 - U3 33 - U3 15 + C29 1 + C31 1 + C30 1 + C32 1 + C27 1 + U2 9 + R13 1 + U1 E19 + U1 U18 + U1 N18 + U1 J18 + R11 1 + C19 1 + C17 1 + U1 W21 + U1 R21 + U1 L21 + U1 G21 U7 1 - C15 1 - U6 1 - U1 L7 + U2 1 + U2 3 + C37 1 + C70 1 + C71 1 + C34 1 + U1 C21 + U1 L16 + U2 15 + U2 55 + U2 18 + U2 61 + U2 33 U1 F6 U1 U5 U1 N5 - U1 C21 U1 J5 - U3 61 U1 F4 - U3 1 - U3 55 - U3 18 - U3 3 - U1 W2 - U1 R2 + U1 L7 U1 L2 U1 G2 - U3 9 - U1 N8 - U1 L8 - C54 1 - U1 G12 - U1 U11 - C49 1 - U1 D16 - C51 1 - C57 1 - U1 R6 - C19 1 - U1 V6 - R11 1 - C53 1 - U1 F11 - C62 1 - C60 1 + U1 C2 + U1 W2 + U1 R2 + U3 55 + U3 18 C59 1 - C63 1 - C66 1 - C56 1 - U2 55 - U2 3 - C65 1 - R13 1 - U2 15 - U2 1 - C68 1 - U2 9 - U1 H15 - C17 1 - U1 K15 - U1 M15 + C57 1 + U3 9 + C54 1 + C51 1 + C49 1 C46 1 - U1 H9 - U1 R10 - U1 R12 C52 1 + U3 3 C43 1 C40 1 + U3 1 + C53 1 + U3 61 + C68 1 + C65 1 + C62 1 + C66 1 + C63 1 + C56 1 + C60 1 + U3 15 + U3 33 + U1 L8 + U1 G12 + U1 F11 + C15 1 + U1 N8 + U1 D16 + U1 H9 + U6 1 + U1 R10 + U1 H15 + U1 U11 + U1 V6 + U1 M15 + U1 R6 + U1 R12 + U1 K15 Net 58 "" "" - R13 2 - R14 1 U3 49 - C20 1 + R14 1 + R13 2 C19 2 + C20 1 Net 59 "" "" - C18 1 - C17 2 U2 49 - R11 2 + C17 2 R12 1 + R11 2 + C18 1 Net 98 "+3.3V" "+3.3V" - U1 E17 - U1 B19 - L2 1 + R3 1 + U1 E13 + R4 1 + U1 G14 + U1 B15 + R6 1 + R5 1 C5 1 C3 1 C1 1 - U6 14 - U6 12 - U7 12 - U1 G14 - U1 B15 - C41 1 + C10 1 + U1 B19 + U1 E17 + C11 1 + L2 1 + U1 E9 + R1 2 + U1 B7 + U1 G10 + U1 B11 + U1 B4 U4 24 - C14 1 U4 7 - U1 E13 - U7 14 - U5 19 - U5 37 - C13 1 - J4 11 - C75 2 U5 12 - C74 1 - C35 1 C36 1 + C35 1 J1 4 - C73 1 - C72 1 + C74 1 + C75 2 C50 1 C47 1 C44 1 - C11 1 - C10 1 + C41 1 + U7 14 + U7 12 + C72 1 + C73 1 + C14 1 + C13 1 + U6 12 + U6 14 + J4 11 J4 9 J4 6 J4 3 - R5 1 - R6 1 - R4 1 - R3 1 - R1 2 - U1 B11 - U1 G10 - U1 E9 - U1 B7 - U1 B4 + U5 19 + U5 37 Net 99 "VCCO2" "VCCO2" - U1 AA19 - U1 V16 - C55 1 - U1 W5 - U1 AA7 - U1 T13 - U1 AA3 - C58 1 + U1 AA15 + U1 AA11 + U8 8 U1 T9 U1 V8 - C69 1 - C61 1 - U1 V12 - U1 AA11 - C67 1 + U1 AA3 + U1 T13 C64 1 - U1 AA15 - U8 8 -Net 168 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" - U1 R20 - RP9 2 -Net 169 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" - U1 U20 - RP8 4 -Net 170 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" - RP5 1 - U1 N20 -Net 171 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" - U1 K20 - RP6 3 -Net 172 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" - U1 V2 - RP10 3 -Net 173 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" - RP10 1 - U1 U3 -Net 174 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" - RP11 2 - U1 P1 -Net 175 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10" - RP11 3 - U1 R3 -Net 176 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" - RP13 1 - U1 N3 -Net 177 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" - U1 M2 - RP13 3 -Net 178 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" - U1 J3 - RP12 1 -Net 179 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" - RP12 2 - U1 J1 -Net 180 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" - RP12 3 - U1 K2 -Net 187 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" - U1 K19 - RP6 2 -Net 188 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" - RP2 4 - U1 G19 -Net 189 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" - U1 F19 - RP7 2 -Net 193 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" - RP9 3 - U1 P22 -Net 194 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" - U1 N22 - RP5 2 -Net 195 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" - RP5 4 - U1 M22 -Net 197 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" - RP4 4 - U1 K22 -Net 198 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" - RP4 2 - U1 J22 -Net 200 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" - RP1 2 - U1 F22 -Net 201 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" - U1 E22 - RP1 3 -Net 202 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" - RP7 1 - U1 D22 -Net 203 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" - RP7 3 - U1 C22 -Net 205 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" - U1 V21 - RP8 2 -Net 206 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" - U1 P21 - RP9 4 -Net 207 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" - U1 M21 - RP5 3 -Net 208 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" - RP4 3 - U1 K21 -Net 209 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" - RP1 1 - U1 F21 -Net 214 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" - RP2 3 - U1 K17 -Net 215 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" + C61 1 + C58 1 + U1 V12 + U1 AA19 + U1 V16 + U1 AA7 + C67 1 + C55 1 + C69 1 + U1 W5 +Net 105 "/FPGA Spartan6/R_M0_A4" "R_M0_A4" + RP17 4 + U1 F3 +Net 106 "/FPGA Spartan6/R_M0_A3" "R_M0_A3" + U1 K6 + RP14 4 +Net 142 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" RP2 2 U1 J17 -Net 226 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" - RP8 1 - U1 V22 -Net 227 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" - U1 U22 - RP8 3 -Net 229 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" - U1 R22 - RP9 1 -Net 230 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" - R18 1 - U1 M20 -Net 235 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" - RP3 1 - U1 L20 -Net 236 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" - RP3 2 - U1 L19 -Net 237 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" - RP3 3 - U1 H19 -Net 238 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" - R17 1 - U1 D21 -Net 261 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" - U1 V1 - RP10 4 -Net 262 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" - U1 U1 - RP10 2 -Net 264 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" - U1 R1 - RP11 4 -Net 265 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" - U1 N1 - RP13 2 -Net 266 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" - U1 M1 - RP13 4 -Net 268 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" - U1 K1 - RP12 4 -Net 337 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" - RP4 1 - U1 J20 -Net 338 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" - RP1 4 - U1 G20 -Net 340 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" - RP6 1 - U1 E20 -Net 342 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" - U1 C20 - RP7 4 -Net 352 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" - RP11 1 - U1 P2 -Net 367 "+1.2V" "+1.2V" - C48 1 +Net 143 "+1.2V" "+1.2V" U1 P9 + U1 N12 + U1 N10 + U1 J12 + U1 K9 + U1 L12 + U1 P11 + U1 J8 + U1 R14 + U1 M13 + C39 1 U1 J10 + U1 P13 + U1 K11 + U1 N14 + U1 J14 U1 L14 U1 L10 - U1 N14 U1 M11 - U1 R14 - U1 N10 - U1 J14 - U1 J12 - U1 L12 + C48 1 U1 M9 - U1 N12 - U1 K9 U1 K13 - U1 M13 - U1 P13 - U1 J8 - U1 P11 - C42 1 - C39 1 - U1 K11 C45 1 -Net 368 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" - RP2 1 - U1 H21 -Net 369 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" - RP3 4 - U1 H22 -Net 370 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" + C42 1 +Net 144 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" + RP12 3 + U1 K2 +Net 145 "/FPGA Spartan6/R_M0_A9" "R_M0_A9" + RP18 3 + U1 E1 +Net 146 "/FPGA Spartan6/R_M0_A11" "R_M0_A11" + U1 C1 + RP18 2 +Net 147 "/FPGA Spartan6/R_M0_A1" "R_M0_A1" + U1 H1 + RP14 2 +Net 148 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1" + RP15 3 + U1 G1 +Net 149 "/FPGA Spartan6/R_M0_A2" "R_M0_A2" + U1 H5 + RP14 3 +Net 150 "/FPGA Spartan6/R_M0_A5" "R_M0_A5" + RP17 3 + U1 K3 +Net 151 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" + RP10 3 + U1 V2 +Net 152 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" + U1 U3 + RP10 1 +Net 153 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" + U1 P1 + RP11 2 +Net 154 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10" + U1 R3 + RP11 3 +Net 155 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" + U1 N3 + RP13 1 +Net 156 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" + U1 M2 + RP13 3 +Net 157 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" + U1 J3 + RP12 1 +Net 158 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" + RP12 2 + U1 J1 +Net 159 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" + U1 K19 + RP6 2 +Net 160 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" + U1 H19 + RP3 3 +Net 161 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" + U1 G19 + RP2 4 +Net 162 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" + RP7 2 + U1 F19 +Net 179 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" + U1 V21 + RP8 2 +Net 180 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" + U1 P21 + RP9 4 +Net 181 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" + RP5 3 + U1 M21 +Net 182 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" + RP4 3 + U1 K21 +Net 183 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" + U1 F21 + RP1 1 +Net 184 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" + U1 D21 + R17 1 +Net 189 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" + RP8 4 + U1 U20 +Net 191 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" + RP9 2 + U1 R20 +Net 193 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" + U1 N20 + RP5 1 +Net 194 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" + RP6 3 + U1 K20 +Net 195 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" + RP4 1 + U1 J20 +Net 203 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" + RP8 1 + U1 V22 +Net 204 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" + RP8 3 + U1 U22 +Net 206 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" + U1 R22 + RP9 1 +Net 207 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" + RP9 3 + U1 P22 +Net 208 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" + U1 N22 + RP5 2 +Net 209 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" + RP5 4 + U1 M22 +Net 211 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" + RP4 4 + U1 K22 +Net 212 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" + U1 J22 + RP4 2 +Net 214 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" + RP1 2 + U1 F22 +Net 215 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" + U1 E22 + RP1 3 +Net 216 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" + RP7 1 + U1 D22 +Net 217 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" + RP7 3 + U1 C22 +Net 317 "/FPGA Spartan6/R_M0_A7" "R_M0_A7" + U1 H6 + RP17 1 +Net 331 "/FPGA Spartan6/R_M0_A6" "R_M0_A6" + U1 J4 + RP17 2 +Net 332 "/FPGA Spartan6/R_M0_A10" "R_M0_A10" + RP15 4 + U1 G4 +Net 333 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" + U1 G20 + RP1 4 +Net 335 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" + RP6 1 + U1 E20 +Net 337 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" + RP7 4 + U1 C20 +Net 356 "/FPGA Spartan6/R_M0_A0" "R_M0_A0" + U1 H2 + RP14 1 +Net 361 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" + RP10 4 + U1 V1 +Net 362 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" + RP10 2 + U1 U1 +Net 364 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" + U1 R1 + RP11 4 +Net 365 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" + U1 N1 + RP13 2 +Net 366 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" + RP13 4 + U1 M1 +Net 368 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" + RP12 4 + U1 K1 +Net 370 "/FPGA Spartan6/R_M0_A12" "R_M0_A12" + RP18 1 + U1 D1 +Net 377 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0" + U1 G3 + RP15 2 +Net 378 "/FPGA Spartan6/R_M0_A8" "R_M0_A8" + RP18 4 + U1 E3 +Net 383 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" + RP11 1 + U1 P2 +Net 384 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" + U1 L20 + RP3 1 +Net 385 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" + RP3 2 + U1 L19 +Net 386 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" + R20 1 + U1 H16 +Net 387 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" U1 T21 R19 1 -Net 371 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" - U1 H16 - R20 1 -Net 372 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - U4 47 +Net 388 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" + R18 1 + U1 M20 +Net 389 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" + RP2 1 + U1 H21 +Net 390 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" + U1 K17 + RP2 3 +Net 391 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" + U1 H22 + RP3 4 +Net 392 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" C9 1 + U4 47 L3 2 -Net 373 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - L2 2 - C8 1 - C7 1 +Net 393 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" U4 38 -Net 374 "" "" + L2 2 + C7 1 + C8 1 +Net 394 "" "" R2 1 U4 37 -Net 377 "" "" - R8 1 +Net 397 "" "" J4 12 -Net 378 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - R8 2 + R8 1 +Net 398 "/Ethernet Phy/ETH_LED1" "ETH_LED1" U4 27 -Net 381 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + R8 2 +Net 401 "/Ethernet Phy/ETH_LED0" "ETH_LED0" R7 2 U4 26 -Net 383 "+1.8V" "+1.8V" - L1 1 - U4 13 +Net 403 "+1.8V" "+1.8V" C4 1 + U4 13 + L1 1 C2 1 -Net 386 "" "" +Net 406 "" "" U4 41 J4 1 R3 2 -Net 387 "" "" +Net 407 "" "" + R5 2 J4 7 U4 33 - R5 2 -Net 388 "" "" - U4 40 +Net 408 "" "" R4 2 J4 2 -Net 389 "" "" - U4 32 + U4 40 +Net 409 "" "" R6 2 + U4 32 J4 8 -Net 390 "" "" +Net 410 "" "" J4 10 R7 1 -Net 391 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - L1 2 +Net 411 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" C6 1 L3 1 + L1 2 U4 31 -Net 392 "" "" - J4 13 - J4 14 +Net 412 "" "" C12 1 R9 1 -Net 399 "" "" + J4 14 + J4 13 +Net 419 "" "" + V2 1 V2 1 J5 2 - V2 1 U6 10 -Net 400 "" "" +Net 420 "" "" J5 4 L5 1 -Net 401 "" "" +Net 421 "" "" + C16 1 + J5 S4 + J5 S3 R10 1 J5 S1 J5 S2 - J5 S3 - J5 S4 - C16 1 -Net 402 "" "" +Net 422 "" "" F2 1 L6 1 -Net 404 "+5V" "+5V" +Net 424 "+5V" "+5V" F1 2 F2 2 -Net 405 "" "" +Net 425 "" "" F1 1 L4 1 -Net 406 "" "" - J5 1 +Net 426 "" "" L4 2 -Net 407 "" "" + J5 1 +Net 427 "" "" U6 11 + V1 1 J5 3 V1 1 - V1 1 -Net 408 "" "" +Net 428 "" "" + V4 1 V4 1 U7 10 - V4 1 -Net 409 "" "" +Net 429 "" "" V3 1 U7 11 V3 1 -Net 410 "" "" +Net 430 "" "" C38 1 R15 1 -Net 430 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" - U8 7 +Net 450 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" U1 U13 -Net 431 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" - U8 3 + U8 7 +Net 451 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" U1 U14 -Net 432 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" - U8 2 + U8 3 +Net 452 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" U1 AA20 -Net 433 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" + U8 2 +Net 453 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" U1 AB20 U8 5 -Net 434 "/FPGA Spartan6/NF_D7" "NF_D7" - U5 44 +Net 454 "/Non volatile memories/NF_D7" "NF_D7" U1 A11 -Net 435 "/Non volatile memories/NF_D6" "NF_D6" + U5 44 +Net 455 "/FPGA Spartan6/NF_D6" "NF_D6" U5 43 U1 D11 -Net 436 "/FPGA Spartan6/NF_D5" "NF_D5" +Net 456 "/Non volatile memories/NF_D5" "NF_D5" U5 42 U1 C12 -Net 437 "/Non volatile memories/NF_D4" "NF_D4" - U5 41 +Net 457 "/FPGA Spartan6/NF_D4" "NF_D4" U1 B12 -Net 438 "/Non volatile memories/NF_D3" "NF_D3" - U1 A12 + U5 41 +Net 458 "/Non volatile memories/NF_D3" "NF_D3" U5 32 -Net 439 "/FPGA Spartan6/NF_D2" "NF_D2" + U1 A12 +Net 459 "/Non volatile memories/NF_D2" "NF_D2" U1 C13 U5 31 -Net 440 "/FPGA Spartan6/NF_D1" "NF_D1" +Net 460 "/Non volatile memories/NF_D1" "NF_D1" U1 A13 U5 30 -Net 441 "/Non volatile memories/NF_D0" "NF_D0" - U5 29 +Net 461 "/FPGA Spartan6/NF_D0" "NF_D0" U1 D14 -Net 442 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" + U5 29 +Net 462 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" U1 A9 U4 20 -Net 443 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" - U1 C9 +Net 463 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" U4 19 -Net 444 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" + U1 C9 +Net 464 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" U1 C8 U4 18 -Net 445 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" +Net 465 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" U4 17 U1 D9 -Net 446 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" - U1 D6 +Net 466 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" U4 3 -Net 447 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" - U4 4 + U1 D6 +Net 467 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" U1 C6 -Net 448 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" + U4 4 +Net 468 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" U1 B6 U4 5 -Net 449 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" - U1 A6 +Net 469 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" U4 6 -Net 450 "/DDR Banks/M0_BA1" "M0_BA1" + U1 A6 +Net 470 "/FPGA Spartan6/M0_BA1" "M0_BA1" + RP15 6 U2 27 - U1 G1 -Net 451 "/FPGA Spartan6/M0_BA0" "M0_BA0" - U1 G3 +Net 471 "/DDR Banks/M0_BA0" "M0_BA0" U2 26 -Net 452 "/DDR Banks/M1_BA1" "M1_BA1" - U3 27 + RP15 7 +Net 472 "/FPGA Spartan6/M1_BA1" "M1_BA1" RP2 6 -Net 453 "/DDR Banks/M1_BA0" "M1_BA0" + U3 27 +Net 473 "/DDR Banks/M1_BA0" "M1_BA0" RP2 7 U3 26 -Net 454 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" +Net 474 "/DDR Banks/M1_DQ15" "M1_DQ15" RP8 8 U3 65 -Net 455 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" - RP8 7 +Net 475 "/DDR Banks/M1_DQ14" "M1_DQ14" U3 63 -Net 456 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" + RP8 7 +Net 476 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" U3 62 RP8 6 -Net 457 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" - RP8 5 +Net 477 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" U3 60 -Net 458 "/DDR Banks/M1_DQ11" "M1_DQ11" - U3 59 + RP8 5 +Net 478 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" RP9 8 -Net 459 "/DDR Banks/M1_DQ10" "M1_DQ10" + U3 59 +Net 479 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" U3 57 RP9 7 -Net 460 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" +Net 480 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" U1 C17 J1 2 -Net 461 "/Non volatile memories/SD_DAT2" "SD_DAT2" +Net 481 "/Non volatile memories/SD_DAT2" "SD_DAT2" U1 A17 J1 1 -Net 462 "/Non volatile memories/SD_DAT1" "SD_DAT1" +Net 482 "/Non volatile memories/SD_DAT1" "SD_DAT1" J1 8 U1 B18 -Net 463 "/Non volatile memories/SD_DAT0" "SD_DAT0" +Net 483 "/FPGA Spartan6/SD_DAT0" "SD_DAT0" U1 A18 J1 7 -Net 464 "/DDR Banks/M1_A7" "M1_A7" - U3 38 +Net 484 "/FPGA Spartan6/M1_A7" "M1_A7" RP6 8 -Net 465 "/FPGA Spartan6/M1_A6" "M1_A6" + U3 38 +Net 485 "/FPGA Spartan6/M1_A6" "M1_A6" RP6 7 U3 37 -Net 466 "/DDR Banks/M1_A5" "M1_A5" - RP6 6 +Net 486 "/FPGA Spartan6/M1_A5" "M1_A5" U3 36 -Net 467 "/FPGA Spartan6/M1_A4" "M1_A4" + RP6 6 +Net 487 "/DDR Banks/M1_A4" "M1_A4" U3 35 RP6 5 -Net 468 "/FPGA Spartan6/M1_A3" "M1_A3" - U3 32 +Net 488 "/FPGA Spartan6/M1_A3" "M1_A3" RP1 5 -Net 469 "/FPGA Spartan6/M1_A2" "M1_A2" + U3 32 +Net 489 "/FPGA Spartan6/M1_A2" "M1_A2" RP1 6 U3 31 -Net 470 "/DDR Banks/M1_A1" "M1_A1" - U3 30 +Net 490 "/FPGA Spartan6/M1_A1" "M1_A1" RP1 7 -Net 471 "/DDR Banks/M1_A0" "M1_A0" + U3 30 +Net 491 "/DDR Banks/M1_A0" "M1_A0" U3 29 RP1 8 -Net 472 "/FPGA Spartan6/M0_A12" "M0_A12" - U1 D1 +Net 492 "/DDR Banks/M0_A12" "M0_A12" U2 42 -Net 473 "/FPGA Spartan6/M0_A11" "M0_A11" + RP18 8 +Net 493 "/DDR Banks/M0_A11" "M0_A11" + RP18 7 U2 41 - U1 C1 -Net 474 "/DDR Banks/M0_A10" "M0_A10" +Net 494 "/FPGA Spartan6/M0_A10" "M0_A10" U2 28 - U1 G4 -Net 475 "/FPGA Spartan6/M0_A9" "M0_A9" - U1 E1 + RP15 5 +Net 495 "/FPGA Spartan6/M0_A9" "M0_A9" + RP18 6 U2 40 -Net 476 "/FPGA Spartan6/M0_A8" "M0_A8" - U1 E3 +Net 496 "/FPGA Spartan6/M0_A8" "M0_A8" U2 39 -Net 477 "/FPGA Spartan6/M0_A7" "M0_A7" - U1 H6 + RP18 5 +Net 497 "/DDR Banks/M0_A7" "M0_A7" + RP17 8 U2 38 -Net 478 "/DDR Banks/M1_DQ9" "M1_DQ9" +Net 498 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" U3 56 RP9 6 -Net 479 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" +Net 499 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" RP9 5 U3 54 -Net 480 "/DDR Banks/M1_DQ7" "M1_DQ7" - U3 13 +Net 500 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" RP4 5 -Net 481 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" - U3 11 + U3 13 +Net 501 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" RP4 6 -Net 482 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" + U3 11 +Net 502 "/DDR Banks/M1_DQ5" "M1_DQ5" U3 10 RP4 7 -Net 483 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" - U3 8 +Net 503 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" RP4 8 -Net 484 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" + U3 8 +Net 504 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" U3 7 RP5 5 -Net 485 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" +Net 505 "/DDR Banks/M1_DQ2" "M1_DQ2" U3 5 RP5 6 -Net 486 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" +Net 506 "/DDR Banks/M1_DQ1" "M1_DQ1" U3 4 RP5 7 -Net 487 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" - RP5 8 +Net 507 "/DDR Banks/M1_DQ0" "M1_DQ0" U3 2 -Net 488 "/FPGA Spartan6/M1_A12" "M1_A12" - RP7 8 + RP5 8 +Net 508 "/DDR Banks/M1_A12" "M1_A12" U3 42 -Net 489 "/FPGA Spartan6/M1_A11" "M1_A11" - RP7 7 + RP7 8 +Net 509 "/FPGA Spartan6/M1_A11" "M1_A11" U3 41 -Net 490 "/FPGA Spartan6/M1_A10" "M1_A10" + RP7 7 +Net 510 "/FPGA Spartan6/M1_A10" "M1_A10" RP2 5 U3 28 -Net 491 "/FPGA Spartan6/M1_A9" "M1_A9" +Net 511 "/FPGA Spartan6/M1_A9" "M1_A9" RP7 6 U3 40 -Net 492 "/DDR Banks/M1_A8" "M1_A8" +Net 512 "/FPGA Spartan6/M1_A8" "M1_A8" RP7 5 U3 39 -Net 493 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" - U2 7 +Net 513 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" RP13 5 -Net 494 "/DDR Banks/M0_DQ2" "M0_DQ2" - U2 5 + U2 7 +Net 514 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" RP13 6 -Net 495 "/DDR Banks/M0_DQ1" "M0_DQ1" + U2 5 +Net 515 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" RP13 7 U2 4 -Net 496 "/DDR Banks/M0_DQ0" "M0_DQ0" +Net 516 "/DDR Banks/M0_DQ0" "M0_DQ0" RP13 8 U2 2 -Net 497 "/FPGA Spartan6/M0_A6" "M0_A6" +Net 517 "/FPGA Spartan6/M0_A6" "M0_A6" U2 37 - U1 J4 -Net 498 "/FPGA Spartan6/M0_A5" "M0_A5" - U1 K3 + RP17 7 +Net 518 "/FPGA Spartan6/M0_A5" "M0_A5" U2 36 -Net 499 "/FPGA Spartan6/M0_A4" "M0_A4" - U1 F3 + RP17 6 +Net 519 "/DDR Banks/M0_A4" "M0_A4" + RP17 5 U2 35 -Net 500 "/FPGA Spartan6/M0_A3" "M0_A3" +Net 520 "/DDR Banks/M0_A3" "M0_A3" + RP14 5 U2 32 - U1 K6 -Net 501 "/FPGA Spartan6/M0_A2" "M0_A2" - U1 H5 +Net 521 "/FPGA Spartan6/M0_A2" "M0_A2" U2 31 -Net 502 "/FPGA Spartan6/M0_A1" "M0_A1" - U1 H1 + RP14 6 +Net 522 "/FPGA Spartan6/M0_A1" "M0_A1" + RP14 7 U2 30 -Net 503 "/DDR Banks/M0_A0" "M0_A0" +Net 523 "/FPGA Spartan6/M0_A0" "M0_A0" U2 29 - U1 H2 -Net 504 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" + RP14 8 +Net 524 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" U2 65 RP10 5 -Net 505 "/DDR Banks/M0_DQ14" "M0_DQ14" +Net 525 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" RP10 6 U2 63 -Net 506 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" +Net 526 "/DDR Banks/M0_DQ13" "M0_DQ13" U2 62 RP10 7 -Net 507 "/DDR Banks/M0_DQ12" "M0_DQ12" +Net 527 "/DDR Banks/M0_DQ12" "M0_DQ12" RP10 8 U2 60 -Net 508 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" +Net 528 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" RP11 5 U2 59 -Net 509 "/DDR Banks/M0_DQ10" "M0_DQ10" - RP11 6 +Net 529 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" U2 57 -Net 510 "/DDR Banks/M0_DQ9" "M0_DQ9" - U2 56 + RP11 6 +Net 530 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" RP11 7 -Net 511 "/DDR Banks/M0_DQ8" "M0_DQ8" - RP11 8 + U2 56 +Net 531 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" U2 54 -Net 512 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" + RP11 8 +Net 532 "/DDR Banks/M0_DQ7" "M0_DQ7" U2 13 RP12 5 -Net 513 "/DDR Banks/M0_DQ6" "M0_DQ6" - U2 11 +Net 533 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" RP12 6 -Net 514 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" - RP12 7 + U2 11 +Net 534 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" U2 10 -Net 515 "/DDR Banks/M0_DQ4" "M0_DQ4" - U2 8 + RP12 7 +Net 535 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" RP12 8 + U2 8 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 31f113f..7ab4dde 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Mon 16 Aug 2010 10:47:37 PM COT +update=Mon 16 Aug 2010 11:30:16 PM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index c7f7e9c..1fdd0b0 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 11:27:48 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03