Connecting some FPGA's free GPIO

kicad/modules/CON_40Pin_2mm.mod

@@ -0,0 +1,456 @@
+PCBNEW-LibModule-V1  Sat 08 May 2010 02:28:45 PM COT
+$INDEX
+CON_40Pin_2mm
+$EndINDEX
+$MODULE CON_40Pin_2mm
+Po 0 0 0 15 4BAADD91 4BE5BB49 ~~
+Li CON_40Pin_2mm
+Sc 4BE5BB49
+AR /4B8F5BC1/4B7C65CF
+Op 0 0 0
+T0 16146 242 315 315 900 31 N V 21 N"CON_40Pin_2mm"
+T1 0 118 118 118 -2700 20 N I 21 N"VAL"
+T2 16154 -830 315 315 900 31 N V 21 N"40"
+T2 -750 -822 315 315 900 31 N V 21 N"2"
+T2 -654 586 315 315 900 31 N V 21 N"1"
+DS 11120 -900 11120 100 40 26
+DS 11120 100 10920 100 40 26
+DS 10920 100 10920 -900 40 26
+DS 10340 -900 10340 100 40 26
+DS 10340 100 10140 100 40 26
+DS 10140 100 10140 -900 40 26
+DS 8760 -900 8760 100 40 26
+DS 8760 100 8560 100 40 26
+DS 8560 100 8560 -900 40 26
+DS 9550 -900 9550 100 40 26
+DS 9550 100 9350 100 40 26
+DS 9350 100 9350 -900 40 26
+DS 7970 -900 7970 100 40 26
+DS 7970 100 7770 100 40 26
+DS 7770 100 7770 -900 40 26
+DS 7190 -900 7190 100 40 26
+DS 7190 100 6990 100 40 26
+DS 6990 100 6990 -900 40 26
+DS 6400 -900 6400 100 40 26
+DS 6400 100 6200 100 40 26
+DS 6200 100 6200 -900 40 26
+DS 5610 -900 5610 100 40 26
+DS 5610 100 5410 100 40 26
+DS 5410 100 5410 -900 40 26
+DS 4820 -900 4820 100 40 26
+DS 4820 100 4620 100 40 26
+DS 4620 100 4620 -900 40 26
+DS 4040 -900 4040 100 40 26
+DS 4040 100 3840 100 40 26
+DS 3840 100 3840 -900 40 26
+DS -750 -250 -750 250 80 26
+DS -750 250 -500 0 80 26
+DS -500 0 -750 -250 80 26
+DS 13490 -900 13490 100 40 26
+DS 13490 100 13290 100 40 26
+DS 13290 100 13290 -900 40 26
+DS 11910 -900 11910 100 40 26
+DS 11910 100 11710 100 40 26
+DS 11710 100 11710 -900 40 26
+DS -750 -250 -750 250 80 21
+DS -750 250 -500 0 80 21
+DS -500 0 -750 -250 80 21
+DS -330 -790 -590 -790 60 26
+DS -590 -790 -590 -1460 60 26
+DS -590 -1460 15550 -1460 60 26
+DS 15550 -1460 15550 -790 60 26
+DS 15550 -790 15260 -790 60 26
+DS 15260 -790 15260 -900 60 26
+DS 15260 -900 14660 -900 60 26
+DS 14660 -900 14660 -790 60 26
+DS 14660 -790 14470 -790 60 26
+DS 14470 -790 14470 -900 60 26
+DS 14470 -900 13870 -900 60 26
+DS 13870 -900 13870 -790 60 26
+DS 13870 -790 13690 -790 60 26
+DS 13690 -790 13690 -900 60 26
+DS 13690 -900 13090 -900 60 26
+DS 13090 -900 13090 -790 60 26
+DS 13090 -790 12900 -790 60 26
+DS 12900 -790 12900 -900 60 26
+DS 12900 -900 12300 -900 60 26
+DS 12300 -900 12300 -790 60 26
+DS 12300 -790 12110 -790 60 26
+DS 12110 -790 12110 -900 60 26
+DS 12110 -900 11510 -900 60 26
+DS 11510 -900 11510 -790 60 26
+DS 11510 -790 11320 -790 60 26
+DS 11320 -790 11320 -900 60 26
+DS 11320 -900 10720 -900 60 26
+DS 10720 -900 10720 -790 60 26
+DS 10720 -790 10540 -790 60 26
+DS 10540 -790 10540 -900 60 26
+DS 10540 -900 9940 -900 60 26
+DS 9940 -900 9940 -790 60 26
+DS 9940 -790 9750 -790 60 26
+DS 9750 -790 9750 -900 60 26
+DS 9750 -900 9150 -900 60 26
+DS 9150 -900 9150 -790 60 26
+DS 9150 -790 8960 -790 60 26
+DS 8960 -790 8960 -900 60 26
+DS 8960 -900 8360 -900 60 26
+DS 8360 -900 8360 -790 60 26
+DS 8360 -790 8170 -790 60 26
+DS 8170 -790 8170 -900 60 26
+DS 8170 -900 7570 -900 60 26
+DS 7570 -900 7570 -790 60 26
+DS 7570 -790 7390 -790 60 26
+DS 7390 -790 7390 -900 60 26
+DS 7390 -900 6790 -900 60 26
+DS 6790 -900 6790 -790 60 26
+DS 6790 -790 6600 -790 60 26
+DS 6600 -790 6600 -900 60 26
+DS 6600 -900 6000 -900 60 26
+DS 6000 -900 6000 -790 60 26
+DS 6000 -790 5810 -790 60 26
+DS 5810 -790 5810 -900 60 26
+DS 5810 -900 5210 -900 60 26
+DS 5210 -900 5210 -790 60 26
+DS 5210 -790 5020 -790 60 26
+DS 5020 -790 5020 -900 60 26
+DS 5020 -900 4420 -900 60 26
+DS 4420 -900 4420 -790 60 26
+DS 4420 -790 4240 -790 60 26
+DS 4240 -790 4240 -900 60 26
+DS 4240 -900 3640 -900 60 26
+DS 3640 -900 3640 -790 60 26
+DS 3640 -790 3450 -790 60 26
+DS 3450 -790 3450 -900 60 26
+DS 3450 -900 2850 -900 60 26
+DS 2850 -900 2850 -790 60 26
+DS 2850 -790 2660 -790 60 26
+DS 2660 -790 2660 -900 60 26
+DS 2660 -900 2060 -900 60 26
+DS 2060 -900 2060 -790 60 26
+DS 2060 -790 1870 -790 60 26
+DS 1870 -790 1870 -900 60 26
+DS 1870 -900 1270 -900 60 26
+DS 1270 -900 1270 -790 60 26
+DS 1270 -790 1090 -790 60 26
+DS 1090 -790 1090 -900 60 26
+DS 1090 -900 490 -900 60 26
+DS 490 -900 490 -790 60 26
+DS 490 -790 300 -790 60 26
+DS 300 -790 300 -900 60 26
+DS 300 -900 -330 -900 60 26
+DS -330 -900 -330 -790 60 26
+DS 12700 -900 12700 100 40 26
+DS 12700 100 12500 100 40 26
+DS 12500 100 12500 -900 40 26
+DS 100 -900 100 100 40 26
+DS 100 100 -100 100 40 26
+DS -100 100 -100 -900 40 26
+DS 890 -900 890 100 40 26
+DS 890 100 690 100 40 26
+DS 690 100 690 -900 40 26
+DS 1680 -900 1680 100 40 26
+DS 1680 100 1480 100 40 26
+DS 1480 100 1480 -900 40 26
+DS 2470 -900 2470 100 40 26
+DS 2470 100 2270 100 40 26
+DS 2270 100 2270 -900 40 26
+DS 3250 -900 3250 100 40 26
+DS 3250 100 3050 100 40 26
+DS 3050 100 3050 -900 40 26
+DS 15060 -900 15060 100 40 26
+DS 15060 100 14860 100 40 26
+DS 14860 100 14860 -900 40 26
+DS -370 -1460 15820 -1460 80 21
+DS 15820 -1460 15820 560 80 21
+DS 15820 560 -380 560 80 21
+DS -380 560 -370 390 80 21
+DS -370 390 -370 -1450 80 21
+DS 14260 -900 14260 100 40 26
+DS 14260 100 14060 100 40 26
+DS 14060 100 14060 -900 40 26
+DS -900 710 -900 -1610 10 24
+DS -900 -1610 15970 -1610 10 24
+DS 15970 -1610 15970 710 10 24
+DS 15970 710 -900 710 10 24
+$PAD
+Sh "1" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 0 0
+$EndPAD
+$PAD
+Sh "2" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 0 -790
+$EndPAD
+$PAD
+Sh "3" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 790 0
+$EndPAD
+$PAD
+Sh "4" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 790 -790
+$EndPAD
+$PAD
+Sh "5" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 1570 0
+$EndPAD
+$PAD
+Sh "6" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 1570 -790
+$EndPAD
+$PAD
+Sh "7" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 2360 0
+$EndPAD
+$PAD
+Sh "8" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 2360 -790
+$EndPAD
+$PAD
+Sh "9" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 3150 0
+$EndPAD
+$PAD
+Sh "10" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 3150 -790
+$EndPAD
+$PAD
+Sh "11" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 3940 0
+$EndPAD
+$PAD
+Sh "12" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 3940 -790
+$EndPAD
+$PAD
+Sh "13" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 4720 0
+$EndPAD
+$PAD
+Sh "14" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 4720 -790
+$EndPAD
+$PAD
+Sh "15" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 5510 0
+$EndPAD
+$PAD
+Sh "16" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 5510 -790
+$EndPAD
+$PAD
+Sh "17" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 6300 0
+$EndPAD
+$PAD
+Sh "18" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 6300 -790
+$EndPAD
+$PAD
+Sh "19" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 7090 0
+$EndPAD
+$PAD
+Sh "20" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 7090 -790
+$EndPAD
+$PAD
+Sh "21" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 7870 0
+$EndPAD
+$PAD
+Sh "22" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 7870 -790
+$EndPAD
+$PAD
+Sh "23" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 8660 0
+$EndPAD
+$PAD
+Sh "24" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 8660 -790
+$EndPAD
+$PAD
+Sh "25" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 9450 0
+$EndPAD
+$PAD
+Sh "26" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 9450 -790
+$EndPAD
+$PAD
+Sh "27" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 10240 0
+$EndPAD
+$PAD
+Sh "28" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 10240 -790
+$EndPAD
+$PAD
+Sh "29" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 11020 0
+$EndPAD
+$PAD
+Sh "30" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 11020 -790
+$EndPAD
+$PAD
+Sh "31" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 11810 0
+$EndPAD
+$PAD
+Sh "32" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 11810 -790
+$EndPAD
+$PAD
+Sh "33" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 12600 0
+$EndPAD
+$PAD
+Sh "34" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 12600 -790
+$EndPAD
+$PAD
+Sh "35" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 13390 0
+$EndPAD
+$PAD
+Sh "36" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 13390 -790
+$EndPAD
+$PAD
+Sh "37" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 14170 0
+$EndPAD
+$PAD
+Sh "38" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 14170 -790
+$EndPAD
+$PAD
+Sh "39" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 14960 0
+$EndPAD
+$PAD
+Sh "40" C 520 520 0 0 0
+Dr 340 0 0
+At STD N 00C08001
+Ne 0 ""
+Po 14960 -790
+$EndPAD
+$EndMODULE  CON_40Pin_2mm
+$EndLIBRARY

kicad/xue-rnc/DBG_PRG.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
 $Descr A4 11700 8267
-Sheet 4 11
+Sheet 6 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""

kicad/xue-rnc/DRAM.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
 $Descr A4 11700 8267
-Sheet 9 11
+Sheet 9 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""

kicad/xue-rnc/FPGA_0_2_PROG.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
 $Descr A3 16535 11700
-Sheet 4 11
+Sheet 5 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""
@@ -63,6 +63,46 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
+Text HLabel 3200 3950 0    40   BiDi ~ 0
+FPGA_VCCO2_IO_AA18
+Text HLabel 3200 1650 0    40   BiDi ~ 0
+FPGA_VCCO2_IO_AB21
+Text HLabel 3200 2350 0    40   BiDi ~ 0
+FPGA_VCCO2_IO_W18
+Text HLabel 3200 5050 0    40   BiDi ~ 0
+FPGA_VCCO2_IO_AB16
+Text HLabel 3200 5450 0    40   BiDi ~ 0
+FPGA_VCCO2_IO_AB15
+Text HLabel 7200 4650 2    40   BiDi ~ 0
+FPGA_VCCO2_IO_V7
+Text HLabel 7200 3350 2    40   BiDi ~ 0
+FPGA_VCCO2_IO_W6
+Text HLabel 7200 2150 2    40   BiDi ~ 0
+FPGA_VCCO2_IO_W4
+Text HLabel 7200 5050 2    40   BiDi ~ 0
+FPGA_VCCO2_IO_Y10
+Text HLabel 7200 5350 2    40   BiDi ~ 0
+FPGA_VCCO2_IO_Y9
+Text HLabel 3200 5350 0    40   BiDi ~ 0
+FPGA_VCCO2_IO_Y15
+Text HLabel 3200 4550 0    40   BiDi ~ 0
+FPGA_VCCO2_IO_Y16
+Text HLabel 7200 5150 2    40   BiDi ~ 0
+FPGA_VCCO2_IO_W10
+Text HLabel 7200 5450 2    40   BiDi ~ 0
+FPGA_VCCO2_IO_W11
+Text HLabel 3200 6150 0    40   BiDi ~ 0
+FPGA_VCCO2_IO_Y12
+Text HLabel 3200 4450 0    40   BiDi ~ 0
+FPGA_VCCO2_IO_AB14
+Text HLabel 3200 6250 0    40   BiDi ~ 0
+FPGA_VCCO2_IO_AB13
+Text HLabel 7200 6150 2    40   BiDi ~ 0
+FPGA_VCCO2_IO_Y11
+Text HLabel 7200 4750 2    40   BiDi ~ 0
+FPGA_VCCO2_IO_W8
+Text HLabel 7200 3950 2    40   BiDi ~ 0
+FPGA_VCCO2_IO_U9
 Text HLabel 7200 1650 2    40   Input ~ 0
 IS_FRAME
 Text HLabel 7200 1750 2    40   Input ~ 0

kicad/xue-rnc/FPGA_1_3.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
 $Descr A3 16535 11700
-Sheet 5 11
+Sheet 5 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""
@@ -63,8 +63,46 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
-Text Label 5600 5100 0    40   ~ 0
+Text HLabel 11500 7500 2    40   BiDi ~ 0
-GND
+FPGA_2.5V_IO_M17
+Text HLabel 11500 7200 2    40   BiDi ~ 0
+FPGA_2.5V_IO_N16
+Text HLabel 11500 8300 2    40   BiDi ~ 0
+FPGA_2.5V_IO_P19
+Text HLabel 11500 7300 2    40   BiDi ~ 0
+FPGA_2.5V_IO_P17
+Text HLabel 11500 7100 2    40   BiDi ~ 0
+FPGA_2.5V_IO_P18
+Text HLabel 11500 7700 2    40   BiDi ~ 0
+FPGA_2.5V_IO_U19
+Text HLabel 11500 6800 2    40   BiDi ~ 0
+FPGA_2.5V_IO_T20
+Text HLabel 11500 7600 2    40   BiDi ~ 0
+FPGA_2.5V_IO_V20
+Text HLabel 11500 8100 2    40   BiDi ~ 0
+FPGA_2.5V_IO_W20
+Text HLabel 11500 8000 2    40   BiDi ~ 0
+FPGA_2.5V_IO_W22
+Text HLabel 7700 2500 0    40   BiDi ~ 0
+FPGA_2.5V_IO_V3
+Text HLabel 7700 2400 0    40   BiDi ~ 0
+FPGA_2.5V_IO_U4
+Text HLabel 7700 2300 0    40   BiDi ~ 0
+FPGA_2.5V_IO_T3
+Text HLabel 7700 2200 0    40   BiDi ~ 0
+FPGA_2.5V_IO_T4
+Text HLabel 7700 1900 0    40   BiDi ~ 0
+FPGA_2.5V_IO_P7
+Text HLabel 7700 1800 0    40   BiDi ~ 0
+FPGA_2.5V_IO_P8
+Text HLabel 7700 1700 0    40   BiDi ~ 0
+FPGA_2.5V_IO_W1
+Text HLabel 7700 1600 0    40   BiDi ~ 0
+FPGA_2.5V_IO_W3
+Text HLabel 7700 1500 0    40   BiDi ~ 0
+FPGA_2.5V_IO_Y1
+Text HLabel 7700 1400 0    40   BiDi ~ 0
+FPGA_2.5V_IO_Y2
 Wire Wire Line
 	7100 9100 6650 9100
 Wire Wire Line
@@ -72,56 +110,58 @@ Wire Wire Line
 Wire Wire Line
 	4500 4150 5050 4150
 Wire Wire Line
-	11300 3600 11800 3600
+	11900 3600 12400 3600
 Wire Wire Line
-	11300 5800 11800 5800
+	11900 5800 12400 5800
 Wire Wire Line
-	7100 5500 6500 5500
+	7700 5500 7100 5500
 Wire Wire Line
-	7100 5700 6500 5700
+	7700 5700 7100 5700
 Wire Wire Line
-	7100 4600 6500 4600
+	7700 4600 7100 4600
 Wire Wire Line
-	7100 4800 6500 4800
+	7700 4800 7100 4800
 Wire Wire Line
-	7100 5000 6500 5000
+	7700 5000 7100 5000
 Wire Wire Line
-	7100 5200 6500 5200
+	7700 5200 7100 5200
 Wire Wire Line
-	7100 4200 6500 4200
+	7700 4200 7100 4200
 Wire Wire Line
 	3900 4300 4000 4300
 Wire Wire Line
-	11300 4200 11800 4200
+	11900 4200 12400 4200
 Wire Wire Line
-	11300 5500 11850 5500
+	11900 5500 12450 5500
-Connection ~ 11700 4900
+Connection ~ 12300 4900
 Wire Wire Line
-	11700 4950 11700 4850
+	12300 4950 12300 4900
 Wire Wire Line
-	11700 4850 12250 4850
+	12300 4900 12300 4850
 Wire Wire Line
-	11300 4900 11700 4900
+	12300 4850 12850 4850
 Wire Wire Line
-	11800 5300 11300 5300
+	11900 4900 12300 4900
 Wire Wire Line
-	11800 4800 11300 4800
+	12400 5300 11900 5300
 Wire Wire Line
-	11800 4600 11300 4600
+	12400 4800 11900 4800
 Wire Wire Line
-	11800 4400 11300 4400
+	12400 4600 11900 4600
 Wire Wire Line
-	11800 4000 11300 4000
+	12400 4400 11900 4400
 Wire Wire Line
-	11800 3800 11300 3800
+	12400 4000 11900 4000
 Wire Wire Line
-	11800 3500 11300 3500
+	12400 3800 11900 3800
+Wire Wire Line
+	12400 3500 11900 3500
 Wire Bus Line
 	2200 1500 2250 1500
 Wire Wire Line
-	7100 4100 6500 4100
+	7700 4100 7100 4100
 Wire Wire Line
-	7100 3900 6500 3900
+	7700 3900 7100 3900
 Wire Wire Line
 	5650 2950 5200 2950
 Wire Wire Line
@@ -259,7 +299,9 @@ Wire Wire Line
 Wire Wire Line
 	5800 10000 5800 9900
 Wire Wire Line
-	5700 9900 6400 9900
+	5700 9900 5800 9900
+Wire Wire Line
+	5800 9900 6400 9900
 Wire Wire Line
 	6400 9900 6400 10000
 Wire Wire Line
@@ -397,9 +439,57 @@ Wire Wire Line
 Wire Wire Line
 	2750 2850 2350 2850
 Wire Bus Line
-	2250 1500 2250 2750
+	2250 1500 2250 1550
 Wire Bus Line
-	1400 6350 1400 7600
+	2250 1550 2250 1650
+Wire Bus Line
+	2250 1650 2250 1750
+Wire Bus Line
+	2250 1750 2250 1850
+Wire Bus Line
+	2250 1850 2250 1950
+Wire Bus Line
+	2250 1950 2250 2050
+Wire Bus Line
+	2250 2050 2250 2150
+Wire Bus Line
+	2250 2150 2250 2250
+Wire Bus Line
+	2250 2250 2250 2350
+Wire Bus Line
+	2250 2350 2250 2450
+Wire Bus Line
+	2250 2450 2250 2550
+Wire Bus Line
+	2250 2550 2250 2650
+Wire Bus Line
+	2250 2650 2250 2750
+Wire Bus Line
+	1400 6350 1400 6400
+Wire Bus Line
+	1400 6400 1400 6500
+Wire Bus Line
+	1400 6500 1400 6600
+Wire Bus Line
+	1400 6600 1400 6700
+Wire Bus Line
+	1400 6700 1400 6800
+Wire Bus Line
+	1400 6800 1400 6900
+Wire Bus Line
+	1400 6900 1400 7000
+Wire Bus Line
+	1400 7000 1400 7100
+Wire Bus Line
+	1400 7100 1400 7200
+Wire Bus Line
+	1400 7200 1400 7300
+Wire Bus Line
+	1400 7300 1400 7400
+Wire Bus Line
+	1400 7400 1400 7500
+Wire Bus Line
+	1400 7500 1400 7600
 Connection ~ 9600 6350
 Wire Wire Line
 	9600 6350 9600 6400
@@ -413,42 +503,78 @@ Wire Wire Line
 Wire Wire Line
 	9700 6400 9700 6350
 Wire Wire Line
-	9700 6350 8800 6350
+	9700 6350 9600 6350
+Wire Wire Line
+	9600 6350 9500 6350
+Wire Wire Line
+	9500 6350 9400 6350
+Wire Wire Line
+	9400 6350 9300 6350
+Wire Wire Line
+	9300 6350 9200 6350
+Wire Wire Line
+	9200 6350 9100 6350
+Wire Wire Line
+	9100 6350 9000 6350
+Wire Wire Line
+	9000 6350 8900 6350
+Wire Wire Line
+	8900 6350 8800 6350
 Wire Wire Line
 	8800 6350 8800 6400
-Connection ~ 9000 950 
-Wire Wire Line
-	9000 950  9000 1000
-Connection ~ 8800 950 
-Wire Wire Line
-	8800 1000 8800 950 
-Connection ~ 9500 950 
-Wire Wire Line
-	9500 950  9500 1000
-Connection ~ 9300 950 
-Wire Wire Line
-	9300 950  9300 1000
-Wire Wire Line
-	9700 1000 9700 950 
-Wire Wire Line
-	9700 950  8700 950 
-Wire Wire Line
-	8700 950  8700 1000
-Connection ~ 9200 950 
-Wire Wire Line
-	9200 850  9200 1000
-Wire Wire Line
-	9400 950  9400 1000
-Connection ~ 9400 950 
-Wire Wire Line
-	9600 950  9600 1000
 Connection ~ 9600 950 
 Wire Wire Line
-	8900 950  8900 1000
+	9600 950  9600 1000
-Connection ~ 8900 950 
+Connection ~ 9400 950 
 Wire Wire Line
-	9100 950  9100 1000
+	9400 1000 9400 950 
-Connection ~ 9100 950 
+Connection ~ 10100 950 
+Wire Wire Line
+	10100 950  10100 1000
+Connection ~ 9900 950 
+Wire Wire Line
+	9900 950  9900 1000
+Wire Wire Line
+	10300 1000 10300 950 
+Wire Wire Line
+	10300 950  10200 950 
+Wire Wire Line
+	10200 950  10100 950 
+Wire Wire Line
+	10100 950  10000 950 
+Wire Wire Line
+	10000 950  9900 950 
+Wire Wire Line
+	9900 950  9800 950 
+Wire Wire Line
+	9800 950  9700 950 
+Wire Wire Line
+	9700 950  9600 950 
+Wire Wire Line
+	9600 950  9500 950 
+Wire Wire Line
+	9500 950  9400 950 
+Wire Wire Line
+	9400 950  9300 950 
+Wire Wire Line
+	9300 950  9300 1000
+Connection ~ 9800 950 
+Wire Wire Line
+	9800 850  9800 950 
+Wire Wire Line
+	9800 950  9800 1000
+Wire Wire Line
+	10000 950  10000 1000
+Connection ~ 10000 950 
+Wire Wire Line
+	10200 950  10200 1000
+Connection ~ 10200 950 
+Wire Wire Line
+	9500 950  9500 1000
+Connection ~ 9500 950 
+Wire Wire Line
+	9700 950  9700 1000
+Connection ~ 9700 950 
 Wire Wire Line
 	8900 6400 8900 6350
 Connection ~ 8900 6350
@@ -462,7 +588,9 @@ Wire Wire Line
 	9500 6350 9500 6400
 Connection ~ 9500 6350
 Wire Wire Line
-	9200 6250 9200 6400
+	9200 6250 9200 6350
+Wire Wire Line
+	9200 6350 9200 6400
 Wire Wire Line
 	1900 7700 1500 7700
 Wire Wire Line
@@ -492,7 +620,37 @@ Wire Wire Line
 Wire Bus Line
 	2350 3500 2450 3500
 Wire Bus Line
-	2450 3500 2450 5100
+	2450 3500 2450 3600
+Wire Bus Line
+	2450 3600 2450 3700
+Wire Bus Line
+	2450 3700 2450 3800
+Wire Bus Line
+	2450 3800 2450 3900
+Wire Bus Line
+	2450 3900 2450 4000
+Wire Bus Line
+	2450 4000 2450 4100
+Wire Bus Line
+	2450 4100 2450 4200
+Wire Bus Line
+	2450 4200 2450 4300
+Wire Bus Line
+	2450 4300 2450 4400
+Wire Bus Line
+	2450 4400 2450 4500
+Wire Bus Line
+	2450 4500 2450 4600
+Wire Bus Line
+	2450 4600 2450 4700
+Wire Bus Line
+	2450 4700 2450 4800
+Wire Bus Line
+	2450 4800 2450 4900
+Wire Bus Line
+	2450 4900 2450 5000
+Wire Bus Line
+	2450 5000 2450 5100
 Wire Wire Line
 	1900 8550 1450 8550
 Wire Wire Line
@@ -615,7 +773,9 @@ Wire Wire Line
 	6650 9900 7100 9900
 Connection ~ 5800 9900
 Wire Wire Line
-	5700 10150 6400 10150
+	5700 10150 6300 10150
+Wire Wire Line
+	6300 10150 6400 10150
 Wire Wire Line
 	6400 10150 6400 10100
 Wire Wire Line
@@ -650,13 +810,41 @@ Wire Wire Line
 Wire Wire Line
 	5250 9500 5850 9500
 Wire Bus Line
-	1350 9350 1350 7850
+	1350 9350 1350 9250
+Wire Bus Line
+	1350 9250 1350 9150
+Wire Bus Line
+	1350 9150 1350 9050
+Wire Bus Line
+	1350 9050 1350 8950
+Wire Bus Line
+	1350 8950 1350 8850
+Wire Bus Line
+	1350 8850 1350 8750
+Wire Bus Line
+	1350 8750 1350 8650
+Wire Bus Line
+	1350 8650 1350 8550
+Wire Bus Line
+	1350 8550 1350 8450
+Wire Bus Line
+	1350 8450 1350 8350
+Wire Bus Line
+	1350 8350 1350 8250
+Wire Bus Line
+	1350 8250 1350 8150
+Wire Bus Line
+	1350 8150 1350 8050
+Wire Bus Line
+	1350 8050 1350 7950
+Wire Bus Line
+	1350 7950 1350 7850
 Wire Bus Line
 	1350 7850 1300 7850
 Wire Wire Line
-	7100 3800 6500 3800
+	7700 3800 7100 3800
 Wire Wire Line
-	7100 4000 6500 4000
+	7700 4000 7100 4000
 Wire Wire Line
 	3550 3450 4000 3450
 Wire Wire Line
@@ -742,52 +930,54 @@ Wire Wire Line
 Wire Wire Line
 	4400 3450 4850 3450
 Wire Wire Line
-	11800 3300 11300 3300
+	12400 3300 11900 3300
 Wire Wire Line
-	11800 3700 11300 3700
+	12400 3700 11900 3700
 Wire Wire Line
-	11800 3900 11300 3900
+	12400 3900 11900 3900
 Wire Wire Line
-	11800 4300 11300 4300
+	12400 4300 11900 4300
 Wire Wire Line
-	11800 4500 11300 4500
+	12400 4500 11900 4500
 Wire Wire Line
-	11800 4700 11300 4700
+	12400 4700 11900 4700
 Wire Wire Line
-	11800 5200 11300 5200
+	12400 5200 11900 5200
 Wire Wire Line
-	11300 5400 11800 5400
+	11900 5400 12400 5400
 Wire Wire Line
-	11300 5000 11700 5000
+	11900 5000 12300 5000
 Wire Wire Line
-	11700 5000 11700 5050
+	12300 5000 12300 5050
 Wire Wire Line
-	11700 5050 12250 5050
+	12300 5050 12800 5050
 Wire Wire Line
-	12200 4950 12200 5050
+	12800 5050 12850 5050
-Connection ~ 12200 5050
 Wire Wire Line
-	11300 5700 11800 5700
+	12800 4950 12800 5050
+Connection ~ 12800 5050
+Wire Wire Line
+	11900 5700 12400 5700
 Wire Wire Line
 	3900 4150 4000 4150
 Wire Wire Line
 	3900 4450 4000 4450
 Wire Wire Line
-	7100 4400 6500 4400
+	7700 4400 7100 4400
 Wire Wire Line
-	7100 5100 6500 5100
+	7700 5100 7100 5100
 Wire Wire Line
-	7100 4900 6500 4900
+	7700 4900 7100 4900
 Wire Wire Line
-	7100 4700 6500 4700
+	7700 4700 7100 4700
 Wire Wire Line
-	7100 4500 6500 4500
+	7700 4500 7100 4500
 Wire Wire Line
-	7100 5600 6500 5600
+	7700 5600 7100 5600
 Wire Wire Line
-	7100 5400 6500 5400
+	7700 5400 7100 5400
 Wire Wire Line
-	11300 5600 11800 5600
+	11900 5600 12400 5600
 Wire Wire Line
 	4500 4300 5050 4300
 Wire Wire Line
@@ -800,6 +990,8 @@ Wire Wire Line
 	7100 7700 7000 7700
 Wire Wire Line
 	7100 8300 7000 8300
+Text Label 5600 5100 0    40   ~ 0
+GND
 Text HLabel 7000 7400 0    60   BiDi ~ 0
 USBD_VP
 Text HLabel 7000 6900 0    60   BiDi ~ 0
@@ -840,13 +1032,13 @@ F 2 "0402" H 4250 4450 60  0001 C CNN
 	1    4250 4450
 	0    1    1    0   
 $EndComp
-Text Label 6500 4200 0    60   ~ 0
+Text Label 7100 4200 0    60   ~ 0
 R_M0_UDQS
-Text Label 11350 5600 0    60   ~ 0
+Text Label 11950 5600 0    60   ~ 0
 R_M0_RAS#
-Text Label 11350 3600 0    60   ~ 0
+Text Label 11950 3600 0    60   ~ 0
 R_M0_CKE
-Text Label 11350 5800 0    60   ~ 0
+Text Label 11950 5800 0    60   ~ 0
 R_M0_UDM
 Text Label 4600 4300 0    60   ~ 0
 R_M0_UDM
@@ -860,22 +1052,22 @@ Text HLabel 3900 4300 0    60   Output ~ 0
 M0_UDM
 Text HLabel 3900 4150 0    60   Output ~ 0
 M0_UDQS
-Text Label 6500 5200 0    60   ~ 0
+Text Label 7100 5200 0    60   ~ 0
 R_M0_LDQS
-Text Label 11350 5700 0    60   ~ 0
+Text Label 11950 5700 0    60   ~ 0
 R_M0_LDM
-Text Label 11350 4200 0    60   ~ 0
+Text Label 11950 4200 0    60   ~ 0
 R_M0_WE#
-Text Label 11350 5500 0    60   ~ 0
+Text Label 11950 5500 0    60   ~ 0
 R_M0_CAS#
 $Comp
 L R R21
 U 1 1 4C6B1B90
-P 11950 4950
+P 12550 4950
-F 0 "R21" V 12030 4950 50  0000 C CNN
+F 0 "R21" V 12630 4950 50  0000 C CNN
-F 1 "120" V 11950 4950 50  0000 C CNN
+F 1 "120" V 12550 4950 50  0000 C CNN
-F 2 "0402" H 11950 4950 60  0001 C CNN
+F 2 "0402" H 12550 4950 60  0001 C CNN
-	1    11950 4950
+	1    12550 4950
 	0    1    1    0   
 $EndComp
 Text HLabel 3400 1450 0    60   Output ~ 0
@@ -1469,10 +1661,10 @@ $EndComp
 $Comp
 L +2.5V #PWR031
 U 1 1 4C61E51F
-P 9200 850
+P 9800 850
-F 0 "#PWR031" H 9200 800 20  0001 C CNN
+F 0 "#PWR031" H 9800 800 20  0001 C CNN
-F 1 "+2.5V" H 9200 950 30  0000 C CNN
+F 1 "+2.5V" H 9800 950 30  0000 C CNN
-	1    9200 850 
+	1    9800 850 
 	1    0    0    -1  
 $EndComp
 Entry Wire Line
@@ -1640,67 +1832,67 @@ Text Label 2650 4400 0    60   ~ 0
 M0_DQ7
 Text Label 2650 4300 0    60   ~ 0
 M0_DQ6
-Text Label 6500 5400 0    60   ~ 0
+Text Label 7100 5400 0    60   ~ 0
 R_M0_DQ6
-Text Label 6500 5500 0    60   ~ 0
+Text Label 7100 5500 0    60   ~ 0
 R_M0_DQ7
-Text Label 6500 5700 0    60   ~ 0
+Text Label 7100 5700 0    60   ~ 0
 R_M0_DQ5
-Text Label 6500 5600 0    60   ~ 0
+Text Label 7100 5600 0    60   ~ 0
 R_M0_DQ4
-Text Label 6500 5000 0    60   ~ 0
+Text Label 7100 5000 0    60   ~ 0
 R_M0_DQ2
-Text Label 6500 5100 0    60   ~ 0
+Text Label 7100 5100 0    60   ~ 0
 R_M0_DQ3
-Text Label 6500 4900 0    60   ~ 0
+Text Label 7100 4900 0    60   ~ 0
 R_M0_DQ1
-Text Label 6500 4800 0    60   ~ 0
+Text Label 7100 4800 0    60   ~ 0
 R_M0_DQ0
-Text Label 6500 4400 0    60   ~ 0
+Text Label 7100 4400 0    60   ~ 0
 R_M0_DQ10
-Text Label 6500 4500 0    60   ~ 0
+Text Label 7100 4500 0    60   ~ 0
 R_M0_DQ11
-Text Label 6500 4700 0    60   ~ 0
+Text Label 7100 4700 0    60   ~ 0
 R_M0_DQ9
-Text Label 6500 4600 0    60   ~ 0
+Text Label 7100 4600 0    60   ~ 0
 R_M0_DQ8
-Text Label 6500 4000 0    60   ~ 0
+Text Label 7100 4000 0    60   ~ 0
 R_M0_DQ12
-Text Label 6500 4100 0    60   ~ 0
+Text Label 7100 4100 0    60   ~ 0
 R_M0_DQ13
-Text Label 6500 3900 0    60   ~ 0
+Text Label 7100 3900 0    60   ~ 0
 R_M0_DQ15
-Text Label 6500 3800 0    60   ~ 0
+Text Label 7100 3800 0    60   ~ 0
 R_M0_DQ14
-Text Label 11350 4800 0    60   ~ 0
+Text Label 11950 4800 0    60   ~ 0
 R_M0_A0
-Text Label 11350 5300 0    60   ~ 0
+Text Label 11950 5300 0    60   ~ 0
 R_M0_A6
-Text Label 11350 5400 0    60   ~ 0
+Text Label 11950 5400 0    60   ~ 0
 R_M0_A5
-Text Label 11350 4300 0    60   ~ 0
+Text Label 11950 4300 0    60   ~ 0
 R_M0_A2
-Text Label 11350 4500 0    60   ~ 0
+Text Label 11950 4500 0    60   ~ 0
 R_M0_BA1
-Text Label 11350 4400 0    60   ~ 0
+Text Label 11950 4400 0    60   ~ 0
 R_M0_A7
-Text Label 11350 4600 0    60   ~ 0
+Text Label 11950 4600 0    60   ~ 0
 R_M0_BA0
-Text Label 11350 4700 0    60   ~ 0
+Text Label 11950 4700 0    60   ~ 0
 R_M0_A1
-Text Label 11350 3500 0    60   ~ 0
+Text Label 11950 3500 0    60   ~ 0
 R_M0_A12
-Text Label 11350 3300 0    60   ~ 0
+Text Label 11950 3300 0    60   ~ 0
 R_M0_A11
-Text Label 11350 3700 0    60   ~ 0
+Text Label 11950 3700 0    60   ~ 0
 R_M0_A9
-Text Label 11350 3800 0    60   ~ 0
+Text Label 11950 3800 0    60   ~ 0
 R_M0_A8
-Text Label 11350 4000 0    60   ~ 0
+Text Label 11950 4000 0    60   ~ 0
 R_M0_A10
-Text Label 11350 5200 0    60   ~ 0
+Text Label 11950 5200 0    60   ~ 0
 R_M0_A3
-Text Label 11350 3900 0    60   ~ 0
+Text Label 11950 3900 0    60   ~ 0
 R_M0_A4
 Text HLabel 2200 1500 0    60   Output ~ 0
 M0_A[0..12]
@@ -1840,17 +2032,17 @@ Text HLabel 5700 9900 0    60   Output ~ 0
 M1_CLK
 Text HLabel 5700 10150 0    60   Output ~ 0
 M1_CLK#
-Text HLabel 12250 5050 2    60   Output ~ 0
+Text HLabel 12850 5050 2    60   Output ~ 0
 M0_CLK
-Text HLabel 12250 4850 2    60   Output ~ 0
+Text HLabel 12850 4850 2    60   Output ~ 0
 M0_CLK#
 $Comp
 L XC6SLX45FGG484 U1
 U 3 1 4C431E3F
-P 9200 3600
+P 9800 3600
-F 0 "U1" H 9200 3700 70  0000 C CNN
+F 0 "U1" H 9800 3700 70  0000 C CNN
-F 1 "XC6SLX45FGG484" H 9200 3500 70  0000 C CNN
+F 1 "XC6SLX45FGG484" H 9800 3500 70  0000 C CNN
-	3    9200 3600
+	3    9800 3600
 	1    0    0    -1  
 $EndComp
 $Comp

kicad/xue-rnc/NV_MEMORIES.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
 $Descr A4 11700 8267
-Sheet 6 11
+Sheet 6 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""

kicad/xue-rnc/PSU.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
 $Descr A4 11700 8267
-Sheet 7 11
+Sheet 7 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""

kicad/xue-rnc/USB.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
 $Descr A4 11700 8267
-Sheet 7 11
+Sheet 7 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""

kicad/xue-rnc/eth_phy.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
 $Descr A4 11700 8267
-Sheet 8 11
+Sheet 8 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""

kicad/xue-rnc/expantion.sch

@@ -0,0 +1,75 @@
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
+LIBS:power
+LIBS:r_pack2
+LIBS:v0402mhs03
+LIBS:usb-48204-0001
+LIBS:microsmd075f
+LIBS:mic2550
+LIBS:rj45-48025
+LIBS:xue-nv
+LIBS:xc6slx75fgg484
+LIBS:xc6slx45fgg484
+LIBS:micron_mobile_ddr
+LIBS:micron_ddr_512Mb
+LIBS:k8001
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:pasives-connectors
+LIBS:x25x64mb
+LIBS:attiny
+LIBS:PSU
+LIBS:tps793xx
+LIBS:reg102
+LIBS:mt9m033
+LIBS:m12-tu400a
+LIBS:xue-rnc-cache
+EELAYER 24  0
+EELAYER END
+$Descr A4 11700 8267
+Sheet 2 12
+Title ""
+Date "9 oct 2010"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CONN_20X2 P?
+U 1 1 4CB0D9BF
+P 6200 1900
+F 0 "P?" H 6200 2950 60  0000 C CNN
+F 1 "CONN_20X2" V 6200 1900 50  0000 C CNN
+	1    6200 1900
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC

kicad/xue-rnc/sensor.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
 $Descr A4 11700 8267
-Sheet 2 11
+Sheet 2 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""

kicad/xue-rnc/sensor_psu.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -53,9 +53,9 @@ LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
 $Descr A4 11700 8267
-Sheet 3 11
+Sheet 3 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""

kicad/xue-rnc/xue-rnc-cache.lib

@@ -1,4 +1,4 @@
-EESchema-LIBRARY Version 2.3  Date: Fri 08 Oct 2010 11:41:21 AM COT
+EESchema-LIBRARY Version 2.3  Date: Sat 09 Oct 2010 04:08:56 PM COT
 #
 # +1.2V
 #
@@ -183,6 +183,56 @@ X ~ 2 0 -100 65 U 40 40 1 1 P
 ENDDRAW
 ENDDEF
 #
+# CONN_20X2
+#
+DEF CONN_20X2 P 0 10 Y N 1 F N
+F0 "P" 0 1050 60 H V C CNN
+F1 "CONN_20X2" 0 0 50 V V C CNN
+DRAW
+S -100 1000 100 -1000 0 1 0 N
+X P1 1 -400 950 300 R 60 30 1 1 P I
+X P2 2 400 950 300 L 60 30 1 1 P I
+X P3 3 -400 850 300 R 60 30 1 1 P I
+X P4 4 400 850 300 L 60 30 1 1 P I
+X P5 5 -400 750 300 R 60 30 1 1 P I
+X P6 6 400 750 300 L 60 30 1 1 P I
+X P7 7 -400 650 300 R 60 30 1 1 P I
+X P8 8 400 650 300 L 60 30 1 1 P I
+X P9 9 -400 550 300 R 60 30 1 1 P I
+X P10 10 400 550 300 L 60 30 1 1 P I
+X P20 20 400 50 300 L 60 30 1 1 P I
+X P30 30 400 -450 300 L 60 30 1 1 P I
+X P40 40 400 -950 300 L 60 30 1 1 P I
+X P11 11 -400 450 300 R 60 30 1 1 P I
+X P21 21 -400 -50 300 R 60 30 1 1 P I
+X P31 31 -400 -550 300 R 60 30 1 1 P I
+X P12 12 400 450 300 L 60 30 1 1 P I
+X P22 22 400 -50 300 L 60 30 1 1 P I
+X P32 32 400 -550 300 L 60 30 1 1 P I
+X P13 13 -400 350 300 R 60 30 1 1 P I
+X P23 23 -400 -150 300 R 60 30 1 1 P I
+X P33 33 -400 -650 300 R 60 30 1 1 P I
+X P14 14 400 350 300 L 60 30 1 1 P I
+X P24 24 400 -150 300 L 60 30 1 1 P I
+X P34 34 400 -650 300 L 60 30 1 1 P I
+X P15 15 -400 250 300 R 60 30 1 1 P I
+X ~ 25 -400 -250 300 R 60 30 1 1 P I
+X P35 35 -400 -750 300 R 60 30 1 1 P I
+X P16 16 400 250 300 L 60 30 1 1 P I
+X P26 26 400 -250 300 L 60 30 1 1 P I
+X P36 36 400 -750 300 L 60 30 1 1 P I
+X P17 17 -400 150 300 R 60 30 1 1 P I
+X P27 27 -400 -350 300 R 60 30 1 1 P I
+X P37 37 -400 -850 300 R 60 30 1 1 P I
+X P18 18 400 150 300 L 60 30 1 1 P I
+X P28 28 400 -350 300 L 60 30 1 1 P I
+X P38 38 400 -850 300 L 60 30 1 1 P I
+X P19 19 -400 50 300 R 60 30 1 1 P I
+X P29 29 -400 -450 300 R 60 30 1 1 P I
+X P39 39 -400 -950 300 R 60 30 1 1 P I
+ENDDRAW
+ENDDEF
+#
 # CONN_4
 #
 DEF CONN_4 P 0 40 Y N 1 F N

kicad/xue-rnc/xue-rnc.pro

@@ -1,4 +1,4 @@
-update=Fri 08 Oct 2010 11:44:31 AM COT
+update=Sat 09 Oct 2010 04:09:08 PM COT
 version=1
 last_client=pcbnew
 [common]
@@ -89,13 +89,13 @@ LibName47=../library/tps793xx
 LibName48=../library/reg102
 LibName49=../library/mt9m033
 LibName50=../library/m12-tu400a
+[general]
+version=1
 [cvpcb]
 version=1
 NetIExt=net
 [cvpcb/libraries]
 EquName1=devcms
-[general]
-version=1
 [pcbnew]
 version=1
 PadDrlX=0

kicad/xue-rnc/xue-rnc.sch

@@ -1,4 +1,4 @@
-EESchema Schematic File Version 2  date Fri 08 Oct 2010 11:41:21 AM COT
+EESchema Schematic File Version 2  date Sat 09 Oct 2010 04:08:56 PM COT
 LIBS:power
 LIBS:r_pack2
 LIBS:v0402mhs03
@@ -52,10 +52,10 @@ LIBS:m12-tu400a
 LIBS:xue-rnc-cache
 EELAYER 24  0
 EELAYER END
-$Descr A3 16535 11700
+$Descr A2 23400 16535
-Sheet 1 11
+Sheet 1 12
 Title ""
-Date "8 oct 2010"
+Date "9 oct 2010"
 Rev ""
 Comp ""
 Comment1 ""
@@ -63,424 +63,470 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Bus Line
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-Wire Bus Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Bus Line
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-Wire Wire Line
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-Wire Wire Line
-	10650 8400 9300 8400
-Wire Wire Line
-	10650 8600 9300 8600
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
-	5950 6750 4950 6750
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
-	3150 8600 3400 8600
-Wire Wire Line
-	3150 8900 3400 8900
-Wire Wire Line
-	3150 9200 3400 9200
-Wire Bus Line
-	5950 9000 4950 9000
-Wire Wire Line
-	4950 7700 5950 7700
-Wire Wire Line
-	5950 7900 4950 7900
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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 $Sheet
-S 3400 7300 1550 2050
+S 14800 5850 1100 5850
+U 4CB0D95D
+F0 "FPGA GPIOS" 60
+F1 "expantion.sch" 60
+$EndSheet
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Bus Line
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+Wire Wire Line
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+Wire Wire Line
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+$Sheet
+S 7550 3650 1550 2050
 U 4C9E2AF4
 F0 "Image Sensor" 60
 F1 "sensor.sch" 60
-F2 "+2.8_VDDIO" B L 3400 8750 60 
+F2 "+2.8_VDDIO" B L 7550 5100 60 
-F3 "+1.8_VDD" B L 3400 8900 60 
+F3 "+1.8_VDD" B L 7550 5250 60 
-F4 "+2.8_VAA" B L 3400 9200 60 
+F4 "+2.8_VAA" B L 7550 5550 60 
-F5 "+2.8_VAAPIX" B L 3400 9050 60 
+F5 "+2.8_VAAPIX" B L 7550 5400 60 
-F6 "+2.8_VDDPLL" B L 3400 8600 60 
+F6 "+2.8_VDDPLL" B L 7550 4950 60 
-F7 "IS_TRIGGER" I R 4950 7400 60 
+F7 "IS_TRIGGER" I R 9100 3750 60 
-F8 "IS_FLASH" O R 4950 7500 60 
+F8 "IS_FLASH" O R 9100 3850 60 
-F9 "IS_SDA" B R 4950 7600 60 
+F9 "IS_SDA" B R 9100 3950 60 
-F10 "IS_SCL" B R 4950 7700 60 
+F10 "IS_SCL" B R 9100 4050 60 
-F11 "IS_I2C_ADDR" I R 4950 7800 60 
+F11 "IS_I2C_ADDR" I R 9100 4150 60 
-F12 "IS_EXTCLK" I R 4950 7900 60 
+F12 "IS_EXTCLK" I R 9100 4250 60 
-F13 "IS_RESET_N" I R 4950 8000 60 
+F13 "IS_RESET_N" I R 9100 4350 60 
-F14 "IS_OE_N" I R 4950 8100 60 
+F14 "IS_OE_N" I R 9100 4450 60 
-F15 "IS_STANDBY" I R 4950 8200 60 
+F15 "IS_STANDBY" I R 9100 4550 60 
-F16 "IS_TEST" I R 4950 8300 60 
+F16 "IS_TEST" I R 9100 4650 60 
-F17 "IS_PIXEL" O R 4950 8400 60 
+F17 "IS_PIXEL" O R 9100 4750 60 
-F18 "IS_LINE" O R 4950 8500 60 
+F18 "IS_LINE" O R 9100 4850 60 
-F19 "IS_FRAME" O R 4950 8600 60 
+F19 "IS_FRAME" O R 9100 4950 60 
-F20 "IS_DOUT[0..11]" O R 4950 9000 60 
+F20 "IS_DOUT[0..11]" O R 9100 5350 60 
 $EndSheet
 $Sheet
-S 2050 8300 1100 1000
+S 6200 4650 1100 1000
 U 4C9E2B0F
 F0 "Snesor PSU" 60
 F1 "sensor_psu.sch" 60
-F2 "+2.8_VDDPLL" B R 3150 8600 60 
+F2 "+2.8_VDDPLL" B R 7300 4950 60 
-F3 "+2.8_VDDIO" B R 3150 8750 60 
+F3 "+2.8_VDDIO" B R 7300 5100 60 
-F4 "+1.8_VDD" B R 3150 8900 60 
+F4 "+1.8_VDD" B R 7300 5250 60 
-F5 "+2.8_VAAPIX" B R 3150 9050 60 
+F5 "+2.8_VAAPIX" B R 7300 5400 60 
-F6 "+2.8_VAA" B R 3150 9200 60 
+F6 "+2.8_VAA" B R 7300 5550 60 
 $EndSheet
 $Sheet
-S 5950 5150 3350 4350
+S 10100 1500 3350 6650
 U 4C7BC2B2
 F0 "FPGA, Port0, Port2, PROG IF" 60
 F1 "FPGA_0_2_PROG.sch" 60
-F2 "S6_TCK" I L 5950 6450 60 
+F2 "S6_TCK" I L 10100 6750 60 
-F3 "S6_TDI" I L 5950 6550 60 
+F3 "S6_TDI" I L 10100 6850 60 
-F4 "S6_TDO" O L 5950 6650 60 
+F4 "S6_TDO" O L 10100 6950 60 
-F5 "S6_TMS" I L 5950 6750 60 
+F5 "S6_TMS" I L 10100 7050 60 
-F6 "PROG_MISO[0..3]" B R 9300 9150 60 
+F6 "PROG_MISO[0..3]" B R 13450 5500 60 
-F7 "PROG_CCLK" O R 9300 9050 60 
+F7 "PROG_CCLK" O R 13450 5400 60 
-F8 "PROG_CSO" O R 9300 8950 60 
+F8 "PROG_CSO" O R 13450 5300 60 
-F9 "NF_D[0..7]" B R 9300 8700 60 
+F9 "NF_D[0..7]" B R 13450 5050 60 
-F10 "ETH_COL" B R 9300 5850 60 
+F10 "ETH_COL" B R 13450 2200 60 
-F11 "ETH_CRS" B R 9300 5750 60 
+F11 "ETH_CRS" B R 13450 2100 60 
-F12 "NF_WE_N" O R 9300 8400 60 
+F12 "NF_WE_N" O R 13450 4750 60 
-F13 "NF_ALE" O R 9300 8200 60 
+F13 "NF_ALE" O R 13450 4550 60 
-F14 "NF_CLE" O R 9300 8300 60 
+F14 "NF_CLE" O R 13450 4650 60 
-F15 "NF_CS1_N" O R 9300 8100 60 
+F15 "NF_CS1_N" O R 13450 4450 60 
-F16 "NF_RE_N" O R 9300 8500 60 
+F16 "NF_RE_N" O R 13450 4850 60 
-F17 "NF_RNB" B R 9300 8600 60 
+F17 "NF_RNB" B R 13450 4950 60 
-F18 "SD_CLK" B R 9300 7550 60 
+F18 "SD_CLK" B R 13450 3900 60 
-F19 "SD_CMD" B R 9300 7650 60 
+F19 "SD_CMD" B R 13450 4000 60 
-F20 "SD_DAT[0..3]" B R 9300 7750 60 
+F20 "SD_DAT[0..3]" B R 13450 4100 60 
-F21 "ETH_CLK" B R 9300 6950 60 
+F21 "ETH_CLK" B R 13450 3300 60 
-F22 "ETH_RXC" B R 9300 5550 60 
+F22 "ETH_RXC" B R 13450 1900 60 
-F23 "ETH_TXC" B R 9300 6550 60 
+F23 "ETH_TXC" B R 13450 2900 60 
-F24 "ETH_TXD[0..3]" O R 9300 6650 60 
+F24 "ETH_TXD[0..3]" O R 13450 3000 60 
-F25 "ETH_TXEN" B R 9300 6750 60 
+F25 "ETH_TXEN" B R 13450 3100 60 
-F26 "ETH_TXER" B R 9300 6850 60 
+F26 "ETH_TXER" B R 13450 3200 60 
-F27 "ETH_RXER" B R 9300 6450 60 
+F27 "ETH_RXER" B R 13450 2800 60 
-F28 "ETH_RXDV" B R 9300 6350 60 
+F28 "ETH_RXDV" B R 13450 2700 60 
-F29 "ETH_RXD[0..3]" I R 9300 6250 60 
+F29 "ETH_RXD[0..3]" I R 13450 2600 60 
-F30 "ETH_RESET_N" B R 9300 5650 60 
+F30 "ETH_RESET_N" B R 13450 2000 60 
-F31 "ETH_MDIO" B R 9300 5950 60 
+F31 "ETH_MDIO" B R 13450 2300 60 
-F32 "ETH_MDC" B R 9300 6050 60 
+F32 "ETH_MDC" B R 13450 2400 60 
-F33 "ETH_INT" B R 9300 5400 60 
+F33 "ETH_INT" B R 13450 1750 60 
-F34 "IS_DOUT[0..11]" I L 5950 9000 60 
+F34 "IS_DOUT[0..11]" I L 10100 5350 60 
-F35 "IS_TEST" O L 5950 8300 60 
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-F36 "IS_STANDBY" O L 5950 8200 60 
+F36 "IS_STANDBY" O L 10100 4550 60 
-F37 "IS_OE_N" O L 5950 8100 60 
+F37 "IS_OE_N" O L 10100 4450 60 
-F38 "IS_RESET_N" O L 5950 8000 60 
+F38 "IS_RESET_N" O L 10100 4350 60 
-F39 "IS_EXTCLK" O L 5950 7900 60 
+F39 "IS_EXTCLK" O L 10100 4250 60 
-F40 "IS_I2C_ADDR" O L 5950 7800 60 
+F40 "IS_I2C_ADDR" O L 10100 4150 60 
-F41 "IS_SCL" B L 5950 7700 60 
+F41 "IS_SCL" B L 10100 4050 60 
-F42 "IS_SDA" B L 5950 7600 60 
+F42 "IS_SDA" B L 10100 3950 60 
-F43 "IS_FRAME" I L 5950 8600 60 
+F43 "IS_FRAME" I L 10100 4950 60 
-F44 "IS_LINE" I L 5950 8500 60 
+F44 "IS_LINE" I L 10100 4850 60 
-F45 "IS_PIXEL" I L 5950 8400 60 
+F45 "IS_PIXEL" I L 10100 4750 60 
-F46 "IS_FLASH" I L 5950 7500 60 
+F46 "IS_FLASH" I L 10100 3850 60 
-F47 "IS_TRIGGER" O L 5950 7400 60 
+F47 "IS_TRIGGER" O L 10100 3750 60 
+F48 "FPGA_VCCO2_IO_AA18" B R 13450 5950 60 
+F49 "FPGA_VCCO2_IO_AB21" B R 13450 6050 60 
+F50 "FPGA_VCCO2_IO_W18" B R 13450 6150 60 
+F51 "FPGA_VCCO2_IO_AB16" B R 13450 6250 60 
+F52 "FPGA_VCCO2_IO_AB15" B R 13450 6350 60 
+F53 "FPGA_VCCO2_IO_V7" B R 13450 6450 60 
+F54 "FPGA_VCCO2_IO_W6" B R 13450 6550 60 
+F55 "FPGA_VCCO2_IO_W4" B R 13450 6650 60 
+F56 "FPGA_VCCO2_IO_Y10" B R 13450 6750 60 
+F57 "FPGA_VCCO2_IO_Y9" B R 13450 6850 60 
+F58 "FPGA_VCCO2_IO_Y15" B R 13450 6950 60 
+F59 "FPGA_VCCO2_IO_Y16" B R 13450 7050 60 
+F60 "FPGA_VCCO2_IO_W10" B R 13450 7150 60 
+F61 "FPGA_VCCO2_IO_W11" B R 13450 7250 60 
+F62 "FPGA_VCCO2_IO_Y12" B R 13450 7350 60 
+F63 "FPGA_VCCO2_IO_AB14" B R 13450 7450 60 
+F64 "FPGA_VCCO2_IO_AB13" B R 13450 7550 60 
+F65 "FPGA_VCCO2_IO_Y11" B R 13450 7650 60 
+F66 "FPGA_VCCO2_IO_W8" B R 13450 7750 60 
+F67 "FPGA_VCCO2_IO_U9" B R 13450 7850 60 
 $EndSheet
 $Sheet
-S 5950 700  3300 4200
+S 10100 9250 3300 4350
 U 4C7BC2A2
 F0 "FPGA Port 1, Port 3 DDR, USB" 60
 F1 "FPGA_1_3.sch" 60
-F2 "USBD_VP" B R 9250 1850 60 
+F2 "USBD_VP" B R 13400 12950 60 
-F3 "USBD_SPD" B R 9250 1550 60 
+F3 "USBD_SPD" B R 13400 12650 60 
-F4 "USBD_OE_N" B R 9250 1650 60 
+F4 "USBD_OE_N" B R 13400 12750 60 
-F5 "USBD_RCV" B R 9250 1750 60 
+F5 "USBD_RCV" B R 13400 12850 60 
-F6 "USBD_VM" B R 9250 1950 60 
+F6 "USBD_VM" B R 13400 13050 60 
-F7 "M0_CKE" O L 5950 4100 60 
+F7 "M0_CKE" O L 10100 12650 60 
-F8 "M0_UDM" O L 5950 3850 60 
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-F9 "M0_UDQS" O L 5950 3550 60 
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-F10 "M0_BA[0..1]" O L 5950 3400 60 
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-F11 "M0_CAS#" O L 5950 4450 60 
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-F12 "M0_RAS#" O L 5950 4550 60 
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-F13 "M0_WE#" O L 5950 4700 60 
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-F14 "M0_LDM" O L 5950 3950 60 
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-F15 "M0_LDQS" O L 5950 3650 60 
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-F16 "M1_UDQS" O L 5950 1500 60 
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-F17 "M1_UDM" O L 5950 1800 60 
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-F18 "M1_LDQS" O L 5950 1600 60 
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-F19 "M1_LDM" O L 5950 1900 60 
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-F20 "M1_WE#" O L 5950 2650 60 
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-F21 "M1_CKE" O L 5950 2050 60 
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-F22 "M1_RAS#" O L 5950 2500 60 
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-F23 "M1_CAS#" O L 5950 2400 60 
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-F24 "M1_BA[0..1]" O L 5950 1300 60 
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-F25 "M1_CS#" O L 5950 950 60 
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-F26 "USBA_VM" B R 9250 1350 60 
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-F27 "USBA_VP" B R 9250 1250 60 
+F27 "USBA_VP" B R 13400 12350 60 
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 $Sheet
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 U 4C716A4D
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 F1 "DBG_PRG.sch" 60
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 $Sheet
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 U 4C4227FE
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 F1 "NV_MEMORIES.sch" 60
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 $Sheet
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 U 4C5F1EDC
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 F1 "USB.sch" 60
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-Text Notes 12850 10750 0    60   ~ 0
+Text Notes 19700 15650 0    60   ~ 0
 Copyright: Andres.Calderon@emQbit.com  /  Juan.Brinez@emQbit.com
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 U 4C4320F3
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 F1 "eth_phy.sch" 60
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 F1 "DRAM.sch" 60
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 $EndSheet
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