1
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mirror of git://projects.qi-hardware.com/xue.git synced 2024-12-26 21:41:44 +02:00

Some routing and revision.

This commit is contained in:
Juan64Bits 2010-11-07 12:37:25 -05:00
parent ca69a54e87
commit 8c6ea43cea
17 changed files with 15942 additions and 14861 deletions

View File

@ -8,11 +8,11 @@ Li TP40R
Sc 4A909090
AR
Op 0 0 0
T0 0 -1224 600 600 0 120 N I 21 "TP40R"
T1 0 2688 600 600 0 120 N V 21 "VAL"
DC 0 0 -270 0 50 21
T0 0 -1224 400 400 0 60 N I 21 "TP40R"
T1 0 2688 400 400 0 60 N I 21 "VAL"
DC 0 0 -130 0 50 21
$PAD
Sh "1" C 394 394 0 0 0
Sh "1" C 197 197 0 0 0
Dr 0 0 0
At SMD N 00888000
Po 0 0

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 7 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""
@ -65,179 +65,211 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
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NoConn ~ 3450 5050
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Wire Wire Line
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8050 4050 8100 4050
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8050 3850 8100 3850
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Connection ~ 3100 4850
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Wire Wire Line
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8050 5350 8100 5350
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8100 5250 8050 5250
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Wire Wire Line
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Wire Wire Line
3050 3100 3100 3100
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
5100 1900 5100 2000
Wire Wire Line
5950 1900 5950 2000
Wire Wire Line
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Wire Wire Line
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Connection ~ 6400 1450
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 6400 2050
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Connection ~ 6950 1450
Wire Wire Line
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Connection ~ 7200 2450
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Connection ~ 5950 1450
Wire Wire Line
4650 1450 5200 1450
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 1550 4300
Wire Wire Line
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Wire Wire Line
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Connection ~ 1700 3500
Wire Wire Line
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Wire Wire Line
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Connection ~ 2350 3400
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 4750 4850
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Wire Wire Line
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3450 4850 3100 4850
Wire Wire Line
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Wire Wire Line
3450 4850 3100 4850
8600 4150 9000 4150
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 1700 3500
Wire Wire Line
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Wire Wire Line
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Connection ~ 1550 4300
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 1700 3550
Wire Wire Line
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Wire Wire Line
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Connection ~ 5100 1450
Wire Wire Line
4650 1450 5200 1450
Connection ~ 5950 1450
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Connection ~ 7200 2450
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Wire Wire Line
5800 3150 6050 3150
Wire Wire Line
8100 5650 8050 5650
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Wire Wire Line
5450 3750 5450 4050
Wire Wire Line
5450 4050 5500 4050
Wire Wire Line
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Wire Wire Line
6750 6050 6750 6150
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Wire Wire Line
7150 6050 7150 6100
Wire Wire Line
7250 6050 7250 6100
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
7050 6050 7050 6100
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Wire Wire Line
7100 6100 7100 6150
Connection ~ 7100 6100
Wire Wire Line
5400 3450 6050 3450
Wire Wire Line
6000 4050 6050 4050
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
6750 2550 6750 2050
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 6400 1450
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
4300 3750 4900 3750
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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NoConn ~ 3450 5050
NoConn ~ 4500 4850
$Comp
L FXO-HC536R X1
U 1 1 4CD349DF

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 9 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A3 16535 11700
Sheet 5 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A3 16535 11700
Sheet 6 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 9 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 8 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""
@ -853,7 +853,7 @@ F 1 "GND" H 1250 6130 30 0001 C CNN
1 1250 6200
1 0 0 -1
$EndComp
Text Label 2350 5250 0 30 ~ 0
Text Label 2300 5200 0 30 ~ 0
VIN_DC-DC-2.5
$Comp
L GND #PWR069

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 10 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 8 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 2 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""
@ -65,16 +65,18 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
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U 1 1 4CBAFE50
P 6800 3550
F 0 "P1" H 6800 4850 60 0000 C CNN
F 1 "CONN_25X2" V 6800 3550 50 0000 C CNN
F 2 "header25x2_smd_2mm" H 6740 4910 60 0001 C CNN
1 6800 3550
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
6400 4750 5500 4750
Wire Wire Line
8300 4650 9300 4650
Wire Wire Line
5500 4250 6400 4250
Wire Wire Line
@ -302,43 +304,19 @@ Wire Wire Line
Wire Wire Line
8100 3050 7200 3050
Wire Wire Line
9800 6700 10700 6700
7200 4350 8100 4350
Wire Wire Line
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9250 5500 8400 5500
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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9200 6150 8350 6150
Wire Wire Line
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Wire Wire Line
@ -349,37 +327,59 @@ Wire Wire Line
5500 3950 6400 3950
Wire Wire Line
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Text Label 9844 1300 0 60 ~ 0
Wire Wire Line
8300 4350 9300 4350
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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L CONN_25X2 P1
U 1 1 4CBAFE50
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1 6800 3550
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FPGA_BANK0_IO_59
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FPGA_BANK0_IO_57
Text Label 5500 4250 0 60 ~ 0
FPGA_BANK0_IO_56
Text Label 9844 700 0 60 ~ 0
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FPGA_BANK0_IO_64
Text Label 9844 1100 0 60 ~ 0
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FPGA_BANK0_IO_60
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FPGA_BANK0_IO_61
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FPGA_BANK0_IO_63
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FPGA_BANK0_IO_62
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FPGA_BANK0_IO_54
Text Label 9844 1600 0 60 ~ 0
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FPGA_BANK0_IO_55
Text Label 9844 1800 0 60 ~ 0
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FPGA_BANK0_IO_53
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FPGA_BANK0_IO_52
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FPGA_BANK0_IO_50
Text Label 9844 2000 0 60 ~ 0
Text Label 5500 4350 0 60 ~ 0
FPGA_BANK0_IO_51
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FPGA_BANK0_IO_49
Text Label 7250 4250 0 60 ~ 0
FPGA_BANK0_IO_48
@ -391,11 +391,11 @@ Text Label 5500 4050 0 60 ~ 0
FPGA_BANK0_IO_45
Text Label 5500 3850 0 60 ~ 0
FPGA_BANK0_IO_44
Text Label 9844 2900 0 60 ~ 0
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FPGA_BANK0_IO_42
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FPGA_BANK0_IO_43
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FPGA_BANK0_IO_41
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FPGA_BANK0_IO_40
@ -407,7 +407,7 @@ Text Label 9844 3400 0 60 ~ 0
FPGA_BANK0_IO_37
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FPGA_BANK0_IO_35
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FPGA_BANK0_IO_34
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FPGA_BANK0_IO_36

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 3 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A4 11700 8267
Sheet 4 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""

View File

@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Thu 04 Nov 2010 09:12:26 PM COT
EESchema-LIBRARY Version 2.3 Date: Sun 07 Nov 2010 12:36:16 PM COT
#
# +1.2V
#

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@ -1,4 +1,4 @@
update=Thu 04 Nov 2010 09:12:34 PM COT
update=Sun 07 Nov 2010 12:36:23 PM COT
version=1
last_client=kicad
[common]

View File

@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Thu 04 Nov 2010 09:12:26 PM COT
EESchema Schematic File Version 2 date Sun 07 Nov 2010 12:36:16 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -57,7 +57,7 @@ EELAYER END
$Descr A3 16535 11700
Sheet 1 12
Title ""
Date "5 nov 2010"
Date "7 nov 2010"
Rev ""
Comp ""
Comment1 ""