From 8cf60ceb3c8640f8347f3ee19306846420ce921d Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Mon, 16 Aug 2010 21:49:00 -0500 Subject: [PATCH] PSU controller added --- kicad/modules/clean | 4 + kicad/xue-rnc/DRAM.sch | 66 +- kicad/xue-rnc/FPGA.sch | 74 +- kicad/xue-rnc/NV_MEMORIES.sch | 34 +- kicad/xue-rnc/PSU.sch | 24 +- kicad/xue-rnc/USB.sch | 82 +- kicad/xue-rnc/eth_phy.sch | 2 +- kicad/xue-rnc/xue-rnc-cache.lib | 2 +- kicad/xue-rnc/xue-rnc.brd | 1535 +++++++++++++++++-------------- kicad/xue-rnc/xue-rnc.net | 1400 ++++++++++++++-------------- kicad/xue-rnc/xue-rnc.pro | 2 +- kicad/xue-rnc/xue-rnc.sch | 2 +- 12 files changed, 1719 insertions(+), 1508 deletions(-) create mode 100755 kicad/modules/clean diff --git a/kicad/modules/clean b/kicad/modules/clean new file mode 100755 index 0000000..ead43ca --- /dev/null +++ b/kicad/modules/clean @@ -0,0 +1,4 @@ +rm *~* +rm *.0* +rm *savepcb.brd +rm *bak diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 3f4e1cb..2f22d7b 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:05:01 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -530,19 +530,19 @@ Entry Wire Line Entry Wire Line 10100 4400 10200 4500 $Comp -L GND #PWR16 +L GND #PWR048 U 1 1 4C699C4D P 9950 2100 -F 0 "#PWR16" H 9950 2100 30 0001 C CNN +F 0 "#PWR048" H 9950 2100 30 0001 C CNN F 1 "GND" H 9950 2030 30 0001 C CNN 1 9950 2100 1 0 0 -1 $EndComp $Comp -L GND #PWR8 +L GND #PWR049 U 1 1 4C699C48 P 4550 2150 -F 0 "#PWR8" H 4550 2150 30 0001 C CNN +F 0 "#PWR049" H 4550 2150 30 0001 C CNN F 1 "GND" H 4550 2080 30 0001 C CNN 1 4550 2150 1 0 0 -1 @@ -600,37 +600,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR10 +L GND #PWR050 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR10" H 6900 6200 30 0001 C CNN +F 0 "#PWR050" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR9 +L +2.5V #PWR051 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR9" H 6900 5750 20 0001 C CNN +F 0 "#PWR051" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR1 +L +2.5V #PWR052 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR1" H 1700 5750 20 0001 C CNN +F 0 "#PWR052" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR2 +L GND #PWR053 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR2" H 1700 6200 30 0001 C CNN +F 0 "#PWR053" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -646,19 +646,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR4 +L +2.5V #PWR054 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR4" H 3050 1700 20 0001 C CNN +F 0 "#PWR054" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR14 +L +2.5V #PWR055 U 1 1 4C61CFC6 P 8400 1700 -F 0 "#PWR14" H 8400 1650 20 0001 C CNN +F 0 "#PWR055" H 8400 1650 20 0001 C CNN F 1 "+2.5V" H 8400 1800 30 0000 C CNN 1 8400 1700 1 0 0 -1 @@ -724,37 +724,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR11 +L +2.5V #PWR056 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR11" H 8300 5700 20 0001 C CNN +F 0 "#PWR056" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR12 +L GND #PWR057 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR12" H 8300 6350 30 0001 C CNN +F 0 "#PWR057" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR6 +L GND #PWR058 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR6" H 3050 6350 30 0001 C CNN +F 0 "#PWR058" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR5 +L +2.5V #PWR059 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR5" H 3050 5700 20 0001 C CNN +F 0 "#PWR059" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -840,19 +840,19 @@ F 2 "0402" H 9950 1750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR15 +L +2.5V #PWR060 U 1 1 4C61CE2F P 9950 800 -F 0 "#PWR15" H 9950 750 20 0001 C CNN +F 0 "#PWR060" H 9950 750 20 0001 C CNN F 1 "+2.5V" H 9950 900 30 0000 C CNN 1 9950 800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR7 +L +2.5V #PWR061 U 1 1 4C61CDF1 P 4550 850 -F 0 "#PWR7" H 4550 800 20 0001 C CNN +F 0 "#PWR061" H 4550 800 20 0001 C CNN F 1 "+2.5V" H 4550 950 30 0000 C CNN 1 4550 850 1 0 0 -1 @@ -935,10 +935,10 @@ $EndComp Text HLabel 5000 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR3 +L GND #PWR062 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR3" H 3000 5200 30 0001 C CNN +F 0 "#PWR062" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1214,10 +1214,10 @@ Entry Wire Line Entry Wire Line 10100 3600 10200 3700 $Comp -L GND #PWR13 +L GND #PWR063 U 1 1 4C437C3F P 8350 5150 -F 0 "#PWR13" H 8350 5150 30 0001 C CNN +F 0 "#PWR063" H 8350 5150 30 0001 C CNN F 1 "GND" H 8350 5080 30 0001 C CNN 1 8350 5150 1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 4243e2c..5cfbdef 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:05:01 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -1632,28 +1632,28 @@ VCC02 Text GLabel 5300 6250 3 30 BiDi ~ 0 VCCO2 $Comp -L +3.3V #PWR30 +L +3.3V #PWR030 U 1 1 4C65CF66 P 1650 14300 -F 0 "#PWR30" H 1650 14260 30 0001 C CNN +F 0 "#PWR030" H 1650 14260 30 0001 C CNN F 1 "+3.3V" H 1650 14410 30 0000 C CNN 1 1650 14300 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR35 +L +2.5V #PWR031 U 1 1 4C65C84B P 4600 14300 -F 0 "#PWR35" H 4600 14250 20 0001 C CNN +F 0 "#PWR031" H 4600 14250 20 0001 C CNN F 1 "+2.5V" H 4600 14400 30 0000 C CNN 1 4600 14300 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR32 +L +2.5V #PWR032 U 1 1 4C65C837 P 4600 12350 -F 0 "#PWR32" H 4600 12300 20 0001 C CNN +F 0 "#PWR032" H 4600 12300 20 0001 C CNN F 1 "+2.5V" H 4600 12450 30 0000 C CNN 1 4600 12350 1 0 0 -1 @@ -1700,10 +1700,10 @@ F 1 "470nF" H 6050 12550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR33 +L GND #PWR033 U 1 1 4C656D9B P 4600 12950 -F 0 "#PWR33" H 4600 12950 30 0001 C CNN +F 0 "#PWR033" H 4600 12950 30 0001 C CNN F 1 "GND" H 4600 12880 30 0001 C CNN 1 4600 12950 1 0 0 -1 @@ -1765,10 +1765,10 @@ F 1 "470nF" H 6050 13550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR34 +L GND #PWR034 U 1 1 4C656D47 P 4600 13950 -F 0 "#PWR34" H 4600 13950 30 0001 C CNN +F 0 "#PWR034" H 4600 13950 30 0001 C CNN F 1 "GND" H 4600 13880 30 0001 C CNN 1 4600 13950 1 0 0 -1 @@ -1821,10 +1821,10 @@ F 1 "470nF" H 6050 14500 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR36 +L GND #PWR035 U 1 1 4C656CFD P 4600 14900 -F 0 "#PWR36" H 4600 14900 30 0001 C CNN +F 0 "#PWR035" H 4600 14900 30 0001 C CNN F 1 "GND" H 4600 14830 30 0001 C CNN 1 4600 14900 1 0 0 -1 @@ -1868,10 +1868,10 @@ F 1 "100uF" H 4650 14500 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR31 +L GND #PWR036 U 1 1 4C656CBC P 1650 14900 -F 0 "#PWR31" H 1650 14900 30 0001 C CNN +F 0 "#PWR036" H 1650 14900 30 0001 C CNN F 1 "GND" H 1650 14830 30 0001 C CNN 1 1650 14900 1 0 0 -1 @@ -1917,10 +1917,10 @@ $EndComp Text Notes 1750 13400 0 30 ~ 0 VCC_AUX Decoupling Capacitors (7) $Comp -L GND #PWR29 +L GND #PWR037 U 1 1 4C656C68 P 1650 14000 -F 0 "#PWR29" H 1650 14000 30 0001 C CNN +F 0 "#PWR037" H 1650 14000 30 0001 C CNN F 1 "GND" H 1650 13930 30 0001 C CNN 1 1650 14000 1 0 0 -1 @@ -1989,19 +1989,19 @@ F 1 "100uF" H 1700 13600 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR28 +L +2.5V #PWR038 U 1 1 4C656BBA P 1650 13400 -F 0 "#PWR28" H 1650 13350 20 0001 C CNN +F 0 "#PWR038" H 1650 13350 20 0001 C CNN F 1 "+2.5V" H 1650 13500 30 0000 C CNN 1 1650 13400 1 0 0 -1 $EndComp $Comp -L GND #PWR27 +L GND #PWR039 U 1 1 4C656BA8 P 1650 12950 -F 0 "#PWR27" H 1650 12950 30 0001 C CNN +F 0 "#PWR039" H 1650 12950 30 0001 C CNN F 1 "GND" H 1650 12880 30 0001 C CNN 1 1650 12950 1 0 0 -1 @@ -2036,10 +2036,10 @@ F 1 "4.7uF" H 2050 12550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR26 +L +1.2V #PWR040 U 1 1 4C656AA1 P 1650 12350 -F 0 "#PWR26" H 1650 12490 20 0001 C CNN +F 0 "#PWR040" H 1650 12490 20 0001 C CNN F 1 "+1.2V" H 1650 12460 30 0000 C CNN 1 1650 12350 1 0 0 -1 @@ -2104,46 +2104,46 @@ NF_RE_N Text HLabel 18000 7250 2 60 BiDi ~ 0 NF_RNB $Comp -L +3.3V #PWR39 +L +3.3V #PWR041 U 1 1 4C61E5B3 P 15900 6100 -F 0 "#PWR39" H 15900 6060 30 0001 C CNN +F 0 "#PWR041" H 15900 6060 30 0001 C CNN F 1 "+3.3V" H 15900 6210 30 0000 C CNN 1 15900 6100 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR41 +L +1.2V #PWR042 U 1 1 4C61E58C P 16500 9850 -F 0 "#PWR41" H 16500 9990 20 0001 C CNN +F 0 "#PWR042" H 16500 9990 20 0001 C CNN F 1 "+1.2V" H 16500 9960 30 0000 C CNN 1 16500 9850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR38 +L +2.5V #PWR043 U 1 1 4C61E577 P 15000 9850 -F 0 "#PWR38" H 15000 9800 20 0001 C CNN +F 0 "#PWR043" H 15000 9800 20 0001 C CNN F 1 "+2.5V" H 15000 9950 30 0000 C CNN 1 15000 9850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR42 +L +2.5V #PWR044 U 1 1 4C61E523 P 19700 650 -F 0 "#PWR42" H 19700 600 20 0001 C CNN +F 0 "#PWR044" H 19700 600 20 0001 C CNN F 1 "+2.5V" H 19700 750 30 0000 C CNN 1 19700 650 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR37 +L +2.5V #PWR045 U 1 1 4C61E51F P 8100 650 -F 0 "#PWR37" H 8100 600 20 0001 C CNN +F 0 "#PWR045" H 8100 600 20 0001 C CNN F 1 "+2.5V" H 8100 750 30 0000 C CNN 1 8100 650 1 0 0 -1 @@ -2189,10 +2189,10 @@ M0_BA[0..1] Text HLabel 15750 3950 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR25 +L GND #PWR046 U 1 1 4C60C21D P 1600 5950 -F 0 "#PWR25" H 1600 5950 30 0001 C CNN +F 0 "#PWR046" H 1600 5950 30 0001 C CNN F 1 "GND" H 1600 5880 30 0001 C CNN 1 1600 5950 -1 0 0 -1 @@ -2620,10 +2620,10 @@ M0_CLK Text HLabel 10550 4700 2 60 Output ~ 0 M0_CLK# $Comp -L GND #PWR40 +L GND #PWR047 U 1 1 4C439B7E P 16400 12650 -F 0 "#PWR40" H 16400 12650 30 0001 C CNN +F 0 "#PWR047" H 16400 12650 30 0001 C CNN F 1 "GND" H 16400 12580 30 0001 C CNN 1 16400 12650 -1 0 0 -1 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 5c2e209..24ff1fc 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:05:01 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -243,19 +243,19 @@ F 1 "100nF" H 4000 5400 50 0000 L CNN -1 0 0 1 $EndComp $Comp -L GND #PWR24 +L GND #PWR02 U 1 1 4C65D6AB P 9350 3150 -F 0 "#PWR24" H 9350 3150 30 0001 C CNN +F 0 "#PWR02" H 9350 3150 30 0001 C CNN F 1 "GND" H 9350 3080 30 0001 C CNN 1 9350 3150 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR23 +L +3.3V #PWR03 U 1 1 4C65D69B P 9350 2650 -F 0 "#PWR23" H 9350 2610 30 0001 C CNN +F 0 "#PWR03" H 9350 2610 30 0001 C CNN F 1 "+3.3V" H 9350 2760 30 0000 C CNN 1 9350 2650 1 0 0 -1 @@ -319,10 +319,10 @@ SPI_DQ[0..3] Text HLabel 2450 1700 0 60 Input ~ 0 SPI_FLASH_CS# $Comp -L GND #PWR17 +L GND #PWR04 U 1 1 4C65ABE9 P 2650 2450 -F 0 "#PWR17" H 2650 2450 30 0001 C CNN +F 0 "#PWR04" H 2650 2450 30 0001 C CNN F 1 "GND" H 2650 2380 30 0001 C CNN 1 2650 2450 1 0 0 -1 @@ -355,19 +355,19 @@ Entry Wire Line Entry Wire Line 8150 3150 8250 3050 $Comp -L +3.3V #PWR21 +L +3.3V #PWR05 U 1 1 4C646C14 P 7950 2900 -F 0 "#PWR21" H 7950 2860 30 0001 C CNN +F 0 "#PWR05" H 7950 2860 30 0001 C CNN F 1 "+3.3V" H 7950 3010 30 0000 C CNN 1 7950 2900 1 0 0 -1 $EndComp $Comp -L GND #PWR22 +L GND #PWR06 U 1 1 4C646BEA P 7950 3000 -F 0 "#PWR22" H 7950 3000 30 0001 C CNN +F 0 "#PWR06" H 7950 3000 30 0001 C CNN F 1 "GND" H 7950 2930 30 0001 C CNN 1 7950 3000 1 0 0 -1 @@ -417,10 +417,10 @@ SD_DAT3 Text Label 4200 6100 0 30 ~ 0 SD_CMD $Comp -L GND #PWR18 +L GND #PWR07 U 1 1 4C61D875 P 3950 5800 -F 0 "#PWR18" H 3950 5800 30 0001 C CNN +F 0 "#PWR07" H 3950 5800 30 0001 C CNN F 1 "GND" H 3950 5730 30 0001 C CNN 1 3950 5800 1 0 0 -1 @@ -432,19 +432,19 @@ SD_DAT0 Text Label 4200 5850 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR20 +L GND #PWR08 U 1 1 4C438ADC P 5800 6200 -F 0 "#PWR20" H 5800 6200 30 0001 C CNN +F 0 "#PWR08" H 5800 6200 30 0001 C CNN F 1 "GND" H 5800 6130 30 0001 C CNN 1 5800 6200 1 0 0 -1 $EndComp $Comp -L GND #PWR19 +L GND #PWR09 U 1 1 4C438AD5 P 5350 6550 -F 0 "#PWR19" H 5350 6550 30 0001 C CNN +F 0 "#PWR09" H 5350 6550 30 0001 C CNN F 1 "GND" H 5350 6480 30 0001 C CNN 1 5350 6550 1 0 0 -1 diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index dbb20f2..e01466a 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:05:01 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,6 +58,28 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Wire Line + 4200 1950 4200 2050 +Wire Wire Line + 4200 2050 4400 2050 +Wire Wire Line + 4200 2200 4200 2150 +Wire Wire Line + 4350 2150 4350 2250 +Wire Wire Line + 4350 2250 4400 2250 +Wire Wire Line + 4200 2150 4400 2150 +Connection ~ 4350 2150 +$Comp +L GND #PWR01 +U 1 1 4C69F7A5 +P 4200 2200 +F 0 "#PWR01" H 4200 2200 30 0001 C CNN +F 1 "GND" H 4200 2130 30 0001 C CNN + 1 4200 2200 + 1 0 0 -1 +$EndComp $Comp L ATTINY24A-MLF U9 U 1 1 4C69EE11 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 7512fae..6d46284 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:05:01 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -59,37 +59,37 @@ Comment3 "" Comment4 "" $EndDescr $Comp -L +3.3V #PWR52 +L +3.3V #PWR010 U 1 1 4C695F50 P 2700 4600 -F 0 "#PWR52" H 2700 4560 30 0001 C CNN +F 0 "#PWR010" H 2700 4560 30 0001 C CNN F 1 "+3.3V" H 2700 4710 30 0000 C CNN 1 2700 4600 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR48 +L +3.3V #PWR011 U 1 1 4C695F4B P 2550 6100 -F 0 "#PWR48" H 2550 6060 30 0001 C CNN +F 0 "#PWR011" H 2550 6060 30 0001 C CNN F 1 "+3.3V" H 2550 6210 30 0000 C CNN 1 2550 6100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR50 +L +3.3V #PWR012 U 1 1 4C695F43 P 2650 1100 -F 0 "#PWR50" H 2650 1060 30 0001 C CNN +F 0 "#PWR012" H 2650 1060 30 0001 C CNN F 1 "+3.3V" H 2650 1210 30 0000 C CNN 1 2650 1100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR47 +L +3.3V #PWR013 U 1 1 4C695F3B P 2500 2400 -F 0 "#PWR47" H 2500 2360 30 0001 C CNN +F 0 "#PWR013" H 2500 2360 30 0001 C CNN F 1 "+3.3V" H 2500 2510 30 0000 C CNN 1 2500 2400 1 0 0 -1 @@ -325,55 +325,55 @@ Connection ~ 2650 1200 Wire Wire Line 3200 5000 3200 4550 $Comp -L +2.5V #PWR55 +L +2.5V #PWR014 U 1 1 4C695DCD P 3200 4550 -F 0 "#PWR55" H 3200 4500 20 0001 C CNN +F 0 "#PWR014" H 3200 4500 20 0001 C CNN F 1 "+2.5V" H 3200 4650 30 0000 C CNN 1 3200 4550 1 0 0 -1 $EndComp $Comp -L GND #PWR56 +L GND #PWR015 U 1 1 4C695F0A P 3200 5550 -F 0 "#PWR56" H 3200 5550 30 0001 C CNN +F 0 "#PWR015" H 3200 5550 30 0001 C CNN F 1 "GND" H 3200 5480 30 0001 C CNN 1 3200 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR51 +L GND #PWR016 U 1 1 4C695F09 P 2650 5550 -F 0 "#PWR51" H 2650 5550 30 0001 C CNN +F 0 "#PWR016" H 2650 5550 30 0001 C CNN F 1 "GND" H 2650 5480 30 0001 C CNN 1 2650 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR54 +L GND #PWR017 U 1 1 4C695DFE P 3150 1850 -F 0 "#PWR54" H 3150 1850 30 0001 C CNN +F 0 "#PWR017" H 3150 1850 30 0001 C CNN F 1 "GND" H 3150 1780 30 0001 C CNN 1 3150 1850 1 0 0 -1 $EndComp $Comp -L GND #PWR49 +L GND #PWR018 U 1 1 4C695DF8 P 2600 1850 -F 0 "#PWR49" H 2600 1850 30 0001 C CNN +F 0 "#PWR018" H 2600 1850 30 0001 C CNN F 1 "GND" H 2600 1780 30 0001 C CNN 1 2600 1850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR53 +L +2.5V #PWR019 U 1 1 4C695DA7 P 3150 1100 -F 0 "#PWR53" H 3150 1050 20 0001 C CNN +F 0 "#PWR019" H 3150 1050 20 0001 C CNN F 1 "+2.5V" H 3150 1200 30 0000 C CNN 1 3150 1100 1 0 0 -1 @@ -470,28 +470,28 @@ USBD_VP Text HLabel 1650 6750 0 40 BiDi ~ 0 USBD_VM $Comp -L GND #PWR62 +L GND #PWR020 U 1 1 4C6552B5 P 5650 7450 -F 0 "#PWR62" H 5650 7450 30 0001 C CNN +F 0 "#PWR020" H 5650 7450 30 0001 C CNN F 1 "GND" H 5650 7380 30 0001 C CNN 1 5650 7450 1 0 0 -1 $EndComp $Comp -L GND #PWR46 +L GND #PWR021 U 1 1 4C6552B4 P 2200 7500 -F 0 "#PWR46" H 2200 7500 30 0001 C CNN +F 0 "#PWR021" H 2200 7500 30 0001 C CNN F 1 "GND" H 2200 7430 30 0001 C CNN 1 2200 7500 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR44 +L +2.5V #PWR022 U 1 1 4C6552B2 P 1600 6150 -F 0 "#PWR44" H 1600 6100 20 0001 C CNN +F 0 "#PWR022" H 1600 6100 20 0001 C CNN F 1 "+2.5V" H 1600 6250 30 0000 C CNN 1 1600 6150 1 0 0 -1 @@ -517,37 +517,37 @@ F 2 "0603" H 4400 6050 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +5V #PWR58 +L +5V #PWR023 U 1 1 4C6552AF P 4400 5050 -F 0 "#PWR58" H 4400 5140 20 0001 C CNN +F 0 "#PWR023" H 4400 5140 20 0001 C CNN F 1 "+5V" H 4400 5140 30 0000 C CNN 1 4400 5050 1 0 0 -1 $EndComp $Comp -L GND #PWR60 +L GND #PWR024 U 1 1 4C6552AE P 4600 7400 -F 0 "#PWR60" H 4600 7400 30 0001 C CNN +F 0 "#PWR024" H 4600 7400 30 0001 C CNN F 1 "GND" H 4600 7330 30 0001 C CNN 1 4600 7400 1 0 0 -1 $EndComp $Comp -L GND #PWR59 +L GND #PWR025 U 1 1 4C63F2B5 P 4550 3700 -F 0 "#PWR59" H 4550 3700 30 0001 C CNN +F 0 "#PWR025" H 4550 3700 30 0001 C CNN F 1 "GND" H 4550 3630 30 0001 C CNN 1 4550 3700 1 0 0 -1 $EndComp $Comp -L +5V #PWR57 +L +5V #PWR026 U 1 1 4C63F295 P 4350 1350 -F 0 "#PWR57" H 4350 1440 20 0001 C CNN +F 0 "#PWR026" H 4350 1440 20 0001 C CNN F 1 "+5V" H 4350 1440 30 0000 C CNN 1 4350 1350 1 0 0 -1 @@ -573,28 +573,28 @@ F 2 "0603" H 4550 3350 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR43 +L +2.5V #PWR027 U 1 1 4C63EC16 P 1550 2450 -F 0 "#PWR43" H 1550 2400 20 0001 C CNN +F 0 "#PWR027" H 1550 2400 20 0001 C CNN F 1 "+2.5V" H 1550 2550 30 0000 C CNN 1 1550 2450 1 0 0 -1 $EndComp $Comp -L GND #PWR45 +L GND #PWR028 U 1 1 4C63EA1B P 2150 3800 -F 0 "#PWR45" H 2150 3800 30 0001 C CNN +F 0 "#PWR028" H 2150 3800 30 0001 C CNN F 1 "GND" H 2150 3730 30 0001 C CNN 1 2150 3800 1 0 0 -1 $EndComp $Comp -L GND #PWR61 +L GND #PWR029 U 1 1 4C63E9FA P 5600 3750 -F 0 "#PWR61" H 5600 3750 30 0001 C CNN +F 0 "#PWR029" H 5600 3750 30 0001 C CNN F 1 "GND" H 5600 3680 30 0001 C CNN 1 5600 3750 1 0 0 -1 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index dbd78ab..8c2c111 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:05:01 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 9118d7c..fe316cd 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Mon 16 Aug 2010 09:05:01 PM COT +EESchema-LIBRARY Version 2.3 Date: Mon 16 Aug 2010 09:46:10 PM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 8937da0..7b81448 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Mon 16 Aug 2010 08:54:48 PM COT +PCBNEW-BOARD Version 1 date Mon 16 Aug 2010 09:47:05 PM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -6,14 +6,14 @@ $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 1FFF801F -Links 590 -NoConn 590 -Di 45200 13449 70210 50668 +Links 595 +NoConn 595 +Di 45200 13510 70149 50668 Ndraw 7 Ntrack 0 Nzone 0 BoardThickness 630 -Nmodule 128 +Nmodule 129 Nnets 207 $EndGENERAL @@ -39,21 +39,21 @@ Layer[2] Inner3 signal Layer[3] Inner4 signal Layer[4] Inner5 signal Layer[15] Front signal -TrackWidth 80 -TrackClearence 100 +TrackWidth 39 +TrackClearence 39 ZoneClearence 200 -TrackMinWidth 80 +TrackMinWidth 39 DrawSegmWidth 150 EdgeSegmWidth 150 -ViaSize 350 -ViaDrill 250 -ViaMinSize 350 -ViaMinDrill 200 -MicroViaSize 200 -MicroViaDrill 50 +ViaSize 197 +ViaDrill 79 +ViaMinSize 197 +ViaMinDrill 79 +MicroViaSize 197 +MicroViaDrill 79 MicroViasAllowed 0 -MicroViaMinSize 200 -MicroViaMinDrill 50 +MicroViaMinSize 197 +MicroViaMinDrill 59 TextPcbWidth 120 TextPcbSize 600 800 EdgeModWidth 59 @@ -90,31 +90,31 @@ Na 5 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A0" +Na 6 "/DDR_Banks/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_A1" +Na 7 "/DDR_Banks/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_A2" +Na 8 "/DDR_Banks/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_A3" +Na 9 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_A6" +Na 10 "/DDR_Banks/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_A8" +Na 11 "/DDR_Banks/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_BA0" +Na 12 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT @@ -122,11 +122,11 @@ Na 13 "/DDR_Banks/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_DQ5" +Na 14 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_DQ6" +Na 15 "/DDR_Banks/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT @@ -138,403 +138,403 @@ Na 17 "/DDR_Banks/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_RAS#" +Na 18 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_UDM" +Na 19 "/DDR_Banks/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M0_WE#" +Na 20 "/DDR_Banks/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M1_A1" +Na 21 "/DDR_Banks/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M1_A10" +Na 22 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_A4" +Na 23 "/DDR_Banks/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_A7" +Na 24 "/DDR_Banks/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_A8" +Na 25 "/DDR_Banks/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_BA0" +Na 26 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_CAS#" +Na 27 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_CKE" +Na 28 "/DDR_Banks/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_CLK" +Na 29 "/DDR_Banks/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_CLK#" +Na 30 "/DDR_Banks/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_DQ0" +Na 31 "/DDR_Banks/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_DQ1" +Na 32 "/DDR_Banks/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_DQ13" +Na 33 "/DDR_Banks/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_DQ14" +Na 34 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_DQ15" +Na 35 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/DDR_Banks/M1_DQ4" +Na 36 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/DDR_Banks/M1_DQ6" +Na 37 "/DDR_Banks/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M1_LDQS" +Na 38 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/DDR_Banks/M1_RAS#" +Na 39 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/DDR_Banks/M1_UDM" +Na 40 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/DDR_Banks/M1_WE#" +Na 41 "/Ethernet_Phy/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_A1.8V" +Na 42 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_A3.3V" +Na 43 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_LED0" +Na 44 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_LED1" +Na 45 "/Ethernet_Phy/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_MDC" +Na 46 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_PLL1.8V" +Na 47 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_RXC" +Na 48 "/Ethernet_Phy/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_RXD0" +Na 49 "/Ethernet_Phy/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/ETH_RXD1" +Na 50 "/Ethernet_Phy/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Ethernet_Phy/ETH_RXER" +Na 51 "/Ethernet_Phy/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/Ethernet_Phy/ETH_TXD0" +Na 52 "/FPGA_Spartan6/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/Ethernet_Phy/ETH_TXD1" +Na 53 "/FPGA_Spartan6/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/Ethernet_Phy/ETH_TXD3" +Na 54 "/FPGA_Spartan6/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/Ethernet_Phy/ETH_TXEN" +Na 55 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/ETH_CLK" +Na 56 "/FPGA_Spartan6/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/ETH_COL" +Na 57 "/FPGA_Spartan6/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/ETH_CRS" +Na 58 "/FPGA_Spartan6/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/ETH_INT" +Na 59 "/FPGA_Spartan6/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/ETH_MDIO" +Na 60 "/FPGA_Spartan6/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/ETH_RESET_N" +Na 61 "/FPGA_Spartan6/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/ETH_RXD2" +Na 62 "/FPGA_Spartan6/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/ETH_RXD3" +Na 63 "/FPGA_Spartan6/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/ETH_RXDV" +Na 64 "/FPGA_Spartan6/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/ETH_TXC" +Na 65 "/FPGA_Spartan6/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/ETH_TXD2" +Na 66 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/ETH_TXER" +Na 67 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/M0_A10" +Na 68 "/FPGA_Spartan6/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_A11" +Na 69 "/FPGA_Spartan6/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_A12" +Na 70 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_A4" +Na 71 "/FPGA_Spartan6/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_A5" +Na 72 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_A7" +Na 73 "/FPGA_Spartan6/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_A9" +Na 74 "/FPGA_Spartan6/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_BA1" +Na 75 "/FPGA_Spartan6/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_CAS#" +Na 76 "/FPGA_Spartan6/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_CKE" +Na 77 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_CLK" +Na 78 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_CLK#" +Na 79 "/FPGA_Spartan6/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_DQ0" +Na 80 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_DQ1" +Na 81 "/FPGA_Spartan6/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_DQ10" +Na 82 "/FPGA_Spartan6/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_DQ11" +Na 83 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_DQ12" +Na 84 "/FPGA_Spartan6/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M0_DQ14" +Na 85 "/FPGA_Spartan6/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M0_DQ15" +Na 86 "/FPGA_Spartan6/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M0_DQ2" +Na 87 "/FPGA_Spartan6/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M0_DQ3" +Na 88 "/FPGA_Spartan6/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M0_DQ4" +Na 89 "/FPGA_Spartan6/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M0_DQ8" +Na 90 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M0_LDM" +Na 91 "/FPGA_Spartan6/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M0_LDQS" +Na 92 "/FPGA_Spartan6/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M0_UDQS" +Na 93 "/FPGA_Spartan6/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_A0" +Na 94 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_A11" +Na 95 "/FPGA_Spartan6/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_A12" +Na 96 "/FPGA_Spartan6/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_A2" +Na 97 "/FPGA_Spartan6/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_A3" +Na 98 "/FPGA_Spartan6/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_A5" +Na 99 "/FPGA_Spartan6/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_A6" +Na 100 "/FPGA_Spartan6/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_A9" +Na 101 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_BA1" +Na 102 "/FPGA_Spartan6/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_CS#" +Na 103 "/FPGA_Spartan6/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_DQ10" +Na 104 "/FPGA_Spartan6/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ11" +Na 105 "/FPGA_Spartan6/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_DQ12" +Na 106 "/FPGA_Spartan6/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_DQ2" +Na 107 "/FPGA_Spartan6/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_DQ3" +Na 108 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ5" +Na 109 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_DQ7" +Na 110 "/FPGA_Spartan6/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_DQ8" +Na 111 "/FPGA_Spartan6/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Spartan6/M1_DQ9" +Na 112 "/FPGA_Spartan6/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_LDM" +Na 113 "/FPGA_Spartan6/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Spartan6/M1_UDQS" +Na 114 "/FPGA_Spartan6/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/NF_ALE" +Na 115 "/FPGA_Spartan6/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/NF_CLE" +Na 116 "/FPGA_Spartan6/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Spartan6/NF_CS1_N" +Na 117 "/FPGA_Spartan6/NF_D2" St ~ $EndEQUIPOT $EQUIPOT @@ -542,239 +542,239 @@ Na 118 "/FPGA_Spartan6/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/NF_D7" +Na 119 "/FPGA_Spartan6/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Spartan6/NF_RNB" +Na 120 "/FPGA_Spartan6/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Spartan6/NF_WE_N" +Na 121 "/FPGA_Spartan6/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Spartan6/PROG_CCLK" +Na 122 "/FPGA_Spartan6/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Spartan6/PROG_CSO" +Na 123 "/FPGA_Spartan6/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Spartan6/PROG_MISO0" +Na 124 "/FPGA_Spartan6/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Spartan6/PROG_MISO1" +Na 125 "/FPGA_Spartan6/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Spartan6/PROG_MISO2" +Na 126 "/FPGA_Spartan6/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Spartan6/PROG_MISO3" +Na 127 "/FPGA_Spartan6/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Spartan6/R_M1_A0" +Na 128 "/FPGA_Spartan6/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/FPGA_Spartan6/R_M1_A1" +Na 129 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/FPGA_Spartan6/R_M1_A10" +Na 130 "/FPGA_Spartan6/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/FPGA_Spartan6/R_M1_A11" +Na 131 "/FPGA_Spartan6/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/FPGA_Spartan6/R_M1_A12" +Na 132 "/FPGA_Spartan6/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/FPGA_Spartan6/R_M1_A2" +Na 133 "/FPGA_Spartan6/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/FPGA_Spartan6/R_M1_A3" +Na 134 "/FPGA_Spartan6/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/FPGA_Spartan6/R_M1_A5" +Na 135 "/FPGA_Spartan6/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/FPGA_Spartan6/R_M1_A6" +Na 136 "/FPGA_Spartan6/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/FPGA_Spartan6/R_M1_A7" +Na 137 "/FPGA_Spartan6/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/FPGA_Spartan6/R_M1_A8" +Na 138 "/FPGA_Spartan6/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/FPGA_Spartan6/R_M1_A9" +Na 139 "/FPGA_Spartan6/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/FPGA_Spartan6/R_M1_BA0" +Na 140 "/FPGA_Spartan6/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/FPGA_Spartan6/R_M1_BA1" +Na 141 "/FPGA_Spartan6/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/FPGA_Spartan6/R_M1_CAS#" +Na 142 "/FPGA_Spartan6/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/FPGA_Spartan6/R_M1_CKE" +Na 143 "/FPGA_Spartan6/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/FPGA_Spartan6/R_M1_CS#" +Na 144 "/FPGA_Spartan6/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/FPGA_Spartan6/R_M1_DQ0" +Na 145 "/FPGA_Spartan6/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/FPGA_Spartan6/R_M1_DQ1" +Na 146 "/FPGA_Spartan6/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/FPGA_Spartan6/R_M1_DQ10" +Na 147 "/FPGA_Spartan6/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/FPGA_Spartan6/R_M1_DQ11" +Na 148 "/FPGA_Spartan6/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/FPGA_Spartan6/R_M1_DQ12" +Na 149 "/FPGA_Spartan6/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/FPGA_Spartan6/R_M1_DQ13" +Na 150 "/FPGA_Spartan6/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/FPGA_Spartan6/R_M1_DQ14" +Na 151 "/FPGA_Spartan6/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/FPGA_Spartan6/R_M1_DQ15" +Na 152 "/FPGA_Spartan6/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/FPGA_Spartan6/R_M1_DQ2" +Na 153 "/FPGA_Spartan6/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/FPGA_Spartan6/R_M1_DQ3" +Na 154 "/FPGA_Spartan6/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/FPGA_Spartan6/R_M1_DQ4" +Na 155 "/FPGA_Spartan6/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/FPGA_Spartan6/R_M1_DQ5" +Na 156 "/FPGA_Spartan6/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/FPGA_Spartan6/R_M1_DQ6" +Na 157 "/FPGA_Spartan6/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/FPGA_Spartan6/R_M1_DQ7" +Na 158 "/FPGA_Spartan6/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/FPGA_Spartan6/R_M1_DQ8" +Na 159 "/FPGA_Spartan6/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/FPGA_Spartan6/R_M1_DQ9" +Na 160 "/FPGA_Spartan6/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/FPGA_Spartan6/R_M1_LDM" +Na 161 "/FPGA_Spartan6/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/FPGA_Spartan6/R_M1_LDQS" +Na 162 "/FPGA_Spartan6/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/FPGA_Spartan6/R_M1_RAS#" +Na 163 "/FPGA_Spartan6/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/FPGA_Spartan6/R_M1_UDM" +Na 164 "/FPGA_Spartan6/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/FPGA_Spartan6/R_M1_UDQS" +Na 165 "/FPGA_Spartan6/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/FPGA_Spartan6/R_M1_WE#" +Na 166 "/FPGA_Spartan6/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/FPGA_Spartan6/SD_CMD" +Na 167 "/FPGA_Spartan6/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/FPGA_Spartan6/SD_DAT3" +Na 168 "/FPGA_Spartan6/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/FPGA_Spartan6/USBA_OE_N" +Na 169 "/FPGA_Spartan6/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/Non_volatile_memories/NF_D0" +Na 170 "/FPGA_Spartan6/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/Non_volatile_memories/NF_D1" +Na 171 "/FPGA_Spartan6/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/Non_volatile_memories/NF_D2" +Na 172 "/Non_volatile_memories/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/Non_volatile_memories/NF_D3" +Na 173 "/Non_volatile_memories/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/Non_volatile_memories/NF_D5" +Na 174 "/Non_volatile_memories/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/Non_volatile_memories/NF_D6" +Na 175 "/Non_volatile_memories/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/Non_volatile_memories/NF_RE_N" +Na 176 "/Non_volatile_memories/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/Non_volatile_memories/SD_CLK" +Na 177 "/Non_volatile_memories/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT @@ -790,15 +790,15 @@ Na 180 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/USB/USBA_RCV" +Na 181 "/Non_volatile_memories/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/USB/USBA_SPD" +Na 182 "/USB/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/USB/USBA_VM" +Na 183 "/USB/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT @@ -818,55 +818,55 @@ Na 187 "N-000059" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "N-000356" +Na 188 "N-000358" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "N-000357" +Na 189 "N-000361" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "N-000361" +Na 190 "N-000370" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "N-000363" +Na 191 "N-000371" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "N-000364" +Na 192 "N-000372" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "N-000365" +Na 193 "N-000373" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "N-000366" +Na 194 "N-000374" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "N-000367" +Na 195 "N-000376" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "N-000377" +Na 196 "N-000383" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "N-000381" +Na 197 "N-000384" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "N-000382" +Na 198 "N-000385" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "N-000385" +Na 199 "N-000386" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "N-000388" +Na 200 "N-000389" St ~ $EndEQUIPOT $EQUIPOT @@ -896,92 +896,89 @@ $EndEQUIPOT $NCLASS Name "Default" Desc "This is the default net class." -Clearance 100 -TrackWidth 80 -ViaDia 350 -ViaDrill 250 -uViaDia 200 -uViaDrill 50 +Clearance 39 +TrackWidth 39 +ViaDia 197 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 AddNet "" AddNet "+1.2V" AddNet "+1.8V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" -AddNet "/DDR_Banks/M0_A0" AddNet "/DDR_Banks/M0_A1" -AddNet "/DDR_Banks/M0_A2" -AddNet "/DDR_Banks/M0_A3" -AddNet "/DDR_Banks/M0_A6" -AddNet "/DDR_Banks/M0_A8" +AddNet "/DDR_Banks/M0_A11" +AddNet "/DDR_Banks/M0_A5" +AddNet "/DDR_Banks/M0_A7" AddNet "/DDR_Banks/M0_BA0" +AddNet "/DDR_Banks/M0_BA1" +AddNet "/DDR_Banks/M0_CLK#" AddNet "/DDR_Banks/M0_DQ13" +AddNet "/DDR_Banks/M0_DQ4" AddNet "/DDR_Banks/M0_DQ5" -AddNet "/DDR_Banks/M0_DQ6" AddNet "/DDR_Banks/M0_DQ7" AddNet "/DDR_Banks/M0_DQ9" +AddNet "/DDR_Banks/M0_LDQS" AddNet "/DDR_Banks/M0_RAS#" AddNet "/DDR_Banks/M0_UDM" +AddNet "/DDR_Banks/M0_UDQS" AddNet "/DDR_Banks/M0_WE#" -AddNet "/DDR_Banks/M1_A1" -AddNet "/DDR_Banks/M1_A10" +AddNet "/DDR_Banks/M1_A3" AddNet "/DDR_Banks/M1_A4" -AddNet "/DDR_Banks/M1_A7" -AddNet "/DDR_Banks/M1_A8" -AddNet "/DDR_Banks/M1_BA0" -AddNet "/DDR_Banks/M1_CAS#" -AddNet "/DDR_Banks/M1_CKE" +AddNet "/DDR_Banks/M1_BA1" AddNet "/DDR_Banks/M1_CLK" -AddNet "/DDR_Banks/M1_CLK#" -AddNet "/DDR_Banks/M1_DQ0" -AddNet "/DDR_Banks/M1_DQ1" -AddNet "/DDR_Banks/M1_DQ13" +AddNet "/DDR_Banks/M1_DQ10" +AddNet "/DDR_Banks/M1_DQ12" AddNet "/DDR_Banks/M1_DQ14" AddNet "/DDR_Banks/M1_DQ15" -AddNet "/DDR_Banks/M1_DQ4" AddNet "/DDR_Banks/M1_DQ6" +AddNet "/DDR_Banks/M1_DQ7" +AddNet "/DDR_Banks/M1_DQ9" +AddNet "/DDR_Banks/M1_LDM" AddNet "/DDR_Banks/M1_LDQS" AddNet "/DDR_Banks/M1_RAS#" -AddNet "/DDR_Banks/M1_UDM" +AddNet "/DDR_Banks/M1_UDQS" AddNet "/DDR_Banks/M1_WE#" AddNet "/Ethernet_Phy/ETH_A1.8V" AddNet "/Ethernet_Phy/ETH_A3.3V" +AddNet "/Ethernet_Phy/ETH_CRS" +AddNet "/Ethernet_Phy/ETH_INT" AddNet "/Ethernet_Phy/ETH_LED0" AddNet "/Ethernet_Phy/ETH_LED1" AddNet "/Ethernet_Phy/ETH_MDC" AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/ETH_RXC" -AddNet "/Ethernet_Phy/ETH_RXD0" AddNet "/Ethernet_Phy/ETH_RXD1" -AddNet "/Ethernet_Phy/ETH_RXER" -AddNet "/Ethernet_Phy/ETH_TXD0" -AddNet "/Ethernet_Phy/ETH_TXD1" -AddNet "/Ethernet_Phy/ETH_TXD3" +AddNet "/Ethernet_Phy/ETH_RXD3" +AddNet "/Ethernet_Phy/ETH_TXC" +AddNet "/Ethernet_Phy/ETH_TXD2" AddNet "/Ethernet_Phy/ETH_TXEN" AddNet "/FPGA_Spartan6/ETH_CLK" AddNet "/FPGA_Spartan6/ETH_COL" -AddNet "/FPGA_Spartan6/ETH_CRS" -AddNet "/FPGA_Spartan6/ETH_INT" AddNet "/FPGA_Spartan6/ETH_MDIO" AddNet "/FPGA_Spartan6/ETH_RESET_N" +AddNet "/FPGA_Spartan6/ETH_RXC" +AddNet "/FPGA_Spartan6/ETH_RXD0" AddNet "/FPGA_Spartan6/ETH_RXD2" -AddNet "/FPGA_Spartan6/ETH_RXD3" AddNet "/FPGA_Spartan6/ETH_RXDV" -AddNet "/FPGA_Spartan6/ETH_TXC" -AddNet "/FPGA_Spartan6/ETH_TXD2" +AddNet "/FPGA_Spartan6/ETH_RXER" +AddNet "/FPGA_Spartan6/ETH_TXD0" +AddNet "/FPGA_Spartan6/ETH_TXD1" +AddNet "/FPGA_Spartan6/ETH_TXD3" AddNet "/FPGA_Spartan6/ETH_TXER" +AddNet "/FPGA_Spartan6/M0_A0" AddNet "/FPGA_Spartan6/M0_A10" -AddNet "/FPGA_Spartan6/M0_A11" AddNet "/FPGA_Spartan6/M0_A12" +AddNet "/FPGA_Spartan6/M0_A2" +AddNet "/FPGA_Spartan6/M0_A3" AddNet "/FPGA_Spartan6/M0_A4" -AddNet "/FPGA_Spartan6/M0_A5" -AddNet "/FPGA_Spartan6/M0_A7" +AddNet "/FPGA_Spartan6/M0_A6" +AddNet "/FPGA_Spartan6/M0_A8" AddNet "/FPGA_Spartan6/M0_A9" -AddNet "/FPGA_Spartan6/M0_BA1" AddNet "/FPGA_Spartan6/M0_CAS#" AddNet "/FPGA_Spartan6/M0_CKE" AddNet "/FPGA_Spartan6/M0_CLK" -AddNet "/FPGA_Spartan6/M0_CLK#" AddNet "/FPGA_Spartan6/M0_DQ0" AddNet "/FPGA_Spartan6/M0_DQ1" AddNet "/FPGA_Spartan6/M0_DQ10" @@ -991,37 +988,42 @@ AddNet "/FPGA_Spartan6/M0_DQ14" AddNet "/FPGA_Spartan6/M0_DQ15" AddNet "/FPGA_Spartan6/M0_DQ2" AddNet "/FPGA_Spartan6/M0_DQ3" -AddNet "/FPGA_Spartan6/M0_DQ4" +AddNet "/FPGA_Spartan6/M0_DQ6" AddNet "/FPGA_Spartan6/M0_DQ8" AddNet "/FPGA_Spartan6/M0_LDM" -AddNet "/FPGA_Spartan6/M0_LDQS" -AddNet "/FPGA_Spartan6/M0_UDQS" AddNet "/FPGA_Spartan6/M1_A0" +AddNet "/FPGA_Spartan6/M1_A1" +AddNet "/FPGA_Spartan6/M1_A10" AddNet "/FPGA_Spartan6/M1_A11" AddNet "/FPGA_Spartan6/M1_A12" AddNet "/FPGA_Spartan6/M1_A2" -AddNet "/FPGA_Spartan6/M1_A3" AddNet "/FPGA_Spartan6/M1_A5" AddNet "/FPGA_Spartan6/M1_A6" +AddNet "/FPGA_Spartan6/M1_A7" +AddNet "/FPGA_Spartan6/M1_A8" AddNet "/FPGA_Spartan6/M1_A9" -AddNet "/FPGA_Spartan6/M1_BA1" +AddNet "/FPGA_Spartan6/M1_BA0" +AddNet "/FPGA_Spartan6/M1_CAS#" +AddNet "/FPGA_Spartan6/M1_CKE" +AddNet "/FPGA_Spartan6/M1_CLK#" AddNet "/FPGA_Spartan6/M1_CS#" -AddNet "/FPGA_Spartan6/M1_DQ10" +AddNet "/FPGA_Spartan6/M1_DQ0" +AddNet "/FPGA_Spartan6/M1_DQ1" AddNet "/FPGA_Spartan6/M1_DQ11" -AddNet "/FPGA_Spartan6/M1_DQ12" +AddNet "/FPGA_Spartan6/M1_DQ13" AddNet "/FPGA_Spartan6/M1_DQ2" AddNet "/FPGA_Spartan6/M1_DQ3" +AddNet "/FPGA_Spartan6/M1_DQ4" AddNet "/FPGA_Spartan6/M1_DQ5" -AddNet "/FPGA_Spartan6/M1_DQ7" AddNet "/FPGA_Spartan6/M1_DQ8" -AddNet "/FPGA_Spartan6/M1_DQ9" -AddNet "/FPGA_Spartan6/M1_LDM" -AddNet "/FPGA_Spartan6/M1_UDQS" -AddNet "/FPGA_Spartan6/NF_ALE" +AddNet "/FPGA_Spartan6/M1_UDM" AddNet "/FPGA_Spartan6/NF_CLE" -AddNet "/FPGA_Spartan6/NF_CS1_N" +AddNet "/FPGA_Spartan6/NF_D0" +AddNet "/FPGA_Spartan6/NF_D2" AddNet "/FPGA_Spartan6/NF_D4" +AddNet "/FPGA_Spartan6/NF_D6" AddNet "/FPGA_Spartan6/NF_D7" +AddNet "/FPGA_Spartan6/NF_RE_N" AddNet "/FPGA_Spartan6/NF_RNB" AddNet "/FPGA_Spartan6/NF_WE_N" AddNet "/FPGA_Spartan6/PROG_CCLK" @@ -1069,40 +1071,38 @@ AddNet "/FPGA_Spartan6/R_M1_RAS#" AddNet "/FPGA_Spartan6/R_M1_UDM" AddNet "/FPGA_Spartan6/R_M1_UDQS" AddNet "/FPGA_Spartan6/R_M1_WE#" -AddNet "/FPGA_Spartan6/SD_CMD" -AddNet "/FPGA_Spartan6/SD_DAT3" -AddNet "/FPGA_Spartan6/USBA_OE_N" -AddNet "/Non_volatile_memories/NF_D0" +AddNet "/FPGA_Spartan6/SD_CLK" +AddNet "/FPGA_Spartan6/USBA_RCV" +AddNet "/FPGA_Spartan6/USBA_VM" +AddNet "/Non_volatile_memories/NF_ALE" +AddNet "/Non_volatile_memories/NF_CS1_N" AddNet "/Non_volatile_memories/NF_D1" -AddNet "/Non_volatile_memories/NF_D2" AddNet "/Non_volatile_memories/NF_D3" AddNet "/Non_volatile_memories/NF_D5" -AddNet "/Non_volatile_memories/NF_D6" -AddNet "/Non_volatile_memories/NF_RE_N" -AddNet "/Non_volatile_memories/SD_CLK" +AddNet "/Non_volatile_memories/SD_CMD" AddNet "/Non_volatile_memories/SD_DAT0" AddNet "/Non_volatile_memories/SD_DAT1" AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "/USB/USBA_RCV" +AddNet "/Non_volatile_memories/SD_DAT3" +AddNet "/USB/USBA_OE_N" AddNet "/USB/USBA_SPD" -AddNet "/USB/USBA_VM" AddNet "/USB/USBA_VP" AddNet "GND" AddNet "N-000058" AddNet "N-000059" -AddNet "N-000356" -AddNet "N-000357" +AddNet "N-000358" AddNet "N-000361" -AddNet "N-000363" -AddNet "N-000364" -AddNet "N-000365" -AddNet "N-000366" -AddNet "N-000367" -AddNet "N-000377" -AddNet "N-000381" -AddNet "N-000382" +AddNet "N-000370" +AddNet "N-000371" +AddNet "N-000372" +AddNet "N-000373" +AddNet "N-000374" +AddNet "N-000376" +AddNet "N-000383" +AddNet "N-000384" AddNet "N-000385" -AddNet "N-000388" +AddNet "N-000386" +AddNet "N-000389" AddNet "N-000390" AddNet "N-000391" AddNet "N-000392" @@ -1180,70 +1180,70 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_CLK" +Ne 52 "/FPGA_Spartan6/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_RESET_N" +Ne 55 "/FPGA_Spartan6/ETH_RESET_N" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_RXD0" +Ne 57 "/FPGA_Spartan6/ETH_RXD0" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXER" +Ne 60 "/FPGA_Spartan6/ETH_RXER" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/ETH_TXEN" +Ne 51 "/Ethernet_Phy/ETH_TXEN" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXD3" +Ne 63 "/FPGA_Spartan6/ETH_TXD3" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_INT" +Ne 42 "/Ethernet_Phy/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/NF_D7" +Ne 120 "/FPGA_Spartan6/NF_D7" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/Non_volatile_memories/NF_D3" +Ne 175 "/Non_volatile_memories/NF_D3" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/Non_volatile_memories/NF_D1" +Ne 174 "/Non_volatile_memories/NF_D1" Po 590 -4133 $EndPAD $PAD @@ -1257,14 +1257,14 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_ALE" +Ne 172 "/Non_volatile_memories/NF_ALE" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/NF_RNB" +Ne 122 "/FPGA_Spartan6/NF_RNB" Po 1771 -4133 $EndPAD $PAD @@ -1348,7 +1348,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_RXD1" +Ne 47 "/Ethernet_Phy/ETH_RXD1" Po -2165 -3739 $EndPAD $PAD @@ -1362,7 +1362,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/ETH_TXER" +Ne 64 "/FPGA_Spartan6/ETH_TXER" Po -1377 -3739 $EndPAD $PAD @@ -1376,7 +1376,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_COL" +Ne 53 "/FPGA_Spartan6/ETH_COL" Po -590 -3739 $EndPAD $PAD @@ -1418,7 +1418,7 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/Non_volatile_memories/NF_RE_N" +Ne 121 "/FPGA_Spartan6/NF_RE_N" Po 1771 -3739 $EndPAD $PAD @@ -1467,7 +1467,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A11" +Ne 7 "/DDR_Banks/M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1495,42 +1495,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_MDIO" +Ne 54 "/FPGA_Spartan6/ETH_MDIO" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_RXD2" +Ne 58 "/FPGA_Spartan6/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_RXDV" +Ne 59 "/FPGA_Spartan6/ETH_RXDV" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_TXD1" +Ne 62 "/FPGA_Spartan6/ETH_TXD1" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/ETH_TXD2" +Ne 50 "/Ethernet_Phy/ETH_TXD2" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_CRS" +Ne 41 "/Ethernet_Phy/ETH_CRS" Po -590 -3346 $EndPAD $PAD @@ -1544,14 +1544,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/Non_volatile_memories/NF_D5" +Ne 176 "/Non_volatile_memories/NF_D5" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/Non_volatile_memories/NF_D2" +Ne 117 "/FPGA_Spartan6/NF_D2" Po 590 -3346 $EndPAD $PAD @@ -1565,21 +1565,21 @@ $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/NF_WE_N" +Ne 123 "/FPGA_Spartan6/NF_WE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_CS1_N" +Ne 173 "/Non_volatile_memories/NF_CS1_N" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/FPGA_Spartan6/SD_DAT3" +Ne 181 "/Non_volatile_memories/SD_DAT3" Po 2165 -3346 $EndPAD $PAD @@ -1600,7 +1600,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/FPGA_Spartan6/R_M1_A8" +Ne 140 "/FPGA_Spartan6/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1614,21 +1614,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/FPGA_Spartan6/R_M1_A9" +Ne 141 "/FPGA_Spartan6/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A12" +Ne 67 "/FPGA_Spartan6/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_CKE" +Ne 75 "/FPGA_Spartan6/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1656,42 +1656,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_RXD3" +Ne 48 "/Ethernet_Phy/ETH_RXD3" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/ETH_TXC" +Ne 49 "/Ethernet_Phy/ETH_TXC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_RXC" +Ne 56 "/FPGA_Spartan6/ETH_RXC" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_TXD0" +Ne 61 "/FPGA_Spartan6/ETH_TXD0" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_MDC" +Ne 45 "/Ethernet_Phy/ETH_MDC" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/Non_volatile_memories/NF_D6" +Ne 119 "/FPGA_Spartan6/NF_D6" Po -196 -2952 $EndPAD $PAD @@ -1712,14 +1712,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/Non_volatile_memories/NF_D0" +Ne 116 "/FPGA_Spartan6/NF_D0" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_CLE" +Ne 115 "/FPGA_Spartan6/NF_CLE" Po 1377 -2952 $EndPAD $PAD @@ -1733,7 +1733,7 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/FPGA_Spartan6/SD_CMD" +Ne 177 "/Non_volatile_memories/SD_CMD" Po 2165 -2952 $EndPAD $PAD @@ -1761,21 +1761,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/FPGA_Spartan6/R_M1_CKE" +Ne 145 "/FPGA_Spartan6/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Spartan6/R_M1_A12" +Ne 134 "/FPGA_Spartan6/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_A9" +Ne 73 "/FPGA_Spartan6/M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -1789,7 +1789,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_A8" +Ne 72 "/FPGA_Spartan6/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1880,7 +1880,7 @@ $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/Non_volatile_memories/SD_CLK" +Ne 169 "/FPGA_Spartan6/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -1908,7 +1908,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA_Spartan6/R_M1_A7" +Ne 139 "/FPGA_Spartan6/R_M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -1922,7 +1922,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Spartan6/R_M1_A2" +Ne 135 "/FPGA_Spartan6/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -1936,14 +1936,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_WE#" +Ne 22 "/DDR_Banks/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A4" +Ne 70 "/FPGA_Spartan6/M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -2055,7 +2055,7 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/R_M1_A11" +Ne 133 "/FPGA_Spartan6/R_M1_A11" Po 2952 -2165 $EndPAD $PAD @@ -2069,21 +2069,21 @@ $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/R_M1_A0" +Ne 130 "/FPGA_Spartan6/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/R_M1_A1" +Ne 131 "/FPGA_Spartan6/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_BA1" +Ne 11 "/DDR_Banks/M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -2097,14 +2097,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_BA0" +Ne 10 "/DDR_Banks/M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A10" +Ne 66 "/FPGA_Spartan6/M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -2209,14 +2209,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/R_M1_A10" +Ne 132 "/FPGA_Spartan6/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Spartan6/R_M1_A3" +Ne 136 "/FPGA_Spartan6/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2237,42 +2237,42 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A1" +Ne 6 "/DDR_Banks/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A0" +Ne 65 "/FPGA_Spartan6/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_CLK#" +Ne 12 "/DDR_Banks/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_CLK" +Ne 76 "/FPGA_Spartan6/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A2" +Ne 68 "/FPGA_Spartan6/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_A7" +Ne 9 "/DDR_Banks/M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -2342,7 +2342,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/FPGA_Spartan6/R_M1_CS#" +Ne 146 "/FPGA_Spartan6/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -2363,35 +2363,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/FPGA_Spartan6/R_M1_WE#" +Ne 168 "/FPGA_Spartan6/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_CLK" +Ne 26 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/FPGA_Spartan6/R_M1_RAS#" +Ne 165 "/FPGA_Spartan6/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/FPGA_Spartan6/R_M1_CAS#" +Ne 144 "/FPGA_Spartan6/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ5" +Ne 15 "/DDR_Banks/M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -2405,14 +2405,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M0_DQ4" +Ne 14 "/DDR_Banks/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_A6" +Ne 71 "/FPGA_Spartan6/M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2503,7 +2503,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/FPGA_Spartan6/R_M1_BA0" +Ne 142 "/FPGA_Spartan6/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2517,14 +2517,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_CLK#" +Ne 103 "/FPGA_Spartan6/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/FPGA_Spartan6/R_M1_DQ4" +Ne 157 "/FPGA_Spartan6/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD @@ -2538,7 +2538,7 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/FPGA_Spartan6/R_M1_DQ5" +Ne 158 "/FPGA_Spartan6/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD @@ -2552,35 +2552,35 @@ $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ6" +Ne 86 "/FPGA_Spartan6/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_A5" +Ne 8 "/DDR_Banks/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_CAS#" +Ne 74 "/FPGA_Spartan6/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_RAS#" +Ne 19 "/DDR_Banks/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A3" +Ne 69 "/FPGA_Spartan6/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2657,7 +2657,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/FPGA_Spartan6/R_M1_BA1" +Ne 143 "/FPGA_Spartan6/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2671,28 +2671,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_Spartan6/R_M1_A6" +Ne 138 "/FPGA_Spartan6/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_Spartan6/R_M1_A5" +Ne 137 "/FPGA_Spartan6/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_Spartan6/R_M1_DQ6" +Ne 159 "/FPGA_Spartan6/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_Spartan6/R_M1_DQ7" +Ne 160 "/FPGA_Spartan6/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2713,14 +2713,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M0_LDQS" +Ne 18 "/DDR_Banks/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M0_LDM" +Ne 88 "/FPGA_Spartan6/M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -2825,14 +2825,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_Spartan6/R_M1_LDM" +Ne 163 "/FPGA_Spartan6/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_Spartan6/R_M1_LDQS" +Ne 164 "/FPGA_Spartan6/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -2853,21 +2853,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_DQ3" +Ne 85 "/FPGA_Spartan6/M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_DQ2" +Ne 84 "/FPGA_Spartan6/M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_UDM" +Ne 20 "/DDR_Banks/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2972,7 +2972,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/USB/USBA_VM" +Ne 171 "/FPGA_Spartan6/USBA_VM" Po 2558 196 $EndPAD $PAD @@ -2986,28 +2986,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/FPGA_Spartan6/R_M1_UDM" +Ne 166 "/FPGA_Spartan6/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_Spartan6/R_M1_DQ2" +Ne 155 "/FPGA_Spartan6/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_Spartan6/R_M1_DQ3" +Ne 156 "/FPGA_Spartan6/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ1" +Ne 78 "/FPGA_Spartan6/M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -3021,7 +3021,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ0" +Ne 77 "/FPGA_Spartan6/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -3112,7 +3112,7 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/USB/USBA_RCV" +Ne 170 "/FPGA_Spartan6/USBA_RCV" Po 1771 590 $EndPAD $PAD @@ -3140,7 +3140,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA_Spartan6/R_M1_DQ0" +Ne 147 "/FPGA_Spartan6/R_M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -3154,7 +3154,7 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA_Spartan6/R_M1_DQ1" +Ne 148 "/FPGA_Spartan6/R_M1_DQ1" Po 4133 590 $EndPAD $PAD @@ -3168,7 +3168,7 @@ $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M0_DQ8" +Ne 87 "/FPGA_Spartan6/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3280,7 +3280,7 @@ $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/FPGA_Spartan6/USBA_OE_N" +Ne 182 "/USB/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -3301,21 +3301,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/FPGA_Spartan6/R_M1_DQ8" +Ne 161 "/FPGA_Spartan6/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/FPGA_Spartan6/R_M1_DQ9" +Ne 162 "/FPGA_Spartan6/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ11" +Ne 80 "/FPGA_Spartan6/M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3329,7 +3329,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ10" +Ne 79 "/FPGA_Spartan6/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3441,14 +3441,14 @@ $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/USB/USBA_SPD" +Ne 183 "/USB/USBA_SPD" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA_Spartan6/R_M1_DQ10" +Ne 149 "/FPGA_Spartan6/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3462,7 +3462,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA_Spartan6/R_M1_DQ11" +Ne 150 "/FPGA_Spartan6/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3476,7 +3476,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M0_UDQS" +Ne 21 "/DDR_Banks/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3497,7 +3497,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/PROG_CSO" +Ne 125 "/FPGA_Spartan6/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -3609,7 +3609,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/FPGA_Spartan6/R_M1_UDQS" +Ne 167 "/FPGA_Spartan6/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3637,7 +3637,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ12" +Ne 81 "/FPGA_Spartan6/M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3707,14 +3707,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/PROG_MISO3" +Ne 129 "/FPGA_Spartan6/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/PROG_MISO2" +Ne 128 "/FPGA_Spartan6/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -3756,7 +3756,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_Spartan6/R_M1_DQ12" +Ne 151 "/FPGA_Spartan6/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -3770,21 +3770,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/FPGA_Spartan6/R_M1_DQ13" +Ne 152 "/FPGA_Spartan6/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ15" +Ne 83 "/FPGA_Spartan6/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ14" +Ne 82 "/FPGA_Spartan6/M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3917,14 +3917,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/FPGA_Spartan6/R_M1_DQ14" +Ne 153 "/FPGA_Spartan6/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/FPGA_Spartan6/R_M1_DQ15" +Ne 154 "/FPGA_Spartan6/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -4372,14 +4372,14 @@ $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/PROG_MISO1" +Ne 127 "/FPGA_Spartan6/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/PROG_CCLK" +Ne 124 "/FPGA_Spartan6/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -4526,7 +4526,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/PROG_MISO0" +Ne 126 "/FPGA_Spartan6/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -4569,21 +4569,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXER" +Ne 60 "/FPGA_Spartan6/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_RXC" +Ne 56 "/FPGA_Spartan6/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_RXDV" +Ne 59 "/FPGA_Spartan6/ETH_RXDV" Po -1613 491 $EndPAD $PAD @@ -4604,63 +4604,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_RXD0" +Ne 57 "/FPGA_Spartan6/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_RXD1" +Ne 47 "/Ethernet_Phy/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_RXD2" +Ne 58 "/FPGA_Spartan6/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_RXD3" +Ne 48 "/Ethernet_Phy/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_MDC" +Ne 45 "/Ethernet_Phy/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_MDIO" +Ne 54 "/FPGA_Spartan6/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_RESET_N" +Ne 55 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 46 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_CLK" +Ne 52 "/FPGA_Spartan6/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -4695,14 +4695,14 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 190 "N-000361" +Ne 190 "N-000370" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 188 "N-000356" +Ne 192 "N-000372" Po 491 -1613 $EndPAD $PAD @@ -4716,35 +4716,35 @@ $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_A3.3V" +Ne 40 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 195 "N-000367" +Ne 188 "N-000358" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_INT" +Ne 42 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_LED0" +Ne 43 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_LED1" +Ne 44 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4772,21 +4772,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_A1.8V" +Ne 39 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 192 "N-000364" +Ne 193 "N-000373" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 194 "N-000366" +Ne 191 "N-000371" Po 1613 -491 $EndPAD $PAD @@ -4821,63 +4821,63 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/ETH_TXER" +Ne 64 "/FPGA_Spartan6/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/ETH_TXC" +Ne 49 "/Ethernet_Phy/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/ETH_TXEN" +Ne 51 "/Ethernet_Phy/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_TXD0" +Ne 61 "/FPGA_Spartan6/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_TXD1" +Ne 62 "/FPGA_Spartan6/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/ETH_TXD2" +Ne 50 "/Ethernet_Phy/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXD3" +Ne 63 "/FPGA_Spartan6/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_COL" +Ne 53 "/FPGA_Spartan6/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_CRS" +Ne 41 "/Ethernet_Phy/ETH_CRS" Po 688 1613 $EndPAD $PAD @@ -5155,28 +5155,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/NF_RNB" +Ne 122 "/FPGA_Spartan6/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/NF_RNB" +Ne 122 "/FPGA_Spartan6/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/Non_volatile_memories/NF_RE_N" +Ne 121 "/FPGA_Spartan6/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_CS1_N" +Ne 173 "/Non_volatile_memories/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -5225,21 +5225,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_CLE" +Ne 115 "/FPGA_Spartan6/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_ALE" +Ne 172 "/Non_volatile_memories/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/NF_WE_N" +Ne 123 "/FPGA_Spartan6/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -5316,28 +5316,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/Non_volatile_memories/NF_D0" +Ne 116 "/FPGA_Spartan6/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/Non_volatile_memories/NF_D1" +Ne 174 "/Non_volatile_memories/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/Non_volatile_memories/NF_D2" +Ne 117 "/FPGA_Spartan6/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/Non_volatile_memories/NF_D3" +Ne 175 "/Non_volatile_memories/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -5407,21 +5407,21 @@ $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/Non_volatile_memories/NF_D5" +Ne 176 "/Non_volatile_memories/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/Non_volatile_memories/NF_D6" +Ne 119 "/FPGA_Spartan6/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/NF_D7" +Ne 120 "/FPGA_Spartan6/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -5481,14 +5481,14 @@ $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 168 "/FPGA_Spartan6/SD_DAT3" +Ne 181 "/Non_volatile_memories/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 167 "/FPGA_Spartan6/SD_CMD" +Ne 177 "/Non_volatile_memories/SD_CMD" Po -433 0 $EndPAD $PAD @@ -5502,7 +5502,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 177 "/Non_volatile_memories/SD_CLK" +Ne 169 "/FPGA_Spartan6/SD_CLK" Po 433 0 $EndPAD $PAD @@ -5571,35 +5571,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 193 "N-000365" +Ne 195 "N-000376" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 193 "N-000365" +Ne 195 "N-000376" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 193 "N-000365" +Ne 195 "N-000376" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 193 "N-000365" +Ne 195 "N-000376" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 190 "N-000361" +Ne 190 "N-000370" Po -1750 -2500 $EndPAD $PAD @@ -5620,14 +5620,14 @@ $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 194 "N-000366" +Ne 191 "N-000371" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 188 "N-000356" +Ne 192 "N-000372" Po -1250 -3500 $EndPAD $PAD @@ -5648,7 +5648,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 192 "N-000364" +Ne 193 "N-000373" Po 1750 -3500 $EndPAD $PAD @@ -5662,7 +5662,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 191 "N-000363" +Ne 194 "N-000374" Po -1150 -5400 $EndPAD $PAD @@ -5676,7 +5676,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 189 "N-000357" +Ne 189 "N-000361" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -5712,14 +5712,14 @@ $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/USB/USBA_SPD" +Ne 183 "/USB/USBA_SPD" Po -511 -1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/USB/USBA_RCV" +Ne 170 "/FPGA_Spartan6/USBA_RCV" Po -255 -1112 $EndPAD $PAD @@ -5733,7 +5733,7 @@ $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/USB/USBA_VM" +Ne 171 "/FPGA_Spartan6/USBA_VM" Po 255 -1112 $EndPAD $PAD @@ -5761,21 +5761,21 @@ $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/FPGA_Spartan6/USBA_OE_N" +Ne 182 "/USB/USBA_OE_N" Po 511 1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "N-000390" +Ne 196 "N-000383" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 205 "N-000394" +Ne 202 "N-000391" Po 0 1112 $EndPAD $PAD @@ -5825,7 +5825,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ0" +Ne 105 "/FPGA_Spartan6/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -5839,14 +5839,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_DQ1" +Ne 106 "/FPGA_Spartan6/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ2" +Ne 109 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD @@ -5860,14 +5860,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ3" +Ne 110 "/FPGA_Spartan6/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_DQ4" +Ne 111 "/FPGA_Spartan6/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -5881,14 +5881,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ5" +Ne 112 "/FPGA_Spartan6/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/DDR_Banks/M1_DQ6" +Ne 31 "/DDR_Banks/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -5902,7 +5902,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ7" +Ne 32 "/DDR_Banks/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5923,7 +5923,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_LDQS" +Ne 35 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -5951,35 +5951,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_LDM" +Ne 34 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/DDR_Banks/M1_WE#" +Ne 38 "/DDR_Banks/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_CAS#" +Ne 101 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M1_RAS#" +Ne 36 "/DDR_Banks/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_CS#" +Ne 104 "/FPGA_Spartan6/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -5993,49 +5993,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_BA0" +Ne 100 "/FPGA_Spartan6/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_BA1" +Ne 25 "/DDR_Banks/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_A10" +Ne 91 "/FPGA_Spartan6/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A0" +Ne 89 "/FPGA_Spartan6/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_A1" +Ne 90 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_A2" +Ne 94 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_A3" +Ne 23 "/DDR_Banks/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -6056,56 +6056,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A4" +Ne 24 "/DDR_Banks/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_A5" +Ne 95 "/FPGA_Spartan6/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_A6" +Ne 96 "/FPGA_Spartan6/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A7" +Ne 97 "/FPGA_Spartan6/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A8" +Ne 98 "/FPGA_Spartan6/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_A9" +Ne 99 "/FPGA_Spartan6/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A11" +Ne 92 "/FPGA_Spartan6/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_A12" +Ne 93 "/FPGA_Spartan6/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -6119,28 +6119,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_CLK#" +Ne 103 "/FPGA_Spartan6/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_CKE" +Ne 102 "/FPGA_Spartan6/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_CLK" +Ne 26 "/DDR_Banks/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/DDR_Banks/M1_UDM" +Ne 114 "/FPGA_Spartan6/M1_UDM" Po 767 -2176 $EndPAD $PAD @@ -6168,7 +6168,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/M1_UDQS" +Ne 37 "/DDR_Banks/M1_UDQS" Po -255 -2176 $EndPAD $PAD @@ -6189,7 +6189,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_DQ8" +Ne 113 "/FPGA_Spartan6/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6203,14 +6203,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_DQ9" +Ne 33 "/DDR_Banks/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ10" +Ne 27 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -6224,14 +6224,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ11" +Ne 107 "/FPGA_Spartan6/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ12" +Ne 28 "/DDR_Banks/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6245,14 +6245,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_DQ13" +Ne 108 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_DQ14" +Ne 29 "/DDR_Banks/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -6266,7 +6266,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_DQ15" +Ne 30 "/DDR_Banks/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -6302,7 +6302,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ0" +Ne 77 "/FPGA_Spartan6/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -6316,14 +6316,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ1" +Ne 78 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_DQ2" +Ne 84 "/FPGA_Spartan6/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -6337,14 +6337,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_DQ3" +Ne 85 "/FPGA_Spartan6/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M0_DQ4" +Ne 14 "/DDR_Banks/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -6358,14 +6358,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ5" +Ne 15 "/DDR_Banks/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ6" +Ne 86 "/FPGA_Spartan6/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -6400,7 +6400,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M0_LDQS" +Ne 18 "/DDR_Banks/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -6428,28 +6428,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M0_LDM" +Ne 88 "/FPGA_Spartan6/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_WE#" +Ne 22 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_CAS#" +Ne 74 "/FPGA_Spartan6/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_RAS#" +Ne 19 "/DDR_Banks/M0_RAS#" Po 1535 2176 $EndPAD $PAD @@ -6470,49 +6470,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_BA0" +Ne 10 "/DDR_Banks/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_BA1" +Ne 11 "/DDR_Banks/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A10" +Ne 66 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A0" +Ne 65 "/FPGA_Spartan6/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A1" +Ne 6 "/DDR_Banks/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A2" +Ne 68 "/FPGA_Spartan6/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A3" +Ne 69 "/FPGA_Spartan6/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -6533,56 +6533,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A4" +Ne 70 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_A5" +Ne 8 "/DDR_Banks/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_A6" +Ne 71 "/FPGA_Spartan6/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_A7" +Ne 9 "/DDR_Banks/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_A8" +Ne 72 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_A9" +Ne 73 "/FPGA_Spartan6/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A11" +Ne 7 "/DDR_Banks/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A12" +Ne 67 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6596,28 +6596,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_CLK#" +Ne 12 "/DDR_Banks/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_CKE" +Ne 75 "/FPGA_Spartan6/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_CLK" +Ne 76 "/FPGA_Spartan6/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_UDM" +Ne 20 "/DDR_Banks/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -6645,7 +6645,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M0_UDQS" +Ne 21 "/DDR_Banks/M0_UDQS" Po -255 -2176 $EndPAD $PAD @@ -6666,7 +6666,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M0_DQ8" +Ne 87 "/FPGA_Spartan6/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6687,7 +6687,7 @@ $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ10" +Ne 79 "/FPGA_Spartan6/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -6701,14 +6701,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ11" +Ne 80 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ12" +Ne 81 "/FPGA_Spartan6/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6729,7 +6729,7 @@ $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ14" +Ne 82 "/FPGA_Spartan6/M0_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -6743,7 +6743,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ15" +Ne 83 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -6771,7 +6771,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 202 "N-000391" +Ne 198 "N-000385" Po -176 0 $EndPAD $PAD @@ -6799,7 +6799,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 193 "N-000365" +Ne 195 "N-000376" Po -176 0 $EndPAD $PAD @@ -6827,14 +6827,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 189 "N-000357" +Ne 189 "N-000361" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 45 "/Ethernet_Phy/ETH_LED1" +Ne 44 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6855,14 +6855,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 191 "N-000363" +Ne 194 "N-000374" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 44 "/Ethernet_Phy/ETH_LED0" +Ne 43 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6890,7 +6890,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 192 "N-000364" +Ne 193 "N-000373" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6918,7 +6918,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 194 "N-000366" +Ne 191 "N-000371" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6946,7 +6946,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 188 "N-000356" +Ne 192 "N-000372" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6974,7 +6974,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 190 "N-000361" +Ne 190 "N-000370" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6995,7 +6995,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 195 "N-000367" +Ne 188 "N-000358" Po -176 0 $EndPAD $PAD @@ -7023,7 +7023,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 60 "/FPGA_Spartan6/ETH_MDIO" +Ne 54 "/FPGA_Spartan6/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -7051,7 +7051,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 202 "N-000391" +Ne 198 "N-000385" Po -176 0 $EndPAD $PAD @@ -7079,7 +7079,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 193 "N-000365" +Ne 195 "N-000376" Po -176 0 $EndPAD $PAD @@ -7163,7 +7163,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 46 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD @@ -7191,7 +7191,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/Ethernet_Phy/ETH_A3.3V" +Ne 40 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD @@ -7219,7 +7219,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/Ethernet_Phy/ETH_A1.8V" +Ne 39 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD @@ -7359,7 +7359,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 201 "N-000390" +Ne 196 "N-000383" Po -294 0 $EndPAD $PAD @@ -7387,7 +7387,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 205 "N-000394" +Ne 202 "N-000391" Po -294 0 $EndPAD $PAD @@ -7499,7 +7499,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_A3.3V" +Ne 40 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD @@ -7555,7 +7555,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 204 "N-000393" +Ne 200 "N-000389" Po -570 0 $EndPAD $PAD @@ -7588,56 +7588,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 203 "N-000392" +Ne 201 "N-000390" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 201 "N-000390" +Ne 196 "N-000383" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 205 "N-000394" +Ne 202 "N-000391" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 205 "N-000394" +Ne 202 "N-000391" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 202 "N-000391" +Ne 198 "N-000385" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 202 "N-000391" +Ne 198 "N-000385" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 202 "N-000391" +Ne 198 "N-000385" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 202 "N-000391" +Ne 198 "N-000385" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -8218,7 +8218,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 198 "N-000382" +Ne 197 "N-000384" Po -294 0 $EndPAD $PAD @@ -8246,14 +8246,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 204 "N-000393" +Ne 200 "N-000389" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 203 "N-000392" +Ne 201 "N-000390" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8274,7 +8274,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 197 "N-000381" +Ne 199 "N-000386" Po -294 0 $EndPAD $PAD @@ -8330,7 +8330,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 200 "N-000388" +Ne 205 "N-000394" Po -176 0 $EndPAD $PAD @@ -8358,7 +8358,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 200 "N-000388" +Ne 205 "N-000394" Po -176 0 $EndPAD $PAD @@ -8414,7 +8414,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 196 "N-000377" +Ne 203 "N-000392" Po -294 0 $EndPAD $PAD @@ -8442,7 +8442,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 199 "N-000385" +Ne 204 "N-000393" Po -294 0 $EndPAD $PAD @@ -8526,7 +8526,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 197 "N-000381" +Ne 199 "N-000386" Po -570 0 $EndPAD $PAD @@ -8625,14 +8625,14 @@ $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 196 "N-000377" +Ne 203 "N-000392" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 199 "N-000385" +Ne 204 "N-000393" Po 0 1112 $EndPAD $PAD @@ -9583,42 +9583,42 @@ $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/PROG_CSO" +Ne 125 "/FPGA_Spartan6/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/PROG_MISO3" +Ne 129 "/FPGA_Spartan6/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/PROG_CCLK" +Ne 124 "/FPGA_Spartan6/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/PROG_MISO0" +Ne 126 "/FPGA_Spartan6/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/PROG_MISO1" +Ne 127 "/FPGA_Spartan6/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/PROG_MISO2" +Ne 128 "/FPGA_Spartan6/PROG_MISO2" Po 250 1050 $EndPAD $PAD @@ -9799,7 +9799,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/Ethernet_Phy/ETH_A3.3V" +Ne 40 "/Ethernet_Phy/ETH_A3.3V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9827,7 +9827,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/Ethernet_Phy/ETH_A1.8V" +Ne 39 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9848,14 +9848,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/Ethernet_Phy/ETH_A1.8V" +Ne 39 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 46 "/Ethernet_Phy/ETH_PLL1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9902,56 +9902,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 128 "/FPGA_Spartan6/R_M1_A0" +Ne 130 "/FPGA_Spartan6/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 129 "/FPGA_Spartan6/R_M1_A1" +Ne 131 "/FPGA_Spartan6/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 133 "/FPGA_Spartan6/R_M1_A2" +Ne 135 "/FPGA_Spartan6/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 134 "/FPGA_Spartan6/R_M1_A3" +Ne 136 "/FPGA_Spartan6/R_M1_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 98 "/FPGA_Spartan6/M1_A3" +Ne 23 "/DDR_Banks/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 97 "/FPGA_Spartan6/M1_A2" +Ne 94 "/FPGA_Spartan6/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 21 "/DDR_Banks/M1_A1" +Ne 90 "/FPGA_Spartan6/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/FPGA_Spartan6/M1_A0" +Ne 89 "/FPGA_Spartan6/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -9970,56 +9970,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/FPGA_Spartan6/R_M1_RAS#" +Ne 165 "/FPGA_Spartan6/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 140 "/FPGA_Spartan6/R_M1_BA0" +Ne 142 "/FPGA_Spartan6/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 141 "/FPGA_Spartan6/R_M1_BA1" +Ne 143 "/FPGA_Spartan6/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 130 "/FPGA_Spartan6/R_M1_A10" +Ne 132 "/FPGA_Spartan6/R_M1_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 22 "/DDR_Banks/M1_A10" +Ne 91 "/FPGA_Spartan6/M1_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 102 "/FPGA_Spartan6/M1_BA1" +Ne 25 "/DDR_Banks/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Banks/M1_BA0" +Ne 100 "/FPGA_Spartan6/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M1_RAS#" +Ne 36 "/DDR_Banks/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10038,56 +10038,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/FPGA_Spartan6/R_M1_DQ4" +Ne 157 "/FPGA_Spartan6/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/FPGA_Spartan6/R_M1_DQ5" +Ne 158 "/FPGA_Spartan6/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/FPGA_Spartan6/R_M1_DQ6" +Ne 159 "/FPGA_Spartan6/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/FPGA_Spartan6/R_M1_DQ7" +Ne 160 "/FPGA_Spartan6/R_M1_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 110 "/FPGA_Spartan6/M1_DQ7" +Ne 32 "/DDR_Banks/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 37 "/DDR_Banks/M1_DQ6" +Ne 31 "/DDR_Banks/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 109 "/FPGA_Spartan6/M1_DQ5" +Ne 112 "/FPGA_Spartan6/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 36 "/DDR_Banks/M1_DQ4" +Ne 111 "/FPGA_Spartan6/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10106,56 +10106,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/FPGA_Spartan6/R_M1_LDQS" +Ne 164 "/FPGA_Spartan6/R_M1_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/FPGA_Spartan6/R_M1_LDM" +Ne 163 "/FPGA_Spartan6/R_M1_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/FPGA_Spartan6/R_M1_WE#" +Ne 168 "/FPGA_Spartan6/R_M1_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/FPGA_Spartan6/R_M1_CAS#" +Ne 144 "/FPGA_Spartan6/R_M1_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Banks/M1_CAS#" +Ne 101 "/FPGA_Spartan6/M1_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/DDR_Banks/M1_WE#" +Ne 38 "/DDR_Banks/M1_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 113 "/FPGA_Spartan6/M1_LDM" +Ne 34 "/DDR_Banks/M1_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_LDQS" +Ne 35 "/DDR_Banks/M1_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10174,56 +10174,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 145 "/FPGA_Spartan6/R_M1_DQ0" +Ne 147 "/FPGA_Spartan6/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 146 "/FPGA_Spartan6/R_M1_DQ1" +Ne 148 "/FPGA_Spartan6/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/FPGA_Spartan6/R_M1_DQ2" +Ne 155 "/FPGA_Spartan6/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 154 "/FPGA_Spartan6/R_M1_DQ3" +Ne 156 "/FPGA_Spartan6/R_M1_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 108 "/FPGA_Spartan6/M1_DQ3" +Ne 110 "/FPGA_Spartan6/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/FPGA_Spartan6/M1_DQ2" +Ne 109 "/FPGA_Spartan6/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Banks/M1_DQ1" +Ne 106 "/FPGA_Spartan6/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/DDR_Banks/M1_DQ0" +Ne 105 "/FPGA_Spartan6/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10242,21 +10242,21 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 137 "/FPGA_Spartan6/R_M1_A7" +Ne 139 "/FPGA_Spartan6/R_M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 136 "/FPGA_Spartan6/R_M1_A6" +Ne 138 "/FPGA_Spartan6/R_M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 135 "/FPGA_Spartan6/R_M1_A5" +Ne 137 "/FPGA_Spartan6/R_M1_A5" Po 98 -177 $EndPAD $PAD @@ -10270,28 +10270,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/DDR_Banks/M1_A4" +Ne 24 "/DDR_Banks/M1_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 99 "/FPGA_Spartan6/M1_A5" +Ne 95 "/FPGA_Spartan6/M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 100 "/FPGA_Spartan6/M1_A6" +Ne 96 "/FPGA_Spartan6/M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Banks/M1_A7" +Ne 97 "/FPGA_Spartan6/M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10310,56 +10310,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 132 "/FPGA_Spartan6/R_M1_A12" +Ne 134 "/FPGA_Spartan6/R_M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 131 "/FPGA_Spartan6/R_M1_A11" +Ne 133 "/FPGA_Spartan6/R_M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 139 "/FPGA_Spartan6/R_M1_A9" +Ne 141 "/FPGA_Spartan6/R_M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 138 "/FPGA_Spartan6/R_M1_A8" +Ne 140 "/FPGA_Spartan6/R_M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M1_A8" +Ne 98 "/FPGA_Spartan6/M1_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 101 "/FPGA_Spartan6/M1_A9" +Ne 99 "/FPGA_Spartan6/M1_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/FPGA_Spartan6/M1_A11" +Ne 92 "/FPGA_Spartan6/M1_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 96 "/FPGA_Spartan6/M1_A12" +Ne 93 "/FPGA_Spartan6/M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10380,14 +10380,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Banks/M1_CLK#" +Ne 103 "/FPGA_Spartan6/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/DDR_Banks/M1_CLK" +Ne 26 "/DDR_Banks/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10406,56 +10406,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 148 "/FPGA_Spartan6/R_M1_DQ11" +Ne 150 "/FPGA_Spartan6/R_M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 147 "/FPGA_Spartan6/R_M1_DQ10" +Ne 149 "/FPGA_Spartan6/R_M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/FPGA_Spartan6/R_M1_DQ9" +Ne 162 "/FPGA_Spartan6/R_M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/FPGA_Spartan6/R_M1_DQ8" +Ne 161 "/FPGA_Spartan6/R_M1_DQ8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 111 "/FPGA_Spartan6/M1_DQ8" +Ne 113 "/FPGA_Spartan6/M1_DQ8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 112 "/FPGA_Spartan6/M1_DQ9" +Ne 33 "/DDR_Banks/M1_DQ9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/FPGA_Spartan6/M1_DQ10" +Ne 27 "/DDR_Banks/M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 105 "/FPGA_Spartan6/M1_DQ11" +Ne 107 "/FPGA_Spartan6/M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10474,56 +10474,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 152 "/FPGA_Spartan6/R_M1_DQ15" +Ne 154 "/FPGA_Spartan6/R_M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 151 "/FPGA_Spartan6/R_M1_DQ14" +Ne 153 "/FPGA_Spartan6/R_M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/FPGA_Spartan6/R_M1_DQ13" +Ne 152 "/FPGA_Spartan6/R_M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/FPGA_Spartan6/R_M1_DQ12" +Ne 151 "/FPGA_Spartan6/R_M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 106 "/FPGA_Spartan6/M1_DQ12" +Ne 28 "/DDR_Banks/M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_DQ13" +Ne 108 "/FPGA_Spartan6/M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/DDR_Banks/M1_DQ14" +Ne 29 "/DDR_Banks/M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/DDR_Banks/M1_DQ15" +Ne 30 "/DDR_Banks/M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10544,14 +10544,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/FPGA_Spartan6/R_M1_UDM" +Ne 166 "/FPGA_Spartan6/R_M1_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/DDR_Banks/M1_UDM" +Ne 114 "/FPGA_Spartan6/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10572,14 +10572,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/FPGA_Spartan6/R_M1_CKE" +Ne 145 "/FPGA_Spartan6/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M1_CKE" +Ne 102 "/FPGA_Spartan6/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10600,14 +10600,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/FPGA_Spartan6/R_M1_CS#" +Ne 146 "/FPGA_Spartan6/R_M1_CS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/FPGA_Spartan6/M1_CS#" +Ne 104 "/FPGA_Spartan6/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10628,17 +10628,200 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/FPGA_Spartan6/R_M1_UDQS" +Ne 167 "/FPGA_Spartan6/R_M1_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 114 "/FPGA_Spartan6/M1_UDQS" +Ne 37 "/DDR_Banks/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 +$MODULE MLF20m1 +Po 65551 41732 0 15 4C69F3CC 4C69F729 ~~ +Li MLF20m1 +Sc 4C69F729 +AR /4C69ED5F/4C69EE11 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"U9" +T1 0 150 200 200 0 40 N I 25 N"ATTINY24A-MLF" +DC -866 -866 -866 -944 39 21 +DS -787 787 -787 -787 39 21 +DS -787 -787 787 -787 39 21 +DS 787 -787 787 787 39 21 +DS 787 787 -787 787 39 21 +$PAD +Sh "PAD" R 433 433 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 185 "GND" +Po -235 235 +$EndPAD +$PAD +Sh "PAD" R 433 433 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 185 "GND" +Po -235 -235 +$EndPAD +$PAD +Sh "PAD" R 433 433 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 185 "GND" +Po 235 235 +$EndPAD +$PAD +Sh "PAD" R 433 433 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 185 "GND" +Po 235 -235 +$EndPAD +$PAD +Sh "15" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -393 688 +$EndPAD +$PAD +Sh "1" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -393 -688 +$EndPAD +$PAD +Sh "14" R 99 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 688 +$EndPAD +$PAD +Sh "2" R 99 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 -688 +$EndPAD +$PAD +Sh "13" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 688 +$EndPAD +$PAD +Sh "3" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 -688 +$EndPAD +$PAD +Sh "12" R 99 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 688 +$EndPAD +$PAD +Sh "4" R 99 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 -688 +$EndPAD +$PAD +Sh "11" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 393 688 +$EndPAD +$PAD +Sh "5" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 393 -688 +$EndPAD +$PAD +Sh "20" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 -393 +$EndPAD +$PAD +Sh "6" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 -393 +$EndPAD +$PAD +Sh "19" R 157 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 -196 +$EndPAD +$PAD +Sh "7" R 157 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 -196 +$EndPAD +$PAD +Sh "18" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 0 +$EndPAD +$PAD +Sh "8" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 185 "GND" +Po 688 0 +$EndPAD +$PAD +Sh "17" R 157 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 196 +$EndPAD +$PAD +Sh "9" R 157 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 196 +$EndPAD +$PAD +Sh "16" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 393 +$EndPAD +$PAD +Sh "10" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 393 +$EndPAD +$EndMODULE MLF20m1 $COTATION Ge 0 25 0 Va 35827 diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 06db05a..57c543f 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,7 +1,7 @@ -# EESchema Netlist Version 1.1 created Mon 16 Aug 2010 09:05:36 PM COT +# EESchema Netlist Version 1.1 created Mon 16 Aug 2010 09:46:17 PM COT ( ( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF} - ( PAD ? ) + ( PAD GND ) ( 1 ? ) ( 2 ? ) ( 3 ? ) @@ -9,7 +9,7 @@ ( 5 ? ) ( 6 ? ) ( 7 ? ) - ( 8 ? ) + ( 8 GND ) ( 9 ? ) ( 10 ? ) ( 11 ? ) @@ -55,9 +55,9 @@ ( CD ? ) ( 1 /Non_volatile_memories/SD_DAT2 ) ( 2 /Non_volatile_memories/SD_DAT3 ) - ( 3 /FPGA_Spartan6/SD_CMD ) + ( 3 /Non_volatile_memories/SD_CMD ) ( 4 +3.3V ) - ( 5 /Non_volatile_memories/SD_CLK ) + ( 5 /FPGA_Spartan6/SD_CLK ) ( 6 GND ) ( 7 /Non_volatile_memories/SD_DAT0 ) ( 8 /Non_volatile_memories/SD_DAT1 ) @@ -68,19 +68,19 @@ ( 3 ? ) ( 4 ? ) ( 5 ? ) - ( 6 /Non_volatile_memories/NF_RNB ) - ( 7 /Non_volatile_memories/NF_RNB ) - ( 8 /Non_volatile_memories/NF_RE_N ) - ( 9 /FPGA_Spartan6/NF_CS1_N ) + ( 6 /FPGA_Spartan6/NF_RNB ) + ( 7 /FPGA_Spartan6/NF_RNB ) + ( 8 /FPGA_Spartan6/NF_RE_N ) + ( 9 /Non_volatile_memories/NF_CS1_N ) ( 10 ? ) ( 11 ? ) ( 12 +3.3V ) ( 13 GND ) ( 14 ? ) ( 15 ? ) - ( 16 /Non_volatile_memories/NF_CLE ) - ( 17 /FPGA_Spartan6/NF_ALE ) - ( 18 /Non_volatile_memories/NF_WE_N ) + ( 16 /FPGA_Spartan6/NF_CLE ) + ( 17 /Non_volatile_memories/NF_ALE ) + ( 18 /FPGA_Spartan6/NF_WE_N ) ( 19 +3.3V ) ( 20 ? ) ( 21 ? ) @@ -92,9 +92,9 @@ ( 27 ? ) ( 28 ? ) ( 29 /FPGA_Spartan6/NF_D0 ) - ( 30 /FPGA_Spartan6/NF_D1 ) + ( 30 /Non_volatile_memories/NF_D1 ) ( 31 /FPGA_Spartan6/NF_D2 ) - ( 32 /FPGA_Spartan6/NF_D3 ) + ( 32 /Non_volatile_memories/NF_D3 ) ( 33 ? ) ( 34 ? ) ( 35 ? ) @@ -103,10 +103,10 @@ ( 38 ? ) ( 39 ? ) ( 40 ? ) - ( 41 /Non_volatile_memories/NF_D4 ) + ( 41 /FPGA_Spartan6/NF_D4 ) ( 42 /Non_volatile_memories/NF_D5 ) - ( 43 /Non_volatile_memories/NF_D6 ) - ( 44 /Non_volatile_memories/NF_D7 ) + ( 43 /FPGA_Spartan6/NF_D6 ) + ( 44 /FPGA_Spartan6/NF_D7 ) ( 45 ? ) ( 46 ? ) ( 47 ? ) @@ -219,8 +219,8 @@ ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) ( 2 /USB/USBA_SPD ) - ( 3 /USB/USBA_RCV ) - ( 4 /FPGA_Spartan6/USBA_VP ) + ( 3 /FPGA_Spartan6/USBA_RCV ) + ( 4 /USB/USBA_VP ) ( 5 /FPGA_Spartan6/USBA_VM ) ( 7 GND ) ( 8 GND ) @@ -236,7 +236,7 @@ ) ( /4C431A63/4C69E92D 0402 R20 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CS# ) - ( 2 /DDR_Banks/M1_CS# ) + ( 2 /FPGA_Spartan6/M1_CS# ) ) ( /4C431A63/4C69E7F8 0402 R17 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CKE ) @@ -244,7 +244,7 @@ ) ( /4C431A63/4C69E7C2 0402 R18 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_UDM ) - ( 2 /DDR_Banks/M1_UDM ) + ( 2 /FPGA_Spartan6/M1_UDM ) ) ( /4C431A63/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ11 ) @@ -252,8 +252,8 @@ ( 3 /FPGA_Spartan6/R_M1_DQ9 ) ( 4 /FPGA_Spartan6/R_M1_DQ8 ) ( 5 /FPGA_Spartan6/M1_DQ8 ) - ( 6 /FPGA_Spartan6/M1_DQ9 ) - ( 7 /FPGA_Spartan6/M1_DQ10 ) + ( 6 /DDR_Banks/M1_DQ9 ) + ( 7 /DDR_Banks/M1_DQ10 ) ( 8 /FPGA_Spartan6/M1_DQ11 ) ) ( /4C431A63/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} @@ -261,10 +261,10 @@ ( 2 /FPGA_Spartan6/R_M1_DQ14 ) ( 3 /FPGA_Spartan6/R_M1_DQ13 ) ( 4 /FPGA_Spartan6/R_M1_DQ12 ) - ( 5 /FPGA_Spartan6/M1_DQ12 ) + ( 5 /DDR_Banks/M1_DQ12 ) ( 6 /FPGA_Spartan6/M1_DQ13 ) - ( 7 /FPGA_Spartan6/M1_DQ14 ) - ( 8 /FPGA_Spartan6/M1_DQ15 ) + ( 7 /DDR_Banks/M1_DQ14 ) + ( 8 /DDR_Banks/M1_DQ15 ) ) ( /4C431A63/4C69DF7A 0402 R16 120 {Lib=R} ( 1 /FPGA_Spartan6/M1_CLK# ) @@ -285,7 +285,7 @@ ( 2 /FPGA_Spartan6/R_M1_A6 ) ( 3 /FPGA_Spartan6/R_M1_A5 ) ( 4 ? ) - ( 5 /FPGA_Spartan6/M1_A4 ) + ( 5 /DDR_Banks/M1_A4 ) ( 6 /FPGA_Spartan6/M1_A5 ) ( 7 /FPGA_Spartan6/M1_A6 ) ( 8 /FPGA_Spartan6/M1_A7 ) @@ -295,7 +295,7 @@ ( 2 /FPGA_Spartan6/R_M1_DQ1 ) ( 3 /FPGA_Spartan6/R_M1_DQ2 ) ( 4 /FPGA_Spartan6/R_M1_DQ3 ) - ( 5 /DDR_Banks/M1_DQ3 ) + ( 5 /FPGA_Spartan6/M1_DQ3 ) ( 6 /FPGA_Spartan6/M1_DQ2 ) ( 7 /FPGA_Spartan6/M1_DQ1 ) ( 8 /FPGA_Spartan6/M1_DQ0 ) @@ -305,7 +305,7 @@ ( 2 /FPGA_Spartan6/R_M1_LDM ) ( 3 /FPGA_Spartan6/R_M1_WE# ) ( 4 /FPGA_Spartan6/R_M1_CAS# ) - ( 5 /DDR_Banks/M1_CAS# ) + ( 5 /FPGA_Spartan6/M1_CAS# ) ( 6 /DDR_Banks/M1_WE# ) ( 7 /DDR_Banks/M1_LDM ) ( 8 /DDR_Banks/M1_LDQS ) @@ -316,9 +316,9 @@ ( 3 /FPGA_Spartan6/R_M1_DQ6 ) ( 4 /FPGA_Spartan6/R_M1_DQ7 ) ( 5 /DDR_Banks/M1_DQ7 ) - ( 6 /FPGA_Spartan6/M1_DQ6 ) + ( 6 /DDR_Banks/M1_DQ6 ) ( 7 /FPGA_Spartan6/M1_DQ5 ) - ( 8 /DDR_Banks/M1_DQ4 ) + ( 8 /FPGA_Spartan6/M1_DQ4 ) ) ( /4C431A63/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_RAS# ) @@ -327,8 +327,8 @@ ( 4 /FPGA_Spartan6/R_M1_A10 ) ( 5 /FPGA_Spartan6/M1_A10 ) ( 6 /DDR_Banks/M1_BA1 ) - ( 7 /DDR_Banks/M1_BA0 ) - ( 8 /FPGA_Spartan6/M1_RAS# ) + ( 7 /FPGA_Spartan6/M1_BA0 ) + ( 8 /DDR_Banks/M1_RAS# ) ) ( /4C431A63/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A0 ) @@ -338,7 +338,7 @@ ( 5 /DDR_Banks/M1_A3 ) ( 6 /FPGA_Spartan6/M1_A2 ) ( 7 /FPGA_Spartan6/M1_A1 ) - ( 8 /DDR_Banks/M1_A0 ) + ( 8 /FPGA_Spartan6/M1_A0 ) ) ( /4C431A63/4C656D9D $noname C66 470nF {Lib=C} ( 1 +2.5V ) @@ -480,7 +480,7 @@ ( L6 ? ) ( K6 /FPGA_Spartan6/M0_A3 ) ( J6 ? ) - ( H6 /FPGA_Spartan6/M0_A7 ) + ( H6 /DDR_Banks/M0_A7 ) ( G6 ? ) ( F6 +2.5V ) ( E6 ? ) @@ -527,44 +527,44 @@ ( K8 ? ) ( Y2 ? ) ( W2 +2.5V ) - ( V2 /DDR_Banks/M0_DQ14 ) - ( T2 /FPGA_Spartan6/M0_UDQS ) + ( V2 /FPGA_Spartan6/M0_DQ14 ) + ( T2 /DDR_Banks/M0_UDQS ) ( R2 +2.5V ) - ( P2 /DDR_Banks/M0_DQ8 ) - ( M2 /DDR_Banks/M0_DQ2 ) + ( P2 /FPGA_Spartan6/M0_DQ8 ) + ( M2 /FPGA_Spartan6/M0_DQ2 ) ( L2 +2.5V ) - ( K2 /DDR_Banks/M0_DQ6 ) + ( K2 /FPGA_Spartan6/M0_DQ6 ) ( H2 /FPGA_Spartan6/M0_A0 ) ( G2 +2.5V ) - ( F2 /FPGA_Spartan6/M0_WE# ) + ( F2 /DDR_Banks/M0_WE# ) ( D2 /FPGA_Spartan6/M0_CKE ) ( C2 +2.5V ) ( B2 ? ) ( A2 ? ) ( Y1 ? ) ( W1 ? ) - ( V1 /DDR_Banks/M0_DQ15 ) + ( V1 /FPGA_Spartan6/M0_DQ15 ) ( U1 /DDR_Banks/M0_DQ13 ) ( T1 ? ) ( R1 /FPGA_Spartan6/M0_DQ11 ) - ( P1 /FPGA_Spartan6/M0_DQ9 ) + ( P1 /DDR_Banks/M0_DQ9 ) ( N1 /FPGA_Spartan6/M0_DQ1 ) ( M1 /FPGA_Spartan6/M0_DQ3 ) ( L1 ? ) - ( K1 /FPGA_Spartan6/M0_DQ7 ) + ( K1 /DDR_Banks/M0_DQ7 ) ( J1 /DDR_Banks/M0_DQ5 ) - ( H1 /FPGA_Spartan6/M0_A1 ) + ( H1 /DDR_Banks/M0_A1 ) ( G1 /DDR_Banks/M0_BA1 ) ( T4 ? ) ( R4 ? ) ( P4 ? ) ( N4 ? ) ( M4 ? ) - ( L4 /DDR_Banks/M0_LDM ) + ( L4 /FPGA_Spartan6/M0_LDM ) ( K4 /FPGA_Spartan6/M0_CAS# ) - ( J4 /DDR_Banks/M0_A6 ) + ( J4 /FPGA_Spartan6/M0_A6 ) ( H4 /FPGA_Spartan6/M0_CLK ) - ( G4 /DDR_Banks/M0_A10 ) + ( G4 /FPGA_Spartan6/M0_A10 ) ( F4 +2.5V ) ( E4 ? ) ( C4 ? ) @@ -574,12 +574,12 @@ ( T3 ? ) ( R3 /FPGA_Spartan6/M0_DQ10 ) ( P3 ? ) - ( N3 /DDR_Banks/M0_DQ0 ) + ( N3 /FPGA_Spartan6/M0_DQ0 ) ( M3 /DDR_Banks/M0_UDM ) - ( L3 /FPGA_Spartan6/M0_LDQS ) - ( K3 /FPGA_Spartan6/M0_A5 ) - ( J3 /FPGA_Spartan6/M0_DQ4 ) - ( H3 /FPGA_Spartan6/M0_CLK# ) + ( L3 /DDR_Banks/M0_LDQS ) + ( K3 /DDR_Banks/M0_A5 ) + ( J3 /DDR_Banks/M0_DQ4 ) + ( H3 /DDR_Banks/M0_CLK# ) ( G3 /DDR_Banks/M0_BA0 ) ( F3 /FPGA_Spartan6/M0_A4 ) ( E3 /FPGA_Spartan6/M0_A8 ) @@ -593,24 +593,24 @@ ( A10 /Ethernet_Phy/ETH_INT ) ( E9 +3.3V ) ( D9 /FPGA_Spartan6/ETH_TXD0 ) - ( C9 /FPGA_Spartan6/ETH_TXD2 ) + ( C9 /Ethernet_Phy/ETH_TXD2 ) ( A9 /FPGA_Spartan6/ETH_TXD3 ) - ( D8 /Ethernet_Phy/ETH_RXC ) - ( C8 /Ethernet_Phy/ETH_TXD1 ) - ( B8 /Ethernet_Phy/ETH_TXER ) - ( A8 /FPGA_Spartan6/ETH_TXEN ) - ( D7 /FPGA_Spartan6/ETH_TXC ) + ( D8 /FPGA_Spartan6/ETH_RXC ) + ( C8 /FPGA_Spartan6/ETH_TXD1 ) + ( B8 /FPGA_Spartan6/ETH_TXER ) + ( A8 /Ethernet_Phy/ETH_TXEN ) + ( D7 /Ethernet_Phy/ETH_TXC ) ( C7 /FPGA_Spartan6/ETH_RXDV ) ( B7 +3.3V ) ( A7 /FPGA_Spartan6/ETH_RXER ) - ( D6 /FPGA_Spartan6/ETH_RXD3 ) - ( C6 /Ethernet_Phy/ETH_RXD2 ) - ( B6 /FPGA_Spartan6/ETH_RXD1 ) + ( D6 /Ethernet_Phy/ETH_RXD3 ) + ( C6 /FPGA_Spartan6/ETH_RXD2 ) + ( B6 /Ethernet_Phy/ETH_RXD1 ) ( A6 /FPGA_Spartan6/ETH_RXD0 ) - ( C5 /Ethernet_Phy/ETH_MDIO ) + ( C5 /FPGA_Spartan6/ETH_MDIO ) ( A5 /FPGA_Spartan6/ETH_RESET_N ) ( B4 +3.3V ) - ( A4 /Ethernet_Phy/ETH_CLK ) + ( A4 /FPGA_Spartan6/ETH_CLK ) ( A3 ? ) ( U19 ? ) ( T19 ? ) @@ -620,17 +620,17 @@ ( B18 /Non_volatile_memories/SD_DAT1 ) ( A18 /Non_volatile_memories/SD_DAT0 ) ( E17 +3.3V ) - ( D17 /FPGA_Spartan6/SD_CMD ) + ( D17 /Non_volatile_memories/SD_CMD ) ( C17 /Non_volatile_memories/SD_DAT3 ) ( A17 /Non_volatile_memories/SD_DAT2 ) - ( E16 /Non_volatile_memories/SD_CLK ) - ( C16 /FPGA_Spartan6/NF_CS1_N ) - ( B16 /Non_volatile_memories/NF_RE_N ) - ( A16 /Non_volatile_memories/NF_RNB ) - ( D15 /Non_volatile_memories/NF_CLE ) - ( C15 /Non_volatile_memories/NF_WE_N ) + ( E16 /FPGA_Spartan6/SD_CLK ) + ( C16 /Non_volatile_memories/NF_CS1_N ) + ( B16 /FPGA_Spartan6/NF_RE_N ) + ( A16 /FPGA_Spartan6/NF_RNB ) + ( D15 /FPGA_Spartan6/NF_CLE ) + ( C15 /FPGA_Spartan6/NF_WE_N ) ( B15 +3.3V ) - ( A15 /FPGA_Spartan6/NF_ALE ) + ( A15 /Non_volatile_memories/NF_ALE ) ( G14 +3.3V ) ( D14 /FPGA_Spartan6/NF_D0 ) ( C14 ? ) @@ -638,14 +638,14 @@ ( A14 ? ) ( E13 +3.3V ) ( C13 /FPGA_Spartan6/NF_D2 ) - ( A13 /FPGA_Spartan6/NF_D1 ) + ( A13 /Non_volatile_memories/NF_D1 ) ( C12 /Non_volatile_memories/NF_D5 ) - ( B12 /Non_volatile_memories/NF_D4 ) - ( A12 /FPGA_Spartan6/NF_D3 ) - ( D11 /Non_volatile_memories/NF_D6 ) + ( B12 /FPGA_Spartan6/NF_D4 ) + ( A12 /Non_volatile_memories/NF_D3 ) + ( D11 /FPGA_Spartan6/NF_D6 ) ( C11 ? ) ( B11 +3.3V ) - ( A11 /Non_volatile_memories/NF_D7 ) + ( A11 /FPGA_Spartan6/NF_D7 ) ( J16 ? ) ( H16 /FPGA_Spartan6/R_M1_CS# ) ( G16 ? ) @@ -695,7 +695,7 @@ ( J18 +2.5V ) ( H18 ? ) ( F18 ? ) - ( P17 /FPGA_Spartan6/USBA_VP ) + ( P17 /USB/USBA_VP ) ( M17 ? ) ( L17 ? ) ( K17 /FPGA_Spartan6/R_M1_BA1 ) @@ -703,7 +703,7 @@ ( H17 ? ) ( G17 ? ) ( F17 ? ) - ( N16 /USB/USBA_RCV ) + ( N16 /FPGA_Spartan6/USBA_RCV ) ( M16 ? ) ( L16 +2.5V ) ( K16 ? ) @@ -861,7 +861,7 @@ ( F1 ? ) ( E1 /FPGA_Spartan6/M0_A9 ) ( D1 /FPGA_Spartan6/M0_A12 ) - ( C1 /FPGA_Spartan6/M0_A11 ) + ( C1 /DDR_Banks/M0_A11 ) ( B1 ? ) ( AB19 ? ) ( AA19 VCCO2 ) @@ -999,7 +999,7 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} - ( 1 /Ethernet_Phy/ETH_MDIO ) + ( 1 /FPGA_Spartan6/ETH_MDIO ) ( 2 +3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} @@ -1023,25 +1023,25 @@ ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /Ethernet_Phy/ETH_MDIO ) + ( 1 /FPGA_Spartan6/ETH_MDIO ) ( 2 /Ethernet_Phy/ETH_MDC ) - ( 3 /FPGA_Spartan6/ETH_RXD3 ) - ( 4 /Ethernet_Phy/ETH_RXD2 ) - ( 5 /FPGA_Spartan6/ETH_RXD1 ) + ( 3 /Ethernet_Phy/ETH_RXD3 ) + ( 4 /FPGA_Spartan6/ETH_RXD2 ) + ( 5 /Ethernet_Phy/ETH_RXD1 ) ( 6 /FPGA_Spartan6/ETH_RXD0 ) ( 7 +3.3V ) ( 8 GND ) ( 9 /FPGA_Spartan6/ETH_RXDV ) - ( 10 /Ethernet_Phy/ETH_RXC ) + ( 10 /FPGA_Spartan6/ETH_RXC ) ( 11 /FPGA_Spartan6/ETH_RXER ) ( 12 GND ) ( 13 +1.8V ) - ( 14 /Ethernet_Phy/ETH_TXER ) - ( 15 /FPGA_Spartan6/ETH_TXC ) - ( 16 /FPGA_Spartan6/ETH_TXEN ) + ( 14 /FPGA_Spartan6/ETH_TXER ) + ( 15 /Ethernet_Phy/ETH_TXC ) + ( 16 /Ethernet_Phy/ETH_TXEN ) ( 17 /FPGA_Spartan6/ETH_TXD0 ) - ( 18 /Ethernet_Phy/ETH_TXD1 ) - ( 19 /FPGA_Spartan6/ETH_TXD2 ) + ( 18 /FPGA_Spartan6/ETH_TXD1 ) + ( 19 /Ethernet_Phy/ETH_TXD2 ) ( 20 /FPGA_Spartan6/ETH_TXD3 ) ( 21 /FPGA_Spartan6/ETH_COL ) ( 22 /Ethernet_Phy/ETH_CRS ) @@ -1068,7 +1068,7 @@ ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 /Ethernet_Phy/ETH_CLK ) + ( 46 /FPGA_Spartan6/ETH_CLK ) ( 47 /Ethernet_Phy/ETH_PLL1.8V ) ( 48 /FPGA_Spartan6/ETH_RESET_N ) ) @@ -1119,11 +1119,11 @@ ( 4 /FPGA_Spartan6/M1_DQ1 ) ( 5 /FPGA_Spartan6/M1_DQ2 ) ( 6 GND ) - ( 7 /DDR_Banks/M1_DQ3 ) - ( 8 /DDR_Banks/M1_DQ4 ) + ( 7 /FPGA_Spartan6/M1_DQ3 ) + ( 8 /FPGA_Spartan6/M1_DQ4 ) ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M1_DQ5 ) - ( 11 /FPGA_Spartan6/M1_DQ6 ) + ( 11 /DDR_Banks/M1_DQ6 ) ( 12 GND ) ( 13 /DDR_Banks/M1_DQ7 ) ( 14 ? ) @@ -1134,20 +1134,20 @@ ( 19 ? ) ( 20 /DDR_Banks/M1_LDM ) ( 21 /DDR_Banks/M1_WE# ) - ( 22 /DDR_Banks/M1_CAS# ) - ( 23 /FPGA_Spartan6/M1_RAS# ) - ( 24 /DDR_Banks/M1_CS# ) + ( 22 /FPGA_Spartan6/M1_CAS# ) + ( 23 /DDR_Banks/M1_RAS# ) + ( 24 /FPGA_Spartan6/M1_CS# ) ( 25 ? ) - ( 26 /DDR_Banks/M1_BA0 ) + ( 26 /FPGA_Spartan6/M1_BA0 ) ( 27 /DDR_Banks/M1_BA1 ) ( 28 /FPGA_Spartan6/M1_A10 ) - ( 29 /DDR_Banks/M1_A0 ) + ( 29 /FPGA_Spartan6/M1_A0 ) ( 30 /FPGA_Spartan6/M1_A1 ) ( 31 /FPGA_Spartan6/M1_A2 ) ( 32 /DDR_Banks/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /FPGA_Spartan6/M1_A4 ) + ( 35 /DDR_Banks/M1_A4 ) ( 36 /FPGA_Spartan6/M1_A5 ) ( 37 /FPGA_Spartan6/M1_A6 ) ( 38 /FPGA_Spartan6/M1_A7 ) @@ -1159,7 +1159,7 @@ ( 44 /FPGA_Spartan6/M1_CLK# ) ( 45 /FPGA_Spartan6/M1_CKE ) ( 46 /DDR_Banks/M1_CLK ) - ( 47 /DDR_Banks/M1_UDM ) + ( 47 /FPGA_Spartan6/M1_UDM ) ( 48 GND ) ( 49 N-000058 ) ( 50 ? ) @@ -1168,16 +1168,16 @@ ( 53 ? ) ( 54 /FPGA_Spartan6/M1_DQ8 ) ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M1_DQ9 ) - ( 57 /FPGA_Spartan6/M1_DQ10 ) + ( 56 /DDR_Banks/M1_DQ9 ) + ( 57 /DDR_Banks/M1_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M1_DQ11 ) - ( 60 /FPGA_Spartan6/M1_DQ12 ) + ( 60 /DDR_Banks/M1_DQ12 ) ( 61 +2.5V ) ( 62 /FPGA_Spartan6/M1_DQ13 ) - ( 63 /FPGA_Spartan6/M1_DQ14 ) + ( 63 /DDR_Banks/M1_DQ14 ) ( 64 GND ) - ( 65 /FPGA_Spartan6/M1_DQ15 ) + ( 65 /DDR_Banks/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} @@ -1278,70 +1278,70 @@ ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /DDR_Banks/M0_DQ0 ) + ( 2 /FPGA_Spartan6/M0_DQ0 ) ( 3 +2.5V ) ( 4 /FPGA_Spartan6/M0_DQ1 ) - ( 5 /DDR_Banks/M0_DQ2 ) + ( 5 /FPGA_Spartan6/M0_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M0_DQ3 ) - ( 8 /FPGA_Spartan6/M0_DQ4 ) + ( 8 /DDR_Banks/M0_DQ4 ) ( 9 +2.5V ) ( 10 /DDR_Banks/M0_DQ5 ) - ( 11 /DDR_Banks/M0_DQ6 ) + ( 11 /FPGA_Spartan6/M0_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Spartan6/M0_DQ7 ) + ( 13 /DDR_Banks/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /FPGA_Spartan6/M0_LDQS ) + ( 16 /DDR_Banks/M0_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /DDR_Banks/M0_LDM ) - ( 21 /FPGA_Spartan6/M0_WE# ) + ( 20 /FPGA_Spartan6/M0_LDM ) + ( 21 /DDR_Banks/M0_WE# ) ( 22 /FPGA_Spartan6/M0_CAS# ) ( 23 /DDR_Banks/M0_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /DDR_Banks/M0_BA0 ) ( 27 /DDR_Banks/M0_BA1 ) - ( 28 /DDR_Banks/M0_A10 ) + ( 28 /FPGA_Spartan6/M0_A10 ) ( 29 /FPGA_Spartan6/M0_A0 ) - ( 30 /FPGA_Spartan6/M0_A1 ) + ( 30 /DDR_Banks/M0_A1 ) ( 31 /FPGA_Spartan6/M0_A2 ) ( 32 /FPGA_Spartan6/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M0_A4 ) - ( 36 /FPGA_Spartan6/M0_A5 ) - ( 37 /DDR_Banks/M0_A6 ) - ( 38 /FPGA_Spartan6/M0_A7 ) + ( 36 /DDR_Banks/M0_A5 ) + ( 37 /FPGA_Spartan6/M0_A6 ) + ( 38 /DDR_Banks/M0_A7 ) ( 39 /FPGA_Spartan6/M0_A8 ) ( 40 /FPGA_Spartan6/M0_A9 ) - ( 41 /FPGA_Spartan6/M0_A11 ) + ( 41 /DDR_Banks/M0_A11 ) ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) - ( 44 /FPGA_Spartan6/M0_CLK# ) + ( 44 /DDR_Banks/M0_CLK# ) ( 45 /FPGA_Spartan6/M0_CKE ) ( 46 /FPGA_Spartan6/M0_CLK ) ( 47 /DDR_Banks/M0_UDM ) ( 48 GND ) ( 49 N-000059 ) ( 50 ? ) - ( 51 /FPGA_Spartan6/M0_UDQS ) + ( 51 /DDR_Banks/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M0_DQ8 ) + ( 54 /FPGA_Spartan6/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M0_DQ9 ) + ( 56 /DDR_Banks/M0_DQ9 ) ( 57 /FPGA_Spartan6/M0_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M0_DQ11 ) ( 60 /FPGA_Spartan6/M0_DQ12 ) ( 61 +2.5V ) ( 62 /DDR_Banks/M0_DQ13 ) - ( 63 /DDR_Banks/M0_DQ14 ) + ( 63 /FPGA_Spartan6/M0_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M0_DQ15 ) + ( 65 /FPGA_Spartan6/M0_DQ15 ) ( 66 GND ) ) ) @@ -1848,297 +1848,299 @@ $endfootprintlist Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" U1 T5 U8 1 -Net 2 "/Non volatile memories/NF_RE_N" "NF_RE_N" +Net 2 "/FPGA Spartan6/NF_RE_N" "NF_RE_N" U5 8 U1 B16 -Net 3 "/FPGA Spartan6/NF_CS1_N" "NF_CS1_N" +Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" U5 9 U1 C16 -Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE" - U5 17 +Net 4 "/Non volatile memories/NF_ALE" "NF_ALE" U1 A15 -Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" + U5 17 +Net 5 "/Ethernet Phy/ETH_TXC" "ETH_TXC" U4 15 U1 D7 -Net 6 "/Ethernet Phy/ETH_RXC" "ETH_RXC" - U1 D8 +Net 6 "/FPGA Spartan6/ETH_RXC" "ETH_RXC" U4 10 -Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK" + U1 D8 +Net 7 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" U1 A4 U4 46 Net 8 "/USB/USBA_SPD" "USBA_SPD" - U6 2 U1 R19 + U6 2 Net 9 "/USB/USBA_OE_N" "USBA_OE_N" U6 9 U1 P18 -Net 10 "/USB/USBA_RCV" "USBA_RCV" - U6 3 +Net 10 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" U1 N16 -Net 11 "/FPGA Spartan6/USBA_VP" "USBA_VP" + U6 3 +Net 11 "/USB/USBA_VP" "USBA_VP" U6 4 U1 P17 Net 12 "/FPGA Spartan6/USBA_VM" "USBA_VM" - U6 5 U1 M18 + U6 5 Net 13 "/FPGA Spartan6/ETH_COL" "ETH_COL" U4 21 U1 B10 Net 14 "/Ethernet Phy/ETH_CRS" "ETH_CRS" - U1 C10 U4 22 -Net 15 "/Non volatile memories/SD_CLK" "SD_CLK" - J1 5 + U1 C10 +Net 15 "/FPGA Spartan6/SD_CLK" "SD_CLK" U1 E16 + J1 5 Net 16 "/Ethernet Phy/ETH_INT" "ETH_INT" U1 A10 U4 25 Net 17 "/Ethernet Phy/ETH_MDC" "ETH_MDC" U4 2 U1 D10 -Net 18 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" +Net 18 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" U4 1 R1 1 U1 C5 Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" - U4 48 U1 A5 + U4 48 Net 20 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" U1 C7 U4 9 Net 21 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" - U4 11 U1 A7 -Net 22 "/Ethernet Phy/ETH_TXER" "ETH_TXER" + U4 11 +Net 22 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" U1 B8 U4 14 -Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" - U1 A8 +Net 23 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" U4 16 -Net 24 "/DDR Banks/M1_CS#" "M1_CS#" + U1 A8 +Net 24 "/FPGA Spartan6/M1_CS#" "M1_CS#" U3 24 R20 2 -Net 25 "/DDR Banks/M1_UDM" "M1_UDM" +Net 25 "/FPGA Spartan6/M1_UDM" "M1_UDM" U3 47 R18 2 Net 26 "/DDR Banks/M1_LDQS" "M1_LDQS" - U3 16 RP3 8 + U3 16 Net 27 "/DDR Banks/M1_LDM" "M1_LDM" U3 20 RP3 7 Net 28 "/DDR Banks/M1_UDQS" "M1_UDQS" - U3 51 R19 2 -Net 29 "/FPGA Spartan6/M0_UDQS" "M0_UDQS" + U3 51 +Net 29 "/DDR Banks/M0_UDQS" "M0_UDQS" U1 T2 U2 51 -Net 30 "/DDR Banks/M0_LDM" "M0_LDM" - U2 20 +Net 30 "/FPGA Spartan6/M0_LDM" "M0_LDM" U1 L4 -Net 31 "/DDR Banks/M1_CAS#" "M1_CAS#" - RP3 5 + U2 20 +Net 31 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" U3 22 + RP3 5 Net 32 "/FPGA Spartan6/M1_CKE" "M1_CKE" - R17 2 U3 45 + R17 2 Net 33 "/DDR Banks/M1_CLK" "M1_CLK" + U1 H20 U3 46 R16 2 - U1 H20 Net 34 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" U3 44 - R16 1 U1 J19 + R16 1 Net 35 "GND" "GND" - C28 2 - C25 2 - C29 2 - C24 2 - C32 2 - U1 J9 - U1 E7 - C22 2 - C27 2 - C23 2 - C30 2 - U1 H7 - C33 2 - C74 2 - C31 2 - U1 A1 - U1 E2 - U1 J2 - U4 23 - U1 D4 - J4 5 - J4 4 - U1 V4 - U1 B5 - U1 G5 - U4 39 - U1 L5 - U1 R5 - U2 48 - U2 58 - U1 N2 - U1 U2 - U1 W19 - U1 AA9 - U1 AB22 - C4 2 - U1 AA13 - U1 AA17 - U1 J21 - C40 2 - U5 13 - C2 2 - U1 E21 - C1 2 - U4 36 - U4 12 - C48 2 - C3 2 - U1 W16 - U1 B17 - U1 N17 - R2 2 - C11 2 - C10 2 - U1 D18 - U1 G18 - U1 L18 - C12 2 - U1 R18 - R9 2 - C73 2 - C72 2 - U4 35 - C5 2 - U1 M10 - U1 P10 - U1 V10 + C46 2 C7 2 - U1 J11 - C8 2 - U1 E11 - C45 2 + C49 2 + C51 2 + C5 2 + C3 2 + C1 2 + U4 23 + U5 13 + C12 2 + R9 2 U5 36 - C42 2 - U1 N11 - U8 4 - U1 B9 - U4 44 - U1 L11 - C70 2 - U1 W7 - U1 U7 - U2 34 - U2 24 - U4 8 - U2 52 - U2 12 - C6 2 - U2 66 - C39 2 - C26 2 - C21 2 - C34 2 - C71 2 - U2 6 + C40 2 + C43 2 + C4 2 + C2 2 + C52 2 + C8 2 + U1 K12 + U1 M12 + U1 P12 + U1 AB1 U1 U21 U1 N21 + U1 J21 + U1 E21 + U1 N11 + U1 P14 + U1 M14 + U1 K14 + U1 N13 + U1 L13 + U1 J13 + U1 B13 + U1 A22 + U1 J9 + U1 B9 + U1 W7 + U1 U7 + U1 H7 + C72 2 + C73 2 + U4 36 + U4 35 + U8 4 + U4 44 + C58 2 + C55 2 + C68 2 + C74 2 + C75 1 + U4 39 + C34 2 + C27 2 + C32 2 + C30 2 + C31 2 + C29 2 + C28 2 + C33 2 + C22 2 + C23 2 + C25 2 + C24 2 + C26 2 + C21 2 J1 CASE J1 CASE J1 CASE J1 COM J1 6 - U1 AA5 - C9 2 + C39 2 + C42 2 + C45 2 + R2 2 + C48 2 + C11 2 + C10 2 + C71 2 + C70 2 + U2 34 + U2 24 + U2 52 + U2 12 + U2 66 U2 64 C18 2 C20 2 R12 2 R14 2 - U1 J13 - U1 P14 - U3 64 - U6 8 - U3 34 - C68 2 - U1 K12 - U1 M12 - C15 2 - U1 B13 - C41 2 - C44 2 - C46 2 - U6 7 - U3 52 - U3 58 - U3 48 - C13 2 - C14 2 - C49 2 - C51 2 - C53 2 - U3 66 - C52 2 - V1 2 - C64 2 - C16 2 - R10 2 - C61 2 - L5 2 + U2 6 C63 2 - C60 2 - U1 J15 - C57 2 - C54 2 - U1 L13 C69 2 + C54 2 + C57 2 + C60 2 + C56 2 + C53 2 + C41 2 + C50 2 + C47 2 + C44 2 C66 2 - C43 2 - C67 2 + U1 AA5 + U1 J15 U1 E15 U1 V14 - C58 2 - C55 2 - U1 K10 - U1 AB1 - C62 2 - U1 N9 - C75 1 - U1 L9 - V4 2 - C37 2 - C36 2 - C35 2 - U1 N13 - R15 2 - C38 2 - V3 2 + U1 AA17 + U1 AA13 + U1 AB22 + U1 AA9 + U1 W19 + U4 12 C65 2 - C50 2 - U7 8 - U7 7 - C47 2 - U1 A22 - U1 P12 + C62 2 + C59 2 + U1 E7 + U1 R5 + U1 L5 + U1 G5 + U1 B5 + U1 V4 + U1 L11 + U1 J11 + U1 E11 + U1 V10 + U1 P10 + U1 M10 + U1 K10 + U1 N9 + U1 L9 + U4 8 + U1 R18 + U1 L18 + U1 G18 + U1 D18 + U1 N17 + U1 B17 + U1 W16 + C67 2 + C61 2 + C64 2 + C9 2 + C6 2 + U1 D4 + U1 U2 + U1 N2 + U1 J2 + U1 E2 + U1 A1 + L5 2 + U3 64 + C14 2 U3 12 V2 2 U3 6 - U1 K14 - C56 2 + C15 2 + U9 8 + U2 48 + U2 58 L7 2 - C59 2 - U1 M14 -Net 36 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" + U3 52 + C35 2 + C36 2 + U6 8 + U6 7 + C37 2 + U9 PAD + J4 4 + J4 5 + U7 7 + U7 8 + U3 48 + U3 58 + C13 2 + V4 2 + V3 2 + V1 2 + C38 2 + C16 2 + U3 34 + R10 2 + R15 2 + U3 66 +Net 36 "/DDR Banks/M0_CLK#" "M0_CLK#" U1 H3 U2 44 Net 37 "/FPGA Spartan6/M0_CLK" "M0_CLK" - U1 H4 U2 46 + U1 H4 Net 38 "/FPGA Spartan6/M0_CKE" "M0_CKE" U2 45 U1 D2 @@ -2146,86 +2148,115 @@ Net 39 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" U2 22 U1 K4 Net 40 "/DDR Banks/M1_WE#" "M1_WE#" - RP3 6 U3 21 -Net 41 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" + RP3 6 +Net 41 "/DDR Banks/M1_RAS#" "M1_RAS#" U3 23 RP2 8 Net 42 "/DDR Banks/M0_RAS#" "M0_RAS#" U1 K5 U2 23 -Net 43 "/FPGA Spartan6/M0_WE#" "M0_WE#" +Net 43 "/DDR Banks/M0_WE#" "M0_WE#" U2 21 U1 F2 -Net 44 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" - U1 L3 +Net 44 "/DDR Banks/M0_LDQS" "M0_LDQS" U2 16 + U1 L3 Net 45 "/DDR Banks/M0_UDM" "M0_UDM" - U1 M3 U2 47 + U1 M3 Net 46 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" U8 6 U1 AA21 -Net 47 "/Non volatile memories/NF_RNB" "NF_RNB" +Net 47 "/FPGA Spartan6/NF_RNB" "NF_RNB" + U1 A16 U5 6 U5 7 - U1 A16 -Net 48 "/Non volatile memories/NF_WE_N" "NF_WE_N" +Net 48 "/FPGA Spartan6/NF_WE_N" "NF_WE_N" U5 18 U1 C15 -Net 49 "/Non volatile memories/NF_CLE" "NF_CLE" - U5 16 +Net 49 "/FPGA Spartan6/NF_CLE" "NF_CLE" U1 D15 -Net 50 "/FPGA Spartan6/SD_CMD" "SD_CMD" + U5 16 +Net 50 "/Non volatile memories/SD_CMD" "SD_CMD" J1 3 U1 D17 Net 56 "+2.5V" "+2.5V" - U1 N8 - U1 L8 - U1 H9 - U1 J18 - U1 N5 - U1 N18 - U1 U18 - U1 E19 - U1 L16 - U1 C2 - U1 G2 - U1 L2 - U1 W2 - U1 R2 + U7 1 + U1 H15 + U1 K15 + U1 M15 + U1 D16 + U3 55 U1 W21 + U6 1 U1 R21 U1 L21 U1 G21 U1 C21 - U1 J5 + U3 1 U1 F4 - U1 L7 + U3 15 U1 F6 U1 U5 - U1 R10 - U1 F11 - U1 U11 - U1 R6 - U1 V6 - U1 D16 + U1 N5 + U1 J5 + U3 18 + U1 W2 + U3 33 + U1 R2 + U1 L2 + U1 G2 + U1 C2 + U1 L7 + C46 1 + C52 1 + C43 1 C40 1 + U1 L16 + U3 61 + U1 J18 + C15 1 + U1 N18 + U1 U18 + U1 E19 + C49 1 + U3 9 + U3 3 + C66 1 C37 1 - C27 1 - C32 1 + C51 1 + C53 1 + U1 H9 + U1 N8 + U1 L8 + U1 V6 + U1 R6 + U1 F11 + C56 1 + U1 R10 + C59 1 + C62 1 + C65 1 + C68 1 + U2 1 + U2 3 + U2 9 + R13 1 + R11 1 + U1 R12 + U1 G12 + U1 U11 + C54 1 + C57 1 + C60 1 + C63 1 + C21 1 C34 1 C71 1 C70 1 - U2 33 - U2 61 - U2 18 - U2 55 - U2 15 - C17 1 - C19 1 - R11 1 - R13 1 + C27 1 + C32 1 C30 1 C31 1 C29 1 @@ -2236,267 +2267,238 @@ Net 56 "+2.5V" "+2.5V" C25 1 C24 1 C26 1 - C21 1 - C57 1 - C54 1 - C68 1 - C62 1 - C59 1 - C56 1 - C53 1 - C51 1 - C49 1 - C46 1 - C52 1 - C43 1 - C66 1 - C63 1 - C60 1 - U3 61 - U3 9 - U3 3 - U7 1 - C65 1 - U3 15 - U3 33 - U6 1 - U3 18 - C15 1 - U3 55 - U3 1 - U2 1 - U2 9 - U2 3 - U1 H15 - U1 K15 - U1 M15 - U1 G12 - U1 R12 + C19 1 + U2 61 + U2 18 + U2 33 + C17 1 + U2 55 + U2 15 Net 58 "" "" U3 49 + C19 2 + C20 1 R14 1 R13 2 - C20 1 - C19 2 Net 59 "" "" - R12 1 - R11 2 C17 2 - U2 49 C18 1 + R12 1 + U2 49 + R11 2 Net 98 "+3.3V" "+3.3V" - C3 1 - C5 1 - U6 14 - U6 12 - C14 1 - C13 1 L2 1 - U4 7 + R5 1 C74 1 - U1 B19 - U1 E17 - C75 2 - C41 1 + U4 7 + U6 12 C44 1 - C47 1 - C1 1 - C50 1 - C72 1 - C73 1 - U4 24 - C35 1 - C36 1 + R6 1 J1 4 R4 1 - R1 2 - R6 1 - C11 1 - C10 1 R3 1 + C41 1 + U7 14 + U1 E17 + C11 1 + C14 1 + C73 1 + C13 1 + C72 1 + U1 B15 + C1 1 + U1 G14 + C3 1 + U1 E13 + C5 1 + C35 1 + C36 1 + U4 24 + R1 2 + U7 12 + C10 1 + U1 B19 + U1 B7 + U5 19 + U1 B4 + U5 12 + J4 9 J4 3 J4 6 - J4 9 + U5 37 + C47 1 J4 11 - U1 E13 - U1 B4 + C75 2 + U6 14 U1 E9 U1 G10 - U5 19 U1 B11 - R5 1 - U1 B7 - U5 37 - U5 12 - U7 14 - U7 12 - U1 G14 - U1 B15 + C50 1 Net 99 "VCCO2" "VCCO2" - C55 1 - C58 1 - U1 AA15 - U1 AA19 - U1 AA7 - C61 1 - C64 1 - U1 AA11 - C67 1 - C69 1 - U1 W5 - U1 AA3 - U1 V8 U1 V16 + U1 AA19 + U1 V8 + U1 AA7 + U1 AA15 + U1 AA3 U1 T13 + U1 W5 U1 T9 - U8 8 + C69 1 + C67 1 + C64 1 U1 V12 -Net 194 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" - RP1 1 + C61 1 + U8 8 + U1 AA11 + C58 1 + C55 1 +Net 186 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" U1 F21 -Net 195 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" - U1 E20 + RP1 1 +Net 187 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" RP6 1 -Net 197 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" - RP7 4 + U1 E20 +Net 189 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" U1 C20 -Net 198 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" + RP7 4 +Net 190 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" RP1 4 U1 G20 -Net 207 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" - RP2 3 - U1 K17 -Net 208 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" - RP2 2 - U1 J17 -Net 223 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" +Net 197 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" U1 K19 RP6 2 -Net 224 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" - U1 G19 +Net 198 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" RP2 4 -Net 225 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" - RP7 2 - U1 F19 -Net 232 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" - U1 H21 - RP2 1 -Net 233 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" - U1 H22 - RP3 4 -Net 287 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" - U1 M20 - R18 1 -Net 288 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" - U1 K20 - RP6 3 -Net 297 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" - RP1 2 + U1 G19 +Net 209 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" U1 F22 -Net 298 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" + RP1 2 +Net 210 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" U1 E22 RP1 3 -Net 299 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" +Net 211 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" RP7 1 U1 D22 -Net 300 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" +Net 212 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" U1 C22 RP7 3 +Net 213 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" + U1 F19 + RP7 2 +Net 221 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" + RP2 3 + U1 K17 +Net 222 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" + U1 J17 + RP2 2 +Net 230 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" + RP2 1 + U1 H21 +Net 231 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" + RP3 4 + U1 H22 +Net 285 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" + R18 1 + U1 M20 +Net 286 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" + RP6 3 + U1 K20 Net 302 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" U1 D21 R17 1 Net 334 "+1.2V" "+1.2V" U1 J12 - C48 1 + U1 P11 U1 L12 + U1 M11 + U1 N12 + U1 R14 + C48 1 C45 1 C42 1 - U1 N12 - U1 P13 - U1 M13 + U1 K9 + U1 J8 + C39 1 + U1 K11 + U1 N10 U1 L10 U1 J10 U1 P9 U1 M9 - U1 K9 - U1 J8 - U1 N10 - U1 K11 - U1 M11 - U1 P11 - U1 K13 - C39 1 - U1 R14 + U1 M13 U1 N14 U1 L14 + U1 P13 U1 J14 -Net 335 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" - RP9 2 + U1 K13 +Net 335 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" + U1 H19 + RP3 3 +Net 336 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" + U1 L19 + RP3 2 +Net 337 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" U1 R20 -Net 336 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" + RP9 2 +Net 338 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" U1 R22 RP9 1 -Net 337 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" - RP9 3 +Net 339 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" U1 P22 -Net 338 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" + RP9 3 +Net 340 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" RP8 4 U1 U20 -Net 339 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" +Net 341 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" RP8 3 U1 U22 -Net 340 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" +Net 342 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" U1 V22 RP8 1 -Net 341 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" - RP8 2 +Net 343 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" U1 V21 -Net 342 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" - U1 K21 + RP8 2 +Net 344 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" RP4 3 -Net 343 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" + U1 K21 +Net 345 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" RP4 4 U1 K22 -Net 344 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" +Net 346 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" U1 J22 RP4 2 -Net 345 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" - RP4 1 +Net 347 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" U1 J20 -Net 346 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" - RP9 4 + RP4 1 +Net 348 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" U1 P21 -Net 347 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" + RP9 4 +Net 349 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" RP5 3 U1 M21 -Net 348 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" +Net 350 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" U1 M22 RP5 4 -Net 349 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" +Net 351 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" U1 N22 RP5 2 -Net 350 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" +Net 352 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" RP5 1 U1 N20 -Net 351 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" +Net 353 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" RP3 1 U1 L20 -Net 352 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" - RP3 2 - U1 L19 -Net 353 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" - RP3 3 - U1 H19 -Net 354 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" - R20 1 - U1 H16 -Net 355 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" - R19 1 +Net 354 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" U1 T21 + R19 1 +Net 355 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" + U1 H16 + R20 1 Net 356 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - U4 47 - C9 1 L3 2 + C9 1 + U4 47 Net 357 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" L2 2 C8 1 @@ -2506,84 +2508,84 @@ Net 358 "" "" U4 37 R2 1 Net 361 "" "" - R8 1 J4 12 + R8 1 Net 362 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - U4 27 R8 2 + U4 27 Net 365 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - U4 26 R7 2 + U4 26 Net 367 "+1.8V" "+1.8V" L1 1 + U4 13 C4 1 C2 1 - U4 13 Net 370 "" "" + J4 1 U4 41 R3 2 - J4 1 Net 371 "" "" U4 33 R5 2 J4 7 Net 372 "" "" + R4 2 U4 40 J4 2 - R4 2 Net 373 "" "" - R6 2 U4 32 + R6 2 J4 8 Net 374 "" "" - R7 1 J4 10 + R7 1 Net 375 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" L1 2 - U4 31 C6 1 L3 1 + U4 31 Net 376 "" "" - R9 1 C12 1 + R9 1 J4 14 J4 13 Net 383 "" "" - J5 2 - V2 1 - V2 1 U6 10 + V2 1 + V2 1 + J5 2 Net 384 "" "" J5 4 L5 1 Net 385 "" "" - R10 1 - J5 S1 - J5 S2 - C16 1 J5 S3 + J5 S2 + J5 S1 J5 S4 + C16 1 + R10 1 Net 386 "" "" L6 1 F2 1 Net 388 "+5V" "+5V" - F2 2 F1 2 + F2 2 Net 389 "" "" F1 1 L4 1 Net 390 "" "" - L4 2 J5 1 + L4 2 Net 391 "" "" + V1 1 + V1 1 U6 11 - V1 1 J5 3 - V1 1 Net 392 "" "" - V4 1 - V4 1 U7 10 + V4 1 + V4 1 Net 393 "" "" U7 11 V3 1 @@ -2591,263 +2593,263 @@ Net 393 "" "" Net 394 "" "" R15 1 C38 1 -Net 416 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" +Net 414 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" U8 7 U1 U13 -Net 417 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" +Net 415 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" U8 3 U1 U14 -Net 418 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" - U1 AA20 +Net 416 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" U8 2 -Net 419 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" - U1 AB20 + U1 AA20 +Net 417 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" U8 5 -Net 420 "/Non volatile memories/NF_D7" "NF_D7" - U5 44 + U1 AB20 +Net 418 "/FPGA Spartan6/NF_D7" "NF_D7" U1 A11 -Net 421 "/Non volatile memories/NF_D6" "NF_D6" + U5 44 +Net 419 "/FPGA Spartan6/NF_D6" "NF_D6" U1 D11 U5 43 -Net 422 "/Non volatile memories/NF_D5" "NF_D5" +Net 420 "/Non volatile memories/NF_D5" "NF_D5" U5 42 U1 C12 -Net 423 "/Non volatile memories/NF_D4" "NF_D4" - U5 41 +Net 421 "/FPGA Spartan6/NF_D4" "NF_D4" U1 B12 -Net 424 "/FPGA Spartan6/NF_D3" "NF_D3" - U5 32 + U5 41 +Net 422 "/Non volatile memories/NF_D3" "NF_D3" U1 A12 -Net 425 "/FPGA Spartan6/NF_D2" "NF_D2" - U5 31 + U5 32 +Net 423 "/FPGA Spartan6/NF_D2" "NF_D2" U1 C13 -Net 426 "/FPGA Spartan6/NF_D1" "NF_D1" + U5 31 +Net 424 "/Non volatile memories/NF_D1" "NF_D1" U5 30 U1 A13 -Net 427 "/FPGA Spartan6/NF_D0" "NF_D0" +Net 425 "/FPGA Spartan6/NF_D0" "NF_D0" U5 29 U1 D14 -Net 428 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" - U1 A9 +Net 426 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" U4 20 -Net 429 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" - U4 19 + U1 A9 +Net 427 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" U1 C9 -Net 430 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" + U4 19 +Net 428 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" U1 C8 U4 18 -Net 431 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" - U4 17 +Net 429 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" U1 D9 -Net 432 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" - U1 D6 + U4 17 +Net 430 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" U4 3 -Net 433 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" - U4 4 + U1 D6 +Net 431 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" U1 C6 -Net 434 "/FPGA Spartan6/ETH_RXD1" "ETH_RXD1" - U4 5 + U4 4 +Net 432 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" U1 B6 -Net 435 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" - U4 6 + U4 5 +Net 433 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" U1 A6 -Net 436 "/DDR Banks/M0_BA1" "M0_BA1" - U2 27 + U4 6 +Net 434 "/DDR Banks/M0_BA1" "M0_BA1" U1 G1 -Net 437 "/DDR Banks/M0_BA0" "M0_BA0" - U1 G3 + U2 27 +Net 435 "/DDR Banks/M0_BA0" "M0_BA0" U2 26 -Net 438 "/DDR Banks/M1_BA1" "M1_BA1" - U3 27 + U1 G3 +Net 436 "/DDR Banks/M1_BA1" "M1_BA1" RP2 6 -Net 439 "/DDR Banks/M1_BA0" "M1_BA0" - U3 26 + U3 27 +Net 437 "/FPGA Spartan6/M1_BA0" "M1_BA0" RP2 7 -Net 440 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" + U3 26 +Net 438 "/DDR Banks/M1_DQ15" "M1_DQ15" U3 65 RP8 8 -Net 441 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" +Net 439 "/DDR Banks/M1_DQ14" "M1_DQ14" RP8 7 U3 63 -Net 442 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" +Net 440 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" U3 62 RP8 6 -Net 443 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" +Net 441 "/DDR Banks/M1_DQ12" "M1_DQ12" RP8 5 U3 60 -Net 444 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" - U3 59 +Net 442 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" RP9 8 -Net 445 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" - U3 57 + U3 59 +Net 443 "/DDR Banks/M1_DQ10" "M1_DQ10" RP9 7 -Net 446 "/Non volatile memories/SD_DAT3" "SD_DAT3" + U3 57 +Net 444 "/Non volatile memories/SD_DAT3" "SD_DAT3" J1 2 U1 C17 -Net 447 "/Non volatile memories/SD_DAT2" "SD_DAT2" +Net 445 "/Non volatile memories/SD_DAT2" "SD_DAT2" U1 A17 J1 1 -Net 448 "/Non volatile memories/SD_DAT1" "SD_DAT1" +Net 446 "/Non volatile memories/SD_DAT1" "SD_DAT1" J1 8 U1 B18 -Net 449 "/Non volatile memories/SD_DAT0" "SD_DAT0" +Net 447 "/Non volatile memories/SD_DAT0" "SD_DAT0" U1 A18 J1 7 -Net 450 "/FPGA Spartan6/M1_A7" "M1_A7" - U3 38 +Net 448 "/FPGA Spartan6/M1_A7" "M1_A7" RP6 8 -Net 451 "/FPGA Spartan6/M1_A6" "M1_A6" - RP6 7 + U3 38 +Net 449 "/FPGA Spartan6/M1_A6" "M1_A6" U3 37 -Net 452 "/FPGA Spartan6/M1_A5" "M1_A5" - U3 36 + RP6 7 +Net 450 "/FPGA Spartan6/M1_A5" "M1_A5" RP6 6 -Net 453 "/FPGA Spartan6/M1_A4" "M1_A4" + U3 36 +Net 451 "/DDR Banks/M1_A4" "M1_A4" U3 35 RP6 5 -Net 454 "/DDR Banks/M1_A3" "M1_A3" +Net 452 "/DDR Banks/M1_A3" "M1_A3" U3 32 RP1 5 -Net 455 "/FPGA Spartan6/M1_A2" "M1_A2" - RP1 6 +Net 453 "/FPGA Spartan6/M1_A2" "M1_A2" U3 31 -Net 456 "/FPGA Spartan6/M1_A1" "M1_A1" + RP1 6 +Net 454 "/FPGA Spartan6/M1_A1" "M1_A1" RP1 7 U3 30 -Net 457 "/DDR Banks/M1_A0" "M1_A0" - RP1 8 +Net 455 "/FPGA Spartan6/M1_A0" "M1_A0" U3 29 -Net 458 "/FPGA Spartan6/M0_A12" "M0_A12" - U2 42 + RP1 8 +Net 456 "/FPGA Spartan6/M0_A12" "M0_A12" U1 D1 -Net 459 "/FPGA Spartan6/M0_A11" "M0_A11" - U2 41 + U2 42 +Net 457 "/DDR Banks/M0_A11" "M0_A11" U1 C1 -Net 460 "/DDR Banks/M0_A10" "M0_A10" + U2 41 +Net 458 "/FPGA Spartan6/M0_A10" "M0_A10" U2 28 U1 G4 -Net 461 "/FPGA Spartan6/M0_A9" "M0_A9" - U1 E1 +Net 459 "/FPGA Spartan6/M0_A9" "M0_A9" U2 40 -Net 462 "/FPGA Spartan6/M0_A8" "M0_A8" - U1 E3 + U1 E1 +Net 460 "/FPGA Spartan6/M0_A8" "M0_A8" U2 39 -Net 463 "/FPGA Spartan6/M0_A7" "M0_A7" + U1 E3 +Net 461 "/DDR Banks/M0_A7" "M0_A7" U2 38 U1 H6 -Net 464 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" - RP9 6 +Net 462 "/DDR Banks/M1_DQ9" "M1_DQ9" U3 56 -Net 465 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" - U3 54 + RP9 6 +Net 463 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" RP9 5 -Net 466 "/DDR Banks/M1_DQ7" "M1_DQ7" - RP4 5 + U3 54 +Net 464 "/DDR Banks/M1_DQ7" "M1_DQ7" U3 13 -Net 467 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" - RP4 6 + RP4 5 +Net 465 "/DDR Banks/M1_DQ6" "M1_DQ6" U3 11 -Net 468 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" - RP4 7 + RP4 6 +Net 466 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" U3 10 -Net 469 "/DDR Banks/M1_DQ4" "M1_DQ4" + RP4 7 +Net 467 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" U3 8 RP4 8 -Net 470 "/DDR Banks/M1_DQ3" "M1_DQ3" +Net 468 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" U3 7 RP5 5 -Net 471 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" - RP5 6 +Net 469 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" U3 5 -Net 472 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" - U3 4 + RP5 6 +Net 470 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" RP5 7 -Net 473 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" + U3 4 +Net 471 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" U3 2 RP5 8 -Net 474 "/FPGA Spartan6/M1_A12" "M1_A12" +Net 472 "/FPGA Spartan6/M1_A12" "M1_A12" U3 42 RP7 8 -Net 475 "/FPGA Spartan6/M1_A11" "M1_A11" +Net 473 "/FPGA Spartan6/M1_A11" "M1_A11" RP7 7 U3 41 -Net 476 "/FPGA Spartan6/M1_A10" "M1_A10" +Net 474 "/FPGA Spartan6/M1_A10" "M1_A10" U3 28 RP2 5 -Net 477 "/FPGA Spartan6/M1_A9" "M1_A9" - U3 40 +Net 475 "/FPGA Spartan6/M1_A9" "M1_A9" RP7 6 -Net 478 "/FPGA Spartan6/M1_A8" "M1_A8" - U3 39 + U3 40 +Net 476 "/FPGA Spartan6/M1_A8" "M1_A8" RP7 5 -Net 479 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" - U1 M1 + U3 39 +Net 477 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" U2 7 -Net 480 "/DDR Banks/M0_DQ2" "M0_DQ2" - U1 M2 + U1 M1 +Net 478 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" U2 5 -Net 481 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" - U1 N1 + U1 M2 +Net 479 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" U2 4 -Net 482 "/DDR Banks/M0_DQ0" "M0_DQ0" + U1 N1 +Net 480 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" U2 2 U1 N3 -Net 483 "/DDR Banks/M0_A6" "M0_A6" +Net 481 "/FPGA Spartan6/M0_A6" "M0_A6" U2 37 U1 J4 -Net 484 "/FPGA Spartan6/M0_A5" "M0_A5" - U2 36 +Net 482 "/DDR Banks/M0_A5" "M0_A5" U1 K3 -Net 485 "/FPGA Spartan6/M0_A4" "M0_A4" + U2 36 +Net 483 "/FPGA Spartan6/M0_A4" "M0_A4" U2 35 U1 F3 -Net 486 "/FPGA Spartan6/M0_A3" "M0_A3" - U2 32 +Net 484 "/FPGA Spartan6/M0_A3" "M0_A3" U1 K6 -Net 487 "/FPGA Spartan6/M0_A2" "M0_A2" + U2 32 +Net 485 "/FPGA Spartan6/M0_A2" "M0_A2" U2 31 U1 H5 -Net 488 "/FPGA Spartan6/M0_A1" "M0_A1" +Net 486 "/DDR Banks/M0_A1" "M0_A1" U2 30 U1 H1 -Net 489 "/FPGA Spartan6/M0_A0" "M0_A0" - U1 H2 +Net 487 "/FPGA Spartan6/M0_A0" "M0_A0" U2 29 -Net 490 "/DDR Banks/M0_DQ15" "M0_DQ15" + U1 H2 +Net 488 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" U2 65 U1 V1 -Net 491 "/DDR Banks/M0_DQ14" "M0_DQ14" - U1 V2 +Net 489 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" U2 63 -Net 492 "/DDR Banks/M0_DQ13" "M0_DQ13" + U1 V2 +Net 490 "/DDR Banks/M0_DQ13" "M0_DQ13" U1 U1 U2 62 -Net 493 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" - U2 60 +Net 491 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" U1 U3 -Net 494 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" + U2 60 +Net 492 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" U1 R1 U2 59 -Net 495 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" - U2 57 +Net 493 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" U1 R3 -Net 496 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" + U2 57 +Net 494 "/DDR Banks/M0_DQ9" "M0_DQ9" U1 P1 U2 56 -Net 497 "/DDR Banks/M0_DQ8" "M0_DQ8" - U2 54 +Net 495 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" U1 P2 -Net 498 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" + U2 54 +Net 496 "/DDR Banks/M0_DQ7" "M0_DQ7" U1 K1 U2 13 -Net 499 "/DDR Banks/M0_DQ6" "M0_DQ6" - U2 11 +Net 497 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" U1 K2 -Net 500 "/DDR Banks/M0_DQ5" "M0_DQ5" + U2 11 +Net 498 "/DDR Banks/M0_DQ5" "M0_DQ5" U2 10 U1 J1 -Net 501 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" - U1 J3 +Net 499 "/DDR Banks/M0_DQ4" "M0_DQ4" U2 8 + U1 J3 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index d5539b3..ba4848d 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Mon 16 Aug 2010 09:07:50 PM COT +update=Mon 16 Aug 2010 09:47:07 PM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 1e6d29f..fb23b73 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:05:01 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03