From 8f8f332469881724faa11e3a2d36d1754882790a Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Fri, 13 Aug 2010 18:20:50 -0500 Subject: [PATCH] decoupling DDR cap. placement --- kicad/xue-rnc/DRAM.sch | 118 ++- kicad/xue-rnc/FPGA.sch | 672 +++++++------- kicad/xue-rnc/NV_MEMORIES.sch | 2 +- kicad/xue-rnc/USB.sch | 2 +- kicad/xue-rnc/eth_phy.sch | 2 +- kicad/xue-rnc/xue-rnc-cache.lib | 2 +- kicad/xue-rnc/xue-rnc.brd | 1513 ++++++++++++++++--------------- kicad/xue-rnc/xue-rnc.net | 1438 ++++++++++++++--------------- kicad/xue-rnc/xue-rnc.sch | 2 +- 9 files changed, 1934 insertions(+), 1817 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index fdcd230..fa3cde0 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -56,8 +56,16 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Text Notes 8000 7300 0 60 ~ 0 -Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com +Connection ~ 4050 6200 +Wire Wire Line + 4350 6200 2200 6200 +Wire Wire Line + 4350 6200 4350 6100 +Connection ~ 9300 6200 +Wire Wire Line + 9600 6100 9600 6200 +Wire Wire Line + 9600 6200 7450 6200 Wire Bus Line 4800 3750 4800 5350 Wire Wire Line @@ -421,17 +429,13 @@ Connection ~ 10150 1600 Wire Wire Line 10150 2100 10150 1950 Wire Wire Line - 2200 6100 2200 6200 -Wire Wire Line - 2200 6200 4050 6200 + 2200 6200 2200 6100 Wire Wire Line 4050 6200 4050 6100 Wire Wire Line - 4050 5900 4050 5800 + 4050 5800 4050 5900 Wire Wire Line - 4050 5800 2200 5800 -Wire Wire Line - 2200 5800 2200 5900 + 2200 5900 2200 5800 Wire Wire Line 2600 6100 2600 6200 Connection ~ 2600 6200 @@ -460,14 +464,10 @@ Wire Wire Line 7850 6100 7850 6200 Wire Wire Line 7450 5900 7450 5800 -Wire Wire Line - 7450 5800 9300 5800 Wire Wire Line 9300 5800 9300 5900 Wire Wire Line - 9300 6100 9300 6200 -Wire Wire Line - 9300 6200 7450 6200 + 9300 6200 9300 6100 Wire Wire Line 7450 6200 7450 6100 Wire Wire Line @@ -484,6 +484,38 @@ Wire Wire Line 3050 1750 3050 1800 Wire Bus Line 10050 3750 10050 5400 +Wire Wire Line + 9600 5900 9600 5800 +Wire Wire Line + 9600 5800 7450 5800 +Connection ~ 9300 5800 +Wire Wire Line + 2200 5800 4350 5800 +Wire Wire Line + 4350 5800 4350 5900 +Connection ~ 4050 5800 +$Comp +L CAP C70 +U 1 1 4C65D2A9 +P 4350 6000 +F 0 "C70" H 4400 6100 50 0000 L CNN +F 1 "10nF" H 4400 5900 50 0000 L CNN +F 2 "0402" H 4350 6000 60 0001 C CNN + 1 4350 6000 + 1 0 0 -1 +$EndComp +$Comp +L CAP C71 +U 1 1 4C65D28E +P 9600 6000 +F 0 "C71" H 9650 6100 50 0000 L CNN +F 1 "10nF" H 9650 5900 50 0000 L CNN +F 2 "0402" H 9600 6000 60 0001 C CNN + 1 9600 6000 + 1 0 0 -1 +$EndComp +Text Notes 8000 7300 0 60 ~ 0 +Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com Entry Wire Line 6650 4750 6750 4650 Entry Wire Line @@ -501,37 +533,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR039 +L GND #PWR038 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR039" H 6900 6200 30 0001 C CNN +F 0 "#PWR038" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR040 +L +2.5V #PWR039 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR040" H 6900 5750 20 0001 C CNN +F 0 "#PWR039" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR041 +L +2.5V #PWR040 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR041" H 1700 5750 20 0001 C CNN +F 0 "#PWR040" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR042 +L GND #PWR041 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR042" H 1700 6200 30 0001 C CNN +F 0 "#PWR041" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -547,19 +579,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR043 +L +2.5V #PWR042 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR043" H 3050 1700 20 0001 C CNN +F 0 "#PWR042" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR044 +L +2.5V #PWR043 U 1 1 4C61CFC6 P 8300 1750 -F 0 "#PWR044" H 8300 1700 20 0001 C CNN +F 0 "#PWR043" H 8300 1700 20 0001 C CNN F 1 "+2.5V" H 8300 1850 30 0000 C CNN 1 8300 1750 1 0 0 -1 @@ -625,37 +657,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR045 +L +2.5V #PWR044 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR045" H 8300 5700 20 0001 C CNN +F 0 "#PWR044" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR046 +L GND #PWR045 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR046" H 8300 6350 30 0001 C CNN +F 0 "#PWR045" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR047 +L GND #PWR046 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR047" H 3050 6350 30 0001 C CNN +F 0 "#PWR046" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR048 +L +2.5V #PWR047 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR048" H 3050 5700 20 0001 C CNN +F 0 "#PWR047" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -741,19 +773,19 @@ F 2 "0402" H 9850 1850 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR049 +L +2.5V #PWR048 U 1 1 4C61CE2F P 9850 1000 -F 0 "#PWR049" H 9850 950 20 0001 C CNN +F 0 "#PWR048" H 9850 950 20 0001 C CNN F 1 "+2.5V" H 9850 1100 30 0000 C CNN 1 9850 1000 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR050 +L +2.5V #PWR049 U 1 1 4C61CDF1 P 4550 900 -F 0 "#PWR050" H 4550 850 20 0001 C CNN +F 0 "#PWR049" H 4550 850 20 0001 C CNN F 1 "+2.5V" H 4550 1000 30 0000 C CNN 1 4550 900 1 0 0 -1 @@ -845,10 +877,10 @@ $EndComp Text HLabel 4950 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR051 +L GND #PWR050 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR051" H 3000 5200 30 0001 C CNN +F 0 "#PWR050" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1142,10 +1174,10 @@ Entry Wire Line Entry Wire Line 9950 3650 10050 3750 $Comp -L GND #PWR052 +L GND #PWR051 U 1 1 4C437C3F P 8250 5200 -F 0 "#PWR052" H 8250 5200 30 0001 C CNN +F 0 "#PWR051" H 8250 5200 30 0001 C CNN F 1 "GND" H 8250 5130 30 0001 C CNN 1 8250 5200 1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index c7a995a..6946dd8 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -57,24 +57,33 @@ Comment3 "" Comment4 "" $EndDescr $Comp -L +2.5V #PWR? -U 1 1 4C65C84B -P 4300 14900 -F 0 "#PWR?" H 4300 14850 20 0001 C CNN -F 1 "+2.5V" H 4300 15000 30 0000 C CNN - 1 4300 14900 +L +3.3V #PWR019 +U 1 1 4C65CF66 +P 1650 14300 +F 0 "#PWR019" H 1650 14260 30 0001 C CNN +F 1 "+3.3V" H 1650 14410 30 0000 C CNN + 1 1650 14300 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR? -U 1 1 4C65C837 -P 4300 12950 -F 0 "#PWR?" H 4300 12900 20 0001 C CNN -F 1 "+2.5V" H 4300 13050 30 0000 C CNN - 1 4300 12950 +L +2.5V #PWR020 +U 1 1 4C65C84B +P 4600 14300 +F 0 "#PWR020" H 4600 14250 20 0001 C CNN +F 1 "+2.5V" H 4600 14400 30 0000 C CNN + 1 4600 14300 1 0 0 -1 $EndComp -Text GLabel 4300 13950 1 30 BiDi ~ 0 +$Comp +L +2.5V #PWR021 +U 1 1 4C65C837 +P 4600 12350 +F 0 "#PWR021" H 4600 12300 20 0001 C CNN +F 1 "+2.5V" H 4600 12450 30 0000 C CNN + 1 4600 12350 + 1 0 0 -1 +$EndComp +Text GLabel 4600 13350 1 30 BiDi ~ 0 VCCO2 Text Label 2200 7800 2 60 ~ 0 PROG_MISO3 @@ -100,163 +109,163 @@ Wire Wire Line 18000 7450 17650 7450 Wire Wire Line 18000 7250 17650 7250 -Connection ~ 5350 13500 +Connection ~ 5650 12900 Wire Wire Line - 5700 13450 5700 13500 + 6000 12850 6000 12900 Wire Wire Line - 5700 13500 4300 13500 -Connection ~ 4300 13500 + 6000 12900 4600 12900 +Connection ~ 4600 12900 Wire Wire Line - 4300 13450 4300 13550 -Connection ~ 5000 13500 + 4600 12850 4600 12950 +Connection ~ 5300 12900 Wire Wire Line - 5000 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Wire Notes Line - 6450 15600 1050 15600 + 6750 15000 1350 15000 Wire Notes Line - 1050 15600 1050 12800 + 1350 15000 1350 12200 Wire Notes Line - 1050 12800 6450 12800 + 1350 12200 6750 12200 Wire Wire Line 17650 7350 18000 7350 Wire Wire Line @@ -1165,373 +1174,364 @@ PROG_CSO $Comp L C C66 U 1 1 4C656D9D -P 5700 13250 -F 0 "C66" H 5750 13350 50 0000 L CNN -F 1 "470nF" H 5750 13150 50 0000 L CNN - 1 5700 13250 +P 6000 12650 +F 0 "C66" H 6050 12750 50 0000 L CNN +F 1 "470nF" H 6050 12550 50 0000 L CNN + 1 6000 12650 1 0 0 -1 $EndComp $Comp -L GND #PWR020 +L GND #PWR022 U 1 1 4C656D9B -P 4300 13550 -F 0 "#PWR020" H 4300 13550 30 0001 C CNN -F 1 "GND" H 4300 13480 30 0001 C CNN - 1 4300 13550 +P 4600 12950 +F 0 "#PWR022" H 4600 12950 30 0001 C CNN +F 1 "GND" H 4600 12880 30 0001 C CNN + 1 4600 12950 1 0 0 -1 $EndComp -Text Notes 4400 12950 0 30 ~ 0 +Text Notes 4700 12350 0 30 ~ 0 BANK1 Decoupling Capacitors (5) $Comp L C C63 U 1 1 4C656D9A -P 5350 13250 -F 0 "C63" H 5400 13350 50 0000 L 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5350 14250 +P 5650 13650 +F 0 "C64" H 5700 13750 50 0000 L CNN +F 1 "470nF" H 5700 13550 50 0000 L CNN + 1 5650 13650 1 0 0 -1 $EndComp $Comp L C C61 U 1 1 4C656D45 -P 5000 14250 -F 0 "C61" H 5050 14350 50 0000 L CNN -F 1 "470nF" H 5050 14150 50 0000 L CNN - 1 5000 14250 +P 5300 13650 +F 0 "C61" H 5350 13750 50 0000 L CNN +F 1 "470nF" H 5350 13550 50 0000 L CNN + 1 5300 13650 1 0 0 -1 $EndComp $Comp L C C58 U 1 1 4C656D44 -P 4650 14250 -F 0 "C58" H 4700 14350 50 0000 L CNN -F 1 "4.7uF" H 4700 14150 50 0000 L CNN - 1 4650 14250 +P 4950 13650 +F 0 "C58" H 5000 13750 50 0000 L CNN +F 1 "4.7uF" H 5000 13550 50 0000 L CNN + 1 4950 13650 1 0 0 -1 $EndComp $Comp L C C55 U 1 1 4C656D43 -P 4300 14250 -F 0 "C55" H 4350 14350 50 0000 L CNN -F 1 "100uF" H 4350 14150 50 0000 L CNN - 1 4300 14250 +P 4600 13650 +F 0 "C55" H 4650 13750 50 0000 L CNN +F 1 "100uF" H 4650 13550 50 0000 L CNN + 1 4600 13650 1 0 0 -1 $EndComp $Comp L C C68 U 1 1 4C656D08 -P 5700 15200 -F 0 "C68" H 5750 15300 50 0000 L CNN -F 1 "470nF" H 5750 15100 50 0000 L CNN - 1 5700 15200 +P 6000 14600 +F 0 "C68" H 6050 14700 50 0000 L CNN +F 1 "470nF" H 6050 14500 50 0000 L CNN + 1 6000 14600 1 0 0 -1 $EndComp $Comp L GND #PWR024 U 1 1 4C656CFD -P 4300 15500 -F 0 "#PWR024" H 4300 15500 30 0001 C CNN -F 1 "GND" H 4300 15430 30 0001 C CNN - 1 4300 15500 +P 4600 14900 +F 0 "#PWR024" H 4600 14900 30 0001 C CNN +F 1 "GND" H 4600 14830 30 0001 C CNN + 1 4600 14900 1 0 0 -1 $EndComp -Text Notes 4400 14900 0 30 ~ 0 +Text Notes 4700 14300 0 30 ~ 0 BANK3 Decoupling Capacitors (5) $Comp L C C65 U 1 1 4C656CFC -P 5350 15200 -F 0 "C65" H 5400 15300 50 0000 L CNN -F 1 "470nF" H 5400 15100 50 0000 L CNN - 1 5350 15200 +P 5650 14600 +F 0 "C65" H 5700 14700 50 0000 L CNN +F 1 "470nF" H 5700 14500 50 0000 L CNN + 1 5650 14600 1 0 0 -1 $EndComp $Comp L C C62 U 1 1 4C656CFB -P 5000 15200 -F 0 "C62" H 5050 15300 50 0000 L CNN -F 1 "470nF" H 5050 15100 50 0000 L CNN - 1 5000 15200 +P 5300 14600 +F 0 "C62" H 5350 14700 50 0000 L CNN +F 1 "470nF" H 5350 14500 50 0000 L CNN + 1 5300 14600 1 0 0 -1 $EndComp $Comp L C C59 U 1 1 4C656CFA -P 4650 15200 -F 0 "C59" H 4700 15300 50 0000 L CNN -F 1 "4.7uF" H 4700 15100 50 0000 L CNN - 1 4650 15200 +P 4950 14600 +F 0 "C59" H 5000 14700 50 0000 L CNN +F 1 "4.7uF" H 5000 14500 50 0000 L CNN + 1 4950 14600 1 0 0 -1 $EndComp $Comp L C C56 U 1 1 4C656CF9 -P 4300 15200 -F 0 "C56" H 4350 15300 50 0000 L CNN -F 1 "100uF" H 4350 15100 50 0000 L CNN - 1 4300 15200 +P 4600 14600 +F 0 "C56" H 4650 14700 50 0000 L CNN +F 1 "100uF" H 4650 14500 50 0000 L CNN + 1 4600 14600 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR025 -U 1 1 4C656CC3 -P 1350 14900 -F 0 "#PWR025" H 1350 14850 20 0001 C CNN -F 1 "+2.5V" H 1350 15000 30 0000 C CNN - 1 1350 14900 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR026 +L GND #PWR025 U 1 1 4C656CBC -P 1350 15500 -F 0 "#PWR026" H 1350 15500 30 0001 C CNN -F 1 "GND" H 1350 15430 30 0001 C CNN - 1 1350 15500 +P 1650 14900 +F 0 "#PWR025" H 1650 14900 30 0001 C CNN +F 1 "GND" H 1650 14830 30 0001 C CNN + 1 1650 14900 1 0 0 -1 $EndComp -Text Notes 1450 14900 0 30 ~ 0 +Text Notes 1750 14300 0 30 ~ 0 BANK0 Decoupling Capacitors (4) $Comp L C C50 U 1 1 4C656CBB -P 2400 15200 -F 0 "C50" H 2450 15300 50 0000 L CNN -F 1 "470nF" H 2450 15100 50 0000 L CNN - 1 2400 15200 +P 2700 14600 +F 0 "C50" H 2750 14700 50 0000 L CNN +F 1 "470nF" H 2750 14500 50 0000 L CNN + 1 2700 14600 1 0 0 -1 $EndComp $Comp L C C47 U 1 1 4C656CBA -P 2050 15200 -F 0 "C47" H 2100 15300 50 0000 L CNN -F 1 "470nF" H 2100 15100 50 0000 L CNN - 1 2050 15200 +P 2350 14600 +F 0 "C47" H 2400 14700 50 0000 L CNN +F 1 "470nF" H 2400 14500 50 0000 L CNN + 1 2350 14600 1 0 0 -1 $EndComp $Comp L C C44 U 1 1 4C656CB9 -P 1700 15200 -F 0 "C44" H 1750 15300 50 0000 L CNN -F 1 "4.7uF" H 1750 15100 50 0000 L CNN - 1 1700 15200 +P 2000 14600 +F 0 "C44" H 2050 14700 50 0000 L CNN +F 1 "4.7uF" H 2050 14500 50 0000 L CNN + 1 2000 14600 1 0 0 -1 $EndComp $Comp L C C41 U 1 1 4C656CB7 -P 1350 15200 -F 0 "C41" H 1400 15300 50 0000 L CNN -F 1 "100uF" H 1400 15100 50 0000 L CNN - 1 1350 15200 +P 1650 14600 +F 0 "C41" H 1700 14700 50 0000 L CNN +F 1 "100uF" H 1700 14500 50 0000 L CNN + 1 1650 14600 1 0 0 -1 $EndComp -Text Notes 1450 14000 0 30 ~ 0 +Text Notes 1750 13400 0 30 ~ 0 VCC_AUX Decoupling Capacitors (7) $Comp -L GND #PWR027 +L GND #PWR026 U 1 1 4C656C68 -P 1350 14600 -F 0 "#PWR027" H 1350 14600 30 0001 C CNN -F 1 "GND" H 1350 14530 30 0001 C CNN - 1 1350 14600 +P 1650 14000 +F 0 "#PWR026" H 1650 14000 30 0001 C CNN +F 1 "GND" H 1650 13930 30 0001 C CNN + 1 1650 14000 1 0 0 -1 $EndComp $Comp L C C53 U 1 1 4C656C49 -P 3400 14300 -F 0 "C53" H 3450 14400 50 0000 L CNN -F 1 "470nF" H 3450 14200 50 0000 L CNN - 1 3400 14300 +P 3700 13700 +F 0 "C53" H 3750 13800 50 0000 L CNN +F 1 "470nF" H 3750 13600 50 0000 L CNN + 1 3700 13700 1 0 0 -1 $EndComp $Comp L C C51 U 1 1 4C656C27 -P 2750 14300 -F 0 "C51" H 2800 14400 50 0000 L CNN -F 1 "470nF" H 2800 14200 50 0000 L CNN - 1 2750 14300 +P 3050 13700 +F 0 "C51" H 3100 13800 50 0000 L CNN +F 1 "470nF" H 3100 13600 50 0000 L CNN + 1 3050 13700 1 0 0 -1 $EndComp $Comp L C C49 U 1 1 4C656C24 -P 2400 14300 -F 0 "C49" H 2450 14400 50 0000 L CNN -F 1 "470nF" H 2450 14200 50 0000 L CNN - 1 2400 14300 +P 2700 13700 +F 0 "C49" H 2750 13800 50 0000 L CNN +F 1 "470nF" H 2750 13600 50 0000 L CNN + 1 2700 13700 1 0 0 -1 $EndComp $Comp L C C46 U 1 1 4C656C16 -P 2050 14300 -F 0 "C46" H 2100 14400 50 0000 L CNN -F 1 "4.7uF" H 2100 14200 50 0000 L CNN - 1 2050 14300 +P 2350 13700 +F 0 "C46" H 2400 13800 50 0000 L CNN +F 1 "4.7uF" H 2400 13600 50 0000 L CNN + 1 2350 13700 1 0 0 -1 $EndComp $Comp L C C52 U 1 1 4C656BFA -P 3050 14300 -F 0 "C52" H 3100 14400 50 0000 L CNN -F 1 "470nF" H 3100 14200 50 0000 L CNN - 1 3050 14300 +P 3350 13700 +F 0 "C52" H 3400 13800 50 0000 L CNN +F 1 "470nF" H 3400 13600 50 0000 L CNN + 1 3350 13700 1 0 0 -1 $EndComp $Comp L C C43 U 1 1 4C656BF9 -P 1700 14300 -F 0 "C43" H 1750 14400 50 0000 L CNN -F 1 "4.7uF" H 1750 14200 50 0000 L CNN - 1 1700 14300 +P 2000 13700 +F 0 "C43" H 2050 13800 50 0000 L CNN +F 1 "4.7uF" H 2050 13600 50 0000 L CNN + 1 2000 13700 1 0 0 -1 $EndComp $Comp L C C40 U 1 1 4C656BF8 -P 1350 14300 -F 0 "C40" H 1400 14400 50 0000 L CNN -F 1 "100uF" H 1400 14200 50 0000 L CNN - 1 1350 14300 +P 1650 13700 +F 0 "C40" H 1700 13800 50 0000 L CNN +F 1 "100uF" H 1700 13600 50 0000 L CNN + 1 1650 13700 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR028 +L +2.5V #PWR027 U 1 1 4C656BBA -P 1350 14000 -F 0 "#PWR028" H 1350 13950 20 0001 C CNN -F 1 "+2.5V" H 1350 14100 30 0000 C CNN - 1 1350 14000 +P 1650 13400 +F 0 "#PWR027" H 1650 13350 20 0001 C CNN +F 1 "+2.5V" H 1650 13500 30 0000 C CNN + 1 1650 13400 1 0 0 -1 $EndComp $Comp -L GND #PWR029 +L GND #PWR028 U 1 1 4C656BA8 -P 1350 13550 -F 0 "#PWR029" H 1350 13550 30 0001 C CNN -F 1 "GND" H 1350 13480 30 0001 C CNN - 1 1350 13550 +P 1650 12950 +F 0 "#PWR028" H 1650 12950 30 0001 C CNN +F 1 "GND" H 1650 12880 30 0001 C CNN + 1 1650 12950 1 0 0 -1 $EndComp -Text Notes 1450 12950 0 30 ~ 0 +Text Notes 1750 12350 0 30 ~ 0 VCC_INT Decoupling Capacitors (4) $Comp L C C48 U 1 1 4C656AC2 -P 2400 13250 -F 0 "C48" H 2450 13350 50 0000 L CNN -F 1 "470nF" H 2450 13150 50 0000 L CNN - 1 2400 13250 +P 2700 12650 +F 0 "C48" H 2750 12750 50 0000 L CNN +F 1 "470nF" H 2750 12550 50 0000 L CNN + 1 2700 12650 1 0 0 -1 $EndComp $Comp L C C45 U 1 1 4C656AC0 -P 2050 13250 -F 0 "C45" H 2100 13350 50 0000 L CNN -F 1 "470nF" H 2100 13150 50 0000 L CNN - 1 2050 13250 +P 2350 12650 +F 0 "C45" H 2400 12750 50 0000 L CNN +F 1 "470nF" H 2400 12550 50 0000 L CNN + 1 2350 12650 1 0 0 -1 $EndComp $Comp L C C42 U 1 1 4C656ABD -P 1700 13250 -F 0 "C42" H 1750 13350 50 0000 L CNN -F 1 "4.7uF" H 1750 13150 50 0000 L CNN - 1 1700 13250 +P 2000 12650 +F 0 "C42" H 2050 12750 50 0000 L CNN +F 1 "4.7uF" H 2050 12550 50 0000 L CNN + 1 2000 12650 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR030 +L +1.2V #PWR029 U 1 1 4C656AA1 -P 1350 12950 -F 0 "#PWR030" H 1350 13090 20 0001 C CNN -F 1 "+1.2V" H 1350 13060 30 0000 C CNN - 1 1350 12950 +P 1650 12350 +F 0 "#PWR029" H 1650 12490 20 0001 C CNN +F 1 "+1.2V" H 1650 12460 30 0000 C CNN + 1 1650 12350 1 0 0 -1 $EndComp $Comp L C C39 U 1 1 4C656A80 -P 1350 13250 -F 0 "C39" H 1400 13350 50 0000 L CNN -F 1 "100uF" H 1400 13150 50 0000 L CNN - 1 1350 13250 +P 1650 12650 +F 0 "C39" H 1700 12750 50 0000 L CNN +F 1 "100uF" H 1700 12550 50 0000 L CNN + 1 1650 12650 1 0 0 -1 $EndComp Text HLabel 18650 8050 2 60 BiDi ~ 0 @@ -1585,46 +1585,46 @@ NF_RE_N Text HLabel 18000 7250 2 60 BiDi ~ 0 NF_RNB $Comp -L +3.3V #PWR031 +L +3.3V #PWR030 U 1 1 4C61E5B3 P 15900 6100 -F 0 "#PWR031" H 15900 6060 30 0001 C CNN +F 0 "#PWR030" H 15900 6060 30 0001 C CNN F 1 "+3.3V" H 15900 6210 30 0000 C CNN 1 15900 6100 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR032 +L +1.2V #PWR031 U 1 1 4C61E58C P 16500 9850 -F 0 "#PWR032" H 16500 9990 20 0001 C CNN +F 0 "#PWR031" H 16500 9990 20 0001 C CNN F 1 "+1.2V" H 16500 9960 30 0000 C CNN 1 16500 9850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR033 +L +2.5V #PWR032 U 1 1 4C61E577 P 15000 9850 -F 0 "#PWR033" H 15000 9800 20 0001 C CNN +F 0 "#PWR032" H 15000 9800 20 0001 C CNN F 1 "+2.5V" H 15000 9950 30 0000 C CNN 1 15000 9850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR034 +L +2.5V #PWR033 U 1 1 4C61E523 P 16000 600 -F 0 "#PWR034" H 16000 550 20 0001 C CNN +F 0 "#PWR033" H 16000 550 20 0001 C CNN F 1 "+2.5V" H 16000 700 30 0000 C CNN 1 16000 600 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR035 +L +2.5V #PWR034 U 1 1 4C61E51F P 5300 650 -F 0 "#PWR035" H 5300 600 20 0001 C CNN +F 0 "#PWR034" H 5300 600 20 0001 C CNN F 1 "+2.5V" H 5300 750 30 0000 C CNN 1 5300 650 1 0 0 -1 @@ -1670,19 +1670,19 @@ M0_BA[0..1] Text HLabel 12400 4850 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR036 +L GND #PWR035 U 1 1 4C60C24F P 12550 5100 -F 0 "#PWR036" H 12550 5100 30 0001 C CNN +F 0 "#PWR035" H 12550 5100 30 0001 C CNN F 1 "GND" H 12550 5030 30 0001 C CNN 1 12550 5100 -1 0 0 -1 $EndComp $Comp -L GND #PWR037 +L GND #PWR036 U 1 1 4C60C21D P 1600 5950 -F 0 "#PWR037" H 1600 5950 30 0001 C CNN +F 0 "#PWR036" H 1600 5950 30 0001 C CNN F 1 "GND" H 1600 5880 30 0001 C CNN 1 1600 5950 -1 0 0 -1 @@ -2158,10 +2158,10 @@ M0_CLK Text HLabel 7750 4700 2 60 Output ~ 0 M0_CLK# $Comp -L GND #PWR038 +L GND #PWR037 U 1 1 4C439B7E P 16400 12650 -F 0 "#PWR038" H 16400 12650 30 0001 C CNN +F 0 "#PWR037" H 16400 12650 30 0001 C CNN F 1 "GND" H 16400 12580 30 0001 C CNN 1 16400 12650 -1 0 0 -1 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 34b6ee8..4454fbb 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 18991c4..90c8670 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 0f7a05a..e5dd12d 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index c8ec7e9..aa410ec 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Fri 13 Aug 2010 05:33:51 PM COT +EESchema-LIBRARY Version 2.3 Date: Fri 13 Aug 2010 06:19:04 PM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 42ddf6a..a9c249b 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Fri 13 Aug 2010 05:25:57 PM COT +PCBNEW-BOARD Version 1 date Fri 13 Aug 2010 06:20:14 PM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -6,15 +6,15 @@ $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 1FFF801F -Links 526 -NoConn 526 +Links 530 +NoConn 530 Di 39754 13449 70210 50403 Ndraw 2 Ntrack 0 Nzone 0 BoardThickness 630 -Nmodule 108 -Nnets 174 +Nmodule 110 +Nnets 175 $EndGENERAL $SHEETDESCR @@ -90,427 +90,427 @@ Na 5 "/DDR_Banks/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A4" +Na 6 "/DDR_Banks/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_A5" +Na 7 "/DDR_Banks/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_A6" +Na 8 "/DDR_Banks/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_A8" +Na 9 "/DDR_Banks/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_BA1" +Na 10 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_CKE" +Na 11 "/DDR_Banks/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_CLK" +Na 12 "/DDR_Banks/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_CLK#" +Na 13 "/DDR_Banks/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_DQ1" +Na 14 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_DQ11" +Na 15 "/DDR_Banks/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_DQ13" +Na 16 "/DDR_Banks/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_DQ2" +Na 17 "/DDR_Banks/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_DQ5" +Na 18 "/DDR_Banks/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_DQ6" +Na 19 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M0_DQ7" +Na 20 "/DDR_Banks/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M0_DQ9" +Na 21 "/DDR_Banks/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M0_RAS#" +Na 22 "/DDR_Banks/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M0_UDM" +Na 23 "/DDR_Banks/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M0_WE#" +Na 24 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_A1" +Na 25 "/DDR_Banks/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_A10" +Na 26 "/DDR_Banks/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_BA0" +Na 27 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_BA1" +Na 28 "/DDR_Banks/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_CKE" +Na 29 "/DDR_Banks/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_DQ12" +Na 30 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_DQ14" +Na 31 "/DDR_Banks/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_DQ15" +Na 32 "/DDR_Banks/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_DQ2" +Na 33 "/DDR_Banks/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_UDM" +Na 34 "/DDR_Banks/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_UDQS" +Na 35 "/DDR_Banks/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/DDR_Banks/M1_WE#" +Na 36 "/DDR_Banks/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/Ethernet_Phy/ETH_1.8V" +Na 37 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/Ethernet_Phy/ETH_A1.8V" +Na 38 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/Ethernet_Phy/ETH_A3.3V" +Na 39 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Ethernet_Phy/ETH_LED0" +Na 40 "/DDR_Banks/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_LED1" +Na 41 "/Ethernet_Phy/ETH_1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_MDIO" +Na 42 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_PLL1.8V" +Na 43 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_RXC" +Na 44 "/Ethernet_Phy/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_RXD3" +Na 45 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_RXER" +Na 46 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_TXD0" +Na 47 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_TXD2" +Na 48 "/Ethernet_Phy/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_TXEN" +Na 49 "/Ethernet_Phy/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/FPGA_Spartan6/ETH_CLK" +Na 50 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/FPGA_Spartan6/ETH_COL" +Na 51 "/Ethernet_Phy/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Spartan6/ETH_CRS" +Na 52 "/Ethernet_Phy/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Spartan6/ETH_INT" +Na 53 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Spartan6/ETH_MDC" +Na 54 "/Ethernet_Phy/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Spartan6/ETH_RESET_N" +Na 55 "/Ethernet_Phy/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/ETH_RXD0" +Na 56 "/Ethernet_Phy/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/ETH_RXD1" +Na 57 "/Ethernet_Phy/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/ETH_RXD2" +Na 58 "/Ethernet_Phy/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/ETH_RXDV" +Na 59 "/Ethernet_Phy/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/ETH_TXC" +Na 60 "/FPGA_Spartan6/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/ETH_TXD1" +Na 61 "/FPGA_Spartan6/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/ETH_TXD3" +Na 62 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/ETH_TXER" +Na 63 "/FPGA_Spartan6/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/M0_A1" +Na 64 "/FPGA_Spartan6/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/M0_A10" +Na 65 "/FPGA_Spartan6/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/M0_A11" +Na 66 "/FPGA_Spartan6/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/M0_A12" +Na 67 "/FPGA_Spartan6/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/M0_A2" +Na 68 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_A3" +Na 69 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_A7" +Na 70 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_A9" +Na 71 "/FPGA_Spartan6/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_BA0" +Na 72 "/FPGA_Spartan6/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_CAS#" +Na 73 "/FPGA_Spartan6/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_DQ0" +Na 74 "/FPGA_Spartan6/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_DQ10" +Na 75 "/FPGA_Spartan6/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_DQ12" +Na 76 "/FPGA_Spartan6/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_DQ14" +Na 77 "/FPGA_Spartan6/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_DQ15" +Na 78 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_DQ3" +Na 79 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_DQ4" +Na 80 "/FPGA_Spartan6/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_DQ8" +Na 81 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_LDM" +Na 82 "/FPGA_Spartan6/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_LDQS" +Na 83 "/FPGA_Spartan6/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_UDQS" +Na 84 "/FPGA_Spartan6/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M1_A0" +Na 85 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M1_A11" +Na 86 "/FPGA_Spartan6/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M1_A12" +Na 87 "/FPGA_Spartan6/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M1_A2" +Na 88 "/FPGA_Spartan6/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M1_A3" +Na 89 "/FPGA_Spartan6/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M1_A4" +Na 90 "/FPGA_Spartan6/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M1_A5" +Na 91 "/FPGA_Spartan6/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M1_A6" +Na 92 "/FPGA_Spartan6/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M1_A7" +Na 93 "/FPGA_Spartan6/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_A8" +Na 94 "/FPGA_Spartan6/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_A9" +Na 95 "/FPGA_Spartan6/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_CAS#" +Na 96 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_CLK" +Na 97 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_CLK#" +Na 98 "/FPGA_Spartan6/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_DQ0" +Na 99 "/FPGA_Spartan6/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_DQ1" +Na 100 "/FPGA_Spartan6/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_DQ10" +Na 101 "/FPGA_Spartan6/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_DQ11" +Na 102 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_DQ13" +Na 103 "/FPGA_Spartan6/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_DQ3" +Na 104 "/FPGA_Spartan6/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ4" +Na 105 "/FPGA_Spartan6/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_DQ5" +Na 106 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_DQ6" +Na 107 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_DQ7" +Na 108 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ8" +Na 109 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_DQ9" +Na 110 "/FPGA_Spartan6/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_LDM" +Na 111 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT @@ -518,131 +518,131 @@ Na 112 "/FPGA_Spartan6/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_RAS#" +Na 113 "/FPGA_Spartan6/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Spartan6/NF_CS1_N" +Na 114 "/FPGA_Spartan6/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/NF_D1" +Na 115 "/FPGA_Spartan6/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/NF_D4" +Na 116 "/FPGA_Spartan6/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Spartan6/NF_D5" +Na 117 "/FPGA_Spartan6/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA_Spartan6/PROG_CCLK" +Na 118 "/FPGA_Spartan6/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/PROG_CSO" +Na 119 "/FPGA_Spartan6/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Spartan6/PROG_MISO0" +Na 120 "/FPGA_Spartan6/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Spartan6/PROG_MISO1" +Na 121 "/FPGA_Spartan6/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Spartan6/PROG_MISO2" +Na 122 "/FPGA_Spartan6/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Spartan6/PROG_MISO3" +Na 123 "/FPGA_Spartan6/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Spartan6/SD_CLK" +Na 124 "/FPGA_Spartan6/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Spartan6/SD_DAT1" +Na 125 "/FPGA_Spartan6/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Spartan6/USBA_OE_N" +Na 126 "/FPGA_Spartan6/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Spartan6/USBA_SPD" +Na 127 "/FPGA_Spartan6/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Spartan6/USBA_VP" +Na 128 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/Non_volatile_memories/NF_ALE" +Na 129 "/FPGA_Spartan6/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/Non_volatile_memories/NF_CLE" +Na 130 "/FPGA_Spartan6/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/Non_volatile_memories/NF_D0" +Na 131 "/FPGA_Spartan6/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/Non_volatile_memories/NF_D2" +Na 132 "/FPGA_Spartan6/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/Non_volatile_memories/NF_D3" +Na 133 "/FPGA_Spartan6/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/Non_volatile_memories/NF_D6" +Na 134 "/Non_volatile_memories/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/Non_volatile_memories/NF_D7" +Na 135 "/Non_volatile_memories/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/Non_volatile_memories/NF_RE_N" +Na 136 "/Non_volatile_memories/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/Non_volatile_memories/NF_RNB" +Na 137 "/Non_volatile_memories/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/Non_volatile_memories/NF_WE_N" +Na 138 "/Non_volatile_memories/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/Non_volatile_memories/SD_CMD" +Na 139 "/Non_volatile_memories/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/Non_volatile_memories/SD_DAT0" +Na 140 "/Non_volatile_memories/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/Non_volatile_memories/SD_DAT2" +Na 141 "/Non_volatile_memories/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/Non_volatile_memories/SD_DAT3" +Na 142 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/USB/USBA_RCV" +Na 143 "/Non_volatile_memories/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/USB/USBA_VM" +Na 144 "/USB/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT @@ -670,47 +670,47 @@ Na 150 "N-000054" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "N-000149" +Na 151 "N-000229" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "N-000317" +Na 152 "N-000316" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "N-000318" +Na 153 "N-000317" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "N-000319" +Na 154 "N-000318" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "N-000320" +Na 155 "N-000319" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "N-000322" +Na 156 "N-000326" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "N-000323" +Na 157 "N-000328" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "N-000324" +Na 158 "N-000329" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "N-000325" +Na 159 "N-000330" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "N-000328" +Na 160 "N-000331" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "N-000331" +Na 161 "N-000333" St ~ $EndEQUIPOT $EQUIPOT @@ -718,49 +718,53 @@ Na 162 "N-000339" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "N-000341" +Na 163 "N-000340" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "N-000342" +Na 164 "N-000341" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "N-000346" +Na 165 "N-000343" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "N-000347" +Na 166 "N-000344" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "N-000348" +Na 167 "N-000345" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "N-000349" +Na 168 "N-000346" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "N-000350" +Na 169 "N-000351" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "N-000352" +Na 170 "N-000355" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "N-000353" +Na 171 "N-000356" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "N-000354" +Na 172 "N-000357" St ~ $EndEQUIPOT $EQUIPOT Na 173 "N-000358" St ~ $EndEQUIPOT +$EQUIPOT +Na 174 "VCCO2" +St ~ +$EndEQUIPOT $NCLASS Name "Default" Desc "This is the default net class." @@ -776,174 +780,175 @@ AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" AddNet "/DDR_Banks/M0_A0" +AddNet "/DDR_Banks/M0_A1" AddNet "/DDR_Banks/M0_A4" AddNet "/DDR_Banks/M0_A5" AddNet "/DDR_Banks/M0_A6" AddNet "/DDR_Banks/M0_A8" -AddNet "/DDR_Banks/M0_BA1" +AddNet "/DDR_Banks/M0_A9" +AddNet "/DDR_Banks/M0_BA0" AddNet "/DDR_Banks/M0_CKE" -AddNet "/DDR_Banks/M0_CLK" -AddNet "/DDR_Banks/M0_CLK#" -AddNet "/DDR_Banks/M0_DQ1" -AddNet "/DDR_Banks/M0_DQ11" -AddNet "/DDR_Banks/M0_DQ13" -AddNet "/DDR_Banks/M0_DQ2" +AddNet "/DDR_Banks/M0_DQ4" AddNet "/DDR_Banks/M0_DQ5" AddNet "/DDR_Banks/M0_DQ6" AddNet "/DDR_Banks/M0_DQ7" -AddNet "/DDR_Banks/M0_DQ9" +AddNet "/DDR_Banks/M0_DQ8" +AddNet "/DDR_Banks/M0_LDM" AddNet "/DDR_Banks/M0_RAS#" -AddNet "/DDR_Banks/M0_UDM" -AddNet "/DDR_Banks/M0_WE#" +AddNet "/DDR_Banks/M0_UDQS" AddNet "/DDR_Banks/M1_A1" -AddNet "/DDR_Banks/M1_A10" +AddNet "/DDR_Banks/M1_A6" +AddNet "/DDR_Banks/M1_A8" +AddNet "/DDR_Banks/M1_A9" AddNet "/DDR_Banks/M1_BA0" -AddNet "/DDR_Banks/M1_BA1" -AddNet "/DDR_Banks/M1_CKE" +AddNet "/DDR_Banks/M1_CLK" +AddNet "/DDR_Banks/M1_DQ0" +AddNet "/DDR_Banks/M1_DQ1" +AddNet "/DDR_Banks/M1_DQ10" AddNet "/DDR_Banks/M1_DQ12" -AddNet "/DDR_Banks/M1_DQ14" -AddNet "/DDR_Banks/M1_DQ15" -AddNet "/DDR_Banks/M1_DQ2" +AddNet "/DDR_Banks/M1_DQ4" +AddNet "/DDR_Banks/M1_DQ5" +AddNet "/DDR_Banks/M1_DQ7" +AddNet "/DDR_Banks/M1_DQ8" +AddNet "/DDR_Banks/M1_DQ9" +AddNet "/DDR_Banks/M1_LDM" +AddNet "/DDR_Banks/M1_RAS#" AddNet "/DDR_Banks/M1_UDM" AddNet "/DDR_Banks/M1_UDQS" -AddNet "/DDR_Banks/M1_WE#" AddNet "/Ethernet_Phy/ETH_1.8V" AddNet "/Ethernet_Phy/ETH_A1.8V" AddNet "/Ethernet_Phy/ETH_A3.3V" +AddNet "/Ethernet_Phy/ETH_CLK" +AddNet "/Ethernet_Phy/ETH_INT" AddNet "/Ethernet_Phy/ETH_LED0" AddNet "/Ethernet_Phy/ETH_LED1" +AddNet "/Ethernet_Phy/ETH_MDC" AddNet "/Ethernet_Phy/ETH_MDIO" AddNet "/Ethernet_Phy/ETH_PLL1.8V" AddNet "/Ethernet_Phy/ETH_RXC" -AddNet "/Ethernet_Phy/ETH_RXD3" -AddNet "/Ethernet_Phy/ETH_RXER" +AddNet "/Ethernet_Phy/ETH_RXD0" +AddNet "/Ethernet_Phy/ETH_RXD1" +AddNet "/Ethernet_Phy/ETH_RXD2" +AddNet "/Ethernet_Phy/ETH_RXDV" +AddNet "/Ethernet_Phy/ETH_TXC" AddNet "/Ethernet_Phy/ETH_TXD0" AddNet "/Ethernet_Phy/ETH_TXD2" -AddNet "/Ethernet_Phy/ETH_TXEN" -AddNet "/FPGA_Spartan6/ETH_CLK" +AddNet "/Ethernet_Phy/ETH_TXER" AddNet "/FPGA_Spartan6/ETH_COL" AddNet "/FPGA_Spartan6/ETH_CRS" -AddNet "/FPGA_Spartan6/ETH_INT" -AddNet "/FPGA_Spartan6/ETH_MDC" AddNet "/FPGA_Spartan6/ETH_RESET_N" -AddNet "/FPGA_Spartan6/ETH_RXD0" -AddNet "/FPGA_Spartan6/ETH_RXD1" -AddNet "/FPGA_Spartan6/ETH_RXD2" -AddNet "/FPGA_Spartan6/ETH_RXDV" -AddNet "/FPGA_Spartan6/ETH_TXC" +AddNet "/FPGA_Spartan6/ETH_RXD3" +AddNet "/FPGA_Spartan6/ETH_RXER" AddNet "/FPGA_Spartan6/ETH_TXD1" AddNet "/FPGA_Spartan6/ETH_TXD3" -AddNet "/FPGA_Spartan6/ETH_TXER" -AddNet "/FPGA_Spartan6/M0_A1" +AddNet "/FPGA_Spartan6/ETH_TXEN" AddNet "/FPGA_Spartan6/M0_A10" AddNet "/FPGA_Spartan6/M0_A11" AddNet "/FPGA_Spartan6/M0_A12" AddNet "/FPGA_Spartan6/M0_A2" AddNet "/FPGA_Spartan6/M0_A3" AddNet "/FPGA_Spartan6/M0_A7" -AddNet "/FPGA_Spartan6/M0_A9" -AddNet "/FPGA_Spartan6/M0_BA0" +AddNet "/FPGA_Spartan6/M0_BA1" AddNet "/FPGA_Spartan6/M0_CAS#" +AddNet "/FPGA_Spartan6/M0_CLK" +AddNet "/FPGA_Spartan6/M0_CLK#" AddNet "/FPGA_Spartan6/M0_DQ0" +AddNet "/FPGA_Spartan6/M0_DQ1" AddNet "/FPGA_Spartan6/M0_DQ10" +AddNet "/FPGA_Spartan6/M0_DQ11" AddNet "/FPGA_Spartan6/M0_DQ12" +AddNet "/FPGA_Spartan6/M0_DQ13" AddNet "/FPGA_Spartan6/M0_DQ14" AddNet "/FPGA_Spartan6/M0_DQ15" +AddNet "/FPGA_Spartan6/M0_DQ2" AddNet "/FPGA_Spartan6/M0_DQ3" -AddNet "/FPGA_Spartan6/M0_DQ4" -AddNet "/FPGA_Spartan6/M0_DQ8" -AddNet "/FPGA_Spartan6/M0_LDM" +AddNet "/FPGA_Spartan6/M0_DQ9" AddNet "/FPGA_Spartan6/M0_LDQS" -AddNet "/FPGA_Spartan6/M0_UDQS" +AddNet "/FPGA_Spartan6/M0_UDM" +AddNet "/FPGA_Spartan6/M0_WE#" AddNet "/FPGA_Spartan6/M1_A0" +AddNet "/FPGA_Spartan6/M1_A10" AddNet "/FPGA_Spartan6/M1_A11" AddNet "/FPGA_Spartan6/M1_A12" AddNet "/FPGA_Spartan6/M1_A2" AddNet "/FPGA_Spartan6/M1_A3" AddNet "/FPGA_Spartan6/M1_A4" AddNet "/FPGA_Spartan6/M1_A5" -AddNet "/FPGA_Spartan6/M1_A6" AddNet "/FPGA_Spartan6/M1_A7" -AddNet "/FPGA_Spartan6/M1_A8" -AddNet "/FPGA_Spartan6/M1_A9" +AddNet "/FPGA_Spartan6/M1_BA1" AddNet "/FPGA_Spartan6/M1_CAS#" -AddNet "/FPGA_Spartan6/M1_CLK" +AddNet "/FPGA_Spartan6/M1_CKE" AddNet "/FPGA_Spartan6/M1_CLK#" -AddNet "/FPGA_Spartan6/M1_DQ0" -AddNet "/FPGA_Spartan6/M1_DQ1" -AddNet "/FPGA_Spartan6/M1_DQ10" AddNet "/FPGA_Spartan6/M1_DQ11" AddNet "/FPGA_Spartan6/M1_DQ13" +AddNet "/FPGA_Spartan6/M1_DQ14" +AddNet "/FPGA_Spartan6/M1_DQ15" +AddNet "/FPGA_Spartan6/M1_DQ2" AddNet "/FPGA_Spartan6/M1_DQ3" -AddNet "/FPGA_Spartan6/M1_DQ4" -AddNet "/FPGA_Spartan6/M1_DQ5" AddNet "/FPGA_Spartan6/M1_DQ6" -AddNet "/FPGA_Spartan6/M1_DQ7" -AddNet "/FPGA_Spartan6/M1_DQ8" -AddNet "/FPGA_Spartan6/M1_DQ9" -AddNet "/FPGA_Spartan6/M1_LDM" AddNet "/FPGA_Spartan6/M1_LDQS" -AddNet "/FPGA_Spartan6/M1_RAS#" +AddNet "/FPGA_Spartan6/M1_WE#" +AddNet "/FPGA_Spartan6/NF_ALE" +AddNet "/FPGA_Spartan6/NF_CLE" AddNet "/FPGA_Spartan6/NF_CS1_N" +AddNet "/FPGA_Spartan6/NF_D0" AddNet "/FPGA_Spartan6/NF_D1" +AddNet "/FPGA_Spartan6/NF_D2" +AddNet "/FPGA_Spartan6/NF_D3" AddNet "/FPGA_Spartan6/NF_D4" -AddNet "/FPGA_Spartan6/NF_D5" +AddNet "/FPGA_Spartan6/NF_WE_N" AddNet "/FPGA_Spartan6/PROG_CCLK" AddNet "/FPGA_Spartan6/PROG_CSO" AddNet "/FPGA_Spartan6/PROG_MISO0" AddNet "/FPGA_Spartan6/PROG_MISO1" AddNet "/FPGA_Spartan6/PROG_MISO2" AddNet "/FPGA_Spartan6/PROG_MISO3" -AddNet "/FPGA_Spartan6/SD_CLK" AddNet "/FPGA_Spartan6/SD_DAT1" -AddNet "/FPGA_Spartan6/USBA_OE_N" +AddNet "/FPGA_Spartan6/USBA_RCV" AddNet "/FPGA_Spartan6/USBA_SPD" +AddNet "/FPGA_Spartan6/USBA_VM" AddNet "/FPGA_Spartan6/USBA_VP" -AddNet "/Non_volatile_memories/NF_ALE" -AddNet "/Non_volatile_memories/NF_CLE" -AddNet "/Non_volatile_memories/NF_D0" -AddNet "/Non_volatile_memories/NF_D2" -AddNet "/Non_volatile_memories/NF_D3" +AddNet "/Non_volatile_memories/NF_D5" AddNet "/Non_volatile_memories/NF_D6" AddNet "/Non_volatile_memories/NF_D7" AddNet "/Non_volatile_memories/NF_RE_N" AddNet "/Non_volatile_memories/NF_RNB" -AddNet "/Non_volatile_memories/NF_WE_N" +AddNet "/Non_volatile_memories/SD_CLK" AddNet "/Non_volatile_memories/SD_CMD" AddNet "/Non_volatile_memories/SD_DAT0" AddNet "/Non_volatile_memories/SD_DAT2" AddNet "/Non_volatile_memories/SD_DAT3" -AddNet "/USB/USBA_RCV" -AddNet "/USB/USBA_VM" +AddNet "/USB/USBA_OE_N" AddNet "3.3V" AddNet "GND" AddNet "N-000050" AddNet "N-000051" AddNet "N-000052" AddNet "N-000054" -AddNet "N-000149" +AddNet "N-000229" +AddNet "N-000316" AddNet "N-000317" AddNet "N-000318" AddNet "N-000319" -AddNet "N-000320" -AddNet "N-000322" -AddNet "N-000323" -AddNet "N-000324" -AddNet "N-000325" +AddNet "N-000326" AddNet "N-000328" +AddNet "N-000329" +AddNet "N-000330" AddNet "N-000331" +AddNet "N-000333" AddNet "N-000339" +AddNet "N-000340" AddNet "N-000341" -AddNet "N-000342" +AddNet "N-000343" +AddNet "N-000344" +AddNet "N-000345" AddNet "N-000346" -AddNet "N-000347" -AddNet "N-000348" -AddNet "N-000349" -AddNet "N-000350" -AddNet "N-000352" -AddNet "N-000353" -AddNet "N-000354" +AddNet "N-000351" +AddNet "N-000355" +AddNet "N-000356" +AddNet "N-000357" AddNet "N-000358" +AddNet "VCCO2" $EndNCLASS $MODULE 1206 Po 63780 39173 1800 15 4C5FF890 4C61D1D4 ~~ @@ -1015,70 +1020,70 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_INT" +Ne 45 "/Ethernet_Phy/ETH_INT" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_MDIO" +Ne 49 "/Ethernet_Phy/ETH_MDIO" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RXD1" +Ne 53 "/Ethernet_Phy/ETH_RXD1" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_RXDV" +Ne 55 "/Ethernet_Phy/ETH_RXDV" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_TXER" +Ne 59 "/Ethernet_Phy/ETH_TXER" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_TXD2" +Ne 58 "/Ethernet_Phy/ETH_TXD2" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/ETH_COL" +Ne 60 "/FPGA_Spartan6/ETH_COL" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/Non_volatile_memories/NF_D7" +Ne 136 "/Non_volatile_memories/NF_D7" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/Non_volatile_memories/NF_D3" +Ne 120 "/FPGA_Spartan6/NF_D3" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_D1" +Ne 118 "/FPGA_Spartan6/NF_D1" Po 590 -4133 $EndPAD $PAD @@ -1092,28 +1097,28 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/Non_volatile_memories/NF_ALE" +Ne 114 "/FPGA_Spartan6/NF_ALE" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/Non_volatile_memories/NF_RNB" +Ne 138 "/Non_volatile_memories/NF_RNB" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/Non_volatile_memories/SD_DAT2" +Ne 142 "/Non_volatile_memories/SD_DAT2" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/Non_volatile_memories/SD_DAT0" +Ne 141 "/Non_volatile_memories/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -1183,7 +1188,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RXD2" +Ne 54 "/Ethernet_Phy/ETH_RXD2" Po -2165 -3739 $EndPAD $PAD @@ -1197,7 +1202,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_RXER" +Ne 64 "/FPGA_Spartan6/ETH_RXER" Po -1377 -3739 $EndPAD $PAD @@ -1211,7 +1216,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_CRS" +Ne 61 "/FPGA_Spartan6/ETH_CRS" Po -590 -3739 $EndPAD $PAD @@ -1225,7 +1230,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_D4" +Ne 121 "/FPGA_Spartan6/NF_D4" Po 196 -3739 $EndPAD $PAD @@ -1253,7 +1258,7 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/Non_volatile_memories/NF_RE_N" +Ne 137 "/Non_volatile_memories/NF_RE_N" Po 1771 -3739 $EndPAD $PAD @@ -1267,7 +1272,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/SD_DAT1" +Ne 129 "/FPGA_Spartan6/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1302,7 +1307,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A11" +Ne 69 "/FPGA_Spartan6/M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1330,42 +1335,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_MDC" +Ne 48 "/Ethernet_Phy/ETH_MDC" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_RXD3" +Ne 63 "/FPGA_Spartan6/ETH_RXD3" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_RXD0" +Ne 52 "/Ethernet_Phy/ETH_RXD0" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_TXD0" +Ne 57 "/Ethernet_Phy/ETH_TXD0" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_TXD1" +Ne 65 "/FPGA_Spartan6/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Spartan6/ETH_CLK" +Ne 44 "/Ethernet_Phy/ETH_CLK" Po -590 -3346 $EndPAD $PAD @@ -1379,14 +1384,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_D5" +Ne 134 "/Non_volatile_memories/NF_D5" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/Non_volatile_memories/NF_D2" +Ne 119 "/FPGA_Spartan6/NF_D2" Po 590 -3346 $EndPAD $PAD @@ -1400,21 +1405,21 @@ $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/Non_volatile_memories/NF_WE_N" +Ne 122 "/FPGA_Spartan6/NF_WE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/NF_CS1_N" +Ne 116 "/FPGA_Spartan6/NF_CS1_N" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/Non_volatile_memories/SD_DAT3" +Ne 143 "/Non_volatile_memories/SD_DAT3" Po 2165 -3346 $EndPAD $PAD @@ -1435,7 +1440,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A8" +Ne 24 "/DDR_Banks/M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1449,21 +1454,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A9" +Ne 25 "/DDR_Banks/M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A12" +Ne 70 "/FPGA_Spartan6/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_CKE" +Ne 13 "/DDR_Banks/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1491,42 +1496,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_RESET_N" +Ne 62 "/FPGA_Spartan6/ETH_RESET_N" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_TXD3" +Ne 66 "/FPGA_Spartan6/ETH_TXD3" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_TXC" +Ne 56 "/Ethernet_Phy/ETH_TXC" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_TXEN" +Ne 67 "/FPGA_Spartan6/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_RXC" +Ne 51 "/Ethernet_Phy/ETH_RXC" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/Non_volatile_memories/NF_D6" +Ne 135 "/Non_volatile_memories/NF_D6" Po -196 -2952 $EndPAD $PAD @@ -1547,14 +1552,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/Non_volatile_memories/NF_D0" +Ne 117 "/FPGA_Spartan6/NF_D0" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/Non_volatile_memories/NF_CLE" +Ne 115 "/FPGA_Spartan6/NF_CLE" Po 1377 -2952 $EndPAD $PAD @@ -1568,7 +1573,7 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/Non_volatile_memories/SD_CMD" +Ne 140 "/Non_volatile_memories/SD_CMD" Po 2165 -2952 $EndPAD $PAD @@ -1596,21 +1601,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_CKE" +Ne 103 "/FPGA_Spartan6/M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M1_A12" +Ne 95 "/FPGA_Spartan6/M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A9" +Ne 11 "/DDR_Banks/M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -1624,7 +1629,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A8" +Ne 10 "/DDR_Banks/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1715,7 +1720,7 @@ $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/SD_CLK" +Ne 139 "/Non_volatile_memories/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -1743,7 +1748,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_A7" +Ne 100 "/FPGA_Spartan6/M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -1757,7 +1762,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M1_A2" +Ne 96 "/FPGA_Spartan6/M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -1771,14 +1776,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M0_WE#" +Ne 91 "/FPGA_Spartan6/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A4" +Ne 7 "/DDR_Banks/M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -1890,35 +1895,35 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M1_A11" +Ne 94 "/FPGA_Spartan6/M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A4" +Ne 98 "/FPGA_Spartan6/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M1_A0" +Ne 92 "/FPGA_Spartan6/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A1" +Ne 22 "/DDR_Banks/M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_BA1" +Ne 74 "/FPGA_Spartan6/M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -1932,14 +1937,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_BA0" +Ne 12 "/DDR_Banks/M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A10" +Ne 68 "/FPGA_Spartan6/M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -2044,14 +2049,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_A10" +Ne 93 "/FPGA_Spartan6/M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A3" +Ne 97 "/FPGA_Spartan6/M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2072,7 +2077,7 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A1" +Ne 6 "/DDR_Banks/M0_A1" Po -4133 -1377 $EndPAD $PAD @@ -2086,28 +2091,28 @@ $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_CLK#" +Ne 77 "/FPGA_Spartan6/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_CLK" +Ne 76 "/FPGA_Spartan6/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A2" +Ne 71 "/FPGA_Spartan6/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A7" +Ne 73 "/FPGA_Spartan6/M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -2198,35 +2203,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_WE#" +Ne 113 "/FPGA_Spartan6/M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_CLK" +Ne 27 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_RAS#" +Ne 38 "/DDR_Banks/M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_CAS#" +Ne 102 "/FPGA_Spartan6/M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_DQ5" +Ne 15 "/DDR_Banks/M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -2240,14 +2245,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ4" +Ne 14 "/DDR_Banks/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A6" +Ne 9 "/DDR_Banks/M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2338,7 +2343,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_BA0" +Ne 26 "/DDR_Banks/M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2352,14 +2357,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_CLK#" +Ne 104 "/FPGA_Spartan6/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ4" +Ne 32 "/DDR_Banks/M1_DQ4" Po 3346 -983 $EndPAD $PAD @@ -2373,49 +2378,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ5" +Ne 33 "/DDR_Banks/M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_DQ7" +Ne 17 "/DDR_Banks/M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_DQ6" +Ne 16 "/DDR_Banks/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A5" +Ne 8 "/DDR_Banks/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_CAS#" +Ne 75 "/FPGA_Spartan6/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_RAS#" +Ne 20 "/DDR_Banks/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A3" +Ne 72 "/FPGA_Spartan6/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2492,7 +2497,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_BA1" +Ne 101 "/FPGA_Spartan6/M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2506,28 +2511,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A6" +Ne 23 "/DDR_Banks/M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A5" +Ne 99 "/FPGA_Spartan6/M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ6" +Ne 111 "/FPGA_Spartan6/M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ7" +Ne 34 "/DDR_Banks/M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2548,14 +2553,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_LDQS" +Ne 89 "/FPGA_Spartan6/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_LDM" +Ne 19 "/DDR_Banks/M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -2660,7 +2665,7 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_LDM" +Ne 37 "/DDR_Banks/M1_LDM" Po 2952 -196 $EndPAD $PAD @@ -2688,21 +2693,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ3" +Ne 87 "/FPGA_Spartan6/M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ2" +Ne 86 "/FPGA_Spartan6/M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M0_UDM" +Ne 90 "/FPGA_Spartan6/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2807,7 +2812,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/USB/USBA_VM" +Ne 132 "/FPGA_Spartan6/USBA_VM" Po 2558 196 $EndPAD $PAD @@ -2821,28 +2826,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_UDM" +Ne 39 "/DDR_Banks/M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_DQ2" +Ne 109 "/FPGA_Spartan6/M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ3" +Ne 110 "/FPGA_Spartan6/M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ1" +Ne 79 "/FPGA_Spartan6/M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -2856,7 +2861,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_DQ0" +Ne 78 "/FPGA_Spartan6/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -2947,7 +2952,7 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/USB/USBA_RCV" +Ne 130 "/FPGA_Spartan6/USBA_RCV" Po 1771 590 $EndPAD $PAD @@ -2975,7 +2980,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_DQ0" +Ne 28 "/DDR_Banks/M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -2989,21 +2994,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_DQ1" +Ne 29 "/DDR_Banks/M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_DQ9" +Ne 88 "/FPGA_Spartan6/M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ8" +Ne 18 "/DDR_Banks/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3108,14 +3113,14 @@ $PAD Sh "P17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/USBA_VP" +Ne 133 "/FPGA_Spartan6/USBA_VP" Po 2165 983 $EndPAD $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/USBA_OE_N" +Ne 144 "/USB/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -3136,21 +3141,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ8" +Ne 35 "/DDR_Banks/M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ9" +Ne 36 "/DDR_Banks/M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ11" +Ne 81 "/FPGA_Spartan6/M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3164,7 +3169,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_DQ10" +Ne 80 "/FPGA_Spartan6/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3276,14 +3281,14 @@ $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/USBA_SPD" +Ne 131 "/FPGA_Spartan6/USBA_SPD" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ10" +Ne 30 "/DDR_Banks/M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3297,7 +3302,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ11" +Ne 105 "/FPGA_Spartan6/M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3311,7 +3316,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_UDQS" +Ne 21 "/DDR_Banks/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3332,7 +3337,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/PROG_CSO" +Ne 124 "/FPGA_Spartan6/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -3360,7 +3365,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po -983 1771 $EndPAD $PAD @@ -3388,7 +3393,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po 590 1771 $EndPAD $PAD @@ -3444,7 +3449,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_UDQS" +Ne 40 "/DDR_Banks/M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3458,7 +3463,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ13" +Ne 83 "/FPGA_Spartan6/M0_DQ13" Po -4133 2165 $EndPAD $PAD @@ -3472,7 +3477,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ12" +Ne 82 "/FPGA_Spartan6/M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3542,14 +3547,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/PROG_MISO3" +Ne 128 "/FPGA_Spartan6/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/PROG_MISO2" +Ne 127 "/FPGA_Spartan6/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -3591,7 +3596,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ12" +Ne 31 "/DDR_Banks/M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -3605,21 +3610,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ13" +Ne 106 "/FPGA_Spartan6/M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ15" +Ne 85 "/FPGA_Spartan6/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ14" +Ne 84 "/FPGA_Spartan6/M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3661,7 +3666,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po -1377 2558 $EndPAD $PAD @@ -3689,7 +3694,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po 196 2558 $EndPAD $PAD @@ -3717,7 +3722,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po 1771 2558 $EndPAD $PAD @@ -3752,14 +3757,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ14" +Ne 107 "/FPGA_Spartan6/M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_DQ15" +Ne 108 "/FPGA_Spartan6/M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -3794,7 +3799,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po -2558 2952 $EndPAD $PAD @@ -4088,7 +4093,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po -3346 3739 $EndPAD $PAD @@ -4116,7 +4121,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po -1771 3739 $EndPAD $PAD @@ -4144,7 +4149,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po -196 3739 $EndPAD $PAD @@ -4172,7 +4177,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po 1377 3739 $EndPAD $PAD @@ -4200,21 +4205,21 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000149" +Ne 151 "N-000229" Po 2952 3739 $EndPAD $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/PROG_MISO1" +Ne 126 "/FPGA_Spartan6/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/PROG_CCLK" +Ne 123 "/FPGA_Spartan6/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -4361,7 +4366,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/PROG_MISO0" +Ne 125 "/FPGA_Spartan6/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -4404,21 +4409,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_RXER" +Ne 64 "/FPGA_Spartan6/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_RXC" +Ne 51 "/Ethernet_Phy/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_RXDV" +Ne 55 "/Ethernet_Phy/ETH_RXDV" Po -1613 491 $EndPAD $PAD @@ -4439,63 +4444,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_RXD0" +Ne 52 "/Ethernet_Phy/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RXD1" +Ne 53 "/Ethernet_Phy/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RXD2" +Ne 54 "/Ethernet_Phy/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_RXD3" +Ne 63 "/FPGA_Spartan6/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_MDC" +Ne 48 "/Ethernet_Phy/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_MDIO" +Ne 49 "/Ethernet_Phy/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_RESET_N" +Ne 62 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 50 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Spartan6/ETH_CLK" +Ne 44 "/Ethernet_Phy/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -4530,14 +4535,14 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 152 "N-000317" +Ne 153 "N-000317" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 159 "N-000325" +Ne 159 "N-000330" Po 491 -1613 $EndPAD $PAD @@ -4551,35 +4556,35 @@ $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_A3.3V" +Ne 43 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 157 "N-000323" +Ne 157 "N-000328" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_INT" +Ne 45 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_LED0" +Ne 46 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_LED1" +Ne 47 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4607,21 +4612,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_A1.8V" +Ne 42 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 158 "N-000324" +Ne 158 "N-000329" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 153 "N-000318" +Ne 152 "N-000316" Po 1613 -491 $EndPAD $PAD @@ -4649,70 +4654,70 @@ $PAD Sh "13" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_1.8V" +Ne 41 "/Ethernet_Phy/ETH_1.8V" Po -1082 1613 $EndPAD $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_TXER" +Ne 59 "/Ethernet_Phy/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_TXC" +Ne 56 "/Ethernet_Phy/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_TXEN" +Ne 67 "/FPGA_Spartan6/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_TXD0" +Ne 57 "/Ethernet_Phy/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_TXD1" +Ne 65 "/FPGA_Spartan6/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_TXD2" +Ne 58 "/Ethernet_Phy/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_TXD3" +Ne 66 "/FPGA_Spartan6/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/ETH_COL" +Ne 60 "/FPGA_Spartan6/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_CRS" +Ne 61 "/FPGA_Spartan6/ETH_CRS" Po 688 1613 $EndPAD $PAD @@ -4990,28 +4995,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/Non_volatile_memories/NF_RNB" +Ne 138 "/Non_volatile_memories/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/Non_volatile_memories/NF_RNB" +Ne 138 "/Non_volatile_memories/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/Non_volatile_memories/NF_RE_N" +Ne 137 "/Non_volatile_memories/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/NF_CS1_N" +Ne 116 "/FPGA_Spartan6/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -5060,21 +5065,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/Non_volatile_memories/NF_CLE" +Ne 115 "/FPGA_Spartan6/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/Non_volatile_memories/NF_ALE" +Ne 114 "/FPGA_Spartan6/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/Non_volatile_memories/NF_WE_N" +Ne 122 "/FPGA_Spartan6/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -5151,28 +5156,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/Non_volatile_memories/NF_D0" +Ne 117 "/FPGA_Spartan6/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_D1" +Ne 118 "/FPGA_Spartan6/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/Non_volatile_memories/NF_D2" +Ne 119 "/FPGA_Spartan6/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/Non_volatile_memories/NF_D3" +Ne 120 "/FPGA_Spartan6/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -5235,28 +5240,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_D4" +Ne 121 "/FPGA_Spartan6/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_D5" +Ne 134 "/Non_volatile_memories/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/Non_volatile_memories/NF_D6" +Ne 135 "/Non_volatile_memories/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/Non_volatile_memories/NF_D7" +Ne 136 "/Non_volatile_memories/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -5309,21 +5314,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 141 "/Non_volatile_memories/SD_DAT2" +Ne 142 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 142 "/Non_volatile_memories/SD_DAT3" +Ne 143 "/Non_volatile_memories/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 139 "/Non_volatile_memories/SD_CMD" +Ne 140 "/Non_volatile_memories/SD_CMD" Po -433 0 $EndPAD $PAD @@ -5337,7 +5342,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 124 "/FPGA_Spartan6/SD_CLK" +Ne 139 "/Non_volatile_memories/SD_CLK" Po 433 0 $EndPAD $PAD @@ -5351,14 +5356,14 @@ $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 140 "/Non_volatile_memories/SD_DAT0" +Ne 141 "/Non_volatile_memories/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 125 "/FPGA_Spartan6/SD_DAT1" +Ne 129 "/FPGA_Spartan6/SD_DAT1" Po 1732 0 $EndPAD $PAD @@ -5406,35 +5411,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 156 "N-000322" +Ne 154 "N-000318" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 156 "N-000322" +Ne 154 "N-000318" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 156 "N-000322" +Ne 154 "N-000318" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 156 "N-000322" +Ne 154 "N-000318" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 152 "N-000317" +Ne 153 "N-000317" Po -1750 -2500 $EndPAD $PAD @@ -5455,14 +5460,14 @@ $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 153 "N-000318" +Ne 152 "N-000316" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 159 "N-000325" +Ne 159 "N-000330" Po -1250 -3500 $EndPAD $PAD @@ -5483,7 +5488,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 158 "N-000324" +Ne 158 "N-000329" Po 1750 -3500 $EndPAD $PAD @@ -5497,7 +5502,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 154 "N-000319" +Ne 155 "N-000319" Po -1150 -5400 $EndPAD $PAD @@ -5511,7 +5516,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 161 "N-000331" +Ne 161 "N-000333" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -5547,28 +5552,28 @@ $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 127 "/FPGA_Spartan6/USBA_SPD" +Ne 131 "/FPGA_Spartan6/USBA_SPD" Po -511 -1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/USB/USBA_RCV" +Ne 130 "/FPGA_Spartan6/USBA_RCV" Po -255 -1112 $EndPAD $PAD Sh "4" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 128 "/FPGA_Spartan6/USBA_VP" +Ne 133 "/FPGA_Spartan6/USBA_VP" Po 0 -1112 $EndPAD $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/USB/USBA_VM" +Ne 132 "/FPGA_Spartan6/USBA_VM" Po 255 -1112 $EndPAD $PAD @@ -5596,21 +5601,21 @@ $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 126 "/FPGA_Spartan6/USBA_OE_N" +Ne 144 "/USB/USBA_OE_N" Po 511 1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 170 "N-000352" +Ne 163 "N-000340" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 171 "N-000353" +Ne 172 "N-000357" Po 0 1112 $EndPAD $PAD @@ -5660,7 +5665,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_DQ0" +Ne 28 "/DDR_Banks/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -5674,14 +5679,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_DQ1" +Ne 29 "/DDR_Banks/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_DQ2" +Ne 109 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD @@ -5695,14 +5700,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ3" +Ne 110 "/FPGA_Spartan6/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ4" +Ne 32 "/DDR_Banks/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -5716,14 +5721,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ5" +Ne 33 "/DDR_Banks/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ6" +Ne 111 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -5737,7 +5742,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ7" +Ne 34 "/DDR_Banks/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5786,28 +5791,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_LDM" +Ne 37 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_WE#" +Ne 113 "/FPGA_Spartan6/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_CAS#" +Ne 102 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_RAS#" +Ne 38 "/DDR_Banks/M1_RAS#" Po 1535 2176 $EndPAD $PAD @@ -5828,49 +5833,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_BA0" +Ne 26 "/DDR_Banks/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_BA1" +Ne 101 "/FPGA_Spartan6/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_A10" +Ne 93 "/FPGA_Spartan6/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M1_A0" +Ne 92 "/FPGA_Spartan6/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A1" +Ne 22 "/DDR_Banks/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M1_A2" +Ne 96 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A3" +Ne 97 "/FPGA_Spartan6/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -5891,56 +5896,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A4" +Ne 98 "/FPGA_Spartan6/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A5" +Ne 99 "/FPGA_Spartan6/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A6" +Ne 23 "/DDR_Banks/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_A7" +Ne 100 "/FPGA_Spartan6/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A8" +Ne 24 "/DDR_Banks/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A9" +Ne 25 "/DDR_Banks/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M1_A11" +Ne 94 "/FPGA_Spartan6/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M1_A12" +Ne 95 "/FPGA_Spartan6/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -5954,28 +5959,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_CLK#" +Ne 104 "/FPGA_Spartan6/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_CKE" +Ne 103 "/FPGA_Spartan6/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_CLK" +Ne 27 "/DDR_Banks/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_UDM" +Ne 39 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD @@ -6003,7 +6008,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_UDQS" +Ne 40 "/DDR_Banks/M1_UDQS" Po -255 -2176 $EndPAD $PAD @@ -6024,7 +6029,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ8" +Ne 35 "/DDR_Banks/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6038,14 +6043,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ9" +Ne 36 "/DDR_Banks/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ10" +Ne 30 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -6059,14 +6064,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ11" +Ne 105 "/FPGA_Spartan6/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ12" +Ne 31 "/DDR_Banks/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6080,14 +6085,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ13" +Ne 106 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ14" +Ne 107 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -6101,7 +6106,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_DQ15" +Ne 108 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -6137,7 +6142,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_DQ0" +Ne 78 "/FPGA_Spartan6/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -6151,14 +6156,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ1" +Ne 79 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ2" +Ne 86 "/FPGA_Spartan6/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -6172,14 +6177,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ3" +Ne 87 "/FPGA_Spartan6/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ4" +Ne 14 "/DDR_Banks/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -6193,14 +6198,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_DQ5" +Ne 15 "/DDR_Banks/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_DQ6" +Ne 16 "/DDR_Banks/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -6214,7 +6219,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_DQ7" +Ne 17 "/DDR_Banks/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -6235,7 +6240,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_LDQS" +Ne 89 "/FPGA_Spartan6/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -6263,28 +6268,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_LDM" +Ne 19 "/DDR_Banks/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M0_WE#" +Ne 91 "/FPGA_Spartan6/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_CAS#" +Ne 75 "/FPGA_Spartan6/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_RAS#" +Ne 20 "/DDR_Banks/M0_RAS#" Po 1535 2176 $EndPAD $PAD @@ -6305,21 +6310,21 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_BA0" +Ne 12 "/DDR_Banks/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_BA1" +Ne 74 "/FPGA_Spartan6/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A10" +Ne 68 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD @@ -6333,21 +6338,21 @@ $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A1" +Ne 6 "/DDR_Banks/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A2" +Ne 71 "/FPGA_Spartan6/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A3" +Ne 72 "/FPGA_Spartan6/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -6368,56 +6373,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A4" +Ne 7 "/DDR_Banks/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A5" +Ne 8 "/DDR_Banks/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A6" +Ne 9 "/DDR_Banks/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A7" +Ne 73 "/FPGA_Spartan6/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A8" +Ne 10 "/DDR_Banks/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A9" +Ne 11 "/DDR_Banks/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A11" +Ne 69 "/FPGA_Spartan6/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A12" +Ne 70 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6431,28 +6436,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_CLK#" +Ne 77 "/FPGA_Spartan6/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_CKE" +Ne 13 "/DDR_Banks/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_CLK" +Ne 76 "/FPGA_Spartan6/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M0_UDM" +Ne 90 "/FPGA_Spartan6/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -6480,7 +6485,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_UDQS" +Ne 21 "/DDR_Banks/M0_UDQS" Po -255 -2176 $EndPAD $PAD @@ -6501,7 +6506,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ8" +Ne 18 "/DDR_Banks/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6515,14 +6520,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_DQ9" +Ne 88 "/FPGA_Spartan6/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_DQ10" +Ne 80 "/FPGA_Spartan6/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -6536,14 +6541,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ11" +Ne 81 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ12" +Ne 82 "/FPGA_Spartan6/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6557,14 +6562,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ13" +Ne 83 "/FPGA_Spartan6/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ14" +Ne 84 "/FPGA_Spartan6/M0_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -6578,7 +6583,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ15" +Ne 85 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -6606,7 +6611,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 172 "N-000354" +Ne 173 "N-000358" Po -176 0 $EndPAD $PAD @@ -6634,7 +6639,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "N-000322" +Ne 154 "N-000318" Po -176 0 $EndPAD $PAD @@ -6662,14 +6667,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 161 "N-000331" +Ne 161 "N-000333" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_LED1" +Ne 47 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6690,14 +6695,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 154 "N-000319" +Ne 155 "N-000319" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_LED0" +Ne 46 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6725,7 +6730,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "N-000324" +Ne 158 "N-000329" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6753,7 +6758,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 153 "N-000318" +Ne 152 "N-000316" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6781,7 +6786,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 159 "N-000325" +Ne 159 "N-000330" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6809,7 +6814,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 152 "N-000317" +Ne 153 "N-000317" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6830,7 +6835,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 157 "N-000323" +Ne 157 "N-000328" Po -176 0 $EndPAD $PAD @@ -6858,7 +6863,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_MDIO" +Ne 49 "/Ethernet_Phy/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -6886,7 +6891,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 172 "N-000354" +Ne 173 "N-000358" Po -176 0 $EndPAD $PAD @@ -6914,7 +6919,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "N-000322" +Ne 154 "N-000318" Po -176 0 $EndPAD $PAD @@ -6998,14 +7003,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 50 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "N-000328" +Ne 160 "N-000331" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7026,7 +7031,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/Ethernet_Phy/ETH_A3.3V" +Ne 43 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD @@ -7054,14 +7059,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_A1.8V" +Ne 42 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "N-000328" +Ne 160 "N-000331" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7110,14 +7115,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 155 "N-000320" +Ne 156 "N-000326" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 160 "N-000328" +Ne 160 "N-000331" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7166,7 +7171,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_1.8V" +Ne 41 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD @@ -7194,7 +7199,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 170 "N-000352" +Ne 163 "N-000340" Po -294 0 $EndPAD $PAD @@ -7222,7 +7227,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 171 "N-000353" +Ne 172 "N-000357" Po -294 0 $EndPAD $PAD @@ -7250,14 +7255,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_A1.8V" +Ne 42 "/Ethernet_Phy/ETH_A1.8V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 50 "/Ethernet_Phy/ETH_PLL1.8V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7285,7 +7290,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_A3.3V" +Ne 43 "/Ethernet_Phy/ETH_A3.3V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7306,14 +7311,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 155 "N-000320" +Ne 156 "N-000326" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_A1.8V" +Ne 42 "/Ethernet_Phy/ETH_A1.8V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7334,7 +7339,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 164 "N-000342" +Ne 166 "N-000344" Po -294 0 $EndPAD $PAD @@ -7362,7 +7367,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 164 "N-000342" +Ne 166 "N-000344" Po -294 0 $EndPAD $PAD @@ -7390,7 +7395,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 164 "N-000342" +Ne 166 "N-000344" Po -294 0 $EndPAD $PAD @@ -7418,7 +7423,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_A3.3V" +Ne 43 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD @@ -7474,7 +7479,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 163 "N-000341" +Ne 165 "N-000343" Po -570 0 $EndPAD $PAD @@ -7507,56 +7512,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 162 "N-000339" +Ne 164 "N-000341" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 170 "N-000352" +Ne 163 "N-000340" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 171 "N-000353" +Ne 172 "N-000357" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 171 "N-000353" +Ne 172 "N-000357" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 172 "N-000354" +Ne 173 "N-000358" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 172 "N-000354" +Ne 173 "N-000358" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 172 "N-000354" +Ne 173 "N-000358" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 172 "N-000354" +Ne 173 "N-000358" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -7757,309 +7762,309 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 45500 37000 0 15 4C5FF890 4C61CEB9 ~~ +Po 50591 37598 1800 0 4C5FF890 4C61CEB9 ~~ Li 0402 Sc 4C61CEB9 AR /4C421DD3/4C61CEB9 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C22" -T1 0 150 200 200 0 40 N I 25 N"100nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C22" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46000 35000 0 15 4C5FF890 4C61CEF7 ~~ +Po 50591 38189 1800 0 4C5FF890 4C61CEF7 ~~ Li 0402 Sc 4C61CEF7 AR /4C421DD3/4C61CEF7 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C23" -T1 0 150 200 200 0 40 N I 25 N"10nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C23" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46000 30000 0 15 4C5FF890 4C61CF16 ~~ +Po 50591 29921 1800 0 4C5FF890 4C61CF16 ~~ Li 0402 Sc 4C61CF16 AR /4C421DD3/4C61CF16 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C25" -T1 0 150 200 200 0 40 N I 25 N"10nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C25" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46000 32000 0 15 4C5FF890 4C61CF17 ~~ +Po 47441 37008 0 0 4C5FF890 4C61CF17 ~~ Li 0402 Sc 4C61CF17 AR /4C421DD3/4C61CF17 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C24" -T1 0 150 200 200 0 40 N I 25 N"10nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 0 40 M V 20 N"C24" +T1 0 -150 200 200 0 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46000 33000 0 15 4C5FF890 4C61CF27 ~~ +Po 47441 35433 0 0 4C5FF890 4C61CF27 ~~ Li 0402 Sc 4C61CF27 AR /4C421DD3/4C61CF27 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C26" -T1 0 150 200 200 0 40 N I 25 N"10nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 0 40 M V 20 N"C26" +T1 0 -150 200 200 0 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67000 36500 0 15 4C5FF890 4C61CFA1 ~~ +Po 65354 38189 1800 0 4C5FF890 4C61CFA1 ~~ Li 0402 Sc 4C61CFA1 AR /4C421DD3/4C61CFA1 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C32" -T1 0 150 200 200 0 40 N I 25 N"10nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C32" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67500 34000 0 15 4C5FF890 4C61CFA2 ~~ +Po 65354 33858 1800 0 4C5FF890 4C61CFA2 ~~ Li 0402 Sc 4C61CFA2 AR /4C421DD3/4C61CFA2 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C30" -T1 0 150 200 200 0 40 N I 25 N"10nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C30" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67500 35000 0 15 4C5FF890 4C61CFA3 ~~ +Po 65354 37598 1800 0 4C5FF890 4C61CFA3 ~~ Li 0402 Sc 4C61CFA3 AR /4C421DD3/4C61CFA3 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C31" -T1 0 150 200 200 0 40 N I 25 N"10nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C31" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67000 35500 0 15 4C5FF890 4C61CFA4 ~~ +Po 62205 36811 0 0 4C5FF890 4C61CFA4 ~~ Li 0402 Sc 4C61CFA4 AR /4C421DD3/4C61CFA4 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C29" -T1 0 150 200 200 0 40 N I 25 N"10nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 0 40 M V 20 N"C29" +T1 0 -150 200 200 0 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67500 32500 0 15 4C5FF890 4C61CFA5 ~~ +Po 62205 35433 0 0 4C5FF890 4C61CFA5 ~~ Li 0402 Sc 4C61CFA5 AR /4C421DD3/4C61CFA5 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C28" -T1 0 150 200 200 0 40 N I 25 N"100nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 0 40 M V 20 N"C28" +T1 0 -150 200 200 0 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0603 -Po 46000 31000 0 15 4C5FF890 4C61CF2F ~~ +Po 45079 36811 0 0 4C5FF890 4C61CF2F ~~ Li 0603 Sc 4C61CF2F AR /4C421DD3/4C61CF2F Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C21" -T1 0 150 200 200 0 40 N I 25 N"1uF" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 +T0 0 150 200 200 0 40 M V 20 N"C21" +T1 0 -150 200 200 0 40 M I 20 N"1uF" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 294 0 $EndPAD @@ -8137,7 +8142,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "N-000347" +Ne 162 "N-000339" Po -294 0 $EndPAD $PAD @@ -8165,14 +8170,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "N-000341" +Ne 165 "N-000343" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "N-000339" +Ne 164 "N-000341" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8193,7 +8198,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 173 "N-000358" +Ne 169 "N-000351" Po -294 0 $EndPAD $PAD @@ -8249,7 +8254,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "N-000348" +Ne 170 "N-000355" Po -176 0 $EndPAD $PAD @@ -8277,7 +8282,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "N-000348" +Ne 170 "N-000355" Po -176 0 $EndPAD $PAD @@ -8305,7 +8310,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "N-000350" +Ne 167 "N-000345" Po -176 0 $EndPAD $PAD @@ -8333,7 +8338,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "N-000349" +Ne 171 "N-000356" Po -294 0 $EndPAD $PAD @@ -8361,7 +8366,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "N-000346" +Ne 168 "N-000346" Po -294 0 $EndPAD $PAD @@ -8389,7 +8394,7 @@ $PAD Sh "1" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "N-000350" +Ne 167 "N-000345" Po -373 0 $EndPAD $PAD @@ -8417,7 +8422,7 @@ $PAD Sh "1" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "N-000350" +Ne 167 "N-000345" Po -373 0 $EndPAD $PAD @@ -8445,7 +8450,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 173 "N-000358" +Ne 169 "N-000351" Po -570 0 $EndPAD $PAD @@ -8544,14 +8549,14 @@ $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 168 "N-000349" +Ne 171 "N-000356" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 165 "N-000346" +Ne 168 "N-000346" Po 0 1112 $EndPAD $PAD @@ -8593,7 +8598,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 174 "VCCO2" Po -176 0 $EndPAD $PAD @@ -8621,7 +8626,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD @@ -8649,7 +8654,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 174 "VCCO2" Po -176 0 $EndPAD $PAD @@ -8677,7 +8682,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD @@ -8705,7 +8710,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD @@ -8733,7 +8738,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 174 "VCCO2" Po -176 0 $EndPAD $PAD @@ -8761,7 +8766,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD @@ -8789,7 +8794,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD @@ -8817,7 +8822,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 174 "VCCO2" Po -176 0 $EndPAD $PAD @@ -8845,7 +8850,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD @@ -8957,7 +8962,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 2 "+2.5V" +Ne 3 "+3.3V" Po -176 0 $EndPAD $PAD @@ -9041,7 +9046,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 2 "+2.5V" +Ne 3 "+3.3V" Po -176 0 $EndPAD $PAD @@ -9069,7 +9074,7 @@ $PAD Sh "1" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 2 "+2.5V" Po -373 0 $EndPAD $PAD @@ -9097,7 +9102,7 @@ $PAD Sh "1" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 174 "VCCO2" Po -373 0 $EndPAD $PAD @@ -9125,7 +9130,7 @@ $PAD Sh "1" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 2 "+2.5V" Po -373 0 $EndPAD $PAD @@ -9181,7 +9186,7 @@ $PAD Sh "1" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 2 "+2.5V" +Ne 3 "+3.3V" Po -373 0 $EndPAD $PAD @@ -9265,7 +9270,7 @@ $PAD Sh "1" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 2 "+2.5V" Po -570 0 $EndPAD $PAD @@ -9293,7 +9298,7 @@ $PAD Sh "1" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 174 "VCCO2" Po -570 0 $EndPAD $PAD @@ -9321,7 +9326,7 @@ $PAD Sh "1" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "+3.3V" +Ne 2 "+2.5V" Po -570 0 $EndPAD $PAD @@ -9349,7 +9354,7 @@ $PAD Sh "1" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 2 "+2.5V" +Ne 3 "+3.3V" Po -570 0 $EndPAD $PAD @@ -9495,49 +9500,49 @@ $PAD Sh "8" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 174 "VCCO2" Po -750 -1050 $EndPAD $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/PROG_CSO" +Ne 124 "/FPGA_Spartan6/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/PROG_MISO3" +Ne 128 "/FPGA_Spartan6/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/PROG_CCLK" +Ne 123 "/FPGA_Spartan6/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/PROG_MISO0" +Ne 125 "/FPGA_Spartan6/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/PROG_MISO1" +Ne 126 "/FPGA_Spartan6/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/PROG_MISO2" +Ne 127 "/FPGA_Spartan6/PROG_MISO2" Po 250 1050 $EndPAD $PAD @@ -9554,6 +9559,62 @@ Of 0.000000 0.000000 0.000000 Ro 0.000000 0.000000 0.000000 $EndSHAPE3D $EndMODULE SO8E +$MODULE 0402 +Po 65354 29921 1800 0 4C5FF890 4C65D2EF ~~ +Li 0402 +Sc 4C65D2EF +AR /4C421DD3/4C65D28E +Op 0 0 0 +At SMD +T0 0 150 200 200 1800 40 M V 20 N"C71" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 2 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 146 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 50591 34646 1800 0 4C5FF890 4C65D2F1 ~~ +Li 0402 +Sc 4C65D2F1 +AR /4C421DD3/4C65D2A9 +Op 0 0 0 +At SMD +T0 0 150 200 200 1800 40 M V 20 N"C70" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 2 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 146 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 $COTATION Ge 0 24 0 Va 21654 diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index cfc7a77..5d05aa3 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,4 +1,4 @@ -# EESchema Netlist Version 1.1 created Fri 13 Aug 2010 05:17:03 PM COT +# EESchema Netlist Version 1.1 created Fri 13 Aug 2010 06:18:51 PM COT ( ( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB} ( 1 /FPGA_Spartan6/PROG_CSO ) @@ -8,7 +8,7 @@ ( 5 /FPGA_Spartan6/PROG_MISO0 ) ( 6 /FPGA_Spartan6/PROG_CCLK ) ( 7 /FPGA_Spartan6/PROG_MISO3 ) - ( 8 ? ) + ( 8 VCCO2 ) ) ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} ( CASE GND ) @@ -18,7 +18,7 @@ ( 2 /Non_volatile_memories/SD_DAT3 ) ( 3 /Non_volatile_memories/SD_CMD ) ( 4 ? ) - ( 5 /FPGA_Spartan6/SD_CLK ) + ( 5 /Non_volatile_memories/SD_CLK ) ( 6 GND ) ( 7 /Non_volatile_memories/SD_DAT0 ) ( 8 /FPGA_Spartan6/SD_DAT1 ) @@ -39,9 +39,9 @@ ( 13 GND ) ( 14 ? ) ( 15 ? ) - ( 16 /Non_volatile_memories/NF_CLE ) - ( 17 /Non_volatile_memories/NF_ALE ) - ( 18 /Non_volatile_memories/NF_WE_N ) + ( 16 /FPGA_Spartan6/NF_CLE ) + ( 17 /FPGA_Spartan6/NF_ALE ) + ( 18 /FPGA_Spartan6/NF_WE_N ) ( 19 3.3V ) ( 20 ? ) ( 21 ? ) @@ -52,10 +52,10 @@ ( 26 ? ) ( 27 ? ) ( 28 ? ) - ( 29 /Non_volatile_memories/NF_D0 ) + ( 29 /FPGA_Spartan6/NF_D0 ) ( 30 /FPGA_Spartan6/NF_D1 ) - ( 31 /Non_volatile_memories/NF_D2 ) - ( 32 /Non_volatile_memories/NF_D3 ) + ( 31 /FPGA_Spartan6/NF_D2 ) + ( 32 /FPGA_Spartan6/NF_D3 ) ( 33 ? ) ( 34 ? ) ( 35 ? ) @@ -65,7 +65,7 @@ ( 39 ? ) ( 40 ? ) ( 41 /FPGA_Spartan6/NF_D4 ) - ( 42 /FPGA_Spartan6/NF_D5 ) + ( 42 /Non_volatile_memories/NF_D5 ) ( 43 /Non_volatile_memories/NF_D6 ) ( 44 /Non_volatile_memories/NF_D7 ) ( 45 ? ) @@ -82,29 +82,29 @@ ( 7 GND ) ( 8 GND ) ( 9 ? ) - ( 10 N-000349 ) + ( 10 N-000356 ) ( 11 N-000346 ) ( 12 3.3V ) ( 14 3.3V ) ) ( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C} - ( 1 N-000350 ) + ( 1 N-000345 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552BD $noname C36 1uF {Lib=C} - ( 1 N-000350 ) + ( 1 N-000345 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552BC $noname C37 470nF {Lib=C} - ( 1 N-000350 ) + ( 1 N-000345 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552BA $noname F2 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000358 ) + ( 1 N-000351 ) ( 2 +5V ) ) ( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000349 ) + ( 1 N-000356 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03} @@ -112,11 +112,11 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C} - ( 1 N-000348 ) + ( 1 N-000355 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R} - ( 1 N-000348 ) + ( 1 N-000355 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} @@ -124,151 +124,151 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552B0 0603 L6 FB {Lib=INDUCTOR} - ( 1 N-000358 ) + ( 1 N-000351 ) ( 2 ? ) ) ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000341 ) - ( 2 N-000339 ) + ( 1 N-000343 ) + ( 2 N-000341 ) ) ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000347 ) + ( 1 N-000339 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000354 ) + ( 1 N-000358 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000354 ) + ( 1 N-000358 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000353 ) + ( 1 N-000357 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000352 ) + ( 1 N-000340 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000341 ) + ( 1 N-000343 ) ( 2 +5V ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000354 ) - ( S2 N-000354 ) - ( S3 N-000354 ) - ( S4 N-000354 ) - ( 1 N-000339 ) - ( 2 N-000352 ) - ( 3 N-000353 ) - ( 4 N-000347 ) + ( S1 N-000358 ) + ( S2 N-000358 ) + ( S3 N-000358 ) + ( S4 N-000358 ) + ( 1 N-000341 ) + ( 2 N-000340 ) + ( 3 N-000357 ) + ( 4 N-000339 ) ) ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} - ( 1 N-000342 ) + ( 1 N-000344 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} - ( 1 N-000342 ) + ( 1 N-000344 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} - ( 1 N-000342 ) + ( 1 N-000344 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) ( 2 /FPGA_Spartan6/USBA_SPD ) - ( 3 /USB/USBA_RCV ) + ( 3 /FPGA_Spartan6/USBA_RCV ) ( 4 /FPGA_Spartan6/USBA_VP ) - ( 5 /USB/USBA_VM ) + ( 5 /FPGA_Spartan6/USBA_VM ) ( 7 GND ) ( 8 GND ) - ( 9 /FPGA_Spartan6/USBA_OE_N ) - ( 10 N-000352 ) - ( 11 N-000353 ) + ( 9 /USB/USBA_OE_N ) + ( 10 N-000340 ) + ( 11 N-000357 ) ( 12 3.3V ) ( 14 3.3V ) ) ( /4C431A63/4C656D9D $noname C66 470nF {Lib=C} - ( 1 +3.3V ) + ( 1 +2.5V ) ( 2 GND ) ) ( /4C431A63/4C656D9A $noname C63 470nF {Lib=C} - ( 1 +3.3V ) + ( 1 +2.5V ) ( 2 GND ) ) ( /4C431A63/4C656D99 $noname C60 470nF {Lib=C} - ( 1 +3.3V ) + ( 1 +2.5V ) ( 2 GND ) ) ( /4C431A63/4C656D98 $noname C57 4.7uF {Lib=C} - ( 1 +3.3V ) + ( 1 +2.5V ) ( 2 GND ) ) ( /4C431A63/4C656D97 $noname C54 100uF {Lib=C} - ( 1 +3.3V ) + ( 1 +2.5V ) ( 2 GND ) ) ( /4C431A63/4C656D53 $noname C69 470nF {Lib=C} - ( 1 +3.3V ) + ( 1 VCCO2 ) ( 2 GND ) ) ( /4C431A63/4C656D49 $noname C67 470nF {Lib=C} - ( 1 +3.3V ) + ( 1 VCCO2 ) ( 2 GND ) ) ( /4C431A63/4C656D46 $noname C64 470nF {Lib=C} - ( 1 +3.3V ) + ( 1 VCCO2 ) ( 2 GND ) ) ( /4C431A63/4C656D45 $noname C61 470nF {Lib=C} - ( 1 +3.3V ) + ( 1 VCCO2 ) ( 2 GND ) ) ( /4C431A63/4C656D44 $noname C58 4.7uF {Lib=C} - ( 1 +3.3V ) + ( 1 VCCO2 ) ( 2 GND ) ) ( /4C431A63/4C656D43 $noname C55 100uF {Lib=C} - ( 1 +3.3V ) + ( 1 VCCO2 ) ( 2 GND ) ) ( /4C431A63/4C656D08 $noname C68 470nF {Lib=C} - ( 1 +3.3V ) + ( 1 +2.5V ) ( 2 GND ) ) ( /4C431A63/4C656CFC $noname C65 470nF {Lib=C} - ( 1 +3.3V ) + ( 1 +2.5V ) ( 2 GND ) ) ( /4C431A63/4C656CFB $noname C62 470nF {Lib=C} - ( 1 +3.3V ) + ( 1 +2.5V ) ( 2 GND ) ) ( /4C431A63/4C656CFA $noname C59 4.7uF {Lib=C} - ( 1 +3.3V ) + ( 1 +2.5V ) ( 2 GND ) ) ( /4C431A63/4C656CF9 $noname C56 100uF {Lib=C} - ( 1 +3.3V ) + ( 1 +2.5V ) ( 2 GND ) ) ( /4C431A63/4C656CBB $noname C50 470nF {Lib=C} - ( 1 +2.5V ) + ( 1 +3.3V ) ( 2 GND ) ) ( /4C431A63/4C656CBA $noname C47 470nF {Lib=C} - ( 1 +2.5V ) + ( 1 +3.3V ) ( 2 GND ) ) ( /4C431A63/4C656CB9 $noname C44 4.7uF {Lib=C} - ( 1 +2.5V ) + ( 1 +3.3V ) ( 2 GND ) ) ( /4C431A63/4C656CB7 $noname C41 100uF {Lib=C} - ( 1 +2.5V ) + ( 1 +3.3V ) ( 2 GND ) ) ( /4C431A63/4C656C49 $noname C53 470nF {Lib=C} @@ -345,10 +345,10 @@ ( E5 ? ) ( D5 ? ) ( U4 ? ) - ( H21 /FPGA_Spartan6/M1_RAS# ) + ( H21 /DDR_Banks/M1_RAS# ) ( G21 +2.5V ) ( F21 /FPGA_Spartan6/M1_A0 ) - ( D21 /DDR_Banks/M1_CKE ) + ( D21 /FPGA_Spartan6/M1_CKE ) ( C21 +2.5V ) ( B21 ? ) ( A21 ? ) @@ -356,19 +356,19 @@ ( V20 ? ) ( U20 /DDR_Banks/M1_DQ12 ) ( T20 ? ) - ( R20 /FPGA_Spartan6/M1_DQ10 ) + ( R20 /DDR_Banks/M1_DQ10 ) ( P20 ? ) - ( N20 /FPGA_Spartan6/M1_DQ0 ) + ( N20 /DDR_Banks/M1_DQ0 ) ( M20 /DDR_Banks/M1_UDM ) ( L20 /FPGA_Spartan6/M1_LDQS ) ( K20 /FPGA_Spartan6/M1_A5 ) - ( J20 /FPGA_Spartan6/M1_DQ4 ) - ( H20 /FPGA_Spartan6/M1_CLK ) + ( J20 /DDR_Banks/M1_DQ4 ) + ( H20 /DDR_Banks/M1_CLK ) ( G20 /FPGA_Spartan6/M1_A3 ) ( F20 /FPGA_Spartan6/M1_A4 ) ( E20 /FPGA_Spartan6/M1_A7 ) ( D20 ? ) - ( C20 /FPGA_Spartan6/M1_A8 ) + ( C20 /DDR_Banks/M1_A8 ) ( B20 ? ) ( A20 ? ) ( P8 ? ) @@ -378,15 +378,15 @@ ( B3 ? ) ( W2 +2.5V ) ( V2 /FPGA_Spartan6/M0_DQ14 ) - ( T2 /FPGA_Spartan6/M0_UDQS ) + ( T2 /DDR_Banks/M0_UDQS ) ( R2 +2.5V ) - ( P2 /FPGA_Spartan6/M0_DQ8 ) - ( M2 /DDR_Banks/M0_DQ2 ) + ( P2 /DDR_Banks/M0_DQ8 ) + ( M2 /FPGA_Spartan6/M0_DQ2 ) ( L2 +2.5V ) ( K2 /DDR_Banks/M0_DQ6 ) ( H2 /DDR_Banks/M0_A0 ) ( G2 +2.5V ) - ( F2 /DDR_Banks/M0_WE# ) + ( F2 /FPGA_Spartan6/M0_WE# ) ( D2 /DDR_Banks/M0_CKE ) ( C2 +2.5V ) ( B2 ? ) @@ -394,26 +394,26 @@ ( Y1 ? ) ( W1 ? ) ( V1 /FPGA_Spartan6/M0_DQ15 ) - ( U1 /DDR_Banks/M0_DQ13 ) + ( U1 /FPGA_Spartan6/M0_DQ13 ) ( T1 ? ) - ( R1 /DDR_Banks/M0_DQ11 ) - ( P1 /DDR_Banks/M0_DQ9 ) - ( N1 /DDR_Banks/M0_DQ1 ) + ( R1 /FPGA_Spartan6/M0_DQ11 ) + ( P1 /FPGA_Spartan6/M0_DQ9 ) + ( N1 /FPGA_Spartan6/M0_DQ1 ) ( M1 /FPGA_Spartan6/M0_DQ3 ) ( L1 ? ) ( K1 /DDR_Banks/M0_DQ7 ) ( J1 /DDR_Banks/M0_DQ5 ) - ( H1 /FPGA_Spartan6/M0_A1 ) - ( G1 /DDR_Banks/M0_BA1 ) + ( H1 /DDR_Banks/M0_A1 ) + ( G1 /FPGA_Spartan6/M0_BA1 ) ( T4 ? ) ( R4 ? ) ( P4 ? ) ( N4 ? ) ( M4 ? ) - ( L4 /FPGA_Spartan6/M0_LDM ) + ( L4 /DDR_Banks/M0_LDM ) ( K4 /FPGA_Spartan6/M0_CAS# ) ( J4 /DDR_Banks/M0_A6 ) - ( H4 /DDR_Banks/M0_CLK ) + ( H4 /FPGA_Spartan6/M0_CLK ) ( G4 /FPGA_Spartan6/M0_A10 ) ( F4 +2.5V ) ( E4 ? ) @@ -425,41 +425,41 @@ ( R3 /FPGA_Spartan6/M0_DQ10 ) ( P3 ? ) ( N3 /FPGA_Spartan6/M0_DQ0 ) - ( M3 /DDR_Banks/M0_UDM ) + ( M3 /FPGA_Spartan6/M0_UDM ) ( L3 /FPGA_Spartan6/M0_LDQS ) ( K3 /DDR_Banks/M0_A5 ) - ( J3 /FPGA_Spartan6/M0_DQ4 ) - ( H3 /DDR_Banks/M0_CLK# ) - ( G3 /FPGA_Spartan6/M0_BA0 ) + ( J3 /DDR_Banks/M0_DQ4 ) + ( H3 /FPGA_Spartan6/M0_CLK# ) + ( G3 /DDR_Banks/M0_BA0 ) ( F3 /DDR_Banks/M0_A4 ) ( E3 /DDR_Banks/M0_A8 ) ( D3 ? ) ( C3 ? ) ( G10 +3.3V ) ( D10 /Ethernet_Phy/ETH_RXC ) - ( C10 /FPGA_Spartan6/ETH_CLK ) + ( C10 /Ethernet_Phy/ETH_CLK ) ( B10 /FPGA_Spartan6/ETH_CRS ) ( A10 /FPGA_Spartan6/ETH_COL ) ( E9 +3.3V ) - ( D9 /Ethernet_Phy/ETH_TXEN ) + ( D9 /FPGA_Spartan6/ETH_TXEN ) ( C9 /FPGA_Spartan6/ETH_TXD1 ) ( A9 /Ethernet_Phy/ETH_TXD2 ) - ( D8 /FPGA_Spartan6/ETH_TXC ) + ( D8 /Ethernet_Phy/ETH_TXC ) ( C8 /Ethernet_Phy/ETH_TXD0 ) - ( B8 /Ethernet_Phy/ETH_RXER ) - ( A8 /FPGA_Spartan6/ETH_TXER ) + ( B8 /FPGA_Spartan6/ETH_RXER ) + ( A8 /Ethernet_Phy/ETH_TXER ) ( D7 /FPGA_Spartan6/ETH_TXD3 ) - ( C7 /FPGA_Spartan6/ETH_RXD0 ) + ( C7 /Ethernet_Phy/ETH_RXD0 ) ( B7 +3.3V ) - ( A7 /FPGA_Spartan6/ETH_RXDV ) + ( A7 /Ethernet_Phy/ETH_RXDV ) ( D6 /FPGA_Spartan6/ETH_RESET_N ) - ( C6 /Ethernet_Phy/ETH_RXD3 ) - ( B6 /FPGA_Spartan6/ETH_RXD2 ) - ( A6 /FPGA_Spartan6/ETH_RXD1 ) - ( C5 /FPGA_Spartan6/ETH_MDC ) + ( C6 /FPGA_Spartan6/ETH_RXD3 ) + ( B6 /Ethernet_Phy/ETH_RXD2 ) + ( A6 /Ethernet_Phy/ETH_RXD1 ) + ( C5 /Ethernet_Phy/ETH_MDC ) ( A5 /Ethernet_Phy/ETH_MDIO ) ( B4 +3.3V ) - ( A4 /FPGA_Spartan6/ETH_INT ) + ( A4 /Ethernet_Phy/ETH_INT ) ( U19 ? ) ( T19 ? ) ( R19 /FPGA_Spartan6/USBA_SPD ) @@ -472,25 +472,25 @@ ( D17 /Non_volatile_memories/SD_CMD ) ( C17 /Non_volatile_memories/SD_DAT3 ) ( A17 /Non_volatile_memories/SD_DAT2 ) - ( E16 /FPGA_Spartan6/SD_CLK ) + ( E16 /Non_volatile_memories/SD_CLK ) ( C16 /FPGA_Spartan6/NF_CS1_N ) ( B16 /Non_volatile_memories/NF_RE_N ) ( A16 /Non_volatile_memories/NF_RNB ) - ( D15 /Non_volatile_memories/NF_CLE ) - ( C15 /Non_volatile_memories/NF_WE_N ) + ( D15 /FPGA_Spartan6/NF_CLE ) + ( C15 /FPGA_Spartan6/NF_WE_N ) ( B15 +3.3V ) - ( A15 /Non_volatile_memories/NF_ALE ) + ( A15 /FPGA_Spartan6/NF_ALE ) ( G14 +3.3V ) - ( D14 /Non_volatile_memories/NF_D0 ) + ( D14 /FPGA_Spartan6/NF_D0 ) ( C14 ? ) ( B14 ? ) ( A14 ? ) ( E13 +3.3V ) - ( C13 /Non_volatile_memories/NF_D2 ) + ( C13 /FPGA_Spartan6/NF_D2 ) ( A13 /FPGA_Spartan6/NF_D1 ) - ( C12 /FPGA_Spartan6/NF_D5 ) + ( C12 /Non_volatile_memories/NF_D5 ) ( B12 /FPGA_Spartan6/NF_D4 ) - ( A12 /Non_volatile_memories/NF_D3 ) + ( A12 /FPGA_Spartan6/NF_D3 ) ( D11 /Non_volatile_memories/NF_D6 ) ( C11 ? ) ( B11 +3.3V ) @@ -500,44 +500,44 @@ ( F16 ? ) ( L15 ? ) ( W22 ? ) - ( V22 /DDR_Banks/M1_DQ15 ) + ( V22 /FPGA_Spartan6/M1_DQ15 ) ( U22 /FPGA_Spartan6/M1_DQ13 ) ( T22 ? ) ( R22 /FPGA_Spartan6/M1_DQ11 ) - ( P22 /FPGA_Spartan6/M1_DQ9 ) - ( N22 /FPGA_Spartan6/M1_DQ1 ) + ( P22 /DDR_Banks/M1_DQ9 ) + ( N22 /DDR_Banks/M1_DQ1 ) ( M22 /FPGA_Spartan6/M1_DQ3 ) ( L22 ? ) - ( K22 /FPGA_Spartan6/M1_DQ7 ) - ( J22 /FPGA_Spartan6/M1_DQ5 ) + ( K22 /DDR_Banks/M1_DQ7 ) + ( J22 /DDR_Banks/M1_DQ5 ) ( H22 /FPGA_Spartan6/M1_CAS# ) ( G22 ? ) ( F22 /DDR_Banks/M1_A1 ) ( E22 /FPGA_Spartan6/M1_A2 ) ( D22 /FPGA_Spartan6/M1_A12 ) - ( C22 /FPGA_Spartan6/M1_A9 ) + ( C22 /DDR_Banks/M1_A9 ) ( B22 ? ) ( W21 +2.5V ) - ( V21 /DDR_Banks/M1_DQ14 ) + ( V21 /FPGA_Spartan6/M1_DQ14 ) ( T21 /DDR_Banks/M1_UDQS ) ( R21 +2.5V ) - ( P21 /FPGA_Spartan6/M1_DQ8 ) - ( M21 /DDR_Banks/M1_DQ2 ) + ( P21 /DDR_Banks/M1_DQ8 ) + ( M21 /FPGA_Spartan6/M1_DQ2 ) ( L21 +2.5V ) ( K21 /FPGA_Spartan6/M1_DQ6 ) ( M19 ? ) - ( L19 /FPGA_Spartan6/M1_LDM ) - ( K19 /FPGA_Spartan6/M1_A6 ) + ( L19 /DDR_Banks/M1_LDM ) + ( K19 /DDR_Banks/M1_A6 ) ( J19 /FPGA_Spartan6/M1_CLK# ) - ( H19 /DDR_Banks/M1_WE# ) - ( G19 /DDR_Banks/M1_A10 ) + ( H19 /FPGA_Spartan6/M1_WE# ) + ( G19 /FPGA_Spartan6/M1_A10 ) ( F19 /FPGA_Spartan6/M1_A11 ) ( E19 +2.5V ) ( D19 ? ) ( U18 +2.5V ) - ( P18 /FPGA_Spartan6/USBA_OE_N ) + ( P18 /USB/USBA_OE_N ) ( N18 +2.5V ) - ( M18 /USB/USBA_VM ) + ( M18 /FPGA_Spartan6/USBA_VM ) ( K18 ? ) ( J18 +2.5V ) ( H18 ? ) @@ -545,12 +545,12 @@ ( P17 /FPGA_Spartan6/USBA_VP ) ( M17 ? ) ( L17 ? ) - ( K17 /DDR_Banks/M1_BA1 ) + ( K17 /FPGA_Spartan6/M1_BA1 ) ( J17 /DDR_Banks/M1_BA0 ) ( H17 ? ) ( G17 ? ) ( F17 ? ) - ( N16 /USB/USBA_RCV ) + ( N16 /FPGA_Spartan6/USBA_RCV ) ( M16 ? ) ( L16 +2.5V ) ( K16 ? ) @@ -683,7 +683,7 @@ ( V18 ? ) ( T18 ? ) ( AB7 ? ) - ( AA7 N-000149 ) + ( AA7 N-000229 ) ( Y17 ? ) ( W17 ? ) ( V17 ? ) @@ -692,7 +692,7 @@ ( AB6 ? ) ( AA6 ? ) ( Y16 ? ) - ( V16 N-000149 ) + ( V16 N-000229 ) ( U16 ? ) ( T16 ? ) ( R16 ? ) @@ -706,19 +706,19 @@ ( AB4 ? ) ( AA4 ? ) ( F1 ? ) - ( E1 /FPGA_Spartan6/M0_A9 ) + ( E1 /DDR_Banks/M0_A9 ) ( D1 /FPGA_Spartan6/M0_A12 ) ( C1 /FPGA_Spartan6/M0_A11 ) ( B1 ? ) ( AB19 ? ) - ( AA19 N-000149 ) + ( AA19 N-000229 ) ( AB18 ? ) ( AA18 ? ) ( AB17 ? ) ( AB16 ? ) ( AA16 ? ) ( AB15 ? ) - ( AA15 N-000149 ) + ( AA15 N-000229 ) ( AB14 ? ) ( AA14 ? ) ( AB13 ? ) @@ -728,7 +728,7 @@ ( AB21 ? ) ( AA21 /FPGA_Spartan6/PROG_CCLK ) ( AB11 ? ) - ( AA11 N-000149 ) + ( AA11 N-000229 ) ( AB20 /FPGA_Spartan6/PROG_MISO0 ) ( AA20 /FPGA_Spartan6/PROG_MISO1 ) ( AB10 ? ) @@ -737,11 +737,11 @@ ( Y19 ? ) ( V9 ? ) ( U9 ? ) - ( T9 N-000149 ) + ( T9 N-000229 ) ( R9 ? ) ( Y8 ? ) ( W8 ? ) - ( V8 N-000149 ) + ( V8 N-000229 ) ( U8 ? ) ( T8 ? ) ( R8 ? ) @@ -754,7 +754,7 @@ ( U6 ? ) ( T6 ? ) ( Y5 ? ) - ( W5 N-000149 ) + ( W5 N-000229 ) ( V5 ? ) ( T5 /FPGA_Spartan6/PROG_CSO ) ( Y4 ? ) @@ -770,18 +770,18 @@ ( U14 /FPGA_Spartan6/PROG_MISO2 ) ( T14 ? ) ( AB3 ? ) - ( AA3 N-000149 ) + ( AA3 N-000229 ) ( Y13 ? ) ( W13 ? ) ( V13 ? ) ( U13 /FPGA_Spartan6/PROG_MISO3 ) - ( T13 N-000149 ) + ( T13 N-000229 ) ( R13 ? ) ( AB2 ? ) ( AA2 ? ) ( Y12 ? ) ( W12 ? ) - ( V12 N-000149 ) + ( V12 N-000229 ) ( U12 ? ) ( T12 ? ) ( Y11 ? ) @@ -798,7 +798,7 @@ ) ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} ( 1 /Ethernet_Phy/ETH_PLL1.8V ) - ( 2 N-000328 ) + ( 2 N-000331 ) ) ( /4C4320F3/4C5D810A $noname L3 INDUCTOR {Lib=INDUCTOR} ( 1 /Ethernet_Phy/ETH_A1.8V ) @@ -806,15 +806,15 @@ ) ( /4C4320F3/4C5D8104 $noname C6 C {Lib=C} ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 N-000328 ) + ( 2 N-000331 ) ) ( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR} - ( 1 N-000320 ) + ( 1 N-000326 ) ( 2 /Ethernet_Phy/ETH_A1.8V ) ) ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} - ( 1 N-000320 ) - ( 2 N-000328 ) + ( 1 N-000326 ) + ( 2 N-000331 ) ) ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} ( 1 /Ethernet_Phy/ETH_1.8V ) @@ -849,7 +849,7 @@ ( 2 3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000323 ) + ( 1 N-000328 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} @@ -861,30 +861,30 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000322 ) + ( 1 N-000318 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000322 ) + ( 1 N-000318 ) ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} ( 1 /Ethernet_Phy/ETH_MDIO ) - ( 2 /FPGA_Spartan6/ETH_MDC ) - ( 3 /Ethernet_Phy/ETH_RXD3 ) - ( 4 /FPGA_Spartan6/ETH_RXD2 ) - ( 5 /FPGA_Spartan6/ETH_RXD1 ) - ( 6 /FPGA_Spartan6/ETH_RXD0 ) + ( 2 /Ethernet_Phy/ETH_MDC ) + ( 3 /FPGA_Spartan6/ETH_RXD3 ) + ( 4 /Ethernet_Phy/ETH_RXD2 ) + ( 5 /Ethernet_Phy/ETH_RXD1 ) + ( 6 /Ethernet_Phy/ETH_RXD0 ) ( 7 3.3V ) ( 8 GND ) - ( 9 /FPGA_Spartan6/ETH_RXDV ) + ( 9 /Ethernet_Phy/ETH_RXDV ) ( 10 /Ethernet_Phy/ETH_RXC ) - ( 11 /Ethernet_Phy/ETH_RXER ) + ( 11 /FPGA_Spartan6/ETH_RXER ) ( 12 GND ) ( 13 /Ethernet_Phy/ETH_1.8V ) - ( 14 /FPGA_Spartan6/ETH_TXER ) - ( 15 /FPGA_Spartan6/ETH_TXC ) - ( 16 /Ethernet_Phy/ETH_TXEN ) + ( 14 /Ethernet_Phy/ETH_TXER ) + ( 15 /Ethernet_Phy/ETH_TXC ) + ( 16 /FPGA_Spartan6/ETH_TXEN ) ( 17 /Ethernet_Phy/ETH_TXD0 ) ( 18 /FPGA_Spartan6/ETH_TXD1 ) ( 19 /Ethernet_Phy/ETH_TXD2 ) @@ -893,28 +893,28 @@ ( 22 /FPGA_Spartan6/ETH_CRS ) ( 23 GND ) ( 24 3.3V ) - ( 25 /FPGA_Spartan6/ETH_INT ) + ( 25 /Ethernet_Phy/ETH_INT ) ( 26 /Ethernet_Phy/ETH_LED0 ) ( 27 /Ethernet_Phy/ETH_LED1 ) ( 28 ? ) ( 29 ? ) ( 30 ? ) ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000324 ) - ( 33 N-000318 ) + ( 32 N-000329 ) + ( 33 N-000316 ) ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000323 ) + ( 37 N-000328 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) - ( 40 N-000325 ) + ( 40 N-000330 ) ( 41 N-000317 ) ( 42 ? ) ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 /FPGA_Spartan6/ETH_CLK ) + ( 46 /Ethernet_Phy/ETH_CLK ) ( 47 /Ethernet_Phy/ETH_PLL1.8V ) ( 48 /FPGA_Spartan6/ETH_RESET_N ) ) @@ -924,18 +924,18 @@ ) ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000325 ) + ( 2 N-000330 ) ) ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000324 ) + ( 2 N-000329 ) ) ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000318 ) + ( 2 N-000316 ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000331 ) + ( 1 N-000333 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} @@ -944,19 +944,27 @@ ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} ( 1 N-000317 ) - ( 2 N-000325 ) + ( 2 N-000330 ) ( 3 3.3V ) ( 4 GND ) ( 5 GND ) ( 6 3.3V ) - ( 7 N-000318 ) - ( 8 N-000324 ) + ( 7 N-000316 ) + ( 8 N-000329 ) ( 9 3.3V ) ( 10 N-000319 ) ( 11 3.3V ) - ( 12 N-000331 ) - ( 13 N-000322 ) - ( 14 N-000322 ) + ( 12 N-000333 ) + ( 13 N-000318 ) + ( 14 N-000318 ) + ) + ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C65D28E 0402 C71 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) ) ( /4C421DD3/4C61D1D4 1206 C34 10uF {Lib=CAP} ( 1 +2.5V ) @@ -1048,33 +1056,33 @@ ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /FPGA_Spartan6/M1_DQ0 ) + ( 2 /DDR_Banks/M1_DQ0 ) ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M1_DQ1 ) - ( 5 /DDR_Banks/M1_DQ2 ) + ( 4 /DDR_Banks/M1_DQ1 ) + ( 5 /FPGA_Spartan6/M1_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M1_DQ3 ) - ( 8 /FPGA_Spartan6/M1_DQ4 ) + ( 8 /DDR_Banks/M1_DQ4 ) ( 9 +2.5V ) - ( 10 /FPGA_Spartan6/M1_DQ5 ) + ( 10 /DDR_Banks/M1_DQ5 ) ( 11 /FPGA_Spartan6/M1_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Spartan6/M1_DQ7 ) + ( 13 /DDR_Banks/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /FPGA_Spartan6/M1_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Spartan6/M1_LDM ) - ( 21 /DDR_Banks/M1_WE# ) + ( 20 /DDR_Banks/M1_LDM ) + ( 21 /FPGA_Spartan6/M1_WE# ) ( 22 /FPGA_Spartan6/M1_CAS# ) - ( 23 /FPGA_Spartan6/M1_RAS# ) + ( 23 /DDR_Banks/M1_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /DDR_Banks/M1_BA0 ) - ( 27 /DDR_Banks/M1_BA1 ) - ( 28 /DDR_Banks/M1_A10 ) + ( 27 /FPGA_Spartan6/M1_BA1 ) + ( 28 /FPGA_Spartan6/M1_A10 ) ( 29 /FPGA_Spartan6/M1_A0 ) ( 30 /DDR_Banks/M1_A1 ) ( 31 /FPGA_Spartan6/M1_A2 ) @@ -1083,16 +1091,16 @@ ( 34 GND ) ( 35 /FPGA_Spartan6/M1_A4 ) ( 36 /FPGA_Spartan6/M1_A5 ) - ( 37 /FPGA_Spartan6/M1_A6 ) + ( 37 /DDR_Banks/M1_A6 ) ( 38 /FPGA_Spartan6/M1_A7 ) - ( 39 /FPGA_Spartan6/M1_A8 ) - ( 40 /FPGA_Spartan6/M1_A9 ) + ( 39 /DDR_Banks/M1_A8 ) + ( 40 /DDR_Banks/M1_A9 ) ( 41 /FPGA_Spartan6/M1_A11 ) ( 42 /FPGA_Spartan6/M1_A12 ) ( 43 ? ) ( 44 /FPGA_Spartan6/M1_CLK# ) - ( 45 /DDR_Banks/M1_CKE ) - ( 46 /FPGA_Spartan6/M1_CLK ) + ( 45 /FPGA_Spartan6/M1_CKE ) + ( 46 /DDR_Banks/M1_CLK ) ( 47 /DDR_Banks/M1_UDM ) ( 48 GND ) ( 49 N-000051 ) @@ -1100,29 +1108,29 @@ ( 51 /DDR_Banks/M1_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /FPGA_Spartan6/M1_DQ8 ) + ( 54 /DDR_Banks/M1_DQ8 ) ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M1_DQ9 ) - ( 57 /FPGA_Spartan6/M1_DQ10 ) + ( 56 /DDR_Banks/M1_DQ9 ) + ( 57 /DDR_Banks/M1_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M1_DQ11 ) ( 60 /DDR_Banks/M1_DQ12 ) ( 61 +2.5V ) ( 62 /FPGA_Spartan6/M1_DQ13 ) - ( 63 /DDR_Banks/M1_DQ14 ) + ( 63 /FPGA_Spartan6/M1_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M1_DQ15 ) + ( 65 /FPGA_Spartan6/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) ( 2 /FPGA_Spartan6/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /DDR_Banks/M0_DQ1 ) - ( 5 /DDR_Banks/M0_DQ2 ) + ( 4 /FPGA_Spartan6/M0_DQ1 ) + ( 5 /FPGA_Spartan6/M0_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M0_DQ3 ) - ( 8 /FPGA_Spartan6/M0_DQ4 ) + ( 8 /DDR_Banks/M0_DQ4 ) ( 9 +2.5V ) ( 10 /DDR_Banks/M0_DQ5 ) ( 11 /DDR_Banks/M0_DQ6 ) @@ -1134,17 +1142,17 @@ ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Spartan6/M0_LDM ) - ( 21 /DDR_Banks/M0_WE# ) + ( 20 /DDR_Banks/M0_LDM ) + ( 21 /FPGA_Spartan6/M0_WE# ) ( 22 /FPGA_Spartan6/M0_CAS# ) ( 23 /DDR_Banks/M0_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 /FPGA_Spartan6/M0_BA0 ) - ( 27 /DDR_Banks/M0_BA1 ) + ( 26 /DDR_Banks/M0_BA0 ) + ( 27 /FPGA_Spartan6/M0_BA1 ) ( 28 /FPGA_Spartan6/M0_A10 ) ( 29 /DDR_Banks/M0_A0 ) - ( 30 /FPGA_Spartan6/M0_A1 ) + ( 30 /DDR_Banks/M0_A1 ) ( 31 /FPGA_Spartan6/M0_A2 ) ( 32 /FPGA_Spartan6/M0_A3 ) ( 33 +2.5V ) @@ -1154,29 +1162,29 @@ ( 37 /DDR_Banks/M0_A6 ) ( 38 /FPGA_Spartan6/M0_A7 ) ( 39 /DDR_Banks/M0_A8 ) - ( 40 /FPGA_Spartan6/M0_A9 ) + ( 40 /DDR_Banks/M0_A9 ) ( 41 /FPGA_Spartan6/M0_A11 ) ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) - ( 44 /DDR_Banks/M0_CLK# ) + ( 44 /FPGA_Spartan6/M0_CLK# ) ( 45 /DDR_Banks/M0_CKE ) - ( 46 /DDR_Banks/M0_CLK ) - ( 47 /DDR_Banks/M0_UDM ) + ( 46 /FPGA_Spartan6/M0_CLK ) + ( 47 /FPGA_Spartan6/M0_UDM ) ( 48 GND ) ( 49 N-000052 ) ( 50 ? ) - ( 51 /FPGA_Spartan6/M0_UDQS ) + ( 51 /DDR_Banks/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /FPGA_Spartan6/M0_DQ8 ) + ( 54 /DDR_Banks/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /DDR_Banks/M0_DQ9 ) + ( 56 /FPGA_Spartan6/M0_DQ9 ) ( 57 /FPGA_Spartan6/M0_DQ10 ) ( 58 GND ) - ( 59 /DDR_Banks/M0_DQ11 ) + ( 59 /FPGA_Spartan6/M0_DQ11 ) ( 60 /FPGA_Spartan6/M0_DQ12 ) ( 61 +2.5V ) - ( 62 /DDR_Banks/M0_DQ13 ) + ( 62 /FPGA_Spartan6/M0_DQ13 ) ( 63 /FPGA_Spartan6/M0_DQ14 ) ( 64 GND ) ( 65 /FPGA_Spartan6/M0_DQ15 ) @@ -1506,6 +1514,16 @@ $component R7 SM0805 R?-* $endlist +$component C70 + SM* + C? + C1-1 +$endlist +$component C71 + SM* + C? + C1-1 +$endlist $component C34 SM* C? @@ -1624,697 +1642,703 @@ $endfootprintlist } { Pin List by Nets Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" - U8 1 U1 T5 + U8 1 Net 2 "/Non volatile memories/NF_RE_N" "NF_RE_N" U5 8 U1 B16 Net 3 "/FPGA Spartan6/NF_CS1_N" "NF_CS1_N" U5 9 U1 C16 -Net 4 "/Non volatile memories/NF_ALE" "NF_ALE" - U1 A15 +Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE" U5 17 -Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" - U1 D8 + U1 A15 +Net 5 "/Ethernet Phy/ETH_TXC" "ETH_TXC" U4 15 + U1 D8 Net 6 "/Ethernet Phy/ETH_RXC" "ETH_RXC" - U1 D10 U4 10 -Net 7 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" - U1 C10 + U1 D10 +Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK" U4 46 + U1 C10 Net 8 "/FPGA Spartan6/USBA_SPD" "USBA_SPD" - U1 R19 U6 2 -Net 9 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" - U1 P18 + U1 R19 +Net 9 "/USB/USBA_OE_N" "USBA_OE_N" U6 9 -Net 10 "/USB/USBA_RCV" "USBA_RCV" - U1 N16 + U1 P18 +Net 10 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" U6 3 + U1 N16 Net 11 "/FPGA Spartan6/USBA_VP" "USBA_VP" U6 4 U1 P17 -Net 12 "/USB/USBA_VM" "USBA_VM" - U6 5 +Net 12 "/FPGA Spartan6/USBA_VM" "USBA_VM" U1 M18 + U6 5 Net 13 "/FPGA Spartan6/ETH_COL" "ETH_COL" U1 A10 U4 21 Net 14 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" U4 22 U1 B10 -Net 15 "/FPGA Spartan6/SD_CLK" "SD_CLK" - U1 E16 +Net 15 "/Non volatile memories/SD_CLK" "SD_CLK" J1 5 -Net 16 "/FPGA Spartan6/ETH_INT" "ETH_INT" + U1 E16 +Net 16 "/Ethernet Phy/ETH_INT" "ETH_INT" U1 A4 U4 25 -Net 17 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" - U1 C5 +Net 17 "/Ethernet Phy/ETH_MDC" "ETH_MDC" U4 2 + U1 C5 Net 18 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" - U4 1 - R1 1 U1 A5 + R1 1 + U4 1 Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" U4 48 U1 D6 -Net 20 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" +Net 20 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" U4 9 U1 A7 -Net 21 "/Ethernet Phy/ETH_RXER" "ETH_RXER" +Net 21 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" U1 B8 U4 11 -Net 22 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" - U1 A8 +Net 22 "/Ethernet Phy/ETH_TXER" "ETH_TXER" U4 14 -Net 23 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" - U4 16 + U1 A8 +Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" U1 D9 + U4 16 Net 24 "/DDR Banks/M1_UDM" "M1_UDM" - U1 M20 U3 47 + U1 M20 Net 25 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" - U1 L20 U3 16 -Net 26 "/FPGA Spartan6/M1_LDM" "M1_LDM" + U1 L20 +Net 26 "/DDR Banks/M1_LDM" "M1_LDM" U3 20 U1 L19 Net 27 "/DDR Banks/M1_UDQS" "M1_UDQS" - U1 T21 U3 51 -Net 28 "/FPGA Spartan6/M0_UDQS" "M0_UDQS" + U1 T21 +Net 28 "/DDR Banks/M0_UDQS" "M0_UDQS" U1 T2 U2 51 -Net 29 "/FPGA Spartan6/M0_LDM" "M0_LDM" - U2 20 +Net 29 "/DDR Banks/M0_LDM" "M0_LDM" U1 L4 + U2 20 Net 30 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" U3 22 U1 H22 -Net 31 "/DDR Banks/M1_CKE" "M1_CKE" +Net 31 "/FPGA Spartan6/M1_CKE" "M1_CKE" U3 45 U1 D21 -Net 32 "/FPGA Spartan6/M1_CLK" "M1_CLK" +Net 32 "/DDR Banks/M1_CLK" "M1_CLK" U3 46 U1 H20 Net 33 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" - U3 44 U1 J19 + U3 44 Net 34 "GND" "GND" U8 4 - U1 N9 - U1 B5 - U1 G5 - U1 L5 - U1 R5 - U1 K10 - U1 M10 - U1 P10 - U1 V10 + U1 U2 U1 J11 - U1 L11 - U1 E7 - U1 H7 - U1 U7 - U1 W7 - U1 B9 - U1 J9 - U1 L9 - J1 CASE - J1 CASE - J1 CASE - J1 COM - J1 6 - U2 12 - U2 52 - U2 6 - U2 66 - U2 48 - U2 58 - U2 24 - U2 34 - U2 64 - U5 36 - U5 13 - U1 N11 - U1 N13 - U1 L13 - U1 J13 - U1 B13 U1 A22 + U3 66 + U1 J13 + U3 64 + U1 AA9 + U3 34 + U1 N2 + U3 24 + U1 J2 + U1 E2 + U1 B13 + U3 52 + U1 A1 + U3 12 + U1 L9 + U1 J9 + U1 AB1 + U1 U21 + U1 N21 + U1 J21 + U1 E21 + U1 N11 + U1 V10 + U1 P10 + U1 M10 + C39 2 U1 P12 + U1 M12 + U1 K10 + U1 N9 + U1 L11 + U1 J15 + U1 G18 + U1 R18 + U1 L18 + U1 E15 + J1 6 + J1 COM + J1 CASE + J1 CASE + J1 CASE + U1 D18 + U5 13 + U1 N17 + U1 B17 + U1 W16 + U1 AA5 U1 AA17 + U1 L13 + U1 N13 U1 K14 U1 M14 U1 P14 + U5 36 U1 V14 - U1 E15 - U1 J15 - U1 AA5 - U1 A1 - U1 E2 - U1 J2 - U1 N2 - U1 U2 - U1 D4 - U1 V4 - U1 E21 - U1 J21 - U1 N21 - U1 U21 - U1 AB1 - U1 M12 - U1 W16 - U1 B17 - U1 N17 - U1 D18 - U1 G18 - U1 L18 - U1 R18 - U1 W19 - U1 AA9 + U1 E7 + U1 R5 + U1 L5 + U2 64 + U2 34 + U2 24 U1 AB22 U1 AA13 + U1 B9 + U1 W7 + U1 U7 + U3 6 + U1 H7 + U1 V4 + U1 D4 + U3 58 + U3 48 + U1 W19 + U2 52 + U2 12 + U2 58 + U2 48 + U2 66 + U1 G5 + U1 B5 + U2 6 U4 8 - U4 12 - U4 23 - R2 2 - C11 2 - C10 2 - C12 2 R9 2 - V2 2 - C15 2 - U4 44 - U4 35 - U4 36 - U4 39 - J4 5 - J4 4 - C8 2 - C7 2 - C5 2 - C3 2 + C12 2 + C34 2 + C71 2 + C70 2 + R2 2 C1 2 + C3 2 + J4 5 + U4 39 + U4 36 + J4 4 + C53 2 + V2 2 + C41 2 + U4 35 + U4 44 + U4 23 + U4 12 + C5 2 + C7 2 + C8 2 C2 2 - L7 2 - L5 2 + C10 2 + C11 2 + C22 2 + C23 2 + C25 2 + C24 2 + C30 2 + C32 2 + C31 2 + C29 2 + C27 2 + C28 2 + C33 2 + C26 2 + C21 2 R10 2 - C16 2 - V1 2 - U7 8 + L5 2 + C68 2 + L7 2 U7 7 - R15 2 - C38 2 - V3 2 - V4 2 - C37 2 - C36 2 + U7 8 C35 2 + C36 2 + C37 2 + V4 2 + V3 2 + C38 2 + C55 2 + C58 2 + C61 2 + R15 2 + C64 2 + C67 2 + C69 2 + C54 2 + C57 2 U6 8 + C62 2 U6 7 C13 2 C14 2 - C62 2 C65 2 + C15 2 + C42 2 + C44 2 + C47 2 + C50 2 + V1 2 + C56 2 + C16 2 + C59 2 + C46 2 + C49 2 + C51 2 + C60 2 + C63 2 + C66 2 C45 2 C48 2 C40 2 C43 2 C52 2 - C46 2 - C49 2 - C51 2 - C53 2 - C54 2 - C57 2 - C60 2 - C63 2 - C41 2 - C44 2 - C47 2 - C50 2 - C56 2 - C59 2 - C39 2 - C42 2 - C66 2 - C68 2 - C55 2 - C58 2 - C61 2 - C64 2 - C67 2 - C69 2 - C34 2 - U3 64 - C33 2 - U3 34 - U3 24 - C30 2 - C32 2 - C27 2 - C21 2 - U3 6 - C24 2 - C25 2 - C23 2 - C22 2 - U3 52 - U3 58 - U3 48 - C28 2 - C31 2 - C29 2 - U3 66 - U3 12 - C26 2 -Net 35 "/DDR Banks/M0_CLK#" "M0_CLK#" - U2 44 +Net 35 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" U1 H3 -Net 36 "/DDR Banks/M0_CLK" "M0_CLK" - U1 H4 + U2 44 +Net 36 "/FPGA Spartan6/M0_CLK" "M0_CLK" U2 46 + U1 H4 Net 37 "/DDR Banks/M0_CKE" "M0_CKE" - U2 45 U1 D2 + U2 45 Net 38 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" U2 22 U1 K4 -Net 39 "/DDR Banks/M1_WE#" "M1_WE#" - U3 21 +Net 39 "/FPGA Spartan6/M1_WE#" "M1_WE#" U1 H19 -Net 40 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" - U3 23 + U3 21 +Net 40 "/DDR Banks/M1_RAS#" "M1_RAS#" U1 H21 + U3 23 Net 41 "/DDR Banks/M0_RAS#" "M0_RAS#" U1 K5 U2 23 -Net 42 "/DDR Banks/M0_WE#" "M0_WE#" +Net 42 "/FPGA Spartan6/M0_WE#" "M0_WE#" U2 21 U1 F2 Net 43 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" U1 L3 U2 16 -Net 44 "/DDR Banks/M0_UDM" "M0_UDM" +Net 44 "/FPGA Spartan6/M0_UDM" "M0_UDM" U1 M3 U2 47 Net 45 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" U1 AA21 U8 6 Net 46 "/Non volatile memories/NF_RNB" "NF_RNB" + U1 A16 U5 6 U5 7 - U1 A16 -Net 47 "/Non volatile memories/NF_WE_N" "NF_WE_N" - U5 18 +Net 47 "/FPGA Spartan6/NF_WE_N" "NF_WE_N" U1 C15 -Net 48 "/Non volatile memories/NF_CLE" "NF_CLE" - U5 16 + U5 18 +Net 48 "/FPGA Spartan6/NF_CLE" "NF_CLE" U1 D15 + U5 16 Net 49 "/Non volatile memories/SD_CMD" "SD_CMD" - U1 D17 J1 3 + U1 D17 Net 50 "" "" R14 2 C20 2 Net 51 "" "" - R14 1 - R13 2 - U3 49 C20 1 C19 2 + U3 49 + R13 2 + R14 1 Net 52 "" "" - R12 1 R11 2 - C17 2 U2 49 + R12 1 + C17 2 C18 1 Net 53 "+2.5V" "+2.5V" - U2 33 - U2 61 - U1 R10 - U1 F11 U1 M15 - U2 1 - U1 D16 - U1 R6 - U1 V6 - C19 1 - C28 1 - C53 1 - C33 1 - C41 1 - C44 1 - C47 1 - U1 L8 - U1 N8 - U1 H9 - U3 33 - R11 1 - C23 1 - C25 1 - U1 W21 - C24 1 - U3 18 - U3 61 - U1 R21 - U1 R12 - C29 1 - C30 1 - U1 J5 - U3 9 - C31 1 - U1 E19 - U1 U18 - U2 55 - U2 15 - U1 N18 - U1 J18 - R13 1 - C22 1 - U2 18 - U1 H15 - U1 K15 - U1 L21 - U1 L16 - C26 1 - U2 9 - C34 1 - U1 U11 - U1 G12 - U2 3 - U3 3 - C51 1 - C49 1 - C46 1 - U3 55 C52 1 C43 1 - C40 1 U7 1 - U1 F6 - U1 F4 - U1 U5 - U1 N5 - C17 1 - U3 15 - U3 1 - C27 1 - U1 L7 - C32 1 + U1 D16 + C40 1 + U1 H15 + C63 1 + C60 1 + U1 G12 + U1 R12 + C66 1 + C49 1 + C46 1 + U1 K15 + U1 F11 + U1 U11 + U1 H9 + U1 R10 + U1 R6 + U1 V6 + C68 1 + U1 L8 + U1 N8 + C54 1 + C57 1 + U1 U18 + U1 W21 + U1 R21 + U1 L21 U1 G21 U1 C21 - U1 W2 - U1 R2 - C50 1 - U1 L2 - U1 G2 - C21 1 - U1 C2 + U1 U5 + U1 N5 + U1 J5 + U1 L7 + U1 F6 + U1 E19 + U1 N18 + U1 J18 + C51 1 + C53 1 + U1 L16 + C56 1 + C59 1 + C62 1 U6 1 + C65 1 + U3 33 + C27 1 + C32 1 + C30 1 + C31 1 + C29 1 + U1 W2 + C28 1 + U1 R2 + R13 1 + C22 1 + C23 1 + U1 L2 + C25 1 + C24 1 + C26 1 + C21 1 + U1 G2 + U1 C2 + U2 61 + U2 1 + U2 3 + U2 9 + U2 18 + U2 33 + U2 15 + U2 55 + U3 3 + U3 9 + R11 1 + C19 1 + C17 1 + U3 1 + U3 15 + U3 55 + U3 18 + U3 61 + C33 1 + U1 F4 + C70 1 + C34 1 + C71 1 Net 54 "" "" C18 2 R12 2 Net 99 "3.3V" "3.3V" - U6 12 - U6 14 - J4 3 - U5 19 - U5 12 - R5 1 - U4 24 - J4 9 + R3 1 + R1 2 + R4 1 + J4 11 + C1 1 + C10 1 + C3 1 J4 6 + J4 9 + C11 1 + U5 12 + U6 14 + R6 1 + R5 1 + U5 19 + J4 3 + U6 12 + U7 12 L2 1 C5 1 - C3 1 - C1 1 - R3 1 + U4 24 U4 7 - R6 1 - U7 12 - R4 1 - R1 2 - J4 11 - C11 1 U7 14 - C10 1 -Net 101 "+3.3V" "+3.3V" - C66 1 - C65 1 - C68 1 +Net 100 "VCCO2" "VCCO2" + C69 1 C55 1 C58 1 C61 1 - C64 1 C67 1 + C64 1 + U8 8 +Net 101 "+3.3V" "+3.3V" + U5 37 + U1 E9 U1 B7 U1 B4 - C56 1 - C59 1 - C62 1 - C69 1 - C54 1 - C57 1 - C60 1 - C63 1 - U1 B19 - U1 E17 - U1 B11 + C41 1 U1 G10 - U1 E9 - U1 B15 - U1 G14 + U1 B19 + C44 1 + U1 B11 + U1 E17 + C47 1 + C50 1 U1 E13 - U5 37 -Net 149 "" "" - U1 AA7 - U1 T9 + U1 G14 + U1 B15 +Net 229 "" "" + U1 V16 + U1 AA15 U1 T13 U1 AA3 - U1 AA11 - U1 AA19 - U1 AA15 U1 V8 - U1 V16 + U1 AA19 U1 W5 U1 V12 -Net 237 "+1.2V" "+1.2V" - U1 K9 - U1 M9 + U1 T9 + U1 AA11 + U1 AA7 +Net 247 "+1.2V" "+1.2V" + C39 1 U1 J8 - U1 K11 U1 N10 U1 L10 U1 J10 U1 P9 - C39 1 - U1 L14 - C42 1 + U1 M9 + U1 K9 + U1 N12 U1 L12 U1 J12 - C45 1 U1 P11 U1 M11 - U1 J14 + U1 K11 + C42 1 + C45 1 C48 1 - U1 P13 U1 M13 - U1 K13 - U1 N12 + U1 P13 + U1 J14 + U1 L14 U1 N14 U1 R14 -Net 316 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - R7 2 - U4 26 -Net 317 "" "" - U4 41 - R3 2 - J4 1 -Net 318 "" "" - U4 33 + U1 K13 +Net 316 "" "" R5 2 J4 7 + U4 33 +Net 317 "" "" + R3 2 + U4 41 + J4 1 +Net 318 "" "" + J4 14 + J4 13 + C12 1 + R9 1 Net 319 "" "" R7 1 J4 10 -Net 320 "" "" - C4 1 - L1 1 -Net 321 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - U4 47 - L3 2 - C9 1 -Net 322 "" "" - C12 1 - R9 1 - J4 13 - J4 14 -Net 323 "" "" - U4 37 - R2 1 -Net 324 "" "" - J4 8 - U4 32 - R6 2 -Net 325 "" "" - R4 2 - U4 40 - J4 2 -Net 326 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" - U4 13 +Net 320 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + U4 26 + R7 2 +Net 321 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" C2 1 -Net 327 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - L1 2 - C6 1 + U4 13 +Net 322 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + L3 2 + U4 47 + C9 1 +Net 325 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" L3 1 + C6 1 U4 31 -Net 328 "" "" - C4 2 - C6 2 - C9 2 -Net 329 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + L1 2 +Net 326 "" "" + L1 1 + C4 1 +Net 327 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + L2 2 + C8 1 U4 38 C7 1 - C8 1 - L2 2 -Net 330 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - U4 27 - R8 2 +Net 328 "" "" + R2 1 + U4 37 +Net 329 "" "" + R6 2 + U4 32 + J4 8 +Net 330 "" "" + R4 2 + J4 2 + U4 40 Net 331 "" "" + C9 2 + C4 2 + C6 2 +Net 332 "/Ethernet Phy/ETH_LED1" "ETH_LED1" + R8 2 + U4 27 +Net 333 "" "" R8 1 J4 12 Net 339 "" "" - L4 2 - J5 1 -Net 340 "+5V" "+5V" - F1 2 - F2 2 -Net 341 "" "" - F1 1 - L4 1 -Net 342 "" "" - C14 1 - C15 1 - C13 1 -Net 346 "" "" - U7 11 - V3 1 - V3 1 -Net 347 "" "" L5 1 J5 4 -Net 348 "" "" - C38 1 +Net 340 "" "" + U6 10 + V2 1 + V2 1 + J5 2 +Net 341 "" "" + J5 1 + L4 2 +Net 342 "+5V" "+5V" + F1 2 + F2 2 +Net 343 "" "" + L4 1 + F1 1 +Net 344 "" "" + C13 1 + C14 1 + C15 1 +Net 345 "" "" + C35 1 + C36 1 + C37 1 +Net 346 "" "" + V3 1 + V3 1 + U7 11 +Net 351 "" "" + F2 1 + L6 1 +Net 355 "" "" R15 1 -Net 349 "" "" + C38 1 +Net 356 "" "" U7 10 V4 1 V4 1 -Net 350 "" "" - C35 1 - C37 1 - C36 1 -Net 352 "" "" - V2 1 - J5 2 - V2 1 - U6 10 -Net 353 "" "" - V1 1 - V1 1 +Net 357 "" "" U6 11 J5 3 -Net 354 "" "" - J5 S2 - J5 S1 - J5 S3 - J5 S4 - C16 1 - R10 1 + V1 1 + V1 1 Net 358 "" "" - F2 1 - L6 1 + C16 1 + J5 S1 + J5 S2 + R10 1 + J5 S4 + J5 S3 Net 359 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" - U1 U13 U8 7 + U1 U13 Net 360 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" - U1 U14 U8 3 + U1 U14 Net 361 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" - U1 AA20 U8 2 + U1 AA20 Net 362 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" - U8 5 U1 AB20 + U8 5 Net 363 "/Non volatile memories/NF_D7" "NF_D7" - U5 44 U1 A11 + U5 44 Net 364 "/Non volatile memories/NF_D6" "NF_D6" - U1 D11 U5 43 -Net 365 "/FPGA Spartan6/NF_D5" "NF_D5" - U5 42 + U1 D11 +Net 365 "/Non volatile memories/NF_D5" "NF_D5" U1 C12 + U5 42 Net 366 "/FPGA Spartan6/NF_D4" "NF_D4" - U1 B12 U5 41 -Net 367 "/Non volatile memories/NF_D3" "NF_D3" - U1 A12 + U1 B12 +Net 367 "/FPGA Spartan6/NF_D3" "NF_D3" U5 32 -Net 368 "/Non volatile memories/NF_D2" "NF_D2" + U1 A12 +Net 368 "/FPGA Spartan6/NF_D2" "NF_D2" U1 C13 U5 31 Net 369 "/FPGA Spartan6/NF_D1" "NF_D1" - U1 A13 U5 30 -Net 370 "/Non volatile memories/NF_D0" "NF_D0" + U1 A13 +Net 370 "/FPGA Spartan6/NF_D0" "NF_D0" U5 29 U1 D14 Net 371 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" - U4 20 U1 D7 + U4 20 Net 372 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" - U4 19 U1 A9 + U4 19 Net 373 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" - U4 18 U1 C9 + U4 18 Net 374 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" U4 17 U1 C8 -Net 375 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" - U1 C6 +Net 375 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" U4 3 -Net 376 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" + U1 C6 +Net 376 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" U1 B6 U4 4 -Net 377 "/FPGA Spartan6/ETH_RXD1" "ETH_RXD1" - U4 5 +Net 377 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" U1 A6 -Net 378 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" + U4 5 +Net 378 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" U1 C7 U4 6 -Net 379 "/DDR Banks/M0_BA1" "M0_BA1" +Net 379 "/FPGA Spartan6/M0_BA1" "M0_BA1" U2 27 U1 G1 -Net 380 "/FPGA Spartan6/M0_BA0" "M0_BA0" - U2 26 +Net 380 "/DDR Banks/M0_BA0" "M0_BA0" U1 G3 -Net 381 "/DDR Banks/M1_BA1" "M1_BA1" + U2 26 +Net 381 "/FPGA Spartan6/M1_BA1" "M1_BA1" U1 K17 U3 27 Net 382 "/DDR Banks/M1_BA0" "M1_BA0" U1 J17 U3 26 -Net 383 "/DDR Banks/M1_DQ15" "M1_DQ15" +Net 383 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" U1 V22 U3 65 -Net 384 "/DDR Banks/M1_DQ14" "M1_DQ14" +Net 384 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" U3 63 U1 V21 Net 385 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" @@ -2326,42 +2350,42 @@ Net 386 "/DDR Banks/M1_DQ12" "M1_DQ12" Net 387 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" U3 59 U1 R22 -Net 388 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" - U3 57 +Net 388 "/DDR Banks/M1_DQ10" "M1_DQ10" U1 R20 + U3 57 Net 389 "/Non volatile memories/SD_DAT3" "SD_DAT3" J1 2 U1 C17 Net 390 "/Non volatile memories/SD_DAT2" "SD_DAT2" - J1 1 U1 A17 + J1 1 Net 391 "/FPGA Spartan6/SD_DAT1" "SD_DAT1" U1 B18 J1 8 Net 392 "/Non volatile memories/SD_DAT0" "SD_DAT0" - J1 7 U1 A18 + J1 7 Net 393 "/FPGA Spartan6/M1_A7" "M1_A7" - U1 E20 U3 38 -Net 394 "/FPGA Spartan6/M1_A6" "M1_A6" - U3 37 + U1 E20 +Net 394 "/DDR Banks/M1_A6" "M1_A6" U1 K19 + U3 37 Net 395 "/FPGA Spartan6/M1_A5" "M1_A5" - U1 K20 U3 36 + U1 K20 Net 396 "/FPGA Spartan6/M1_A4" "M1_A4" - U1 F20 U3 35 + U1 F20 Net 397 "/FPGA Spartan6/M1_A3" "M1_A3" - U3 32 U1 G20 + U3 32 Net 398 "/FPGA Spartan6/M1_A2" "M1_A2" U1 E22 U3 31 Net 399 "/DDR Banks/M1_A1" "M1_A1" - U1 F22 U3 30 + U1 F22 Net 400 "/FPGA Spartan6/M1_A0" "M1_A0" U3 29 U1 F21 @@ -2374,127 +2398,127 @@ Net 402 "/FPGA Spartan6/M0_A11" "M0_A11" Net 403 "/FPGA Spartan6/M0_A10" "M0_A10" U1 G4 U2 28 -Net 404 "/FPGA Spartan6/M0_A9" "M0_A9" +Net 404 "/DDR Banks/M0_A9" "M0_A9" U2 40 U1 E1 Net 405 "/DDR Banks/M0_A8" "M0_A8" - U1 E3 U2 39 + U1 E3 Net 406 "/FPGA Spartan6/M0_A7" "M0_A7" U1 H6 U2 38 -Net 407 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" +Net 407 "/DDR Banks/M1_DQ9" "M1_DQ9" U3 56 U1 P22 -Net 408 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" +Net 408 "/DDR Banks/M1_DQ8" "M1_DQ8" U3 54 U1 P21 -Net 409 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" +Net 409 "/DDR Banks/M1_DQ7" "M1_DQ7" U3 13 U1 K22 Net 410 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" - U1 K21 U3 11 -Net 411 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" + U1 K21 +Net 411 "/DDR Banks/M1_DQ5" "M1_DQ5" U3 10 U1 J22 -Net 412 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" +Net 412 "/DDR Banks/M1_DQ4" "M1_DQ4" U1 J20 U3 8 Net 413 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" - U3 7 U1 M22 -Net 414 "/DDR Banks/M1_DQ2" "M1_DQ2" + U3 7 +Net 414 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" U1 M21 U3 5 -Net 415 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" - U1 N22 +Net 415 "/DDR Banks/M1_DQ1" "M1_DQ1" U3 4 -Net 416 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" - U1 N20 + U1 N22 +Net 416 "/DDR Banks/M1_DQ0" "M1_DQ0" U3 2 + U1 N20 Net 417 "/FPGA Spartan6/M1_A12" "M1_A12" U1 D22 U3 42 Net 418 "/FPGA Spartan6/M1_A11" "M1_A11" U3 41 U1 F19 -Net 419 "/DDR Banks/M1_A10" "M1_A10" - U1 G19 +Net 419 "/FPGA Spartan6/M1_A10" "M1_A10" U3 28 -Net 420 "/FPGA Spartan6/M1_A9" "M1_A9" + U1 G19 +Net 420 "/DDR Banks/M1_A9" "M1_A9" U1 C22 U3 40 -Net 421 "/FPGA Spartan6/M1_A8" "M1_A8" - U1 C20 +Net 421 "/DDR Banks/M1_A8" "M1_A8" U3 39 + U1 C20 Net 422 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" - U2 7 U1 M1 -Net 423 "/DDR Banks/M0_DQ2" "M0_DQ2" + U2 7 +Net 423 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" U2 5 U1 M2 -Net 424 "/DDR Banks/M0_DQ1" "M0_DQ1" +Net 424 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" U1 N1 U2 4 Net 425 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" - U2 2 U1 N3 + U2 2 Net 426 "/DDR Banks/M0_A6" "M0_A6" - U1 J4 U2 37 + U1 J4 Net 427 "/DDR Banks/M0_A5" "M0_A5" - U2 36 U1 K3 + U2 36 Net 428 "/DDR Banks/M0_A4" "M0_A4" - U1 F3 U2 35 + U1 F3 Net 429 "/FPGA Spartan6/M0_A3" "M0_A3" U2 32 U1 K6 Net 430 "/FPGA Spartan6/M0_A2" "M0_A2" - U2 31 U1 H5 -Net 431 "/FPGA Spartan6/M0_A1" "M0_A1" + U2 31 +Net 431 "/DDR Banks/M0_A1" "M0_A1" U2 30 U1 H1 Net 432 "/DDR Banks/M0_A0" "M0_A0" U2 29 U1 H2 Net 433 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" - U2 65 U1 V1 + U2 65 Net 434 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" U2 63 U1 V2 -Net 435 "/DDR Banks/M0_DQ13" "M0_DQ13" - U2 62 +Net 435 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" U1 U1 + U2 62 Net 436 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" - U2 60 U1 U3 -Net 437 "/DDR Banks/M0_DQ11" "M0_DQ11" - U1 R1 + U2 60 +Net 437 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" U2 59 + U1 R1 Net 438 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" U1 R3 U2 57 -Net 439 "/DDR Banks/M0_DQ9" "M0_DQ9" +Net 439 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" U2 56 U1 P1 -Net 440 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" +Net 440 "/DDR Banks/M0_DQ8" "M0_DQ8" U2 54 U1 P2 Net 441 "/DDR Banks/M0_DQ7" "M0_DQ7" - U1 K1 U2 13 + U1 K1 Net 442 "/DDR Banks/M0_DQ6" "M0_DQ6" - U2 11 U1 K2 + U2 11 Net 443 "/DDR Banks/M0_DQ5" "M0_DQ5" - U2 10 U1 J1 -Net 444 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" + U2 10 +Net 444 "/DDR Banks/M0_DQ4" "M0_DQ4" U1 J3 U2 8 } diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 7ac2247..e4261c3 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 05:33:51 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:19:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001