From 980b8534545b679b9054bd0ea4063052cb4ef3cc Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Sun, 22 Aug 2010 13:35:28 -0500 Subject: [PATCH] debug+prog connector added --- kicad/xue-rnc/DBG_PRG.sch | 87 + kicad/xue-rnc/DRAM.sch | 68 +- kicad/xue-rnc/FPGA.sch | 3035 +++++++------- kicad/xue-rnc/NV_MEMORIES.sch | 4 +- kicad/xue-rnc/PSU.sch | 4 +- kicad/xue-rnc/USB.sch | 4 +- kicad/xue-rnc/eth_phy.sch | 4 +- kicad/xue-rnc/xue-rnc-cache.lib | 28 +- kicad/xue-rnc/xue-rnc.brd | 6951 ++++++++++++++++--------------- kicad/xue-rnc/xue-rnc.cmp | 242 +- kicad/xue-rnc/xue-rnc.net | 2206 +++++----- kicad/xue-rnc/xue-rnc.pro | 2 +- kicad/xue-rnc/xue-rnc.sch | 38 +- 13 files changed, 6769 insertions(+), 5904 deletions(-) create mode 100644 kicad/xue-rnc/DBG_PRG.sch diff --git a/kicad/xue-rnc/DBG_PRG.sch b/kicad/xue-rnc/DBG_PRG.sch new file mode 100644 index 0000000..294ce4b --- /dev/null +++ b/kicad/xue-rnc/DBG_PRG.sch @@ -0,0 +1,87 @@ +EESchema Schematic File Version 2 date Sun 22 Aug 2010 01:33:25 PM COT +LIBS:power +LIBS:r_pack2 +LIBS:v0402mhs03 +LIBS:usb-48204-0001 +LIBS:microsmd075f +LIBS:mic2550ayts +LIBS:rj45-48025 +LIBS:xue-nv +LIBS:xc6slx75fgg484 +LIBS:xc6slx45fgg484 +LIBS:micron_mobile_ddr +LIBS:micron_ddr_512Mb +LIBS:k8001 +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:pasives-connectors +LIBS:x25x64mb +LIBS:attiny +LIBS:PSU +LIBS:xue-rnc-cache +EELAYER 24 0 +EELAYER END +$Descr A4 11700 8267 +Sheet 2 8 +Title "" +Date "22 aug 2010" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L CONN_8X2 J6 +U 1 1 4C716CAB +P 2550 2350 +F 0 "J6" H 2550 2800 60 0000 C CNN +F 1 "CONN_8X2" V 2550 2350 50 0000 C CNN + 1 2550 2350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2150 2200 1900 2200 +Text HLabel 1900 2200 0 60 BiDi ~ 0 +FPGA_TDO +Text HLabel 1900 2300 0 60 BiDi ~ 0 +FPGA_TDI +Wire Wire Line + 2150 2300 1900 2300 +Wire Wire Line + 2150 2100 1900 2100 +Text HLabel 1900 2100 0 60 BiDi ~ 0 +FPGA_TMS +Text HLabel 1900 2000 0 60 BiDi ~ 0 +FPGA_TCK +Wire Wire Line + 2150 2000 1900 2000 +$EndSCHEMATC diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 653b7a3..4241197 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:19:33 AM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 01:33:25 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,7 +49,7 @@ LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 7 7 +Sheet 7 8 Title "" Date "22 aug 2010" Rev "" @@ -535,19 +535,19 @@ Entry Wire Line Entry Wire Line 10100 4400 10200 4500 $Comp -L GND #PWR059 +L GND #PWR062 U 1 1 4C699C4D P 9950 2100 -F 0 "#PWR059" H 9950 2100 30 0001 C CNN +F 0 "#PWR062" H 9950 2100 30 0001 C CNN F 1 "GND" H 9950 2030 30 0001 C CNN 1 9950 2100 1 0 0 -1 $EndComp $Comp -L GND #PWR060 +L GND #PWR063 U 1 1 4C699C48 P 4550 2150 -F 0 "#PWR060" H 4550 2150 30 0001 C CNN +F 0 "#PWR063" H 4550 2150 30 0001 C CNN F 1 "GND" H 4550 2080 30 0001 C CNN 1 4550 2150 1 0 0 -1 @@ -605,37 +605,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR061 +L GND #PWR064 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR061" H 6900 6200 30 0001 C CNN +F 0 "#PWR064" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR062 +L +2.5V #PWR065 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR062" H 6900 5750 20 0001 C CNN +F 0 "#PWR065" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR063 +L +2.5V #PWR066 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR063" H 1700 5750 20 0001 C CNN +F 0 "#PWR066" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR064 +L GND #PWR067 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR064" H 1700 6200 30 0001 C CNN +F 0 "#PWR067" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -651,19 +651,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR065 +L +2.5V #PWR068 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR065" H 3050 1700 20 0001 C CNN +F 0 "#PWR068" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR066 +L +2.5V #PWR069 U 1 1 4C61CFC6 P 8400 1700 -F 0 "#PWR066" H 8400 1650 20 0001 C CNN +F 0 "#PWR069" H 8400 1650 20 0001 C CNN F 1 "+2.5V" H 8400 1800 30 0000 C CNN 1 8400 1700 1 0 0 -1 @@ -729,37 +729,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR067 +L +2.5V #PWR070 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR067" H 8300 5700 20 0001 C CNN +F 0 "#PWR070" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR068 +L GND #PWR071 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR068" H 8300 6350 30 0001 C CNN +F 0 "#PWR071" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR069 +L GND #PWR072 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR069" H 3050 6350 30 0001 C CNN +F 0 "#PWR072" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR070 +L +2.5V #PWR073 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR070" H 3050 5700 20 0001 C CNN +F 0 "#PWR073" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -845,19 +845,19 @@ F 2 "0402" H 9950 1750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR071 +L +2.5V #PWR074 U 1 1 4C61CE2F P 9950 800 -F 0 "#PWR071" H 9950 750 20 0001 C CNN +F 0 "#PWR074" H 9950 750 20 0001 C CNN F 1 "+2.5V" H 9950 900 30 0000 C CNN 1 9950 800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR072 +L +2.5V #PWR075 U 1 1 4C61CDF1 P 4550 850 -F 0 "#PWR072" H 4550 800 20 0001 C CNN +F 0 "#PWR075" H 4550 800 20 0001 C CNN F 1 "+2.5V" H 4550 950 30 0000 C CNN 1 4550 850 1 0 0 -1 @@ -940,10 +940,10 @@ $EndComp Text HLabel 5000 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR073 +L GND #PWR076 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR073" H 3000 5200 30 0001 C CNN +F 0 "#PWR076" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1219,10 +1219,10 @@ Entry Wire Line Entry Wire Line 10100 3600 10200 3700 $Comp -L GND #PWR074 +L GND #PWR077 U 1 1 4C437C3F P 8350 5150 -F 0 "#PWR074" H 8350 5150 30 0001 C CNN +F 0 "#PWR077" H 8350 5150 30 0001 C CNN F 1 "GND" H 8350 5080 30 0001 C CNN 1 8350 5150 1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 5b799dc..7799177 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:19:33 AM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 01:33:25 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,7 +49,7 @@ LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A2 23400 16535 -Sheet 5 7 +Sheet 5 8 Title "" Date "22 aug 2010" Rev "" @@ -60,1456 +60,1539 @@ Comment3 "" Comment4 "" $EndDescr Wire Wire Line - 17650 7750 18000 7750 + 19500 10700 19800 10700 Wire Wire Line - 17650 8050 18000 8050 + 19800 10600 19500 10600 Wire Wire Line - 14000 8650 14250 8650 + 19500 10400 19800 10400 Wire Wire Line - 14000 7850 14250 7850 + 12500 10400 12250 10400 Wire Wire Line - 14250 7950 14000 7950 + 12250 10400 12250 10000 Wire Wire Line - 14250 7350 14150 7350 + 12250 10000 12100 10000 Wire Wire Line - 14200 7050 14250 7050 -Connection ~ 6000 12400 + 12500 10500 12100 10500 Wire Wire Line - 4600 12400 6400 12400 -Connection ~ 2700 12400 + 20350 10350 20350 10300 Wire Wire Line - 3100 12450 3100 12400 + 19500 10800 19700 10800 Wire Wire Line - 3100 12400 1650 12400 -Wire Wire Line - 3400 4100 3950 4100 -Wire Wire Line - 10200 5400 10700 5400 -Wire Wire Line - 6000 5200 5400 5200 -Wire Wire Line - 6000 5400 5400 5400 -Wire Wire Line - 6000 4300 5400 4300 -Wire Wire Line - 6000 4500 5400 4500 -Wire Wire Line - 6000 4700 5400 4700 -Wire Wire Line - 6000 4900 5400 4900 -Wire Wire Line - 6000 4200 5400 4200 -Wire Wire Line - 2800 4250 2900 4250 -Wire Wire Line - 2800 3950 2900 3950 -Wire Wire Line - 10200 5500 10700 5500 -Connection ~ 11100 4850 -Wire Wire Line - 11100 4750 11100 4850 -Wire Wire Line - 11150 4850 10600 4850 -Wire Wire Line - 10600 4850 10600 4800 -Wire Wire Line - 10600 4800 10200 4800 -Wire Wire Line - 10200 5200 10700 5200 -Wire Wire Line - 10700 5000 10200 5000 -Wire Wire Line - 10700 4500 10200 4500 -Wire Wire Line - 10700 4300 10200 4300 -Wire Wire Line - 10700 4100 10200 4100 -Wire Wire Line - 10700 3700 10200 3700 -Wire Wire Line - 10700 3500 10200 3500 -Wire Wire Line - 10700 3100 10200 3100 -Wire Wire Line - 3300 3250 3750 3250 -Wire Wire Line - 2800 2050 2900 2050 -Wire Wire Line - 2800 1950 2900 1950 -Wire Wire Line - 3300 1550 3800 1550 -Wire Wire Line - 3800 1850 3300 1850 -Wire Wire Line - 3750 1350 3300 1350 -Wire Wire Line - 2600 850 2900 850 -Wire Wire Line - 2600 750 2900 750 -Wire Wire Line - 3300 950 3750 950 -Wire Wire Line - 3300 750 3750 750 -Wire Bus Line - 2400 1350 2400 1250 -Wire Bus Line - 2400 1250 2300 1250 -Wire Wire Line - 3300 650 3750 650 -Wire Wire Line - 3300 850 3750 850 -Wire Wire Line - 2600 650 2900 650 -Wire Wire Line - 2600 950 2900 950 -Wire Wire Line - 2500 1450 2900 1450 -Wire Wire Line - 2900 1350 2500 1350 -Wire Wire Line - 2900 1850 2550 1850 -Wire Wire Line - 2550 1550 2900 1550 -Wire Wire Line - 3750 1450 3300 1450 -Wire Wire Line - 3750 1950 3300 1950 -Wire Wire Line - 2800 2150 2900 2150 -Wire Wire Line - 3750 2050 3300 2050 -Wire Wire Line - 3750 2150 3300 2150 -Wire Wire Line - 2900 2550 2450 2550 -Wire Wire Line - 2900 2750 2450 2750 -Wire Wire Line - 2900 2650 2450 2650 -Wire Wire Line - 2450 2450 2900 2450 -Wire Wire Line - 3300 2450 3750 2450 -Wire Wire Line - 3750 2650 3300 2650 -Wire Wire Line - 3750 2750 3300 2750 -Wire Wire Line - 3750 2550 3300 2550 -Wire Wire Line - 3750 3150 3300 3150 -Wire Wire Line - 3750 3350 3300 3350 -Wire Wire Line - 3750 1250 3300 1250 -Wire Wire Line - 3300 3050 3750 3050 -Wire Wire Line - 2450 3050 2900 3050 -Wire Wire Line - 2900 3350 2450 3350 -Wire Wire Line - 2900 3150 2450 3150 -Wire Wire Line - 2900 1250 2500 1250 -Wire Wire Line - 2450 3250 2900 3250 -Wire Wire Line - 6000 3800 5400 3800 -Wire Wire Line - 6000 3600 5400 3600 -Wire Bus Line - 12350 2300 12400 2300 -Wire Bus Line - 12400 2300 12400 3800 -Wire Wire Line - 16300 3950 16900 3950 -Wire Wire Line - 16300 3800 16900 3800 -Wire Wire Line - 16300 3500 16900 3500 -Wire Wire Line - 15750 3800 15800 3800 -Wire Wire Line - 15750 3500 15800 3500 -Wire Wire Line - 17050 5200 17600 5200 -Wire Wire Line - 22550 3500 22000 3500 -Wire Wire Line - 22550 3200 22000 3200 -Wire Wire Line - 22000 4300 22500 4300 -Wire Wire Line - 22000 4500 22500 4500 -Wire Wire Line - 22000 5200 22500 5200 -Wire Wire Line - 22550 3900 22000 3900 -Wire Wire Line - 17600 4800 17150 4800 -Connection ~ 16800 4550 -Wire Wire Line - 16800 4400 16800 4550 -Wire Wire Line - 17600 4500 16900 4500 -Wire Wire Line - 16900 4500 16900 4550 -Wire Wire Line - 16900 4550 16200 4550 -Connection ~ 16300 4300 -Wire Wire Line - 17150 4300 17600 4300 -Wire Wire Line - 17600 3900 17150 3900 -Wire Wire Line - 13800 3750 14250 3750 -Wire Wire Line - 14250 1750 13850 1750 -Wire Wire Line - 17600 3300 17150 3300 -Wire Wire Line - 17600 3100 17150 3100 -Wire Wire Line - 14250 3650 13800 3650 -Wire Wire Line - 14250 3850 13800 3850 -Wire Wire Line - 13800 3550 14250 3550 -Wire Wire Line - 14650 3550 15100 3550 -Wire Wire Line - 15100 1750 14650 1750 -Wire Wire Line - 15100 3850 14650 3850 -Wire Wire Line - 15100 3650 14650 3650 -Wire Wire Line - 15100 3050 14650 3050 -Wire Wire Line - 15100 3250 14650 3250 -Wire Wire Line - 15100 3150 14650 3150 -Wire Wire Line - 14650 2950 15100 2950 -Wire Wire Line - 13800 2950 14250 2950 -Wire Wire Line - 14250 3150 13800 3150 -Wire Wire Line - 14250 3250 13800 3250 -Wire Wire Line - 14250 3050 13800 3050 -Wire Wire Line - 15100 2650 14650 2650 -Wire Wire Line - 15100 2550 14650 2550 -Wire Wire Line - 14150 2650 14250 2650 -Wire Wire Line - 17150 3600 17600 3600 -Wire Wire Line - 15100 2450 14650 2450 -Wire Wire Line - 17600 3000 17150 3000 -Wire Wire Line - 17150 4100 17600 4100 -Wire Wire Line - 17600 5000 17050 5000 -Wire Wire Line - 15100 1950 14650 1950 -Wire Wire Line - 13900 2050 14250 2050 -Wire Wire Line - 14250 2350 13900 2350 -Wire Wire Line - 14250 1850 13850 1850 -Wire Wire Line - 13850 1950 14250 1950 -Wire Wire Line - 13950 1450 14250 1450 -Wire Wire Line - 13950 1150 14250 1150 -Wire Wire Line - 14650 1350 15100 1350 -Wire Wire Line - 14650 1150 15100 1150 -Wire Wire Line - 16400 12650 16400 12400 -Wire Wire Line - 1650 7800 2250 7800 -Wire Wire Line - 1650 7700 2250 7700 -Wire Bus Line - 1450 7300 1550 7300 -Wire Bus Line - 1550 7300 1550 7700 -Wire Wire Line - 2700 7200 3300 7200 -Wire Wire Line - 2700 9000 3300 9000 -Wire Wire Line - 3300 7000 2600 7000 -Wire Wire Line - 18000 7650 17650 7650 -Wire Wire Line - 18000 7450 17650 7450 -Wire Wire Line - 18000 7250 17650 7250 -Connection ~ 5650 12900 -Wire Wire Line - 6000 12850 6000 12900 -Wire Wire Line - 6000 12900 4600 12900 -Connection ~ 4600 12900 -Wire Wire Line - 4600 12950 4600 12850 -Connection ~ 5300 12900 -Wire Wire Line - 5300 12900 5300 12850 -Connection ~ 4600 12400 -Wire Wire Line - 4600 12350 4600 12450 -Connection ~ 5300 12400 -Wire Wire Line - 5300 12400 5300 12450 -Wire Wire Line - 5650 12400 5650 12450 -Wire Wire Line - 4950 12400 4950 12450 -Connection ~ 4950 12400 -Wire Wire Line - 5650 12900 5650 12850 -Wire Wire Line - 4950 12850 4950 12900 -Connection ~ 4950 12900 -Wire Wire Line - 6000 12450 6000 12400 -Connection ~ 5650 12400 -Connection ~ 6000 13900 -Wire Wire Line - 6350 13850 6350 13900 -Wire Wire Line - 6350 13900 4600 13900 -Connection ~ 5650 13900 -Wire Wire Line - 6000 13900 6000 13850 -Connection ~ 4600 13900 -Wire Wire Line - 4600 13950 4600 13850 -Connection ~ 5300 13900 -Wire Wire Line - 5300 13900 5300 13850 -Connection ~ 4600 13400 -Wire Wire Line - 4600 13350 4600 13450 -Connection ~ 5300 13400 -Wire Wire Line - 5300 13400 5300 13450 -Wire Wire Line - 5650 13400 5650 13450 -Wire Wire Line - 4950 13450 4950 13400 -Connection ~ 4950 13400 -Wire Wire Line - 5650 13900 5650 13850 -Wire Wire Line - 4950 13850 4950 13900 -Connection ~ 4950 13900 -Wire Wire Line - 6000 13400 6000 13450 -Connection ~ 5650 13400 -Connection ~ 5650 14850 -Wire Wire Line - 6000 14800 6000 14850 -Wire Wire Line - 6000 14850 4600 14850 -Connection ~ 4600 14850 -Wire Wire Line - 4600 14900 4600 14800 -Connection ~ 5300 14850 -Wire Wire Line - 5300 14850 5300 14800 -Connection ~ 4600 14350 -Wire Wire Line - 4600 14300 4600 14400 -Connection ~ 5300 14350 -Wire Wire Line - 5300 14350 5300 14400 -Wire Wire Line - 5650 14400 5650 14350 -Wire Wire Line - 4950 14350 4950 14400 -Connection ~ 4950 14350 -Wire Wire Line - 5650 14850 5650 14800 -Wire Wire Line - 4950 14800 4950 14850 -Connection ~ 4950 14850 -Connection ~ 1650 14850 -Wire Wire Line - 1650 14900 1650 14800 -Connection ~ 2350 14850 -Wire Wire Line - 2350 14850 2350 14800 -Connection ~ 1650 14350 -Wire Wire Line - 1650 14300 1650 14400 -Connection ~ 2350 14350 -Wire Wire Line - 2350 14350 2350 14400 -Wire Wire Line - 1650 14350 2700 14350 -Wire Wire Line - 2700 14350 2700 14400 -Wire Wire Line - 2000 14350 2000 14400 -Connection ~ 2000 14350 -Wire Wire Line - 1650 14850 2700 14850 -Wire Wire Line - 2700 14850 2700 14800 -Wire Wire Line - 2000 14850 2000 14800 -Connection ~ 2000 14850 -Connection ~ 3350 13950 -Wire Wire Line - 3350 13950 3350 13900 -Connection ~ 2700 13950 -Wire Wire Line - 2700 13950 2700 13900 -Connection ~ 1650 13950 -Connection ~ 2000 13950 -Wire Wire Line - 1650 13950 3700 13950 -Connection ~ 2700 13450 -Wire Wire Line - 2700 13450 2700 13500 -Connection ~ 3350 13450 -Wire Wire Line - 3350 13450 3350 13500 -Connection ~ 2000 13450 -Wire Wire Line - 2350 13450 2350 13500 -Wire Wire Line - 1650 14000 1650 13900 -Wire Wire Line - 1650 13400 1650 13500 -Wire Wire Line - 2000 13500 2000 13450 -Wire Wire Line - 2000 13950 2000 13900 -Connection ~ 1650 12900 -Wire Wire Line - 1650 12950 1650 12850 -Connection ~ 2350 12900 -Wire Wire Line - 2350 12900 2350 12850 -Connection ~ 1650 12400 -Wire Wire Line - 1650 12350 1650 12450 -Connection ~ 2350 12400 -Wire Wire Line - 2350 12400 2350 12450 -Wire Bus Line - 19450 8050 19150 8050 -Wire Wire Line - 18450 8750 19050 8750 -Wire Wire Line - 19050 8550 18450 8550 -Wire Wire Line - 18450 8850 19050 8850 -Wire Wire Line - 18450 8450 19050 8450 -Wire Wire Line - 18450 8250 19050 8250 -Wire Wire Line - 19050 8150 18450 8150 -Wire Wire Line - 18450 8350 19050 8350 -Connection ~ 15900 6200 -Wire Wire Line - 15900 6200 15900 6100 -Wire Wire Line - 16500 9850 16500 10000 -Wire Bus Line - 18450 6750 18350 6750 -Wire Wire Line - 17650 7050 18250 7050 -Wire Wire Line - 18250 6850 17650 6850 -Wire Wire Line - 17650 6750 17800 6750 -Wire Bus Line - 13650 1750 13750 1750 -Wire Bus Line - 13750 1750 13750 1850 -Wire Wire Line - 1450 5700 1600 5700 -Wire Wire Line - 12750 7950 11450 7950 -Wire Wire Line - 12750 7750 11450 7750 -Wire Wire Line - 14150 7550 14250 7550 -Wire Wire Line - 13450 6550 12150 6550 -Wire Wire Line - 13450 6350 12150 6350 -Wire Wire Line - 14200 6750 14250 6750 -Wire Wire Line - 22000 1800 22100 1800 -Wire Wire Line - 22000 1600 22100 1600 -Wire Wire Line - 22100 1400 22000 1400 -Wire Bus Line - 11350 7900 11350 7500 -Wire Bus Line - 11350 7500 11250 7500 -Wire Bus Line - 11950 6100 12050 6100 -Wire Wire Line - 12950 3600 12500 3600 -Wire Wire Line - 12950 3800 12500 3800 -Wire Wire Line - 12950 3900 12500 3900 -Wire Wire Line - 12950 3700 12500 3700 -Wire Wire Line - 12950 3300 12500 3300 -Wire Wire Line - 12950 3500 12500 3500 -Wire Wire Line - 12950 3400 12500 3400 -Wire Wire Line - 12950 3200 12500 3200 -Wire Wire Line - 12950 2600 12500 2600 -Wire Wire Line - 12950 2400 12500 2400 -Wire Wire Line - 12950 2500 12500 2500 -Wire Wire Line - 12950 2700 12500 2700 -Wire Wire Line - 12950 2900 12500 2900 -Wire Wire Line - 12950 3100 12500 3100 -Wire Wire Line - 12950 2800 12500 2800 -Wire Wire Line - 12950 3000 12500 3000 -Wire Bus Line - 1350 4900 1350 3300 -Wire Bus Line - 1350 3300 1250 3300 -Wire Wire Line - 12950 1550 12550 1550 -Wire Wire Line - 12950 1650 12550 1650 -Wire Wire Line - 12950 1850 12550 1850 -Wire Wire Line - 12950 2050 12550 2050 -Wire Wire Line - 12950 950 12550 950 -Wire Wire Line - 12950 1050 12550 1050 -Wire Wire Line - 12950 1350 12550 1350 -Wire Wire Line - 12950 1250 12550 1250 -Wire Wire Line - 12950 1750 12550 1750 -Wire Wire Line - 12950 1150 12550 1150 -Wire Wire Line - 12950 1450 12550 1450 -Wire Wire Line - 12950 1950 12550 1950 -Wire Wire Line - 12950 2150 12550 2150 -Connection ~ 5700 6350 -Wire Wire Line - 5700 6400 5700 6350 -Connection ~ 5500 6350 -Wire Wire Line - 5500 6350 5500 6400 -Connection ~ 5300 6350 -Connection ~ 5100 6350 -Wire Wire Line - 5100 6350 5100 6400 -Connection ~ 4900 6350 -Wire Wire Line - 4900 6350 4900 6400 -Wire Wire Line - 5800 6400 5800 6350 -Wire Wire Line - 5800 6350 4800 6350 -Connection ~ 15850 6200 -Wire Wire Line - 15850 6200 15850 6250 -Connection ~ 15650 6200 -Wire Wire Line - 15650 6200 15650 6250 -Connection ~ 16050 6200 -Wire Wire Line - 16050 6200 16050 6250 -Connection ~ 16250 6200 -Wire Wire Line - 16250 6200 16250 6250 -Wire Wire Line - 19700 800 19700 650 -Connection ~ 20000 750 -Wire Wire Line - 20000 750 20000 800 -Connection ~ 19800 750 -Wire Wire Line - 19800 750 19800 800 -Connection ~ 19600 750 -Wire Wire Line - 19600 750 19600 800 -Connection ~ 19400 750 -Wire Wire Line - 19400 800 19400 750 -Connection ~ 8000 750 -Wire Wire Line - 8000 750 8000 800 -Connection ~ 7800 750 -Wire Wire Line - 7800 750 7800 800 -Connection ~ 8500 750 -Wire Wire Line - 8500 750 8500 800 -Connection ~ 8300 750 -Wire Wire Line - 8300 750 8300 800 -Wire Wire Line - 8100 800 8100 650 -Connection ~ 8100 750 -Connection ~ 18800 12500 -Wire Wire Line - 18800 12500 18800 12400 -Connection ~ 18600 12500 -Wire Wire Line - 18600 12500 18600 12400 -Connection ~ 18400 12500 -Wire Wire Line - 18400 12500 18400 12400 -Connection ~ 18200 12500 -Wire Wire Line - 18200 12500 18200 12400 -Wire Wire Line - 17900 12500 17900 12400 -Connection ~ 18000 12500 -Connection ~ 17800 12500 -Wire Wire Line - 17800 12500 17800 12400 -Connection ~ 17200 12500 -Wire Wire Line - 17200 12500 17200 12400 -Connection ~ 17000 12500 -Wire Wire Line - 17000 12500 17000 12400 -Connection ~ 16800 12500 -Wire Wire Line - 16800 12500 16800 12400 -Connection ~ 16600 12500 -Wire Wire Line - 16600 12500 16600 12400 -Connection ~ 16400 12500 -Connection ~ 16200 12500 -Wire Wire Line - 16200 12500 16200 12400 -Connection ~ 16000 12500 -Wire Wire Line - 16000 12500 16000 12400 -Connection ~ 17500 12500 -Wire Wire Line - 17500 12500 17500 12400 -Connection ~ 17700 12500 -Wire Wire Line - 17700 12500 17700 12400 -Connection ~ 15700 12500 -Wire Wire Line - 15700 12500 15700 12400 -Connection ~ 15500 12500 -Wire Wire Line - 15500 12500 15500 12400 -Connection ~ 15300 12500 -Wire Wire Line - 15300 12500 15300 12400 -Connection ~ 15100 12500 -Wire Wire Line - 15100 12500 15100 12400 -Connection ~ 15000 12500 -Wire Wire Line - 15000 12500 15000 12400 -Connection ~ 14800 12500 -Wire Wire Line - 14800 12500 14800 12400 -Connection ~ 14600 12500 -Wire Wire Line - 14600 12500 14600 12400 -Connection ~ 14400 12500 -Wire Wire Line - 14400 12500 14400 12400 -Connection ~ 14200 12500 -Wire Wire Line - 14200 12500 14200 12400 -Connection ~ 14000 12500 -Wire Wire Line - 14000 12500 14000 12400 -Connection ~ 13800 12500 -Wire Wire Line - 13800 12500 13800 12400 -Connection ~ 13600 12500 -Wire Wire Line - 13600 12500 13600 12400 -Connection ~ 13400 12500 -Wire Wire Line - 13400 12500 13400 12400 -Connection ~ 13200 12500 -Wire Wire Line - 13200 12400 13200 12500 -Connection ~ 15200 9950 -Wire Wire Line - 15200 9950 15200 10000 -Connection ~ 15400 9950 -Wire Wire Line - 15400 9950 15400 10000 -Connection ~ 15100 9950 -Wire Wire Line - 15100 9950 15100 10000 -Connection ~ 14900 9950 -Wire Wire Line - 14900 9950 14900 10000 -Connection ~ 14700 9950 -Wire Wire Line - 14700 9950 14700 10000 -Connection ~ 14500 9950 -Wire Wire Line - 14500 9950 14500 10000 -Connection ~ 17400 9950 -Wire Wire Line - 17400 9950 17400 10000 -Connection ~ 17200 9950 -Wire Wire Line - 17200 9950 17200 10000 -Connection ~ 17000 9950 -Wire Wire Line - 17000 9950 17000 10000 -Connection ~ 16800 9950 -Wire Wire Line - 16800 9950 16800 10000 -Connection ~ 16600 9950 -Wire Wire Line - 16600 9950 16600 10000 -Connection ~ 16400 9950 -Wire Wire Line - 16400 9950 16400 10000 -Connection ~ 16200 9950 -Wire Wire Line - 16200 9950 16200 10000 -Connection ~ 16000 9950 -Wire Wire Line - 16000 9950 16000 10000 -Connection ~ 15800 9950 -Wire Wire Line - 15800 9950 15800 10000 -Wire Wire Line - 17600 10000 17600 9950 -Wire Wire Line - 17600 9950 15700 9950 -Wire Wire Line - 15700 9950 15700 10000 -Wire Wire Line - 14300 10000 14300 9950 -Wire Wire Line - 14300 9950 15600 9950 -Wire Wire Line - 15600 9950 15600 10000 -Wire Wire Line - 17500 9950 17500 10000 -Connection ~ 17500 9950 -Wire Wire Line - 15900 9950 15900 10000 -Connection ~ 15900 9950 -Wire Wire Line - 16100 9950 16100 10000 -Connection ~ 16100 9950 -Wire Wire Line - 16300 9950 16300 10000 -Connection ~ 16300 9950 -Connection ~ 16500 9950 -Wire Wire Line - 16700 9950 16700 10000 -Connection ~ 16700 9950 -Wire Wire Line - 16900 9950 16900 10000 -Connection ~ 16900 9950 -Wire Wire Line - 17100 9950 17100 10000 -Connection ~ 17100 9950 -Wire Wire Line - 17300 9950 17300 10000 -Connection ~ 17300 9950 -Wire Wire Line - 14400 9950 14400 10000 -Connection ~ 14400 9950 -Wire Wire Line - 14600 9950 14600 10000 -Connection ~ 14600 9950 -Wire Wire Line - 14800 9950 14800 10000 -Connection ~ 14800 9950 -Connection ~ 15000 9950 -Wire Wire Line - 15500 10000 15500 9950 -Connection ~ 15500 9950 -Wire Wire Line - 15300 9950 15300 10000 -Connection ~ 15300 9950 -Wire Wire Line - 13100 12400 13100 12500 -Wire Wire Line - 13100 12500 18900 12500 -Wire Wire Line - 18900 12500 18900 12400 -Wire Wire Line - 13300 12500 13300 12400 -Connection ~ 13300 12500 -Wire Wire Line - 13500 12500 13500 12400 -Connection ~ 13500 12500 -Wire Wire Line - 13700 12500 13700 12400 -Connection ~ 13700 12500 -Wire Wire Line - 13900 12500 13900 12400 -Connection ~ 13900 12500 -Wire Wire Line - 14100 12500 14100 12400 -Connection ~ 14100 12500 -Wire Wire Line - 14300 12500 14300 12400 -Connection ~ 14300 12500 -Wire Wire Line - 14500 12500 14500 12400 -Connection ~ 14500 12500 -Wire Wire Line - 14700 12500 14700 12400 -Connection ~ 14700 12500 -Wire Wire Line - 14900 12500 14900 12400 -Connection ~ 14900 12500 -Connection ~ 15900 12500 -Wire Wire Line - 15200 12500 15200 12400 -Connection ~ 15200 12500 -Wire Wire Line - 15400 12500 15400 12400 -Connection ~ 15400 12500 -Wire Wire Line - 15600 12500 15600 12400 -Connection ~ 15600 12500 -Wire Wire Line - 15800 12500 15800 12400 -Connection ~ 15800 12500 -Wire Wire Line - 17600 12500 17600 12400 -Connection ~ 17600 12500 -Wire Wire Line - 17400 12500 17400 12400 -Connection ~ 17400 12500 -Wire Wire Line - 16100 12500 16100 12400 -Connection ~ 16100 12500 -Wire Wire Line - 16300 12500 16300 12400 -Connection ~ 16300 12500 -Wire Wire Line - 16500 12500 16500 12400 -Connection ~ 16500 12500 -Wire Wire Line - 16700 12500 16700 12400 -Connection ~ 16700 12500 -Wire Wire Line - 16900 12500 16900 12400 -Connection ~ 16900 12500 -Wire Wire Line - 17100 12500 17100 12400 -Connection ~ 17100 12500 -Wire Wire Line - 17300 12500 17300 12400 -Connection ~ 17300 12500 -Connection ~ 17900 12500 -Wire Wire Line - 18000 12500 18000 12400 -Wire Wire Line - 18100 12500 18100 12400 -Connection ~ 18100 12500 -Wire Wire Line - 18300 12500 18300 12400 -Connection ~ 18300 12500 -Wire Wire Line - 18500 12500 18500 12400 -Connection ~ 18500 12500 -Wire Wire Line - 18700 12500 18700 12400 -Connection ~ 18700 12500 -Wire Wire Line - 7600 800 7600 750 -Wire Wire Line - 7600 750 8600 750 -Wire Wire Line - 8600 750 8600 800 -Wire Wire Line - 8200 750 8200 800 -Connection ~ 8200 750 -Wire Wire Line - 8400 750 8400 800 -Connection ~ 8400 750 -Wire Wire Line - 7700 750 7700 800 -Connection ~ 7700 750 -Wire Wire Line - 7900 750 7900 800 -Connection ~ 7900 750 -Wire Wire Line - 19300 800 19300 750 -Wire Wire Line - 19300 750 20200 750 -Wire Wire Line - 20200 750 20200 800 -Wire Wire Line - 19500 750 19500 800 -Connection ~ 19500 750 -Connection ~ 19700 750 -Wire Wire Line - 19900 750 19900 800 -Connection ~ 19900 750 -Wire Wire Line - 20100 800 20100 750 -Connection ~ 20100 750 -Wire Wire Line - 15450 6250 15450 6200 -Wire Wire Line - 15450 6200 16350 6200 -Wire Wire Line - 16350 6200 16350 6250 -Wire Wire Line - 16150 6200 16150 6250 -Connection ~ 16150 6200 -Wire Wire Line - 15550 6200 15550 6250 -Connection ~ 15550 6200 -Wire Wire Line - 15750 6200 15750 6250 -Connection ~ 15750 6200 -Wire Wire Line - 15950 6200 15950 6250 -Connection ~ 15950 6200 -Wire Wire Line - 4800 6350 4800 6400 -Wire Wire Line - 5000 6350 5000 6400 -Connection ~ 5000 6350 -Wire Wire Line - 5200 6350 5200 6400 -Connection ~ 5200 6350 -Wire Wire Line - 5400 6350 5400 6400 -Connection ~ 5400 6350 -Wire Wire Line - 5600 6350 5600 6400 -Connection ~ 5600 6350 -Wire Wire Line - 17550 3500 17150 3500 -Wire Bus Line - 12450 2050 12450 800 -Wire Bus Line - 1150 2550 1150 1300 -Wire Wire Line - 1650 2650 1250 2650 -Wire Wire Line - 1650 2450 1250 2450 -Wire Wire Line - 1650 1950 1250 1950 -Wire Wire Line - 1650 1650 1250 1650 -Wire Wire Line - 1650 2250 1250 2250 -Wire Wire Line - 1650 1750 1250 1750 -Wire Wire Line - 1650 1850 1250 1850 -Wire Wire Line - 1650 1550 1250 1550 -Wire Wire Line - 1650 1450 1250 1450 -Wire Wire Line - 1650 2550 1250 2550 -Wire Wire Line - 1650 2350 1250 2350 -Wire Wire Line - 1650 2150 1250 2150 -Wire Wire Line - 1650 2050 1250 2050 -Wire Wire Line - 1900 4100 1450 4100 -Wire Wire Line - 1900 3900 1450 3900 -Wire Wire Line - 1900 4200 1450 4200 -Wire Wire Line - 1900 4000 1450 4000 -Wire Wire Line - 1900 3800 1450 3800 -Wire Wire Line - 1900 3600 1450 3600 -Wire Wire Line - 1900 3500 1450 3500 -Wire Wire Line - 1900 3700 1450 3700 -Wire Wire Line - 1900 4300 1450 4300 -Wire Wire Line - 1900 4500 1450 4500 -Wire Wire Line - 1900 4600 1450 4600 -Wire Wire Line - 1900 4400 1450 4400 -Wire Wire Line - 1900 4800 1450 4800 -Wire Wire Line - 1900 5000 1450 5000 -Wire Wire Line - 1900 4900 1450 4900 -Wire Wire Line - 1900 4700 1450 4700 -Wire Wire Line - 22450 4100 22000 4100 -Wire Bus Line - 12050 6100 12050 6500 -Wire Wire Line - 22000 1500 22100 1500 -Wire Wire Line - 22000 1700 22100 1700 -Wire Wire Line - 14200 8750 14250 8750 -Wire Wire Line - 13450 6250 12150 6250 -Wire Wire Line - 13450 6450 12150 6450 -Wire Wire Line - 14150 7650 14250 7650 -Wire Wire Line - 12750 7650 11450 7650 -Wire Wire Line - 12750 7850 11450 7850 -Wire Wire Line - 1600 5700 1600 5950 -Wire Wire Line - 17650 6650 17800 6650 -Wire Wire Line - 17650 6950 18250 6950 -Wire Wire Line - 17650 7150 18250 7150 -Wire Bus Line - 18350 6750 18350 7050 -Wire Wire Line - 15000 9850 15000 10000 -Wire Bus Line - 19150 8050 19150 8750 -Wire Wire Line - 2700 12400 2700 12450 -Wire Wire Line - 2000 12450 2000 12400 -Connection ~ 2000 12400 -Wire Wire Line - 2700 12850 2700 12900 -Wire Wire Line - 2000 12900 2000 12850 -Connection ~ 2000 12900 -Connection ~ 1650 13450 -Wire Wire Line - 1650 13450 3700 13450 -Wire Wire Line - 3700 13450 3700 13500 -Connection ~ 2350 13450 -Wire Wire Line - 3050 13450 3050 13500 -Connection ~ 3050 13450 -Wire Wire Line - 3700 13950 3700 13900 -Wire Wire Line - 2350 13950 2350 13900 -Connection ~ 2350 13950 -Wire Wire Line - 3050 13950 3050 13900 -Connection ~ 3050 13950 -Wire Wire Line - 6000 14400 6000 14350 -Wire Wire Line - 6000 14350 4600 14350 -Connection ~ 5650 14350 -Wire Wire Line - 4600 13400 6350 13400 -Wire Wire Line - 6350 13400 6350 13450 -Connection ~ 6000 13400 -Wire Notes Line - 6750 15000 6750 12200 -Wire Notes Line - 6750 15000 1350 15000 -Wire Notes Line - 1350 15000 1350 12200 -Wire Notes Line - 1350 12200 6750 12200 -Wire Wire Line - 17650 7350 18000 7350 -Wire Wire Line - 17650 7550 18000 7550 -Wire Wire Line - 18000 7950 17650 7950 -Wire Wire Line - 7300 6900 7900 6900 -Wire Wire Line - 2700 9100 3300 9100 -Wire Wire Line - 2700 7300 3300 7300 -Wire Wire Line - 1650 7600 2250 7600 -Wire Wire Line - 1650 7500 2250 7500 -Wire Wire Line - 15900 12500 15900 12400 -Wire Wire Line - 5300 6400 5300 6250 -Wire Wire Line - 14650 1250 15100 1250 -Wire Wire Line - 14650 1450 15100 1450 -Wire Wire Line - 13950 1250 14250 1250 -Wire Wire Line - 13950 1350 14250 1350 -Wire Wire Line - 15100 1850 14650 1850 -Wire Wire Line - 15150 2350 14650 2350 -Wire Wire Line - 17600 5100 17050 5100 -Wire Wire Line - 14650 2050 15150 2050 -Wire Wire Line - 17150 4000 17600 4000 -Wire Wire Line - 15850 2950 15400 2950 -Wire Wire Line - 15850 3150 15400 3150 -Wire Wire Line - 15850 3050 15400 3050 -Wire Wire Line - 15400 2850 15850 2850 -Wire Wire Line - 16250 2850 16700 2850 -Wire Wire Line - 16700 3050 16250 3050 -Wire Wire Line - 16700 3150 16250 3150 -Wire Wire Line - 16700 2950 16250 2950 -Wire Wire Line - 15400 2250 15850 2250 -Wire Wire Line - 15850 2450 15400 2450 -Wire Wire Line - 15850 2550 15400 2550 -Wire Wire Line - 15850 2350 15400 2350 -Wire Wire Line - 16700 2350 16250 2350 -Wire Wire Line - 16700 2550 16250 2550 -Wire Wire Line - 16700 2450 16250 2450 -Wire Wire Line - 16250 2250 16700 2250 -Wire Wire Line - 14150 2450 14250 2450 -Wire Wire Line - 14150 2550 14250 2550 -Wire Wire Line - 17600 2900 17150 2900 -Wire Wire Line - 17600 3200 17150 3200 -Wire Wire Line - 17600 3400 17150 3400 -Wire Wire Line - 14650 3750 15100 3750 -Wire Wire Line - 17600 3800 17150 3800 -Wire Wire Line - 17600 4200 17150 4200 -Wire Wire Line - 17600 4400 16900 4400 -Wire Wire Line - 16900 4400 16900 4300 -Wire Wire Line - 16900 4300 16200 4300 -Wire Wire Line - 16300 4400 16300 4300 -Wire Wire Line - 17600 4600 17150 4600 -Wire Wire Line - 17600 4900 17150 4900 -Wire Wire Line - 16250 1100 16700 1100 -Wire Wire Line - 16700 1300 16250 1300 -Wire Wire Line - 16700 1400 16250 1400 -Wire Wire Line - 16700 1200 16250 1200 -Wire Wire Line - 15850 1200 15400 1200 -Wire Wire Line - 15850 1400 15400 1400 -Wire Wire Line - 15850 1300 15400 1300 -Wire Wire Line - 15400 1100 15850 1100 -Wire Wire Line - 22550 3800 22000 3800 -Wire Wire Line - 22500 4000 22000 4000 -Wire Wire Line - 22000 5100 22500 5100 -Wire Wire Line - 22000 5000 22500 5000 -Wire Wire Line - 22000 4900 22500 4900 -Wire Wire Line - 22000 4800 22500 4800 -Wire Wire Line - 22000 4700 22500 4700 -Wire Wire Line - 22000 4200 22500 4200 -Wire Wire Line - 22000 4400 22500 4400 -Wire Wire Line - 15400 1700 15850 1700 -Wire Wire Line - 15850 1900 15400 1900 -Wire Wire Line - 15850 2000 15400 2000 -Wire Wire Line - 15850 1800 15400 1800 -Wire Wire Line - 16700 1800 16250 1800 -Wire Wire Line - 16700 2000 16250 2000 -Wire Wire Line - 16700 1900 16250 1900 -Wire Wire Line - 16250 1700 16700 1700 -Wire Wire Line - 22550 3300 22000 3300 -Wire Wire Line - 22000 3400 22550 3400 -Wire Wire Line - 22550 3700 22000 3700 -Wire Wire Line - 15750 3650 15800 3650 -Wire Wire Line - 16300 3650 16900 3650 -Wire Wire Line - 15750 3950 15800 3950 -Wire Wire Line - 17150 2400 17600 2400 -Wire Bus Line - 12450 800 12400 800 -Wire Wire Line - 4100 1000 4550 1000 -Wire Wire Line - 4550 1200 4100 1200 -Wire Wire Line - 4550 1300 4100 1300 -Wire Wire Line - 4550 1100 4100 1100 -Wire Wire Line - 5400 1100 4950 1100 -Wire Wire Line - 5400 1300 4950 1300 -Wire Wire Line - 5400 1200 4950 1200 -Wire Wire Line - 4950 1000 5400 1000 -Wire Wire Line - 4950 1550 5400 1550 -Wire Wire Line - 5400 1750 4950 1750 -Wire Wire Line - 5400 1850 4950 1850 -Wire Wire Line - 5400 1650 4950 1650 -Wire Wire Line - 4550 1650 4100 1650 -Wire Wire Line - 4550 1850 4100 1850 -Wire Wire Line - 4550 1750 4100 1750 -Wire Wire Line - 4100 1550 4550 1550 -Wire Wire Line - 4950 2100 5400 2100 -Wire Wire Line - 5400 2300 4950 2300 -Wire Wire Line - 5400 2400 4950 2400 -Wire Wire Line - 5400 2200 4950 2200 -Wire Wire Line - 4550 2200 4100 2200 -Wire Wire Line - 4550 2400 4100 2400 -Wire Wire Line - 4550 2300 4100 2300 -Wire Wire Line - 4100 2100 4550 2100 -Wire Wire Line - 5400 2750 4950 2750 -Wire Wire Line - 5400 2950 4950 2950 -Wire Wire Line - 5400 2850 4950 2850 -Wire Wire Line - 4950 2650 5400 2650 -Wire Wire Line - 4100 2650 4550 2650 -Wire Wire Line - 4550 2850 4100 2850 -Wire Wire Line - 4550 2950 4100 2950 -Wire Wire Line - 4550 2750 4100 2750 -Wire Wire Line - 6000 3700 5400 3700 -Wire Wire Line - 6000 3900 5400 3900 -Wire Bus Line - 1150 1300 1100 1300 -Wire Wire Line - 10700 3300 10200 3300 -Wire Wire Line - 10700 3600 10200 3600 -Wire Wire Line - 10700 3800 10200 3800 -Wire Wire Line - 10700 4200 10200 4200 -Wire Wire Line - 10700 4400 10200 4400 -Wire Wire Line - 10700 4600 10200 4600 -Wire Wire Line - 10700 5100 10200 5100 -Wire Wire Line - 10200 4700 10600 4700 -Wire Wire Line - 11150 4650 10600 4650 -Wire Wire Line - 10600 4650 10600 4750 -Connection ~ 10600 4700 -Wire Wire Line - 10200 5300 10750 5300 -Wire Wire Line - 10200 4000 10700 4000 -Wire Wire Line - 2800 4100 2900 4100 -Wire Wire Line - 6000 4000 5400 4000 -Wire Wire Line - 6000 5000 5400 5000 -Wire Wire Line - 6000 4800 5400 4800 -Wire Wire Line - 6000 4600 5400 4600 -Wire Wire Line - 6000 4400 5400 4400 -Wire Wire Line - 6000 5500 5400 5500 -Wire Wire Line - 6000 5300 5400 5300 -Wire Wire Line - 10200 5600 10700 5600 -Wire Wire Line - 10200 3400 10700 3400 -Wire Wire Line - 3400 3950 3950 3950 -Wire Wire Line - 3400 4250 3950 4250 -Wire Wire Line - 3100 12850 3100 12900 -Wire Wire Line - 3100 12900 1650 12900 -Connection ~ 2700 12900 -Wire Wire Line - 6400 12400 6400 12450 -Wire Wire Line - 5000 12900 6400 12900 -Wire Wire Line - 6400 12900 6400 12850 -Wire Wire Line - 14250 6850 13550 6850 -Wire Wire Line - 14250 7150 13550 7150 -Wire Wire Line - 14250 7250 13550 7250 -Wire Wire Line - 14250 6950 13550 6950 -Wire Wire Line - 14250 7450 14150 7450 -Wire Wire Line - 14250 8250 14000 8250 -Wire Wire Line - 14000 8350 14250 8350 -Wire Wire Line - 14250 8050 13550 8050 -Wire Wire Line - 14250 7750 13550 7750 -Wire Wire Line - 14250 8450 13550 8450 -Wire Wire Line - 13500 8550 14250 8550 -Wire Wire Line - 13950 8150 14250 8150 -Wire Wire Line - 14250 8850 13800 8850 -Wire Wire Line - 19050 8650 18450 8650 -Wire Wire Line - 18250 8650 17650 8650 -Wire Wire Line - 17650 8350 18250 8350 -Wire Wire Line - 18250 8150 17650 8150 -Wire Wire Line - 17650 8250 18250 8250 -Wire Wire Line - 17650 8450 18250 8450 -Wire Wire Line - 17650 8850 18250 8850 -Wire Wire Line - 18250 8550 17650 8550 + 17650 7850 18000 7850 Wire Wire Line 17650 8750 18250 8750 Wire Wire Line - 17650 7850 18000 7850 + 18250 8550 17650 8550 +Wire Wire Line + 17650 8850 18250 8850 +Wire Wire Line + 17650 8450 18250 8450 +Wire Wire Line + 17650 8250 18250 8250 +Wire Wire Line + 18250 8150 17650 8150 +Wire Wire Line + 17650 8350 18250 8350 +Wire Wire Line + 18250 8650 17650 8650 +Wire Wire Line + 19050 8650 18450 8650 +Wire Wire Line + 14250 8850 13800 8850 +Wire Wire Line + 13950 8150 14250 8150 +Wire Wire Line + 13500 8550 14250 8550 +Wire Wire Line + 14250 8450 13550 8450 +Wire Wire Line + 14250 7750 13550 7750 +Wire Wire Line + 14250 8050 13550 8050 +Wire Wire Line + 14000 8350 14250 8350 +Wire Wire Line + 14250 8250 14000 8250 +Wire Wire Line + 14250 7450 14150 7450 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Line + 10600 4650 11150 4650 +Wire Wire Line + 10200 4700 10600 4700 +Wire Wire Line + 10700 5100 10200 5100 +Wire Wire Line + 10700 4600 10200 4600 +Wire Wire Line + 10700 4400 10200 4400 +Wire Wire Line + 10700 4200 10200 4200 +Wire Wire Line + 10700 3800 10200 3800 +Wire Wire Line + 10700 3600 10200 3600 +Wire Wire Line + 10700 3300 10200 3300 +Wire Bus Line + 1100 1300 1150 1300 +Wire Wire Line + 6000 3900 5400 3900 +Wire Wire Line + 6000 3700 5400 3700 +Wire Wire Line + 4550 2750 4100 2750 +Wire Wire Line + 4550 2950 4100 2950 +Wire Wire Line + 4550 2850 4100 2850 +Wire Wire Line + 4100 2650 4550 2650 +Wire Wire Line + 4950 2650 5400 2650 +Wire Wire Line + 5400 2850 4950 2850 +Wire Wire Line + 5400 2950 4950 2950 +Wire Wire Line + 5400 2750 4950 2750 +Wire Wire Line + 4100 2100 4550 2100 +Wire Wire Line + 4550 2300 4100 2300 +Wire Wire Line + 4550 2400 4100 2400 +Wire Wire Line + 4550 2200 4100 2200 +Wire Wire Line + 5400 2200 4950 2200 +Wire Wire Line + 5400 2400 4950 2400 +Wire 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10900 +Wire Wire Line + 20350 10900 20350 10850 +Wire Wire Line + 12100 10000 12100 9950 +Wire Wire Line + 19500 10500 19800 10500 +Text HLabel 19800 10700 2 60 Input ~ 0 +S6_TCK +Text HLabel 19800 10600 2 60 Input ~ 0 +S6_TDI +Text HLabel 19800 10500 2 60 Output ~ 0 +S6_TDO +Text HLabel 19800 10400 2 60 Input ~ 0 +S6_TMS +$Comp +L R R30 +U 1 1 4C7168DD +P 12100 10250 +F 0 "R30" V 12180 10250 50 0000 C CNN +F 1 "330" V 12100 10250 50 0000 C CNN +F 2 "0402" H 12100 10250 60 0001 C CNN + 1 12100 10250 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR041 +U 1 1 4C7168D5 +P 12100 9950 +F 0 "#PWR041" H 12100 9910 30 0001 C CNN +F 1 "+3.3V" H 12100 10060 30 0000 C CNN + 1 12100 9950 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR042 +U 1 1 4C716889 +P 20350 10300 +F 0 "#PWR042" H 20350 10260 30 0001 C CNN +F 1 "+3.3V" H 20350 10410 30 0000 C CNN + 1 20350 10300 + 1 0 0 -1 +$EndComp +$Comp +L R R29 +U 1 1 4C716877 +P 20350 10600 +F 0 "R29" V 20430 10600 50 0000 C CNN +F 1 "4.7k" V 20350 10600 50 0000 C CNN +F 2 "0402" H 20350 10600 60 0001 C CNN + 1 20350 10600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR043 +U 1 1 4C716816 +P 19700 11050 +F 0 "#PWR043" H 19700 11050 30 0001 C CNN +F 1 "GND" H 19700 10980 30 0001 C CNN + 1 19700 11050 + 1 0 0 -1 +$EndComp Text Label 18250 8450 2 60 ~ 0 NF_D4 Text Label 18250 8650 2 60 ~ 0 @@ -2214,28 +2297,28 @@ VCC02 Text GLabel 5300 6250 3 30 BiDi ~ 0 VCCO2 $Comp -L +3.3V #PWR041 +L +3.3V #PWR044 U 1 1 4C65CF66 P 1650 14300 -F 0 "#PWR041" H 1650 14260 30 0001 C CNN +F 0 "#PWR044" H 1650 14260 30 0001 C CNN F 1 "+3.3V" H 1650 14410 30 0000 C CNN 1 1650 14300 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR042 +L +2.5V #PWR045 U 1 1 4C65C84B P 4600 14300 -F 0 "#PWR042" H 4600 14250 20 0001 C CNN +F 0 "#PWR045" H 4600 14250 20 0001 C CNN F 1 "+2.5V" H 4600 14400 30 0000 C CNN 1 4600 14300 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR043 +L +2.5V #PWR046 U 1 1 4C65C837 P 4600 12350 -F 0 "#PWR043" H 4600 12300 20 0001 C CNN +F 0 "#PWR046" H 4600 12300 20 0001 C CNN F 1 "+2.5V" H 4600 12450 30 0000 C CNN 1 4600 12350 1 0 0 -1 @@ -2282,10 +2365,10 @@ F 1 "470nF" H 6050 12550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR044 +L GND #PWR047 U 1 1 4C656D9B P 4600 12950 -F 0 "#PWR044" H 4600 12950 30 0001 C CNN +F 0 "#PWR047" H 4600 12950 30 0001 C CNN F 1 "GND" H 4600 12880 30 0001 C CNN 1 4600 12950 1 0 0 -1 @@ -2347,10 +2430,10 @@ F 1 "470nF" H 6050 13550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR045 +L GND #PWR048 U 1 1 4C656D47 P 4600 13950 -F 0 "#PWR045" H 4600 13950 30 0001 C CNN +F 0 "#PWR048" H 4600 13950 30 0001 C CNN F 1 "GND" H 4600 13880 30 0001 C CNN 1 4600 13950 1 0 0 -1 @@ -2403,10 +2486,10 @@ F 1 "470nF" H 6050 14500 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR046 +L GND #PWR049 U 1 1 4C656CFD P 4600 14900 -F 0 "#PWR046" H 4600 14900 30 0001 C CNN +F 0 "#PWR049" H 4600 14900 30 0001 C CNN F 1 "GND" H 4600 14830 30 0001 C CNN 1 4600 14900 1 0 0 -1 @@ -2450,10 +2533,10 @@ F 1 "100uF" H 4650 14500 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR047 +L GND #PWR050 U 1 1 4C656CBC P 1650 14900 -F 0 "#PWR047" H 1650 14900 30 0001 C CNN +F 0 "#PWR050" H 1650 14900 30 0001 C CNN F 1 "GND" H 1650 14830 30 0001 C CNN 1 1650 14900 1 0 0 -1 @@ -2499,10 +2582,10 @@ $EndComp Text Notes 1750 13400 0 30 ~ 0 VCC_AUX Decoupling Capacitors (7) $Comp -L GND #PWR048 +L GND #PWR051 U 1 1 4C656C68 P 1650 14000 -F 0 "#PWR048" H 1650 14000 30 0001 C CNN +F 0 "#PWR051" H 1650 14000 30 0001 C CNN F 1 "GND" H 1650 13930 30 0001 C CNN 1 1650 14000 1 0 0 -1 @@ -2571,19 +2654,19 @@ F 1 "100uF" H 1700 13600 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR049 +L +2.5V #PWR052 U 1 1 4C656BBA P 1650 13400 -F 0 "#PWR049" H 1650 13350 20 0001 C CNN +F 0 "#PWR052" H 1650 13350 20 0001 C CNN F 1 "+2.5V" H 1650 13500 30 0000 C CNN 1 1650 13400 1 0 0 -1 $EndComp $Comp -L GND #PWR050 +L GND #PWR053 U 1 1 4C656BA8 P 1650 12950 -F 0 "#PWR050" H 1650 12950 30 0001 C CNN +F 0 "#PWR053" H 1650 12950 30 0001 C CNN F 1 "GND" H 1650 12880 30 0001 C CNN 1 1650 12950 1 0 0 -1 @@ -2618,10 +2701,10 @@ F 1 "4.7uF" H 2050 12550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR051 +L +1.2V #PWR054 U 1 1 4C656AA1 P 1650 12350 -F 0 "#PWR051" H 1650 12490 20 0001 C CNN +F 0 "#PWR054" H 1650 12490 20 0001 C CNN F 1 "+1.2V" H 1650 12460 30 0000 C CNN 1 1650 12350 1 0 0 -1 @@ -2686,46 +2769,46 @@ NF_RE_N Text HLabel 18000 7650 2 60 BiDi ~ 0 NF_RNB $Comp -L +3.3V #PWR052 +L +3.3V #PWR055 U 1 1 4C61E5B3 P 15900 6100 -F 0 "#PWR052" H 15900 6060 30 0001 C CNN +F 0 "#PWR055" H 15900 6060 30 0001 C CNN F 1 "+3.3V" H 15900 6210 30 0000 C CNN 1 15900 6100 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR053 +L +1.2V #PWR056 U 1 1 4C61E58C P 16500 9850 -F 0 "#PWR053" H 16500 9990 20 0001 C CNN +F 0 "#PWR056" H 16500 9990 20 0001 C CNN F 1 "+1.2V" H 16500 9960 30 0000 C CNN 1 16500 9850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR054 +L +2.5V #PWR057 U 1 1 4C61E577 P 15000 9850 -F 0 "#PWR054" H 15000 9800 20 0001 C CNN +F 0 "#PWR057" H 15000 9800 20 0001 C CNN F 1 "+2.5V" H 15000 9950 30 0000 C CNN 1 15000 9850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR055 +L +2.5V #PWR058 U 1 1 4C61E523 P 19700 650 -F 0 "#PWR055" H 19700 600 20 0001 C CNN +F 0 "#PWR058" H 19700 600 20 0001 C CNN F 1 "+2.5V" H 19700 750 30 0000 C CNN 1 19700 650 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR056 +L +2.5V #PWR059 U 1 1 4C61E51F P 8100 650 -F 0 "#PWR056" H 8100 600 20 0001 C CNN +F 0 "#PWR059" H 8100 600 20 0001 C CNN F 1 "+2.5V" H 8100 750 30 0000 C CNN 1 8100 650 1 0 0 -1 @@ -2765,10 +2848,10 @@ M1_BA[0..1] Text HLabel 15750 3950 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR057 +L GND #PWR060 U 1 1 4C60C21D P 1600 5950 -F 0 "#PWR057" H 1600 5950 30 0001 C CNN +F 0 "#PWR060" H 1600 5950 30 0001 C CNN F 1 "GND" H 1600 5880 30 0001 C CNN 1 1600 5950 -1 0 0 -1 @@ -3180,10 +3263,10 @@ M0_CLK Text HLabel 11150 4650 2 60 Output ~ 0 M0_CLK# $Comp -L GND #PWR058 +L GND #PWR061 U 1 1 4C439B7E P 16400 12650 -F 0 "#PWR058" H 16400 12650 30 0001 C CNN +F 0 "#PWR061" H 16400 12650 30 0001 C CNN F 1 "GND" H 16400 12580 30 0001 C CNN 1 16400 12650 -1 0 0 -1 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 0e0cac4..08fed14 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:19:33 AM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 01:33:25 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,7 +49,7 @@ LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 2 7 +Sheet 2 8 Title "" Date "22 aug 2010" Rev "" diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index 0e8989c..6add8a6 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:19:33 AM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 01:33:25 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,7 +49,7 @@ LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 2 7 +Sheet 2 8 Title "" Date "22 aug 2010" Rev "" diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 7a000b4..9b07891 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:19:33 AM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 01:33:25 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,7 +49,7 @@ LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 3 7 +Sheet 3 8 Title "" Date "22 aug 2010" Rev "" diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 3bde0bd..64f04ab 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:19:33 AM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 01:33:25 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,7 +49,7 @@ LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 6 7 +Sheet 6 8 Title "" Date "22 aug 2010" Rev "" diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index ed77eb5..9e49735 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Sun 22 Aug 2010 08:19:33 AM COT +EESchema-LIBRARY Version 2.3 Date: Sun 22 Aug 2010 01:33:25 PM COT # # +1.2V # @@ -155,6 +155,32 @@ X ~ 2 0 -100 65 U 40 40 1 1 P ENDDRAW ENDDEF # +# CONN_8X2 +# +DEF CONN_8X2 P 0 40 Y Y 1 F N +F0 "P" 0 450 60 H V C CNN +F1 "CONN_8X2" 0 0 50 V V C CNN +DRAW +S -100 400 100 -400 0 1 0 N +X ~ 1 -400 350 300 R 60 60 1 1 P I +X ~ 2 400 350 300 L 60 60 1 1 P I +X ~ 3 -400 250 300 R 60 60 1 1 P I +X ~ 4 400 250 300 L 60 60 1 1 P I +X ~ 5 -400 150 300 R 60 60 1 1 P I +X ~ 6 400 150 300 L 60 60 1 1 P I +X ~ 7 -400 50 300 R 60 60 1 1 P I +X ~ 8 400 50 300 L 60 60 1 1 P I +X ~ 9 -400 -50 300 R 60 60 1 1 P I +X ~ 10 400 -50 300 L 60 60 1 1 P I +X ~ 11 -400 -150 300 R 60 60 1 1 P I +X ~ 12 400 -150 300 L 60 60 1 1 P I +X ~ 13 -400 -250 300 R 60 60 1 1 P I +X ~ 14 400 -250 300 L 60 60 1 1 P I +X ~ 15 -400 -350 300 R 60 60 1 1 P I +X ~ 16 400 -350 300 L 60 60 1 1 P I +ENDDRAW +ENDDEF +# # GND # DEF ~GND #PWR 0 0 Y Y 1 F P diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index a5c76fa..79a3f0c 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,20 +1,20 @@ -PCBNEW-BOARD Version 1 date Sun 22 Aug 2010 08:23:04 AM COT +PCBNEW-BOARD Version 1 date Sun 22 Aug 2010 01:34:23 PM COT -# Created by Pcbnew(2010-07-27 BZR 2423)-unstable +# Created by Pcbnew(2010-07-15 BZR 2414)-unstable $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 13FF801F -Links 675 -NoConn 543 -Di 45200 12883 79122 50668 +Links 685 +NoConn 539 +Di 45200 12883 81982 50668 Ndraw 7 -Ntrack 1203 +Ntrack 1268 Nzone 0 BoardThickness 630 -Nmodule 161 -Nnets 252 +Nmodule 164 +Nnets 258 $EndGENERAL $SHEETDESCR @@ -90,987 +90,1011 @@ Na 5 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A1" +Na 6 "/DBG_PRG/FPGA_TCK" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_A6" +Na 7 "/DBG_PRG/FPGA_TDI" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_A8" +Na 8 "/DBG_PRG/FPGA_TDO" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_BA0" +Na 9 "/DBG_PRG/FPGA_TMS" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_CAS#" +Na 10 "/DDR_Banks/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_CLK#" +Na 11 "/DDR_Banks/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_DQ1" +Na 12 "/DDR_Banks/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_DQ10" +Na 13 "/DDR_Banks/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_DQ7" +Na 14 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_DQ8" +Na 15 "/DDR_Banks/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_DQ9" +Na 16 "/DDR_Banks/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_UDQS" +Na 17 "/DDR_Banks/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_VREF" +Na 18 "/DDR_Banks/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M1_A0" +Na 19 "/DDR_Banks/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M1_A11" +Na 20 "/DDR_Banks/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M1_A2" +Na 21 "/DDR_Banks/M0_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M1_A4" +Na 22 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_A5" +Na 23 "/DDR_Banks/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_A6" +Na 24 "/DDR_Banks/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_A7" +Na 25 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_A8" +Na 26 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_BA0" +Na 27 "/DDR_Banks/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_CAS#" +Na 28 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_CLK" +Na 29 "/DDR_Banks/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_DQ14" +Na 30 "/DDR_Banks/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_DQ15" +Na 31 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_DQ4" +Na 32 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_VREF" +Na 33 "/DDR_Banks/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/Ethernet_Phy/ETH_A1.8V" +Na 34 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/Ethernet_Phy/ETH_A3.3V" +Na 35 "/DDR_Banks/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/Ethernet_Phy/ETH_CLK" +Na 36 "/DDR_Banks/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/Ethernet_Phy/ETH_CRS" +Na 37 "/DDR_Banks/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/Ethernet_Phy/ETH_LED0" +Na 38 "/DDR_Banks/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/Ethernet_Phy/ETH_LED1" +Na 39 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Ethernet_Phy/ETH_PLL1.8V" +Na 40 "/DDR_Banks/M1_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_RXC" +Na 41 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_RXD0" +Na 42 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_RXD1" +Na 43 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_TXD2" +Na 44 "/Ethernet_Phy/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_TXD3" +Na 45 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/MAG_RX+" +Na 46 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/MAG_RX-" +Na 47 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/MAG_SHIELD" +Na 48 "/Ethernet_Phy/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/MAG_TX+" +Na 49 "/Ethernet_Phy/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/MAG_TX-" +Na 50 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/FPGA_Spartan6/ETH_COL" +Na 51 "/Ethernet_Phy/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Spartan6/ETH_INT" +Na 52 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Spartan6/ETH_MDC" +Na 53 "/Ethernet_Phy/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Spartan6/ETH_MDIO" +Na 54 "/Ethernet_Phy/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Spartan6/ETH_RESET_N" +Na 55 "/Ethernet_Phy/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/ETH_RXD2" +Na 56 "/Ethernet_Phy/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/ETH_RXD3" +Na 57 "/Ethernet_Phy/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/ETH_RXDV" +Na 58 "/Ethernet_Phy/MAG_RX+" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/ETH_RXER" +Na 59 "/Ethernet_Phy/MAG_RX-" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/ETH_TXC" +Na 60 "/Ethernet_Phy/MAG_SHIELD" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/ETH_TXD0" +Na 61 "/Ethernet_Phy/MAG_TX+" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/ETH_TXD1" +Na 62 "/Ethernet_Phy/MAG_TX-" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/ETH_TXEN" +Na 63 "/FPGA_Spartan6/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/ETH_TXER" +Na 64 "/FPGA_Spartan6/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/M0_A0" +Na 65 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/M0_A10" +Na 66 "/FPGA_Spartan6/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/M0_A11" +Na 67 "/FPGA_Spartan6/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/M0_A12" +Na 68 "/FPGA_Spartan6/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_A2" +Na 69 "/FPGA_Spartan6/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_A3" +Na 70 "/FPGA_Spartan6/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_A4" +Na 71 "/FPGA_Spartan6/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_A5" +Na 72 "/FPGA_Spartan6/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_A7" +Na 73 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_A9" +Na 74 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_BA1" +Na 75 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_CKE" +Na 76 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_CLK" +Na 77 "/FPGA_Spartan6/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_DQ0" +Na 78 "/FPGA_Spartan6/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_DQ11" +Na 79 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_DQ12" +Na 80 "/FPGA_Spartan6/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_DQ13" +Na 81 "/FPGA_Spartan6/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_DQ14" +Na 82 "/FPGA_Spartan6/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_DQ15" +Na 83 "/FPGA_Spartan6/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_DQ2" +Na 84 "/FPGA_Spartan6/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M0_DQ3" +Na 85 "/FPGA_Spartan6/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M0_DQ4" +Na 86 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M0_DQ5" +Na 87 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M0_DQ6" +Na 88 "/FPGA_Spartan6/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M0_LDM" +Na 89 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M0_LDQS" +Na 90 "/FPGA_Spartan6/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M0_RAS#" +Na 91 "/FPGA_Spartan6/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M0_UDM" +Na 92 "/FPGA_Spartan6/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M0_WE#" +Na 93 "/FPGA_Spartan6/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_A1" +Na 94 "/FPGA_Spartan6/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_A10" +Na 95 "/FPGA_Spartan6/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_A12" +Na 96 "/FPGA_Spartan6/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_A3" +Na 97 "/FPGA_Spartan6/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_A9" +Na 98 "/FPGA_Spartan6/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_BA1" +Na 99 "/FPGA_Spartan6/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_CKE" +Na 100 "/FPGA_Spartan6/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_CLK#" +Na 101 "/FPGA_Spartan6/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_CS#" +Na 102 "/FPGA_Spartan6/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_DQ0" +Na 103 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_DQ1" +Na 104 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ10" +Na 105 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_DQ11" +Na 106 "/FPGA_Spartan6/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_DQ12" +Na 107 "/FPGA_Spartan6/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_DQ13" +Na 108 "/FPGA_Spartan6/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ2" +Na 109 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_DQ3" +Na 110 "/FPGA_Spartan6/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_DQ5" +Na 111 "/FPGA_Spartan6/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Spartan6/M1_DQ6" +Na 112 "/FPGA_Spartan6/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_DQ7" +Na 113 "/FPGA_Spartan6/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Spartan6/M1_DQ8" +Na 114 "/FPGA_Spartan6/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/M1_DQ9" +Na 115 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/M1_LDM" +Na 116 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Spartan6/M1_LDQS" +Na 117 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA_Spartan6/M1_RAS#" +Na 118 "/FPGA_Spartan6/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/M1_UDM" +Na 119 "/FPGA_Spartan6/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Spartan6/M1_UDQS" +Na 120 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Spartan6/M1_WE#" +Na 121 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Spartan6/NF_ALE" +Na 122 "/FPGA_Spartan6/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Spartan6/NF_CLE" +Na 123 "/FPGA_Spartan6/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Spartan6/NF_D2" +Na 124 "/FPGA_Spartan6/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Spartan6/NF_D4" +Na 125 "/FPGA_Spartan6/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Spartan6/NF_D6" +Na 126 "/FPGA_Spartan6/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Spartan6/NF_D7" +Na 127 "/FPGA_Spartan6/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Spartan6/NF_RNB" +Na 128 "/FPGA_Spartan6/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/FPGA_Spartan6/NF_WE_N" +Na 129 "/FPGA_Spartan6/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/FPGA_Spartan6/PROG_CCLK" +Na 130 "/FPGA_Spartan6/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/FPGA_Spartan6/PROG_CSO" +Na 131 "/FPGA_Spartan6/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/FPGA_Spartan6/PROG_MISO0" +Na 132 "/FPGA_Spartan6/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/FPGA_Spartan6/PROG_MISO1" +Na 133 "/FPGA_Spartan6/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/FPGA_Spartan6/PROG_MISO2" +Na 134 "/FPGA_Spartan6/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/FPGA_Spartan6/PROG_MISO3" +Na 135 "/FPGA_Spartan6/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/FPGA_Spartan6/R_M0_A0" +Na 136 "/FPGA_Spartan6/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/FPGA_Spartan6/R_M0_A1" +Na 137 "/FPGA_Spartan6/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/FPGA_Spartan6/R_M0_A10" +Na 138 "/FPGA_Spartan6/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/FPGA_Spartan6/R_M0_A11" +Na 139 "/FPGA_Spartan6/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/FPGA_Spartan6/R_M0_A12" +Na 140 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/FPGA_Spartan6/R_M0_A2" +Na 141 "/FPGA_Spartan6/R_M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/FPGA_Spartan6/R_M0_A3" +Na 142 "/FPGA_Spartan6/R_M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/FPGA_Spartan6/R_M0_A4" +Na 143 "/FPGA_Spartan6/R_M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/FPGA_Spartan6/R_M0_A5" +Na 144 "/FPGA_Spartan6/R_M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/FPGA_Spartan6/R_M0_A6" +Na 145 "/FPGA_Spartan6/R_M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/FPGA_Spartan6/R_M0_A7" +Na 146 "/FPGA_Spartan6/R_M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/FPGA_Spartan6/R_M0_A8" +Na 147 "/FPGA_Spartan6/R_M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/FPGA_Spartan6/R_M0_A9" +Na 148 "/FPGA_Spartan6/R_M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/FPGA_Spartan6/R_M0_BA0" +Na 149 "/FPGA_Spartan6/R_M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/FPGA_Spartan6/R_M0_BA1" +Na 150 "/FPGA_Spartan6/R_M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/FPGA_Spartan6/R_M0_CAS#" +Na 151 "/FPGA_Spartan6/R_M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/FPGA_Spartan6/R_M0_CKE" +Na 152 "/FPGA_Spartan6/R_M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/FPGA_Spartan6/R_M0_DQ0" +Na 153 "/FPGA_Spartan6/R_M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/FPGA_Spartan6/R_M0_DQ1" +Na 154 "/FPGA_Spartan6/R_M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/FPGA_Spartan6/R_M0_DQ10" +Na 155 "/FPGA_Spartan6/R_M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/FPGA_Spartan6/R_M0_DQ11" +Na 156 "/FPGA_Spartan6/R_M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/FPGA_Spartan6/R_M0_DQ12" +Na 157 "/FPGA_Spartan6/R_M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/FPGA_Spartan6/R_M0_DQ13" +Na 158 "/FPGA_Spartan6/R_M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/FPGA_Spartan6/R_M0_DQ14" +Na 159 "/FPGA_Spartan6/R_M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/FPGA_Spartan6/R_M0_DQ15" +Na 160 "/FPGA_Spartan6/R_M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/FPGA_Spartan6/R_M0_DQ2" +Na 161 "/FPGA_Spartan6/R_M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/FPGA_Spartan6/R_M0_DQ3" +Na 162 "/FPGA_Spartan6/R_M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/FPGA_Spartan6/R_M0_DQ4" +Na 163 "/FPGA_Spartan6/R_M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/FPGA_Spartan6/R_M0_DQ5" +Na 164 "/FPGA_Spartan6/R_M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/FPGA_Spartan6/R_M0_DQ6" +Na 165 "/FPGA_Spartan6/R_M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/FPGA_Spartan6/R_M0_DQ7" +Na 166 "/FPGA_Spartan6/R_M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/FPGA_Spartan6/R_M0_DQ8" +Na 167 "/FPGA_Spartan6/R_M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/FPGA_Spartan6/R_M0_DQ9" +Na 168 "/FPGA_Spartan6/R_M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/FPGA_Spartan6/R_M0_LDM" +Na 169 "/FPGA_Spartan6/R_M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/FPGA_Spartan6/R_M0_LDQS" +Na 170 "/FPGA_Spartan6/R_M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/FPGA_Spartan6/R_M0_RAS#" +Na 171 "/FPGA_Spartan6/R_M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/FPGA_Spartan6/R_M0_UDM" +Na 172 "/FPGA_Spartan6/R_M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/FPGA_Spartan6/R_M0_UDQS" +Na 173 "/FPGA_Spartan6/R_M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/FPGA_Spartan6/R_M0_WE#" +Na 174 "/FPGA_Spartan6/R_M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/FPGA_Spartan6/R_M1_A0" +Na 175 "/FPGA_Spartan6/R_M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/FPGA_Spartan6/R_M1_A1" +Na 176 "/FPGA_Spartan6/R_M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/FPGA_Spartan6/R_M1_A10" +Na 177 "/FPGA_Spartan6/R_M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/FPGA_Spartan6/R_M1_A11" +Na 178 "/FPGA_Spartan6/R_M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/FPGA_Spartan6/R_M1_A12" +Na 179 "/FPGA_Spartan6/R_M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 180 "/FPGA_Spartan6/R_M1_A2" +Na 180 "/FPGA_Spartan6/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/FPGA_Spartan6/R_M1_A3" +Na 181 "/FPGA_Spartan6/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/FPGA_Spartan6/R_M1_A5" +Na 182 "/FPGA_Spartan6/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/FPGA_Spartan6/R_M1_A6" +Na 183 "/FPGA_Spartan6/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/FPGA_Spartan6/R_M1_A7" +Na 184 "/FPGA_Spartan6/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "/FPGA_Spartan6/R_M1_A8" +Na 185 "/FPGA_Spartan6/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "/FPGA_Spartan6/R_M1_A9" +Na 186 "/FPGA_Spartan6/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "/FPGA_Spartan6/R_M1_BA0" +Na 187 "/FPGA_Spartan6/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "/FPGA_Spartan6/R_M1_BA1" +Na 188 "/FPGA_Spartan6/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "/FPGA_Spartan6/R_M1_CAS#" +Na 189 "/FPGA_Spartan6/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "/FPGA_Spartan6/R_M1_CKE" +Na 190 "/FPGA_Spartan6/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "/FPGA_Spartan6/R_M1_CS#" +Na 191 "/FPGA_Spartan6/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "/FPGA_Spartan6/R_M1_DQ0" +Na 192 "/FPGA_Spartan6/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "/FPGA_Spartan6/R_M1_DQ1" +Na 193 "/FPGA_Spartan6/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "/FPGA_Spartan6/R_M1_DQ10" +Na 194 "/FPGA_Spartan6/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "/FPGA_Spartan6/R_M1_DQ11" +Na 195 "/FPGA_Spartan6/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "/FPGA_Spartan6/R_M1_DQ12" +Na 196 "/FPGA_Spartan6/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "/FPGA_Spartan6/R_M1_DQ13" +Na 197 "/FPGA_Spartan6/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "/FPGA_Spartan6/R_M1_DQ14" +Na 198 "/FPGA_Spartan6/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "/FPGA_Spartan6/R_M1_DQ15" +Na 199 "/FPGA_Spartan6/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "/FPGA_Spartan6/R_M1_DQ2" +Na 200 "/FPGA_Spartan6/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 201 "/FPGA_Spartan6/R_M1_DQ3" +Na 201 "/FPGA_Spartan6/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 202 "/FPGA_Spartan6/R_M1_DQ4" +Na 202 "/FPGA_Spartan6/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 203 "/FPGA_Spartan6/R_M1_DQ5" +Na 203 "/FPGA_Spartan6/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 204 "/FPGA_Spartan6/R_M1_DQ6" +Na 204 "/FPGA_Spartan6/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 205 "/FPGA_Spartan6/R_M1_DQ7" +Na 205 "/FPGA_Spartan6/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 206 "/FPGA_Spartan6/R_M1_DQ8" +Na 206 "/FPGA_Spartan6/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 207 "/FPGA_Spartan6/R_M1_DQ9" +Na 207 "/FPGA_Spartan6/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 208 "/FPGA_Spartan6/R_M1_LDM" +Na 208 "/FPGA_Spartan6/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 209 "/FPGA_Spartan6/R_M1_LDQS" +Na 209 "/FPGA_Spartan6/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 210 "/FPGA_Spartan6/R_M1_RAS#" +Na 210 "/FPGA_Spartan6/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 211 "/FPGA_Spartan6/R_M1_UDM" +Na 211 "/FPGA_Spartan6/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 212 "/FPGA_Spartan6/R_M1_UDQS" +Na 212 "/FPGA_Spartan6/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 213 "/FPGA_Spartan6/R_M1_WE#" +Na 213 "/FPGA_Spartan6/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 214 "/FPGA_Spartan6/SD_DAT0" +Na 214 "/FPGA_Spartan6/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 215 "/FPGA_Spartan6/USBA_RCV" +Na 215 "/FPGA_Spartan6/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 216 "/FPGA_Spartan6/USBA_VP" +Na 216 "/FPGA_Spartan6/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 217 "/Non_volatile_memories/NF_CS1_N" +Na 217 "/FPGA_Spartan6/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 218 "/Non_volatile_memories/NF_D0" +Na 218 "/FPGA_Spartan6/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 219 "/Non_volatile_memories/NF_D1" +Na 219 "/FPGA_Spartan6/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 220 "/Non_volatile_memories/NF_D3" +Na 220 "/FPGA_Spartan6/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 221 "/Non_volatile_memories/NF_D5" +Na 221 "/FPGA_Spartan6/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 222 "/Non_volatile_memories/NF_RE_N" +Na 222 "/FPGA_Spartan6/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 223 "/Non_volatile_memories/SD_CLK" +Na 223 "/FPGA_Spartan6/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 224 "/Non_volatile_memories/SD_CMD" +Na 224 "/Non_volatile_memories/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 225 "/Non_volatile_memories/SD_DAT1" +Na 225 "/Non_volatile_memories/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 226 "/Non_volatile_memories/SD_DAT2" +Na 226 "/Non_volatile_memories/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 227 "/Non_volatile_memories/SD_DAT3" +Na 227 "/Non_volatile_memories/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 228 "/USB/USBA_OE_N" +Na 228 "/Non_volatile_memories/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 229 "/USB/USBA_SPD" +Na 229 "/Non_volatile_memories/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 230 "/USB/USBA_VM" +Na 230 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 231 "GND" +Na 231 "/USB/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 232 "N-000395" +Na 232 "/USB/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 233 "N-000397" +Na 233 "/USB/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 234 "N-000398" +Na 234 "/USB/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 235 "N-000422" +Na 235 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 236 "N-000424" +Na 236 "N-000127" St ~ $EndEQUIPOT $EQUIPOT -Na 237 "N-000425" +Na 237 "N-000132" St ~ $EndEQUIPOT $EQUIPOT -Na 238 "N-000426" +Na 238 "N-000393" St ~ $EndEQUIPOT $EQUIPOT -Na 239 "N-000427" +Na 239 "N-000394" St ~ $EndEQUIPOT $EQUIPOT -Na 240 "N-000429" +Na 240 "N-000395" St ~ $EndEQUIPOT $EQUIPOT -Na 241 "N-000430" +Na 241 "N-000414" St ~ $EndEQUIPOT $EQUIPOT -Na 242 "N-000431" +Na 242 "N-000415" St ~ $EndEQUIPOT $EQUIPOT -Na 243 "N-000432" +Na 243 "N-000416" St ~ $EndEQUIPOT $EQUIPOT -Na 244 "N-000433" +Na 244 "N-000425" St ~ $EndEQUIPOT $EQUIPOT -Na 245 "N-000434" +Na 245 "N-000426" St ~ $EndEQUIPOT $EQUIPOT -Na 246 "N-000435" +Na 246 "N-000427" St ~ $EndEQUIPOT $EQUIPOT -Na 247 "N-000436" +Na 247 "N-000428" St ~ $EndEQUIPOT $EQUIPOT -Na 248 "N-000437" +Na 248 "N-000429" St ~ $EndEQUIPOT $EQUIPOT -Na 249 "N-000447" +Na 249 "N-000430" St ~ $EndEQUIPOT $EQUIPOT -Na 250 "N-000466" +Na 250 "N-000431" St ~ $EndEQUIPOT $EQUIPOT -Na 251 "VCCO2" +Na 251 "N-000432" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 252 "N-000433" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 253 "N-000434" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 254 "N-000435" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 255 "N-000445" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 256 "N-000464" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 257 "VCCO2" St ~ $EndEQUIPOT $NCLASS @@ -1083,190 +1107,141 @@ ViaDrill 79 uViaDia 197 uViaDrill 79 AddNet "" -AddNet "/DDR_Banks/M0_A1" -AddNet "/DDR_Banks/M0_A6" -AddNet "/DDR_Banks/M0_A8" -AddNet "/DDR_Banks/M0_BA0" -AddNet "/DDR_Banks/M0_CAS#" -AddNet "/DDR_Banks/M0_CLK#" -AddNet "/DDR_Banks/M0_DQ1" -AddNet "/DDR_Banks/M0_DQ10" -AddNet "/DDR_Banks/M0_DQ7" -AddNet "/DDR_Banks/M0_DQ8" -AddNet "/DDR_Banks/M0_DQ9" -AddNet "/DDR_Banks/M0_UDQS" -AddNet "/DDR_Banks/M1_A0" +AddNet "/DBG_PRG/FPGA_TCK" +AddNet "/DBG_PRG/FPGA_TDI" +AddNet "/DBG_PRG/FPGA_TDO" +AddNet "/DBG_PRG/FPGA_TMS" +AddNet "/DDR_Banks/M0_A0" +AddNet "/DDR_Banks/M0_A2" +AddNet "/DDR_Banks/M0_A3" +AddNet "/DDR_Banks/M0_A4" +AddNet "/DDR_Banks/M0_A7" +AddNet "/DDR_Banks/M0_CKE" +AddNet "/DDR_Banks/M0_DQ14" +AddNet "/DDR_Banks/M0_DQ15" +AddNet "/DDR_Banks/M0_DQ3" +AddNet "/DDR_Banks/M0_DQ6" +AddNet "/DDR_Banks/M0_UDM" +AddNet "/DDR_Banks/M0_VREF" +AddNet "/DDR_Banks/M0_WE#" +AddNet "/DDR_Banks/M1_A10" AddNet "/DDR_Banks/M1_A11" -AddNet "/DDR_Banks/M1_A2" -AddNet "/DDR_Banks/M1_A4" +AddNet "/DDR_Banks/M1_A12" AddNet "/DDR_Banks/M1_A5" AddNet "/DDR_Banks/M1_A6" -AddNet "/DDR_Banks/M1_A7" AddNet "/DDR_Banks/M1_A8" -AddNet "/DDR_Banks/M1_BA0" -AddNet "/DDR_Banks/M1_CAS#" +AddNet "/DDR_Banks/M1_A9" +AddNet "/DDR_Banks/M1_BA1" AddNet "/DDR_Banks/M1_CLK" +AddNet "/DDR_Banks/M1_CLK#" +AddNet "/DDR_Banks/M1_DQ0" +AddNet "/DDR_Banks/M1_DQ10" AddNet "/DDR_Banks/M1_DQ14" -AddNet "/DDR_Banks/M1_DQ15" -AddNet "/DDR_Banks/M1_DQ4" -AddNet "/Ethernet_Phy/ETH_CLK" -AddNet "/Ethernet_Phy/ETH_CRS" -AddNet "/Ethernet_Phy/ETH_RXC" +AddNet "/DDR_Banks/M1_DQ3" +AddNet "/DDR_Banks/M1_DQ7" +AddNet "/DDR_Banks/M1_DQ8" +AddNet "/DDR_Banks/M1_LDQS" +AddNet "/DDR_Banks/M1_VREF" +AddNet "/DDR_Banks/M1_WE#" +AddNet "/Ethernet_Phy/ETH_A1.8V" +AddNet "/Ethernet_Phy/ETH_A3.3V" +AddNet "/Ethernet_Phy/ETH_COL" +AddNet "/Ethernet_Phy/ETH_INT" +AddNet "/Ethernet_Phy/ETH_LED0" +AddNet "/Ethernet_Phy/ETH_LED1" +AddNet "/Ethernet_Phy/ETH_MDC" +AddNet "/Ethernet_Phy/ETH_MDIO" +AddNet "/Ethernet_Phy/ETH_PLL1.8V" AddNet "/Ethernet_Phy/ETH_RXD0" AddNet "/Ethernet_Phy/ETH_RXD1" +AddNet "/Ethernet_Phy/ETH_RXD3" +AddNet "/Ethernet_Phy/ETH_RXDV" +AddNet "/Ethernet_Phy/ETH_TXC" AddNet "/Ethernet_Phy/ETH_TXD2" -AddNet "/Ethernet_Phy/ETH_TXD3" -AddNet "/FPGA_Spartan6/ETH_COL" -AddNet "/FPGA_Spartan6/ETH_INT" -AddNet "/FPGA_Spartan6/ETH_MDC" -AddNet "/FPGA_Spartan6/ETH_MDIO" +AddNet "/Ethernet_Phy/ETH_TXEN" +AddNet "/Ethernet_Phy/MAG_RX+" +AddNet "/Ethernet_Phy/MAG_RX-" +AddNet "/Ethernet_Phy/MAG_SHIELD" +AddNet "/Ethernet_Phy/MAG_TX+" +AddNet "/Ethernet_Phy/MAG_TX-" +AddNet "/FPGA_Spartan6/ETH_CLK" +AddNet "/FPGA_Spartan6/ETH_CRS" AddNet "/FPGA_Spartan6/ETH_RESET_N" +AddNet "/FPGA_Spartan6/ETH_RXC" AddNet "/FPGA_Spartan6/ETH_RXD2" -AddNet "/FPGA_Spartan6/ETH_RXD3" -AddNet "/FPGA_Spartan6/ETH_RXDV" AddNet "/FPGA_Spartan6/ETH_RXER" -AddNet "/FPGA_Spartan6/ETH_TXC" AddNet "/FPGA_Spartan6/ETH_TXD0" AddNet "/FPGA_Spartan6/ETH_TXD1" -AddNet "/FPGA_Spartan6/ETH_TXEN" +AddNet "/FPGA_Spartan6/ETH_TXD3" AddNet "/FPGA_Spartan6/ETH_TXER" -AddNet "/FPGA_Spartan6/M0_A0" +AddNet "/FPGA_Spartan6/M0_A1" AddNet "/FPGA_Spartan6/M0_A10" AddNet "/FPGA_Spartan6/M0_A11" AddNet "/FPGA_Spartan6/M0_A12" -AddNet "/FPGA_Spartan6/M0_A2" -AddNet "/FPGA_Spartan6/M0_A3" -AddNet "/FPGA_Spartan6/M0_A4" AddNet "/FPGA_Spartan6/M0_A5" -AddNet "/FPGA_Spartan6/M0_A7" +AddNet "/FPGA_Spartan6/M0_A6" +AddNet "/FPGA_Spartan6/M0_A8" AddNet "/FPGA_Spartan6/M0_A9" +AddNet "/FPGA_Spartan6/M0_BA0" AddNet "/FPGA_Spartan6/M0_BA1" -AddNet "/FPGA_Spartan6/M0_CKE" +AddNet "/FPGA_Spartan6/M0_CAS#" AddNet "/FPGA_Spartan6/M0_CLK" +AddNet "/FPGA_Spartan6/M0_CLK#" AddNet "/FPGA_Spartan6/M0_DQ0" +AddNet "/FPGA_Spartan6/M0_DQ1" +AddNet "/FPGA_Spartan6/M0_DQ10" AddNet "/FPGA_Spartan6/M0_DQ11" AddNet "/FPGA_Spartan6/M0_DQ12" -AddNet "/FPGA_Spartan6/M0_DQ14" -AddNet "/FPGA_Spartan6/M0_DQ15" +AddNet "/FPGA_Spartan6/M0_DQ13" AddNet "/FPGA_Spartan6/M0_DQ2" -AddNet "/FPGA_Spartan6/M0_DQ3" AddNet "/FPGA_Spartan6/M0_DQ4" AddNet "/FPGA_Spartan6/M0_DQ5" -AddNet "/FPGA_Spartan6/M0_DQ6" +AddNet "/FPGA_Spartan6/M0_DQ7" +AddNet "/FPGA_Spartan6/M0_DQ8" +AddNet "/FPGA_Spartan6/M0_DQ9" AddNet "/FPGA_Spartan6/M0_LDM" AddNet "/FPGA_Spartan6/M0_LDQS" AddNet "/FPGA_Spartan6/M0_RAS#" -AddNet "/FPGA_Spartan6/M0_UDM" -AddNet "/FPGA_Spartan6/M0_WE#" +AddNet "/FPGA_Spartan6/M0_UDQS" +AddNet "/FPGA_Spartan6/M1_A0" AddNet "/FPGA_Spartan6/M1_A1" -AddNet "/FPGA_Spartan6/M1_A10" -AddNet "/FPGA_Spartan6/M1_A12" +AddNet "/FPGA_Spartan6/M1_A2" AddNet "/FPGA_Spartan6/M1_A3" -AddNet "/FPGA_Spartan6/M1_A9" -AddNet "/FPGA_Spartan6/M1_BA1" +AddNet "/FPGA_Spartan6/M1_A4" +AddNet "/FPGA_Spartan6/M1_A7" +AddNet "/FPGA_Spartan6/M1_BA0" +AddNet "/FPGA_Spartan6/M1_CAS#" AddNet "/FPGA_Spartan6/M1_CKE" -AddNet "/FPGA_Spartan6/M1_CLK#" AddNet "/FPGA_Spartan6/M1_CS#" -AddNet "/FPGA_Spartan6/M1_DQ0" AddNet "/FPGA_Spartan6/M1_DQ1" -AddNet "/FPGA_Spartan6/M1_DQ10" AddNet "/FPGA_Spartan6/M1_DQ11" AddNet "/FPGA_Spartan6/M1_DQ12" AddNet "/FPGA_Spartan6/M1_DQ13" +AddNet "/FPGA_Spartan6/M1_DQ15" AddNet "/FPGA_Spartan6/M1_DQ2" -AddNet "/FPGA_Spartan6/M1_DQ3" +AddNet "/FPGA_Spartan6/M1_DQ4" AddNet "/FPGA_Spartan6/M1_DQ5" AddNet "/FPGA_Spartan6/M1_DQ6" -AddNet "/FPGA_Spartan6/M1_DQ7" -AddNet "/FPGA_Spartan6/M1_DQ8" AddNet "/FPGA_Spartan6/M1_DQ9" AddNet "/FPGA_Spartan6/M1_LDM" -AddNet "/FPGA_Spartan6/M1_LDQS" AddNet "/FPGA_Spartan6/M1_RAS#" AddNet "/FPGA_Spartan6/M1_UDM" AddNet "/FPGA_Spartan6/M1_UDQS" -AddNet "/FPGA_Spartan6/M1_WE#" -AddNet "/FPGA_Spartan6/NF_ALE" AddNet "/FPGA_Spartan6/NF_CLE" +AddNet "/FPGA_Spartan6/NF_CS1_N" +AddNet "/FPGA_Spartan6/NF_D0" AddNet "/FPGA_Spartan6/NF_D2" +AddNet "/FPGA_Spartan6/NF_D3" AddNet "/FPGA_Spartan6/NF_D4" AddNet "/FPGA_Spartan6/NF_D6" -AddNet "/FPGA_Spartan6/NF_D7" +AddNet "/FPGA_Spartan6/NF_RE_N" AddNet "/FPGA_Spartan6/NF_RNB" -AddNet "/FPGA_Spartan6/NF_WE_N" AddNet "/FPGA_Spartan6/PROG_CCLK" AddNet "/FPGA_Spartan6/PROG_CSO" AddNet "/FPGA_Spartan6/PROG_MISO0" AddNet "/FPGA_Spartan6/PROG_MISO1" AddNet "/FPGA_Spartan6/PROG_MISO2" AddNet "/FPGA_Spartan6/PROG_MISO3" -AddNet "/FPGA_Spartan6/SD_DAT0" -AddNet "/FPGA_Spartan6/USBA_RCV" -AddNet "/FPGA_Spartan6/USBA_VP" -AddNet "/Non_volatile_memories/NF_CS1_N" -AddNet "/Non_volatile_memories/NF_D0" -AddNet "/Non_volatile_memories/NF_D1" -AddNet "/Non_volatile_memories/NF_D3" -AddNet "/Non_volatile_memories/NF_D5" -AddNet "/Non_volatile_memories/NF_RE_N" -AddNet "/Non_volatile_memories/SD_CLK" -AddNet "/Non_volatile_memories/SD_CMD" -AddNet "/Non_volatile_memories/SD_DAT1" -AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "/Non_volatile_memories/SD_DAT3" -AddNet "/USB/USBA_OE_N" -AddNet "/USB/USBA_SPD" -AddNet "/USB/USBA_VM" -AddNet "N-000395" -AddNet "N-000397" -AddNet "N-000398" -AddNet "N-000422" -AddNet "N-000424" -AddNet "N-000425" -AddNet "N-000426" -AddNet "N-000427" -AddNet "N-000429" -AddNet "N-000430" -AddNet "N-000431" -AddNet "N-000432" -AddNet "N-000433" -AddNet "N-000434" -AddNet "N-000435" -AddNet "N-000436" -AddNet "N-000437" -AddNet "N-000447" -AddNet "N-000466" -$EndNCLASS -$NCLASS -Name "ADDRESS/DDR" -Desc "" -Clearance 59 -TrackWidth 39 -ViaDia 157 -ViaDrill 79 -uViaDia 197 -uViaDrill 79 -$EndNCLASS -$NCLASS -Name "CLK#CLK/DDR" -Desc "" -Clearance 39 -TrackWidth 39 -ViaDia 157 -ViaDrill 79 -uViaDia 197 -uViaDrill 79 -$EndNCLASS -$NCLASS -Name "DATA/DDR" -Desc "" -Clearance 79 -TrackWidth 39 -ViaDia 157 -ViaDrill 79 -uViaDia 197 -uViaDrill 79 -AddNet "/FPGA_Spartan6/M0_DQ13" AddNet "/FPGA_Spartan6/R_M0_A0" AddNet "/FPGA_Spartan6/R_M0_A1" AddNet "/FPGA_Spartan6/R_M0_A10" @@ -1345,6 +1320,73 @@ AddNet "/FPGA_Spartan6/R_M1_RAS#" AddNet "/FPGA_Spartan6/R_M1_UDM" AddNet "/FPGA_Spartan6/R_M1_UDQS" AddNet "/FPGA_Spartan6/R_M1_WE#" +AddNet "/FPGA_Spartan6/SD_CLK" +AddNet "/FPGA_Spartan6/SD_CMD" +AddNet "/FPGA_Spartan6/SD_DAT1" +AddNet "/FPGA_Spartan6/SD_DAT3" +AddNet "/FPGA_Spartan6/USBA_SPD" +AddNet "/Non_volatile_memories/NF_ALE" +AddNet "/Non_volatile_memories/NF_D1" +AddNet "/Non_volatile_memories/NF_D5" +AddNet "/Non_volatile_memories/NF_D7" +AddNet "/Non_volatile_memories/NF_WE_N" +AddNet "/Non_volatile_memories/SD_DAT0" +AddNet "/Non_volatile_memories/SD_DAT2" +AddNet "/USB/USBA_OE_N" +AddNet "/USB/USBA_RCV" +AddNet "/USB/USBA_VM" +AddNet "/USB/USBA_VP" +AddNet "N-000127" +AddNet "N-000132" +AddNet "N-000393" +AddNet "N-000394" +AddNet "N-000395" +AddNet "N-000414" +AddNet "N-000415" +AddNet "N-000416" +AddNet "N-000425" +AddNet "N-000426" +AddNet "N-000427" +AddNet "N-000428" +AddNet "N-000429" +AddNet "N-000430" +AddNet "N-000431" +AddNet "N-000432" +AddNet "N-000433" +AddNet "N-000434" +AddNet "N-000435" +AddNet "N-000445" +AddNet "N-000464" +$EndNCLASS +$NCLASS +Name "ADDRESS/DDR" +Desc "" +Clearance 59 +TrackWidth 39 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +$EndNCLASS +$NCLASS +Name "CLK#CLK/DDR" +Desc "" +Clearance 39 +TrackWidth 39 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +$EndNCLASS +$NCLASS +Name "DATA/DDR" +Desc "" +Clearance 79 +TrackWidth 39 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 $EndNCLASS $NCLASS Name "ETH/ANALOG" @@ -1355,12 +1397,6 @@ ViaDia 157 ViaDrill 79 uViaDia 197 uViaDrill 79 -AddNet "/Ethernet_Phy/ETH_LED0" -AddNet "/Ethernet_Phy/ETH_LED1" -AddNet "/Ethernet_Phy/MAG_RX+" -AddNet "/Ethernet_Phy/MAG_RX-" -AddNet "/Ethernet_Phy/MAG_TX+" -AddNet "/Ethernet_Phy/MAG_TX-" $EndNCLASS $NCLASS Name "ETH/POWER" @@ -1371,10 +1407,6 @@ ViaDia 157 ViaDrill 79 uViaDia 197 uViaDrill 79 -AddNet "/Ethernet_Phy/ETH_A1.8V" -AddNet "/Ethernet_Phy/ETH_A3.3V" -AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/MAG_SHIELD" $EndNCLASS $NCLASS Name "POWER" @@ -1390,8 +1422,6 @@ AddNet "+1.8V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" -AddNet "/DDR_Banks/M0_VREF" -AddNet "/DDR_Banks/M1_VREF" AddNet "GND" AddNet "VCCO2" $EndNCLASS @@ -1416,7 +1446,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -4133 -4133 $EndPAD $PAD @@ -1437,84 +1467,84 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_CLK" +Ne 63 "/FPGA_Spartan6/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_RXD1" +Ne 52 "/Ethernet_Phy/ETH_RXD1" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RXDV" +Ne 54 "/Ethernet_Phy/ETH_RXDV" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_RXC" +Ne 66 "/FPGA_Spartan6/ETH_RXC" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_TXD3" +Ne 71 "/FPGA_Spartan6/ETH_TXD3" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/ETH_COL" +Ne 44 "/Ethernet_Phy/ETH_COL" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_INT" +Ne 45 "/Ethernet_Phy/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/NF_D6" +Ne 132 "/FPGA_Spartan6/NF_D6" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/NF_D4" +Ne 131 "/FPGA_Spartan6/NF_D4" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/NF_D2" +Ne 129 "/FPGA_Spartan6/NF_D2" Po 590 -4133 $EndPAD $PAD Sh "A14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_ALE" +Ne 224 "/Non_volatile_memories/NF_ALE" Po 983 -4133 $EndPAD $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/NF_RNB" +Ne 134 "/FPGA_Spartan6/NF_RNB" Po 1377 -4133 $EndPAD $PAD @@ -1528,21 +1558,21 @@ $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 226 "/Non_volatile_memories/SD_DAT2" +Ne 230 "/Non_volatile_memories/SD_DAT2" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 214 "/FPGA_Spartan6/SD_DAT0" +Ne 229 "/Non_volatile_memories/SD_DAT0" Po 2558 -4133 $EndPAD $PAD Sh "A19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 8 "/DBG_PRG/FPGA_TDO" Po 2952 -4133 $EndPAD $PAD @@ -1563,7 +1593,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 4133 -4133 $EndPAD $PAD @@ -1598,14 +1628,14 @@ $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2558 -3739 $EndPAD $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_RXD0" +Ne 51 "/Ethernet_Phy/ETH_RXD0" Po -2165 -3739 $EndPAD $PAD @@ -1619,21 +1649,21 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_RXER" +Ne 68 "/FPGA_Spartan6/ETH_RXER" Po -1377 -3739 $EndPAD $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -983 -3739 $EndPAD $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_CRS" +Ne 64 "/FPGA_Spartan6/ETH_CRS" Po -590 -3739 $EndPAD $PAD @@ -1647,21 +1677,21 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 220 "/Non_volatile_memories/NF_D3" +Ne 130 "/FPGA_Spartan6/NF_D3" Po 196 -3739 $EndPAD $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 590 -3739 $EndPAD $PAD Sh "B14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/NF_CLE" +Ne 126 "/FPGA_Spartan6/NF_CLE" Po 983 -3739 $EndPAD $PAD @@ -1682,14 +1712,14 @@ $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 2165 -3739 $EndPAD $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 225 "/Non_volatile_memories/SD_DAT1" +Ne 221 "/FPGA_Spartan6/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1724,7 +1754,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/FPGA_Spartan6/R_M0_A11" +Ne 144 "/FPGA_Spartan6/R_M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1752,56 +1782,56 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RXD3" +Ne 53 "/Ethernet_Phy/ETH_RXD3" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_RXD2" +Ne 67 "/FPGA_Spartan6/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_RESET_N" +Ne 65 "/FPGA_Spartan6/ETH_RESET_N" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_TXC" +Ne 55 "/Ethernet_Phy/ETH_TXC" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_TXD1" +Ne 70 "/FPGA_Spartan6/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_TXD2" +Ne 56 "/Ethernet_Phy/ETH_TXD2" Po -590 -3346 $EndPAD $PAD Sh "C11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/Non_volatile_memories/NF_D5" +Ne 226 "/Non_volatile_memories/NF_D5" Po -196 -3346 $EndPAD $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 218 "/Non_volatile_memories/NF_D0" +Ne 128 "/FPGA_Spartan6/NF_D0" Po 196 -3346 $EndPAD $PAD @@ -1815,14 +1845,14 @@ $PAD Sh "C14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/NF_WE_N" +Ne 228 "/Non_volatile_memories/NF_WE_N" Po 983 -3346 $EndPAD $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "/Non_volatile_memories/NF_RE_N" +Ne 133 "/FPGA_Spartan6/NF_RE_N" Po 1377 -3346 $EndPAD $PAD @@ -1836,14 +1866,14 @@ $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 227 "/Non_volatile_memories/SD_DAT3" +Ne 222 "/FPGA_Spartan6/SD_DAT3" Po 2165 -3346 $EndPAD $PAD Sh "C18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 9 "/DBG_PRG/FPGA_TMS" Po 2558 -3346 $EndPAD $PAD @@ -1857,7 +1887,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "/FPGA_Spartan6/R_M1_A8" +Ne 190 "/FPGA_Spartan6/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1871,21 +1901,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 186 "/FPGA_Spartan6/R_M1_A9" +Ne 191 "/FPGA_Spartan6/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/FPGA_Spartan6/R_M0_A12" +Ne 145 "/FPGA_Spartan6/R_M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/FPGA_Spartan6/R_M0_CKE" +Ne 157 "/FPGA_Spartan6/R_M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1899,7 +1929,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1913,42 +1943,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_MDIO" +Ne 49 "/Ethernet_Phy/ETH_MDIO" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_MDC" +Ne 48 "/Ethernet_Phy/ETH_MDC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_TXER" +Ne 72 "/FPGA_Spartan6/ETH_TXER" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_TXEN" +Ne 57 "/Ethernet_Phy/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_TXD0" +Ne 69 "/FPGA_Spartan6/ETH_TXD0" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/NF_D7" +Ne 227 "/Non_volatile_memories/NF_D7" Po -196 -2952 $EndPAD $PAD @@ -1969,14 +1999,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 219 "/Non_volatile_memories/NF_D1" +Ne 225 "/Non_volatile_memories/NF_D1" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/Non_volatile_memories/NF_CS1_N" +Ne 127 "/FPGA_Spartan6/NF_CS1_N" Po 1377 -2952 $EndPAD $PAD @@ -1990,14 +2020,14 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 224 "/Non_volatile_memories/SD_CMD" +Ne 220 "/FPGA_Spartan6/SD_CMD" Po 2165 -2952 $EndPAD $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 2558 -2952 $EndPAD $PAD @@ -2018,35 +2048,35 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/FPGA_Spartan6/R_M1_CKE" +Ne 195 "/FPGA_Spartan6/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/FPGA_Spartan6/R_M1_A12" +Ne 184 "/FPGA_Spartan6/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA_Spartan6/R_M0_A9" +Ne 153 "/FPGA_Spartan6/R_M0_A9" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA_Spartan6/R_M0_A8" +Ne 152 "/FPGA_Spartan6/R_M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -2074,7 +2104,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -1771 -2558 $EndPAD $PAD @@ -2102,7 +2132,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -196 -2558 $EndPAD $PAD @@ -2130,14 +2160,14 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 1377 -2558 $EndPAD $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 223 "/Non_volatile_memories/SD_CLK" +Ne 219 "/FPGA_Spartan6/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -2151,7 +2181,7 @@ $PAD Sh "E18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 7 "/DBG_PRG/FPGA_TDI" Po 2558 -2558 $EndPAD $PAD @@ -2165,21 +2195,21 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/FPGA_Spartan6/R_M1_A7" +Ne 189 "/FPGA_Spartan6/R_M1_A7" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 180 "/FPGA_Spartan6/R_M1_A2" +Ne 185 "/FPGA_Spartan6/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -2193,14 +2223,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/FPGA_Spartan6/R_M0_WE#" +Ne 179 "/FPGA_Spartan6/R_M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/FPGA_Spartan6/R_M0_A4" +Ne 148 "/FPGA_Spartan6/R_M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -2312,7 +2342,7 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/FPGA_Spartan6/R_M1_A11" +Ne 183 "/FPGA_Spartan6/R_M1_A11" Po 2952 -2165 $EndPAD $PAD @@ -2326,21 +2356,21 @@ $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/FPGA_Spartan6/R_M1_A0" +Ne 180 "/FPGA_Spartan6/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/FPGA_Spartan6/R_M1_A1" +Ne 181 "/FPGA_Spartan6/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/FPGA_Spartan6/R_M0_BA1" +Ne 155 "/FPGA_Spartan6/R_M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -2354,21 +2384,21 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_Spartan6/R_M0_BA0" +Ne 154 "/FPGA_Spartan6/R_M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/FPGA_Spartan6/R_M0_A10" +Ne 143 "/FPGA_Spartan6/R_M0_A10" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2558 -1771 $EndPAD $PAD @@ -2438,7 +2468,7 @@ $PAD Sh "G15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 6 "/DBG_PRG/FPGA_TCK" Po 1377 -1771 $EndPAD $PAD @@ -2459,21 +2489,21 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/FPGA_Spartan6/R_M1_A10" +Ne 182 "/FPGA_Spartan6/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/FPGA_Spartan6/R_M1_A3" +Ne 186 "/FPGA_Spartan6/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2494,49 +2524,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA_Spartan6/R_M0_A1" +Ne 142 "/FPGA_Spartan6/R_M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_Spartan6/R_M0_A0" +Ne 141 "/FPGA_Spartan6/R_M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_CLK#" +Ne 85 "/FPGA_Spartan6/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_CLK" +Ne 84 "/FPGA_Spartan6/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/FPGA_Spartan6/R_M0_A2" +Ne 146 "/FPGA_Spartan6/R_M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA_Spartan6/R_M0_A7" +Ne 151 "/FPGA_Spartan6/R_M0_A7" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -1771 -1377 $EndPAD $PAD @@ -2599,7 +2629,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/FPGA_Spartan6/R_M1_CS#" +Ne 196 "/FPGA_Spartan6/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -2620,56 +2650,56 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 213 "/FPGA_Spartan6/R_M1_WE#" +Ne 218 "/FPGA_Spartan6/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_CLK" +Ne 31 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 210 "/FPGA_Spartan6/R_M1_RAS#" +Ne 215 "/FPGA_Spartan6/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/FPGA_Spartan6/R_M1_CAS#" +Ne 194 "/FPGA_Spartan6/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/FPGA_Spartan6/R_M0_DQ5" +Ne 169 "/FPGA_Spartan6/R_M0_DQ5" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/FPGA_Spartan6/R_M0_DQ4" +Ne 168 "/FPGA_Spartan6/R_M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA_Spartan6/R_M0_A6" +Ne 150 "/FPGA_Spartan6/R_M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2704,7 +2734,7 @@ $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -983 -983 $EndPAD $PAD @@ -2718,7 +2748,7 @@ $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -196 -983 $EndPAD $PAD @@ -2732,7 +2762,7 @@ $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 590 -983 $EndPAD $PAD @@ -2746,7 +2776,7 @@ $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 1377 -983 $EndPAD $PAD @@ -2760,7 +2790,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/FPGA_Spartan6/R_M1_BA0" +Ne 192 "/FPGA_Spartan6/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2774,70 +2804,70 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_CLK#" +Ne 32 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 202 "/FPGA_Spartan6/R_M1_DQ4" +Ne 207 "/FPGA_Spartan6/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 203 "/FPGA_Spartan6/R_M1_DQ5" +Ne 208 "/FPGA_Spartan6/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/FPGA_Spartan6/R_M0_DQ7" +Ne 171 "/FPGA_Spartan6/R_M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/FPGA_Spartan6/R_M0_DQ6" +Ne 170 "/FPGA_Spartan6/R_M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/FPGA_Spartan6/R_M0_A5" +Ne 149 "/FPGA_Spartan6/R_M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/FPGA_Spartan6/R_M0_CAS#" +Ne 156 "/FPGA_Spartan6/R_M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/FPGA_Spartan6/R_M0_RAS#" +Ne 176 "/FPGA_Spartan6/R_M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/FPGA_Spartan6/R_M0_A3" +Ne 147 "/FPGA_Spartan6/R_M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2865,7 +2895,7 @@ $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -590 -590 $EndPAD $PAD @@ -2879,7 +2909,7 @@ $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 196 -590 $EndPAD $PAD @@ -2893,7 +2923,7 @@ $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 983 -590 $EndPAD $PAD @@ -2914,7 +2944,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/FPGA_Spartan6/R_M1_BA1" +Ne 193 "/FPGA_Spartan6/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2928,28 +2958,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/FPGA_Spartan6/R_M1_A6" +Ne 188 "/FPGA_Spartan6/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/FPGA_Spartan6/R_M1_A5" +Ne 187 "/FPGA_Spartan6/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 204 "/FPGA_Spartan6/R_M1_DQ6" +Ne 209 "/FPGA_Spartan6/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 205 "/FPGA_Spartan6/R_M1_DQ7" +Ne 210 "/FPGA_Spartan6/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2970,21 +3000,21 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/FPGA_Spartan6/R_M0_LDQS" +Ne 175 "/FPGA_Spartan6/R_M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/FPGA_Spartan6/R_M0_LDM" +Ne 174 "/FPGA_Spartan6/R_M0_LDM" Po -2952 -196 $EndPAD $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2558 -196 $EndPAD $PAD @@ -3012,7 +3042,7 @@ $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -983 -196 $EndPAD $PAD @@ -3026,7 +3056,7 @@ $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -196 -196 $EndPAD $PAD @@ -3040,7 +3070,7 @@ $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 590 -196 $EndPAD $PAD @@ -3075,21 +3105,21 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 208 "/FPGA_Spartan6/R_M1_LDM" +Ne 213 "/FPGA_Spartan6/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 209 "/FPGA_Spartan6/R_M1_LDQS" +Ne 214 "/FPGA_Spartan6/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -3110,21 +3140,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_Spartan6/R_M0_DQ3" +Ne 167 "/FPGA_Spartan6/R_M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_Spartan6/R_M0_DQ2" +Ne 166 "/FPGA_Spartan6/R_M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/FPGA_Spartan6/R_M0_UDM" +Ne 177 "/FPGA_Spartan6/R_M0_UDM" Po -3346 196 $EndPAD $PAD @@ -3173,7 +3203,7 @@ $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -590 196 $EndPAD $PAD @@ -3187,7 +3217,7 @@ $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 196 196 $EndPAD $PAD @@ -3201,7 +3231,7 @@ $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 983 196 $EndPAD $PAD @@ -3229,7 +3259,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 230 "/USB/USBA_VM" +Ne 233 "/USB/USBA_VM" Po 2558 196 $EndPAD $PAD @@ -3243,42 +3273,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 211 "/FPGA_Spartan6/R_M1_UDM" +Ne 216 "/FPGA_Spartan6/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 200 "/FPGA_Spartan6/R_M1_DQ2" +Ne 205 "/FPGA_Spartan6/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "/FPGA_Spartan6/R_M1_DQ3" +Ne 206 "/FPGA_Spartan6/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_Spartan6/R_M0_DQ1" +Ne 159 "/FPGA_Spartan6/R_M0_DQ1" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_Spartan6/R_M0_DQ0" +Ne 158 "/FPGA_Spartan6/R_M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -3320,7 +3350,7 @@ $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -983 590 $EndPAD $PAD @@ -3334,7 +3364,7 @@ $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -196 590 $EndPAD $PAD @@ -3348,7 +3378,7 @@ $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 590 590 $EndPAD $PAD @@ -3362,21 +3392,21 @@ $PAD Sh "N15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 235 "GND" Po 1377 590 $EndPAD $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 215 "/FPGA_Spartan6/USBA_RCV" +Ne 232 "/USB/USBA_RCV" Po 1771 590 $EndPAD $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 2165 590 $EndPAD $PAD @@ -3397,35 +3427,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 192 "/FPGA_Spartan6/R_M1_DQ0" +Ne 197 "/FPGA_Spartan6/R_M1_DQ0" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 193 "/FPGA_Spartan6/R_M1_DQ1" +Ne 198 "/FPGA_Spartan6/R_M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/FPGA_Spartan6/R_M0_DQ9" +Ne 173 "/FPGA_Spartan6/R_M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/FPGA_Spartan6/R_M0_DQ8" +Ne 172 "/FPGA_Spartan6/R_M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3481,7 +3511,7 @@ $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -590 983 $EndPAD $PAD @@ -3495,7 +3525,7 @@ $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 196 983 $EndPAD $PAD @@ -3509,7 +3539,7 @@ $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 983 983 $EndPAD $PAD @@ -3530,14 +3560,14 @@ $PAD Sh "P17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 216 "/FPGA_Spartan6/USBA_VP" +Ne 234 "/USB/USBA_VP" Po 2165 983 $EndPAD $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 228 "/USB/USBA_OE_N" +Ne 231 "/USB/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -3558,21 +3588,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "/FPGA_Spartan6/R_M1_DQ8" +Ne 211 "/FPGA_Spartan6/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 207 "/FPGA_Spartan6/R_M1_DQ9" +Ne 212 "/FPGA_Spartan6/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/FPGA_Spartan6/R_M0_DQ11" +Ne 161 "/FPGA_Spartan6/R_M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3586,7 +3616,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/FPGA_Spartan6/R_M0_DQ10" +Ne 160 "/FPGA_Spartan6/R_M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3600,7 +3630,7 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2558 1377 $EndPAD $PAD @@ -3691,21 +3721,21 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 2558 1377 $EndPAD $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "/USB/USBA_SPD" +Ne 223 "/FPGA_Spartan6/USBA_SPD" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 194 "/FPGA_Spartan6/R_M1_DQ10" +Ne 199 "/FPGA_Spartan6/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3719,7 +3749,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 195 "/FPGA_Spartan6/R_M1_DQ11" +Ne 200 "/FPGA_Spartan6/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3733,7 +3763,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/FPGA_Spartan6/R_M0_UDQS" +Ne 178 "/FPGA_Spartan6/R_M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3754,7 +3784,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/PROG_CSO" +Ne 136 "/FPGA_Spartan6/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -3782,7 +3812,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -983 1771 $EndPAD $PAD @@ -3810,7 +3840,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po 590 1771 $EndPAD $PAD @@ -3866,7 +3896,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 212 "/FPGA_Spartan6/R_M1_UDQS" +Ne 217 "/FPGA_Spartan6/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3880,21 +3910,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_Spartan6/R_M0_DQ13" +Ne 163 "/FPGA_Spartan6/R_M0_DQ13" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_Spartan6/R_M0_DQ12" +Ne 162 "/FPGA_Spartan6/R_M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3922,7 +3952,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -1771 2165 $EndPAD $PAD @@ -3964,14 +3994,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_Spartan6/PROG_MISO3" +Ne 140 "/FPGA_Spartan6/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Spartan6/PROG_MISO2" +Ne 139 "/FPGA_Spartan6/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -4013,35 +4043,35 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 196 "/FPGA_Spartan6/R_M1_DQ12" +Ne 201 "/FPGA_Spartan6/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 197 "/FPGA_Spartan6/R_M1_DQ13" +Ne 202 "/FPGA_Spartan6/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/FPGA_Spartan6/R_M0_DQ15" +Ne 165 "/FPGA_Spartan6/R_M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/FPGA_Spartan6/R_M0_DQ14" +Ne 164 "/FPGA_Spartan6/R_M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -4055,7 +4085,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2952 2558 $EndPAD $PAD @@ -4083,7 +4113,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -1377 2558 $EndPAD $PAD @@ -4097,7 +4127,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -590 2558 $EndPAD $PAD @@ -4111,7 +4141,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po 196 2558 $EndPAD $PAD @@ -4125,7 +4155,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 983 2558 $EndPAD $PAD @@ -4139,7 +4169,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po 1771 2558 $EndPAD $PAD @@ -4174,14 +4204,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 198 "/FPGA_Spartan6/R_M1_DQ14" +Ne 203 "/FPGA_Spartan6/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 199 "/FPGA_Spartan6/R_M1_DQ15" +Ne 204 "/FPGA_Spartan6/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -4216,7 +4246,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -2558 2952 $EndPAD $PAD @@ -4230,7 +4260,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -1771 2952 $EndPAD $PAD @@ -4293,7 +4323,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 1771 2952 $EndPAD $PAD @@ -4314,7 +4344,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 2952 2952 $EndPAD $PAD @@ -4475,7 +4505,7 @@ $PAD Sh "Y20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 4 "+3.3V" Po 3346 3346 $EndPAD $PAD @@ -4489,14 +4519,14 @@ $PAD Sh "Y22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 236 "N-000127" Po 4133 3346 $EndPAD $PAD Sh "AA1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 237 "N-000132" Po -4133 3739 $EndPAD $PAD @@ -4510,7 +4540,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -3346 3739 $EndPAD $PAD @@ -4524,7 +4554,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2558 3739 $EndPAD $PAD @@ -4538,7 +4568,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -1771 3739 $EndPAD $PAD @@ -4552,7 +4582,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -983 3739 $EndPAD $PAD @@ -4566,7 +4596,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -196 3739 $EndPAD $PAD @@ -4580,7 +4610,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 590 3739 $EndPAD $PAD @@ -4594,7 +4624,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po 1377 3739 $EndPAD $PAD @@ -4608,7 +4638,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 2165 3739 $EndPAD $PAD @@ -4622,21 +4652,21 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po 2952 3739 $EndPAD $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Spartan6/PROG_MISO1" +Ne 138 "/FPGA_Spartan6/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/PROG_CCLK" +Ne 135 "/FPGA_Spartan6/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -4650,7 +4680,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -4133 4133 $EndPAD $PAD @@ -4783,7 +4813,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Spartan6/PROG_MISO0" +Ne 137 "/FPGA_Spartan6/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -4797,7 +4827,7 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 @@ -4819,7 +4849,7 @@ $PAD Sh "PAD" R 904 628 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 0 0 $EndPAD $PAD @@ -4840,7 +4870,7 @@ $PAD Sh "2" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -196 491 $EndPAD $PAD @@ -4882,7 +4912,7 @@ $PAD Sh "5" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 393 491 $EndPAD $PAD @@ -4917,7 +4947,7 @@ $PAD Sh "2" R 157 236 0 0 1350 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4945,7 +4975,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4966,14 +4996,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 172 "/FPGA_Spartan6/R_M0_UDM" +Ne 177 "/FPGA_Spartan6/R_M0_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 92 "/FPGA_Spartan6/M0_UDM" +Ne 20 "/DDR_Banks/M0_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4994,14 +5024,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 173 "/FPGA_Spartan6/R_M0_UDQS" +Ne 178 "/FPGA_Spartan6/R_M0_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 17 "/DDR_Banks/M0_UDQS" +Ne 101 "/FPGA_Spartan6/M0_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5022,14 +5052,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 152 "/FPGA_Spartan6/R_M0_CKE" +Ne 157 "/FPGA_Spartan6/R_M0_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 76 "/FPGA_Spartan6/M0_CKE" +Ne 15 "/DDR_Banks/M0_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5050,14 +5080,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 77 "/FPGA_Spartan6/M0_CLK" +Ne 84 "/FPGA_Spartan6/M0_CLK" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 11 "/DDR_Banks/M0_CLK#" +Ne 85 "/FPGA_Spartan6/M0_CLK#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5076,56 +5106,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 136 "/FPGA_Spartan6/R_M0_A0" +Ne 141 "/FPGA_Spartan6/R_M0_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 137 "/FPGA_Spartan6/R_M0_A1" +Ne 142 "/FPGA_Spartan6/R_M0_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 141 "/FPGA_Spartan6/R_M0_A2" +Ne 146 "/FPGA_Spartan6/R_M0_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/FPGA_Spartan6/R_M0_A3" +Ne 147 "/FPGA_Spartan6/R_M0_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 70 "/FPGA_Spartan6/M0_A3" +Ne 12 "/DDR_Banks/M0_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 69 "/FPGA_Spartan6/M0_A2" +Ne 11 "/DDR_Banks/M0_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 6 "/DDR_Banks/M0_A1" +Ne 73 "/FPGA_Spartan6/M0_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 65 "/FPGA_Spartan6/M0_A0" +Ne 10 "/DDR_Banks/M0_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5144,56 +5174,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/FPGA_Spartan6/R_M0_RAS#" +Ne 176 "/FPGA_Spartan6/R_M0_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/FPGA_Spartan6/R_M0_BA0" +Ne 154 "/FPGA_Spartan6/R_M0_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/FPGA_Spartan6/R_M0_BA1" +Ne 155 "/FPGA_Spartan6/R_M0_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 138 "/FPGA_Spartan6/R_M0_A10" +Ne 143 "/FPGA_Spartan6/R_M0_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 66 "/FPGA_Spartan6/M0_A10" +Ne 74 "/FPGA_Spartan6/M0_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 75 "/FPGA_Spartan6/M0_BA1" +Ne 82 "/FPGA_Spartan6/M0_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 9 "/DDR_Banks/M0_BA0" +Ne 81 "/FPGA_Spartan6/M0_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 91 "/FPGA_Spartan6/M0_RAS#" +Ne 100 "/FPGA_Spartan6/M0_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5212,56 +5242,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/FPGA_Spartan6/R_M0_LDQS" +Ne 175 "/FPGA_Spartan6/R_M0_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/FPGA_Spartan6/R_M0_LDM" +Ne 174 "/FPGA_Spartan6/R_M0_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 174 "/FPGA_Spartan6/R_M0_WE#" +Ne 179 "/FPGA_Spartan6/R_M0_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 151 "/FPGA_Spartan6/R_M0_CAS#" +Ne 156 "/FPGA_Spartan6/R_M0_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 10 "/DDR_Banks/M0_CAS#" +Ne 83 "/FPGA_Spartan6/M0_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 93 "/FPGA_Spartan6/M0_WE#" +Ne 22 "/DDR_Banks/M0_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 89 "/FPGA_Spartan6/M0_LDM" +Ne 98 "/FPGA_Spartan6/M0_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 90 "/FPGA_Spartan6/M0_LDQS" +Ne 99 "/FPGA_Spartan6/M0_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5280,56 +5310,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 146 "/FPGA_Spartan6/R_M0_A7" +Ne 151 "/FPGA_Spartan6/R_M0_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 145 "/FPGA_Spartan6/R_M0_A6" +Ne 150 "/FPGA_Spartan6/R_M0_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/FPGA_Spartan6/R_M0_A5" +Ne 149 "/FPGA_Spartan6/R_M0_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/FPGA_Spartan6/R_M0_A4" +Ne 148 "/FPGA_Spartan6/R_M0_A4" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 71 "/FPGA_Spartan6/M0_A4" +Ne 13 "/DDR_Banks/M0_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 72 "/FPGA_Spartan6/M0_A5" +Ne 77 "/FPGA_Spartan6/M0_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 7 "/DDR_Banks/M0_A6" +Ne 78 "/FPGA_Spartan6/M0_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 73 "/FPGA_Spartan6/M0_A7" +Ne 14 "/DDR_Banks/M0_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5348,56 +5378,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 140 "/FPGA_Spartan6/R_M0_A12" +Ne 145 "/FPGA_Spartan6/R_M0_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 139 "/FPGA_Spartan6/R_M0_A11" +Ne 144 "/FPGA_Spartan6/R_M0_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 148 "/FPGA_Spartan6/R_M0_A9" +Ne 153 "/FPGA_Spartan6/R_M0_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 147 "/FPGA_Spartan6/R_M0_A8" +Ne 152 "/FPGA_Spartan6/R_M0_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 8 "/DDR_Banks/M0_A8" +Ne 79 "/FPGA_Spartan6/M0_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 74 "/FPGA_Spartan6/M0_A9" +Ne 80 "/FPGA_Spartan6/M0_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 67 "/FPGA_Spartan6/M0_A11" +Ne 75 "/FPGA_Spartan6/M0_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 68 "/FPGA_Spartan6/M0_A12" +Ne 76 "/FPGA_Spartan6/M0_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5416,56 +5446,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/FPGA_Spartan6/R_M0_DQ4" +Ne 168 "/FPGA_Spartan6/R_M0_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/FPGA_Spartan6/R_M0_DQ5" +Ne 169 "/FPGA_Spartan6/R_M0_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/FPGA_Spartan6/R_M0_DQ6" +Ne 170 "/FPGA_Spartan6/R_M0_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/FPGA_Spartan6/R_M0_DQ7" +Ne 171 "/FPGA_Spartan6/R_M0_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 14 "/DDR_Banks/M0_DQ7" +Ne 95 "/FPGA_Spartan6/M0_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 88 "/FPGA_Spartan6/M0_DQ6" +Ne 19 "/DDR_Banks/M0_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 87 "/FPGA_Spartan6/M0_DQ5" +Ne 94 "/FPGA_Spartan6/M0_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 86 "/FPGA_Spartan6/M0_DQ4" +Ne 93 "/FPGA_Spartan6/M0_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5484,56 +5514,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/FPGA_Spartan6/R_M0_DQ0" +Ne 158 "/FPGA_Spartan6/R_M0_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 154 "/FPGA_Spartan6/R_M0_DQ1" +Ne 159 "/FPGA_Spartan6/R_M0_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/FPGA_Spartan6/R_M0_DQ2" +Ne 166 "/FPGA_Spartan6/R_M0_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/FPGA_Spartan6/R_M0_DQ3" +Ne 167 "/FPGA_Spartan6/R_M0_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 85 "/FPGA_Spartan6/M0_DQ3" +Ne 18 "/DDR_Banks/M0_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Spartan6/M0_DQ2" +Ne 92 "/FPGA_Spartan6/M0_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 12 "/DDR_Banks/M0_DQ1" +Ne 87 "/FPGA_Spartan6/M0_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 78 "/FPGA_Spartan6/M0_DQ0" +Ne 86 "/FPGA_Spartan6/M0_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5552,56 +5582,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/FPGA_Spartan6/R_M0_DQ8" +Ne 172 "/FPGA_Spartan6/R_M0_DQ8" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/FPGA_Spartan6/R_M0_DQ9" +Ne 173 "/FPGA_Spartan6/R_M0_DQ9" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/FPGA_Spartan6/R_M0_DQ10" +Ne 160 "/FPGA_Spartan6/R_M0_DQ10" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/FPGA_Spartan6/R_M0_DQ11" +Ne 161 "/FPGA_Spartan6/R_M0_DQ11" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 79 "/FPGA_Spartan6/M0_DQ11" +Ne 89 "/FPGA_Spartan6/M0_DQ11" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 13 "/DDR_Banks/M0_DQ10" +Ne 88 "/FPGA_Spartan6/M0_DQ10" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 16 "/DDR_Banks/M0_DQ9" +Ne 97 "/FPGA_Spartan6/M0_DQ9" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 15 "/DDR_Banks/M0_DQ8" +Ne 96 "/FPGA_Spartan6/M0_DQ8" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5620,56 +5650,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/FPGA_Spartan6/R_M0_DQ12" +Ne 162 "/FPGA_Spartan6/R_M0_DQ12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/FPGA_Spartan6/R_M0_DQ13" +Ne 163 "/FPGA_Spartan6/R_M0_DQ13" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/FPGA_Spartan6/R_M0_DQ14" +Ne 164 "/FPGA_Spartan6/R_M0_DQ14" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/FPGA_Spartan6/R_M0_DQ15" +Ne 165 "/FPGA_Spartan6/R_M0_DQ15" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 83 "/FPGA_Spartan6/M0_DQ15" +Ne 17 "/DDR_Banks/M0_DQ15" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 82 "/FPGA_Spartan6/M0_DQ14" +Ne 16 "/DDR_Banks/M0_DQ14" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 81 "/FPGA_Spartan6/M0_DQ13" +Ne 91 "/FPGA_Spartan6/M0_DQ13" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 80 "/FPGA_Spartan6/M0_DQ12" +Ne 90 "/FPGA_Spartan6/M0_DQ12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5691,28 +5721,28 @@ $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -235 -235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 235 -235 $EndPAD $PAD @@ -5824,7 +5854,7 @@ $PAD Sh "8" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 688 0 $EndPAD $PAD @@ -5873,14 +5903,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 212 "/FPGA_Spartan6/R_M1_UDQS" +Ne 217 "/FPGA_Spartan6/R_M1_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 120 "/FPGA_Spartan6/M1_UDQS" +Ne 125 "/FPGA_Spartan6/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5901,14 +5931,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 191 "/FPGA_Spartan6/R_M1_CS#" +Ne 196 "/FPGA_Spartan6/R_M1_CS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 102 "/FPGA_Spartan6/M1_CS#" +Ne 111 "/FPGA_Spartan6/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5929,14 +5959,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 190 "/FPGA_Spartan6/R_M1_CKE" +Ne 195 "/FPGA_Spartan6/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 100 "/FPGA_Spartan6/M1_CKE" +Ne 110 "/FPGA_Spartan6/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5957,14 +5987,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 211 "/FPGA_Spartan6/R_M1_UDM" +Ne 216 "/FPGA_Spartan6/R_M1_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 119 "/FPGA_Spartan6/M1_UDM" +Ne 124 "/FPGA_Spartan6/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5983,56 +6013,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 199 "/FPGA_Spartan6/R_M1_DQ15" +Ne 204 "/FPGA_Spartan6/R_M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 198 "/FPGA_Spartan6/R_M1_DQ14" +Ne 203 "/FPGA_Spartan6/R_M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 197 "/FPGA_Spartan6/R_M1_DQ13" +Ne 202 "/FPGA_Spartan6/R_M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 196 "/FPGA_Spartan6/R_M1_DQ12" +Ne 201 "/FPGA_Spartan6/R_M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/FPGA_Spartan6/M1_DQ12" +Ne 114 "/FPGA_Spartan6/M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 108 "/FPGA_Spartan6/M1_DQ13" +Ne 115 "/FPGA_Spartan6/M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Banks/M1_DQ14" +Ne 35 "/DDR_Banks/M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/DDR_Banks/M1_DQ15" +Ne 116 "/FPGA_Spartan6/M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6051,56 +6081,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 195 "/FPGA_Spartan6/R_M1_DQ11" +Ne 200 "/FPGA_Spartan6/R_M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 194 "/FPGA_Spartan6/R_M1_DQ10" +Ne 199 "/FPGA_Spartan6/R_M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 207 "/FPGA_Spartan6/R_M1_DQ9" +Ne 212 "/FPGA_Spartan6/R_M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 206 "/FPGA_Spartan6/R_M1_DQ8" +Ne 211 "/FPGA_Spartan6/R_M1_DQ8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 114 "/FPGA_Spartan6/M1_DQ8" +Ne 38 "/DDR_Banks/M1_DQ8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 115 "/FPGA_Spartan6/M1_DQ9" +Ne 121 "/FPGA_Spartan6/M1_DQ9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 105 "/FPGA_Spartan6/M1_DQ10" +Ne 34 "/DDR_Banks/M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 106 "/FPGA_Spartan6/M1_DQ11" +Ne 113 "/FPGA_Spartan6/M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6121,14 +6151,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 101 "/FPGA_Spartan6/M1_CLK#" +Ne 32 "/DDR_Banks/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/DDR_Banks/M1_CLK" +Ne 31 "/DDR_Banks/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6147,56 +6177,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 179 "/FPGA_Spartan6/R_M1_A12" +Ne 184 "/FPGA_Spartan6/R_M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 178 "/FPGA_Spartan6/R_M1_A11" +Ne 183 "/FPGA_Spartan6/R_M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 186 "/FPGA_Spartan6/R_M1_A9" +Ne 191 "/FPGA_Spartan6/R_M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "/FPGA_Spartan6/R_M1_A8" +Ne 190 "/FPGA_Spartan6/R_M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Banks/M1_A8" +Ne 28 "/DDR_Banks/M1_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 98 "/FPGA_Spartan6/M1_A9" +Ne 29 "/DDR_Banks/M1_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/DDR_Banks/M1_A11" +Ne 24 "/DDR_Banks/M1_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 96 "/FPGA_Spartan6/M1_A12" +Ne 25 "/DDR_Banks/M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6215,21 +6245,21 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/FPGA_Spartan6/R_M1_A7" +Ne 189 "/FPGA_Spartan6/R_M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/FPGA_Spartan6/R_M1_A6" +Ne 188 "/FPGA_Spartan6/R_M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/FPGA_Spartan6/R_M1_A5" +Ne 187 "/FPGA_Spartan6/R_M1_A5" Po 98 -177 $EndPAD $PAD @@ -6243,28 +6273,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 22 "/DDR_Banks/M1_A4" +Ne 106 "/FPGA_Spartan6/M1_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/DDR_Banks/M1_A5" +Ne 26 "/DDR_Banks/M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Banks/M1_A6" +Ne 27 "/DDR_Banks/M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M1_A7" +Ne 107 "/FPGA_Spartan6/M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6283,56 +6313,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 192 "/FPGA_Spartan6/R_M1_DQ0" +Ne 197 "/FPGA_Spartan6/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 193 "/FPGA_Spartan6/R_M1_DQ1" +Ne 198 "/FPGA_Spartan6/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 200 "/FPGA_Spartan6/R_M1_DQ2" +Ne 205 "/FPGA_Spartan6/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "/FPGA_Spartan6/R_M1_DQ3" +Ne 206 "/FPGA_Spartan6/R_M1_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 110 "/FPGA_Spartan6/M1_DQ3" +Ne 36 "/DDR_Banks/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 109 "/FPGA_Spartan6/M1_DQ2" +Ne 117 "/FPGA_Spartan6/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/FPGA_Spartan6/M1_DQ1" +Ne 112 "/FPGA_Spartan6/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/FPGA_Spartan6/M1_DQ0" +Ne 33 "/DDR_Banks/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6351,56 +6381,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 209 "/FPGA_Spartan6/R_M1_LDQS" +Ne 214 "/FPGA_Spartan6/R_M1_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 208 "/FPGA_Spartan6/R_M1_LDM" +Ne 213 "/FPGA_Spartan6/R_M1_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 213 "/FPGA_Spartan6/R_M1_WE#" +Ne 218 "/FPGA_Spartan6/R_M1_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 189 "/FPGA_Spartan6/R_M1_CAS#" +Ne 194 "/FPGA_Spartan6/R_M1_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M1_CAS#" +Ne 109 "/FPGA_Spartan6/M1_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 121 "/FPGA_Spartan6/M1_WE#" +Ne 41 "/DDR_Banks/M1_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 116 "/FPGA_Spartan6/M1_LDM" +Ne 122 "/FPGA_Spartan6/M1_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 117 "/FPGA_Spartan6/M1_LDQS" +Ne 39 "/DDR_Banks/M1_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6419,56 +6449,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 202 "/FPGA_Spartan6/R_M1_DQ4" +Ne 207 "/FPGA_Spartan6/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 203 "/FPGA_Spartan6/R_M1_DQ5" +Ne 208 "/FPGA_Spartan6/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 204 "/FPGA_Spartan6/R_M1_DQ6" +Ne 209 "/FPGA_Spartan6/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 205 "/FPGA_Spartan6/R_M1_DQ7" +Ne 210 "/FPGA_Spartan6/R_M1_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 113 "/FPGA_Spartan6/M1_DQ7" +Ne 37 "/DDR_Banks/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 112 "/FPGA_Spartan6/M1_DQ6" +Ne 120 "/FPGA_Spartan6/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 111 "/FPGA_Spartan6/M1_DQ5" +Ne 119 "/FPGA_Spartan6/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Banks/M1_DQ4" +Ne 118 "/FPGA_Spartan6/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6487,56 +6517,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 210 "/FPGA_Spartan6/R_M1_RAS#" +Ne 215 "/FPGA_Spartan6/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 187 "/FPGA_Spartan6/R_M1_BA0" +Ne 192 "/FPGA_Spartan6/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 188 "/FPGA_Spartan6/R_M1_BA1" +Ne 193 "/FPGA_Spartan6/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 177 "/FPGA_Spartan6/R_M1_A10" +Ne 182 "/FPGA_Spartan6/R_M1_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/FPGA_Spartan6/M1_A10" +Ne 23 "/DDR_Banks/M1_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 99 "/FPGA_Spartan6/M1_BA1" +Ne 30 "/DDR_Banks/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Banks/M1_BA0" +Ne 108 "/FPGA_Spartan6/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "/FPGA_Spartan6/M1_RAS#" +Ne 123 "/FPGA_Spartan6/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6555,56 +6585,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 175 "/FPGA_Spartan6/R_M1_A0" +Ne 180 "/FPGA_Spartan6/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 176 "/FPGA_Spartan6/R_M1_A1" +Ne 181 "/FPGA_Spartan6/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 180 "/FPGA_Spartan6/R_M1_A2" +Ne 185 "/FPGA_Spartan6/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/FPGA_Spartan6/R_M1_A3" +Ne 186 "/FPGA_Spartan6/R_M1_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 97 "/FPGA_Spartan6/M1_A3" +Ne 105 "/FPGA_Spartan6/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 21 "/DDR_Banks/M1_A2" +Ne 104 "/FPGA_Spartan6/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/FPGA_Spartan6/M1_A1" +Ne 103 "/FPGA_Spartan6/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 19 "/DDR_Banks/M1_A0" +Ne 102 "/FPGA_Spartan6/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6625,7 +6655,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -176 0 $EndPAD $PAD @@ -6653,14 +6683,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/Ethernet_Phy/ETH_A1.8V" +Ne 42 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 50 "/Ethernet_Phy/ETH_PLL1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6688,35 +6718,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/Ethernet_Phy/ETH_A1.8V" -Po 176 0 -$EndPAD -$EndMODULE 0402 -$MODULE 0402 -Po 51200 25300 1800 0 4C5FF890 4C5D7FB7 ~~ -Li 0402 -Sc 4C5D7FB7 -AR /4C4320F3/4C5D7FB7 -Op 0 0 0 -At SMD -T0 0 150 200 200 1800 40 M V 20 N"L2" -T1 0 -150 200 200 1800 40 M I 20 N"FB" -DS -305 -168 -305 168 50 20 -DS -305 168 305 168 50 20 -DS 305 168 305 -168 50 20 -DS 305 -168 -305 -168 50 20 -$PAD -Sh "1" R 157 236 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 4 "+3.3V" -Po -176 0 -$EndPAD -$PAD -Sh "2" R 157 236 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 35 "/Ethernet_Phy/ETH_A3.3V" +Ne 42 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6744,7 +6746,7 @@ $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -6772,7 +6774,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6800,7 +6802,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6828,7 +6830,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6856,7 +6858,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6883,56 +6885,56 @@ $PAD Sh "8" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -750 -1050 $EndPAD $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/PROG_CSO" +Ne 136 "/FPGA_Spartan6/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_Spartan6/PROG_MISO3" +Ne 140 "/FPGA_Spartan6/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/PROG_CCLK" +Ne 135 "/FPGA_Spartan6/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Spartan6/PROG_MISO0" +Ne 137 "/FPGA_Spartan6/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Spartan6/PROG_MISO1" +Ne 138 "/FPGA_Spartan6/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Spartan6/PROG_MISO2" +Ne 139 "/FPGA_Spartan6/PROG_MISO2" Po 250 1050 $EndPAD $PAD Sh "4" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 750 1050 $EndPAD $SHAPE3D @@ -6966,7 +6968,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -6994,7 +6996,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7022,7 +7024,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7050,7 +7052,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7078,7 +7080,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7106,7 +7108,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7127,14 +7129,14 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7162,7 +7164,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7190,7 +7192,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7218,7 +7220,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7246,7 +7248,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7274,7 +7276,7 @@ $PAD Sh "2" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7302,7 +7304,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7323,14 +7325,14 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7358,7 +7360,7 @@ $PAD Sh "2" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7386,7 +7388,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7414,7 +7416,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7442,7 +7444,7 @@ $PAD Sh "2" R 157 236 0 0 2250 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7470,7 +7472,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7498,7 +7500,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7526,7 +7528,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7554,7 +7556,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7582,7 +7584,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7603,14 +7605,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7638,7 +7640,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7666,7 +7668,7 @@ $PAD Sh "2" R 157 236 0 0 1350 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7687,14 +7689,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7722,7 +7724,7 @@ $PAD Sh "2" R 157 236 0 0 450 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7750,7 +7752,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7771,14 +7773,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7806,7 +7808,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7827,14 +7829,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 251 "VCCO2" +Ne 257 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7905,14 +7907,14 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 767 -1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 767 1112 $EndPAD $PAD @@ -7926,14 +7928,14 @@ $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 242 "N-000431" +Ne 248 "N-000429" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 243 "N-000432" +Ne 249 "N-000430" Po 0 1112 $EndPAD $PAD @@ -7975,7 +7977,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 235 "N-000422" +Ne 244 "N-000425" Po -570 0 $EndPAD $PAD @@ -8010,7 +8012,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -8038,7 +8040,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -8059,14 +8061,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 243 "N-000432" +Ne 249 "N-000430" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8087,14 +8089,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 242 "N-000431" +Ne 248 "N-000429" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8122,7 +8124,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8143,14 +8145,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 244 "N-000433" +Ne 250 "N-000431" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8171,14 +8173,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 244 "N-000433" +Ne 250 "N-000431" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8206,7 +8208,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8227,7 +8229,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 235 "N-000422" +Ne 244 "N-000425" Po -294 0 $EndPAD $PAD @@ -8255,14 +8257,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 240 "N-000429" +Ne 246 "N-000427" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 239 "N-000427" +Ne 245 "N-000426" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8283,14 +8285,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 237 "N-000425" +Ne 242 "N-000415" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8311,14 +8313,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_VREF" +Ne 40 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8346,7 +8348,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8374,7 +8376,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8402,7 +8404,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8430,7 +8432,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8458,7 +8460,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8486,7 +8488,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8514,7 +8516,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8542,7 +8544,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8570,7 +8572,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8598,7 +8600,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8626,7 +8628,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8654,7 +8656,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8682,7 +8684,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_VREF" +Ne 40 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8703,14 +8705,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Banks/M0_VREF" +Ne 21 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8738,7 +8740,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Banks/M0_VREF" +Ne 21 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8766,7 +8768,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_VREF" +Ne 40 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8787,14 +8789,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_VREF" +Ne 40 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8815,14 +8817,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Banks/M0_VREF" +Ne 21 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8850,12 +8852,12 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Banks/M0_VREF" +Ne 21 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE USB-48204 -Po 56200 18910 1800 15 4C5F28A8 4C5F23DD ~~ +Po 56354 18323 1800 15 4C5F28A8 4C5F23DD ~~ Li USB-48204 Sc 4C5F23DD AR /4C5F1EDC/4C5F23DD @@ -8876,56 +8878,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 239 "N-000427" +Ne 245 "N-000426" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 238 "N-000426" +Ne 243 "N-000416" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 241 "N-000430" +Ne 247 "N-000428" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 241 "N-000430" +Ne 247 "N-000428" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 236 "N-000424" +Ne 241 "N-000414" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 236 "N-000424" +Ne 241 "N-000414" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 236 "N-000424" +Ne 241 "N-000414" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 236 "N-000424" +Ne 241 "N-000414" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -8946,7 +8948,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 240 "N-000429" +Ne 246 "N-000427" Po -570 0 $EndPAD $PAD @@ -8958,58 +8960,58 @@ Po 570 0 $EndPAD $EndMODULE 1210 $MODULE 0603 -Po 51200 24400 1800 15 4C5FF890 4C5D7F9F ~~ +Po 47209 23642 0 15 4C5FF890 4C5D7F9F ~~ Li 0603 Sc 4C5D7F9F AR /4C4320F3/4C5D7F9F Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C1" -T1 0 150 200 200 1800 40 N I 25 N"1uF" +T0 0 -150 200 200 0 40 N V 25 N"C1" +T1 0 150 200 200 0 40 N I 25 N"1uF" DS -443 227 -443 -227 50 21 DS -443 -227 443 -227 50 21 DS 443 -227 443 227 50 21 DS 443 227 -443 227 50 21 $PAD -Sh "1" R 197 354 0 0 1800 +Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -294 0 $EndPAD $PAD -Sh "2" R 197 354 0 0 1800 +Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 63674 20567 1800 15 4C5FF890 4C5D7FA5 ~~ +Po 46350 24551 900 15 4C5FF890 4C5D7FA5 ~~ Li 0603 Sc 4C5D7FA5 AR /4C4320F3/4C5D7FA5 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C7" -T1 0 150 200 200 1800 40 N I 25 N"1uF" +T0 0 -150 200 200 900 40 N V 25 N"C7" +T1 0 150 200 200 900 40 N I 25 N"1uF" DS -443 227 -443 -227 50 21 DS -443 -227 443 -227 50 21 DS 443 -227 443 227 50 21 DS 443 227 -443 227 50 21 $PAD -Sh "1" R 197 354 0 0 1800 +Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_A3.3V" +Ne 43 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD -Sh "2" R 197 354 0 0 1800 +Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9037,7 +9039,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9065,7 +9067,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9093,7 +9095,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9114,14 +9116,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 241 "N-000430" +Ne 247 "N-000428" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9142,14 +9144,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 238 "N-000426" +Ne 243 "N-000416" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9177,35 +9179,35 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51200 24900 1800 0 4C5FF890 4C5D7FA1 ~~ +Po 46965 23445 0 0 4C5FF890 4C5D7FA1 ~~ Li 0402 Sc 4C5D7FA1 AR /4C4320F3/4C5D7FA1 Op 0 0 0 At SMD -T0 0 150 200 200 1800 40 M V 20 N"C3" -T1 0 -150 200 200 1800 40 M I 20 N"100nF" +T0 0 150 200 200 0 40 M V 20 N"C3" +T1 0 -150 200 200 0 40 M I 20 N"100nF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 1800 +Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 1800 +Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9233,35 +9235,35 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 50000 28346 1800 0 4C5FF890 4C5D7FA3 ~~ +Po 46953 23858 0 0 4C5FF890 4C5D7FA3 ~~ Li 0402 Sc 4C5D7FA3 AR /4C4320F3/4C5D7FA3 Op 0 0 0 At SMD -T0 0 150 200 200 1800 40 M V 20 N"C5" -T1 0 -150 200 200 1800 40 M I 20 N"100nF" +T0 0 150 200 200 0 40 M V 20 N"C5" +T1 0 -150 200 200 0 40 M I 20 N"100nF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 1800 +Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 Ne 4 "+3.3V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 1800 +Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9282,14 +9284,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/Ethernet_Phy/ETH_A1.8V" +Ne 42 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9310,14 +9312,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/Ethernet_Phy/ETH_A3.3V" +Ne 43 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9338,14 +9340,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 50 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9373,7 +9375,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9401,7 +9403,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9422,14 +9424,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 48 "/Ethernet_Phy/MAG_SHIELD" +Ne 60 "/Ethernet_Phy/MAG_SHIELD" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9450,19 +9452,19 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 236 "N-000424" +Ne 241 "N-000414" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 47224 28337 1800 0 4C5FF890 4C5D7F39 ~~ +Po 47185 27878 1800 0 4C5FF890 4C5D7F39 ~~ Li 0402 Sc 4C5D7F39 AR /4C4320F3/4C5D7F39 @@ -9478,7 +9480,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 54 "/FPGA_Spartan6/ETH_MDIO" +Ne 49 "/Ethernet_Phy/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -9490,30 +9492,30 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46654 25059 2700 0 4C5FF890 4C5D7ECF ~~ +Po 47043 25087 900 0 4C5FF890 4C5D7ECF ~~ Li 0402 Sc 4C5D7ECF AR /4C4320F3/4C5D7ECF Op 0 0 0 At SMD -T0 0 150 200 200 2700 40 M V 20 N"R2" -T1 0 -150 200 200 2700 40 M I 20 N"6.65K" +T0 0 150 200 200 900 40 M V 20 N"R2" +T1 0 -150 200 200 900 40 M I 20 N"6.65K" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 2700 +Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 233 "N-000397" +Ne 240 "N-000395" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 2700 +Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9541,7 +9543,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 49 "/Ethernet_Phy/MAG_TX+" +Ne 61 "/Ethernet_Phy/MAG_TX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9569,7 +9571,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 50 "/Ethernet_Phy/MAG_TX-" +Ne 62 "/Ethernet_Phy/MAG_TX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9597,7 +9599,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/Ethernet_Phy/MAG_RX+" +Ne 58 "/Ethernet_Phy/MAG_RX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9625,7 +9627,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/MAG_RX-" +Ne 59 "/Ethernet_Phy/MAG_RX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9646,14 +9648,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 232 "N-000395" +Ne 238 "N-000393" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/Ethernet_Phy/ETH_LED0" +Ne 46 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9674,14 +9676,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 234 "N-000398" +Ne 239 "N-000394" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/Ethernet_Phy/ETH_LED1" +Ne 47 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9702,14 +9704,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 48 "/Ethernet_Phy/MAG_SHIELD" +Ne 60 "/Ethernet_Phy/MAG_SHIELD" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9730,14 +9732,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 236 "N-000424" +Ne 241 "N-000414" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9766,7 +9768,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ0" +Ne 86 "/FPGA_Spartan6/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -9780,35 +9782,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_DQ1" +Ne 87 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ2" +Ne 92 "/FPGA_Spartan6/M0_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ3" +Ne 18 "/DDR_Banks/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ4" +Ne 93 "/FPGA_Spartan6/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -9822,28 +9824,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_DQ5" +Ne 94 "/FPGA_Spartan6/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_DQ6" +Ne 19 "/DDR_Banks/M0_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ7" +Ne 95 "/FPGA_Spartan6/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -9864,7 +9866,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M0_LDQS" +Ne 99 "/FPGA_Spartan6/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -9892,35 +9894,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M0_LDM" +Ne 98 "/FPGA_Spartan6/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M0_WE#" +Ne 22 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_CAS#" +Ne 83 "/FPGA_Spartan6/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M0_RAS#" +Ne 100 "/FPGA_Spartan6/M0_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 1791 2176 $EndPAD $PAD @@ -9934,49 +9936,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_BA0" +Ne 81 "/FPGA_Spartan6/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_BA1" +Ne 82 "/FPGA_Spartan6/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A10" +Ne 74 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A0" +Ne 10 "/DDR_Banks/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A1" +Ne 73 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A2" +Ne 11 "/DDR_Banks/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A3" +Ne 12 "/DDR_Banks/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -9990,63 +9992,63 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A4" +Ne 13 "/DDR_Banks/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_A5" +Ne 77 "/FPGA_Spartan6/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A6" +Ne 78 "/FPGA_Spartan6/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_A7" +Ne 14 "/DDR_Banks/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A8" +Ne 79 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_A9" +Ne 80 "/FPGA_Spartan6/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A11" +Ne 75 "/FPGA_Spartan6/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A12" +Ne 76 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -10060,42 +10062,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_CLK#" +Ne 85 "/FPGA_Spartan6/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_CKE" +Ne 15 "/DDR_Banks/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_CLK" +Ne 84 "/FPGA_Spartan6/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M0_UDM" +Ne 20 "/DDR_Banks/M0_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_VREF" +Ne 21 "/DDR_Banks/M0_VREF" Po 255 -2176 $EndPAD $PAD @@ -10109,14 +10111,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_UDQS" +Ne 101 "/FPGA_Spartan6/M0_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -511 -2176 $EndPAD $PAD @@ -10130,7 +10132,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ8" +Ne 96 "/FPGA_Spartan6/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10144,35 +10146,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ9" +Ne 97 "/FPGA_Spartan6/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ10" +Ne 88 "/FPGA_Spartan6/M0_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ11" +Ne 89 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ12" +Ne 90 "/FPGA_Spartan6/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10186,35 +10188,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ13" +Ne 91 "/FPGA_Spartan6/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ14" +Ne 16 "/DDR_Banks/M0_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ15" +Ne 17 "/DDR_Banks/M0_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -10243,7 +10245,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ0" +Ne 33 "/DDR_Banks/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -10257,35 +10259,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ1" +Ne 112 "/FPGA_Spartan6/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ2" +Ne 117 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ3" +Ne 36 "/DDR_Banks/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_DQ4" +Ne 118 "/FPGA_Spartan6/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -10299,28 +10301,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_DQ5" +Ne 119 "/FPGA_Spartan6/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_DQ6" +Ne 120 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_DQ7" +Ne 37 "/DDR_Banks/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -10341,7 +10343,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/M1_LDQS" +Ne 39 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -10369,35 +10371,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/M1_LDM" +Ne 122 "/FPGA_Spartan6/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/M1_WE#" +Ne 41 "/DDR_Banks/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_CAS#" +Ne 109 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/M1_RAS#" +Ne 123 "/FPGA_Spartan6/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_CS#" +Ne 111 "/FPGA_Spartan6/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -10411,49 +10413,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_BA0" +Ne 108 "/FPGA_Spartan6/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_BA1" +Ne 30 "/DDR_Banks/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A10" +Ne 23 "/DDR_Banks/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M1_A0" +Ne 102 "/FPGA_Spartan6/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A1" +Ne 103 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_A2" +Ne 104 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_A3" +Ne 105 "/FPGA_Spartan6/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -10467,63 +10469,63 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_A4" +Ne 106 "/FPGA_Spartan6/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A5" +Ne 26 "/DDR_Banks/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A6" +Ne 27 "/DDR_Banks/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A7" +Ne 107 "/FPGA_Spartan6/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_A8" +Ne 28 "/DDR_Banks/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_A9" +Ne 29 "/DDR_Banks/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_A11" +Ne 24 "/DDR_Banks/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_A12" +Ne 25 "/DDR_Banks/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -10537,42 +10539,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_CLK#" +Ne 32 "/DDR_Banks/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_CKE" +Ne 110 "/FPGA_Spartan6/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_CLK" +Ne 31 "/DDR_Banks/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/M1_UDM" +Ne 124 "/FPGA_Spartan6/M1_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_VREF" +Ne 40 "/DDR_Banks/M1_VREF" Po 255 -2176 $EndPAD $PAD @@ -10586,14 +10588,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/M1_UDQS" +Ne 125 "/FPGA_Spartan6/M1_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -511 -2176 $EndPAD $PAD @@ -10607,7 +10609,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/M1_DQ8" +Ne 38 "/DDR_Banks/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10621,35 +10623,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/M1_DQ9" +Ne 121 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ10" +Ne 34 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ11" +Ne 113 "/FPGA_Spartan6/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ12" +Ne 114 "/FPGA_Spartan6/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10663,35 +10665,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ13" +Ne 115 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ14" +Ne 35 "/DDR_Banks/M1_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ15" +Ne 116 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -10727,28 +10729,28 @@ $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 229 "/USB/USBA_SPD" +Ne 223 "/FPGA_Spartan6/USBA_SPD" Po -511 -1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 215 "/FPGA_Spartan6/USBA_RCV" +Ne 232 "/USB/USBA_RCV" Po -255 -1112 $EndPAD $PAD Sh "4" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 216 "/FPGA_Spartan6/USBA_VP" +Ne 234 "/USB/USBA_VP" Po 0 -1112 $EndPAD $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 230 "/USB/USBA_VM" +Ne 233 "/USB/USBA_VM" Po 255 -1112 $EndPAD $PAD @@ -10762,35 +10764,35 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 767 -1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 767 1112 $EndPAD $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 228 "/USB/USBA_OE_N" +Ne 231 "/USB/USBA_OE_N" Po 511 1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 238 "N-000426" +Ne 243 "N-000416" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 241 "N-000430" +Ne 247 "N-000428" Po 0 1112 $EndPAD $PAD @@ -10831,35 +10833,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 48 "/Ethernet_Phy/MAG_SHIELD" +Ne 60 "/Ethernet_Phy/MAG_SHIELD" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 48 "/Ethernet_Phy/MAG_SHIELD" +Ne 60 "/Ethernet_Phy/MAG_SHIELD" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 48 "/Ethernet_Phy/MAG_SHIELD" +Ne 60 "/Ethernet_Phy/MAG_SHIELD" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 48 "/Ethernet_Phy/MAG_SHIELD" +Ne 60 "/Ethernet_Phy/MAG_SHIELD" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 49 "/Ethernet_Phy/MAG_TX+" +Ne 61 "/Ethernet_Phy/MAG_TX+" Po -1750 -2500 $EndPAD $PAD @@ -10873,28 +10875,28 @@ $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 231 "GND" +Ne 235 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 46 "/Ethernet_Phy/MAG_RX+" +Ne 58 "/Ethernet_Phy/MAG_RX+" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 50 "/Ethernet_Phy/MAG_TX-" +Ne 62 "/Ethernet_Phy/MAG_TX-" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 231 "GND" +Ne 235 "GND" Po -250 -3500 $EndPAD $PAD @@ -10908,7 +10910,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 47 "/Ethernet_Phy/MAG_RX-" +Ne 59 "/Ethernet_Phy/MAG_RX-" Po 1750 -3500 $EndPAD $PAD @@ -10922,7 +10924,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 232 "N-000395" +Ne 238 "N-000393" Po -1150 -5400 $EndPAD $PAD @@ -10936,7 +10938,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 234 "N-000398" +Ne 239 "N-000394" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -10961,21 +10963,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 226 "/Non_volatile_memories/SD_DAT2" +Ne 230 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 227 "/Non_volatile_memories/SD_DAT3" +Ne 222 "/FPGA_Spartan6/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 224 "/Non_volatile_memories/SD_CMD" +Ne 220 "/FPGA_Spartan6/SD_CMD" Po -433 0 $EndPAD $PAD @@ -10989,56 +10991,56 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 223 "/Non_volatile_memories/SD_CLK" +Ne 219 "/FPGA_Spartan6/SD_CLK" Po 433 0 $EndPAD $PAD Sh "6" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 866 0 $EndPAD $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 214 "/FPGA_Spartan6/SD_DAT0" +Ne 229 "/Non_volatile_memories/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 225 "/Non_volatile_memories/SD_DAT1" +Ne 221 "/FPGA_Spartan6/SD_DAT1" Po 1732 0 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po -2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po -2707 -2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 231 "GND" +Ne 235 "GND" Po 2707 -2244 $EndPAD $EndMODULE MICROSD-500901 @@ -11302,28 +11304,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/NF_RNB" +Ne 134 "/FPGA_Spartan6/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/NF_RNB" +Ne 134 "/FPGA_Spartan6/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 222 "/Non_volatile_memories/NF_RE_N" +Ne 133 "/FPGA_Spartan6/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/Non_volatile_memories/NF_CS1_N" +Ne 127 "/FPGA_Spartan6/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -11351,7 +11353,7 @@ $PAD Sh "13" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 100 3850 $EndPAD $PAD @@ -11372,21 +11374,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/NF_CLE" +Ne 126 "/FPGA_Spartan6/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_ALE" +Ne 224 "/Non_volatile_memories/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/NF_WE_N" +Ne 228 "/Non_volatile_memories/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -11463,28 +11465,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 218 "/Non_volatile_memories/NF_D0" +Ne 128 "/FPGA_Spartan6/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 219 "/Non_volatile_memories/NF_D1" +Ne 225 "/Non_volatile_memories/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/NF_D2" +Ne 129 "/FPGA_Spartan6/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 220 "/Non_volatile_memories/NF_D3" +Ne 130 "/FPGA_Spartan6/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -11512,7 +11514,7 @@ $PAD Sh "36" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 100 -3850 $EndPAD $PAD @@ -11547,28 +11549,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/NF_D4" +Ne 131 "/FPGA_Spartan6/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/Non_volatile_memories/NF_D5" +Ne 226 "/Non_volatile_memories/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/NF_D6" +Ne 132 "/FPGA_Spartan6/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/NF_D7" +Ne 227 "/Non_volatile_memories/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -11618,35 +11620,35 @@ $PAD Sh "12" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -1613 1082 $EndPAD $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_RXER" +Ne 68 "/FPGA_Spartan6/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_RXC" +Ne 66 "/FPGA_Spartan6/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RXDV" +Ne 54 "/Ethernet_Phy/ETH_RXDV" Po -1613 491 $EndPAD $PAD Sh "8" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -1613 295 $EndPAD $PAD @@ -11660,63 +11662,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_RXD0" +Ne 51 "/Ethernet_Phy/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_RXD1" +Ne 52 "/Ethernet_Phy/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_RXD2" +Ne 67 "/FPGA_Spartan6/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RXD3" +Ne 53 "/Ethernet_Phy/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_MDC" +Ne 48 "/Ethernet_Phy/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_MDIO" +Ne 49 "/Ethernet_Phy/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_RESET_N" +Ne 65 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 50 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_CLK" +Ne 63 "/FPGA_Spartan6/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -11730,7 +11732,7 @@ $PAD Sh "44" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po -295 -1613 $EndPAD $PAD @@ -11751,56 +11753,56 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/MAG_TX+" +Ne 61 "/Ethernet_Phy/MAG_TX+" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/MAG_TX-" +Ne 62 "/Ethernet_Phy/MAG_TX-" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_A3.3V" +Ne 43 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 233 "N-000397" +Ne 240 "N-000395" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_INT" +Ne 45 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_LED0" +Ne 46 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_LED1" +Ne 47 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -11828,21 +11830,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Ethernet_Phy/ETH_A1.8V" +Ne 42 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/MAG_RX-" +Ne 59 "/Ethernet_Phy/MAG_RX-" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/MAG_RX+" +Ne 58 "/Ethernet_Phy/MAG_RX+" Po 1613 -491 $EndPAD $PAD @@ -11856,14 +11858,14 @@ $PAD Sh "35" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 1613 -1082 $EndPAD $PAD @@ -11877,70 +11879,70 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_TXER" +Ne 72 "/FPGA_Spartan6/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_TXC" +Ne 55 "/Ethernet_Phy/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_TXEN" +Ne 57 "/Ethernet_Phy/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_TXD0" +Ne 69 "/FPGA_Spartan6/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_TXD1" +Ne 70 "/FPGA_Spartan6/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_TXD2" +Ne 56 "/Ethernet_Phy/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_TXD3" +Ne 71 "/FPGA_Spartan6/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/ETH_COL" +Ne 44 "/Ethernet_Phy/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_CRS" +Ne 64 "/FPGA_Spartan6/ETH_CRS" Po 688 1613 $EndPAD $PAD Sh "23" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 885 1613 $EndPAD $PAD @@ -11975,7 +11977,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -11997,35 +11999,35 @@ $PAD Sh "1" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 247 "N-000436" +Ne 253 "N-000434" Po -375 500 $EndPAD $PAD Sh "3" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 249 "N-000447" +Ne 255 "N-000445" Po 375 500 $EndPAD $PAD Sh "5" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 248 "N-000437" +Ne 254 "N-000435" Po -375 -500 $EndPAD $PAD Sh "2" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 0 500 $EndPAD $PAD Sh "4" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 247 "N-000436" +Ne 253 "N-000434" Po 375 -500 $EndPAD $SHAPE3D @@ -12053,35 +12055,35 @@ $PAD Sh "1" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 245 "N-000434" +Ne 251 "N-000432" Po -375 500 $EndPAD $PAD Sh "3" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 250 "N-000466" +Ne 256 "N-000464" Po 375 500 $EndPAD $PAD Sh "5" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 246 "N-000435" +Ne 252 "N-000433" Po -375 -500 $EndPAD $PAD Sh "2" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 0 500 $EndPAD $PAD Sh "4" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 245 "N-000434" +Ne 251 "N-000432" Po 375 -500 $EndPAD $SHAPE3D @@ -12115,7 +12117,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 248 "N-000437" +Ne 254 "N-000435" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12136,14 +12138,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 248 "N-000437" +Ne 254 "N-000435" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12171,7 +12173,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 248 "N-000437" +Ne 254 "N-000435" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12199,7 +12201,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12227,7 +12229,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12255,7 +12257,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 246 "N-000435" +Ne 252 "N-000433" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12276,14 +12278,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 246 "N-000435" +Ne 252 "N-000433" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12311,7 +12313,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 246 "N-000435" +Ne 252 "N-000433" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12332,14 +12334,14 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 247 "N-000436" +Ne 253 "N-000434" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -12360,14 +12362,14 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 245 "N-000434" +Ne 251 "N-000432" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -12395,7 +12397,7 @@ $PAD Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -12423,7 +12425,7 @@ $PAD Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 231 "GND" +Ne 235 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -12451,7 +12453,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 249 "N-000447" +Ne 255 "N-000445" Po 570 0 $EndPAD $EndMODULE 1210 @@ -12479,10 +12481,227 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 250 "N-000466" +Ne 256 "N-000464" Po 570 0 $EndPAD $EndMODULE 1210 +$MODULE 0603 +Po 46992 24362 1800 0 4C5FF890 4C5D7FB7 ~~ +Li 0603 +Sc 4C5D7FB7 +AR /4C4320F3/4C5D7FB7 +Op 0 0 0 +At SMD +T0 0 150 200 200 1800 40 M V 20 N"L2" +T1 0 -150 200 200 1800 40 M I 20 N"FB" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 43 "/Ethernet_Phy/ETH_A3.3V" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0402 +Po 60921 37756 1800 0 4C5FF890 4C716CF6 ~~ +Li 0402 +Sc 4C716CF6 +AR /4C431A63/4C7168DD +Op 0 0 0 +At SMD +T0 0 150 200 200 1800 40 M V 20 N"R30" +T1 0 -150 200 200 1800 40 M I 20 N"330" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 236 "N-000127" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 51559 39350 0 0 4C5FF890 4C716CF8 ~~ +Li 0402 +Sc 4C716CF8 +AR /4C431A63/4C716877 +Op 0 0 0 +At SMD +T0 0 150 200 200 0 40 M V 20 N"R29" +T1 0 -150 200 200 0 40 M I 20 N"4.7k" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 237 "N-000132" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE pin_array_8x2 +Po 77882 23228 0 15 3FB38B89 4C716CF9 ~~ +Li pin_array_8x2 +Cd Double rangee de contacts 2 x 8 pins +Kw CONN +Sc 4C716CF9 +AR /4C716A4D/4C716CAB +Op 0 0 0 +T0 0 -1300 400 400 0 80 N V 21 N"J6" +T1 0 1300 400 400 0 80 N V 21 N"CONN_8X2" +DS -3900 900 -3900 -900 120 21 +DS -3900 -900 3900 -900 120 21 +DS 3900 -900 3900 900 120 21 +DS 3900 900 -3900 900 120 21 +$PAD +Sh "1" R 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 6 "/DBG_PRG/FPGA_TCK" +Po -3500 500 +$EndPAD +$PAD +Sh "2" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po -3500 -500 +$EndPAD +$PAD +Sh "3" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 9 "/DBG_PRG/FPGA_TMS" +Po -2500 500 +$EndPAD +$PAD +Sh "4" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po -2500 -500 +$EndPAD +$PAD +Sh "5" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 8 "/DBG_PRG/FPGA_TDO" +Po -1500 500 +$EndPAD +$PAD +Sh "6" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po -1500 -500 +$EndPAD +$PAD +Sh "7" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 7 "/DBG_PRG/FPGA_TDI" +Po -500 500 +$EndPAD +$PAD +Sh "8" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po -500 -500 +$EndPAD +$PAD +Sh "9" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 500 500 +$EndPAD +$PAD +Sh "10" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 500 -500 +$EndPAD +$PAD +Sh "11" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 1500 500 +$EndPAD +$PAD +Sh "12" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 1500 -500 +$EndPAD +$PAD +Sh "13" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 2500 500 +$EndPAD +$PAD +Sh "14" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 2500 -500 +$EndPAD +$PAD +Sh "15" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 3500 500 +$EndPAD +$PAD +Sh "16" C 600 600 0 0 0 +Dr 400 0 0 +At STD N 00E0FFFF +Ne 0 "" +Po 3500 -500 +$EndPAD +$SHAPE3D +Na "pin_array/pins_array_8x2.wrl" +Sc 1.000000 1.000000 1.000000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE pin_array_8x2 $COTATION Ge 0 25 0 Va 21500 @@ -12542,14 +12761,52 @@ Po 3 50069 27352 50069 27352 157 -1 De 15 1 2 0 0 Po 0 50071 27354 50069 27352 79 -1 De 15 0 2 0 0 +Po 0 48773 27885 48773 27684 79 -1 +De 15 0 4 0 800 +Po 0 48851 27531 48851 27453 79 -1 +De 0 0 4 0 400 +Po 0 48795 27587 48851 27531 79 -1 +De 0 0 4 0 0 +Po 3 48795 27587 48795 27587 157 -1 +De 15 1 4 0 0 +Po 0 48795 27662 48795 27587 79 -1 +De 15 0 4 0 0 +Po 0 48773 27684 48795 27662 79 -1 +De 15 0 4 0 0 +Po 0 46777 23858 46759 23858 79 -1 +De 0 0 4 0 800 +Po 0 46759 23858 46543 23642 79 -1 +De 0 0 4 0 0 +Po 0 46789 23445 46740 23445 79 -1 +De 0 0 4 0 800 +Po 0 46740 23445 46543 23642 79 -1 +De 0 0 4 0 0 +Po 3 46543 23642 46543 23642 157 -1 +De 15 1 4 0 0 +Po 0 46543 23642 46915 23642 79 -1 +De 15 0 4 0 400 +Po 0 47286 24362 47281 24362 79 -1 +De 0 0 4 0 800 +Po 0 47281 24362 46777 23858 79 -1 +De 0 0 4 0 400 +Po 0 53164 20272 53164 20570 79 -1 +De 0 0 4 0 800 +Po 0 53164 20572 53164 20863 79 -1 +De 0 0 4 0 400 +Po 0 53165 20571 53164 20572 79 -1 +De 0 0 4 0 0 +Po 3 53165 20571 53165 20571 157 -1 +De 15 1 4 0 0 +Po 0 53164 20570 53165 20571 79 -1 +De 0 0 4 0 0 Po 0 59221 30639 59221 30633 79 -1 -De 15 0 4 0 C00 +De 15 0 4 0 800 Po 3 59413 30441 59413 30441 157 -1 De 15 1 4 0 0 Po 0 59221 30633 59413 30441 79 -1 -De 15 0 4 0 800 +De 15 0 4 0 0 Po 0 58434 31820 58434 31818 79 -1 -De 15 0 4 0 C00 +De 15 0 4 0 800 Po 0 58622 31614 58618 31614 79 -1 De 0 0 4 0 0 Po 0 58630 31622 58622 31614 79 -1 @@ -12557,7 +12814,7 @@ De 0 0 4 0 0 Po 3 58630 31622 58630 31622 157 -1 De 15 1 4 0 0 Po 0 58434 31818 58630 31622 79 -1 -De 15 0 4 0 800 +De 15 0 4 0 0 Po 0 56139 30173 56139 30190 79 -1 De 0 0 4 0 800 Po 0 56139 30190 55876 30453 79 -1 @@ -12642,2300 +12899,2392 @@ Po 3 53317 30472 53317 30472 157 -1 De 15 1 4 0 0 Po 0 53317 30443 53317 30472 79 -1 De 15 0 4 0 0 -Po 0 50995 31320 50040 31320 39 -1 -De 15 0 6 0 800 -Po 0 50020 31338 49768 31338 39 -1 -De 0 0 6 0 400 -Po 0 50039 31319 50020 31338 39 -1 -De 0 0 6 0 0 -Po 3 50039 31319 50039 31319 157 -1 -De 15 1 6 0 0 -Po 0 50040 31320 50039 31319 39 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50995 35669 39 -1 -De 15 0 14 0 400 -Po 0 50071 35945 50347 35669 39 -1 -De 15 0 14 0 0 -Po 3 50071 35945 50071 35945 157 -1 -De 15 1 14 0 0 -Po 0 46643 35669 46826 35669 39 -1 -De 15 0 15 0 800 -Po 0 47157 36000 47351 36000 39 -1 -De 0 0 15 0 400 -Po 0 47035 35878 47157 36000 39 -1 -De 0 0 15 0 0 -Po 3 47035 35878 47035 35878 157 -1 -De 15 1 15 0 0 -Po 0 46826 35669 47035 35878 39 -1 -De 15 0 15 0 0 -Po 0 47351 36197 47031 36197 39 -1 -De 0 0 16 0 800 -Po 0 47015 36181 46643 36181 39 -1 -De 15 0 16 0 400 -Po 0 47031 36197 47015 36181 39 -1 -De 15 0 16 0 0 -Po 3 47031 36197 47031 36197 157 -1 -De 15 1 16 0 0 -Po 0 46643 34391 47017 34391 79 -1 -De 15 0 18 0 800 -Po 0 47265 34290 47265 34154 79 -1 -De 0 0 18 0 400 -Po 0 47165 34390 47265 34290 79 -1 -De 0 0 18 0 0 -Po 0 47018 34390 47165 34390 79 -1 -De 0 0 18 0 0 -Po 3 47018 34390 47018 34390 157 -1 -De 15 1 18 0 0 -Po 0 47017 34391 47018 34390 79 -1 -De 15 0 18 0 0 -Po 0 47265 34646 47265 34154 79 -1 -De 0 0 18 0 C00 -Po 0 47265 33661 47265 34154 79 -1 -De 0 0 18 0 C00 -Po 0 47265 33169 47265 33661 79 -1 -De 0 0 18 0 C00 -Po 0 48499 25878 48499 25484 118 -1 -De 0 0 34 0 C00 -Po 0 47867 26665 47867 26307 118 -1 -De 0 0 34 0 800 -Po 0 48296 25878 48499 25878 118 -1 -De 0 0 34 0 400 -Po 0 47867 26307 48296 25878 118 -1 -De 0 0 34 0 0 -Po 0 47062 25387 47365 25387 118 -1 -De 15 0 35 0 800 -Po 0 47490 25394 47490 25265 118 -1 -De 0 0 35 0 400 -Po 0 47431 25453 47490 25394 118 -1 -De 0 0 35 0 0 -Po 3 47431 25453 47431 25453 157 -1 -De 15 1 35 0 0 -Po 0 47365 25387 47431 25453 118 -1 -De 15 0 35 0 0 -Po 0 50965 29675 52973 29675 39 -1 -De 0 0 36 0 0 -Po 0 53317 30049 53317 30245 39 -1 -De 15 0 36 0 400 -Po 3 53219 29951 53219 29951 157 -1 -De 15 1 36 0 0 -Po 0 53317 30049 53219 29951 39 -1 -De 15 0 36 0 0 -Po 0 53219 29921 53219 29951 39 -1 -De 0 0 36 0 0 -Po 0 52973 29675 53219 29921 39 -1 -De 0 0 36 0 0 -Po 0 47413 26960 47062 26960 39 -1 -De 15 0 36 0 400 -Po 0 47805 27352 47413 26960 39 -1 -De 15 0 36 0 0 -Po 3 47805 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231 0 800 +De 15 0 235 0 800 Po 0 53543 30650 53533 30650 79 -1 -De 0 0 231 0 0 +De 0 0 235 0 0 Po 3 53543 30650 53543 30650 157 -1 -De 15 1 231 0 0 +De 15 1 235 0 0 Po 0 53563 30650 53543 30650 39 -1 -De 15 0 231 0 0 +De 15 0 235 0 0 Po 0 53574 30639 53563 30650 39 -1 -De 15 0 231 0 0 +De 15 0 235 0 0 Po 0 46643 35157 46870 35157 79 -1 -De 15 0 231 0 800 +De 15 0 235 0 800 Po 3 46870 35157 46870 35157 157 -1 -De 15 1 231 0 0 +De 15 1 235 0 0 Po 0 48499 27453 48499 27229 79 -1 -De 0 0 231 0 800 +De 0 0 235 0 800 Po 3 48494 27224 48494 27224 157 -1 -De 15 1 231 0 0 +De 15 1 235 0 0 Po 0 48499 27229 48494 27224 79 -1 -De 0 0 231 0 0 +De 0 0 235 0 0 Po 0 47062 26567 46734 26567 79 -1 -De 15 0 231 0 800 +De 15 0 235 0 800 Po 3 46732 26565 46732 26565 157 -1 -De 15 1 231 0 0 +De 15 1 235 0 0 Po 0 46734 26567 46732 26565 79 -1 -De 15 0 231 0 0 +De 15 0 235 0 0 Po 0 47062 25584 46676 25584 79 -1 -De 15 0 231 0 800 +De 15 0 235 0 800 Po 3 46673 25591 46673 25591 157 -1 -De 15 1 231 0 0 +De 15 1 235 0 0 Po 0 46673 25587 46673 25591 79 -1 -De 15 0 231 0 0 +De 15 0 235 0 0 Po 0 46676 25584 46673 25587 79 -1 -De 15 0 231 0 0 +De 15 0 235 0 0 Po 0 50615 18560 50862 18560 79 -1 -De 0 0 231 0 800 +De 0 0 235 0 800 Po 3 50862 18560 50862 18560 157 -1 -De 15 1 231 0 0 +De 15 1 235 0 0 Po 0 50615 18560 50615 18117 79 -1 -De 0 0 231 0 800 +De 0 0 235 0 800 Po 0 50615 18117 50605 18107 79 -1 -De 0 0 231 0 400 +De 0 0 235 0 400 Po 0 49757 27885 49910 27885 79 -1 -De 15 0 231 0 800 +De 15 0 235 0 800 Po 0 49911 27884 49902 27884 79 -1 -De 0 0 231 0 0 +De 0 0 235 0 0 Po 3 49911 27884 49911 27884 157 -1 -De 15 1 231 0 0 +De 15 1 235 0 0 Po 0 49910 27885 49911 27884 79 -1 -De 15 0 231 0 0 +De 15 0 235 0 0 Po 0 48970 27885 48970 28156 79 -1 -De 15 0 231 0 800 +De 15 0 235 0 800 Po 0 48957 28169 48957 28189 79 -1 -De 0 0 231 0 0 +De 0 0 235 0 0 Po 0 48967 28159 48957 28169 79 -1 -De 0 0 231 0 0 +De 0 0 235 0 0 Po 3 48967 28159 48967 28159 157 -1 -De 15 1 231 0 0 +De 15 1 235 0 0 Po 0 48970 28156 48967 28159 79 -1 -De 15 0 231 0 0 -Po 0 47062 25190 47050 25190 39 -1 -De 15 0 233 0 800 -Po 0 46743 24883 46654 24883 39 -1 -De 0 0 233 0 400 -Po 0 46949 25089 46743 24883 39 -1 -De 0 0 233 0 0 -Po 3 46949 25089 46949 25089 157 -1 -De 15 1 233 0 0 -Po 0 47050 25190 46949 25089 39 -1 -De 15 0 233 0 0 +De 15 0 235 0 0 +Po 0 47062 25190 46708 25190 39 -1 +De 15 0 240 0 800 +Po 0 46973 25193 47043 25263 39 -1 +De 0 0 240 0 400 +Po 0 46713 25193 46973 25193 39 -1 +De 0 0 240 0 0 +Po 0 46717 25161 46713 25193 39 -1 +De 0 0 240 0 0 +Po 3 46717 25161 46717 25161 157 -1 +De 15 1 240 0 0 +Po 0 46709 25191 46717 25161 39 -1 +De 15 0 240 0 0 +Po 0 46708 25190 46709 25191 39 -1 +De 15 0 240 0 0 $EndTRACK $ZONE $EndZONE diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp index ee57428..3153650 100644 --- a/kicad/xue-rnc/xue-rnc.cmp +++ b/kicad/xue-rnc/xue-rnc.cmp @@ -1,4 +1,4 @@ -Cmp-Mod V01 Genere par PcbNew le Thu 19 Aug 2010 04:47:26 AM COT +Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Sun 22 Aug 2010 01:31:08 PM COT BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; @@ -525,6 +525,76 @@ ValeurCmp = 100nF; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C431A63/4C6B29A3; +Reference = C76; +ValeurCmp = 470nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C6B29DA; +Reference = C77; +ValeurCmp = 470nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2C7C; +Reference = C78; +ValeurCmp = 4.7uF; +IdModule = 0805; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2C7F; +Reference = C79; +ValeurCmp = 22pF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2C83; +Reference = C80; +ValeurCmp = 10uF; +IdModule = 1206; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2F0B; +Reference = C81; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2FD7; +Reference = C82; +ValeurCmp = 4.7uF; +IdModule = 0805; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2FD6; +Reference = C83; +ValeurCmp = 22pF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2FD5; +Reference = C84; +ValeurCmp = 10uF; +IdModule = 1206; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2FD0; +Reference = C85; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + BeginCmp TimeStamp = /4C5F1EDC/4C5F2B55; Reference = F1; @@ -560,6 +630,13 @@ ValeurCmp = USB-48204-0001; IdModule = USB-48204; EndCmp +BeginCmp +TimeStamp = /4C716A4D/4C716CAB; +Reference = J6; +ValeurCmp = CONN_8X2; +IdModule = pin_array_8x2; +EndCmp + BeginCmp TimeStamp = /4C4320F3/4C5D80F3; Reference = L1; @@ -571,7 +648,7 @@ BeginCmp TimeStamp = /4C4320F3/4C5D7FB7; Reference = L2; ValeurCmp = FB; -IdModule = 0402; +IdModule = 0603; EndCmp BeginCmp @@ -609,6 +686,20 @@ ValeurCmp = FB; IdModule = 0603; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4C6D2E6A; +Reference = L8; +ValeurCmp = 2.2uH; +IdModule = 1210; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2FD1; +Reference = L9; +ValeurCmp = 2.2uH; +IdModule = 1210; +EndCmp + BeginCmp TimeStamp = /4C4320F3/4C5D7F39; Reference = R1; @@ -749,6 +840,76 @@ ValeurCmp = 33; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C431A63/4C6B1B90; +Reference = R21; +ValeurCmp = 120; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C6B216D; +Reference = R22; +ValeurCmp = 33; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C6B216E; +Reference = R23; +ValeurCmp = 33; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C6B216B; +Reference = R24; +ValeurCmp = 33; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2DBC; +Reference = R25; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2DDD; +Reference = R26; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2FD3; +Reference = R27; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2FD2; +Reference = R28; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C716877; +Reference = R29; +ValeurCmp = 4.7k; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C7168DD; +Reference = R30; +ValeurCmp = 330; +IdModule = 0402; +EndCmp + BeginCmp TimeStamp = /4C431A63/4C69C6B2; Reference = RP1; @@ -819,6 +980,62 @@ ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp +BeginCmp +TimeStamp = /4C431A63/4C69FCE6; +Reference = RP11; +ValeurCmp = R_PACK4; +IdModule = R_PACK4-0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C69FCE8; +Reference = RP12; +ValeurCmp = R_PACK4; +IdModule = R_PACK4-0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C69FCE7; +Reference = RP13; +ValeurCmp = R_PACK4; +IdModule = R_PACK4-0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C6A0D58; +Reference = RP14; +ValeurCmp = R_PACK4; +IdModule = R_PACK4-0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C6A0D57; +Reference = RP15; +ValeurCmp = R_PACK4; +IdModule = R_PACK4-0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C6A0D56; +Reference = RP16; +ValeurCmp = R_PACK4; +IdModule = R_PACK4-0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C6A0D55; +Reference = RP17; +ValeurCmp = R_PACK4; +IdModule = R_PACK4-0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C6A0D54; +Reference = RP18; +ValeurCmp = R_PACK4; +IdModule = R_PACK4-0402; +EndCmp + BeginCmp TimeStamp = /4C431A63/4C431E53; Reference = U1; @@ -882,6 +1099,27 @@ ValeurCmp = ATTINY24A-MLF; IdModule = MLF20m1; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4C6C9DB9; +Reference = U10; +ValeurCmp = A7130; +IdModule = DFN10; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2AA5; +Reference = U11; +ValeurCmp = A7108; +IdModule = SOT23-5; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4C6D2AE0; +Reference = U12; +ValeurCmp = A7108; +IdModule = SOT23-5; +EndCmp + BeginCmp TimeStamp = /4C5F1EDC/4C5F2CA7; Reference = V1; diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 72944e2..f6344ff 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,28 +1,46 @@ -# EESchema Netlist Version 1.1 created Sun 22 Aug 2010 08:19:37 AM COT +# EESchema Netlist Version 1.1 created Sun 22 Aug 2010 01:33:42 PM COT ( + ( /4C716A4D/4C716CAB $noname J6 CONN_8X2 {Lib=CONN_8X2} + ( 1 /DBG_PRG/FPGA_TCK ) + ( 2 ? ) + ( 3 /DBG_PRG/FPGA_TMS ) + ( 4 ? ) + ( 5 /DBG_PRG/FPGA_TDO ) + ( 6 ? ) + ( 7 /DBG_PRG/FPGA_TDI ) + ( 8 ? ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 ? ) + ( 13 ? ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ) ( /4C69ED5F/4C6D2FD7 0805 C82 4.7uF {Lib=CAP} - ( 1 N-000434 ) + ( 1 N-000432 ) ( 2 GND ) ) ( /4C69ED5F/4C6D2FD6 0402 C83 22pF {Lib=CAP} ( 1 +1.2V ) - ( 2 N-000435 ) + ( 2 N-000433 ) ) ( /4C69ED5F/4C6D2FD5 1206 C84 10uF {Lib=CAP} ( 1 +1.2V ) ( 2 GND ) ) ( /4C69ED5F/4C6D2FD3 0402 R27 R {Lib=R} - ( 1 N-000435 ) + ( 1 N-000433 ) ( 2 GND ) ) ( /4C69ED5F/4C6D2FD2 0402 R28 R {Lib=R} ( 1 +1.2V ) - ( 2 N-000435 ) + ( 2 N-000433 ) ) ( /4C69ED5F/4C6D2FD1 1210 L9 2.2uH {Lib=INDUCTOR} ( 1 +1.2V ) - ( 2 N-000466 ) + ( 2 N-000464 ) ) ( /4C69ED5F/4C6D2FD0 0402 C85 100nF {Lib=CAP} ( 1 +1.2V ) @@ -34,14 +52,14 @@ ) ( /4C69ED5F/4C6D2E6A 1210 L8 2.2uH {Lib=INDUCTOR} ( 1 +3.3V ) - ( 2 N-000447 ) + ( 2 N-000445 ) ) ( /4C69ED5F/4C6D2DDD 0402 R26 R {Lib=R} ( 1 +3.3V ) - ( 2 N-000437 ) + ( 2 N-000435 ) ) ( /4C69ED5F/4C6D2DBC 0402 R25 R {Lib=R} - ( 1 N-000437 ) + ( 1 N-000435 ) ( 2 GND ) ) ( /4C69ED5F/4C6D2C83 1206 C80 10uF {Lib=CAP} @@ -50,25 +68,25 @@ ) ( /4C69ED5F/4C6D2C7F 0402 C79 22pF {Lib=CAP} ( 1 +3.3V ) - ( 2 N-000437 ) + ( 2 N-000435 ) ) ( /4C69ED5F/4C6D2C7C 0805 C78 4.7uF {Lib=CAP} - ( 1 N-000436 ) + ( 1 N-000434 ) ( 2 GND ) ) ( /4C69ED5F/4C6D2AE0 SOT23-5 U12 A7108 {Lib=A7108} - ( 1 N-000434 ) + ( 1 N-000432 ) ( 2 GND ) - ( 3 N-000466 ) - ( 4 N-000434 ) - ( 5 N-000435 ) + ( 3 N-000464 ) + ( 4 N-000432 ) + ( 5 N-000433 ) ) ( /4C69ED5F/4C6D2AA5 SOT23-5 U11 A7108 {Lib=A7108} - ( 1 N-000436 ) + ( 1 N-000434 ) ( 2 GND ) - ( 3 N-000447 ) - ( 4 N-000436 ) - ( 5 N-000437 ) + ( 3 N-000445 ) + ( 4 N-000434 ) + ( 5 N-000435 ) ) ( /4C69ED5F/4C6C9DB9 DFN10 U10 A7130 {Lib=A7130} ( PAD GND ) @@ -137,13 +155,13 @@ ( COM GND ) ( CD ? ) ( 1 /Non_volatile_memories/SD_DAT2 ) - ( 2 /Non_volatile_memories/SD_DAT3 ) - ( 3 /Non_volatile_memories/SD_CMD ) + ( 2 /FPGA_Spartan6/SD_DAT3 ) + ( 3 /FPGA_Spartan6/SD_CMD ) ( 4 +3.3V ) - ( 5 /Non_volatile_memories/SD_CLK ) + ( 5 /FPGA_Spartan6/SD_CLK ) ( 6 GND ) - ( 7 /FPGA_Spartan6/SD_DAT0 ) - ( 8 /Non_volatile_memories/SD_DAT1 ) + ( 7 /Non_volatile_memories/SD_DAT0 ) + ( 8 /FPGA_Spartan6/SD_DAT1 ) ) ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} ( 1 ? ) @@ -153,8 +171,8 @@ ( 5 ? ) ( 6 /FPGA_Spartan6/NF_RNB ) ( 7 /FPGA_Spartan6/NF_RNB ) - ( 8 /Non_volatile_memories/NF_RE_N ) - ( 9 /Non_volatile_memories/NF_CS1_N ) + ( 8 /FPGA_Spartan6/NF_RE_N ) + ( 9 /FPGA_Spartan6/NF_CS1_N ) ( 10 ? ) ( 11 ? ) ( 12 +3.3V ) @@ -162,8 +180,8 @@ ( 14 ? ) ( 15 ? ) ( 16 /FPGA_Spartan6/NF_CLE ) - ( 17 /FPGA_Spartan6/NF_ALE ) - ( 18 /FPGA_Spartan6/NF_WE_N ) + ( 17 /Non_volatile_memories/NF_ALE ) + ( 18 /Non_volatile_memories/NF_WE_N ) ( 19 +3.3V ) ( 20 ? ) ( 21 ? ) @@ -174,10 +192,10 @@ ( 26 ? ) ( 27 ? ) ( 28 ? ) - ( 29 /Non_volatile_memories/NF_D0 ) + ( 29 /FPGA_Spartan6/NF_D0 ) ( 30 /Non_volatile_memories/NF_D1 ) ( 31 /FPGA_Spartan6/NF_D2 ) - ( 32 /Non_volatile_memories/NF_D3 ) + ( 32 /FPGA_Spartan6/NF_D3 ) ( 33 ? ) ( 34 ? ) ( 35 ? ) @@ -189,7 +207,7 @@ ( 41 /FPGA_Spartan6/NF_D4 ) ( 42 /Non_volatile_memories/NF_D5 ) ( 43 /FPGA_Spartan6/NF_D6 ) - ( 44 /FPGA_Spartan6/NF_D7 ) + ( 44 /Non_volatile_memories/NF_D7 ) ( 45 ? ) ( 46 ? ) ( 47 ? ) @@ -204,8 +222,8 @@ ( 7 GND ) ( 8 GND ) ( 9 ? ) - ( 10 N-000431 ) - ( 11 N-000432 ) + ( 10 N-000429 ) + ( 11 N-000430 ) ( 12 +3.3V ) ( 14 +3.3V ) ) @@ -222,23 +240,23 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552BA $noname F2 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000422 ) + ( 1 N-000425 ) ( 2 +5V ) ) ( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000431 ) + ( 1 N-000429 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000432 ) + ( 1 N-000430 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C} - ( 1 N-000433 ) + ( 1 N-000431 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R} - ( 1 N-000433 ) + ( 1 N-000431 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} @@ -246,46 +264,46 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552B0 0603 L6 FB {Lib=INDUCTOR} - ( 1 N-000422 ) + ( 1 N-000425 ) ( 2 ? ) ) ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000429 ) - ( 2 N-000427 ) + ( 1 N-000427 ) + ( 2 N-000426 ) ) ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000425 ) + ( 1 N-000415 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000424 ) + ( 1 N-000414 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000424 ) + ( 1 N-000414 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000430 ) + ( 1 N-000428 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000426 ) + ( 1 N-000416 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000429 ) + ( 1 N-000427 ) ( 2 +5V ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000424 ) - ( S2 N-000424 ) - ( S3 N-000424 ) - ( S4 N-000424 ) - ( 1 N-000427 ) - ( 2 N-000426 ) - ( 3 N-000430 ) - ( 4 N-000425 ) + ( S1 N-000414 ) + ( S2 N-000414 ) + ( S3 N-000414 ) + ( S4 N-000414 ) + ( 1 N-000426 ) + ( 2 N-000416 ) + ( 3 N-000428 ) + ( 4 N-000415 ) ) ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} ( 1 +2.5V ) @@ -301,18 +319,26 @@ ) ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) - ( 2 /USB/USBA_SPD ) - ( 3 /FPGA_Spartan6/USBA_RCV ) - ( 4 /FPGA_Spartan6/USBA_VP ) + ( 2 /FPGA_Spartan6/USBA_SPD ) + ( 3 /USB/USBA_RCV ) + ( 4 /USB/USBA_VP ) ( 5 /USB/USBA_VM ) ( 7 GND ) ( 8 GND ) ( 9 /USB/USBA_OE_N ) - ( 10 N-000426 ) - ( 11 N-000430 ) + ( 10 N-000416 ) + ( 11 N-000428 ) ( 12 +3.3V ) ( 14 +3.3V ) ) + ( /4C431A63/4C7168DD 0402 R30 330 {Lib=R} + ( 1 +3.3V ) + ( 2 N-000127 ) + ) + ( /4C431A63/4C716877 0402 R29 4.7k {Lib=R} + ( 1 +3.3V ) + ( 2 N-000132 ) + ) ( /4C431A63/4C6B29DA 0402 C77 470nF {Lib=C} ( 1 +2.5V ) ( 2 GND ) @@ -323,29 +349,29 @@ ) ( /4C431A63/4C6B216E 0402 R23 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M0_UDM ) - ( 2 /FPGA_Spartan6/M0_UDM ) + ( 2 /DDR_Banks/M0_UDM ) ) ( /4C431A63/4C6B216D 0402 R22 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M0_UDQS ) - ( 2 /DDR_Banks/M0_UDQS ) + ( 2 /FPGA_Spartan6/M0_UDQS ) ) ( /4C431A63/4C6B216B 0402 R24 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M0_CKE ) - ( 2 /FPGA_Spartan6/M0_CKE ) + ( 2 /DDR_Banks/M0_CKE ) ) ( /4C431A63/4C6B1B90 0402 R21 120 {Lib=R} ( 1 /FPGA_Spartan6/M0_CLK ) - ( 2 /DDR_Banks/M0_CLK# ) + ( 2 /FPGA_Spartan6/M0_CLK# ) ) ( /4C431A63/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_A0 ) ( 2 /FPGA_Spartan6/R_M0_A1 ) ( 3 /FPGA_Spartan6/R_M0_A2 ) ( 4 /FPGA_Spartan6/R_M0_A3 ) - ( 5 /FPGA_Spartan6/M0_A3 ) - ( 6 /FPGA_Spartan6/M0_A2 ) - ( 7 /DDR_Banks/M0_A1 ) - ( 8 /FPGA_Spartan6/M0_A0 ) + ( 5 /DDR_Banks/M0_A3 ) + ( 6 /DDR_Banks/M0_A2 ) + ( 7 /FPGA_Spartan6/M0_A1 ) + ( 8 /DDR_Banks/M0_A0 ) ) ( /4C431A63/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_RAS# ) @@ -354,7 +380,7 @@ ( 4 /FPGA_Spartan6/R_M0_A10 ) ( 5 /FPGA_Spartan6/M0_A10 ) ( 6 /FPGA_Spartan6/M0_BA1 ) - ( 7 /DDR_Banks/M0_BA0 ) + ( 7 /FPGA_Spartan6/M0_BA0 ) ( 8 /FPGA_Spartan6/M0_RAS# ) ) ( /4C431A63/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 {Lib=R_PACK4} @@ -362,8 +388,8 @@ ( 2 /FPGA_Spartan6/R_M0_LDM ) ( 3 /FPGA_Spartan6/R_M0_WE# ) ( 4 /FPGA_Spartan6/R_M0_CAS# ) - ( 5 /DDR_Banks/M0_CAS# ) - ( 6 /FPGA_Spartan6/M0_WE# ) + ( 5 /FPGA_Spartan6/M0_CAS# ) + ( 6 /DDR_Banks/M0_WE# ) ( 7 /FPGA_Spartan6/M0_LDM ) ( 8 /FPGA_Spartan6/M0_LDQS ) ) @@ -372,17 +398,17 @@ ( 2 /FPGA_Spartan6/R_M0_A6 ) ( 3 /FPGA_Spartan6/R_M0_A5 ) ( 4 /FPGA_Spartan6/R_M0_A4 ) - ( 5 /FPGA_Spartan6/M0_A4 ) + ( 5 /DDR_Banks/M0_A4 ) ( 6 /FPGA_Spartan6/M0_A5 ) - ( 7 /DDR_Banks/M0_A6 ) - ( 8 /FPGA_Spartan6/M0_A7 ) + ( 7 /FPGA_Spartan6/M0_A6 ) + ( 8 /DDR_Banks/M0_A7 ) ) ( /4C431A63/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_A12 ) ( 2 /FPGA_Spartan6/R_M0_A11 ) ( 3 /FPGA_Spartan6/R_M0_A9 ) ( 4 /FPGA_Spartan6/R_M0_A8 ) - ( 5 /DDR_Banks/M0_A8 ) + ( 5 /FPGA_Spartan6/M0_A8 ) ( 6 /FPGA_Spartan6/M0_A9 ) ( 7 /FPGA_Spartan6/M0_A11 ) ( 8 /FPGA_Spartan6/M0_A12 ) @@ -392,8 +418,8 @@ ( 2 /FPGA_Spartan6/R_M0_DQ5 ) ( 3 /FPGA_Spartan6/R_M0_DQ6 ) ( 4 /FPGA_Spartan6/R_M0_DQ7 ) - ( 5 /DDR_Banks/M0_DQ7 ) - ( 6 /FPGA_Spartan6/M0_DQ6 ) + ( 5 /FPGA_Spartan6/M0_DQ7 ) + ( 6 /DDR_Banks/M0_DQ6 ) ( 7 /FPGA_Spartan6/M0_DQ5 ) ( 8 /FPGA_Spartan6/M0_DQ4 ) ) @@ -402,9 +428,9 @@ ( 2 /FPGA_Spartan6/R_M0_DQ1 ) ( 3 /FPGA_Spartan6/R_M0_DQ2 ) ( 4 /FPGA_Spartan6/R_M0_DQ3 ) - ( 5 /FPGA_Spartan6/M0_DQ3 ) + ( 5 /DDR_Banks/M0_DQ3 ) ( 6 /FPGA_Spartan6/M0_DQ2 ) - ( 7 /DDR_Banks/M0_DQ1 ) + ( 7 /FPGA_Spartan6/M0_DQ1 ) ( 8 /FPGA_Spartan6/M0_DQ0 ) ) ( /4C431A63/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4} @@ -413,17 +439,17 @@ ( 3 /FPGA_Spartan6/R_M0_DQ10 ) ( 4 /FPGA_Spartan6/R_M0_DQ11 ) ( 5 /FPGA_Spartan6/M0_DQ11 ) - ( 6 /DDR_Banks/M0_DQ10 ) - ( 7 /DDR_Banks/M0_DQ9 ) - ( 8 /DDR_Banks/M0_DQ8 ) + ( 6 /FPGA_Spartan6/M0_DQ10 ) + ( 7 /FPGA_Spartan6/M0_DQ9 ) + ( 8 /FPGA_Spartan6/M0_DQ8 ) ) ( /4C431A63/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_DQ12 ) ( 2 /FPGA_Spartan6/R_M0_DQ13 ) ( 3 /FPGA_Spartan6/R_M0_DQ14 ) ( 4 /FPGA_Spartan6/R_M0_DQ15 ) - ( 5 /FPGA_Spartan6/M0_DQ15 ) - ( 6 /FPGA_Spartan6/M0_DQ14 ) + ( 5 /DDR_Banks/M0_DQ15 ) + ( 6 /DDR_Banks/M0_DQ14 ) ( 7 /FPGA_Spartan6/M0_DQ13 ) ( 8 /FPGA_Spartan6/M0_DQ12 ) ) @@ -448,9 +474,9 @@ ( 2 /FPGA_Spartan6/R_M1_DQ10 ) ( 3 /FPGA_Spartan6/R_M1_DQ9 ) ( 4 /FPGA_Spartan6/R_M1_DQ8 ) - ( 5 /FPGA_Spartan6/M1_DQ8 ) + ( 5 /DDR_Banks/M1_DQ8 ) ( 6 /FPGA_Spartan6/M1_DQ9 ) - ( 7 /FPGA_Spartan6/M1_DQ10 ) + ( 7 /DDR_Banks/M1_DQ10 ) ( 8 /FPGA_Spartan6/M1_DQ11 ) ) ( /4C431A63/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} @@ -461,10 +487,10 @@ ( 5 /FPGA_Spartan6/M1_DQ12 ) ( 6 /FPGA_Spartan6/M1_DQ13 ) ( 7 /DDR_Banks/M1_DQ14 ) - ( 8 /DDR_Banks/M1_DQ15 ) + ( 8 /FPGA_Spartan6/M1_DQ15 ) ) ( /4C431A63/4C69DF7A 0402 R16 120 {Lib=R} - ( 1 /FPGA_Spartan6/M1_CLK# ) + ( 1 /DDR_Banks/M1_CLK# ) ( 2 /DDR_Banks/M1_CLK ) ) ( /4C431A63/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4} @@ -473,58 +499,58 @@ ( 3 /FPGA_Spartan6/R_M1_A9 ) ( 4 /FPGA_Spartan6/R_M1_A8 ) ( 5 /DDR_Banks/M1_A8 ) - ( 6 /FPGA_Spartan6/M1_A9 ) + ( 6 /DDR_Banks/M1_A9 ) ( 7 /DDR_Banks/M1_A11 ) - ( 8 /FPGA_Spartan6/M1_A12 ) + ( 8 /DDR_Banks/M1_A12 ) ) ( /4C431A63/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A7 ) ( 2 /FPGA_Spartan6/R_M1_A6 ) ( 3 /FPGA_Spartan6/R_M1_A5 ) ( 4 ? ) - ( 5 /DDR_Banks/M1_A4 ) + ( 5 /FPGA_Spartan6/M1_A4 ) ( 6 /DDR_Banks/M1_A5 ) ( 7 /DDR_Banks/M1_A6 ) - ( 8 /DDR_Banks/M1_A7 ) + ( 8 /FPGA_Spartan6/M1_A7 ) ) ( /4C431A63/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ0 ) ( 2 /FPGA_Spartan6/R_M1_DQ1 ) ( 3 /FPGA_Spartan6/R_M1_DQ2 ) ( 4 /FPGA_Spartan6/R_M1_DQ3 ) - ( 5 /FPGA_Spartan6/M1_DQ3 ) + ( 5 /DDR_Banks/M1_DQ3 ) ( 6 /FPGA_Spartan6/M1_DQ2 ) ( 7 /FPGA_Spartan6/M1_DQ1 ) - ( 8 /FPGA_Spartan6/M1_DQ0 ) + ( 8 /DDR_Banks/M1_DQ0 ) ) ( /4C431A63/4C69D3A4 $noname RP3 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_LDQS ) ( 2 /FPGA_Spartan6/R_M1_LDM ) ( 3 /FPGA_Spartan6/R_M1_WE# ) ( 4 /FPGA_Spartan6/R_M1_CAS# ) - ( 5 /DDR_Banks/M1_CAS# ) - ( 6 /FPGA_Spartan6/M1_WE# ) + ( 5 /FPGA_Spartan6/M1_CAS# ) + ( 6 /DDR_Banks/M1_WE# ) ( 7 /FPGA_Spartan6/M1_LDM ) - ( 8 /FPGA_Spartan6/M1_LDQS ) + ( 8 /DDR_Banks/M1_LDQS ) ) ( /4C431A63/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ4 ) ( 2 /FPGA_Spartan6/R_M1_DQ5 ) ( 3 /FPGA_Spartan6/R_M1_DQ6 ) ( 4 /FPGA_Spartan6/R_M1_DQ7 ) - ( 5 /FPGA_Spartan6/M1_DQ7 ) + ( 5 /DDR_Banks/M1_DQ7 ) ( 6 /FPGA_Spartan6/M1_DQ6 ) ( 7 /FPGA_Spartan6/M1_DQ5 ) - ( 8 /DDR_Banks/M1_DQ4 ) + ( 8 /FPGA_Spartan6/M1_DQ4 ) ) ( /4C431A63/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_RAS# ) ( 2 /FPGA_Spartan6/R_M1_BA0 ) ( 3 /FPGA_Spartan6/R_M1_BA1 ) ( 4 /FPGA_Spartan6/R_M1_A10 ) - ( 5 /FPGA_Spartan6/M1_A10 ) - ( 6 /FPGA_Spartan6/M1_BA1 ) - ( 7 /DDR_Banks/M1_BA0 ) + ( 5 /DDR_Banks/M1_A10 ) + ( 6 /DDR_Banks/M1_BA1 ) + ( 7 /FPGA_Spartan6/M1_BA0 ) ( 8 /FPGA_Spartan6/M1_RAS# ) ) ( /4C431A63/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4} @@ -533,9 +559,9 @@ ( 3 /FPGA_Spartan6/R_M1_A2 ) ( 4 /FPGA_Spartan6/R_M1_A3 ) ( 5 /FPGA_Spartan6/M1_A3 ) - ( 6 /DDR_Banks/M1_A2 ) + ( 6 /FPGA_Spartan6/M1_A2 ) ( 7 /FPGA_Spartan6/M1_A1 ) - ( 8 /DDR_Banks/M1_A0 ) + ( 8 /FPGA_Spartan6/M1_A0 ) ) ( /4C431A63/4C656D9D $noname C66 470nF {Lib=C} ( 1 +2.5V ) @@ -776,7 +802,7 @@ ( L3 /FPGA_Spartan6/R_M0_LDQS ) ( K3 /FPGA_Spartan6/R_M0_A5 ) ( J3 /FPGA_Spartan6/R_M0_DQ4 ) - ( H3 /DDR_Banks/M0_CLK# ) + ( H3 /FPGA_Spartan6/M0_CLK# ) ( G3 /FPGA_Spartan6/R_M0_BA0 ) ( F3 /FPGA_Spartan6/R_M0_A4 ) ( E3 /FPGA_Spartan6/R_M0_A8 ) @@ -786,60 +812,60 @@ ( G10 +3.3V ) ( D10 /FPGA_Spartan6/ETH_TXD0 ) ( C10 /Ethernet_Phy/ETH_TXD2 ) - ( B10 /Ethernet_Phy/ETH_CRS ) - ( A10 /FPGA_Spartan6/ETH_INT ) + ( B10 /FPGA_Spartan6/ETH_CRS ) + ( A10 /Ethernet_Phy/ETH_INT ) ( E9 +3.3V ) - ( D9 /FPGA_Spartan6/ETH_TXEN ) + ( D9 /Ethernet_Phy/ETH_TXEN ) ( C9 /FPGA_Spartan6/ETH_TXD1 ) - ( A9 /FPGA_Spartan6/ETH_COL ) + ( A9 /Ethernet_Phy/ETH_COL ) ( D8 /FPGA_Spartan6/ETH_TXER ) - ( C8 /FPGA_Spartan6/ETH_TXC ) + ( C8 /Ethernet_Phy/ETH_TXC ) ( B8 /FPGA_Spartan6/ETH_RXER ) - ( A8 /Ethernet_Phy/ETH_TXD3 ) - ( D7 /FPGA_Spartan6/ETH_MDC ) + ( A8 /FPGA_Spartan6/ETH_TXD3 ) + ( D7 /Ethernet_Phy/ETH_MDC ) ( C7 /FPGA_Spartan6/ETH_RESET_N ) ( B7 +3.3V ) - ( A7 /Ethernet_Phy/ETH_RXC ) - ( D6 /FPGA_Spartan6/ETH_MDIO ) + ( A7 /FPGA_Spartan6/ETH_RXC ) + ( D6 /Ethernet_Phy/ETH_MDIO ) ( C6 /FPGA_Spartan6/ETH_RXD2 ) ( B6 /Ethernet_Phy/ETH_RXD0 ) - ( A6 /FPGA_Spartan6/ETH_RXDV ) - ( C5 /FPGA_Spartan6/ETH_RXD3 ) + ( A6 /Ethernet_Phy/ETH_RXDV ) + ( C5 /Ethernet_Phy/ETH_RXD3 ) ( A5 /Ethernet_Phy/ETH_RXD1 ) ( B4 +3.3V ) - ( A4 /Ethernet_Phy/ETH_CLK ) + ( A4 /FPGA_Spartan6/ETH_CLK ) ( A3 ? ) ( U19 ? ) ( T19 ? ) - ( R19 /USB/USBA_SPD ) + ( R19 /FPGA_Spartan6/USBA_SPD ) ( P19 ? ) ( B19 +3.3V ) - ( B18 /Non_volatile_memories/SD_DAT1 ) - ( A18 /FPGA_Spartan6/SD_DAT0 ) + ( B18 /FPGA_Spartan6/SD_DAT1 ) + ( A18 /Non_volatile_memories/SD_DAT0 ) ( E17 +3.3V ) - ( D17 /Non_volatile_memories/SD_CMD ) - ( C17 /Non_volatile_memories/SD_DAT3 ) + ( D17 /FPGA_Spartan6/SD_CMD ) + ( C17 /FPGA_Spartan6/SD_DAT3 ) ( A17 /Non_volatile_memories/SD_DAT2 ) - ( E16 /Non_volatile_memories/SD_CLK ) + ( E16 /FPGA_Spartan6/SD_CLK ) ( C16 ? ) ( B16 ? ) ( A16 ? ) - ( D15 /Non_volatile_memories/NF_CS1_N ) - ( C15 /Non_volatile_memories/NF_RE_N ) + ( D15 /FPGA_Spartan6/NF_CS1_N ) + ( C15 /FPGA_Spartan6/NF_RE_N ) ( B15 +3.3V ) ( A15 /FPGA_Spartan6/NF_RNB ) ( G14 +3.3V ) ( D14 /Non_volatile_memories/NF_D1 ) - ( C14 /FPGA_Spartan6/NF_WE_N ) + ( C14 /Non_volatile_memories/NF_WE_N ) ( B14 /FPGA_Spartan6/NF_CLE ) - ( A14 /FPGA_Spartan6/NF_ALE ) + ( A14 /Non_volatile_memories/NF_ALE ) ( E13 +3.3V ) ( C13 ? ) ( A13 /FPGA_Spartan6/NF_D2 ) - ( C12 /Non_volatile_memories/NF_D0 ) - ( B12 /Non_volatile_memories/NF_D3 ) + ( C12 /FPGA_Spartan6/NF_D0 ) + ( B12 /FPGA_Spartan6/NF_D3 ) ( A12 /FPGA_Spartan6/NF_D4 ) - ( D11 /FPGA_Spartan6/NF_D7 ) + ( D11 /Non_volatile_memories/NF_D7 ) ( C11 /Non_volatile_memories/NF_D5 ) ( B11 +3.3V ) ( A11 /FPGA_Spartan6/NF_D6 ) @@ -877,7 +903,7 @@ ( M19 ? ) ( L19 /FPGA_Spartan6/R_M1_LDM ) ( K19 /FPGA_Spartan6/R_M1_A6 ) - ( J19 /FPGA_Spartan6/M1_CLK# ) + ( J19 /DDR_Banks/M1_CLK# ) ( H19 /FPGA_Spartan6/R_M1_WE# ) ( G19 /FPGA_Spartan6/R_M1_A10 ) ( F19 /FPGA_Spartan6/R_M1_A11 ) @@ -892,7 +918,7 @@ ( J18 +2.5V ) ( H18 ? ) ( F18 ? ) - ( P17 /FPGA_Spartan6/USBA_VP ) + ( P17 /USB/USBA_VP ) ( M17 ? ) ( L17 ? ) ( K17 /FPGA_Spartan6/R_M1_BA1 ) @@ -900,7 +926,7 @@ ( H17 ? ) ( G17 ? ) ( F17 ? ) - ( N16 /FPGA_Spartan6/USBA_RCV ) + ( N16 /USB/USBA_RCV ) ( M16 ? ) ( L16 +2.5V ) ( K16 ? ) @@ -919,7 +945,7 @@ ( F13 ? ) ( D13 ? ) ( B13 GND ) - ( Y22 ? ) + ( Y22 N-000127 ) ( A22 GND ) ( R12 +2.5V ) ( P12 GND ) @@ -934,13 +960,13 @@ ( E12 ? ) ( D12 ? ) ( AB1 GND ) - ( A19 ? ) + ( A19 /DBG_PRG/FPGA_TDO ) ( R18 GND ) ( L18 GND ) ( G18 GND ) - ( E18 ? ) + ( E18 /DBG_PRG/FPGA_TDI ) ( D18 GND ) - ( C18 ? ) + ( C18 /DBG_PRG/FPGA_TMS ) ( R17 ? ) ( N17 GND ) ( B17 GND ) @@ -949,12 +975,12 @@ ( D16 +2.5V ) ( AA5 GND ) ( P15 ? ) - ( N15 ? ) + ( N15 GND ) ( M15 +2.5V ) ( K15 +2.5V ) ( J15 GND ) ( H15 +2.5V ) - ( G15 ? ) + ( G15 /DBG_PRG/FPGA_TCK ) ( F15 ? ) ( E15 GND ) ( V14 GND ) @@ -994,7 +1020,7 @@ ( J2 GND ) ( E2 GND ) ( A1 GND ) - ( AA1 ? ) + ( AA1 N-000132 ) ( U21 GND ) ( N21 GND ) ( J21 GND ) @@ -1010,7 +1036,7 @@ ( G11 ? ) ( F11 +2.5V ) ( E11 GND ) - ( Y20 ? ) + ( Y20 +3.3V ) ( V10 GND ) ( R10 +2.5V ) ( P10 GND ) @@ -1196,11 +1222,11 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} - ( 1 /FPGA_Spartan6/ETH_MDIO ) + ( 1 /Ethernet_Phy/ETH_MDIO ) ( 2 +3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000397 ) + ( 1 N-000395 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} @@ -1220,31 +1246,31 @@ ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /FPGA_Spartan6/ETH_MDIO ) - ( 2 /FPGA_Spartan6/ETH_MDC ) - ( 3 /FPGA_Spartan6/ETH_RXD3 ) + ( 1 /Ethernet_Phy/ETH_MDIO ) + ( 2 /Ethernet_Phy/ETH_MDC ) + ( 3 /Ethernet_Phy/ETH_RXD3 ) ( 4 /FPGA_Spartan6/ETH_RXD2 ) ( 5 /Ethernet_Phy/ETH_RXD1 ) ( 6 /Ethernet_Phy/ETH_RXD0 ) ( 7 +3.3V ) ( 8 GND ) - ( 9 /FPGA_Spartan6/ETH_RXDV ) - ( 10 /Ethernet_Phy/ETH_RXC ) + ( 9 /Ethernet_Phy/ETH_RXDV ) + ( 10 /FPGA_Spartan6/ETH_RXC ) ( 11 /FPGA_Spartan6/ETH_RXER ) ( 12 GND ) ( 13 +1.8V ) ( 14 /FPGA_Spartan6/ETH_TXER ) - ( 15 /FPGA_Spartan6/ETH_TXC ) - ( 16 /FPGA_Spartan6/ETH_TXEN ) + ( 15 /Ethernet_Phy/ETH_TXC ) + ( 16 /Ethernet_Phy/ETH_TXEN ) ( 17 /FPGA_Spartan6/ETH_TXD0 ) ( 18 /FPGA_Spartan6/ETH_TXD1 ) ( 19 /Ethernet_Phy/ETH_TXD2 ) - ( 20 /Ethernet_Phy/ETH_TXD3 ) - ( 21 /FPGA_Spartan6/ETH_COL ) - ( 22 /Ethernet_Phy/ETH_CRS ) + ( 20 /FPGA_Spartan6/ETH_TXD3 ) + ( 21 /Ethernet_Phy/ETH_COL ) + ( 22 /FPGA_Spartan6/ETH_CRS ) ( 23 GND ) ( 24 +3.3V ) - ( 25 /FPGA_Spartan6/ETH_INT ) + ( 25 /Ethernet_Phy/ETH_INT ) ( 26 /Ethernet_Phy/ETH_LED0 ) ( 27 /Ethernet_Phy/ETH_LED1 ) ( 28 ? ) @@ -1256,7 +1282,7 @@ ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000397 ) + ( 37 N-000395 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) ( 40 /Ethernet_Phy/MAG_TX- ) @@ -1265,7 +1291,7 @@ ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 /Ethernet_Phy/ETH_CLK ) + ( 46 /FPGA_Spartan6/ETH_CLK ) ( 47 /Ethernet_Phy/ETH_PLL1.8V ) ( 48 /FPGA_Spartan6/ETH_RESET_N ) ) @@ -1286,11 +1312,11 @@ ( 2 /Ethernet_Phy/MAG_RX+ ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000398 ) + ( 1 N-000394 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000395 ) + ( 1 N-000393 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} @@ -1303,57 +1329,57 @@ ( 7 /Ethernet_Phy/MAG_RX+ ) ( 8 /Ethernet_Phy/MAG_RX- ) ( 9 +3.3V ) - ( 10 N-000395 ) + ( 10 N-000393 ) ( 11 +3.3V ) - ( 12 N-000398 ) + ( 12 N-000394 ) ( 13 /Ethernet_Phy/MAG_SHIELD ) ( 14 /Ethernet_Phy/MAG_SHIELD ) ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /FPGA_Spartan6/M1_DQ0 ) + ( 2 /DDR_Banks/M1_DQ0 ) ( 3 +2.5V ) ( 4 /FPGA_Spartan6/M1_DQ1 ) ( 5 /FPGA_Spartan6/M1_DQ2 ) ( 6 GND ) - ( 7 /FPGA_Spartan6/M1_DQ3 ) - ( 8 /DDR_Banks/M1_DQ4 ) + ( 7 /DDR_Banks/M1_DQ3 ) + ( 8 /FPGA_Spartan6/M1_DQ4 ) ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M1_DQ5 ) ( 11 /FPGA_Spartan6/M1_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Spartan6/M1_DQ7 ) + ( 13 /DDR_Banks/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /FPGA_Spartan6/M1_LDQS ) + ( 16 /DDR_Banks/M1_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) ( 20 /FPGA_Spartan6/M1_LDM ) - ( 21 /FPGA_Spartan6/M1_WE# ) - ( 22 /DDR_Banks/M1_CAS# ) + ( 21 /DDR_Banks/M1_WE# ) + ( 22 /FPGA_Spartan6/M1_CAS# ) ( 23 /FPGA_Spartan6/M1_RAS# ) ( 24 /FPGA_Spartan6/M1_CS# ) ( 25 ? ) - ( 26 /DDR_Banks/M1_BA0 ) - ( 27 /FPGA_Spartan6/M1_BA1 ) - ( 28 /FPGA_Spartan6/M1_A10 ) - ( 29 /DDR_Banks/M1_A0 ) + ( 26 /FPGA_Spartan6/M1_BA0 ) + ( 27 /DDR_Banks/M1_BA1 ) + ( 28 /DDR_Banks/M1_A10 ) + ( 29 /FPGA_Spartan6/M1_A0 ) ( 30 /FPGA_Spartan6/M1_A1 ) - ( 31 /DDR_Banks/M1_A2 ) + ( 31 /FPGA_Spartan6/M1_A2 ) ( 32 /FPGA_Spartan6/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /DDR_Banks/M1_A4 ) + ( 35 /FPGA_Spartan6/M1_A4 ) ( 36 /DDR_Banks/M1_A5 ) ( 37 /DDR_Banks/M1_A6 ) - ( 38 /DDR_Banks/M1_A7 ) + ( 38 /FPGA_Spartan6/M1_A7 ) ( 39 /DDR_Banks/M1_A8 ) - ( 40 /FPGA_Spartan6/M1_A9 ) + ( 40 /DDR_Banks/M1_A9 ) ( 41 /DDR_Banks/M1_A11 ) - ( 42 /FPGA_Spartan6/M1_A12 ) + ( 42 /DDR_Banks/M1_A12 ) ( 43 ? ) - ( 44 /FPGA_Spartan6/M1_CLK# ) + ( 44 /DDR_Banks/M1_CLK# ) ( 45 /FPGA_Spartan6/M1_CKE ) ( 46 /DDR_Banks/M1_CLK ) ( 47 /FPGA_Spartan6/M1_UDM ) @@ -1363,10 +1389,10 @@ ( 51 /FPGA_Spartan6/M1_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /FPGA_Spartan6/M1_DQ8 ) + ( 54 /DDR_Banks/M1_DQ8 ) ( 55 +2.5V ) ( 56 /FPGA_Spartan6/M1_DQ9 ) - ( 57 /FPGA_Spartan6/M1_DQ10 ) + ( 57 /DDR_Banks/M1_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M1_DQ11 ) ( 60 /FPGA_Spartan6/M1_DQ12 ) @@ -1374,7 +1400,7 @@ ( 62 /FPGA_Spartan6/M1_DQ13 ) ( 63 /DDR_Banks/M1_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M1_DQ15 ) + ( 65 /FPGA_Spartan6/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} @@ -1477,16 +1503,16 @@ ( 1 +2.5V ) ( 2 /FPGA_Spartan6/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /DDR_Banks/M0_DQ1 ) + ( 4 /FPGA_Spartan6/M0_DQ1 ) ( 5 /FPGA_Spartan6/M0_DQ2 ) ( 6 GND ) - ( 7 /FPGA_Spartan6/M0_DQ3 ) + ( 7 /DDR_Banks/M0_DQ3 ) ( 8 /FPGA_Spartan6/M0_DQ4 ) ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M0_DQ5 ) - ( 11 /FPGA_Spartan6/M0_DQ6 ) + ( 11 /DDR_Banks/M0_DQ6 ) ( 12 GND ) - ( 13 /DDR_Banks/M0_DQ7 ) + ( 13 /FPGA_Spartan6/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /FPGA_Spartan6/M0_LDQS ) @@ -1494,51 +1520,51 @@ ( 18 +2.5V ) ( 19 ? ) ( 20 /FPGA_Spartan6/M0_LDM ) - ( 21 /FPGA_Spartan6/M0_WE# ) - ( 22 /DDR_Banks/M0_CAS# ) + ( 21 /DDR_Banks/M0_WE# ) + ( 22 /FPGA_Spartan6/M0_CAS# ) ( 23 /FPGA_Spartan6/M0_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 /DDR_Banks/M0_BA0 ) + ( 26 /FPGA_Spartan6/M0_BA0 ) ( 27 /FPGA_Spartan6/M0_BA1 ) ( 28 /FPGA_Spartan6/M0_A10 ) - ( 29 /FPGA_Spartan6/M0_A0 ) - ( 30 /DDR_Banks/M0_A1 ) - ( 31 /FPGA_Spartan6/M0_A2 ) - ( 32 /FPGA_Spartan6/M0_A3 ) + ( 29 /DDR_Banks/M0_A0 ) + ( 30 /FPGA_Spartan6/M0_A1 ) + ( 31 /DDR_Banks/M0_A2 ) + ( 32 /DDR_Banks/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /FPGA_Spartan6/M0_A4 ) + ( 35 /DDR_Banks/M0_A4 ) ( 36 /FPGA_Spartan6/M0_A5 ) - ( 37 /DDR_Banks/M0_A6 ) - ( 38 /FPGA_Spartan6/M0_A7 ) - ( 39 /DDR_Banks/M0_A8 ) + ( 37 /FPGA_Spartan6/M0_A6 ) + ( 38 /DDR_Banks/M0_A7 ) + ( 39 /FPGA_Spartan6/M0_A8 ) ( 40 /FPGA_Spartan6/M0_A9 ) ( 41 /FPGA_Spartan6/M0_A11 ) ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) - ( 44 /DDR_Banks/M0_CLK# ) - ( 45 /FPGA_Spartan6/M0_CKE ) + ( 44 /FPGA_Spartan6/M0_CLK# ) + ( 45 /DDR_Banks/M0_CKE ) ( 46 /FPGA_Spartan6/M0_CLK ) - ( 47 /FPGA_Spartan6/M0_UDM ) + ( 47 /DDR_Banks/M0_UDM ) ( 48 GND ) ( 49 /DDR_Banks/M0_VREF ) ( 50 ? ) - ( 51 /DDR_Banks/M0_UDQS ) + ( 51 /FPGA_Spartan6/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M0_DQ8 ) + ( 54 /FPGA_Spartan6/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /DDR_Banks/M0_DQ9 ) - ( 57 /DDR_Banks/M0_DQ10 ) + ( 56 /FPGA_Spartan6/M0_DQ9 ) + ( 57 /FPGA_Spartan6/M0_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M0_DQ11 ) ( 60 /FPGA_Spartan6/M0_DQ12 ) ( 61 +2.5V ) ( 62 /FPGA_Spartan6/M0_DQ13 ) - ( 63 /FPGA_Spartan6/M0_DQ14 ) + ( 63 /DDR_Banks/M0_DQ14 ) ( 64 GND ) - ( 65 /FPGA_Spartan6/M0_DQ15 ) + ( 65 /DDR_Banks/M0_DQ15 ) ( 66 GND ) ) ) @@ -1680,6 +1706,18 @@ $component C13 C? C1-1 $endlist +$component R30 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R29 + R? + SM0603 + SM0805 + R?-* +$endlist $component C77 SM* C? @@ -2141,1180 +2179,1202 @@ $endfootprintlist } { Pin List by Nets Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" - U1 T5 U8 1 -Net 2 "/Non volatile memories/NF_RE_N" "NF_RE_N" - U1 C15 + U1 T5 +Net 2 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" + U8 6 + U1 AA21 +Net 3 "/FPGA Spartan6/NF_RNB" "NF_RNB" + U5 6 + U5 7 + U1 A15 +Net 4 "/FPGA Spartan6/NF_RE_N" "NF_RE_N" U5 8 -Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" - U1 D15 + U1 C15 +Net 5 "/FPGA Spartan6/NF_CS1_N" "NF_CS1_N" U5 9 -Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE" - U5 17 + U1 D15 +Net 6 "/Non volatile memories/NF_ALE" "NF_ALE" U1 A14 -Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" - U1 C8 - U4 15 -Net 6 "/Ethernet Phy/ETH_RXC" "ETH_RXC" - U4 10 - U1 A7 -Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK" - U1 A4 - U4 46 -Net 8 "/USB/USBA_SPD" "USBA_SPD" - U1 R19 - U6 2 -Net 9 "/USB/USBA_OE_N" "USBA_OE_N" - U1 P18 - U6 9 -Net 10 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" - U6 3 - U1 N16 -Net 11 "/FPGA Spartan6/USBA_VP" "USBA_VP" - U6 4 - U1 P17 -Net 12 "/USB/USBA_VM" "USBA_VM" - U6 5 - U1 M18 -Net 13 "/FPGA Spartan6/ETH_COL" "ETH_COL" + U5 17 +Net 7 "/Non volatile memories/NF_WE_N" "NF_WE_N" + U5 18 + U1 C14 +Net 8 "/Ethernet Phy/ETH_COL" "ETH_COL" U4 21 U1 A9 -Net 14 "/Ethernet Phy/ETH_CRS" "ETH_CRS" - U1 B10 +Net 9 "/Ethernet Phy/ETH_TXC" "ETH_TXC" + U1 C8 + U4 15 +Net 10 "/FPGA Spartan6/ETH_RXC" "ETH_RXC" + U4 10 + U1 A7 +Net 11 "/FPGA Spartan6/USBA_SPD" "USBA_SPD" + U6 2 + U1 R19 +Net 12 "/USB/USBA_OE_N" "USBA_OE_N" + U6 9 + U1 P18 +Net 13 "/USB/USBA_RCV" "USBA_RCV" + U1 N16 + U6 3 +Net 14 "/USB/USBA_VP" "USBA_VP" + U1 P17 + U6 4 +Net 15 "/USB/USBA_VM" "USBA_VM" + U6 5 + U1 M18 +Net 16 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" U4 22 -Net 15 "/Non volatile memories/SD_CLK" "SD_CLK" - J1 5 + U1 B10 +Net 17 "/FPGA Spartan6/SD_CLK" "SD_CLK" U1 E16 -Net 16 "/FPGA Spartan6/ETH_INT" "ETH_INT" - U1 A10 - U4 25 -Net 17 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" + J1 5 +Net 18 "/Ethernet Phy/ETH_MDC" "ETH_MDC" U4 2 U1 D7 -Net 18 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" - R1 1 - U1 D6 +Net 19 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" U4 1 -Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" + U1 D6 + R1 1 +Net 20 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" U4 48 U1 C7 -Net 20 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" +Net 21 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" U4 9 U1 A6 -Net 21 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" +Net 22 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" U1 B8 U4 11 -Net 22 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" - U4 14 - U1 D8 -Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" - U1 D9 +Net 23 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" U4 16 + U1 D9 Net 24 "/FPGA Spartan6/M1_CS#" "M1_CS#" R20 2 U3 24 Net 25 "/FPGA Spartan6/M1_UDM" "M1_UDM" - R18 2 U3 47 -Net 26 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" - RP3 8 + R18 2 +Net 26 "/DDR Banks/M1_LDQS" "M1_LDQS" U3 16 + RP3 8 Net 27 "/FPGA Spartan6/M1_LDM" "M1_LDM" - U3 20 RP3 7 + U3 20 Net 28 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" - U3 51 R19 2 -Net 29 "/DDR Banks/M0_UDQS" "M0_UDQS" - U2 51 + U3 51 +Net 29 "/FPGA Spartan6/M0_UDQS" "M0_UDQS" R22 2 + U2 51 Net 30 "/FPGA Spartan6/M0_LDM" "M0_LDM" U2 20 RP16 7 -Net 31 "/DDR Banks/M1_CAS#" "M1_CAS#" +Net 31 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" RP3 5 U3 22 Net 32 "/FPGA Spartan6/M1_CKE" "M1_CKE" - U3 45 R17 2 + U3 45 Net 33 "/DDR Banks/M1_CLK" "M1_CLK" - U1 H20 U3 46 + U1 H20 R16 2 -Net 34 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" +Net 34 "/DDR Banks/M1_CLK#" "M1_CLK#" U3 44 - R16 1 U1 J19 + R16 1 Net 35 "GND" "GND" - U2 48 - C24 2 - C25 2 - C7 2 - C23 2 - R2 2 - C1 2 - C5 2 - C21 2 - C3 2 + C67 2 + J1 6 + C64 2 + C61 2 U2 58 - C26 2 - C27 2 - C33 2 - C28 2 - C29 2 - C31 2 - C30 2 - C32 2 - C75 1 - U1 AA5 - U1 W16 - U5 13 - U1 B17 - U1 N17 - U1 D18 - U1 G18 - U1 L18 - U1 R18 - C76 2 - U1 W19 - U1 AA9 - U1 AB22 - U1 AA13 + C58 2 + U2 48 + C55 2 + C68 2 U1 AA17 - U1 B13 - U1 J13 - U1 L13 - U1 N13 + R14 2 U1 K14 U1 M14 U1 P14 + C22 2 U1 V14 + C60 2 U1 E15 + C63 2 U1 J15 - U1 J11 - U1 L11 - U1 N11 - U1 E21 - U1 J21 - U1 N21 - U1 U21 - U1 AB1 - U1 K12 - U1 M12 - U1 P12 - U1 A22 - U1 H7 - U1 U7 - U1 W7 - U1 B9 - U1 J9 - C72 2 - U1 L9 - C73 2 - U1 N9 - C74 2 - U1 K10 - U1 M10 - U1 P10 - U1 V10 - J1 CASE - J1 CASE - U5 36 - C77 2 - U1 A1 - U1 E2 - U1 J2 - J1 CASE - J1 COM - U1 N2 - U1 U2 - U1 D4 - J1 6 - U1 V4 - U1 B5 - U1 G5 - U1 L5 - U1 R5 - U1 E7 - U2 34 - U2 24 - U2 52 - U2 12 + U1 N15 + U1 AA5 + U1 W16 + U1 B17 + U1 N17 + U1 D18 + U2 6 + C40 2 + C43 2 + C52 2 + C46 2 U2 66 - C58 2 - C55 2 - C68 2 + J1 CASE + J1 CASE + J1 CASE U2 64 C18 2 + C20 2 + C57 2 + U1 G18 + U1 L18 + U1 R18 + U1 W19 + R12 2 + U1 AA9 + U1 AB22 + U1 AA13 + C44 2 + C47 2 + C48 2 + U8 4 + C45 2 + C42 2 + C39 2 + U5 13 + C50 2 + C66 2 + C56 2 + C62 2 + U5 36 + C59 2 + C49 2 + C51 2 + C53 2 + C41 2 + C72 2 + C73 2 + C74 2 + C75 1 + C24 2 + C26 2 + C21 2 + C27 2 + C32 2 + C30 2 + C31 2 + C29 2 + C28 2 + C33 2 + C23 2 + C25 2 + U2 34 + U2 24 + C69 2 + U2 52 + C54 2 + U2 12 + J1 COM U3 58 C34 2 C71 2 C70 2 - C64 2 - C61 2 - U8 4 - C51 2 - C49 2 - C46 2 - C52 2 - C43 2 - C40 2 - C48 2 - C45 2 - C42 2 - C39 2 + V3 2 + C38 2 + R15 2 + U1 L11 + U1 J11 U1 E11 - C20 2 - C65 2 - C62 2 - C59 2 - C56 2 - R12 2 - C50 2 - C47 2 - C44 2 - R14 2 - C41 2 - C22 2 - C53 2 - C66 2 - C63 2 - U2 6 - C60 2 - C57 2 - C54 2 - C69 2 - C67 2 - V1 2 - V2 2 + U1 V10 + U1 P10 + U1 M10 + U1 K10 + L7 2 + U7 8 + U7 7 + L5 2 + U1 N11 R10 2 C16 2 + V1 2 + V2 2 + C37 2 + V4 2 + U4 12 + C8 2 + C7 2 + C5 2 + C3 2 + C1 2 + R2 2 + C11 2 + C10 2 + J4 4 + J4 5 + U4 23 C15 2 C14 2 C13 2 U6 7 + U1 N9 + U1 L9 + U1 J9 + U1 N13 + U1 L13 U6 8 - L7 2 - L5 2 - C81 2 + C36 2 + C35 2 + C12 2 + R9 2 + U4 8 U9 8 U9 PAD U11 2 U10 2 U10 5 U10 PAD - R25 2 C80 2 + R25 2 C78 2 U12 2 R27 2 C85 2 + C81 2 C82 2 C84 2 - C35 2 - U4 39 - U4 12 - U4 23 - U4 44 - U4 35 - U4 36 - R15 2 - C38 2 - V3 2 - V4 2 - C37 2 - C36 2 + U1 B9 + U1 U21 + C76 2 + C77 2 + U1 N21 + U1 J21 + U1 E21 + U1 D4 + U1 U2 + U1 N2 + U1 J2 + U1 E2 + U1 A1 + C65 2 + U1 W7 + U1 U7 + U1 H7 + U1 E7 + U1 R5 + U1 L5 + U1 G5 + U1 B5 + U1 V4 C9 2 C6 2 C4 2 C2 2 - C11 2 - C10 2 - C12 2 - R9 2 - U4 8 - C8 2 - J4 4 - J4 5 - U7 8 - U7 7 + U4 44 + U1 J13 + U4 35 + U4 36 + U1 B13 + U4 39 + U1 A22 + U1 P12 + U1 M12 + U1 K12 + U1 AB1 + U3 6 + U3 64 + U3 34 U3 52 U3 12 U3 48 U3 66 - U3 64 - U3 34 - U3 6 -Net 36 "/DDR Banks/M0_CLK#" "M0_CLK#" +Net 36 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" U1 H3 R21 2 U2 44 Net 37 "/FPGA Spartan6/M0_CLK" "M0_CLK" - R21 1 - U2 46 U1 H4 -Net 38 "/FPGA Spartan6/M0_CKE" "M0_CKE" + U2 46 + R21 1 +Net 38 "/DDR Banks/M0_CKE" "M0_CKE" R24 2 U2 45 -Net 39 "/DDR Banks/M0_CAS#" "M0_CAS#" - RP16 5 +Net 39 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" U2 22 -Net 40 "/FPGA Spartan6/M1_WE#" "M1_WE#" + RP16 5 +Net 40 "/DDR Banks/M1_WE#" "M1_WE#" U3 21 RP3 6 Net 41 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" - U3 23 RP2 8 + U3 23 Net 42 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" - RP15 8 U2 23 -Net 43 "/FPGA Spartan6/M0_WE#" "M0_WE#" - RP16 6 + RP15 8 +Net 43 "/DDR Banks/M0_WE#" "M0_WE#" U2 21 -Net 44 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" + RP16 6 +Net 44 "/Ethernet Phy/ETH_INT" "ETH_INT" + U4 25 + U1 A10 +Net 45 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" + U4 46 + U1 A4 +Net 46 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" + U1 D8 + U4 14 +Net 47 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" U2 16 RP16 8 -Net 45 "/FPGA Spartan6/M0_UDM" "M0_UDM" - R23 2 +Net 48 "/DDR Banks/M0_UDM" "M0_UDM" U2 47 -Net 46 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" - U8 6 - U1 AA21 -Net 47 "/FPGA Spartan6/NF_RNB" "NF_RNB" - U1 A15 - U5 7 - U5 6 -Net 48 "/FPGA Spartan6/NF_WE_N" "NF_WE_N" - U1 C14 - U5 18 + R23 2 Net 49 "/FPGA Spartan6/NF_CLE" "NF_CLE" U5 16 U1 B14 -Net 50 "/Non volatile memories/SD_CMD" "SD_CMD" - J1 3 +Net 50 "/FPGA Spartan6/SD_CMD" "SD_CMD" U1 D17 -Net 55 "+2.5V" "+2.5V" - U1 G12 - U2 18 - U1 F11 - U3 15 - U1 U11 - U1 R10 + J1 3 +Net 51 "/DBG_PRG/FPGA_TCK" "FPGA_TCK" + U1 G15 + J6 1 +Net 52 "/DBG_PRG/FPGA_TMS" "FPGA_TMS" + J6 3 + U1 C18 +Net 53 "/DBG_PRG/FPGA_TDI" "FPGA_TDI" + U1 E18 + J6 7 +Net 54 "/DBG_PRG/FPGA_TDO" "FPGA_TDO" + U1 A19 + J6 5 +Net 59 "+2.5V" "+2.5V" U1 U18 + C32 1 + C30 1 U1 E19 - U1 D16 - C70 1 - C71 1 - C34 1 - U1 R12 - U2 61 - U1 L8 - U1 N8 - U1 H9 - U2 33 - C66 1 - U3 3 - U2 9 - C63 1 - C60 1 - C57 1 - C54 1 - U2 3 - U2 1 - C17 1 - U3 9 - C37 1 + C31 1 + C29 1 + C28 1 + U1 F6 + C68 1 C65 1 C62 1 - C19 1 - C59 1 - C56 1 - R11 1 - R13 1 - C53 1 - C51 1 - U2 15 - C68 1 - U2 55 - C46 1 - C52 1 - U3 18 - C43 1 - C40 1 - U7 1 - U3 33 - U3 61 U3 1 U3 55 - C49 1 - C77 1 - U1 F4 + U1 N18 + U1 L7 + U1 J18 U1 R6 U1 V6 - U6 1 - U1 L2 - U1 G2 - U1 C2 - U1 F6 - U1 U5 - U1 N5 - U1 J5 - C15 1 + U1 L8 + U1 N8 C27 1 + U1 L16 + C24 1 + C26 1 + C21 1 + U3 3 + C25 1 + C77 1 + C66 1 + C52 1 + C43 1 + C40 1 + C63 1 + U2 15 + C60 1 + U1 J5 + C57 1 + C54 1 + U1 N5 + U1 U5 + U3 61 + C59 1 + C56 1 + C23 1 C22 1 C33 1 - C28 1 - C29 1 - C31 1 - U1 L16 - C30 1 - U1 J18 - C32 1 - U1 N18 - U1 H15 - U1 K15 + C53 1 + U3 9 + C51 1 + C49 1 + C46 1 + U2 33 + U3 15 + C19 1 + C15 1 + U3 33 + C17 1 + U2 1 + U2 3 + R13 1 + C37 1 + U2 9 + U1 D16 U1 M15 + U1 K15 + U1 H15 + R11 1 + U2 61 + U6 1 + U2 18 + C34 1 + C71 1 + U3 18 + U1 R2 + U1 H9 + U1 L2 + U1 G21 + U2 55 + U1 C21 + U1 G12 + U1 W2 + U1 R12 + U1 F4 + U7 1 + U1 G2 + U1 R10 + C70 1 + U1 W21 + U1 F11 U1 R21 U1 L21 - U1 G21 - U1 C21 - U1 L7 - U1 W21 - C24 1 - C25 1 - C23 1 - U1 W2 - U1 R2 - C21 1 - C26 1 -Net 58 "/DDR Banks/M0_VREF" "M0_VREF" - R11 2 - C18 1 + U1 C2 + U1 U11 +Net 62 "/DDR Banks/M0_VREF" "M0_VREF" R12 1 - U2 49 + R11 2 C17 2 -Net 59 "/DDR Banks/M1_VREF" "M1_VREF" + U2 49 + C18 1 +Net 63 "/DDR Banks/M1_VREF" "M1_VREF" R13 2 R14 1 U3 49 - C19 2 C20 1 -Net 68 "VCCO2" "VCCO2" - C58 1 - C55 1 - U1 V16 - U1 AA3 + C19 2 +Net 73 "VCCO2" "VCCO2" U1 T13 - U1 W5 - U8 8 - C61 1 - C64 1 - C67 1 C69 1 - U1 AA11 - U1 AA7 - U1 AA19 - U1 AA15 + C67 1 + U8 8 + C64 1 U1 V12 - U1 T9 + C61 1 + U1 AA3 + C58 1 U1 V8 -Net 87 "+3.3V" "+3.3V" - U1 B7 - U1 B4 + C55 1 + U1 W5 + U1 T9 + U1 AA11 + U1 AA15 + U1 AA19 + U1 V16 + U1 AA7 +Net 90 "+3.3V" "+3.3V" + L8 1 + C81 1 + C36 1 + U1 Y20 + J4 6 + C10 1 R4 1 R6 1 - R5 1 + C1 1 + C35 1 + U6 12 + C79 1 + C80 1 + C14 1 + L2 1 + R26 1 + U4 24 + C13 1 U1 E17 U1 B19 - U4 24 - R3 1 - R26 1 - C80 1 - C79 1 - C81 1 - L8 1 - U7 12 - U6 12 - U6 14 - C36 1 - C35 1 - C14 1 - C13 1 - U7 14 - U5 12 - U5 37 - U5 19 - J1 4 - C50 1 - C47 1 - C44 1 - C41 1 - C72 1 - C73 1 - C74 1 - C75 2 - U1 G14 - U1 E13 - C11 1 - R1 2 - U1 B11 - U1 G10 - C1 1 - U1 E9 C3 1 C5 1 - L2 1 - U4 7 - C10 1 - J4 11 - J4 9 - J4 6 - J4 3 + U1 B11 + R1 2 + R3 1 + U1 E13 + U6 14 + U1 G14 U1 B15 -Net 100 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" - RP6 3 - U1 K20 -Net 101 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" - RP7 1 - U1 D22 -Net 102 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" - RP7 3 - U1 C22 -Net 104 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" - U1 E22 - RP1 3 -Net 105 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" - RP1 2 - U1 F22 -Net 106 "/FPGA Spartan6/R_M0_A1" "R_M0_A1" - U1 H1 - RP14 2 -Net 107 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1" - RP15 3 - U1 G1 -Net 108 "/FPGA Spartan6/R_M0_A2" "R_M0_A2" - U1 H5 - RP14 3 -Net 109 "/FPGA Spartan6/R_M0_A5" "R_M0_A5" - RP17 3 - U1 K3 -Net 110 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" - U1 V2 - RP10 3 -Net 111 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" - RP10 1 - U1 U3 -Net 112 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" - U1 P1 - RP11 2 -Net 113 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" - RP11 4 - U1 R1 -Net 114 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10" - RP11 3 - U1 R3 -Net 115 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" - U1 N1 - RP13 2 -Net 116 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" - RP13 4 - U1 M1 -Net 117 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" - U1 J3 - RP12 1 -Net 118 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" - U1 K2 - RP12 3 -Net 119 "/FPGA Spartan6/R_M0_A4" "R_M0_A4" - RP17 4 - U1 F3 -Net 120 "/FPGA Spartan6/R_M0_A3" "R_M0_A3" - U1 K6 - RP14 4 -Net 121 "/FPGA Spartan6/R_M0_A9" "R_M0_A9" - U1 E1 - RP18 3 -Net 122 "/FPGA Spartan6/R_M0_A11" "R_M0_A11" - U1 C1 - RP18 2 -Net 164 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" - RP9 2 - U1 R20 -Net 165 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" - RP2 3 - U1 K17 -Net 166 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" - RP2 2 - U1 J17 -Net 167 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" - RP8 4 - U1 U20 -Net 168 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" - U1 M21 - RP5 3 -Net 169 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" - RP5 1 - U1 N20 -Net 171 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" - RP3 3 - U1 H19 -Net 190 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" - U1 V22 - RP8 1 -Net 191 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" - RP8 3 - U1 U22 -Net 193 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" - U1 R22 - RP9 1 -Net 194 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" - RP9 3 - U1 P22 -Net 195 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" - RP5 2 - U1 N22 -Net 202 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" - RP6 2 - U1 K19 -Net 203 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" - RP2 4 - U1 G19 -Net 204 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" - U1 F19 - RP7 2 -Net 207 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" - U1 M20 - R18 1 -Net 237 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" - RP10 4 - U1 V1 -Net 238 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" - U1 U1 - RP10 2 -Net 241 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" - RP12 4 - U1 K1 -Net 242 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" - RP12 2 - U1 J1 -Net 244 "/FPGA Spartan6/R_M0_A12" "R_M0_A12" + J4 3 + J1 4 + U1 E9 + C72 1 + U1 G10 + J4 11 + C73 1 + J4 9 + C74 1 + C75 2 + U7 14 + U7 12 + U4 7 + R30 1 + U5 12 + U5 19 + R29 1 + C41 1 + C44 1 + C47 1 + C50 1 + U5 37 + C11 1 + R5 1 + U1 B4 + U1 B7 +Net 104 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0" + U1 G3 + RP15 2 +Net 105 "/FPGA Spartan6/R_M0_A12" "R_M0_A12" RP18 1 U1 D1 -Net 308 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" - RP4 1 - U1 J20 -Net 309 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" - U1 G20 - RP1 4 -Net 311 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" - U1 E20 - RP6 1 -Net 313 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" - U1 C20 - RP7 4 -Net 331 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" - U1 M22 - RP5 4 -Net 333 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" - RP4 4 - U1 K22 -Net 334 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" - U1 J22 - RP4 2 -Net 337 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" - U1 V21 - RP8 2 -Net 338 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" - RP9 4 - U1 P21 -Net 339 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" - RP4 3 - U1 K21 -Net 340 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" - RP1 1 - U1 F21 -Net 349 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" - RP13 1 - U1 N3 -Net 350 "/FPGA Spartan6/R_M0_LDQS" "R_M0_LDQS" - RP16 1 - U1 L3 -Net 351 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0" - RP15 2 - U1 G3 -Net 352 "/FPGA Spartan6/R_M0_A8" "R_M0_A8" - U1 E3 +Net 106 "/FPGA Spartan6/R_M0_A8" "R_M0_A8" RP18 4 -Net 357 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" - U1 P2 - RP11 1 -Net 358 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" - RP13 3 - U1 M2 -Net 359 "/FPGA Spartan6/R_M0_A0" "R_M0_A0" - U1 H2 - RP14 1 -Net 361 "/FPGA Spartan6/R_M0_A7" "R_M0_A7" - RP17 1 - U1 H6 -Net 375 "/FPGA Spartan6/R_M0_A6" "R_M0_A6" - U1 J4 - RP17 2 -Net 376 "/FPGA Spartan6/R_M0_A10" "R_M0_A10" + U1 E3 +Net 107 "/FPGA Spartan6/R_M0_A10" "R_M0_A10" U1 G4 RP15 4 -Net 380 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" +Net 108 "/FPGA Spartan6/R_M0_A7" "R_M0_A7" + RP17 1 + U1 H6 +Net 109 "/FPGA Spartan6/R_M0_A6" "R_M0_A6" + RP17 2 + U1 J4 +Net 110 "/FPGA Spartan6/R_M0_A0" "R_M0_A0" + RP14 1 + U1 H2 +Net 111 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" + RP10 4 + U1 V1 +Net 112 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" + RP10 2 + U1 U1 +Net 113 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" + RP11 1 + U1 P2 +Net 114 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" + RP13 1 + U1 N3 +Net 115 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" + U1 M2 + RP13 3 +Net 116 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" + RP12 2 + U1 J1 +Net 117 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" + RP12 4 + U1 K1 +Net 127 "" "" + R30 2 + U1 Y22 +Net 132 "" "" + U1 AA1 + R29 2 +Net 139 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" RP2 1 U1 H21 -Net 381 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" +Net 140 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" U1 H22 RP3 4 -Net 382 "+1.2V" "+1.2V" - C85 1 - L9 1 - R28 1 - C48 1 +Net 141 "+1.2V" "+1.2V" + C83 1 + C84 1 C45 1 - C42 1 - C39 1 - U1 K11 - U1 M11 - U1 P11 + C48 1 + U1 J8 U1 J12 U1 L12 U1 N12 - U1 J8 + U1 K13 + U1 M13 + U1 P13 U1 K9 U1 M9 U1 P9 U1 J10 + C76 1 + C39 1 + C42 1 + U1 R14 + U1 N14 + U1 L14 + U1 J14 U1 L10 U1 N10 - U1 K13 - U1 M13 - U1 P13 - U1 J14 - U1 L14 - U1 N14 - U1 R14 - C83 1 - C76 1 - C84 1 -Net 383 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" - R19 1 - U1 T21 -Net 384 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" - U1 D21 - R17 1 -Net 385 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" + U1 K11 + U1 M11 + U1 P11 + C85 1 + L9 1 + R28 1 +Net 143 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" + RP6 2 + U1 K19 +Net 144 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" + U1 G19 + RP2 4 +Net 145 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" + RP7 2 + U1 F19 +Net 153 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" + U1 K17 + RP2 3 +Net 154 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" + RP2 2 + U1 J17 +Net 165 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" + U1 F21 + RP1 1 +Net 170 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" + RP8 4 + U1 U20 +Net 172 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" + U1 R20 + RP9 2 +Net 174 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" + RP5 1 + U1 N20 +Net 175 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" + RP6 3 + U1 K20 +Net 176 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" + U1 J20 + RP4 1 +Net 177 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" + RP1 4 + U1 G20 +Net 179 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" + U1 E20 + RP6 1 +Net 181 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" + U1 C20 + RP7 4 +Net 189 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" R20 1 U1 H16 +Net 194 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" + U1 V22 + RP8 1 +Net 195 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" + RP8 3 + U1 U22 +Net 197 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" + U1 R22 + RP9 1 +Net 198 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" + RP9 3 + U1 P22 +Net 199 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" + U1 N22 + RP5 2 +Net 200 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" + RP5 4 + U1 M22 +Net 202 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" + RP4 4 + U1 K22 +Net 203 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" + RP4 2 + U1 J22 +Net 205 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" + U1 F22 + RP1 2 +Net 206 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" + U1 E22 + RP1 3 +Net 207 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" + RP7 1 + U1 D22 +Net 208 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" + RP7 3 + U1 C22 +Net 210 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" + U1 V21 + RP8 2 +Net 211 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" + U1 P21 + RP9 4 +Net 212 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" + RP5 3 + U1 M21 +Net 213 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" + U1 K21 + RP4 3 +Net 304 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" + RP10 1 + U1 U3 +Net 306 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10" + U1 R3 + RP11 3 +Net 308 "/FPGA Spartan6/R_M0_A5" "R_M0_A5" + RP17 3 + U1 K3 +Net 309 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" + U1 J3 + RP12 1 +Net 310 "/FPGA Spartan6/R_M0_A4" "R_M0_A4" + RP17 4 + U1 F3 +Net 326 "/FPGA Spartan6/R_M0_A3" "R_M0_A3" + RP14 4 + U1 K6 +Net 332 "/FPGA Spartan6/R_M0_A2" "R_M0_A2" + U1 H5 + RP14 3 +Net 339 "/FPGA Spartan6/R_M0_A11" "R_M0_A11" + RP18 2 + U1 C1 +Net 363 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" + RP10 3 + U1 V2 +Net 364 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" + RP12 3 + U1 K2 +Net 370 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" + U1 R1 + RP11 4 +Net 371 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" + RP11 2 + U1 P1 +Net 372 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" + RP13 2 + U1 N1 +Net 373 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" + U1 M1 + RP13 4 +Net 375 "/FPGA Spartan6/R_M0_A1" "R_M0_A1" + RP14 2 + U1 H1 +Net 376 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1" + RP15 3 + U1 G1 +Net 378 "/FPGA Spartan6/R_M0_A9" "R_M0_A9" + U1 E1 + RP18 3 +Net 379 "/FPGA Spartan6/R_M0_CAS#" "R_M0_CAS#" + U1 K4 + RP16 4 +Net 380 "/FPGA Spartan6/R_M0_WE#" "R_M0_WE#" + RP16 3 + U1 F2 +Net 381 "/FPGA Spartan6/R_M0_LDM" "R_M0_LDM" + U1 L4 + RP16 2 +Net 382 "/FPGA Spartan6/R_M0_LDQS" "R_M0_LDQS" + U1 L3 + RP16 1 +Net 383 "/FPGA Spartan6/R_M0_RAS#" "R_M0_RAS#" + RP15 1 + U1 K5 +Net 384 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" + R17 1 + U1 D21 +Net 385 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" + RP3 1 + U1 L20 Net 386 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" U1 L19 RP3 2 -Net 387 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" - U1 L20 - RP3 1 -Net 388 "/FPGA Spartan6/R_M0_CKE" "R_M0_CKE" - U1 D2 - R24 1 -Net 389 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS" +Net 387 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" + U1 H19 + RP3 3 +Net 388 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" + R19 1 + U1 T21 +Net 389 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" + U1 M20 + R18 1 +Net 390 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS" U1 T2 R22 1 -Net 390 "/FPGA Spartan6/R_M0_LDM" "R_M0_LDM" - RP16 2 - U1 L4 -Net 391 "/FPGA Spartan6/R_M0_WE#" "R_M0_WE#" - U1 F2 - RP16 3 -Net 392 "/FPGA Spartan6/R_M0_CAS#" "R_M0_CAS#" - RP16 4 - U1 K4 -Net 393 "/FPGA Spartan6/R_M0_RAS#" "R_M0_RAS#" - U1 K5 - RP15 1 -Net 394 "/FPGA Spartan6/R_M0_UDM" "R_M0_UDM" - R23 1 +Net 391 "/FPGA Spartan6/R_M0_CKE" "R_M0_CKE" + U1 D2 + R24 1 +Net 392 "/FPGA Spartan6/R_M0_UDM" "R_M0_UDM" U1 M3 -Net 395 "" "" + R23 1 +Net 393 "" "" R7 1 J4 10 -Net 396 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - U4 26 - R7 2 -Net 397 "" "" +Net 394 "" "" + J4 12 + R8 1 +Net 395 "" "" U4 37 R2 1 -Net 398 "" "" - R8 1 - J4 12 -Net 399 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - U4 27 - R8 2 -Net 405 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" +Net 396 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + U4 38 C7 1 C8 1 L2 2 - U4 38 -Net 406 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD" - C12 1 - R9 1 - J4 14 - J4 13 -Net 407 "/Ethernet Phy/MAG_TX+" "MAG_TX+" - J4 1 - U4 41 - R3 2 -Net 408 "/Ethernet Phy/MAG_RX+" "MAG_RX+" - U4 33 - R5 2 - J4 7 -Net 409 "/Ethernet Phy/MAG_RX-" "MAG_RX-" - U4 32 - R6 2 - J4 8 -Net 410 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - C9 1 - L3 2 - U4 47 -Net 411 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - U4 31 - L3 1 - C6 1 - L1 2 -Net 412 "+1.8V" "+1.8V" - C4 1 - U4 13 - C2 1 - L1 1 -Net 415 "/Ethernet Phy/MAG_TX-" "MAG_TX-" +Net 397 "/Ethernet Phy/ETH_LED1" "ETH_LED1" + R8 2 + U4 27 +Net 398 "/Ethernet Phy/MAG_TX-" "MAG_TX-" J4 2 R4 2 U4 40 -Net 422 "" "" - F2 1 - L6 1 -Net 424 "" "" - J5 S1 - J5 S4 +Net 399 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD" + R9 1 + C12 1 + J4 13 + J4 14 +Net 400 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + C9 1 + U4 47 + L3 2 +Net 401 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + L1 2 + C6 1 + L3 1 + U4 31 +Net 402 "+1.8V" "+1.8V" + L1 1 + U4 13 + C4 1 + C2 1 +Net 405 "/Ethernet Phy/MAG_RX+" "MAG_RX+" + R5 2 + U4 33 + J4 7 +Net 406 "/Ethernet Phy/MAG_TX+" "MAG_TX+" + J4 1 + U4 41 + R3 2 +Net 407 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + U4 26 + R7 2 +Net 408 "/Ethernet Phy/MAG_RX-" "MAG_RX-" + J4 8 + R6 2 + U4 32 +Net 414 "" "" + J5 S3 C16 1 R10 1 - J5 S3 + J5 S4 J5 S2 -Net 425 "" "" + J5 S1 +Net 415 "" "" L5 1 J5 4 -Net 426 "" "" - J5 2 +Net 416 "" "" + V2 1 + V2 1 U6 10 - V2 1 - V2 1 -Net 427 "" "" - L4 2 - J5 1 -Net 428 "+5V" "+5V" + J5 2 +Net 424 "+5V" "+5V" F2 2 F1 2 -Net 429 "" "" +Net 425 "" "" + L6 1 + F2 1 +Net 426 "" "" + L4 2 + J5 1 +Net 427 "" "" L4 1 F1 1 -Net 430 "" "" - U6 11 - V1 1 - V1 1 +Net 428 "" "" J5 3 -Net 431 "" "" + V1 1 + V1 1 + U6 11 +Net 429 "" "" + V4 1 + V4 1 U7 10 - V4 1 - V4 1 -Net 432 "" "" +Net 430 "" "" + V3 1 V3 1 U7 11 - V3 1 -Net 433 "" "" +Net 431 "" "" R15 1 C38 1 -Net 434 "" "" - U12 4 +Net 432 "" "" C82 1 + U12 4 U12 1 -Net 435 "" "" +Net 433 "" "" C83 2 + R28 2 R27 1 U12 5 - R28 2 -Net 436 "" "" +Net 434 "" "" C78 1 U11 1 U11 4 -Net 437 "" "" +Net 435 "" "" + U11 5 R26 2 R25 1 C79 2 - U11 5 -Net 447 "" "" - U11 3 +Net 445 "" "" L8 2 -Net 466 "" "" + U11 3 +Net 464 "" "" U12 3 L9 2 -Net 467 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" - U8 7 +Net 477 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" U1 U13 -Net 468 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" - U1 U14 + U8 7 +Net 478 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" U8 3 -Net 469 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" + U1 U14 +Net 479 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" U1 AA20 U8 2 -Net 470 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" +Net 480 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" U1 AB20 U8 5 -Net 471 "/FPGA Spartan6/NF_D7" "NF_D7" - U1 D11 +Net 481 "/Non volatile memories/NF_D7" "NF_D7" U5 44 -Net 472 "/FPGA Spartan6/NF_D6" "NF_D6" - U5 43 + U1 D11 +Net 482 "/FPGA Spartan6/NF_D6" "NF_D6" U1 A11 -Net 473 "/Non volatile memories/NF_D5" "NF_D5" + U5 43 +Net 483 "/Non volatile memories/NF_D5" "NF_D5" U1 C11 U5 42 -Net 474 "/FPGA Spartan6/NF_D4" "NF_D4" +Net 484 "/FPGA Spartan6/NF_D4" "NF_D4" U5 41 U1 A12 -Net 475 "/Non volatile memories/NF_D3" "NF_D3" +Net 485 "/FPGA Spartan6/NF_D3" "NF_D3" U1 B12 U5 32 -Net 476 "/FPGA Spartan6/NF_D2" "NF_D2" +Net 486 "/FPGA Spartan6/NF_D2" "NF_D2" U1 A13 U5 31 -Net 477 "/Non volatile memories/NF_D1" "NF_D1" +Net 487 "/Non volatile memories/NF_D1" "NF_D1" U5 30 U1 D14 -Net 478 "/Non volatile memories/NF_D0" "NF_D0" - U1 C12 +Net 488 "/FPGA Spartan6/NF_D0" "NF_D0" U5 29 -Net 479 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" - U4 20 + U1 C12 +Net 489 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" U1 A8 -Net 480 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" - U1 C10 + U4 20 +Net 490 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" U4 19 -Net 481 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" - U4 18 + U1 C10 +Net 491 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" U1 C9 -Net 482 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" + U4 18 +Net 492 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" U4 17 U1 D10 -Net 483 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" +Net 493 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" U4 3 U1 C5 -Net 484 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" - U4 4 +Net 494 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" U1 C6 -Net 485 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" - U4 5 + U4 4 +Net 495 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" U1 A5 -Net 486 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" - U1 B6 + U4 5 +Net 496 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" U4 6 -Net 487 "/FPGA Spartan6/M0_BA1" "M0_BA1" + U1 B6 +Net 497 "/FPGA Spartan6/M0_BA1" "M0_BA1" U2 27 RP15 6 -Net 488 "/DDR Banks/M0_BA0" "M0_BA0" +Net 498 "/FPGA Spartan6/M0_BA0" "M0_BA0" U2 26 RP15 7 -Net 489 "/FPGA Spartan6/M1_BA1" "M1_BA1" +Net 499 "/DDR Banks/M1_BA1" "M1_BA1" U3 27 RP2 6 -Net 490 "/DDR Banks/M1_BA0" "M1_BA0" - RP2 7 +Net 500 "/FPGA Spartan6/M1_BA0" "M1_BA0" U3 26 -Net 491 "/DDR Banks/M1_DQ15" "M1_DQ15" - U3 65 + RP2 7 +Net 501 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" RP8 8 -Net 492 "/DDR Banks/M1_DQ14" "M1_DQ14" - RP8 7 + U3 65 +Net 502 "/DDR Banks/M1_DQ14" "M1_DQ14" U3 63 -Net 493 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" + RP8 7 +Net 503 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" U3 62 RP8 6 -Net 494 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" +Net 504 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" RP8 5 U3 60 -Net 495 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" - RP9 8 +Net 505 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" U3 59 -Net 496 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" - RP9 7 + RP9 8 +Net 506 "/DDR Banks/M1_DQ10" "M1_DQ10" U3 57 -Net 497 "/Non volatile memories/SD_DAT3" "SD_DAT3" - U1 C17 - J1 2 -Net 498 "/Non volatile memories/SD_DAT2" "SD_DAT2" - J1 1 - U1 A17 -Net 499 "/Non volatile memories/SD_DAT1" "SD_DAT1" - J1 8 - U1 B18 -Net 500 "/FPGA Spartan6/SD_DAT0" "SD_DAT0" - U1 A18 - J1 7 -Net 501 "/DDR Banks/M1_A7" "M1_A7" - U3 38 - RP6 8 -Net 502 "/DDR Banks/M1_A6" "M1_A6" - U3 37 - RP6 7 -Net 503 "/DDR Banks/M1_A5" "M1_A5" - U3 36 - RP6 6 -Net 504 "/DDR Banks/M1_A4" "M1_A4" - U3 35 - RP6 5 -Net 505 "/FPGA Spartan6/M1_A3" "M1_A3" - U3 32 - RP1 5 -Net 506 "/DDR Banks/M1_A2" "M1_A2" - U3 31 - RP1 6 -Net 507 "/FPGA Spartan6/M1_A1" "M1_A1" - RP1 7 - U3 30 -Net 508 "/DDR Banks/M1_A0" "M1_A0" - U3 29 - RP1 8 -Net 509 "/FPGA Spartan6/M0_A12" "M0_A12" - U2 42 - RP18 8 -Net 510 "/FPGA Spartan6/M0_A11" "M0_A11" - RP18 7 - U2 41 -Net 511 "/FPGA Spartan6/M0_A10" "M0_A10" - U2 28 - RP15 5 -Net 512 "/FPGA Spartan6/M0_A9" "M0_A9" - U2 40 - RP18 6 -Net 513 "/DDR Banks/M0_A8" "M0_A8" - U2 39 - RP18 5 -Net 514 "/FPGA Spartan6/M0_A7" "M0_A7" - U2 38 - RP17 8 -Net 515 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" + RP9 7 +Net 507 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" RP9 6 U3 56 -Net 516 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" +Net 508 "/DDR Banks/M1_DQ8" "M1_DQ8" RP9 5 U3 54 -Net 517 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" +Net 509 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" + J1 2 + U1 C17 +Net 510 "/Non volatile memories/SD_DAT2" "SD_DAT2" + U1 A17 + J1 1 +Net 511 "/FPGA Spartan6/SD_DAT1" "SD_DAT1" + J1 8 + U1 B18 +Net 512 "/Non volatile memories/SD_DAT0" "SD_DAT0" + U1 A18 + J1 7 +Net 513 "/DDR Banks/M1_A6" "M1_A6" + U3 37 + RP6 7 +Net 514 "/DDR Banks/M1_A5" "M1_A5" + U3 36 + RP6 6 +Net 515 "/FPGA Spartan6/M1_A4" "M1_A4" + U3 35 + RP6 5 +Net 516 "/FPGA Spartan6/M1_A3" "M1_A3" + RP1 5 + U3 32 +Net 517 "/FPGA Spartan6/M1_A2" "M1_A2" + U3 31 + RP1 6 +Net 518 "/FPGA Spartan6/M1_A1" "M1_A1" + RP1 7 + U3 30 +Net 519 "/FPGA Spartan6/M1_A0" "M1_A0" + U3 29 + RP1 8 +Net 520 "/FPGA Spartan6/M0_A12" "M0_A12" + RP18 8 + U2 42 +Net 521 "/FPGA Spartan6/M0_A11" "M0_A11" + RP18 7 + U2 41 +Net 522 "/FPGA Spartan6/M0_A10" "M0_A10" + RP15 5 + U2 28 +Net 523 "/FPGA Spartan6/M0_A9" "M0_A9" + RP18 6 + U2 40 +Net 524 "/FPGA Spartan6/M0_A8" "M0_A8" + RP18 5 + U2 39 +Net 525 "/DDR Banks/M0_A7" "M0_A7" + U2 38 + RP17 8 +Net 526 "/FPGA Spartan6/M0_A6" "M0_A6" + U2 37 + RP17 7 +Net 527 "/DDR Banks/M1_DQ7" "M1_DQ7" RP4 5 U3 13 -Net 518 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" +Net 528 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" U3 11 RP4 6 -Net 519 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" - U3 10 +Net 529 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" RP4 7 -Net 520 "/DDR Banks/M1_DQ4" "M1_DQ4" + U3 10 +Net 530 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" U3 8 RP4 8 -Net 521 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" - RP5 5 +Net 531 "/DDR Banks/M1_DQ3" "M1_DQ3" U3 7 -Net 522 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" - U3 5 + RP5 5 +Net 532 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" RP5 6 -Net 523 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" + U3 5 +Net 533 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" U3 4 RP5 7 -Net 524 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" - U3 2 +Net 534 "/DDR Banks/M1_DQ0" "M1_DQ0" RP5 8 -Net 525 "/FPGA Spartan6/M1_A12" "M1_A12" + U3 2 +Net 535 "/DDR Banks/M1_A12" "M1_A12" RP7 8 U3 42 -Net 526 "/DDR Banks/M1_A11" "M1_A11" - U3 41 +Net 536 "/DDR Banks/M1_A11" "M1_A11" RP7 7 -Net 527 "/FPGA Spartan6/M1_A10" "M1_A10" + U3 41 +Net 537 "/DDR Banks/M1_A10" "M1_A10" RP2 5 U3 28 -Net 528 "/FPGA Spartan6/M1_A9" "M1_A9" +Net 538 "/DDR Banks/M1_A9" "M1_A9" RP7 6 U3 40 -Net 529 "/DDR Banks/M1_A8" "M1_A8" +Net 539 "/DDR Banks/M1_A8" "M1_A8" U3 39 RP7 5 -Net 530 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" - U2 7 - RP13 5 -Net 531 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" - RP13 6 - U2 5 -Net 532 "/DDR Banks/M0_DQ1" "M0_DQ1" - RP13 7 +Net 540 "/FPGA Spartan6/M1_A7" "M1_A7" + U3 38 + RP6 8 +Net 541 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" U2 4 -Net 533 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" - U2 2 + RP13 7 +Net 542 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" RP13 8 -Net 534 "/DDR Banks/M0_A6" "M0_A6" - RP17 7 - U2 37 -Net 535 "/FPGA Spartan6/M0_A5" "M0_A5" - U2 36 + U2 2 +Net 543 "/FPGA Spartan6/M0_A5" "M0_A5" RP17 6 -Net 536 "/FPGA Spartan6/M0_A4" "M0_A4" + U2 36 +Net 544 "/DDR Banks/M0_A4" "M0_A4" RP17 5 U2 35 -Net 537 "/FPGA Spartan6/M0_A3" "M0_A3" - U2 32 +Net 545 "/DDR Banks/M0_A3" "M0_A3" RP14 5 -Net 538 "/FPGA Spartan6/M0_A2" "M0_A2" + U2 32 +Net 546 "/DDR Banks/M0_A2" "M0_A2" RP14 6 U2 31 -Net 539 "/DDR Banks/M0_A1" "M0_A1" +Net 547 "/FPGA Spartan6/M0_A1" "M0_A1" RP14 7 U2 30 -Net 540 "/FPGA Spartan6/M0_A0" "M0_A0" +Net 548 "/DDR Banks/M0_A0" "M0_A0" U2 29 RP14 8 -Net 541 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" - U2 65 +Net 549 "/DDR Banks/M0_DQ15" "M0_DQ15" RP10 5 -Net 542 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" + U2 65 +Net 550 "/DDR Banks/M0_DQ14" "M0_DQ14" RP10 6 U2 63 -Net 543 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" +Net 551 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" U2 62 RP10 7 -Net 544 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" - RP10 8 +Net 552 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" U2 60 -Net 545 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" + RP10 8 +Net 553 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" RP11 5 U2 59 -Net 546 "/DDR Banks/M0_DQ10" "M0_DQ10" +Net 554 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" U2 57 RP11 6 -Net 547 "/DDR Banks/M0_DQ9" "M0_DQ9" +Net 555 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" U2 56 RP11 7 -Net 548 "/DDR Banks/M0_DQ8" "M0_DQ8" +Net 556 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" U2 54 RP11 8 -Net 549 "/DDR Banks/M0_DQ7" "M0_DQ7" - U2 13 +Net 557 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" RP12 5 -Net 550 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" + U2 13 +Net 558 "/DDR Banks/M0_DQ6" "M0_DQ6" RP12 6 U2 11 -Net 551 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" - RP12 7 +Net 559 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" U2 10 -Net 552 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" - RP12 8 + RP12 7 +Net 560 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" U2 8 + RP12 8 +Net 561 "/DDR Banks/M0_DQ3" "M0_DQ3" + U2 7 + RP13 5 +Net 562 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" + RP13 6 + U2 5 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index a8066bb..a8b8ac2 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Sun 22 Aug 2010 08:23:05 AM COT +update=Sun 22 Aug 2010 01:34:33 PM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index d3a8a55..0d41219 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:19:33 AM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 01:33:25 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,7 +49,7 @@ LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 -Sheet 1 7 +Sheet 1 8 Title "" Date "22 aug 2010" Rev "" @@ -59,12 +59,10 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -$Sheet -S 3650 7300 1100 1300 -U 4C69ED5F -F0 "PSU" 60 -F1 "PSU.sch" 60 -$EndSheet +Wire Wire Line + 5950 8150 4950 8150 +Wire Wire Line + 5950 7950 4950 7950 Wire Wire Line 10650 4400 9300 4400 Wire Wire Line @@ -189,6 +187,26 @@ Wire Wire Line 10650 3450 9300 3450 Wire Bus Line 10650 4500 9300 4500 +Wire Wire Line + 5950 7850 4950 7850 +Wire Wire Line + 4950 8050 5950 8050 +$Sheet +S 3750 7800 1200 700 +U 4C716A4D +F0 "DBG_PRG" 60 +F1 "DBG_PRG.sch" 60 +F2 "FPGA_TDO" B R 4950 8050 60 +F3 "FPGA_TDI" B R 4950 7950 60 +F4 "FPGA_TMS" B R 4950 8150 60 +F5 "FPGA_TCK" B R 4950 7850 60 +$EndSheet +$Sheet +S 10750 8650 1100 1300 +U 4C69ED5F +F0 "PSU" 60 +F1 "PSU.sch" 60 +$EndSheet $Sheet S 10650 2700 1050 1950 U 4C4227FE @@ -287,6 +305,10 @@ F59 "NF_RNB" B R 9300 3950 60 F60 "PROG_CCLK" O R 9300 4400 60 F61 "PROG_CSO" O R 9300 4300 60 F62 "PROG_MISO[0..3]" B R 9300 4500 60 +F63 "S6_TCK" I L 5950 7850 60 +F64 "S6_TDI" I L 5950 7950 60 +F65 "S6_TDO" O L 5950 8050 60 +F66 "S6_TMS" I L 5950 8150 60 $EndSheet $Sheet S 10600 6250 1300 1800