From a8fcbf091cbd19965d50c6faafe2e16d07d17870 Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Mon, 9 Aug 2010 22:25:05 -0500 Subject: [PATCH] early placement --- kicad/xue-rnc/DRAM.sch | 2 +- kicad/xue-rnc/FPGA.sch | 1806 +++++++++++----------- kicad/xue-rnc/NV_MEMORIES.sch | 2 +- kicad/xue-rnc/USB.sch | 2 +- kicad/xue-rnc/eth_phy.sch | 2 +- kicad/xue-rnc/xue-rnc-cache.lib | 2 +- kicad/xue-rnc/xue-rnc.brd | 1122 +++++++------- kicad/xue-rnc/xue-rnc.net | 2492 +++++++++++++++++++------------ kicad/xue-rnc/xue-rnc.pro | 2 +- kicad/xue-rnc/xue-rnc.sch | 2 +- 10 files changed, 3061 insertions(+), 2373 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index a8f5939..9292acd 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 84b90e3..e7618a7 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -54,924 +54,950 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Text HLabel 12400 5450 0 60 Output ~ 0 +M1_CS# +$Comp +L GND #PWR? +U 1 1 4C60C24F +P 12550 5700 +F 0 "#PWR?" H 12550 5700 30 0001 C CNN +F 1 "GND" H 12550 5630 30 0001 C CNN + 1 12550 5700 + -1 0 0 -1 +$EndComp Wire Wire Line - 16350 11000 16400 11000 + 12550 5450 12550 5700 Wire Wire Line - 16350 10800 16400 10800 + 12400 5450 12550 5450 Wire Wire Line - 16400 10600 15100 10600 + 1450 5700 1600 5700 Wire Wire Line - 16400 10400 15100 10400 + 14150 10650 14200 10650 Wire Wire Line - 16350 10200 16400 10200 + 14200 10450 12900 10450 Wire Wire Line - 16350 10000 16400 10000 + 14200 10250 12900 10250 Wire Wire Line - 16400 9800 15100 9800 + 14150 10050 14200 10050 Wire Wire Line - 16400 9600 15100 9600 + 14150 9850 14200 9850 Wire Wire Line - 16350 9400 16400 9400 + 14200 9650 12900 9650 Wire Wire Line - 16350 9200 16400 9200 + 14200 9450 12900 9450 Wire Wire Line - 19800 9300 19900 9300 + 14150 9250 14200 9250 Wire Wire Line - 19800 9100 19900 9100 + 14150 9050 14200 9050 +Wire Wire Line + 17600 9150 17700 9150 +Wire Wire Line + 17600 8950 17700 8950 +Wire Wire Line + 17700 8750 17600 8750 Wire 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CNN - 1 13450 15700 - 1 0 0 -1 +P 13950 15700 +F 0 "#PWR01" H 13950 15700 30 0001 C CNN +F 1 "GND" H 13950 15630 30 0001 C CNN + 1 13950 15700 + -1 0 0 -1 $EndComp $Comp L XC6SLX45FGG484 U1 @@ -1300,10 +1324,10 @@ $EndComp $Comp L XC6SLX45FGG484 U1 U 4 1 4C431E48 -P 7600 9250 -F 0 "U1" H 7600 9350 70 0000 C CNN -F 1 "XC6SLX45FGG484" H 7600 9150 70 0000 C CNN - 4 7600 9250 +P 5350 9850 +F 0 "U1" H 5350 9950 70 0000 C CNN +F 1 "XC6SLX45FGG484" H 5350 9750 70 0000 C CNN + 4 5350 9850 1 0 0 -1 $EndComp $Comp @@ -1318,19 +1342,19 @@ $EndComp $Comp L XC6SLX45FGG484 U1 U 1 1 4C431E37 -P 18150 3650 -F 0 "U1" H 18150 3750 70 0000 C CNN -F 1 "XC6SLX45FGG484" H 18150 3550 70 0000 C CNN - 1 18150 3650 +P 16100 3750 +F 0 "U1" H 16100 3850 70 0000 C CNN +F 1 "XC6SLX45FGG484" H 16100 3650 70 0000 C CNN + 1 16100 3750 1 0 0 -1 $EndComp $Comp L XC6SLX45FGG484 U1 U 2 1 4C431E29 -P 18100 10100 -F 0 "U1" H 18100 10200 70 0000 C CNN -F 1 "XC6SLX45FGG484" H 18100 10000 70 0000 C CNN - 2 18100 10100 +P 15900 9850 +F 0 "U1" H 15900 9950 70 0000 C CNN +F 1 "XC6SLX45FGG484" H 15900 9750 70 0000 C CNN + 2 15900 9850 1 0 0 -1 $EndComp $EndSCHEMATC diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 6c684e1..418303d 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 906ebbd..67b040e 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 734ed1b..003222f 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index b82181b..07d3966 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Mon 09 Aug 2010 09:53:48 PM COT +EESchema-LIBRARY Version 2.3 Date: Mon 09 Aug 2010 10:11:04 PM COT # # C # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index b740fa3..198e8cc 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Mon 09 Aug 2010 09:50:49 PM COT +PCBNEW-BOARD Version 1 date Mon 09 Aug 2010 10:24:02 PM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -6,15 +6,15 @@ $GENERAL LayerCount 4 Ly 1FFF8007 EnabledLayers 1FFF8007 -Links 329 -NoConn 329 -Di -1231 -600 66209 48914 +Links 337 +NoConn 337 +Di 25909 11079 66209 48965 Ndraw 0 Ntrack 0 Nzone 0 BoardThickness 630 -Nmodule 39 -Nnets 108 +Nmodule 41 +Nnets 109 $EndGENERAL $SHEETDESCR @@ -68,339 +68,339 @@ Na 0 "" St ~ $EndEQUIPOT $EQUIPOT -Na 1 "/DDR_Ban11" +Na 1 "/DDR_Banks/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 2 "/DDR_Ban15" +Na 2 "/DDR_Banks/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 3 "/DDR_Ban16" +Na 3 "/DDR_Banks/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 4 "/DDR_Ban22" +Na 4 "/DDR_Banks/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/DDR_Ban23" +Na 5 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Ban25" +Na 6 "/DDR_Banks/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Ban26" +Na 7 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Ban30" +Na 8 "/DDR_Banks/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Ban34" +Na 9 "/DDR_Banks/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Ban35" +Na 10 "/DDR_Banks/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Ban42" +Na 11 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Ban44" +Na 12 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Ban45" +Na 13 "/DDR_Banks/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Ban46" +Na 14 "/DDR_Banks/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Ban49" +Na 15 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Ban51" +Na 16 "/DDR_Banks/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Ban64" +Na 17 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Ban68" +Na 18 "/DDR_Banks/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Ban71" +Na 19 "/DDR_Banks/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M0_A0" +Na 20 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M0_A4" +Na 21 "/DDR_Banks/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M0_A7" +Na 22 "/DDR_Banks/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M0_A8" +Na 23 "/DDR_Banks/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_A0" +Na 24 "/DDR_Banks/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_A1" +Na 25 "/DDR_Banks/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_A2" +Na 26 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_A5" +Na 27 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_A6" +Na 28 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_A7" +Na 29 "/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_A9" +Na 30 "/Ethernet_Phy/ETH_1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/ETH_MDIO" +Na 31 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/Etherne1" +Na 32 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/Etherne2" +Na 33 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/Etherne3" +Na 34 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/Etherne4" +Na 35 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/Etherne5" +Na 36 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/Etherne6" +Na 37 "/FPGA_Spartan6/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/Etherne7" +Na 38 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/FPGA_Sp10" +Na 39 "/FPGA_Spartan6/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/FPGA_Sp12" +Na 40 "/FPGA_Spartan6/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/FPGA_Sp13" +Na 41 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/FPGA_Sp14" +Na 42 "/FPGA_Spartan6/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/FPGA_Sp17" +Na 43 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/FPGA_Sp18" +Na 44 "/FPGA_Spartan6/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/FPGA_Sp19" +Na 45 "/FPGA_Spartan6/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/FPGA_Sp20" +Na 46 "/FPGA_Spartan6/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/FPGA_Sp21" +Na 47 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/FPGA_Sp24" +Na 48 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/FPGA_Sp27" +Na 49 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/FPGA_Sp28" +Na 50 "/FPGA_Spartan6/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/FPGA_Sp29" +Na 51 "/FPGA_Spartan6/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Sp31" +Na 52 "/FPGA_Spartan6/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Sp32" +Na 53 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Sp33" +Na 54 "/FPGA_Spartan6/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Sp36" +Na 55 "/FPGA_Spartan6/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Sp37" +Na 56 "/FPGA_Spartan6/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Sp38" +Na 57 "/FPGA_Spartan6/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Sp39" +Na 58 "/FPGA_Spartan6/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Sp40" +Na 59 "/FPGA_Spartan6/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Sp41" +Na 60 "/FPGA_Spartan6/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Sp43" +Na 61 "/FPGA_Spartan6/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Sp47" +Na 62 "/FPGA_Spartan6/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Sp48" +Na 63 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Sp50" +Na 64 "/FPGA_Spartan6/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Sp52" +Na 65 "/FPGA_Spartan6/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Sp53" +Na 66 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Sp54" +Na 67 "/FPGA_Spartan6/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Sp55" +Na 68 "/FPGA_Spartan6/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Sp56" +Na 69 "/FPGA_Spartan6/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Sp57" +Na 70 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Sp58" +Na 71 "/FPGA_Spartan6/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Sp59" +Na 72 "/FPGA_Spartan6/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Sp60" +Na 73 "/FPGA_Spartan6/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Sp61" +Na 74 "/FPGA_Spartan6/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Sp62" +Na 75 "/FPGA_Spartan6/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Sp63" +Na 76 "/FPGA_Spartan6/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Sp65" +Na 77 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Sp66" +Na 78 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Sp67" +Na 79 "/FPGA_Spartan6/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Sp69" +Na 80 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Sp70" +Na 81 "/FPGA_Spartan6/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Sp8" +Na 82 "/FPGA_Spartan6/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Sp9" +Na 83 "/FPGA_Spartan6/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/Non_vol72" +Na 84 "/Non_volatile_memories/FRB_N" St ~ $EndEQUIPOT $EQUIPOT @@ -412,15 +412,15 @@ Na 86 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "N-000048" +Na 87 "N-000047" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "N-000056" +Na 88 "N-000054" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "N-000152" +Na 89 "N-000137" St ~ $EndEQUIPOT $EQUIPOT @@ -432,15 +432,15 @@ Na 91 "N-000154" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "N-000158" +Na 92 "N-000155" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "N-000159" +Na 93 "N-000156" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "N-000160" +Na 94 "N-000157" St ~ $EndEQUIPOT $EQUIPOT @@ -460,19 +460,19 @@ Na 98 "N-000400" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "N-000402" +Na 99 "N-000405" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "N-000404" +Na 100 "N-000406" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "N-000405" +Na 101 "N-000407" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "N-000406" +Na 102 "N-000408" St ~ $EndEQUIPOT $EQUIPOT @@ -484,15 +484,19 @@ Na 104 "N-000417" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "N-000420" +Na 105 "N-000419" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "N-000426" +Na 106 "N-000420" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "N-000428" +Na 107 "N-000425" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 108 "N-000426" St ~ $EndEQUIPOT $NCLASS @@ -505,113 +509,114 @@ ViaDrill 250 uViaDia 200 uViaDrill 50 AddNet "" -AddNet "/DDR_Ban11" -AddNet "/DDR_Ban15" -AddNet "/DDR_Ban16" -AddNet "/DDR_Ban22" -AddNet "/DDR_Ban23" -AddNet "/DDR_Ban25" -AddNet "/DDR_Ban26" -AddNet "/DDR_Ban30" -AddNet "/DDR_Ban34" -AddNet "/DDR_Ban35" -AddNet "/DDR_Ban42" -AddNet "/DDR_Ban44" -AddNet "/DDR_Ban45" -AddNet "/DDR_Ban46" -AddNet "/DDR_Ban49" -AddNet "/DDR_Ban51" -AddNet "/DDR_Ban64" -AddNet "/DDR_Ban68" -AddNet "/DDR_Ban71" -AddNet "/DDR_Banks/M0_A0" -AddNet "/DDR_Banks/M0_A4" +AddNet "/DDR_Banks/M0_A1" +AddNet "/DDR_Banks/M0_A10" +AddNet "/DDR_Banks/M0_A12" +AddNet "/DDR_Banks/M0_A6" AddNet "/DDR_Banks/M0_A7" -AddNet "/DDR_Banks/M0_A8" -AddNet "/DDR_Banks/M1_A0" -AddNet "/DDR_Banks/M1_A1" -AddNet "/DDR_Banks/M1_A2" +AddNet "/DDR_Banks/M0_CAS#" +AddNet "/DDR_Banks/M0_CLK#" +AddNet "/DDR_Banks/M0_DQ10" +AddNet "/DDR_Banks/M0_DQ3" +AddNet "/DDR_Banks/M0_DQ8" +AddNet "/DDR_Banks/M0_LDM" +AddNet "/DDR_Banks/M0_LDQS" +AddNet "/DDR_Banks/M0_RAS#" +AddNet "/DDR_Banks/M0_UDQS" +AddNet "/DDR_Banks/M1_A12" +AddNet "/DDR_Banks/M1_A3" AddNet "/DDR_Banks/M1_A5" AddNet "/DDR_Banks/M1_A6" AddNet "/DDR_Banks/M1_A7" -AddNet "/DDR_Banks/M1_A9" +AddNet "/DDR_Banks/M1_DQ10" +AddNet "/DDR_Banks/M1_DQ11" +AddNet "/DDR_Banks/M1_DQ14" +AddNet "/DDR_Banks/M1_DQ15" +AddNet "/DDR_Banks/M1_DQ5" +AddNet "/DDR_Banks/M1_DQ8" +AddNet "/DDR_Banks/M1_LDQS" +AddNet "/DDR_Banks/M1_UDM" +AddNet "/DDR_Banks/M1_WE#" AddNet "/ETH_MDIO" -AddNet "/Etherne1" -AddNet "/Etherne2" -AddNet "/Etherne3" -AddNet "/Etherne4" -AddNet "/Etherne5" -AddNet "/Etherne6" -AddNet "/Etherne7" -AddNet "/FPGA_Sp10" -AddNet "/FPGA_Sp12" -AddNet "/FPGA_Sp13" -AddNet "/FPGA_Sp14" -AddNet "/FPGA_Sp17" -AddNet "/FPGA_Sp18" -AddNet "/FPGA_Sp19" -AddNet "/FPGA_Sp20" -AddNet "/FPGA_Sp21" -AddNet "/FPGA_Sp24" -AddNet "/FPGA_Sp27" -AddNet "/FPGA_Sp28" -AddNet "/FPGA_Sp29" -AddNet "/FPGA_Sp31" -AddNet "/FPGA_Sp32" -AddNet "/FPGA_Sp33" -AddNet "/FPGA_Sp36" -AddNet "/FPGA_Sp37" -AddNet "/FPGA_Sp38" -AddNet "/FPGA_Sp39" -AddNet "/FPGA_Sp40" -AddNet "/FPGA_Sp41" -AddNet "/FPGA_Sp43" -AddNet "/FPGA_Sp47" -AddNet "/FPGA_Sp48" -AddNet "/FPGA_Sp50" -AddNet "/FPGA_Sp52" -AddNet "/FPGA_Sp53" -AddNet "/FPGA_Sp54" -AddNet "/FPGA_Sp55" -AddNet "/FPGA_Sp56" -AddNet "/FPGA_Sp57" -AddNet "/FPGA_Sp58" -AddNet "/FPGA_Sp59" -AddNet "/FPGA_Sp60" -AddNet "/FPGA_Sp61" -AddNet "/FPGA_Sp62" -AddNet "/FPGA_Sp63" -AddNet "/FPGA_Sp65" -AddNet "/FPGA_Sp66" -AddNet "/FPGA_Sp67" -AddNet "/FPGA_Sp69" -AddNet "/FPGA_Sp70" -AddNet "/FPGA_Sp8" -AddNet "/FPGA_Sp9" -AddNet "/Non_vol72" +AddNet "/Ethernet_Phy/ETH_1.8V" +AddNet "/Ethernet_Phy/ETH_A1.8V" +AddNet "/Ethernet_Phy/ETH_A3.3V" +AddNet "/Ethernet_Phy/ETH_INT" +AddNet "/Ethernet_Phy/ETH_LED0" +AddNet "/Ethernet_Phy/ETH_LED1" +AddNet "/Ethernet_Phy/ETH_PLL1.8V" +AddNet "/FPGA_Spartan6/M0_A0" +AddNet "/FPGA_Spartan6/M0_A11" +AddNet "/FPGA_Spartan6/M0_A2" +AddNet "/FPGA_Spartan6/M0_A3" +AddNet "/FPGA_Spartan6/M0_A4" +AddNet "/FPGA_Spartan6/M0_A5" +AddNet "/FPGA_Spartan6/M0_A8" +AddNet "/FPGA_Spartan6/M0_A9" +AddNet "/FPGA_Spartan6/M0_CKE" +AddNet "/FPGA_Spartan6/M0_CLK" +AddNet "/FPGA_Spartan6/M0_DQ0" +AddNet "/FPGA_Spartan6/M0_DQ1" +AddNet "/FPGA_Spartan6/M0_DQ11" +AddNet "/FPGA_Spartan6/M0_DQ12" +AddNet "/FPGA_Spartan6/M0_DQ13" +AddNet "/FPGA_Spartan6/M0_DQ14" +AddNet "/FPGA_Spartan6/M0_DQ15" +AddNet "/FPGA_Spartan6/M0_DQ2" +AddNet "/FPGA_Spartan6/M0_DQ4" +AddNet "/FPGA_Spartan6/M0_DQ5" +AddNet "/FPGA_Spartan6/M0_DQ6" +AddNet "/FPGA_Spartan6/M0_DQ7" +AddNet "/FPGA_Spartan6/M0_DQ9" +AddNet "/FPGA_Spartan6/M0_UDM" +AddNet "/FPGA_Spartan6/M0_WE#" +AddNet "/FPGA_Spartan6/M1_A0" +AddNet "/FPGA_Spartan6/M1_A1" +AddNet "/FPGA_Spartan6/M1_A10" +AddNet "/FPGA_Spartan6/M1_A11" +AddNet "/FPGA_Spartan6/M1_A2" +AddNet "/FPGA_Spartan6/M1_A4" +AddNet "/FPGA_Spartan6/M1_A8" +AddNet "/FPGA_Spartan6/M1_A9" +AddNet "/FPGA_Spartan6/M1_CAS#" +AddNet "/FPGA_Spartan6/M1_CKE" +AddNet "/FPGA_Spartan6/M1_CLK" +AddNet "/FPGA_Spartan6/M1_CLK#" +AddNet "/FPGA_Spartan6/M1_DQ0" +AddNet "/FPGA_Spartan6/M1_DQ1" +AddNet "/FPGA_Spartan6/M1_DQ12" +AddNet "/FPGA_Spartan6/M1_DQ13" +AddNet "/FPGA_Spartan6/M1_DQ6" +AddNet "/FPGA_Spartan6/M1_DQ7" +AddNet "/FPGA_Spartan6/M1_DQ9" +AddNet "/FPGA_Spartan6/M1_LDM" +AddNet "/FPGA_Spartan6/M1_RAS#" +AddNet "/FPGA_Spartan6/M1_UDQS" +AddNet "/Non_volatile_memories/FRB_N" AddNet "3.3V" AddNet "GND" -AddNet "N-000048" -AddNet "N-000056" -AddNet "N-000152" +AddNet "N-000047" +AddNet "N-000054" +AddNet "N-000137" AddNet "N-000153" AddNet "N-000154" -AddNet "N-000158" -AddNet "N-000159" -AddNet "N-000160" +AddNet "N-000155" +AddNet "N-000156" +AddNet "N-000157" AddNet "N-000396" AddNet "N-000398" AddNet "N-000399" AddNet "N-000400" -AddNet "N-000402" -AddNet "N-000404" AddNet "N-000405" AddNet "N-000406" +AddNet "N-000407" +AddNet "N-000408" AddNet "N-000416" AddNet "N-000417" +AddNet "N-000419" AddNet "N-000420" +AddNet "N-000425" AddNet "N-000426" -AddNet "N-000428" $EndNCLASS $MODULE FGG484bga-p10 Po 56450 33930 0 15 4C4325AE 4C431E53 ~~ @@ -662,7 +667,7 @@ $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Etherne7" +Ne 33 "/Ethernet_Phy/ETH_INT" Po -2558 -4133 $EndPAD $PAD @@ -809,7 +814,7 @@ $PAD Sh "B4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 89 "N-000137" Po -2952 -3739 $EndPAD $PAD @@ -830,7 +835,7 @@ $PAD Sh "B7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 89 "N-000137" Po -1771 -3739 $EndPAD $PAD @@ -858,7 +863,7 @@ $PAD Sh "B11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 89 "N-000137" Po -196 -3739 $EndPAD $PAD @@ -886,7 +891,7 @@ $PAD Sh "B15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 89 "N-000137" Po 1377 -3739 $EndPAD $PAD @@ -914,7 +919,7 @@ $PAD Sh "B19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 89 "N-000137" Po 2952 -3739 $EndPAD $PAD @@ -942,14 +947,14 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Sp8" +Ne 38 "/FPGA_Spartan6/M0_A11" Po -4133 -3346 $EndPAD $PAD Sh "C2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -3739 -3346 $EndPAD $PAD @@ -1075,35 +1080,35 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Sp9" +Ne 68 "/FPGA_Spartan6/M1_A8" Po 3346 -3346 $EndPAD $PAD Sh "C21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 92 "N-000155" Po 3739 -3346 $EndPAD $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_A9" +Ne 69 "/FPGA_Spartan6/M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/FPGA_Sp10" +Ne 3 "/DDR_Banks/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "/DDR_Ban11" +Ne 45 "/FPGA_Spartan6/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1201,7 +1206,7 @@ $PAD Sh "D16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po 1771 -2952 $EndPAD $PAD @@ -1236,21 +1241,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/FPGA_Sp12" +Ne 71 "/FPGA_Spartan6/M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/FPGA_Sp13" +Ne 15 "/DDR_Banks/M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/FPGA_Sp14" +Ne 44 "/FPGA_Spartan6/M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -1264,7 +1269,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M0_A8" +Ne 43 "/FPGA_Spartan6/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1306,7 +1311,7 @@ $PAD Sh "E9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 89 "N-000137" Po -983 -2558 $EndPAD $PAD @@ -1320,7 +1325,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 0 "" Po -196 -2558 $EndPAD $PAD @@ -1334,7 +1339,7 @@ $PAD Sh "E13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 89 "N-000137" Po 590 -2558 $EndPAD $PAD @@ -1362,7 +1367,7 @@ $PAD Sh "E17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 89 "N-000137" Po 2165 -2558 $EndPAD $PAD @@ -1376,14 +1381,14 @@ $PAD Sh "E19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 92 "N-000155" Po 2952 -2558 $EndPAD $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_A7" +Ne 19 "/DDR_Banks/M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -1397,7 +1402,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_A2" +Ne 66 "/FPGA_Spartan6/M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -1411,21 +1416,21 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/DDR_Ban15" +Ne 61 "/FPGA_Spartan6/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_A4" +Ne 41 "/FPGA_Spartan6/M0_A4" Po -3346 -2165 $EndPAD $PAD Sh "F4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -2952 -2165 $EndPAD $PAD @@ -1439,7 +1444,7 @@ $PAD Sh "F6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -2165 -2165 $EndPAD $PAD @@ -1474,7 +1479,7 @@ $PAD Sh "F11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po -196 -2165 $EndPAD $PAD @@ -1530,28 +1535,28 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/DDR_Ban16" +Ne 65 "/FPGA_Spartan6/M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/FPGA_Sp17" +Ne 67 "/FPGA_Spartan6/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A0" +Ne 62 "/FPGA_Spartan6/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A1" +Ne 63 "/FPGA_Spartan6/M1_A1" Po 4133 -2165 $EndPAD $PAD @@ -1565,7 +1570,7 @@ $PAD Sh "G2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -3739 -1771 $EndPAD $PAD @@ -1579,7 +1584,7 @@ $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/FPGA_Sp18" +Ne 2 "/DDR_Banks/M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -1621,7 +1626,7 @@ $PAD Sh "G10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 89 "N-000137" Po -590 -1771 $EndPAD $PAD @@ -1635,7 +1640,7 @@ $PAD Sh "G12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po 196 -1771 $EndPAD $PAD @@ -1649,7 +1654,7 @@ $PAD Sh "G14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 89 "N-000137" Po 983 -1771 $EndPAD $PAD @@ -1684,21 +1689,21 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/FPGA_Sp19" +Ne 64 "/FPGA_Spartan6/M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/FPGA_Sp20" +Ne 16 "/DDR_Banks/M1_A3" Po 3346 -1771 $EndPAD $PAD Sh "G21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 92 "N-000155" Po 3739 -1771 $EndPAD $PAD @@ -1712,42 +1717,42 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/FPGA_Sp21" +Ne 1 "/DDR_Banks/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_A0" +Ne 37 "/FPGA_Spartan6/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/DDR_Ban22" +Ne 7 "/DDR_Banks/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Ban23" +Ne 46 "/FPGA_Spartan6/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/FPGA_Sp24" +Ne 39 "/FPGA_Spartan6/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_A7" +Ne 5 "/DDR_Banks/M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -1768,7 +1773,7 @@ $PAD Sh "H9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po -983 -1377 $EndPAD $PAD @@ -1810,7 +1815,7 @@ $PAD Sh "H15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po 1377 -1377 $EndPAD $PAD @@ -1838,35 +1843,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Ban25" +Ne 28 "/DDR_Banks/M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Ban26" +Ne 72 "/FPGA_Spartan6/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/FPGA_Sp27" +Ne 82 "/FPGA_Spartan6/M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Sp28" +Ne 70 "/FPGA_Spartan6/M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Sp29" +Ne 56 "/FPGA_Spartan6/M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -1880,21 +1885,21 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Ban30" +Ne 55 "/FPGA_Spartan6/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Sp31" +Ne 4 "/DDR_Banks/M0_A6" Po -2952 -983 $EndPAD $PAD Sh "J5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -2558 -983 $EndPAD $PAD @@ -1915,7 +1920,7 @@ $PAD Sh "J8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po -1377 -983 $EndPAD $PAD @@ -1929,7 +1934,7 @@ $PAD Sh "J10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po -590 -983 $EndPAD $PAD @@ -1943,7 +1948,7 @@ $PAD Sh "J12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po 196 -983 $EndPAD $PAD @@ -1957,7 +1962,7 @@ $PAD Sh "J14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po 983 -983 $EndPAD $PAD @@ -1985,14 +1990,14 @@ $PAD Sh "J18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 92 "N-000155" Po 2558 -983 $EndPAD $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Sp32" +Ne 73 "/FPGA_Spartan6/M1_CLK#" Po 2952 -983 $EndPAD $PAD @@ -2013,49 +2018,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Sp33" +Ne 24 "/DDR_Banks/M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Ban34" +Ne 58 "/FPGA_Spartan6/M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Ban35" +Ne 57 "/FPGA_Spartan6/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Sp36" +Ne 42 "/FPGA_Spartan6/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Sp37" +Ne 6 "/DDR_Banks/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Sp38" +Ne 13 "/DDR_Banks/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Sp39" +Ne 40 "/FPGA_Spartan6/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2076,7 +2081,7 @@ $PAD Sh "K9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po -983 -590 $EndPAD $PAD @@ -2090,21 +2095,21 @@ $PAD Sh "K11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po -196 -590 $EndPAD $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 0 "" Po 196 -590 $EndPAD $PAD Sh "K13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po 590 -590 $EndPAD $PAD @@ -2118,7 +2123,7 @@ $PAD Sh "K15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po 1377 -590 $EndPAD $PAD @@ -2146,28 +2151,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_A6" +Ne 18 "/DDR_Banks/M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_A5" +Ne 17 "/DDR_Banks/M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Sp40" +Ne 78 "/FPGA_Spartan6/M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Sp41" +Ne 79 "/FPGA_Spartan6/M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2181,21 +2186,21 @@ $PAD Sh "L2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -3739 -196 $EndPAD $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Ban42" +Ne 12 "/DDR_Banks/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Sp43" +Ne 11 "/DDR_Banks/M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -2216,14 +2221,14 @@ $PAD Sh "L7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -1771 -196 $EndPAD $PAD Sh "L8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po -1377 -196 $EndPAD $PAD @@ -2237,7 +2242,7 @@ $PAD Sh "L10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po -590 -196 $EndPAD $PAD @@ -2251,7 +2256,7 @@ $PAD Sh "L12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po 196 -196 $EndPAD $PAD @@ -2265,7 +2270,7 @@ $PAD Sh "L14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po 983 -196 $EndPAD $PAD @@ -2279,7 +2284,7 @@ $PAD Sh "L16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 92 "N-000155" Po 1771 -196 $EndPAD $PAD @@ -2300,21 +2305,21 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Ban44" +Ne 81 "/FPGA_Spartan6/M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Ban45" +Ne 26 "/DDR_Banks/M1_LDQS" Po 3346 -196 $EndPAD $PAD Sh "L21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 92 "N-000155" Po 3739 -196 $EndPAD $PAD @@ -2328,21 +2333,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Ban46" +Ne 9 "/DDR_Banks/M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Sp47" +Ne 54 "/FPGA_Spartan6/M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Sp48" +Ne 60 "/FPGA_Spartan6/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2384,7 +2389,7 @@ $PAD Sh "M9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po -983 196 $EndPAD $PAD @@ -2398,7 +2403,7 @@ $PAD Sh "M11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po -196 196 $EndPAD $PAD @@ -2412,7 +2417,7 @@ $PAD Sh "M13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po 590 196 $EndPAD $PAD @@ -2426,7 +2431,7 @@ $PAD Sh "M15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po 1377 196 $EndPAD $PAD @@ -2461,7 +2466,7 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Ban49" +Ne 27 "/DDR_Banks/M1_UDM" Po 3346 196 $EndPAD $PAD @@ -2482,7 +2487,7 @@ $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Sp50" +Ne 48 "/FPGA_Spartan6/M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -2496,7 +2501,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Ban51" +Ne 47 "/FPGA_Spartan6/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -2510,7 +2515,7 @@ $PAD Sh "N5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -2558 590 $EndPAD $PAD @@ -2531,7 +2536,7 @@ $PAD Sh "N8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po -1377 590 $EndPAD $PAD @@ -2545,7 +2550,7 @@ $PAD Sh "N10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po -590 590 $EndPAD $PAD @@ -2559,7 +2564,7 @@ $PAD Sh "N12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po 196 590 $EndPAD $PAD @@ -2573,7 +2578,7 @@ $PAD Sh "N14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po 983 590 $EndPAD $PAD @@ -2601,7 +2606,7 @@ $PAD Sh "N18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 92 "N-000155" Po 2558 590 $EndPAD $PAD @@ -2615,7 +2620,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Sp52" +Ne 74 "/FPGA_Spartan6/M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -2629,21 +2634,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Sp53" +Ne 75 "/FPGA_Spartan6/M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Sp54" +Ne 59 "/FPGA_Spartan6/M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Sp55" +Ne 10 "/DDR_Banks/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -2692,7 +2697,7 @@ $PAD Sh "P9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po -983 983 $EndPAD $PAD @@ -2706,7 +2711,7 @@ $PAD Sh "P11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po -196 983 $EndPAD $PAD @@ -2720,7 +2725,7 @@ $PAD Sh "P13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po 590 983 $EndPAD $PAD @@ -2776,35 +2781,35 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Sp56" +Ne 25 "/DDR_Banks/M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Sp57" +Ne 80 "/FPGA_Spartan6/M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Sp58" +Ne 49 "/FPGA_Spartan6/M0_DQ11" Po -4133 1377 $EndPAD $PAD Sh "R2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -3739 1377 $EndPAD $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Sp59" +Ne 8 "/DDR_Banks/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -2825,7 +2830,7 @@ $PAD Sh "R6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po -2165 1377 $EndPAD $PAD @@ -2853,7 +2858,7 @@ $PAD Sh "R10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po -590 1377 $EndPAD $PAD @@ -2867,7 +2872,7 @@ $PAD Sh "R12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po 196 1377 $EndPAD $PAD @@ -2881,7 +2886,7 @@ $PAD Sh "R14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000159" +Ne 93 "N-000156" Po 983 1377 $EndPAD $PAD @@ -2923,21 +2928,21 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Sp60" +Ne 20 "/DDR_Banks/M1_DQ10" Po 3346 1377 $EndPAD $PAD Sh "R21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 92 "N-000155" Po 3739 1377 $EndPAD $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Sp61" +Ne 21 "/DDR_Banks/M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -2951,7 +2956,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Sp62" +Ne 14 "/DDR_Banks/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3000,7 +3005,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po -983 1771 $EndPAD $PAD @@ -3028,7 +3033,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po 590 1771 $EndPAD $PAD @@ -3084,7 +3089,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Sp63" +Ne 83 "/FPGA_Spartan6/M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3098,7 +3103,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Ban64" +Ne 51 "/FPGA_Spartan6/M0_DQ13" Po -4133 2165 $EndPAD $PAD @@ -3112,7 +3117,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Sp65" +Ne 50 "/FPGA_Spartan6/M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3126,7 +3131,7 @@ $PAD Sh "U5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -2558 2165 $EndPAD $PAD @@ -3168,7 +3173,7 @@ $PAD Sh "U11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po -196 2165 $EndPAD $PAD @@ -3217,7 +3222,7 @@ $PAD Sh "U18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 92 "N-000155" Po 2558 2165 $EndPAD $PAD @@ -3231,7 +3236,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Sp66" +Ne 76 "/FPGA_Spartan6/M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -3245,21 +3250,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Sp67" +Ne 77 "/FPGA_Spartan6/M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Ban68" +Ne 53 "/FPGA_Spartan6/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Sp69" +Ne 52 "/FPGA_Spartan6/M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3287,7 +3292,7 @@ $PAD Sh "V6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000160" +Ne 94 "N-000157" Po -2165 2558 $EndPAD $PAD @@ -3301,7 +3306,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po -1377 2558 $EndPAD $PAD @@ -3329,7 +3334,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po 196 2558 $EndPAD $PAD @@ -3357,7 +3362,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po 1771 2558 $EndPAD $PAD @@ -3392,14 +3397,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Sp70" +Ne 22 "/DDR_Banks/M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Ban71" +Ne 23 "/DDR_Banks/M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -3413,7 +3418,7 @@ $PAD Sh "W2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000158" +Ne 90 "N-000153" Po -3739 2952 $EndPAD $PAD @@ -3434,7 +3439,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po -2558 2952 $EndPAD $PAD @@ -3546,7 +3551,7 @@ $PAD Sh "W21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 92 "N-000155" Po 3739 2952 $EndPAD $PAD @@ -3728,7 +3733,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po -3346 3739 $EndPAD $PAD @@ -3756,7 +3761,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po -1771 3739 $EndPAD $PAD @@ -3784,7 +3789,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po -196 3739 $EndPAD $PAD @@ -3812,7 +3817,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po 1377 3739 $EndPAD $PAD @@ -3840,7 +3845,7 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000152" +Ne 91 "N-000154" Po 2952 3739 $EndPAD $PAD @@ -4114,7 +4119,7 @@ $PAD Sh "1" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/ETH_MDIO" +Ne 29 "/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD @@ -4128,7 +4133,7 @@ $PAD Sh "47" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Etherne4" +Ne 36 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD @@ -4177,7 +4182,7 @@ $PAD Sh "40" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "N-000406" +Ne 102 "N-000408" Po 491 -1613 $EndPAD $PAD @@ -4191,35 +4196,35 @@ $PAD Sh "38" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Etherne3" +Ne 32 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "N-000402" +Ne 100 "N-000406" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Etherne7" +Ne 33 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Etherne5" +Ne 34 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Etherne6" +Ne 35 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4247,14 +4252,14 @@ $PAD Sh "31" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/Etherne2" +Ne 31 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "N-000405" +Ne 101 "N-000407" Po 1613 -295 $EndPAD $PAD @@ -4289,7 +4294,7 @@ $PAD Sh "13" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Etherne1" +Ne 30 "/Ethernet_Phy/ETH_1.8V" Po -1082 1613 $EndPAD $PAD @@ -4630,14 +4635,14 @@ $PAD Sh "6" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/Non_vol72" +Ne 84 "/Non_volatile_memories/FRB_N" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/Non_vol72" +Ne 84 "/Non_volatile_memories/FRB_N" Po -1090 3850 $EndPAD $PAD @@ -5102,7 +5107,7 @@ $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 102 "N-000406" +Ne 102 "N-000408" Po -1250 -3500 $EndPAD $PAD @@ -5123,7 +5128,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 101 "N-000405" +Ne 101 "N-000407" Po 1750 -3500 $EndPAD $PAD @@ -5151,7 +5156,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 100 "N-000404" +Ne 99 "N-000405" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -5243,14 +5248,14 @@ $PAD Sh "10" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "N-000420" +Ne 105 "N-000419" Po 255 -1112 $EndPAD $PAD Sh "11" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "N-000426" +Ne 106 "N-000420" Po 0 -1112 $EndPAD $PAD @@ -5293,28 +5298,28 @@ $PAD Sh "1" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000048" +Ne 87 "N-000047" Po -4094 2176 $EndPAD $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Sp52" +Ne 74 "/FPGA_Spartan6/M1_DQ0" Po -3838 2176 $EndPAD $PAD Sh "3" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000048" +Ne 87 "N-000047" Po -3582 2176 $EndPAD $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Sp53" +Ne 75 "/FPGA_Spartan6/M1_DQ1" Po -3326 2176 $EndPAD $PAD @@ -5349,21 +5354,21 @@ $PAD Sh "9" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000048" +Ne 87 "N-000047" Po -2047 2176 $EndPAD $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Sp33" +Ne 24 "/DDR_Banks/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Sp40" +Ne 78 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -5377,7 +5382,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Sp41" +Ne 79 "/FPGA_Spartan6/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5391,14 +5396,14 @@ $PAD Sh "15" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000048" +Ne 87 "N-000047" Po -511 2176 $EndPAD $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Ban45" +Ne 26 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -5412,7 +5417,7 @@ $PAD Sh "18" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000048" +Ne 87 "N-000047" Po 255 2176 $EndPAD $PAD @@ -5426,35 +5431,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Ban44" +Ne 81 "/FPGA_Spartan6/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Ban25" +Ne 28 "/DDR_Banks/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Sp28" +Ne 70 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/FPGA_Sp27" +Ne 82 "/FPGA_Spartan6/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 86 "GND" Po 1791 2176 $EndPAD $PAD @@ -5482,42 +5487,42 @@ $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/FPGA_Sp19" +Ne 64 "/FPGA_Spartan6/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A0" +Ne 62 "/FPGA_Spartan6/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A1" +Ne 63 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_A2" +Ne 66 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/FPGA_Sp20" +Ne 16 "/DDR_Banks/M1_A3" Po 3838 2176 $EndPAD $PAD Sh "33" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000048" +Ne 87 "N-000047" Po 4094 2176 $EndPAD $PAD @@ -5531,56 +5536,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/FPGA_Sp17" +Ne 67 "/FPGA_Spartan6/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_A5" +Ne 17 "/DDR_Banks/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_A6" +Ne 18 "/DDR_Banks/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_A7" +Ne 19 "/DDR_Banks/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Sp9" +Ne 68 "/FPGA_Spartan6/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_A9" +Ne 69 "/FPGA_Spartan6/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/DDR_Ban16" +Ne 65 "/FPGA_Spartan6/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/FPGA_Sp13" +Ne 15 "/DDR_Banks/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -5594,28 +5599,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Sp32" +Ne 73 "/FPGA_Spartan6/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/FPGA_Sp12" +Ne 71 "/FPGA_Spartan6/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Ban26" +Ne 72 "/FPGA_Spartan6/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Ban49" +Ne 27 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD @@ -5643,7 +5648,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Sp63" +Ne 83 "/FPGA_Spartan6/M1_UDQS" Po -255 -2176 $EndPAD $PAD @@ -5664,28 +5669,28 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Sp56" +Ne 25 "/DDR_Banks/M1_DQ8" Po -1023 -2176 $EndPAD $PAD Sh "55" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000048" +Ne 87 "N-000047" Po -1279 -2176 $EndPAD $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Sp57" +Ne 80 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Sp60" +Ne 20 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -5699,35 +5704,35 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Sp61" +Ne 21 "/DDR_Banks/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Sp66" +Ne 76 "/FPGA_Spartan6/M1_DQ12" Po -2558 -2176 $EndPAD $PAD Sh "61" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000048" +Ne 87 "N-000047" Po -2814 -2176 $EndPAD $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Sp67" +Ne 77 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Sp70" +Ne 22 "/DDR_Banks/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -5741,7 +5746,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Ban71" +Ne 23 "/DDR_Banks/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -5770,35 +5775,35 @@ $PAD Sh "1" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000056" +Ne 88 "N-000054" Po -4094 2176 $EndPAD $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Ban51" +Ne 47 "/FPGA_Spartan6/M0_DQ0" Po -3838 2176 $EndPAD $PAD Sh "3" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000056" +Ne 88 "N-000054" Po -3582 2176 $EndPAD $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Sp50" +Ne 48 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Sp47" +Ne 54 "/FPGA_Spartan6/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -5812,35 +5817,35 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Ban46" +Ne 9 "/DDR_Banks/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Ban30" +Ne 55 "/FPGA_Spartan6/M0_DQ4" Po -2303 2176 $EndPAD $PAD Sh "9" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000056" +Ne 88 "N-000054" Po -2047 2176 $EndPAD $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Sp29" +Ne 56 "/FPGA_Spartan6/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Ban35" +Ne 57 "/FPGA_Spartan6/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -5854,7 +5859,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Ban34" +Ne 58 "/FPGA_Spartan6/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5868,14 +5873,14 @@ $PAD Sh "15" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000056" +Ne 88 "N-000054" Po -511 2176 $EndPAD $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Ban42" +Ne 12 "/DDR_Banks/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -5889,7 +5894,7 @@ $PAD Sh "18" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000056" +Ne 88 "N-000054" Po 255 2176 $EndPAD $PAD @@ -5903,35 +5908,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Sp43" +Ne 11 "/DDR_Banks/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/DDR_Ban15" +Ne 61 "/FPGA_Spartan6/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Sp37" +Ne 6 "/DDR_Banks/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Sp38" +Ne 13 "/DDR_Banks/M0_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 86 "GND" Po 1791 2176 $EndPAD $PAD @@ -5959,42 +5964,42 @@ $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/FPGA_Sp18" +Ne 2 "/DDR_Banks/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_A0" +Ne 37 "/FPGA_Spartan6/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/FPGA_Sp21" +Ne 1 "/DDR_Banks/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/FPGA_Sp24" +Ne 39 "/FPGA_Spartan6/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Sp39" +Ne 40 "/FPGA_Spartan6/M0_A3" Po 3838 2176 $EndPAD $PAD Sh "33" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000056" +Ne 88 "N-000054" Po 4094 2176 $EndPAD $PAD @@ -6008,56 +6013,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_A4" +Ne 41 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Sp36" +Ne 42 "/FPGA_Spartan6/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Sp31" +Ne 4 "/DDR_Banks/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_A7" +Ne 5 "/DDR_Banks/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M0_A8" +Ne 43 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/FPGA_Sp14" +Ne 44 "/FPGA_Spartan6/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Sp8" +Ne 38 "/FPGA_Spartan6/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/FPGA_Sp10" +Ne 3 "/DDR_Banks/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6071,28 +6076,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/DDR_Ban22" +Ne 7 "/DDR_Banks/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "/DDR_Ban11" +Ne 45 "/FPGA_Spartan6/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Ban23" +Ne 46 "/FPGA_Spartan6/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Sp48" +Ne 60 "/FPGA_Spartan6/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -6120,7 +6125,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Sp62" +Ne 14 "/DDR_Banks/M0_UDQS" Po -255 -2176 $EndPAD $PAD @@ -6141,28 +6146,28 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Sp55" +Ne 10 "/DDR_Banks/M0_DQ8" Po -1023 -2176 $EndPAD $PAD Sh "55" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000056" +Ne 88 "N-000054" Po -1279 -2176 $EndPAD $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Sp54" +Ne 59 "/FPGA_Spartan6/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Sp59" +Ne 8 "/DDR_Banks/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -6176,35 +6181,35 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Sp58" +Ne 49 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Sp65" +Ne 50 "/FPGA_Spartan6/M0_DQ12" Po -2558 -2176 $EndPAD $PAD Sh "61" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000056" +Ne 88 "N-000054" Po -2814 -2176 $EndPAD $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Ban64" +Ne 51 "/FPGA_Spartan6/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Sp69" +Ne 52 "/FPGA_Spartan6/M0_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -6218,7 +6223,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Ban68" +Ne 53 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -6230,7 +6235,7 @@ Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE78 ~~ +Po 33661 32874 0 15 4C5FF890 4C60BE78 ~~ Li 0402 Sc 4C60BE78 AR /4C5F1EDC/4C5F2D27 @@ -6246,7 +6251,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "N-000428" +Ne 108 "N-000426" Po -176 0 $EndPAD $PAD @@ -6258,7 +6263,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE7A ~~ +Po 61614 23228 0 15 4C5FF890 4C60BE7A ~~ Li 0402 Sc 4C60BE7A AR /4C4320F3/4C5D7DC4 @@ -6286,7 +6291,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE7C ~~ +Po 53543 22244 0 15 4C5FF890 4C60BE7C ~~ Li 0402 Sc 4C60BE7C AR /4C4320F3/4C5D71DB @@ -6302,19 +6307,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "N-000404" +Ne 99 "N-000405" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Etherne6" +Ne 35 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE7E ~~ +Po 54921 22047 0 15 4C5FF890 4C60BE7E ~~ Li 0402 Sc 4C60BE7E AR /4C4320F3/4C5D719D @@ -6337,12 +6342,12 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Etherne5" +Ne 34 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE80 ~~ +Po 49016 27362 0 15 4C5FF890 4C60BE80 ~~ Li 0402 Sc 4C60BE80 AR /4C4320F3/4C5D7AF9 @@ -6365,12 +6370,12 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "N-000405" +Ne 101 "N-000407" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE82 ~~ +Po 49016 26575 0 15 4C5FF890 4C60BE82 ~~ Li 0402 Sc 4C60BE82 AR /4C4320F3/4C5D7AF7 @@ -6398,7 +6403,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE84 ~~ +Po 48622 25197 0 15 4C5FF890 4C60BE84 ~~ Li 0402 Sc 4C60BE84 AR /4C4320F3/4C5D7AFC @@ -6421,12 +6426,12 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "N-000406" +Ne 102 "N-000408" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE86 ~~ +Po 41929 18504 0 15 4C5FF890 4C60BE86 ~~ Li 0402 Sc 4C60BE86 AR /4C4320F3/4C5D7AFE @@ -6454,7 +6459,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE88 ~~ +Po 52559 22835 0 15 4C5FF890 4C60BE88 ~~ Li 0402 Sc 4C60BE88 AR /4C4320F3/4C5D7ECF @@ -6470,7 +6475,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "N-000402" +Ne 100 "N-000406" Po -176 0 $EndPAD $PAD @@ -6482,7 +6487,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE8A ~~ +Po 51575 22835 0 15 4C5FF890 4C60BE8A ~~ Li 0402 Sc 4C60BE8A AR /4C4320F3/4C5D7F39 @@ -6498,7 +6503,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/ETH_MDIO" +Ne 29 "/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -6510,7 +6515,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE8C ~~ +Po 33268 31299 0 15 4C5FF890 4C60BE8C ~~ Li 0402 Sc 4C60BE8C AR /4C5F1EDC/4C5F2D1E @@ -6526,7 +6531,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "N-000428" +Ne 108 "N-000426" Po -176 0 $EndPAD $PAD @@ -6538,7 +6543,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE8E ~~ +Po 50787 26969 0 15 4C5FF890 4C60BE8E ~~ Li 0402 Sc 4C60BE8E AR /4C4320F3/4C5D7DCB @@ -6566,7 +6571,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE90 ~~ +Po 55709 23425 0 15 4C5FF890 4C60BE90 ~~ Li 0402 Sc 4C60BE90 AR /4C4320F3/4C5D7E43 @@ -6594,7 +6599,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE92 ~~ +Po 59449 26772 0 15 4C5FF890 4C60BE92 ~~ Li 0402 Sc 4C60BE92 AR /4C4320F3/4C5D7E41 @@ -6622,7 +6627,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE94 ~~ +Po 59055 22244 0 15 4C5FF890 4C60BE94 ~~ Li 0402 Sc 4C60BE94 AR /4C4320F3/4C5D8114 @@ -6638,7 +6643,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Etherne4" +Ne 36 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD @@ -6650,7 +6655,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE96 ~~ +Po 58858 24409 0 15 4C5FF890 4C60BE96 ~~ Li 0402 Sc 4C60BE96 AR /4C4320F3/4C5D7FA7 @@ -6666,7 +6671,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Etherne3" +Ne 32 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD @@ -6678,7 +6683,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE98 ~~ +Po 48425 23622 0 15 4C5FF890 4C60BE98 ~~ Li 0402 Sc 4C60BE98 AR /4C4320F3/4C5D8104 @@ -6694,7 +6699,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/Etherne2" +Ne 31 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD @@ -6706,7 +6711,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE9A ~~ +Po 56890 22835 0 15 4C5FF890 4C60BE9A ~~ Li 0402 Sc 4C60BE9A AR /4C4320F3/4C5D7FA3 @@ -6734,7 +6739,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE9C ~~ +Po 50591 22835 0 15 4C5FF890 4C60BE9C ~~ Li 0402 Sc 4C60BE9C AR /4C4320F3/4C5D80F0 @@ -6762,7 +6767,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BE9E ~~ +Po 50000 24016 0 15 4C5FF890 4C60BE9E ~~ Li 0402 Sc 4C60BE9E AR /4C4320F3/4C5D7FA1 @@ -6790,7 +6795,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 0 0 0 15 4C5FF890 4C60BEA0 ~~ +Po 51772 27756 0 15 4C5FF890 4C60BEA0 ~~ Li 0402 Sc 4C60BEA0 AR /4C4320F3/4C5D80ED @@ -6806,7 +6811,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Etherne1" +Ne 30 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD @@ -6818,7 +6823,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0603 -Po 0 0 0 15 4C5FF890 4C60BEA1 ~~ +Po 39173 34646 0 15 4C5FF890 4C60BEA1 ~~ Li 0603 Sc 4C60BEA1 AR /4C5F1EDC/4C5F2CA3 @@ -6834,7 +6839,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "N-000420" +Ne 105 "N-000419" Po -294 0 $EndPAD $PAD @@ -6846,7 +6851,7 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 0 0 0 15 4C5FF890 4C60BEA3 ~~ +Po 40945 43504 0 15 4C5FF890 4C60BEA3 ~~ Li 0603 Sc 4C60BEA3 AR /4C5F1EDC/4C5F2CA7 @@ -6862,7 +6867,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "N-000426" +Ne 106 "N-000420" Po -294 0 $EndPAD $PAD @@ -6874,7 +6879,7 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 0 0 0 15 4C5FF890 4C60BEA5 ~~ +Po 45472 25197 0 15 4C5FF890 4C60BEA5 ~~ Li 0603 Sc 4C60BEA5 AR /4C4320F3/4C5D810A @@ -6890,19 +6895,19 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/Etherne2" +Ne 31 "/Ethernet_Phy/ETH_A1.8V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Etherne4" +Ne 36 "/Ethernet_Phy/ETH_PLL1.8V" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 0 0 0 15 4C5FF890 4C60BEA7 ~~ +Po 48031 22638 0 15 4C5FF890 4C60BEA7 ~~ Li 0603 Sc 4C60BEA7 AR /4C4320F3/4C5D7FB7 @@ -6925,12 +6930,12 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Etherne3" +Ne 32 "/Ethernet_Phy/ETH_A3.3V" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 0 0 0 15 4C5FF890 4C60BEA9 ~~ +Po 57087 25394 0 15 4C5FF890 4C60BEA9 ~~ Li 0603 Sc 4C60BEA9 AR /4C4320F3/4C5D80F3 @@ -6953,12 +6958,12 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/Etherne2" +Ne 31 "/Ethernet_Phy/ETH_A1.8V" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 0 0 0 15 4C5FF890 4C60BEAB ~~ +Po 35433 31496 0 15 4C5FF890 4C60BEAB ~~ Li 0603 Sc 4C60BEAB AR /4C5F1EDC/4C5F2039 @@ -6986,7 +6991,7 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 0 0 0 15 4C5FF890 4C60BEAD ~~ +Po 35433 30512 0 15 4C5FF890 4C60BEAD ~~ Li 0603 Sc 4C60BEAD AR /4C5F1EDC/4C5F2037 @@ -7014,7 +7019,7 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 0 0 0 15 4C5FF890 4C60BEAF ~~ +Po 35433 32874 0 15 4C5FF890 4C60BEAF ~~ Li 0603 Sc 4C60BEAF AR /4C5F1EDC/4C5F2033 @@ -7042,7 +7047,7 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 0 0 0 15 4C5FF890 4C60BEB1 ~~ +Po 36417 37598 0 15 4C5FF890 4C60BEB1 ~~ Li 0603 Sc 4C60BEB1 AR /4C4320F3/4C5D7FA5 @@ -7058,7 +7063,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Etherne3" +Ne 32 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD @@ -7070,7 +7075,7 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 5906 3150 0 15 4C5FF890 4C60BEB3 ~~ +Po 50197 25787 0 15 4C5FF890 4C60BEB3 ~~ Li 0603 Sc 4C60BEB3 AR /4C4320F3/4C5D7F9F @@ -7097,6 +7102,109 @@ Ne 86 "GND" Po 294 0 $EndPAD $EndMODULE 0603 +$MODULE 1210 +Po 27362 30709 0 15 4C5FF890 4C60C35F ~~ +Li 1210 +Sc 4C60C35F +AR /4C5F1EDC/4C5F2B55 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"F1" +T1 0 150 200 200 0 40 N I 25 N"MICROSMD075F" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 107 "N-000425" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE USB-48204 +Po 35433 43504 0 15 4C5F28A8 4C60C360 ~~ +Li USB-48204 +Sc 4C60C360 +AR /4C5F1EDC/4C5F23DD +Op 0 0 0 +T0 120 -3162 157 157 0 20 N V 21 N"J5" +T1 0 118 118 118 -1800 20 N I 21 N"USB-48204-0001" +DS -1499 5299 -1704 5299 60 21 +DS -1704 5299 -1704 5178 60 21 +DS -1704 5178 -1502 5178 60 21 +DS 1500 5298 1708 5298 60 21 +DS 1708 5298 1707 5180 60 21 +DS 1707 5180 1499 5181 60 21 +DS -1500 -3000 -1500 5300 60 21 +DS -1500 -3000 1500 -3000 60 21 +DS 1500 -3000 1500 5300 60 21 +DS -1500 5300 1500 5300 60 21 +$PAD +Sh "1" R 470 470 0 0 0 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 107 "N-000425" +Po 0 -2362 +$EndPAD +$PAD +Sh "2" C 470 470 0 0 0 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 105 "N-000419" +Po 0 -1575 +$EndPAD +$PAD +Sh "3" C 470 470 0 0 0 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 106 "N-000420" +Po 0 -787 +$EndPAD +$PAD +Sh "3" C 470 470 0 0 0 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 106 "N-000420" +Po 0 0 +$EndPAD +$PAD +Sh "S1" C 670 670 0 0 0 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 108 "N-000426" +Po 1077 287 +$EndPAD +$PAD +Sh "S2" C 670 670 0 0 0 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 108 "N-000426" +Po -1077 287 +$EndPAD +$PAD +Sh "S3" C 670 670 0 0 0 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 108 "N-000426" +Po 1077 -2468 +$EndPAD +$PAD +Sh "S4" C 670 670 0 0 0 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 108 "N-000426" +Po -1077 -2468 +$EndPAD +$EndMODULE USB-48204 $TRACK $EndTRACK $ZONE diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index ecd03b5..3fa3938 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,972 +1,913 @@ -# EESchema Netlist Version 1.1 created Mon 09 Aug 2010 09:53:42 PM COT +# EESchema Netlist Version 1.1 created Mon 09 Aug 2010 10:11:11 PM COT ( - ( /4C4320F3/4C5D7F9F 0603 C1 1uF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D80ED 0402 C2 C - ( 1 /Etherne1 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA1 0402 C3 100nF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D80F0 0402 C4 C - ( 1 N-000417 ) - ( 2 N-000416 ) - ) - ( /4C4320F3/4C5D7FA3 0402 C5 100nF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D8104 0402 C6 C - ( 1 /Etherne2 ) - ( 2 N-000416 ) - ) - ( /4C4320F3/4C5D7FA5 0603 C7 1uF - ( 1 /Etherne3 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA7 0402 C8 100nF - ( 1 /Etherne3 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D8114 0402 C9 C - ( 1 /Etherne4 ) - ( 2 N-000416 ) - ) - ( /4C4320F3/4C5D7E41 0402 C10 100nF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E43 0402 C11 100nF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7DCB 0402 C12 47nF - ( 1 N-000400 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2033 0603 C13 1uF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2037 0603 C14 1uF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2039 0603 C15 470nF - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2D1E 0402 C16 4.7nF - ( 1 N-000428 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2B55 1210 F1 MICROSMD075F - ( 1 N-000427 ) - ( 2 ? ) - ) - ( /4C4227FE/4B76F5E2 MICROSD-500901 J1 MICROSD - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) - ( 7 ? ) - ( 8 ? ) - ( CASE GND ) - ( CD ? ) - ( COM GND ) - ) - ( /4C4320F3/4C5D6F5A SD-48025 J4 RJ45-48025 - ( 1 N-000398 ) - ( 2 N-000406 ) - ( 3 3.3V ) - ( 4 GND ) - ( 5 GND ) - ( 6 3.3V ) - ( 7 N-000399 ) - ( 8 N-000405 ) - ( 9 3.3V ) - ( 10 N-000396 ) - ( 11 3.3V ) - ( 12 N-000404 ) - ( 13 N-000400 ) - ( 14 N-000400 ) - ) - ( /4C5F1EDC/4C5F23DD USB-48204 J5 USB-48204-0001 - ( 1 N-000427 ) - ( 2 N-000420 ) - ( 3 N-000426 ) - ( 4 GND ) - ( S1 N-000428 ) - ( S2 N-000428 ) - ( S3 N-000428 ) - ( S4 N-000428 ) - ) - ( /4C4320F3/4C5D80F3 0603 L1 INDUCTOR - ( 1 N-000417 ) - ( 2 /Etherne2 ) - ) - ( /4C4320F3/4C5D7FB7 0603 L2 FB - ( 1 3.3V ) - ( 2 /Etherne3 ) - ) - ( /4C4320F3/4C5D810A 0603 L3 INDUCTOR - ( 1 /Etherne2 ) - ( 2 /Etherne4 ) - ) - ( /4C4320F3/4C5D7F39 0402 R1 4.7K - ( 1 /ETH_MDIO ) - ( 2 3.3V ) - ) - ( /4C4320F3/4C5D7ECF 0402 R2 6.65K - ( 1 N-000402 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7AFE 0402 R3 49.9 - ( 1 3.3V ) - ( 2 N-000398 ) - ) - ( /4C4320F3/4C5D7AFC 0402 R4 49.9 - ( 1 3.3V ) - ( 2 N-000406 ) - ) - ( /4C4320F3/4C5D7AF7 0402 R5 49.9 - ( 1 3.3V ) - ( 2 N-000399 ) - ) - ( /4C4320F3/4C5D7AF9 0402 R6 49.9 - ( 1 3.3V ) - ( 2 N-000405 ) - ) - ( /4C4320F3/4C5D719D 0402 R7 220 - ( 1 N-000396 ) - ( 2 /Etherne5 ) - ) - ( /4C4320F3/4C5D71DB 0402 R8 220 - ( 1 N-000404 ) - ( 2 /Etherne6 ) - ) - ( /4C4320F3/4C5D7DC4 0402 R9 1M - ( 1 N-000400 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2D27 0402 R10 1M - ( 1 N-000428 ) - ( 2 GND ) - ) - ( /4C431A63/4C431E53 FGG484bga-p10 U1 XC6SLX45FGG484 - ( A1 GND ) - ( A2 ? ) - ( A4 ? ) - ( A5 /Etherne7 ) - ( A6 ? ) - ( A7 ? ) - ( A8 ? ) - ( A9 ? ) - ( A10 ? ) - ( A11 ? ) - ( A12 ? ) - ( A13 ? ) - ( A14 ? ) - ( A15 ? ) - ( A16 ? ) - ( A17 ? ) - ( A18 ? ) - ( A19 ? ) - ( A20 ? ) - ( A21 ? ) - ( A22 GND ) - ( AA1 ? ) - ( AA2 ? ) - ( AA3 N-000152 ) - ( AA4 ? ) - ( AA5 GND ) - ( AA6 ? ) - ( AA7 N-000152 ) - ( AA8 ? ) - ( AA9 GND ) - ( AA10 ? ) - ( AA11 N-000152 ) - ( AA12 ? ) - ( AA13 GND ) - ( AA14 ? ) - ( AA15 N-000152 ) - ( AA16 ? ) - ( AA17 GND ) - ( AA18 ? ) - ( AA19 N-000152 ) - ( AA20 ? ) - ( AA21 ? ) - ( AA22 ? ) - ( AB1 GND ) - ( AB2 ? ) - ( AB3 ? ) - ( AB4 ? ) - ( AB5 ? ) - ( AB6 ? ) - ( AB7 ? ) - ( AB8 ? ) - ( AB9 ? ) - ( AB10 ? ) - ( AB11 ? ) - ( AB12 ? ) - ( AB13 ? ) - ( AB14 ? ) - ( AB15 ? ) - ( AB16 ? ) - ( AB17 ? ) - ( AB18 ? ) + ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} + ( P7 ? ) + ( N7 ? ) + ( M7 ? ) + ( L7 N-000153 ) + ( K7 ? ) + ( J7 ? ) + ( G7 ? ) + ( F7 ? ) + ( P6 ? ) + ( N6 ? ) + ( M6 ? ) + ( L6 ? ) + ( K6 /FPGA_Spartan6/M0_A3 ) + ( J6 ? ) + ( H6 /DDR_Banks/M0_A7 ) + ( G6 ? ) + ( F6 N-000153 ) + ( E6 ? ) + ( U5 N-000153 ) + ( P5 ? ) + ( N5 N-000153 ) + ( M5 ? ) + ( K5 /DDR_Banks/M0_RAS# ) + ( J5 N-000153 ) + ( H5 /FPGA_Spartan6/M0_A2 ) + ( F5 ? ) + ( E5 ? ) + ( D5 ? ) + ( U4 ? ) + ( H21 /FPGA_Spartan6/M1_RAS# ) + ( G21 N-000155 ) + ( F21 /FPGA_Spartan6/M1_A0 ) + ( D21 /FPGA_Spartan6/M1_CKE ) + ( C21 N-000155 ) + ( B21 ? ) + ( A21 ? ) + ( W20 ? ) + ( V20 ? ) + ( U20 /FPGA_Spartan6/M1_DQ12 ) + ( T20 ? ) + ( R20 /DDR_Banks/M1_DQ10 ) + ( P20 ? ) + ( N20 /FPGA_Spartan6/M1_DQ0 ) + ( M20 /DDR_Banks/M1_UDM ) + ( L20 /DDR_Banks/M1_LDQS ) + ( K20 /DDR_Banks/M1_A5 ) + ( J20 ? ) + ( H20 /FPGA_Spartan6/M1_CLK ) + ( G20 /DDR_Banks/M1_A3 ) + ( F20 /FPGA_Spartan6/M1_A4 ) + ( E20 /DDR_Banks/M1_A7 ) + ( D20 ? ) + ( C20 /FPGA_Spartan6/M1_A8 ) + ( B20 ? ) + ( A20 ? ) + ( P8 ? ) + ( M8 ? ) + ( K8 ? ) + ( H8 ? ) + ( B3 ? ) + ( W2 N-000153 ) + ( V2 /FPGA_Spartan6/M0_DQ14 ) + ( T2 /DDR_Banks/M0_UDQS ) + ( R2 N-000153 ) + ( P2 /DDR_Banks/M0_DQ8 ) + ( M2 /FPGA_Spartan6/M0_DQ2 ) + ( L2 N-000153 ) + ( K2 /FPGA_Spartan6/M0_DQ6 ) + ( H2 /FPGA_Spartan6/M0_A0 ) + ( G2 N-000153 ) + ( F2 /FPGA_Spartan6/M0_WE# ) + ( D2 /FPGA_Spartan6/M0_CKE ) + ( C2 N-000153 ) + ( B2 ? ) + ( A2 ? ) + ( Y1 ? ) + ( W1 ? ) + ( V1 /FPGA_Spartan6/M0_DQ15 ) + ( U1 /FPGA_Spartan6/M0_DQ13 ) + ( T1 ? ) + ( R1 /FPGA_Spartan6/M0_DQ11 ) + ( P1 /FPGA_Spartan6/M0_DQ9 ) + ( N1 /FPGA_Spartan6/M0_DQ1 ) + ( M1 /DDR_Banks/M0_DQ3 ) + ( L1 ? ) + ( K1 /FPGA_Spartan6/M0_DQ7 ) + ( J1 /FPGA_Spartan6/M0_DQ5 ) + ( H1 /DDR_Banks/M0_A1 ) + ( G1 ? ) + ( T4 ? ) + ( R4 ? ) + ( P4 ? ) + ( N4 ? ) + ( M4 ? ) + ( L4 /DDR_Banks/M0_LDM ) + ( K4 /DDR_Banks/M0_CAS# ) + ( J4 /DDR_Banks/M0_A6 ) + ( H4 /FPGA_Spartan6/M0_CLK ) + ( G4 /DDR_Banks/M0_A10 ) + ( F4 N-000153 ) + ( E4 ? ) + ( C4 ? ) + ( W3 ? ) + ( V3 ? ) + ( U3 /FPGA_Spartan6/M0_DQ12 ) + ( T3 ? ) + ( R3 /DDR_Banks/M0_DQ10 ) + ( P3 ? ) + ( N3 /FPGA_Spartan6/M0_DQ0 ) + ( M3 /FPGA_Spartan6/M0_UDM ) + ( L3 /DDR_Banks/M0_LDQS ) + ( K3 /FPGA_Spartan6/M0_A5 ) + ( J3 /FPGA_Spartan6/M0_DQ4 ) + ( H3 /DDR_Banks/M0_CLK# ) + ( G3 ? ) + ( F3 /FPGA_Spartan6/M0_A4 ) + ( E3 /FPGA_Spartan6/M0_A8 ) + ( D3 ? ) + ( C3 ? ) + ( G10 N-000137 ) + ( D10 ? ) + ( C10 ? ) + ( B10 ? ) + ( A10 ? ) + ( E9 N-000137 ) + ( D9 ? ) + ( C9 ? ) + ( A9 ? ) + ( D8 ? ) + ( C8 ? ) + ( B8 ? ) + ( A8 ? ) + ( D7 ? ) + ( C7 ? ) + ( B7 N-000137 ) + ( A7 ? ) + ( D6 ? ) + ( C6 ? ) + ( B6 ? ) + ( A6 ? ) + ( C5 ? ) + ( A5 /Ethernet_Phy/ETH_INT ) + ( B4 N-000137 ) + ( A4 ? ) + ( U19 ? ) + ( T19 ? ) + ( R19 ? ) + ( P19 ? ) + ( N19 ? ) + ( B19 N-000137 ) + ( B18 ? ) + ( A18 ? ) + ( E17 N-000137 ) + ( D17 ? ) + ( C17 ? ) + ( A17 ? ) + ( E16 ? ) + ( C16 ? ) + ( B16 ? ) + ( A16 ? ) + ( D15 ? ) + ( C15 ? ) + ( B15 N-000137 ) + ( A15 ? ) + ( G14 N-000137 ) + ( D14 ? ) + ( C14 ? ) + ( B14 ? ) + ( A14 ? ) + ( E13 N-000137 ) + ( C13 ? ) + ( A13 ? ) + ( C12 ? ) + ( B12 ? ) + ( A12 ? ) + ( D11 ? ) + ( C11 ? ) + ( B11 N-000137 ) + ( A11 ? ) + ( H16 ? ) + ( G16 ? ) + ( F16 ? ) + ( L15 ? ) + ( W22 ? ) + ( V22 /DDR_Banks/M1_DQ15 ) + ( U22 /FPGA_Spartan6/M1_DQ13 ) + ( T22 ? ) + ( R22 /DDR_Banks/M1_DQ11 ) + ( P22 /FPGA_Spartan6/M1_DQ9 ) + ( N22 /FPGA_Spartan6/M1_DQ1 ) + ( M22 ? ) + ( L22 ? ) + ( K22 /FPGA_Spartan6/M1_DQ7 ) + ( J22 /DDR_Banks/M1_DQ5 ) + ( H22 /FPGA_Spartan6/M1_CAS# ) + ( G22 ? ) + ( F22 /FPGA_Spartan6/M1_A1 ) + ( E22 /FPGA_Spartan6/M1_A2 ) + ( D22 /DDR_Banks/M1_A12 ) + ( C22 /FPGA_Spartan6/M1_A9 ) + ( B22 ? ) + ( W21 N-000155 ) + ( V21 /DDR_Banks/M1_DQ14 ) + ( T21 /FPGA_Spartan6/M1_UDQS ) + ( R21 N-000155 ) + ( P21 /DDR_Banks/M1_DQ8 ) + ( M21 ? ) + ( L21 N-000155 ) + ( K21 /FPGA_Spartan6/M1_DQ6 ) + ( M19 ? ) + ( L19 /FPGA_Spartan6/M1_LDM ) + ( K19 /DDR_Banks/M1_A6 ) + ( J19 /FPGA_Spartan6/M1_CLK# ) + ( H19 /DDR_Banks/M1_WE# ) + ( G19 /FPGA_Spartan6/M1_A10 ) + ( F19 /FPGA_Spartan6/M1_A11 ) + ( E19 N-000155 ) + ( D19 ? ) + ( U18 N-000155 ) + ( P18 ? ) + ( N18 N-000155 ) + ( M18 ? ) + ( K18 ? ) + ( J18 N-000155 ) + ( H18 ? ) + ( F18 ? ) + ( P17 ? ) + ( M17 ? ) + ( L17 ? ) + ( K17 ? ) + ( J17 ? ) + ( H17 ? ) + ( G17 ? ) + ( F17 ? ) + ( N16 ? ) + ( M16 ? ) + ( L16 N-000155 ) + ( K16 ? ) + ( J16 ? ) + ( J14 N-000156 ) + ( H14 ? ) + ( F14 ? ) + ( E14 ? ) + ( P13 N-000156 ) + ( N13 GND ) + ( M13 N-000156 ) + ( L13 GND ) + ( K13 N-000156 ) + ( J13 GND ) + ( H13 ? ) + ( G13 ? ) + ( F13 ? ) + ( D13 ? ) + ( B13 GND ) + ( Y22 ? ) + ( A22 GND ) + ( R12 N-000157 ) + ( P12 GND ) + ( N12 N-000156 ) + ( M12 GND ) + ( L12 N-000156 ) + ( K12 ? ) + ( J12 N-000156 ) + ( H12 ? ) + ( G12 N-000157 ) + ( F12 ? ) + ( E12 ? ) + ( D12 ? ) + ( AB1 GND ) + ( A19 ? ) + ( R18 GND ) + ( L18 GND ) + ( G18 GND ) + ( E18 ? ) + ( D18 GND ) + ( C18 ? ) + ( R17 ? ) + ( N17 GND ) + ( B17 GND ) + ( W16 GND ) + ( P16 ? ) + ( D16 N-000157 ) + ( AA5 GND ) + ( P15 ? ) + ( N15 ? ) + ( M15 N-000157 ) + ( K15 N-000157 ) + ( J15 GND ) + ( H15 N-000157 ) + ( G15 ? ) + ( F15 ? ) + ( E15 GND ) + ( V14 GND ) + ( R14 N-000156 ) + ( P14 GND ) + ( N14 N-000156 ) + ( M14 GND ) + ( L14 N-000156 ) + ( K14 GND ) + ( L9 GND ) + ( K9 N-000156 ) + ( J9 GND ) + ( H9 N-000157 ) + ( G9 ? ) + ( F9 ? ) + ( B9 GND ) + ( N8 N-000157 ) + ( L8 N-000157 ) + ( J8 N-000156 ) + ( G8 ? ) + ( F8 ? ) + ( E8 ? ) + ( W7 GND ) + ( U7 GND ) + ( H7 GND ) + ( E7 GND ) + ( V6 N-000157 ) + ( R6 N-000157 ) + ( R5 GND ) + ( L5 GND ) + ( G5 GND ) + ( B5 GND ) + ( V4 GND ) + ( D4 GND ) + ( U2 GND ) + ( N2 GND ) + ( J2 GND ) + ( E2 GND ) + ( A1 GND ) + ( AA1 ? ) + ( U21 GND ) + ( N21 GND ) + ( J21 GND ) + ( E21 GND ) + ( U11 N-000157 ) + ( P11 N-000156 ) + ( N11 GND ) + ( M11 N-000156 ) + ( L11 GND ) + ( K11 N-000156 ) + ( J11 GND ) + ( H11 ? ) + ( G11 ? ) + ( F11 N-000157 ) + ( E11 ? ) + ( V10 GND ) + ( R10 N-000157 ) + ( P10 GND ) + ( N10 N-000156 ) + ( M10 GND ) + ( L10 N-000156 ) + ( K10 GND ) + ( J10 N-000156 ) + ( H10 ? ) + ( F10 ? ) + ( E10 ? ) + ( P9 N-000156 ) + ( N9 GND ) + ( M9 N-000156 ) + ( V19 ? ) + ( AB8 ? ) + ( AA8 ? ) + ( Y18 ? ) + ( W18 ? ) + ( V18 ? ) + ( T18 ? ) + ( AB7 ? ) + ( AA7 N-000154 ) + ( Y17 ? ) + ( W17 ? ) + ( V17 ? ) + ( U17 ? ) + ( T17 ? ) + ( AB6 ? ) + ( AA6 ? ) + ( Y16 ? ) + ( V16 N-000154 ) + ( U16 ? ) + ( T16 ? ) + ( R16 ? ) + ( AB5 ? ) + ( Y15 ? ) + ( W15 ? ) + ( V15 ? ) + ( U15 ? ) + ( T15 ? ) + ( R15 ? ) + ( AB4 ? ) + ( AA4 ? ) + ( F1 ? ) + ( E1 /FPGA_Spartan6/M0_A9 ) + ( D1 /DDR_Banks/M0_A12 ) + ( C1 /FPGA_Spartan6/M0_A11 ) + ( B1 ? ) ( AB19 ? ) - ( AB20 ? ) + ( AA19 N-000154 ) + ( AB18 ? ) + ( AA18 ? ) + ( AB17 ? ) + ( AB16 ? ) + ( AA16 ? ) + ( AB15 ? ) + ( AA15 N-000154 ) + ( AB14 ? ) + ( AA14 ? ) + ( AB13 ? ) + ( AA22 ? ) + ( AB12 ? ) + ( AA12 ? ) ( AB21 ? ) + ( AA21 ? ) + ( AB11 ? ) + ( AA11 N-000154 ) + ( AB20 ? ) + ( AA20 ? ) + ( AB10 ? ) + ( AA10 ? ) + ( AB9 ? ) + ( Y19 ? ) + ( V9 ? ) + ( U9 ? ) + ( T9 N-000154 ) + ( R9 ? ) + ( Y8 ? ) + ( W8 ? ) + ( V8 N-000154 ) + ( U8 ? ) + ( T8 ? ) + ( R8 ? ) + ( Y7 ? ) + ( V7 ? ) + ( T7 ? ) + ( R7 ? ) + ( Y6 ? ) + ( W6 ? ) + ( U6 ? ) + ( T6 ? ) + ( Y5 ? ) + ( W5 N-000154 ) + ( V5 ? ) + ( T5 ? ) + ( Y4 ? ) + ( W4 ? ) + ( Y3 ? ) + ( AA17 GND ) + ( AA13 GND ) ( AB22 GND ) - ( B1 ? ) - ( B2 ? ) - ( B3 ? ) - ( B4 N-000153 ) - ( B5 GND ) - ( B6 ? ) - ( B7 N-000153 ) - ( B8 ? ) - ( B9 GND ) - ( B10 ? ) - ( B11 N-000153 ) - ( B12 ? ) - ( B13 GND ) - ( B14 ? ) - ( B15 N-000153 ) - ( B16 ? ) - ( B17 GND ) - ( B18 ? ) - ( B19 N-000153 ) - ( B20 ? ) - ( B21 ? ) - ( B22 ? ) - ( C1 /FPGA_Sp8 ) - ( C2 N-000158 ) - ( C3 ? ) - ( C4 ? ) - ( C5 ? ) - ( C6 ? ) - ( C7 ? ) - ( C8 ? ) - ( C9 ? ) - ( C10 ? ) - ( C11 ? ) - ( C12 ? ) - ( C13 ? ) - ( C14 ? ) - ( C15 ? ) - ( C16 ? ) - ( C17 ? ) - ( C18 ? ) - ( C20 /FPGA_Sp9 ) - ( C21 N-000154 ) - ( C22 /DDR_Banks/M1_A9 ) - ( D1 /FPGA_Sp10 ) - ( D2 /DDR_Ban11 ) - ( D3 ? ) - ( D4 GND ) - ( D5 ? ) - ( D6 ? ) - ( D7 ? ) - ( D8 ? ) - ( D9 ? ) - ( D10 ? ) - ( D11 ? ) - ( D12 ? ) - ( D13 ? ) - ( D14 ? ) - ( D15 ? ) - ( D16 N-000160 ) - ( D17 ? ) - ( D18 GND ) - ( D19 ? ) - ( D20 ? ) - ( D21 /FPGA_Sp12 ) - ( D22 /FPGA_Sp13 ) - ( E1 /FPGA_Sp14 ) - ( E2 GND ) - ( E3 /DDR_Banks/M0_A8 ) - ( E4 ? ) - ( E5 ? ) - ( E6 ? ) - ( E7 GND ) - ( E8 ? ) - ( E9 N-000153 ) - ( E10 ? ) - ( E11 GND ) - ( E12 ? ) - ( E13 N-000153 ) - ( E14 ? ) - ( E15 GND ) - ( E16 ? ) - ( E17 N-000153 ) - ( E18 ? ) - ( E19 N-000154 ) - ( E20 /DDR_Banks/M1_A7 ) - ( E21 GND ) - ( E22 /DDR_Banks/M1_A2 ) - ( F1 ? ) - ( F2 /DDR_Ban15 ) - ( F3 /DDR_Banks/M0_A4 ) - ( F4 N-000158 ) - ( F5 ? ) - ( F6 N-000158 ) - ( F7 ? ) - ( F8 ? ) - ( F9 ? ) - ( F10 ? ) - ( F11 N-000160 ) - ( F12 ? ) - ( F13 ? ) - ( F14 ? ) - ( F15 ? ) - ( F16 ? ) - ( F17 ? ) - ( F18 ? ) - ( F19 /DDR_Ban16 ) - ( F20 /FPGA_Sp17 ) - ( F21 /DDR_Banks/M1_A0 ) - ( F22 /DDR_Banks/M1_A1 ) - ( G1 ? ) - ( G2 N-000158 ) - ( G3 ? ) - ( G4 /FPGA_Sp18 ) - ( G5 GND ) - ( G6 ? ) - ( G7 ? ) - ( G8 ? ) - ( G9 ? ) - ( G10 N-000153 ) - ( G11 ? ) - ( G12 N-000160 ) - ( G13 ? ) - ( G14 N-000153 ) - ( G15 ? ) - ( G16 ? ) - ( G17 ? ) - ( G18 GND ) - ( G19 /FPGA_Sp19 ) - ( G20 /FPGA_Sp20 ) - ( G21 N-000154 ) - ( G22 ? ) - ( H1 /FPGA_Sp21 ) - ( H2 /DDR_Banks/M0_A0 ) - ( H3 /DDR_Ban22 ) - ( H4 /DDR_Ban23 ) - ( H5 /FPGA_Sp24 ) - ( H6 /DDR_Banks/M0_A7 ) - ( H7 GND ) - ( H8 ? ) - ( H9 N-000160 ) - ( H10 ? ) - ( H11 ? ) - ( H12 ? ) - ( H13 ? ) - ( H14 ? ) - ( H15 N-000160 ) - ( H16 ? ) - ( H17 ? ) - ( H18 ? ) - ( H19 /DDR_Ban25 ) - ( H20 /DDR_Ban26 ) - ( H21 /FPGA_Sp27 ) - ( H22 /FPGA_Sp28 ) - ( J1 /FPGA_Sp29 ) - ( J2 GND ) - ( J3 /DDR_Ban30 ) - ( J4 /FPGA_Sp31 ) - ( J5 N-000158 ) - ( J6 ? ) - ( J7 ? ) - ( J8 N-000159 ) - ( J9 GND ) - ( J10 N-000159 ) - ( J11 GND ) - ( J12 N-000159 ) - ( J13 GND ) - ( J14 N-000159 ) - ( J15 GND ) - ( J16 ? ) - ( J17 ? ) - ( J18 N-000154 ) - ( J19 /FPGA_Sp32 ) - ( J20 ? ) - ( J21 GND ) - ( J22 /FPGA_Sp33 ) - ( K1 /DDR_Ban34 ) - ( K2 /DDR_Ban35 ) - ( K3 /FPGA_Sp36 ) - ( K4 /FPGA_Sp37 ) - ( K5 /FPGA_Sp38 ) - ( K6 /FPGA_Sp39 ) - ( K7 ? ) - ( K8 ? ) - ( K9 N-000159 ) - ( K10 GND ) - ( K11 N-000159 ) - ( K12 GND ) - ( K13 N-000159 ) - ( K14 GND ) - ( K15 N-000160 ) - ( K16 ? ) - ( K17 ? ) - ( K18 ? ) - ( K19 /DDR_Banks/M1_A6 ) - ( K20 /DDR_Banks/M1_A5 ) - ( K21 /FPGA_Sp40 ) - ( K22 /FPGA_Sp41 ) - ( L1 ? ) - ( L2 N-000158 ) - ( L3 /DDR_Ban42 ) - ( L4 /FPGA_Sp43 ) - ( L5 GND ) - ( L6 ? ) - ( L7 N-000158 ) - ( L8 N-000160 ) - ( L9 GND ) - ( L10 N-000159 ) - ( L11 GND ) - ( L12 N-000159 ) - ( L13 GND ) - ( L14 N-000159 ) - ( L15 ? ) - ( L16 N-000154 ) - ( L17 ? ) - ( L18 GND ) - ( L19 /DDR_Ban44 ) - ( L20 /DDR_Ban45 ) - ( L21 N-000154 ) - ( L22 ? ) - ( M1 /DDR_Ban46 ) - ( M2 /FPGA_Sp47 ) - ( M3 /FPGA_Sp48 ) - ( M4 ? ) - ( M5 ? ) - ( M6 ? ) - ( M7 ? ) - ( M8 ? ) - ( M9 N-000159 ) - ( M10 GND ) - ( M11 N-000159 ) - ( M12 GND ) - ( M13 N-000159 ) - ( M14 GND ) - ( M15 N-000160 ) - ( M16 ? ) - ( M17 ? ) - ( M18 ? ) - ( M19 ? ) - ( M20 /DDR_Ban49 ) - ( M21 ? ) - ( M22 ? ) - ( N1 /FPGA_Sp50 ) - ( N2 GND ) - ( N3 /DDR_Ban51 ) - ( N4 ? ) - ( N5 N-000158 ) - ( N6 ? ) - ( N7 ? ) - ( N8 N-000160 ) - ( N9 GND ) - ( N10 N-000159 ) - ( N11 GND ) - ( N12 N-000159 ) - ( N13 GND ) - ( N14 N-000159 ) - ( N15 ? ) - ( N16 ? ) - ( N17 GND ) - ( N18 N-000154 ) - ( N19 ? ) - ( N20 /FPGA_Sp52 ) - ( N21 GND ) - ( N22 /FPGA_Sp53 ) - ( P1 /FPGA_Sp54 ) - ( P2 /FPGA_Sp55 ) - ( P3 ? ) - ( P4 ? ) - ( P5 ? ) - ( P6 ? ) - ( P7 ? ) - ( P8 ? ) - ( P9 N-000159 ) - ( P10 GND ) - ( P11 N-000159 ) - ( P12 GND ) - ( P13 N-000159 ) - ( P14 GND ) - ( P15 ? ) - ( P16 ? ) - ( P17 ? ) - ( P18 ? ) - ( P19 ? ) - ( P20 ? ) - ( P21 /FPGA_Sp56 ) - ( P22 /FPGA_Sp57 ) - ( R1 /FPGA_Sp58 ) - ( R2 N-000158 ) - ( R3 /FPGA_Sp59 ) - ( R4 ? ) - ( R5 GND ) - ( R6 N-000160 ) - ( R7 ? ) - ( R8 ? ) - ( R9 ? ) - ( R10 N-000160 ) - ( R11 ? ) - ( R12 N-000160 ) - ( R13 ? ) - ( R14 N-000159 ) - ( R15 ? ) - ( R16 ? ) - ( R17 ? ) - ( R18 GND ) - ( R19 ? ) - ( R20 /FPGA_Sp60 ) - ( R21 N-000154 ) - ( R22 /FPGA_Sp61 ) - ( T1 ? ) - ( T2 /FPGA_Sp62 ) - ( T3 ? ) - ( T4 ? ) - ( T5 ? ) - ( T6 ? ) - ( T7 ? ) - ( T8 ? ) - ( T9 N-000152 ) - ( T10 ? ) - ( T11 ? ) - ( T12 ? ) - ( T13 N-000152 ) - ( T14 ? ) - ( T15 ? ) - ( T16 ? ) - ( T17 ? ) - ( T18 ? ) - ( T19 ? ) - ( T20 ? ) - ( T21 /FPGA_Sp63 ) - ( T22 ? ) - ( U1 /DDR_Ban64 ) - ( U2 GND ) - ( U3 /FPGA_Sp65 ) - ( U4 ? ) - ( U5 N-000158 ) - ( U6 ? ) - ( U7 GND ) - ( U8 ? ) - ( U9 ? ) - ( U10 ? ) - ( U11 N-000160 ) - ( U12 ? ) - ( U13 ? ) - ( U14 ? ) - ( U15 ? ) - ( U16 ? ) - ( U17 ? ) - ( U18 N-000154 ) - ( U19 ? ) - ( U20 /FPGA_Sp66 ) - ( U21 GND ) - ( U22 /FPGA_Sp67 ) - ( V1 /DDR_Ban68 ) - ( V2 /FPGA_Sp69 ) - ( V3 ? ) - ( V4 GND ) - ( V5 ? ) - ( V6 N-000160 ) - ( V7 ? ) - ( V8 N-000152 ) - ( V9 ? ) - ( V10 GND ) - ( V11 ? ) - ( V12 N-000152 ) - ( V13 ? ) - ( V14 GND ) - ( V15 ? ) - ( V16 N-000152 ) - ( V17 ? ) - ( V18 ? ) - ( V19 ? ) - ( V20 ? ) - ( V21 /FPGA_Sp70 ) - ( V22 /DDR_Ban71 ) - ( W1 ? ) - ( W2 N-000158 ) - ( W3 ? ) - ( W4 ? ) - ( W5 N-000152 ) - ( W6 ? ) - ( W7 GND ) - ( W8 ? ) - ( W9 ? ) - ( W10 ? ) - ( W11 ? ) - ( W12 ? ) - ( W13 ? ) - ( W14 ? ) - ( W15 ? ) - ( W16 GND ) - ( W17 ? ) - ( W18 ? ) - ( W19 GND ) - ( W20 ? ) - ( W21 N-000154 ) - ( W22 ? ) - ( Y1 ? ) - ( Y3 ? ) - ( Y4 ? ) - ( Y5 ? ) - ( Y6 ? ) - ( Y7 ? ) - ( Y8 ? ) - ( Y9 ? ) - ( Y10 ? ) - ( Y11 ? ) - ( Y12 ? ) - ( Y13 ? ) - ( Y14 ? ) - ( Y15 ? ) - ( Y16 ? ) - ( Y17 ? ) - ( Y18 ? ) - ( Y19 ? ) - ( Y22 ? ) + ( AA9 GND ) + ( W19 GND ) + ( Y14 ? ) + ( W14 ? ) + ( U14 ? ) + ( T14 ? ) + ( AB3 ? ) + ( AA3 N-000154 ) + ( Y13 ? ) + ( W13 ? ) + ( V13 ? ) + ( U13 ? ) + ( T13 N-000154 ) + ( R13 ? ) + ( AB2 ? ) + ( AA2 ? ) + ( Y12 ? ) + ( W12 ? ) + ( V12 N-000154 ) + ( U12 ? ) + ( T12 ? ) + ( Y11 ? ) + ( W11 ? ) + ( V11 ? ) + ( T11 ? ) + ( R11 ? ) + ( Y10 ? ) + ( W10 ? ) + ( U10 ? ) + ( T10 ? ) + ( Y9 ? ) + ( W9 ? ) ) - ( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG - ( 1 N-000056 ) - ( 2 /DDR_Ban51 ) - ( 3 N-000056 ) - ( 4 /FPGA_Sp50 ) - ( 5 /FPGA_Sp47 ) - ( 6 GND ) - ( 7 /DDR_Ban46 ) - ( 8 /DDR_Ban30 ) - ( 9 N-000056 ) - ( 10 /FPGA_Sp29 ) - ( 11 /DDR_Ban35 ) - ( 12 GND ) - ( 13 /DDR_Ban34 ) - ( 14 ? ) - ( 15 N-000056 ) - ( 16 /DDR_Ban42 ) - ( 17 ? ) - ( 18 N-000056 ) - ( 19 ? ) - ( 20 /FPGA_Sp43 ) - ( 21 /DDR_Ban15 ) - ( 22 /FPGA_Sp37 ) - ( 23 /FPGA_Sp38 ) - ( 24 ? ) - ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 /FPGA_Sp18 ) - ( 29 /DDR_Banks/M0_A0 ) - ( 30 /FPGA_Sp21 ) - ( 31 /FPGA_Sp24 ) - ( 32 /FPGA_Sp39 ) - ( 33 N-000056 ) - ( 34 GND ) - ( 35 /DDR_Banks/M0_A4 ) - ( 36 /FPGA_Sp36 ) - ( 37 /FPGA_Sp31 ) - ( 38 /DDR_Banks/M0_A7 ) - ( 39 /DDR_Banks/M0_A8 ) - ( 40 /FPGA_Sp14 ) - ( 41 /FPGA_Sp8 ) - ( 42 /FPGA_Sp10 ) - ( 43 ? ) - ( 44 /DDR_Ban22 ) - ( 45 /DDR_Ban11 ) - ( 46 /DDR_Ban23 ) - ( 47 /FPGA_Sp48 ) - ( 48 GND ) - ( 49 ? ) - ( 50 ? ) - ( 51 /FPGA_Sp62 ) - ( 52 GND ) - ( 53 ? ) - ( 54 /FPGA_Sp55 ) - ( 55 N-000056 ) - ( 56 /FPGA_Sp54 ) - ( 57 /FPGA_Sp59 ) - ( 58 GND ) - ( 59 /FPGA_Sp58 ) - ( 60 /FPGA_Sp65 ) - ( 61 N-000056 ) - ( 62 /DDR_Ban64 ) - ( 63 /FPGA_Sp69 ) - ( 64 GND ) - ( 65 /DDR_Ban68 ) - ( 66 GND ) + ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} + ( 1 N-000426 ) + ( 2 GND ) ) - ( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG - ( 1 N-000048 ) - ( 2 /FPGA_Sp52 ) - ( 3 N-000048 ) - ( 4 /FPGA_Sp53 ) - ( 5 ? ) - ( 6 GND ) - ( 7 ? ) - ( 8 ? ) - ( 9 N-000048 ) - ( 10 /FPGA_Sp33 ) - ( 11 /FPGA_Sp40 ) - ( 12 GND ) - ( 13 /FPGA_Sp41 ) - ( 14 ? ) - ( 15 N-000048 ) - ( 16 /DDR_Ban45 ) - ( 17 ? ) - ( 18 N-000048 ) - ( 19 ? ) - ( 20 /DDR_Ban44 ) - ( 21 /DDR_Ban25 ) - ( 22 /FPGA_Sp28 ) - ( 23 /FPGA_Sp27 ) - ( 24 ? ) - ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 /FPGA_Sp19 ) - ( 29 /DDR_Banks/M1_A0 ) - ( 30 /DDR_Banks/M1_A1 ) - ( 31 /DDR_Banks/M1_A2 ) - ( 32 /FPGA_Sp20 ) - ( 33 N-000048 ) - ( 34 GND ) - ( 35 /FPGA_Sp17 ) - ( 36 /DDR_Banks/M1_A5 ) - ( 37 /DDR_Banks/M1_A6 ) - ( 38 /DDR_Banks/M1_A7 ) - ( 39 /FPGA_Sp9 ) - ( 40 /DDR_Banks/M1_A9 ) - ( 41 /DDR_Ban16 ) - ( 42 /FPGA_Sp13 ) - ( 43 ? ) - ( 44 /FPGA_Sp32 ) - ( 45 /FPGA_Sp12 ) - ( 46 /DDR_Ban26 ) - ( 47 /DDR_Ban49 ) - ( 48 GND ) - ( 49 ? ) - ( 50 ? ) - ( 51 /FPGA_Sp63 ) - ( 52 GND ) - ( 53 ? ) - ( 54 /FPGA_Sp56 ) - ( 55 N-000048 ) - ( 56 /FPGA_Sp57 ) - ( 57 /FPGA_Sp60 ) - ( 58 GND ) - ( 59 /FPGA_Sp61 ) - ( 60 /FPGA_Sp66 ) - ( 61 N-000048 ) - ( 62 /FPGA_Sp67 ) - ( 63 /FPGA_Sp70 ) - ( 64 GND ) - ( 65 /DDR_Ban71 ) - ( 66 GND ) + ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} + ( 1 N-000426 ) + ( 2 GND ) ) - ( /4C4320F3/4C432132 LQFP48 U4 K8001 - ( 1 /ETH_MDIO ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) - ( 7 3.3V ) - ( 8 GND ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 GND ) - ( 13 /Etherne1 ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ( 17 ? ) - ( 18 ? ) - ( 19 ? ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 GND ) - ( 24 3.3V ) - ( 25 /Etherne7 ) - ( 26 /Etherne5 ) - ( 27 /Etherne6 ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 /Etherne2 ) - ( 32 N-000405 ) - ( 33 N-000399 ) - ( 34 ? ) - ( 35 GND ) - ( 36 GND ) - ( 37 N-000402 ) - ( 38 /Etherne3 ) - ( 39 GND ) - ( 40 N-000406 ) - ( 41 N-000398 ) - ( 42 ? ) - ( 43 ? ) - ( 44 GND ) - ( 45 ? ) - ( 46 ? ) - ( 47 /Etherne4 ) - ( 48 ? ) + ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000420 ) + ( 2 GND ) ) - ( /4C4227FE/4B76F108 NAND-48TSOP U5 NAND - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 /Non_vol72 ) - ( 7 /Non_vol72 ) - ( 8 ? ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 3.3V ) - ( 13 GND ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ( 17 ? ) - ( 18 ? ) - ( 19 3.3V ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 ? ) - ( 24 ? ) - ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 ? ) - ( 32 ? ) - ( 33 ? ) - ( 34 ? ) - ( 35 ? ) - ( 36 GND ) - ( 37 3.3V ) - ( 38 ? ) - ( 39 ? ) - ( 40 ? ) - ( 41 ? ) - ( 42 ? ) - ( 43 ? ) - ( 44 ? ) - ( 45 ? ) - ( 46 ? ) - ( 47 ? ) - ( 48 ? ) + ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000419 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2025 TSSOP-14 U6 MIC2550AYTS - ( 1 3.3V ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 7 GND ) - ( 8 GND ) - ( 9 ? ) - ( 10 N-000420 ) - ( 11 N-000426 ) - ( 12 3.3V ) - ( 14 3.3V ) + ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} + ( 1 N-000425 ) + ( 2 ? ) ) - ( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 - ( 1 N-000426 ) - ( 2 GND ) + ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} + ( S1 N-000426 ) + ( S2 N-000426 ) + ( S3 N-000426 ) + ( S4 N-000426 ) + ( 1 N-000425 ) + ( 2 N-000419 ) + ( 3 N-000420 ) + ( 4 GND ) ) - ( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 - ( 1 N-000420 ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} + ( 1 3.3V ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 7 GND ) + ( 8 GND ) + ( 9 ? ) + ( 10 N-000419 ) + ( 11 N-000420 ) + ( 12 3.3V ) + ( 14 3.3V ) + ) + ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} + ( 1 /Ethernet_Phy/ETH_PLL1.8V ) + ( 2 N-000416 ) + ) + ( /4C4320F3/4C5D810A $noname L3 INDUCTOR {Lib=INDUCTOR} + ( 1 /Ethernet_Phy/ETH_A1.8V ) + ( 2 /Ethernet_Phy/ETH_PLL1.8V ) + ) + ( /4C4320F3/4C5D8104 $noname C6 C {Lib=C} + ( 1 /Ethernet_Phy/ETH_A1.8V ) + ( 2 N-000416 ) + ) + ( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR} + ( 1 N-000417 ) + ( 2 /Ethernet_Phy/ETH_A1.8V ) + ) + ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} + ( 1 N-000417 ) + ( 2 N-000416 ) + ) + ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} + ( 1 /Ethernet_Phy/ETH_1.8V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FB7 $noname L2 FB {Lib=INDUCTOR} + ( 1 3.3V ) + ( 2 /Ethernet_Phy/ETH_A3.3V ) + ) + ( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C} + ( 1 /Ethernet_Phy/ETH_A3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C} + ( 1 /Ethernet_Phy/ETH_A3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} + ( 1 /ETH_MDIO ) + ( 2 3.3V ) + ) + ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} + ( 1 N-000406 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C} + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} + ( 1 N-000400 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} + ( 1 N-000400 ) + ( 2 GND ) + ) + ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} + ( 1 /ETH_MDIO ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 ? ) + ( 7 3.3V ) + ( 8 GND ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 GND ) + ( 13 /Ethernet_Phy/ETH_1.8V ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ( 17 ? ) + ( 18 ? ) + ( 19 ? ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 GND ) + ( 24 3.3V ) + ( 25 /Ethernet_Phy/ETH_INT ) + ( 26 /Ethernet_Phy/ETH_LED0 ) + ( 27 /Ethernet_Phy/ETH_LED1 ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 /Ethernet_Phy/ETH_A1.8V ) + ( 32 N-000407 ) + ( 33 N-000399 ) + ( 34 ? ) + ( 35 GND ) + ( 36 GND ) + ( 37 N-000406 ) + ( 38 /Ethernet_Phy/ETH_A3.3V ) + ( 39 GND ) + ( 40 N-000408 ) + ( 41 N-000398 ) + ( 42 ? ) + ( 43 ? ) + ( 44 GND ) + ( 45 ? ) + ( 46 ? ) + ( 47 /Ethernet_Phy/ETH_PLL1.8V ) + ( 48 ? ) + ) + ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} + ( 1 3.3V ) + ( 2 N-000398 ) + ) + ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} + ( 1 3.3V ) + ( 2 N-000408 ) + ) + ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} + ( 1 3.3V ) + ( 2 N-000407 ) + ) + ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} + ( 1 3.3V ) + ( 2 N-000399 ) + ) + ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} + ( 1 N-000405 ) + ( 2 /Ethernet_Phy/ETH_LED1 ) + ) + ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} + ( 1 N-000396 ) + ( 2 /Ethernet_Phy/ETH_LED0 ) + ) + ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} + ( 1 N-000398 ) + ( 2 N-000408 ) + ( 3 3.3V ) + ( 4 GND ) + ( 5 GND ) + ( 6 3.3V ) + ( 7 N-000399 ) + ( 8 N-000407 ) + ( 9 3.3V ) + ( 10 N-000396 ) + ( 11 3.3V ) + ( 12 N-000405 ) + ( 13 N-000400 ) + ( 14 N-000400 ) + ) + ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} + ( CASE GND ) + ( COM GND ) + ( CD ? ) + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 ? ) + ( 7 ? ) + ( 8 ? ) + ) + ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 /Non_volatile_memories/FRB_N ) + ( 7 /Non_volatile_memories/FRB_N ) + ( 8 ? ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 3.3V ) + ( 13 GND ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ( 17 ? ) + ( 18 ? ) + ( 19 3.3V ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 ? ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 ? ) + ( 32 ? ) + ( 33 ? ) + ( 34 ? ) + ( 35 ? ) + ( 36 GND ) + ( 37 3.3V ) + ( 38 ? ) + ( 39 ? ) + ( 40 ? ) + ( 41 ? ) + ( 42 ? ) + ( 43 ? ) + ( 44 ? ) + ( 45 ? ) + ( 46 ? ) + ( 47 ? ) + ( 48 ? ) + ) + ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} + ( 1 N-000047 ) + ( 2 /FPGA_Spartan6/M1_DQ0 ) + ( 3 N-000047 ) + ( 4 /FPGA_Spartan6/M1_DQ1 ) + ( 5 ? ) + ( 6 GND ) + ( 7 ? ) + ( 8 ? ) + ( 9 N-000047 ) + ( 10 /DDR_Banks/M1_DQ5 ) + ( 11 /FPGA_Spartan6/M1_DQ6 ) + ( 12 GND ) + ( 13 /FPGA_Spartan6/M1_DQ7 ) + ( 14 ? ) + ( 15 N-000047 ) + ( 16 /DDR_Banks/M1_LDQS ) + ( 17 ? ) + ( 18 N-000047 ) + ( 19 ? ) + ( 20 /FPGA_Spartan6/M1_LDM ) + ( 21 /DDR_Banks/M1_WE# ) + ( 22 /FPGA_Spartan6/M1_CAS# ) + ( 23 /FPGA_Spartan6/M1_RAS# ) + ( 24 GND ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 /FPGA_Spartan6/M1_A10 ) + ( 29 /FPGA_Spartan6/M1_A0 ) + ( 30 /FPGA_Spartan6/M1_A1 ) + ( 31 /FPGA_Spartan6/M1_A2 ) + ( 32 /DDR_Banks/M1_A3 ) + ( 33 N-000047 ) + ( 34 GND ) + ( 35 /FPGA_Spartan6/M1_A4 ) + ( 36 /DDR_Banks/M1_A5 ) + ( 37 /DDR_Banks/M1_A6 ) + ( 38 /DDR_Banks/M1_A7 ) + ( 39 /FPGA_Spartan6/M1_A8 ) + ( 40 /FPGA_Spartan6/M1_A9 ) + ( 41 /FPGA_Spartan6/M1_A11 ) + ( 42 /DDR_Banks/M1_A12 ) + ( 43 ? ) + ( 44 /FPGA_Spartan6/M1_CLK# ) + ( 45 /FPGA_Spartan6/M1_CKE ) + ( 46 /FPGA_Spartan6/M1_CLK ) + ( 47 /DDR_Banks/M1_UDM ) + ( 48 GND ) + ( 49 ? ) + ( 50 ? ) + ( 51 /FPGA_Spartan6/M1_UDQS ) + ( 52 GND ) + ( 53 ? ) + ( 54 /DDR_Banks/M1_DQ8 ) + ( 55 N-000047 ) + ( 56 /FPGA_Spartan6/M1_DQ9 ) + ( 57 /DDR_Banks/M1_DQ10 ) + ( 58 GND ) + ( 59 /DDR_Banks/M1_DQ11 ) + ( 60 /FPGA_Spartan6/M1_DQ12 ) + ( 61 N-000047 ) + ( 62 /FPGA_Spartan6/M1_DQ13 ) + ( 63 /DDR_Banks/M1_DQ14 ) + ( 64 GND ) + ( 65 /DDR_Banks/M1_DQ15 ) + ( 66 GND ) + ) + ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} + ( 1 N-000054 ) + ( 2 /FPGA_Spartan6/M0_DQ0 ) + ( 3 N-000054 ) + ( 4 /FPGA_Spartan6/M0_DQ1 ) + ( 5 /FPGA_Spartan6/M0_DQ2 ) + ( 6 GND ) + ( 7 /DDR_Banks/M0_DQ3 ) + ( 8 /FPGA_Spartan6/M0_DQ4 ) + ( 9 N-000054 ) + ( 10 /FPGA_Spartan6/M0_DQ5 ) + ( 11 /FPGA_Spartan6/M0_DQ6 ) + ( 12 GND ) + ( 13 /FPGA_Spartan6/M0_DQ7 ) + ( 14 ? ) + ( 15 N-000054 ) + ( 16 /DDR_Banks/M0_LDQS ) + ( 17 ? ) + ( 18 N-000054 ) + ( 19 ? ) + ( 20 /DDR_Banks/M0_LDM ) + ( 21 /FPGA_Spartan6/M0_WE# ) + ( 22 /DDR_Banks/M0_CAS# ) + ( 23 /DDR_Banks/M0_RAS# ) + ( 24 GND ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 /DDR_Banks/M0_A10 ) + ( 29 /FPGA_Spartan6/M0_A0 ) + ( 30 /DDR_Banks/M0_A1 ) + ( 31 /FPGA_Spartan6/M0_A2 ) + ( 32 /FPGA_Spartan6/M0_A3 ) + ( 33 N-000054 ) + ( 34 GND ) + ( 35 /FPGA_Spartan6/M0_A4 ) + ( 36 /FPGA_Spartan6/M0_A5 ) + ( 37 /DDR_Banks/M0_A6 ) + ( 38 /DDR_Banks/M0_A7 ) + ( 39 /FPGA_Spartan6/M0_A8 ) + ( 40 /FPGA_Spartan6/M0_A9 ) + ( 41 /FPGA_Spartan6/M0_A11 ) + ( 42 /DDR_Banks/M0_A12 ) + ( 43 ? ) + ( 44 /DDR_Banks/M0_CLK# ) + ( 45 /FPGA_Spartan6/M0_CKE ) + ( 46 /FPGA_Spartan6/M0_CLK ) + ( 47 /FPGA_Spartan6/M0_UDM ) + ( 48 GND ) + ( 49 ? ) + ( 50 ? ) + ( 51 /DDR_Banks/M0_UDQS ) + ( 52 GND ) + ( 53 ? ) + ( 54 /DDR_Banks/M0_DQ8 ) + ( 55 N-000054 ) + ( 56 /FPGA_Spartan6/M0_DQ9 ) + ( 57 /DDR_Banks/M0_DQ10 ) + ( 58 GND ) + ( 59 /FPGA_Spartan6/M0_DQ11 ) + ( 60 /FPGA_Spartan6/M0_DQ12 ) + ( 61 N-000054 ) + ( 62 /FPGA_Spartan6/M0_DQ13 ) + ( 63 /FPGA_Spartan6/M0_DQ14 ) + ( 64 GND ) + ( 65 /FPGA_Spartan6/M0_DQ15 ) + ( 66 GND ) ) ) * { Allowed footprints by component: -$component C1 - SM* - C? - C1-1 +$component R10 + R? + SM0603 + SM0805 + R?-* $endlist -$component C2 - SM* - C? - C1-1 -$endlist -$component C3 - SM* - C? - C1-1 -$endlist -$component C4 - SM* - C? - C1-1 -$endlist -$component C5 - SM* - C? - C1-1 -$endlist -$component C6 - SM* - C? - C1-1 -$endlist -$component C7 - SM* - C? - C1-1 -$endlist -$component C8 - SM* - C? - C1-1 -$endlist -$component C9 - SM* - C? - C1-1 -$endlist -$component C10 - SM* - C? - C1-1 -$endlist -$component C11 - SM* - C? - C1-1 -$endlist -$component C12 - SM* - C? - C1-1 -$endlist -$component C13 - SM* - C? - C1-1 -$endlist -$component C14 +$component C16 SM* C? C1-1 @@ -976,7 +917,57 @@ $component C15 C? C1-1 $endlist -$component C16 +$component C14 + SM* + C? + C1-1 +$endlist +$component C13 + SM* + C? + C1-1 +$endlist +$component C9 + SM* + C? + C1-1 +$endlist +$component C6 + SM* + C? + C1-1 +$endlist +$component C4 + SM* + C? + C1-1 +$endlist +$component C2 + SM* + C? + C1-1 +$endlist +$component C8 + SM* + C? + C1-1 +$endlist +$component C7 + SM* + C? + C1-1 +$endlist +$component C5 + SM* + C? + C1-1 +$endlist +$component C3 + SM* + C? + C1-1 +$endlist +$component C1 SM* C? C1-1 @@ -993,6 +984,27 @@ $component R2 SM0805 R?-* $endlist +$component C11 + SM* + C? + C1-1 +$endlist +$component C10 + SM* + C? + C1-1 +$endlist +$component C12 + SM* + C? + C1-1 +$endlist +$component R9 + R? + SM0603 + SM0805 + R?-* +$endlist $component R3 R? SM0603 @@ -1005,19 +1017,13 @@ $component R4 SM0805 R?-* $endlist -$component R5 - R? - SM0603 - SM0805 - R?-* -$endlist $component R6 R? SM0603 SM0805 R?-* $endlist -$component R7 +$component R5 R? SM0603 SM0805 @@ -1029,13 +1035,7 @@ $component R8 SM0805 R?-* $endlist -$component R9 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R10 +$component R7 R? SM0603 SM0805 @@ -1043,3 +1043,559 @@ $component R10 $endlist $endfootprintlist } +{ Pin List by Nets +Net 5 "/Ethernet Phy/ETH_INT" "ETH_INT" + U4 25 + U1 A5 +Net 6 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" + U3 22 + U1 H22 +Net 7 "/FPGA Spartan6/M1_CKE" "M1_CKE" + U1 D21 + U3 45 +Net 8 "/FPGA Spartan6/M1_CLK" "M1_CLK" + U1 H20 + U3 46 +Net 9 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" + U3 44 + U1 J19 +Net 10 "GND" "GND" + U3 58 + U2 6 + U2 66 + U2 48 + U2 58 + J1 COM + J1 CASE + J1 CASE + J1 CASE + U5 13 + U5 36 + U2 12 + U2 52 + U2 24 + U2 34 + U2 64 + U3 48 + U4 35 + U4 36 + U4 39 + U4 12 + U4 23 + U4 44 + J4 5 + J4 4 + C2 2 + C16 2 + V1 2 + V2 2 + J5 4 + C15 2 + C14 2 + C13 2 + U6 7 + U6 8 + R10 2 + R2 2 + C11 2 + C10 2 + C12 2 + R9 2 + U4 8 + C1 2 + C3 2 + C5 2 + C7 2 + C8 2 + U1 B13 + U1 J13 + U1 L13 + U1 N13 + U1 K14 + U1 J21 + U1 N21 + U1 U21 + U1 AB1 + U1 M12 + U1 P12 + U1 A22 + U1 W16 + U1 R5 + U1 E7 + U1 H7 + U1 U7 + U1 W7 + U1 A1 + U1 E2 + U1 J2 + U1 M10 + U1 P10 + U1 V10 + U1 J11 + U1 L11 + U1 N11 + U1 E21 + U1 B9 + U1 J9 + U1 L9 + U1 N9 + U1 K10 + U1 B17 + U1 N17 + U1 D18 + U1 G18 + U1 L18 + U1 R18 + U1 W19 + U1 AA9 + U1 AB22 + U1 AA13 + U1 AA17 + U1 M14 + U1 P14 + U1 V14 + U1 E15 + U1 J15 + U1 AA5 + U1 N2 + U1 U2 + U1 D4 + U1 V4 + U1 B5 + U1 G5 + U1 L5 + U3 24 + U3 34 + U3 64 + U3 66 + U3 6 + U3 12 + U3 52 +Net 11 "/DDR Banks/M0_CLK#" "M0_CLK#" + U1 H3 + U2 44 +Net 12 "/FPGA Spartan6/M0_CLK" "M0_CLK" + U2 46 + U1 H4 +Net 13 "/FPGA Spartan6/M0_CKE" "M0_CKE" + U2 45 + U1 D2 +Net 14 "/DDR Banks/M0_CAS#" "M0_CAS#" + U1 K4 + U2 22 +Net 15 "/DDR Banks/M1_WE#" "M1_WE#" + U3 21 + U1 H19 +Net 16 "/DDR Banks/M0_RAS#" "M0_RAS#" + U1 K5 + U2 23 +Net 17 "/FPGA Spartan6/M0_WE#" "M0_WE#" + U1 F2 + U2 21 +Net 18 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" + U1 H21 + U3 23 +Net 26 "/FPGA Spartan6/M1_LDM" "M1_LDM" + U1 L19 + U3 20 +Net 27 "/DDR Banks/M1_LDQS" "M1_LDQS" + U1 L20 + U3 16 +Net 28 "/DDR Banks/M1_UDM" "M1_UDM" + U1 M20 + U3 47 +Net 29 "/FPGA Spartan6/M0_UDM" "M0_UDM" + U1 M3 + U2 47 +Net 30 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" + U3 51 + U1 T21 +Net 31 "/DDR Banks/M0_UDQS" "M0_UDQS" + U1 T2 + U2 51 +Net 32 "/DDR Banks/M0_LDM" "M0_LDM" + U1 L4 + U2 20 +Net 33 "/DDR Banks/M0_LDQS" "M0_LDQS" + U1 L3 + U2 16 +Net 36 "/ETH_MDIO" "ETH_MDIO" + U4 1 + R1 1 +Net 47 "" "" + U3 9 + U3 55 + U3 15 + U3 1 + U3 3 + U3 61 + U3 18 + U3 33 +Net 54 "" "" + U2 61 + U2 33 + U2 18 + U2 15 + U2 3 + U2 1 + U2 55 + U2 9 +Net 117 "/Non volatile memories/FRB_N" "FRB_N" + U5 6 + U5 7 +Net 122 "3.3V" "3.3V" + C1 1 + C3 1 + U6 12 + C5 1 + U6 14 + R1 2 + J4 3 + U4 7 + C14 1 + L2 1 + C15 1 + C10 1 + C11 1 + U5 12 + U5 19 + U5 37 + C13 1 + R3 1 + U4 24 + J4 6 + J4 9 + J4 11 + U6 1 + R5 1 + R6 1 + R4 1 +Net 137 "" "" + U1 B4 + U1 B11 + U1 G10 + U1 B19 + U1 E17 + U1 E13 + U1 G14 + U1 E9 + U1 B15 + U1 B7 +Net 153 "" "" + U1 R2 + U1 L2 + U1 G2 + U1 C2 + U1 F4 + U1 N5 + U1 U5 + U1 F6 + U1 J5 + U1 L7 + U1 W2 +Net 154 "" "" + U1 AA19 + U1 AA11 + U1 AA15 + U1 AA7 + U1 AA3 + U1 T13 + U1 V12 + U1 V16 + U1 V8 + U1 W5 + U1 T9 +Net 155 "" "" + U1 U18 + U1 E19 + U1 L16 + U1 R21 + U1 W21 + U1 L21 + U1 G21 + U1 C21 + U1 J18 + U1 N18 +Net 156 "" "" + U1 K13 + U1 M13 + U1 P13 + U1 J14 + U1 J12 + U1 L12 + U1 N12 + U1 R14 + U1 L14 + U1 N14 + U1 L10 + U1 J10 + U1 P9 + U1 M9 + U1 K9 + U1 J8 + U1 P11 + U1 M11 + U1 K11 + U1 N10 +Net 157 "" "" + U1 R12 + U1 D16 + U1 M15 + U1 H9 + U1 N8 + U1 L8 + U1 U11 + U1 K15 + U1 H15 + U1 F11 + U1 R10 + U1 V6 + U1 R6 + U1 G12 +Net 396 "" "" + R7 1 + J4 10 +Net 397 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + R7 2 + U4 26 +Net 398 "" "" + U4 41 + R3 2 + J4 1 +Net 399 "" "" + J4 7 + R5 2 + U4 33 +Net 400 "" "" + C12 1 + R9 1 + J4 14 + J4 13 +Net 401 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" + C2 1 + U4 13 +Net 402 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + C9 1 + L3 2 + U4 47 +Net 403 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + U4 38 + C7 1 + C8 1 + L2 2 +Net 404 "/Ethernet Phy/ETH_LED1" "ETH_LED1" + R8 2 + U4 27 +Net 405 "" "" + R8 1 + J4 12 +Net 406 "" "" + R2 1 + U4 37 +Net 407 "" "" + R6 2 + U4 32 + J4 8 +Net 408 "" "" + R4 2 + J4 2 + U4 40 +Net 416 "" "" + C4 2 + C6 2 + C9 2 +Net 417 "" "" + L1 1 + C4 1 +Net 418 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + L3 1 + C6 1 + U4 31 + L1 2 +Net 419 "" "" + J5 2 + V2 1 + V2 1 + U6 10 +Net 420 "" "" + V1 1 + V1 1 + U6 11 + J5 3 +Net 425 "" "" + J5 1 + F1 1 +Net 426 "" "" + J5 S1 + R10 1 + C16 1 + J5 S2 + J5 S3 + J5 S4 +Net 438 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" + U1 N3 + U2 2 +Net 442 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" + U3 2 + U1 N20 +Net 443 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" + U3 4 + U1 N22 +Net 447 "/DDR Banks/M1_DQ5" "M1_DQ5" + U1 J22 + U3 10 +Net 448 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" + U3 11 + U1 K21 +Net 449 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" + U3 13 + U1 K22 +Net 450 "/DDR Banks/M1_DQ8" "M1_DQ8" + U1 P21 + U3 54 +Net 451 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" + U3 56 + U1 P22 +Net 452 "/DDR Banks/M1_DQ10" "M1_DQ10" + U1 R20 + U3 57 +Net 453 "/DDR Banks/M1_DQ15" "M1_DQ15" + U3 65 + U1 V22 +Net 454 "/DDR Banks/M1_DQ14" "M1_DQ14" + U3 63 + U1 V21 +Net 455 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" + U3 62 + U1 U22 +Net 456 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" + U1 U20 + U3 60 +Net 457 "/DDR Banks/M1_DQ11" "M1_DQ11" + U1 R22 + U3 59 +Net 458 "/FPGA Spartan6/M1_A0" "M1_A0" + U3 29 + U1 F21 +Net 459 "/FPGA Spartan6/M1_A1" "M1_A1" + U3 30 + U1 F22 +Net 460 "/FPGA Spartan6/M1_A2" "M1_A2" + U1 E22 + U3 31 +Net 461 "/DDR Banks/M1_A3" "M1_A3" + U1 G20 + U3 32 +Net 462 "/FPGA Spartan6/M1_A4" "M1_A4" + U1 F20 + U3 35 +Net 463 "/DDR Banks/M1_A5" "M1_A5" + U1 K20 + U3 36 +Net 464 "/DDR Banks/M1_A6" "M1_A6" + U1 K19 + U3 37 +Net 465 "/DDR Banks/M1_A7" "M1_A7" + U1 E20 + U3 38 +Net 466 "/FPGA Spartan6/M1_A8" "M1_A8" + U3 39 + U1 C20 +Net 467 "/FPGA Spartan6/M1_A9" "M1_A9" + U1 C22 + U3 40 +Net 468 "/FPGA Spartan6/M1_A10" "M1_A10" + U1 G19 + U3 28 +Net 469 "/FPGA Spartan6/M1_A11" "M1_A11" + U1 F19 + U3 41 +Net 470 "/DDR Banks/M1_A12" "M1_A12" + U3 42 + U1 D22 +Net 471 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" + U1 N1 + U2 4 +Net 472 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" + U1 M2 + U2 5 +Net 473 "/DDR Banks/M0_DQ3" "M0_DQ3" + U1 M1 + U2 7 +Net 474 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" + U1 J3 + U2 8 +Net 475 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" + U2 10 + U1 J1 +Net 476 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" + U2 11 + U1 K2 +Net 477 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" + U1 K1 + U2 13 +Net 478 "/DDR Banks/M0_DQ8" "M0_DQ8" + U1 P2 + U2 54 +Net 479 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" + U1 P1 + U2 56 +Net 480 "/DDR Banks/M0_DQ10" "M0_DQ10" + U2 57 + U1 R3 +Net 481 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" + U1 R1 + U2 59 +Net 482 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" + U2 60 + U1 U3 +Net 483 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" + U2 62 + U1 U1 +Net 484 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" + U2 63 + U1 V2 +Net 485 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" + U1 V1 + U2 65 +Net 486 "/DDR Banks/M0_A12" "M0_A12" + U2 42 + U1 D1 +Net 487 "/FPGA Spartan6/M0_A11" "M0_A11" + U1 C1 + U2 41 +Net 488 "/DDR Banks/M0_A10" "M0_A10" + U2 28 + U1 G4 +Net 489 "/FPGA Spartan6/M0_A9" "M0_A9" + U2 40 + U1 E1 +Net 490 "/FPGA Spartan6/M0_A8" "M0_A8" + U1 E3 + U2 39 +Net 491 "/DDR Banks/M0_A7" "M0_A7" + U2 38 + U1 H6 +Net 492 "/DDR Banks/M0_A6" "M0_A6" + U1 J4 + U2 37 +Net 493 "/FPGA Spartan6/M0_A5" "M0_A5" + U2 36 + U1 K3 +Net 494 "/FPGA Spartan6/M0_A4" "M0_A4" + U2 35 + U1 F3 +Net 495 "/FPGA Spartan6/M0_A3" "M0_A3" + U2 32 + U1 K6 +Net 496 "/FPGA Spartan6/M0_A2" "M0_A2" + U1 H5 + U2 31 +Net 497 "/DDR Banks/M0_A1" "M0_A1" + U2 30 + U1 H1 +Net 498 "/FPGA Spartan6/M0_A0" "M0_A0" + U1 H2 + U2 29 +} +#End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 20b006a..8732c46 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Mon 09 Aug 2010 09:51:02 PM COT +update=Mon 09 Aug 2010 10:24:04 PM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 013b4fa..822f7be 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 09:53:48 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001