diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index a8bfc8b..f2c6482 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -500,37 +500,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR018 +L GND #PWR020 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR018" H 6900 6200 30 0001 C CNN +F 0 "#PWR020" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR019 +L +2.5V #PWR021 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR019" H 6900 5750 20 0001 C CNN +F 0 "#PWR021" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR020 +L +2.5V #PWR022 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR020" H 1700 5750 20 0001 C CNN +F 0 "#PWR022" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR021 +L GND #PWR023 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR021" H 1700 6200 30 0001 C CNN +F 0 "#PWR023" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -546,19 +546,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR022 +L +2.5V #PWR024 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR022" H 3050 1700 20 0001 C CNN +F 0 "#PWR024" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR023 +L +2.5V #PWR025 U 1 1 4C61CFC6 P 8300 1750 -F 0 "#PWR023" H 8300 1700 20 0001 C CNN +F 0 "#PWR025" H 8300 1700 20 0001 C CNN F 1 "+2.5V" H 8300 1850 30 0000 C CNN 1 8300 1750 1 0 0 -1 @@ -624,37 +624,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR024 +L +2.5V #PWR026 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR024" H 8300 5700 20 0001 C CNN +F 0 "#PWR026" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR025 +L GND #PWR027 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR025" H 8300 6350 30 0001 C CNN +F 0 "#PWR027" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR026 +L GND #PWR028 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR026" H 3050 6350 30 0001 C CNN +F 0 "#PWR028" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR027 +L +2.5V #PWR029 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR027" H 3050 5700 20 0001 C CNN +F 0 "#PWR029" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -740,19 +740,19 @@ F 2 "0402" H 9850 1850 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR028 +L +2.5V #PWR030 U 1 1 4C61CE2F P 9850 1000 -F 0 "#PWR028" H 9850 950 20 0001 C CNN +F 0 "#PWR030" H 9850 950 20 0001 C CNN F 1 "+2.5V" H 9850 1100 30 0000 C CNN 1 9850 1000 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR029 +L +2.5V #PWR031 U 1 1 4C61CDF1 P 4550 900 -F 0 "#PWR029" H 4550 850 20 0001 C CNN +F 0 "#PWR031" H 4550 850 20 0001 C CNN F 1 "+2.5V" H 4550 1000 30 0000 C CNN 1 4550 900 1 0 0 -1 @@ -844,10 +844,10 @@ $EndComp Text HLabel 4950 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR030 +L GND #PWR032 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR030" H 3000 5200 30 0001 C CNN +F 0 "#PWR032" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1141,10 +1141,10 @@ Entry Wire Line Entry Wire Line 9950 3650 10050 3750 $Comp -L GND #PWR031 +L GND #PWR033 U 1 1 4C437C3F P 8250 5200 -F 0 "#PWR031" H 8250 5200 30 0001 C CNN +F 0 "#PWR033" H 8250 5200 30 0001 C CNN F 1 "GND" H 8250 5130 30 0001 C CNN 1 8250 5200 1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 0d29eea..efaf2b3 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -55,6 +55,26 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Text HLabel 18600 10150 2 60 BiDi ~ 0 +ND_D[0..7] +Wire Bus Line + 18600 10150 18300 10150 +Wire Wire Line + 17600 10850 18200 10850 +Wire Wire Line + 18200 10650 17600 10650 +Wire Wire Line + 17600 10750 18200 10750 +Wire Wire Line + 17600 10950 18200 10950 +Wire Wire Line + 17600 10550 18200 10550 +Wire Wire Line + 17600 10350 18200 10350 +Wire Wire Line + 18200 10250 17600 10250 +Wire Wire Line + 17600 10450 18200 10450 Wire Wire Line 14200 10750 14150 10750 Connection ~ 15850 8300 @@ -63,13 +83,13 @@ Wire Wire Line Wire Wire Line 14050 12900 14050 13050 Wire Bus Line - 18400 9350 18300 9350 + 18400 8850 18300 8850 Wire Wire Line - 17600 9650 18200 9650 + 17600 9150 18200 9150 Wire Wire Line - 18200 9450 17600 9450 + 18200 8950 17600 8950 Wire Wire Line - 17600 9350 17750 9350 + 17600 8850 17750 8850 Wire Bus Line 13300 3750 13400 3750 Wire Bus Line @@ -101,11 +121,11 @@ Wire Wire Line Wire Wire Line 14150 8850 14200 8850 Wire Wire Line - 17600 9150 17700 9150 + 18300 1750 18400 1750 Wire Wire Line - 17600 8950 17700 8950 + 18300 1550 18400 1550 Wire Wire Line - 17700 8750 17600 8750 + 18400 1350 18300 1350 Wire Bus Line 12800 10200 12800 9800 Wire Bus Line @@ -806,9 +826,9 @@ Wire Wire Line Wire Bus Line 12800 9000 12800 9400 Wire Wire Line - 17600 8850 17700 8850 + 18300 1450 18400 1450 Wire Wire Line - 17600 9050 17700 9050 + 18300 1650 18400 1650 Wire Wire Line 14150 8750 14200 8750 Wire Wire Line @@ -838,17 +858,51 @@ Wire Bus Line Wire Wire Line 13900 3850 13500 3850 Wire Wire Line - 17600 9250 17750 9250 + 17600 8750 17750 8750 Wire Wire Line - 17600 9550 18200 9550 + 17600 9050 18200 9050 Wire Wire Line - 17600 9750 18200 9750 + 17600 9250 18200 9250 Wire Bus Line - 18300 9350 18300 9650 + 18300 8850 18300 9150 Wire Wire Line 12550 12900 12550 13050 Wire Wire Line 14200 10650 14150 10650 +Wire Bus Line + 18300 10150 18300 10850 +Text Label 18200 10950 2 60 ~ 0 +NF_D7 +Text Label 18200 10850 2 60 ~ 0 +NF_D6 +Text Label 18200 10750 2 60 ~ 0 +NF_D5 +Text Label 18200 10650 2 60 ~ 0 +NF_D4 +Entry Wire Line + 18200 10950 18300 10850 +Entry Wire Line + 18200 10850 18300 10750 +Entry Wire Line + 18200 10750 18300 10650 +Entry Wire Line + 18200 10650 18300 10550 +Entry Wire Line + 18200 10250 18300 10150 +Entry Wire Line + 18200 10350 18300 10250 +Entry Wire Line + 18200 10450 18300 10350 +Entry Wire Line + 18200 10550 18300 10450 +Text Label 18200 10250 2 60 ~ 0 +NF_D0 +Text Label 18200 10350 2 60 ~ 0 +NF_D1 +Text Label 18200 10450 2 60 ~ 0 +NF_D2 +Text Label 18200 10550 2 60 ~ 0 +NF_D3 Text HLabel 14150 10750 0 60 BiDi ~ 0 ETH_COL Text HLabel 14150 10650 0 60 BiDi ~ 0 @@ -898,27 +952,27 @@ F 1 "+2.5V" H 5300 750 30 0000 C CNN 1 5300 650 1 0 0 -1 $EndComp -Text Label 18200 9750 2 60 ~ 0 +Text Label 18200 9250 2 60 ~ 0 SD_DAT3 -Text Label 18200 9650 2 60 ~ 0 +Text Label 18200 9150 2 60 ~ 0 SD_DAT2 -Text Label 18200 9550 2 60 ~ 0 +Text Label 18200 9050 2 60 ~ 0 SD_DAT1 -Text Label 18200 9450 2 60 ~ 0 +Text Label 18200 8950 2 60 ~ 0 SD_DAT0 Entry Wire Line - 18200 9750 18300 9650 + 18200 9250 18300 9150 Entry Wire Line - 18200 9650 18300 9550 + 18200 9150 18300 9050 Entry Wire Line - 18200 9550 18300 9450 + 18200 9050 18300 8950 Entry Wire Line - 18200 9450 18300 9350 -Text HLabel 17750 9350 2 60 BiDi ~ 0 + 18200 8950 18300 8850 +Text HLabel 17750 8850 2 60 BiDi ~ 0 SD_CLK -Text HLabel 17750 9250 2 60 BiDi ~ 0 +Text HLabel 17750 8750 2 60 BiDi ~ 0 SD_CMD -Text HLabel 18400 9350 2 60 BiDi ~ 0 +Text HLabel 18400 8850 2 60 BiDi ~ 0 SD_DAT[0..3] Entry Wire Line 13400 3850 13500 3950 @@ -956,15 +1010,15 @@ F 1 "GND" H 1600 5880 30 0001 C CNN 1 1600 5950 -1 0 0 -1 $EndComp -Text HLabel 17700 9150 2 60 BiDi ~ 0 +Text HLabel 18400 1750 2 60 BiDi ~ 0 USBA_VM -Text HLabel 17700 9050 2 60 BiDi ~ 0 +Text HLabel 18400 1650 2 60 BiDi ~ 0 USBA_VP -Text HLabel 17700 8950 2 60 BiDi ~ 0 +Text HLabel 18400 1550 2 60 BiDi ~ 0 USBA_RCV -Text HLabel 17700 8850 2 60 BiDi ~ 0 +Text HLabel 18400 1450 2 60 BiDi ~ 0 USBA_OE_N -Text HLabel 17700 8750 2 60 BiDi ~ 0 +Text HLabel 18400 1350 2 60 BiDi ~ 0 USBA_SPD Text HLabel 14150 10550 0 60 BiDi ~ 0 ETH_CLK diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 2fccd0d..86598a6 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -55,155 +55,177 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Text HLabel 1250 5500 0 60 BiDi ~ 0 -SD_DAT[0..3] +Text HLabel 8450 2400 2 60 BiDi ~ 0 +NF_D[0..7] Wire Bus Line - 1250 5500 1650 5500 + 8450 2400 8250 2400 Wire Bus Line - 1650 5500 1650 5900 + 8250 2400 8250 3200 Wire Wire Line - 3100 5450 3100 5800 + 7850 2700 8150 2700 Wire Wire Line - 3100 5800 3200 5800 + 7850 2650 8150 2650 Wire Wire Line - 3200 5750 2800 5750 + 7850 2550 8150 2550 Wire Wire Line - 3200 5650 2800 5650 + 7850 2600 8150 2600 Wire Wire Line - 3200 5600 2800 5600 -Connection ~ 4400 5850 + 7850 3200 8150 3200 Wire Wire Line - 4400 5950 4400 5750 -Connection ~ 4400 5800 + 7850 3150 8150 3150 Wire Wire Line - 4300 5800 4400 5800 -Connection ~ 7400 4900 + 7850 3250 8150 3250 Wire Wire Line - 7400 4800 7400 5000 + 7850 3300 8150 3300 Wire Wire Line - 8200 4800 8200 4900 -Wire Wire Line - 8200 4900 7400 4900 -Wire Wire Line - 8200 4400 8200 4300 -Wire Wire Line - 8200 4300 7400 4300 -Wire Wire Line - 8200 3300 7850 3300 -Wire Wire Line - 8200 3200 7850 3200 -Wire Wire Line - 8200 2650 7850 2650 -Wire Wire Line - 8200 2600 7850 2600 -Wire Wire Line - 6550 2650 6550 2550 -Wire Wire Line - 6850 2650 6850 2600 -Wire Wire Line - 6850 2900 7050 2900 -Wire Wire Line - 6850 3200 7050 3200 -Wire Wire Line - 6850 3100 7050 3100 -Wire Wire Line - 6850 2750 7050 2750 -Wire Wire Line - 6850 2600 7050 2600 -Wire Wire Line - 7050 2700 6850 2700 -Wire Wire Line - 6850 3150 7050 3150 -Wire Wire Line - 6850 3250 7050 3250 -Wire Wire Line - 7850 2900 8000 2900 -Wire Wire Line - 6850 2950 7050 2950 -Wire Wire Line - 7850 2950 8000 2950 -Connection ~ 6850 2650 -Wire Wire Line - 7050 2650 6450 2650 -Connection ~ 6550 2650 -Wire Wire Line - 8200 2550 7850 2550 -Wire Wire Line - 8200 3150 7850 3150 -Wire Wire Line - 8200 2700 7850 2700 -Wire Wire Line - 8200 3250 7850 3250 -Wire Wire Line - 7800 4400 7800 4300 -Connection ~ 7800 4300 -Wire Wire Line - 7800 4800 7800 4900 -Connection ~ 7800 4900 -Wire Wire Line - 7400 4400 7400 4200 -Connection ~ 7400 4300 -Wire Wire Line - 3200 5700 3050 5700 -Wire Wire Line - 4400 5850 4300 5850 -Wire Wire Line - 4400 5750 4300 5750 -Connection ~ 4400 5750 -Wire Wire Line - 4000 3000 4200 3000 -Wire Wire Line - 4000 2900 4200 2900 -Wire Wire Line - 4000 2800 4200 2800 -Wire Wire Line - 4000 2600 4200 2600 -Wire Wire Line - 4000 2500 4200 2500 -Wire Wire Line - 4000 2400 4200 2400 -Wire Wire Line - 4000 2300 4200 2300 -Wire Wire Line - 4200 2350 4000 2350 -Wire Wire Line - 4200 2450 4000 2450 -Wire Wire Line - 4200 2550 4000 2550 -Wire Wire Line - 4200 2650 4000 2650 -Wire Wire Line - 4200 2750 4000 2750 -Wire Wire Line - 4200 2850 4000 2850 -Wire Wire Line - 4200 2950 4000 2950 -Wire Wire Line - 4200 3050 4000 3050 -Wire Wire Line - 4000 2700 4200 2700 -Wire Bus Line - 4300 2400 4300 3200 -Wire Bus Line - 4300 3200 4350 3200 -Wire Wire Line - 3950 6300 3950 6200 -Wire Wire Line - 3050 5700 3050 6150 -Wire Wire Line - 3200 5900 2800 5900 -Wire Wire Line - 3200 5850 2800 5850 -Wire Wire Line - 3200 5950 2800 5950 -Wire Wire Line - 1750 5700 2200 5700 -Wire Wire Line - 1750 5800 2200 5800 + 1750 5900 2200 5900 Wire Wire Line 1750 6000 2200 6000 Wire Wire Line - 1750 5900 2200 5900 + 1750 5800 2200 5800 +Wire Wire Line + 1750 5700 2200 5700 +Wire Wire Line + 3200 5950 2800 5950 +Wire Wire Line + 3200 5850 2800 5850 +Wire Wire Line + 3200 5900 2800 5900 +Wire Wire Line + 3050 6150 3050 5700 +Wire Wire Line + 3950 6300 3950 6200 +Connection ~ 4400 5750 +Wire Wire Line + 4300 5750 4400 5750 +Wire Wire Line + 4400 5850 4300 5850 +Wire Wire Line + 3050 5700 3200 5700 +Connection ~ 7400 4300 +Wire Wire Line + 7400 4400 7400 4200 +Connection ~ 7800 4900 +Wire Wire Line + 7800 4800 7800 4900 +Connection ~ 7800 4300 +Wire Wire Line + 7800 4400 7800 4300 +Connection ~ 6550 2650 +Wire Wire Line + 7050 2650 6450 2650 +Connection ~ 6850 2650 +Wire Wire Line + 6850 2950 7050 2950 +Wire Wire Line + 6850 3250 7050 3250 +Wire Wire Line + 6850 3150 7050 3150 +Wire Wire Line + 7050 2700 6850 2700 +Wire Wire Line + 7050 2600 6850 2600 +Wire Wire Line + 6850 2750 7050 2750 +Wire Wire Line + 6850 3100 7050 3100 +Wire Wire Line + 6850 3200 7050 3200 +Wire Wire Line + 6850 2900 7050 2900 +Wire Wire Line + 6850 2600 6850 2650 +Wire Wire Line + 6550 2650 6550 2550 +Wire Wire Line + 7400 4300 8200 4300 +Wire Wire Line + 8200 4300 8200 4400 +Wire Wire Line + 7400 4900 8200 4900 +Wire Wire Line + 8200 4900 8200 4800 +Wire Wire Line + 7400 4800 7400 5000 +Connection ~ 7400 4900 +Wire Wire Line + 4300 5800 4400 5800 +Connection ~ 4400 5800 +Wire Wire Line + 4400 5750 4400 5950 +Connection ~ 4400 5850 +Wire Wire Line + 3200 5600 2800 5600 +Wire Wire Line + 3200 5650 2800 5650 +Wire Wire Line + 3200 5750 2800 5750 +Wire Wire Line + 3200 5800 3100 5800 +Wire Wire Line + 3100 5800 3100 5450 +Wire Bus Line + 1650 5900 1650 5500 +Wire Bus Line + 1650 5500 1250 5500 +Wire Wire Line + 7850 2950 7950 2950 +Wire Wire Line + 7950 2950 7950 3000 +Wire Wire Line + 7850 2900 7950 2900 +Entry Wire Line + 8150 2700 8250 2600 +Entry Wire Line + 8150 2650 8250 2550 +Entry Wire Line + 8150 2550 8250 2450 +Entry Wire Line + 8150 2600 8250 2500 +Entry Wire Line + 8150 3300 8250 3200 +Entry Wire Line + 8150 3250 8250 3150 +Entry Wire Line + 8150 3200 8250 3100 +Entry Wire Line + 8150 3150 8250 3050 +$Comp +L +3.3V #PWR015 +U 1 1 4C646C14 +P 7950 2900 +F 0 "#PWR015" H 7950 2860 30 0001 C CNN +F 1 "+3.3V" H 7950 3010 30 0000 C CNN + 1 7950 2900 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR016 +U 1 1 4C646BEA +P 7950 3000 +F 0 "#PWR016" H 7950 3000 30 0001 C CNN +F 1 "GND" H 7950 2930 30 0001 C CNN + 1 7950 3000 + 1 0 0 -1 +$EndComp +Text Label 7950 2700 0 30 ~ 0 +NF_D4 +Text Label 7950 2650 0 30 ~ 0 +NF_D5 +Text Label 7950 2550 0 30 ~ 0 +NF_D7 +Text Label 7950 2600 0 30 ~ 0 +NF_D6 +Text Label 7950 3200 0 30 ~ 0 +NF_D2 +Text Label 7950 3150 0 30 ~ 0 +NF_D3 +Text Label 7950 3250 0 30 ~ 0 +NF_D1 +Text Label 7950 3300 0 30 ~ 0 +NF_D0 +Text HLabel 1250 5500 0 60 BiDi ~ 0 +SD_DAT[0..3] Text Label 1800 5900 0 60 ~ 0 SD_DAT2 Text Label 1800 6000 0 60 ~ 0 @@ -231,10 +253,10 @@ SD_DAT3 Text Label 2800 5850 0 30 ~ 0 SD_CMD $Comp -L GND #PWR015 +L GND #PWR017 U 1 1 4C61D875 P 3050 6150 -F 0 "#PWR015" H 3050 6150 30 0001 C CNN +F 0 "#PWR017" H 3050 6150 30 0001 C CNN F 1 "GND" H 3050 6080 30 0001 C CNN 1 3050 6150 1 0 0 -1 @@ -246,116 +268,46 @@ SD_DAT0 Text Label 2800 5600 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR016 +L GND #PWR018 U 1 1 4C438ADC P 4400 5950 -F 0 "#PWR016" H 4400 5950 30 0001 C CNN +F 0 "#PWR018" H 4400 5950 30 0001 C CNN F 1 "GND" H 4400 5880 30 0001 C CNN 1 4400 5950 1 0 0 -1 $EndComp $Comp -L GND #PWR017 +L GND #PWR019 U 1 1 4C438AD5 P 3950 6300 -F 0 "#PWR017" H 3950 6300 30 0001 C CNN +F 0 "#PWR019" H 3950 6300 30 0001 C CNN F 1 "GND" H 3950 6230 30 0001 C CNN 1 3950 6300 1 0 0 -1 $EndComp -Text GLabel 8000 2950 2 20 BiDi ~ 0 -GND Text GLabel 6850 2950 0 20 BiDi ~ 0 GND Text GLabel 7400 5000 1 20 BiDi ~ 0 GND NoConn ~ 7050 2800 -Text HLabel 4350 3200 2 20 BiDi ~ 0 -D[0..15] -Entry Wire Line - 4200 3050 4300 3150 -Entry Wire Line - 4200 3000 4300 3100 -Entry Wire Line - 4200 2950 4300 3050 -Entry Wire Line - 4200 2900 4300 3000 -Entry Wire Line - 4200 2850 4300 2950 -Entry Wire Line - 4200 2800 4300 2900 -Entry Wire Line - 4200 2750 4300 2850 -Entry Wire Line - 4200 2700 4300 2800 -Entry Wire Line - 4200 2650 4300 2750 -Entry Wire Line - 4200 2600 4300 2700 -Entry Wire Line - 4200 2550 4300 2650 -Entry Wire Line - 4200 2500 4300 2600 -Entry Wire Line - 4200 2450 4300 2550 -Entry Wire Line - 4200 2400 4300 2500 -Entry Wire Line - 4200 2350 4300 2450 -Entry Wire Line - 4200 2300 4300 2400 -Text Label 4000 2700 0 20 ~ 0 -D8 -Text Label 4000 3050 0 20 ~ 0 -D15 -Text Label 4000 3000 0 20 ~ 0 -D14 -Text Label 4000 2950 0 20 ~ 0 -D13 -Text Label 4000 2900 0 20 ~ 0 -D12 -Text Label 4000 2850 0 20 ~ 0 -D11 -Text Label 4000 2800 0 20 ~ 0 -D10 -Text Label 4000 2750 0 20 ~ 0 -D9 -Text Label 4000 2650 0 20 ~ 0 -D7 -Text Label 4000 2600 0 20 ~ 0 -D6 -Text Label 4000 2550 0 20 ~ 0 -D5 -Text Label 4000 2500 0 20 ~ 0 -D4 -Text Label 4000 2450 0 20 ~ 0 -D3 -Text Label 4000 2400 0 20 ~ 0 -D2 -Text Label 4000 2350 0 20 ~ 0 -D1 -Text Label 4000 2300 0 20 ~ 0 -D0 Text GLabel 7400 4200 3 20 BiDi ~ 0 3.3V -Text GLabel 8000 2900 2 20 BiDi ~ 0 -3.3V Text GLabel 6850 2900 0 20 BiDi ~ 0 3.3V Text GLabel 6850 3250 0 20 BiDi ~ 0 3.3V Text HLabel 6850 3200 0 20 BiDi ~ 0 -FWE_N +NF_WE_N Text HLabel 6850 3150 0 20 BiDi ~ 0 NF_ALE Text HLabel 6850 3100 0 20 BiDi ~ 0 NF_CLE Text HLabel 6850 2750 0 20 BiDi ~ 0 -CS1_N +NF_CS1_N Text HLabel 6850 2700 0 20 BiDi ~ 0 -FRE_N +NF_RE_N Text HLabel 6450 2650 0 20 BiDi ~ 0 -FRB_N +NF_RNB $Comp L MICROSD J1 U 1 1 4B76F5E2 @@ -365,22 +317,6 @@ F 1 "MICROSD" H 3350 6250 60 0000 C CNN 1 2950 6150 1 0 0 -1 $EndComp -Text Label 8200 2550 0 20 ~ 0 -D7 -Text Label 8200 2600 0 20 ~ 0 -D6 -Text Label 8200 2650 0 20 ~ 0 -D5 -Text Label 8200 2700 0 20 ~ 0 -D4 -Text Label 8200 3150 0 20 ~ 0 -D3 -Text Label 8200 3200 0 20 ~ 0 -D2 -Text Label 8200 3250 0 20 ~ 0 -D1 -Text Label 8200 3300 0 20 ~ 0 -D0 NoConn ~ 7850 2350 NoConn ~ 7850 2400 NoConn ~ 7850 2450 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 6f07d4a..572976f 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 59a5ddd..895ea77 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 59d797c..8ae8b00 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Thu 12 Aug 2010 08:51:39 AM COT +EESchema-LIBRARY Version 2.3 Date: Thu 12 Aug 2010 05:12:17 PM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index c6c1f7f..f322bc5 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,66 +1,66 @@ -# EESchema Netlist Version 1.1 created Thu 12 Aug 2010 08:51:33 AM COT +# EESchema Netlist Version 1.1 created Thu 12 Aug 2010 05:12:23 PM COT ( ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000357 ) - ( 2 N-000362 ) + ( 1 N-000358 ) + ( 2 N-000363 ) ) ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000358 ) + ( 1 N-000359 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000361 ) + ( 1 N-000362 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000361 ) + ( 1 N-000362 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000360 ) + ( 1 N-000361 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000356 ) + ( 1 N-000357 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000357 ) + ( 1 N-000358 ) ( 2 +5V ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000361 ) - ( S2 N-000361 ) - ( S3 N-000361 ) - ( S4 N-000361 ) - ( 1 N-000362 ) - ( 2 N-000356 ) - ( 3 N-000360 ) - ( 4 N-000358 ) + ( S1 N-000362 ) + ( S2 N-000362 ) + ( S3 N-000362 ) + ( S4 N-000362 ) + ( 1 N-000363 ) + ( 2 N-000357 ) + ( 3 N-000361 ) + ( 4 N-000359 ) ) ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} - ( 1 N-000363 ) + ( 1 N-000364 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} - ( 1 N-000363 ) + ( 1 N-000364 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} - ( 1 N-000363 ) + ( 1 N-000364 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) - ( 2 /USB/USBA_SPD ) - ( 3 /USB/USBA_RCV ) + ( 2 /FPGA_Spartan6/USBA_SPD ) + ( 3 /FPGA_Spartan6/USBA_RCV ) ( 4 /FPGA_Spartan6/USBA_VP ) ( 5 /FPGA_Spartan6/USBA_VM ) ( 7 GND ) ( 8 GND ) ( 9 /FPGA_Spartan6/USBA_OE_N ) - ( 10 N-000356 ) - ( 11 N-000360 ) + ( 10 N-000357 ) + ( 11 N-000361 ) ( 12 3.3V ) ( 14 3.3V ) ) @@ -77,9 +77,9 @@ ( N6 ? ) ( M6 ? ) ( L6 ? ) - ( K6 /FPGA_Spartan6/M0_A3 ) + ( K6 /DDR_Banks/M0_A3 ) ( J6 ? ) - ( H6 /DDR_Banks/M0_A7 ) + ( H6 /FPGA_Spartan6/M0_A7 ) ( G6 ? ) ( F6 +2.5V ) ( E6 ? ) @@ -87,7 +87,7 @@ ( P5 ? ) ( N5 +2.5V ) ( M5 ? ) - ( K5 /FPGA_Spartan6/M0_RAS# ) + ( K5 /DDR_Banks/M0_RAS# ) ( J5 +2.5V ) ( H5 /FPGA_Spartan6/M0_A2 ) ( F5 ? ) @@ -97,27 +97,27 @@ ( H21 /DDR_Banks/M1_RAS# ) ( G21 +2.5V ) ( F21 /FPGA_Spartan6/M1_A0 ) - ( D21 /DDR_Banks/M1_CKE ) + ( D21 /FPGA_Spartan6/M1_CKE ) ( C21 +2.5V ) ( B21 ? ) ( A21 ? ) ( W20 ? ) ( V20 ? ) - ( U20 /FPGA_Spartan6/M1_DQ12 ) + ( U20 /DDR_Banks/M1_DQ12 ) ( T20 ? ) ( R20 /FPGA_Spartan6/M1_DQ10 ) ( P20 ? ) - ( N20 /DDR_Banks/M1_DQ0 ) + ( N20 /FPGA_Spartan6/M1_DQ0 ) ( M20 /FPGA_Spartan6/M1_UDM ) - ( L20 /FPGA_Spartan6/M1_LDQS ) - ( K20 /DDR_Banks/M1_A5 ) - ( J20 /FPGA_Spartan6/M1_DQ4 ) - ( H20 /FPGA_Spartan6/M1_CLK ) - ( G20 /FPGA_Spartan6/M1_A3 ) - ( F20 /DDR_Banks/M1_A4 ) + ( L20 /DDR_Banks/M1_LDQS ) + ( K20 /FPGA_Spartan6/M1_A5 ) + ( J20 /DDR_Banks/M1_DQ4 ) + ( H20 /DDR_Banks/M1_CLK ) + ( G20 /DDR_Banks/M1_A3 ) + ( F20 /FPGA_Spartan6/M1_A4 ) ( E20 /FPGA_Spartan6/M1_A7 ) ( D20 ? ) - ( C20 /FPGA_Spartan6/M1_A8 ) + ( C20 /DDR_Banks/M1_A8 ) ( B20 ? ) ( A20 ? ) ( P8 ? ) @@ -129,13 +129,13 @@ ( V2 /FPGA_Spartan6/M0_DQ14 ) ( T2 /DDR_Banks/M0_UDQS ) ( R2 +2.5V ) - ( P2 /FPGA_Spartan6/M0_DQ8 ) + ( P2 /DDR_Banks/M0_DQ8 ) ( M2 /FPGA_Spartan6/M0_DQ2 ) ( L2 +2.5V ) - ( K2 /DDR_Banks/M0_DQ6 ) + ( K2 /FPGA_Spartan6/M0_DQ6 ) ( H2 /FPGA_Spartan6/M0_A0 ) ( G2 +2.5V ) - ( F2 /FPGA_Spartan6/M0_WE# ) + ( F2 /DDR_Banks/M0_WE# ) ( D2 /FPGA_Spartan6/M0_CKE ) ( C2 +2.5V ) ( B2 ? ) @@ -145,41 +145,41 @@ ( V1 /FPGA_Spartan6/M0_DQ15 ) ( U1 /DDR_Banks/M0_DQ13 ) ( T1 ? ) - ( R1 /FPGA_Spartan6/M0_DQ11 ) - ( P1 /DDR_Banks/M0_DQ9 ) - ( N1 /FPGA_Spartan6/M0_DQ1 ) + ( R1 /DDR_Banks/M0_DQ11 ) + ( P1 /FPGA_Spartan6/M0_DQ9 ) + ( N1 /DDR_Banks/M0_DQ1 ) ( M1 /FPGA_Spartan6/M0_DQ3 ) ( L1 ? ) - ( K1 /FPGA_Spartan6/M0_DQ7 ) - ( J1 /DDR_Banks/M0_DQ5 ) + ( K1 /DDR_Banks/M0_DQ7 ) + ( J1 /FPGA_Spartan6/M0_DQ5 ) ( H1 /FPGA_Spartan6/M0_A1 ) - ( G1 /FPGA_Spartan6/M0_BA1 ) + ( G1 /DDR_Banks/M0_BA1 ) ( T4 ? ) ( R4 ? ) ( P4 ? ) ( N4 ? ) ( M4 ? ) ( L4 /DDR_Banks/M0_LDM ) - ( K4 /FPGA_Spartan6/M0_CAS# ) - ( J4 /FPGA_Spartan6/M0_A6 ) - ( H4 /DDR_Banks/M0_CLK ) + ( K4 /DDR_Banks/M0_CAS# ) + ( J4 /DDR_Banks/M0_A6 ) + ( H4 /FPGA_Spartan6/M0_CLK ) ( G4 /DDR_Banks/M0_A10 ) ( F4 +2.5V ) ( E4 ? ) ( C4 ? ) ( W3 ? ) ( V3 ? ) - ( U3 /FPGA_Spartan6/M0_DQ12 ) + ( U3 /DDR_Banks/M0_DQ12 ) ( T3 ? ) ( R3 /DDR_Banks/M0_DQ10 ) ( P3 ? ) ( N3 /FPGA_Spartan6/M0_DQ0 ) - ( M3 /DDR_Banks/M0_UDM ) + ( M3 /FPGA_Spartan6/M0_UDM ) ( L3 /DDR_Banks/M0_LDQS ) - ( K3 /DDR_Banks/M0_A5 ) - ( J3 /FPGA_Spartan6/M0_DQ4 ) + ( K3 /FPGA_Spartan6/M0_A5 ) + ( J3 /DDR_Banks/M0_DQ4 ) ( H3 /FPGA_Spartan6/M0_CLK# ) - ( G3 /DDR_Banks/M0_BA0 ) + ( G3 /FPGA_Spartan6/M0_BA0 ) ( F3 /FPGA_Spartan6/M0_A4 ) ( E3 /FPGA_Spartan6/M0_A8 ) ( D3 ? ) @@ -190,45 +190,45 @@ ( B10 /Ethernet_Phy/ETH_CRS ) ( A10 /Ethernet_Phy/ETH_COL ) ( E9 +3.3V ) - ( D9 /Ethernet_Phy/ETH_TXEN ) - ( C9 /Ethernet_Phy/ETH_TXD1 ) + ( D9 /FPGA_Spartan6/ETH_TXEN ) + ( C9 /FPGA_Spartan6/ETH_TXD1 ) ( A9 /Ethernet_Phy/ETH_TXD2 ) - ( D8 /Ethernet_Phy/ETH_TXC ) - ( C8 /FPGA_Spartan6/ETH_TXD0 ) - ( B8 /Ethernet_Phy/ETH_RXER ) - ( A8 /Ethernet_Phy/ETH_TXER ) + ( D8 /FPGA_Spartan6/ETH_TXC ) + ( C8 /Ethernet_Phy/ETH_TXD0 ) + ( B8 /FPGA_Spartan6/ETH_RXER ) + ( A8 /FPGA_Spartan6/ETH_TXER ) ( D7 /FPGA_Spartan6/ETH_TXD3 ) ( C7 /Ethernet_Phy/ETH_RXD0 ) ( B7 +3.3V ) ( A7 /Ethernet_Phy/ETH_RXDV ) ( D6 /FPGA_Spartan6/ETH_RESET_N ) - ( C6 /FPGA_Spartan6/ETH_RXD3 ) - ( B6 /FPGA_Spartan6/ETH_RXD2 ) + ( C6 /Ethernet_Phy/ETH_RXD3 ) + ( B6 /Ethernet_Phy/ETH_RXD2 ) ( A6 /Ethernet_Phy/ETH_RXD1 ) ( C5 /Ethernet_Phy/ETH_MDC ) ( A5 /FPGA_Spartan6/ETH_MDIO ) ( B4 +3.3V ) - ( A4 /Ethernet_Phy/ETH_INT ) + ( A4 /FPGA_Spartan6/ETH_INT ) ( U19 ? ) ( T19 ? ) - ( R19 ? ) + ( R19 /FPGA_Spartan6/USBA_SPD ) ( P19 ? ) ( N19 ? ) ( B19 +3.3V ) - ( B18 /FPGA_Spartan6/USBA_VP ) - ( A18 /USB/USBA_RCV ) + ( B18 /FPGA_Spartan6/SD_DAT1 ) + ( A18 /Non_volatile_memories/SD_DAT0 ) ( E17 +3.3V ) - ( D17 /USB/USBA_SPD ) - ( C17 /Non_volatile_memories/SD_CMD ) - ( A17 /FPGA_Spartan6/USBA_VM ) - ( E16 /FPGA_Spartan6/USBA_OE_N ) - ( C16 /Non_volatile_memories/SD_DAT1 ) - ( B16 /Non_volatile_memories/SD_DAT0 ) - ( A16 /Non_volatile_memories/SD_CLK ) - ( D15 /Non_volatile_memories/SD_DAT2 ) + ( D17 /Non_volatile_memories/SD_CMD ) + ( C17 /Non_volatile_memories/SD_DAT3 ) + ( A17 /Non_volatile_memories/SD_DAT2 ) + ( E16 /FPGA_Spartan6/SD_CLK ) + ( C16 ? ) + ( B16 ? ) + ( A16 ? ) + ( D15 ? ) ( C15 ? ) ( B15 +3.3V ) - ( A15 /FPGA_Spartan6/SD_DAT3 ) + ( A15 ? ) ( G14 +3.3V ) ( D14 ? ) ( C14 ? ) @@ -249,13 +249,13 @@ ( F16 ? ) ( L15 ? ) ( W22 ? ) - ( V22 /FPGA_Spartan6/M1_DQ15 ) - ( U22 /DDR_Banks/M1_DQ13 ) + ( V22 /DDR_Banks/M1_DQ15 ) + ( U22 /FPGA_Spartan6/M1_DQ13 ) ( T22 ? ) ( R22 /FPGA_Spartan6/M1_DQ11 ) - ( P22 /FPGA_Spartan6/M1_DQ9 ) + ( P22 /DDR_Banks/M1_DQ9 ) ( N22 /FPGA_Spartan6/M1_DQ1 ) - ( M22 /DDR_Banks/M1_DQ3 ) + ( M22 /FPGA_Spartan6/M1_DQ3 ) ( L22 ? ) ( K22 /FPGA_Spartan6/M1_DQ7 ) ( J22 /DDR_Banks/M1_DQ5 ) @@ -268,38 +268,38 @@ ( B22 ? ) ( W21 +2.5V ) ( V21 /FPGA_Spartan6/M1_DQ14 ) - ( T21 /FPGA_Spartan6/M1_UDQS ) + ( T21 /DDR_Banks/M1_UDQS ) ( R21 +2.5V ) ( P21 /FPGA_Spartan6/M1_DQ8 ) ( M21 /FPGA_Spartan6/M1_DQ2 ) ( L21 +2.5V ) ( K21 /DDR_Banks/M1_DQ6 ) ( M19 ? ) - ( L19 /DDR_Banks/M1_LDM ) - ( K19 /DDR_Banks/M1_A6 ) + ( L19 /FPGA_Spartan6/M1_LDM ) + ( K19 /FPGA_Spartan6/M1_A6 ) ( J19 /FPGA_Spartan6/M1_CLK# ) ( H19 /FPGA_Spartan6/M1_WE# ) - ( G19 /DDR_Banks/M1_A10 ) - ( F19 /DDR_Banks/M1_A11 ) + ( G19 /FPGA_Spartan6/M1_A10 ) + ( F19 /FPGA_Spartan6/M1_A11 ) ( E19 +2.5V ) ( D19 ? ) ( U18 +2.5V ) - ( P18 ? ) + ( P18 /FPGA_Spartan6/USBA_OE_N ) ( N18 +2.5V ) - ( M18 ? ) + ( M18 /FPGA_Spartan6/USBA_VM ) ( K18 ? ) ( J18 +2.5V ) ( H18 ? ) ( F18 ? ) - ( P17 ? ) + ( P17 /FPGA_Spartan6/USBA_VP ) ( M17 ? ) ( L17 ? ) ( K17 /FPGA_Spartan6/M1_BA1 ) - ( J17 /DDR_Banks/M1_BA0 ) + ( J17 /FPGA_Spartan6/M1_BA0 ) ( H17 ? ) ( G17 ? ) ( F17 ? ) - ( N16 ? ) + ( N16 /FPGA_Spartan6/USBA_RCV ) ( M16 ? ) ( L16 +2.5V ) ( K16 ? ) @@ -432,7 +432,7 @@ ( V18 ? ) ( T18 ? ) ( AB7 ? ) - ( AA7 N-000101 ) + ( AA7 N-000118 ) ( Y17 ? ) ( W17 ? ) ( V17 ? ) @@ -441,7 +441,7 @@ ( AB6 ? ) ( AA6 ? ) ( Y16 ? ) - ( V16 N-000101 ) + ( V16 N-000118 ) ( U16 ? ) ( T16 ? ) ( R16 ? ) @@ -456,18 +456,18 @@ ( AA4 ? ) ( F1 ? ) ( E1 /FPGA_Spartan6/M0_A9 ) - ( D1 /FPGA_Spartan6/M0_A12 ) + ( D1 /DDR_Banks/M0_A12 ) ( C1 /FPGA_Spartan6/M0_A11 ) ( B1 ? ) ( AB19 ? ) - ( AA19 N-000101 ) + ( AA19 N-000118 ) ( AB18 ? ) ( AA18 ? ) ( AB17 ? ) ( AB16 ? ) ( AA16 ? ) ( AB15 ? ) - ( AA15 N-000101 ) + ( AA15 N-000118 ) ( AB14 ? ) ( AA14 ? ) ( AB13 ? ) @@ -477,7 +477,7 @@ ( AB21 ? ) ( AA21 ? ) ( AB11 ? ) - ( AA11 N-000101 ) + ( AA11 N-000118 ) ( AB20 ? ) ( AA20 ? ) ( AB10 ? ) @@ -486,11 +486,11 @@ ( Y19 ? ) ( V9 ? ) ( U9 ? ) - ( T9 N-000101 ) + ( T9 N-000118 ) ( R9 ? ) ( Y8 ? ) ( W8 ? ) - ( V8 N-000101 ) + ( V8 N-000118 ) ( U8 ? ) ( T8 ? ) ( R8 ? ) @@ -503,7 +503,7 @@ ( U6 ? ) ( T6 ? ) ( Y5 ? ) - ( W5 N-000101 ) + ( W5 N-000118 ) ( V5 ? ) ( T5 ? ) ( Y4 ? ) @@ -519,18 +519,18 @@ ( U14 ? ) ( T14 ? ) ( AB3 ? ) - ( AA3 N-000101 ) + ( AA3 N-000118 ) ( Y13 ? ) ( W13 ? ) ( V13 ? ) ( U13 ? ) - ( T13 N-000101 ) + ( T13 N-000118 ) ( R13 ? ) ( AB2 ? ) ( AA2 ? ) ( Y12 ? ) ( W12 ? ) - ( V12 N-000101 ) + ( V12 N-000118 ) ( U12 ? ) ( T12 ? ) ( Y11 ? ) @@ -547,7 +547,7 @@ ) ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} ( 1 /Ethernet_Phy/ETH_PLL1.8V ) - ( 2 N-000347 ) + ( 2 N-000348 ) ) ( /4C4320F3/4C5D810A $noname L3 INDUCTOR {Lib=INDUCTOR} ( 1 /Ethernet_Phy/ETH_A1.8V ) @@ -555,15 +555,15 @@ ) ( /4C4320F3/4C5D8104 $noname C6 C {Lib=C} ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 N-000347 ) + ( 2 N-000348 ) ) ( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR} - ( 1 N-000338 ) + ( 1 N-000339 ) ( 2 /Ethernet_Phy/ETH_A1.8V ) ) ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} - ( 1 N-000338 ) - ( 2 N-000347 ) + ( 1 N-000339 ) + ( 2 N-000348 ) ) ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} ( 1 /Ethernet_Phy/ETH_1.8V ) @@ -598,7 +598,7 @@ ( 2 3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000344 ) + ( 1 N-000345 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} @@ -610,55 +610,55 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000336 ) + ( 1 N-000337 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000336 ) + ( 1 N-000337 ) ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} ( 1 /FPGA_Spartan6/ETH_MDIO ) ( 2 /Ethernet_Phy/ETH_MDC ) - ( 3 /FPGA_Spartan6/ETH_RXD3 ) - ( 4 /FPGA_Spartan6/ETH_RXD2 ) + ( 3 /Ethernet_Phy/ETH_RXD3 ) + ( 4 /Ethernet_Phy/ETH_RXD2 ) ( 5 /Ethernet_Phy/ETH_RXD1 ) ( 6 /Ethernet_Phy/ETH_RXD0 ) ( 7 3.3V ) ( 8 GND ) ( 9 /Ethernet_Phy/ETH_RXDV ) ( 10 /Ethernet_Phy/ETH_RXC ) - ( 11 /Ethernet_Phy/ETH_RXER ) + ( 11 /FPGA_Spartan6/ETH_RXER ) ( 12 GND ) ( 13 /Ethernet_Phy/ETH_1.8V ) - ( 14 /Ethernet_Phy/ETH_TXER ) - ( 15 /Ethernet_Phy/ETH_TXC ) - ( 16 /Ethernet_Phy/ETH_TXEN ) - ( 17 /FPGA_Spartan6/ETH_TXD0 ) - ( 18 /Ethernet_Phy/ETH_TXD1 ) + ( 14 /FPGA_Spartan6/ETH_TXER ) + ( 15 /FPGA_Spartan6/ETH_TXC ) + ( 16 /FPGA_Spartan6/ETH_TXEN ) + ( 17 /Ethernet_Phy/ETH_TXD0 ) + ( 18 /FPGA_Spartan6/ETH_TXD1 ) ( 19 /Ethernet_Phy/ETH_TXD2 ) ( 20 /FPGA_Spartan6/ETH_TXD3 ) ( 21 /Ethernet_Phy/ETH_COL ) ( 22 /Ethernet_Phy/ETH_CRS ) ( 23 GND ) ( 24 3.3V ) - ( 25 /Ethernet_Phy/ETH_INT ) + ( 25 /FPGA_Spartan6/ETH_INT ) ( 26 /Ethernet_Phy/ETH_LED0 ) ( 27 /Ethernet_Phy/ETH_LED1 ) ( 28 ? ) ( 29 ? ) ( 30 ? ) ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000345 ) - ( 33 N-000335 ) + ( 32 N-000346 ) + ( 33 N-000336 ) ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000344 ) + ( 37 N-000345 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) - ( 40 N-000346 ) - ( 41 N-000334 ) + ( 40 N-000347 ) + ( 41 N-000335 ) ( 42 ? ) ( 43 ? ) ( 44 GND ) @@ -669,56 +669,56 @@ ) ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000334 ) + ( 2 N-000335 ) ) ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000346 ) + ( 2 N-000347 ) ) ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000345 ) + ( 2 N-000346 ) ) ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000335 ) + ( 2 N-000336 ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000350 ) + ( 1 N-000351 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000337 ) + ( 1 N-000338 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000334 ) - ( 2 N-000346 ) + ( 1 N-000335 ) + ( 2 N-000347 ) ( 3 3.3V ) ( 4 GND ) ( 5 GND ) ( 6 3.3V ) - ( 7 N-000335 ) - ( 8 N-000345 ) + ( 7 N-000336 ) + ( 8 N-000346 ) ( 9 3.3V ) - ( 10 N-000337 ) + ( 10 N-000338 ) ( 11 3.3V ) - ( 12 N-000350 ) - ( 13 N-000336 ) - ( 14 N-000336 ) + ( 12 N-000351 ) + ( 13 N-000337 ) + ( 14 N-000337 ) ) ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} ( CASE GND ) ( COM GND ) ( CD ? ) ( 1 /Non_volatile_memories/SD_DAT2 ) - ( 2 /FPGA_Spartan6/SD_DAT3 ) + ( 2 /Non_volatile_memories/SD_DAT3 ) ( 3 /Non_volatile_memories/SD_CMD ) ( 4 ? ) - ( 5 /Non_volatile_memories/SD_CLK ) + ( 5 /FPGA_Spartan6/SD_CLK ) ( 6 GND ) ( 7 /Non_volatile_memories/SD_DAT0 ) - ( 8 /Non_volatile_memories/SD_DAT1 ) + ( 8 /FPGA_Spartan6/SD_DAT1 ) ) ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} ( 1 ? ) @@ -726,8 +726,8 @@ ( 3 ? ) ( 4 ? ) ( 5 ? ) - ( 6 /Non_volatile_memories/FRB_N ) - ( 7 /Non_volatile_memories/FRB_N ) + ( 6 /Non_volatile_memories/NF_RNB ) + ( 7 /Non_volatile_memories/NF_RNB ) ( 8 ? ) ( 9 ? ) ( 10 ? ) @@ -757,7 +757,7 @@ ( 34 ? ) ( 35 ? ) ( 36 GND ) - ( 37 3.3V ) + ( 37 +3.3V ) ( 38 ? ) ( 39 ? ) ( 40 ? ) @@ -828,45 +828,45 @@ ) ( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R} ( 1 +2.5V ) - ( 2 N-000044 ) + ( 2 N-000050 ) ) ( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R} - ( 1 N-000044 ) - ( 2 N-000043 ) + ( 1 N-000050 ) + ( 2 N-000049 ) ) ( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R} - ( 1 N-000045 ) - ( 2 N-000047 ) + ( 1 N-000051 ) + ( 2 N-000053 ) ) ( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R} ( 1 +2.5V ) - ( 2 N-000045 ) + ( 2 N-000051 ) ) ( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP} ( 1 +2.5V ) - ( 2 N-000044 ) + ( 2 N-000050 ) ) ( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP} - ( 1 N-000044 ) - ( 2 N-000043 ) + ( 1 N-000050 ) + ( 2 N-000049 ) ) ( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP} - ( 1 N-000045 ) - ( 2 N-000047 ) + ( 1 N-000051 ) + ( 2 N-000053 ) ) ( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP} ( 1 +2.5V ) - ( 2 N-000045 ) + ( 2 N-000051 ) ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /DDR_Banks/M1_DQ0 ) + ( 2 /FPGA_Spartan6/M1_DQ0 ) ( 3 +2.5V ) ( 4 /FPGA_Spartan6/M1_DQ1 ) ( 5 /FPGA_Spartan6/M1_DQ2 ) ( 6 GND ) - ( 7 /DDR_Banks/M1_DQ3 ) - ( 8 /FPGA_Spartan6/M1_DQ4 ) + ( 7 /FPGA_Spartan6/M1_DQ3 ) + ( 8 /DDR_Banks/M1_DQ4 ) ( 9 +2.5V ) ( 10 /DDR_Banks/M1_DQ5 ) ( 11 /DDR_Banks/M1_DQ6 ) @@ -874,72 +874,72 @@ ( 13 /FPGA_Spartan6/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /FPGA_Spartan6/M1_LDQS ) + ( 16 /DDR_Banks/M1_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /DDR_Banks/M1_LDM ) + ( 20 /FPGA_Spartan6/M1_LDM ) ( 21 /FPGA_Spartan6/M1_WE# ) ( 22 /DDR_Banks/M1_CAS# ) ( 23 /DDR_Banks/M1_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 /DDR_Banks/M1_BA0 ) + ( 26 /FPGA_Spartan6/M1_BA0 ) ( 27 /FPGA_Spartan6/M1_BA1 ) - ( 28 /DDR_Banks/M1_A10 ) + ( 28 /FPGA_Spartan6/M1_A10 ) ( 29 /FPGA_Spartan6/M1_A0 ) ( 30 /FPGA_Spartan6/M1_A1 ) ( 31 /FPGA_Spartan6/M1_A2 ) - ( 32 /FPGA_Spartan6/M1_A3 ) + ( 32 /DDR_Banks/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /DDR_Banks/M1_A4 ) - ( 36 /DDR_Banks/M1_A5 ) - ( 37 /DDR_Banks/M1_A6 ) + ( 35 /FPGA_Spartan6/M1_A4 ) + ( 36 /FPGA_Spartan6/M1_A5 ) + ( 37 /FPGA_Spartan6/M1_A6 ) ( 38 /FPGA_Spartan6/M1_A7 ) - ( 39 /FPGA_Spartan6/M1_A8 ) + ( 39 /DDR_Banks/M1_A8 ) ( 40 /DDR_Banks/M1_A9 ) - ( 41 /DDR_Banks/M1_A11 ) + ( 41 /FPGA_Spartan6/M1_A11 ) ( 42 /FPGA_Spartan6/M1_A12 ) ( 43 ? ) ( 44 /FPGA_Spartan6/M1_CLK# ) - ( 45 /DDR_Banks/M1_CKE ) - ( 46 /FPGA_Spartan6/M1_CLK ) + ( 45 /FPGA_Spartan6/M1_CKE ) + ( 46 /DDR_Banks/M1_CLK ) ( 47 /FPGA_Spartan6/M1_UDM ) ( 48 GND ) - ( 49 N-000044 ) + ( 49 N-000050 ) ( 50 ? ) - ( 51 /FPGA_Spartan6/M1_UDQS ) + ( 51 /DDR_Banks/M1_UDQS ) ( 52 GND ) ( 53 ? ) ( 54 /FPGA_Spartan6/M1_DQ8 ) ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M1_DQ9 ) + ( 56 /DDR_Banks/M1_DQ9 ) ( 57 /FPGA_Spartan6/M1_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M1_DQ11 ) - ( 60 /FPGA_Spartan6/M1_DQ12 ) + ( 60 /DDR_Banks/M1_DQ12 ) ( 61 +2.5V ) - ( 62 /DDR_Banks/M1_DQ13 ) + ( 62 /FPGA_Spartan6/M1_DQ13 ) ( 63 /FPGA_Spartan6/M1_DQ14 ) ( 64 GND ) - ( 65 /FPGA_Spartan6/M1_DQ15 ) + ( 65 /DDR_Banks/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) ( 2 /FPGA_Spartan6/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M0_DQ1 ) + ( 4 /DDR_Banks/M0_DQ1 ) ( 5 /FPGA_Spartan6/M0_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M0_DQ3 ) - ( 8 /FPGA_Spartan6/M0_DQ4 ) + ( 8 /DDR_Banks/M0_DQ4 ) ( 9 +2.5V ) - ( 10 /DDR_Banks/M0_DQ5 ) - ( 11 /DDR_Banks/M0_DQ6 ) + ( 10 /FPGA_Spartan6/M0_DQ5 ) + ( 11 /FPGA_Spartan6/M0_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Spartan6/M0_DQ7 ) + ( 13 /DDR_Banks/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /DDR_Banks/M0_LDQS ) @@ -947,46 +947,46 @@ ( 18 +2.5V ) ( 19 ? ) ( 20 /DDR_Banks/M0_LDM ) - ( 21 /FPGA_Spartan6/M0_WE# ) - ( 22 /FPGA_Spartan6/M0_CAS# ) - ( 23 /FPGA_Spartan6/M0_RAS# ) + ( 21 /DDR_Banks/M0_WE# ) + ( 22 /DDR_Banks/M0_CAS# ) + ( 23 /DDR_Banks/M0_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 /DDR_Banks/M0_BA0 ) - ( 27 /FPGA_Spartan6/M0_BA1 ) + ( 26 /FPGA_Spartan6/M0_BA0 ) + ( 27 /DDR_Banks/M0_BA1 ) ( 28 /DDR_Banks/M0_A10 ) ( 29 /FPGA_Spartan6/M0_A0 ) ( 30 /FPGA_Spartan6/M0_A1 ) ( 31 /FPGA_Spartan6/M0_A2 ) - ( 32 /FPGA_Spartan6/M0_A3 ) + ( 32 /DDR_Banks/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M0_A4 ) - ( 36 /DDR_Banks/M0_A5 ) - ( 37 /FPGA_Spartan6/M0_A6 ) - ( 38 /DDR_Banks/M0_A7 ) + ( 36 /FPGA_Spartan6/M0_A5 ) + ( 37 /DDR_Banks/M0_A6 ) + ( 38 /FPGA_Spartan6/M0_A7 ) ( 39 /FPGA_Spartan6/M0_A8 ) ( 40 /FPGA_Spartan6/M0_A9 ) ( 41 /FPGA_Spartan6/M0_A11 ) - ( 42 /FPGA_Spartan6/M0_A12 ) + ( 42 /DDR_Banks/M0_A12 ) ( 43 ? ) ( 44 /FPGA_Spartan6/M0_CLK# ) ( 45 /FPGA_Spartan6/M0_CKE ) - ( 46 /DDR_Banks/M0_CLK ) - ( 47 /DDR_Banks/M0_UDM ) + ( 46 /FPGA_Spartan6/M0_CLK ) + ( 47 /FPGA_Spartan6/M0_UDM ) ( 48 GND ) - ( 49 N-000045 ) + ( 49 N-000051 ) ( 50 ? ) ( 51 /DDR_Banks/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /FPGA_Spartan6/M0_DQ8 ) + ( 54 /DDR_Banks/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /DDR_Banks/M0_DQ9 ) + ( 56 /FPGA_Spartan6/M0_DQ9 ) ( 57 /DDR_Banks/M0_DQ10 ) ( 58 GND ) - ( 59 /FPGA_Spartan6/M0_DQ11 ) - ( 60 /FPGA_Spartan6/M0_DQ12 ) + ( 59 /DDR_Banks/M0_DQ11 ) + ( 60 /DDR_Banks/M0_DQ12 ) ( 61 +2.5V ) ( 62 /DDR_Banks/M0_DQ13 ) ( 63 /FPGA_Spartan6/M0_DQ14 ) @@ -1255,723 +1255,723 @@ $endfootprintlist } { Pin List by Nets Net 1 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" - U4 46 U1 C10 -Net 2 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" - U1 K4 - U2 22 -Net 3 "/FPGA Spartan6/M1_WE#" "M1_WE#" - U1 H19 - U3 21 -Net 4 "/DDR Banks/M1_RAS#" "M1_RAS#" - U1 H21 - U3 23 -Net 5 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" - U1 K5 - U2 23 -Net 6 "/FPGA Spartan6/M0_WE#" "M0_WE#" - U1 F2 + U4 46 +Net 2 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" + U1 D8 + U4 15 +Net 3 "/DDR Banks/M0_WE#" "M0_WE#" U2 21 -Net 8 "/Non volatile memories/SD_CMD" "SD_CMD" + U1 F2 +Net 4 "/Non volatile memories/NF_RNB" "NF_RNB" + U5 7 + U5 6 +Net 11 "/Non volatile memories/SD_CMD" "SD_CMD" J1 3 - U1 C17 -Net 9 "/Non volatile memories/SD_CLK" "SD_CLK" - U1 A16 + U1 D17 +Net 12 "/FPGA Spartan6/SD_CLK" "SD_CLK" + U1 E16 J1 5 -Net 10 "/Ethernet Phy/ETH_INT" "ETH_INT" +Net 13 "/FPGA Spartan6/ETH_INT" "ETH_INT" U1 A4 U4 25 -Net 11 "/Ethernet Phy/ETH_TXER" "ETH_TXER" +Net 14 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" + U1 A7 + U4 9 +Net 15 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" + U4 11 + U1 B8 +Net 16 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" U1 A8 U4 14 -Net 12 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" - U4 16 +Net 17 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" U1 D9 -Net 13 "/Ethernet Phy/ETH_TXC" "ETH_TXC" - U4 15 - U1 D8 -Net 14 "/Ethernet Phy/ETH_RXER" "ETH_RXER" - U1 B8 - U4 11 -Net 15 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" - U4 9 - U1 A7 -Net 16 "/Ethernet Phy/ETH_MDC" "ETH_MDC" + U4 16 +Net 18 "/Ethernet Phy/ETH_MDC" "ETH_MDC" U1 C5 U4 2 -Net 17 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" - U4 1 +Net 19 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" U1 A5 + U4 1 R1 1 -Net 18 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" - U4 48 +Net 20 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" U1 D6 -Net 19 "/Ethernet Phy/ETH_RXC" "ETH_RXC" + U4 48 +Net 21 "/Ethernet Phy/ETH_RXC" "ETH_RXC" U1 D10 U4 10 -Net 20 "/Ethernet Phy/ETH_COL" "ETH_COL" +Net 22 "/Ethernet Phy/ETH_COL" "ETH_COL" U4 21 U1 A10 -Net 21 "/Ethernet Phy/ETH_CRS" "ETH_CRS" - U4 22 +Net 23 "/Ethernet Phy/ETH_CRS" "ETH_CRS" U1 B10 -Net 22 "/FPGA Spartan6/M1_UDM" "M1_UDM" - U3 47 + U4 22 +Net 24 "/FPGA Spartan6/M1_UDM" "M1_UDM" U1 M20 -Net 23 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" + U3 47 +Net 25 "/DDR Banks/M1_LDQS" "M1_LDQS" U1 L20 U3 16 -Net 24 "/DDR Banks/M1_LDM" "M1_LDM" - U1 L19 +Net 26 "/FPGA Spartan6/M1_LDM" "M1_LDM" U3 20 -Net 25 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" + U1 L19 +Net 27 "/DDR Banks/M1_UDQS" "M1_UDQS" U1 T21 U3 51 -Net 26 "/DDR Banks/M0_UDQS" "M0_UDQS" +Net 28 "/DDR Banks/M0_UDQS" "M0_UDQS" U1 T2 U2 51 -Net 27 "/DDR Banks/M0_LDM" "M0_LDM" +Net 29 "/DDR Banks/M0_LDM" "M0_LDM" U1 L4 U2 20 -Net 28 "/DDR Banks/M1_CAS#" "M1_CAS#" +Net 30 "/DDR Banks/M1_CAS#" "M1_CAS#" U3 22 U1 H22 -Net 29 "/DDR Banks/M1_CKE" "M1_CKE" - U3 45 +Net 31 "/FPGA Spartan6/M1_CKE" "M1_CKE" U1 D21 -Net 30 "GND" "GND" - U2 66 + U3 45 +Net 32 "GND" "GND" + U1 W16 + U1 D4 + U1 V4 + U5 13 + U1 AA5 U1 B5 - U3 66 - U1 M12 - U3 48 - U1 J15 - U3 58 - U3 52 - U2 34 + U5 36 + U1 E21 + U4 8 + C12 2 + U1 J2 + U1 E2 + U1 A1 + U1 B17 + U1 U2 + U1 N2 + U3 64 + U1 N11 + U1 L11 + J1 6 + U1 J11 + U1 V10 + U1 P10 + V1 2 + U1 M10 + U3 12 U2 64 + U2 34 U2 24 U2 58 - U1 AB1 U2 48 - U3 12 - U2 6 U3 6 - U1 J13 - U1 A22 - U4 39 - U1 P14 - U1 V14 - U1 E15 - U1 H7 - U4 36 - U1 B13 - U1 G5 + U2 66 + U2 6 + U3 66 + R9 2 + U3 48 + U3 58 + U3 52 + U2 52 + U2 12 U3 24 U3 34 - U3 64 - U1 L5 + U1 N9 + U1 B13 + U4 12 + U1 A22 U1 P12 - U4 35 - U1 R5 - U1 E7 + R10 2 + U1 M12 + U1 J15 + U1 AB1 + U1 U21 + U1 N21 + U1 J21 + U1 K10 + J1 COM + J1 CASE + J1 CASE + J1 CASE + C16 2 + C11 2 + R2 2 + U1 B9 + J4 4 + J4 5 + U4 44 + L5 2 + C24 2 + C25 2 + C23 2 + C22 2 + U1 AA9 + U1 AB22 + C31 2 + C30 2 + C32 2 + U1 AA13 + C27 2 U1 AA17 - U1 AA5 - U1 W16 - U1 B17 + U6 7 + U6 8 + C21 2 + U1 H7 + U4 23 + U1 E7 + C8 2 + U1 R5 + C7 2 + C5 2 + C3 2 + C1 2 + U1 L5 + U1 G5 + U1 W7 + U1 U7 + U1 W19 + U1 J13 + U4 35 + U1 L13 + U1 N13 + U4 36 + U1 L9 + U1 J9 + U1 K14 + U4 39 + V2 2 U1 N17 U1 D18 U1 G18 U1 L18 U1 R18 - U1 W19 - U1 AA9 - U1 AB22 - U1 AA13 - J1 CASE - U2 52 - U2 12 - U1 A1 - U1 E2 - U1 J2 - U1 N2 - U1 U2 - U1 D4 - U1 V4 - J1 6 - J1 COM - J1 CASE - J1 CASE - U5 36 - U5 13 - U1 L11 - U4 44 - U1 N11 - C3 2 - U4 23 - U1 E21 - U1 J21 - U4 12 - C1 2 - U1 N21 - U1 U21 - U1 L13 - U1 U7 - U1 W7 - C2 2 - U1 P10 - U1 V10 - U1 J11 - R9 2 - U1 N13 - C8 2 - U4 8 - C12 2 - C7 2 - C10 2 - C5 2 - C11 2 - R2 2 - C21 2 - C27 2 - C32 2 - C30 2 - C31 2 + U1 P14 C33 2 - C22 2 - C23 2 - C25 2 - C24 2 - C26 2 + U1 V14 + U1 E15 + C15 2 C28 2 C29 2 - U1 N9 - C34 2 - U1 B9 - U1 J9 - U1 L9 - J4 5 - U6 8 - U6 7 - U1 K14 - C13 2 C14 2 - C15 2 - V2 2 - V1 2 - C16 2 - R10 2 + C13 2 + C2 2 + C26 2 + C10 2 + C34 2 U1 M14 - J4 4 - L5 2 - U1 K10 - U1 M10 -Net 31 "/FPGA Spartan6/M0_CKE" "M0_CKE" - U2 45 +Net 33 "/FPGA Spartan6/M0_CKE" "M0_CKE" U1 D2 -Net 32 "/DDR Banks/M0_LDQS" "M0_LDQS" + U2 45 +Net 34 "/DDR Banks/M0_CAS#" "M0_CAS#" + U1 K4 + U2 22 +Net 35 "/FPGA Spartan6/M1_WE#" "M1_WE#" + U1 H19 + U3 21 +Net 36 "/DDR Banks/M1_RAS#" "M1_RAS#" + U3 23 + U1 H21 +Net 37 "/DDR Banks/M0_RAS#" "M0_RAS#" + U2 23 + U1 K5 +Net 38 "/DDR Banks/M0_LDQS" "M0_LDQS" U1 L3 U2 16 -Net 33 "/DDR Banks/M0_UDM" "M0_UDM" +Net 39 "/FPGA Spartan6/M0_UDM" "M0_UDM" U2 47 U1 M3 -Net 34 "/FPGA Spartan6/USBA_VP" "USBA_VP" - U1 B18 - U6 4 -Net 35 "/USB/USBA_RCV" "USBA_RCV" +Net 40 "/FPGA Spartan6/USBA_VM" "USBA_VM" + U1 M18 + U6 5 +Net 41 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" U6 3 - U1 A18 -Net 36 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" - U6 9 - U1 E16 -Net 37 "/USB/USBA_SPD" "USBA_SPD" + U1 N16 +Net 42 "/FPGA Spartan6/USBA_SPD" "USBA_SPD" U6 2 - U1 D17 -Net 38 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" + U1 R19 +Net 43 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" U1 H3 U2 44 -Net 39 "/DDR Banks/M0_CLK" "M0_CLK" +Net 44 "/FPGA Spartan6/M0_CLK" "M0_CLK" U1 H4 U2 46 -Net 40 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" - U3 44 +Net 45 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" U1 J19 -Net 41 "/FPGA Spartan6/M1_CLK" "M1_CLK" + U3 44 +Net 46 "/DDR Banks/M1_CLK" "M1_CLK" U1 H20 U3 46 -Net 42 "/FPGA Spartan6/USBA_VM" "USBA_VM" - U1 A17 - U6 5 -Net 43 "" "" - C20 2 +Net 47 "/FPGA Spartan6/USBA_VP" "USBA_VP" + U1 P17 + U6 4 +Net 48 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" + U1 P18 + U6 9 +Net 49 "" "" R14 2 -Net 44 "" "" - R13 2 + C20 2 +Net 50 "" "" R14 1 - C19 2 + R13 2 U3 49 C20 1 -Net 45 "" "" - C18 1 + C19 2 +Net 51 "" "" R12 1 + C18 1 C17 2 - R11 2 U2 49 -Net 46 "+2.5V" "+2.5V" - U1 N8 - U1 G2 - U1 L16 - U1 R10 - U1 C2 - U1 F11 + R11 2 +Net 52 "+2.5V" "+2.5V" + C33 1 U1 H9 - U1 L8 - U3 15 - U1 L2 - U1 E19 + U1 V6 U1 U18 - U1 G21 U1 N18 U1 J18 - C33 1 - U3 3 - U1 W21 - U1 R2 - U3 55 - U1 U11 - U1 D16 - U1 W2 - U1 R21 - U1 L21 - U1 G12 - U3 18 - U1 R12 - U3 33 - U2 61 + U1 L16 + U1 F4 + U1 R6 + R13 1 + U6 1 C22 1 C23 1 - U3 61 C25 1 - U2 33 C24 1 - C28 1 C26 1 - U2 1 C34 1 - U2 3 - U2 9 - U1 C21 - C31 1 - C30 1 - C32 1 - R11 1 - R13 1 - U1 M15 - U1 K15 - U3 9 - U1 N5 - U6 1 - U1 U5 - U1 V6 - U2 15 - C19 1 - U1 F4 - U1 F6 - U1 J5 C29 1 - U1 H15 - U1 L7 - U3 1 - C17 1 - C27 1 - U2 18 + C28 1 + U1 E19 + U1 L8 + U1 N8 + U1 R21 + U1 L21 + U1 G21 + U1 C21 C21 1 + U1 W21 + C27 1 + C32 1 + C30 1 + C31 1 + U1 J5 + U2 33 + U3 18 + U3 33 + U2 61 + U3 15 + U1 L7 + U1 F11 + U1 R10 + U1 W2 + U1 R2 + U1 L2 + U1 G2 + U1 R12 + U1 C2 + U1 G12 + U1 H15 + U1 U11 + U1 K15 + U3 61 + U3 9 + R11 1 U2 55 - U1 R6 -Net 47 "" "" - C18 2 + C19 1 + U2 15 + C17 1 + U3 1 + U3 3 + U2 18 + U3 55 + U1 F6 + U2 9 + U1 U5 + U1 N5 + U2 3 + U2 1 + U1 D16 + U1 M15 +Net 53 "" "" R12 2 -Net 93 "/Non volatile memories/FRB_N" "FRB_N" - U5 7 - U5 6 -Net 94 "3.3V" "3.3V" - L2 1 - U4 7 + C18 2 +Net 98 "3.3V" "3.3V" J4 11 - C5 1 - C10 1 J4 9 - J4 6 - R5 1 - U6 12 - J4 3 - R3 1 - R4 1 U6 14 - R6 1 - R1 2 - U5 37 - U5 19 - U5 12 - C11 1 - C1 1 - U4 24 + C5 1 C3 1 -Net 98 "+1.2V" "+1.2V" - U1 P9 - U1 R14 - U1 P11 - U1 N14 - U1 L10 - U1 N10 - U1 L12 - U1 J8 - U1 K13 - U1 K9 - U1 J12 - U1 M9 - U1 L14 - U1 J14 - U1 M11 - U1 P13 - U1 M13 - U1 N12 - U1 K11 - U1 J10 -Net 100 "+3.3V" "+3.3V" - U1 E9 - U1 G10 - U1 B4 - U1 B11 - U1 E13 - U1 G14 + C1 1 + R6 1 + L2 1 + R5 1 + U4 24 + C11 1 + J4 3 + J4 6 + C10 1 + U6 12 + U5 12 + R1 2 + U4 7 + R4 1 + U5 19 + R3 1 +Net 99 "+3.3V" "+3.3V" U1 B15 - U1 B7 + U1 G14 + U1 E13 + U1 B4 + U5 37 U1 B19 U1 E17 -Net 101 "" "" - U1 V12 - U1 AA7 - U1 T13 + U1 E9 + U1 B7 + U1 G10 + U1 B11 +Net 118 "" "" + U1 AA19 U1 T9 + U1 AA7 U1 AA11 - U1 W5 - U1 V16 U1 V8 U1 AA3 U1 AA15 - U1 AA19 -Net 333 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - R7 2 + U1 V16 + U1 V12 + U1 T13 + U1 W5 +Net 119 "+1.2V" "+1.2V" + U1 M11 + U1 K11 + U1 J12 + U1 L12 + U1 N12 + U1 K13 + U1 M13 + U1 P13 + U1 M9 + U1 P11 + U1 K9 + U1 J14 + U1 N10 + U1 L10 + U1 L14 + U1 N14 + U1 R14 + U1 P9 + U1 J10 + U1 J8 +Net 334 "/Ethernet Phy/ETH_LED0" "ETH_LED0" U4 26 -Net 334 "" "" + R7 2 +Net 335 "" "" + R3 2 J4 1 U4 41 - R3 2 -Net 335 "" "" - U4 33 - J4 7 - R5 2 Net 336 "" "" - R9 1 + J4 7 + U4 33 + R5 2 +Net 337 "" "" C12 1 J4 13 J4 14 -Net 337 "" "" - R7 1 - J4 10 + R9 1 Net 338 "" "" - L1 1 + J4 10 + R7 1 +Net 339 "" "" C4 1 -Net 339 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" + L1 1 +Net 340 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" C2 1 U4 13 -Net 340 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - L3 2 +Net 341 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" C9 1 U4 47 -Net 343 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - U4 31 + L3 2 +Net 344 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" L1 2 - L3 1 + U4 31 C6 1 -Net 344 "" "" + L3 1 +Net 345 "" "" R2 1 U4 37 -Net 345 "" "" - J4 8 +Net 346 "" "" U4 32 R6 2 -Net 346 "" "" + J4 8 +Net 347 "" "" U4 40 R4 2 J4 2 -Net 347 "" "" - C4 2 - C6 2 +Net 348 "" "" C9 2 -Net 348 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - U4 38 + C6 2 + C4 2 +Net 349 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" L2 2 C8 1 C7 1 -Net 349 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - R8 2 + U4 38 +Net 350 "/Ethernet Phy/ETH_LED1" "ETH_LED1" U4 27 -Net 350 "" "" + R8 2 +Net 351 "" "" R8 1 J4 12 -Net 356 "" "" - V2 1 - U6 10 - J5 2 - V2 1 Net 357 "" "" - F1 1 - L4 1 + V2 1 + V2 1 + J5 2 + U6 10 Net 358 "" "" - J5 4 + L4 1 + F1 1 +Net 359 "" "" L5 1 -Net 360 "" "" + J5 4 +Net 361 "" "" J5 3 U6 11 V1 1 V1 1 -Net 361 "" "" - J5 S4 - J5 S3 - R10 1 - C16 1 - J5 S2 - J5 S1 Net 362 "" "" - L4 2 - J5 1 + J5 S1 + R10 1 + J5 S2 + J5 S4 + C16 1 + J5 S3 Net 363 "" "" - C13 1 - C14 1 + J5 1 + L4 2 +Net 364 "" "" C15 1 -Net 371 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" + C14 1 + C13 1 +Net 365 "/Non volatile memories/SD_DAT3" "SD_DAT3" J1 2 - U1 A15 -Net 372 "/Non volatile memories/SD_DAT2" "SD_DAT2" - U1 D15 + U1 C17 +Net 366 "/Non volatile memories/SD_DAT2" "SD_DAT2" J1 1 -Net 373 "/Non volatile memories/SD_DAT1" "SD_DAT1" + U1 A17 +Net 367 "/FPGA Spartan6/SD_DAT1" "SD_DAT1" + U1 B18 J1 8 - U1 C16 -Net 374 "/Non volatile memories/SD_DAT0" "SD_DAT0" - U1 B16 +Net 368 "/Non volatile memories/SD_DAT0" "SD_DAT0" + U1 A18 J1 7 -Net 375 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" +Net 369 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" U1 D7 U4 20 -Net 376 "/FPGA Spartan6/M1_BA1" "M1_BA1" - U1 K17 - U3 27 -Net 377 "/DDR Banks/M1_BA0" "M1_BA0" - U3 26 - U1 J17 -Net 378 "/FPGA Spartan6/M0_BA1" "M0_BA1" - U1 G1 - U2 27 -Net 379 "/DDR Banks/M0_BA0" "M0_BA0" - U1 G3 - U2 26 -Net 389 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" - U1 C6 - U4 3 -Net 390 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" - U4 4 - U1 B6 -Net 391 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" - U1 A6 - U4 5 -Net 392 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" - U1 C7 - U4 6 -Net 393 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" - U4 19 +Net 370 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" U1 A9 -Net 394 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" - U1 C9 + U4 19 +Net 371 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" U4 18 -Net 395 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" + U1 C9 +Net 372 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" U4 17 U1 C8 -Net 396 "/DDR Banks/M1_A9" "M1_A9" - U1 C22 - U3 40 -Net 397 "/FPGA Spartan6/M1_A8" "M1_A8" +Net 373 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" + U4 3 + U1 C6 +Net 374 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" + U4 4 + U1 B6 +Net 375 "/FPGA Spartan6/M1_BA1" "M1_BA1" + U1 K17 + U3 27 +Net 376 "/FPGA Spartan6/M1_BA0" "M1_BA0" + U3 26 + U1 J17 +Net 377 "/DDR Banks/M0_BA1" "M0_BA1" + U2 27 + U1 G1 +Net 378 "/FPGA Spartan6/M0_BA0" "M0_BA0" + U1 G3 + U2 26 +Net 387 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" + U1 A6 + U4 5 +Net 388 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" + U4 6 + U1 C7 +Net 389 "/DDR Banks/M1_A8" "M1_A8" U3 39 U1 C20 -Net 398 "/FPGA Spartan6/M1_A7" "M1_A7" +Net 390 "/FPGA Spartan6/M1_A7" "M1_A7" U1 E20 U3 38 -Net 399 "/DDR Banks/M1_A6" "M1_A6" +Net 391 "/FPGA Spartan6/M1_A6" "M1_A6" U1 K19 U3 37 -Net 400 "/DDR Banks/M1_A5" "M1_A5" - U1 K20 +Net 392 "/FPGA Spartan6/M1_A5" "M1_A5" U3 36 -Net 401 "/DDR Banks/M1_A4" "M1_A4" - U1 F20 + U1 K20 +Net 393 "/FPGA Spartan6/M1_A4" "M1_A4" U3 35 -Net 402 "/FPGA Spartan6/M1_A3" "M1_A3" - U3 32 + U1 F20 +Net 394 "/DDR Banks/M1_A3" "M1_A3" U1 G20 -Net 403 "/FPGA Spartan6/M1_A2" "M1_A2" - U3 31 + U3 32 +Net 395 "/FPGA Spartan6/M1_A2" "M1_A2" U1 E22 -Net 404 "/FPGA Spartan6/M1_A1" "M1_A1" - U3 30 + U3 31 +Net 396 "/FPGA Spartan6/M1_A1" "M1_A1" U1 F22 -Net 405 "/FPGA Spartan6/M1_A0" "M1_A0" + U3 30 +Net 397 "/FPGA Spartan6/M1_A0" "M1_A0" U3 29 U1 F21 -Net 406 "/FPGA Spartan6/M0_A12" "M0_A12" - U1 D1 +Net 398 "/DDR Banks/M0_A12" "M0_A12" U2 42 -Net 407 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" - U3 65 - U1 V22 -Net 408 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" - U1 V21 - U3 63 -Net 409 "/DDR Banks/M1_DQ13" "M1_DQ13" - U3 62 - U1 U22 -Net 410 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" - U3 60 - U1 U20 -Net 411 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" - U3 59 - U1 R22 -Net 412 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" - U1 R20 - U3 57 -Net 413 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" - U3 56 - U1 P22 -Net 414 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" - U3 54 - U1 P21 -Net 415 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" - U1 K22 - U3 13 -Net 416 "/DDR Banks/M1_DQ6" "M1_DQ6" - U3 11 - U1 K21 -Net 417 "/DDR Banks/M1_DQ5" "M1_DQ5" - U3 10 - U1 J22 -Net 418 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" - U3 8 - U1 J20 -Net 419 "/DDR Banks/M1_DQ3" "M1_DQ3" - U3 7 - U1 M22 -Net 420 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" - U3 5 - U1 M21 -Net 421 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" - U1 N22 - U3 4 -Net 422 "/DDR Banks/M1_DQ0" "M1_DQ0" - U3 2 - U1 N20 -Net 423 "/FPGA Spartan6/M1_A12" "M1_A12" - U3 42 - U1 D22 -Net 424 "/DDR Banks/M1_A11" "M1_A11" - U1 F19 - U3 41 -Net 425 "/DDR Banks/M1_A10" "M1_A10" - U3 28 - U1 G19 -Net 426 "/DDR Banks/M0_DQ10" "M0_DQ10" - U2 57 - U1 R3 -Net 427 "/DDR Banks/M0_DQ9" "M0_DQ9" - U2 56 - U1 P1 -Net 428 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" - U2 54 - U1 P2 -Net 429 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" - U1 K1 - U2 13 -Net 430 "/DDR Banks/M0_DQ6" "M0_DQ6" - U2 11 - U1 K2 -Net 431 "/DDR Banks/M0_DQ5" "M0_DQ5" - U1 J1 - U2 10 -Net 432 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" - U2 8 - U1 J3 -Net 433 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" - U2 7 - U1 M1 -Net 434 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" - U2 5 - U1 M2 -Net 435 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" - U2 4 - U1 N1 -Net 436 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" - U1 N3 - U2 2 -Net 437 "/FPGA Spartan6/M0_A11" "M0_A11" + U1 D1 +Net 399 "/FPGA Spartan6/M0_A11" "M0_A11" U1 C1 U2 41 -Net 438 "/DDR Banks/M0_A10" "M0_A10" +Net 400 "/DDR Banks/M0_A10" "M0_A10" U2 28 U1 G4 -Net 439 "/FPGA Spartan6/M0_A9" "M0_A9" - U2 40 +Net 401 "/DDR Banks/M1_DQ15" "M1_DQ15" + U1 V22 + U3 65 +Net 402 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" + U3 63 + U1 V21 +Net 403 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" + U1 U22 + U3 62 +Net 404 "/DDR Banks/M1_DQ12" "M1_DQ12" + U3 60 + U1 U20 +Net 405 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" + U1 R22 + U3 59 +Net 406 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" + U1 R20 + U3 57 +Net 407 "/DDR Banks/M1_DQ9" "M1_DQ9" + U3 56 + U1 P22 +Net 408 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" + U3 54 + U1 P21 +Net 409 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" + U3 13 + U1 K22 +Net 410 "/DDR Banks/M1_DQ6" "M1_DQ6" + U1 K21 + U3 11 +Net 411 "/DDR Banks/M1_DQ5" "M1_DQ5" + U3 10 + U1 J22 +Net 412 "/DDR Banks/M1_DQ4" "M1_DQ4" + U1 J20 + U3 8 +Net 413 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" + U3 7 + U1 M22 +Net 414 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" + U3 5 + U1 M21 +Net 415 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" + U3 4 + U1 N22 +Net 416 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" + U3 2 + U1 N20 +Net 417 "/FPGA Spartan6/M1_A12" "M1_A12" + U3 42 + U1 D22 +Net 418 "/FPGA Spartan6/M1_A11" "M1_A11" + U3 41 + U1 F19 +Net 419 "/FPGA Spartan6/M1_A10" "M1_A10" + U3 28 + U1 G19 +Net 420 "/DDR Banks/M1_A9" "M1_A9" + U3 40 + U1 C22 +Net 421 "/DDR Banks/M0_DQ7" "M0_DQ7" + U2 13 + U1 K1 +Net 422 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" + U1 K2 + U2 11 +Net 423 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" + U2 10 + U1 J1 +Net 424 "/DDR Banks/M0_DQ4" "M0_DQ4" + U2 8 + U1 J3 +Net 425 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" + U1 M1 + U2 7 +Net 426 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" + U2 5 + U1 M2 +Net 427 "/DDR Banks/M0_DQ1" "M0_DQ1" + U1 N1 + U2 4 +Net 428 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" + U1 N3 + U2 2 +Net 429 "/FPGA Spartan6/M0_A9" "M0_A9" U1 E1 -Net 440 "/FPGA Spartan6/M0_A8" "M0_A8" + U2 40 +Net 430 "/FPGA Spartan6/M0_A8" "M0_A8" U2 39 U1 E3 -Net 441 "/DDR Banks/M0_A7" "M0_A7" +Net 431 "/FPGA Spartan6/M0_A7" "M0_A7" U1 H6 U2 38 -Net 442 "/FPGA Spartan6/M0_A6" "M0_A6" - U1 J4 +Net 432 "/DDR Banks/M0_A6" "M0_A6" U2 37 -Net 443 "/DDR Banks/M0_A5" "M0_A5" - U1 K3 + U1 J4 +Net 433 "/FPGA Spartan6/M0_A5" "M0_A5" U2 36 -Net 444 "/FPGA Spartan6/M0_A4" "M0_A4" - U1 F3 + U1 K3 +Net 434 "/FPGA Spartan6/M0_A4" "M0_A4" U2 35 -Net 445 "/FPGA Spartan6/M0_A3" "M0_A3" - U1 K6 + U1 F3 +Net 435 "/DDR Banks/M0_A3" "M0_A3" U2 32 -Net 446 "/FPGA Spartan6/M0_A2" "M0_A2" - U1 H5 + U1 K6 +Net 436 "/FPGA Spartan6/M0_A2" "M0_A2" U2 31 -Net 447 "/FPGA Spartan6/M0_A1" "M0_A1" + U1 H5 +Net 437 "/FPGA Spartan6/M0_A1" "M0_A1" U2 30 U1 H1 -Net 448 "/FPGA Spartan6/M0_A0" "M0_A0" - U1 H2 +Net 438 "/FPGA Spartan6/M0_A0" "M0_A0" U2 29 -Net 449 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" - U2 65 + U1 H2 +Net 439 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" U1 V1 -Net 450 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" - U1 V2 + U2 65 +Net 440 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" U2 63 -Net 451 "/DDR Banks/M0_DQ13" "M0_DQ13" + U1 V2 +Net 441 "/DDR Banks/M0_DQ13" "M0_DQ13" U1 U1 U2 62 -Net 452 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" +Net 442 "/DDR Banks/M0_DQ12" "M0_DQ12" U1 U3 U2 60 -Net 453 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" +Net 443 "/DDR Banks/M0_DQ11" "M0_DQ11" U1 R1 U2 59 +Net 444 "/DDR Banks/M0_DQ10" "M0_DQ10" + U2 57 + U1 R3 +Net 445 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" + U2 56 + U1 P1 +Net 446 "/DDR Banks/M0_DQ8" "M0_DQ8" + U1 P2 + U2 54 } #End diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 30b77d8..221abff 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -56,109 +56,125 @@ Comment3 "" Comment4 "" $EndDescr Wire Wire Line - 10600 6800 9300 6800 + 10650 3950 9300 3950 +Wire Wire Line + 10650 3750 9300 3750 +Wire Wire Line + 10650 3650 9300 3650 +Wire Wire Line + 10650 3450 9300 3450 Wire Bus Line - 9300 3100 10650 3100 + 10650 4050 9300 4050 Wire Wire Line - 9300 2900 10650 2900 + 10600 6700 9300 6700 Wire Wire Line - 10650 5400 9300 5400 -Wire Wire Line - 10650 5200 9300 5200 -Wire Wire Line - 10650 5000 9300 5000 -Wire Wire Line - 9300 7800 10600 7800 -Wire Wire Line - 9300 7400 10600 7400 -Wire Wire Line - 10600 6900 9300 6900 -Wire Wire Line - 9300 6500 10600 6500 + 9300 3000 10650 3000 Wire Bus Line - 4700 3150 5950 3150 -Wire Wire Line - 4700 2800 5950 2800 -Wire Wire Line - 4700 3750 5950 3750 -Wire Wire Line - 4700 3900 5950 3900 -Wire Wire Line - 4700 4250 5950 4250 -Wire Wire Line - 4700 5950 5950 5950 -Wire Wire Line - 4700 6550 5950 6550 + 10600 7200 9300 7200 Wire Bus Line - 4700 5250 5950 5250 + 9300 7600 10600 7600 Wire Wire Line - 4700 6300 5950 6300 -Wire Wire Line - 4700 5700 5950 5700 -Wire Wire Line - 4700 5400 5950 5400 -Wire Bus Line - 4700 3050 5950 3050 -Wire Wire Line - 5950 4100 4700 4100 -Wire Wire Line - 4700 6150 5950 6150 -Wire Bus Line - 5950 5100 5950 5050 -Wire Bus Line - 5950 5050 4700 5050 -Wire Wire Line - 4700 6050 5950 6050 -Wire Wire Line - 4700 4000 5950 4000 -Wire Bus Line - 4700 5150 5950 5150 -Wire Wire Line - 4700 5800 5950 5800 -Wire Wire Line - 4700 5500 5950 5500 -Wire Wire Line - 4700 6400 5950 6400 -Wire Wire Line - 4700 4900 5950 4900 -Wire Wire Line - 4700 4350 5950 4350 -Wire Wire Line - 4700 4500 5950 4500 -Wire Wire Line - 4700 3650 5950 3650 -Wire Wire Line - 4700 3450 5950 3450 -Wire Wire Line - 4700 3350 5950 3350 -Wire Bus Line - 4700 2950 5950 2950 -Wire Wire Line - 9300 6350 10600 6350 -Wire Wire Line - 9300 6600 10600 6600 -Wire Wire Line - 9300 7000 10600 7000 -Wire Wire Line - 9300 7300 10600 7300 -Wire Wire Line - 9300 7500 10600 7500 -Wire Wire Line - 9300 7700 10600 7700 -Wire Wire Line - 9300 7900 10600 7900 + 10650 5300 9300 5300 Wire Wire Line 10650 5100 9300 5100 Wire Wire Line - 10650 5300 9300 5300 -Wire Bus Line - 9300 7600 10600 7600 -Wire Bus Line - 10600 7200 9300 7200 + 9300 7900 10600 7900 Wire Wire Line - 9300 3000 10650 3000 + 9300 7700 10600 7700 Wire Wire Line - 10600 6700 9300 6700 + 9300 7500 10600 7500 +Wire Wire Line + 9300 7300 10600 7300 +Wire Wire Line + 9300 7000 10600 7000 +Wire Wire Line + 9300 6600 10600 6600 +Wire Wire Line + 9300 6350 10600 6350 +Wire Bus Line + 4700 2950 5950 2950 +Wire Wire Line + 4700 3350 5950 3350 +Wire Wire Line + 4700 3450 5950 3450 +Wire Wire Line + 4700 3650 5950 3650 +Wire Wire Line + 4700 4500 5950 4500 +Wire Wire Line + 4700 4350 5950 4350 +Wire Wire Line + 4700 4900 5950 4900 +Wire Wire Line + 4700 6400 5950 6400 +Wire Wire Line + 4700 5500 5950 5500 +Wire Wire Line + 4700 5800 5950 5800 +Wire Bus Line + 4700 5150 5950 5150 +Wire Wire Line + 4700 4000 5950 4000 +Wire Wire Line + 4700 6050 5950 6050 +Wire Bus Line + 4700 5050 5950 5050 +Wire Bus Line + 5950 5050 5950 5100 +Wire Wire Line + 4700 6150 5950 6150 +Wire Wire Line + 5950 4100 4700 4100 +Wire Bus Line + 4700 3050 5950 3050 +Wire Wire Line + 4700 5400 5950 5400 +Wire Wire Line + 4700 5700 5950 5700 +Wire Wire Line + 4700 6300 5950 6300 +Wire Bus Line + 4700 5250 5950 5250 +Wire Wire Line + 4700 6550 5950 6550 +Wire Wire Line + 4700 5950 5950 5950 +Wire Wire Line + 4700 4250 5950 4250 +Wire Wire Line + 4700 3900 5950 3900 +Wire Wire Line + 4700 3750 5950 3750 +Wire Wire Line + 4700 2800 5950 2800 +Wire Bus Line + 4700 3150 5950 3150 +Wire Wire Line + 9300 6500 10600 6500 +Wire Wire Line + 10600 6900 9300 6900 +Wire Wire Line + 9300 7400 10600 7400 +Wire Wire Line + 9300 7800 10600 7800 +Wire Wire Line + 10650 5000 9300 5000 +Wire Wire Line + 10650 5200 9300 5200 +Wire Wire Line + 10650 5400 9300 5400 +Wire Wire Line + 9300 2900 10650 2900 +Wire Bus Line + 9300 3100 10650 3100 +Wire Wire Line + 10600 6800 9300 6800 +Wire Wire Line + 10650 3350 9300 3350 +Wire Wire Line + 9300 3550 10650 3550 +Wire Wire Line + 10650 3850 9300 3850 $Sheet S 10650 4800 1150 750 U 4C5F1EDC @@ -228,6 +244,7 @@ F49 "SD_CMD" B R 9300 3000 60 F50 "SD_DAT[0..3]" B R 9300 3100 60 F51 "ETH_CRS" I R 9300 6700 60 F52 "ETH_COL" I R 9300 6800 60 +F53 "ND_D[0..7]" B R 9300 4050 60 $EndSheet $Sheet S 10600 6250 1300 1800 @@ -258,8 +275,14 @@ F1 "NV_MEMORIES.sch" 60 F2 "SD_CMD" I L 10650 3000 60 F3 "SD_CLK" I L 10650 2900 60 F4 "SD_DAT[0..3]" B L 10650 3100 60 -F5 "D[0..15]" B L 10650 3450 60 -F6 "FWE_N" B L 10650 3750 60 +F5 "NF_D[0..7]" B L 10650 4050 60 +F6 "FWE_N" B L 10650 3450 60 +F7 "NF_ALE" B L 10650 3550 60 +F8 "NF_CLE" B L 10650 3650 60 +F9 "NF_WE_N" B L 10650 3750 60 +F10 "NF_CS1_N" B L 10650 3350 60 +F11 "NF_RE_N" B L 10650 3850 60 +F12 "NF_RNB" B L 10650 3950 60 $EndSheet $Sheet S 3600 2700 1100 4000