From b22aa62b24765398eb50ac5a57f2780388f4a4ed Mon Sep 17 00:00:00 2001 From: Juan64Bits Date: Mon, 9 Aug 2010 15:37:18 -0500 Subject: [PATCH] Ethernet-phy and USB connected to FPGA --- kicad/xue-rnc/DRAM.sch | 2 +- kicad/xue-rnc/FPGA.sch | 321 ++-- kicad/xue-rnc/NV_MEMORIES.sch | 2 +- kicad/xue-rnc/USB.sch | 139 +- kicad/xue-rnc/eth_phy.sch | 566 +++---- kicad/xue-rnc/xue-rnc.brd | 2612 +++++++++++++++++++++++-------- kicad/xue-rnc/xue-rnc.cache.dcm | 2 +- kicad/xue-rnc/xue-rnc.cache.lib | 8 +- kicad/xue-rnc/xue-rnc.cmp | 122 +- kicad/xue-rnc/xue-rnc.net | 2324 +++++++++++++++++---------- kicad/xue-rnc/xue-rnc.pro | 105 +- kicad/xue-rnc/xue-rnc.sch | 185 ++- 12 files changed, 4303 insertions(+), 2085 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 8c7713a..623fefd 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 08 Aug 2010 05:52:09 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 03:34:05 PM COT LIBS:power,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./xue-rnc.cache EELAYER 24 0 EELAYER END diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 02a9912..33c8794 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,46 +1,9 @@ -EESchema Schematic File Version 2 date Sun 08 Aug 2010 10:51:44 PM COT -LIBS:power -LIBS:rj45-48025 -LIBS:xue-nv -LIBS:xc6slx75fgg484 -LIBS:xc6slx45fgg484 -LIBS:micron_mobile_ddr -LIBS:micron_ddr_512Mb -LIBS:k8001 -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:xue-rnc-cache +EESchema Schematic File Version 2 date Mon 09 Aug 2010 03:34:05 PM COT +LIBS:power,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./xue-rnc.cache EELAYER 24 0 EELAYER END $Descr A2 23400 16535 -Sheet 4 6 +Sheet 2 6 Title "" Date "9 aug 2010" Rev "" @@ -50,6 +13,32 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Wire Line + 16350 11000 16400 11000 +Wire Wire Line + 16350 10800 16400 10800 +Wire Wire Line + 16400 10600 15100 10600 +Wire Wire Line + 16400 10400 15100 10400 +Wire Wire Line + 16350 10200 16400 10200 +Wire Wire Line + 16350 10000 16400 10000 +Wire Wire Line + 16400 9800 15100 9800 +Wire Wire Line + 16400 9600 15100 9600 +Wire Wire Line + 16350 9400 16400 9400 +Wire Wire Line + 16350 9200 16400 9200 +Wire Wire Line + 19800 9300 19900 9300 +Wire Wire Line + 19800 9100 19900 9100 +Wire Bus Line + 15000 9850 15000 9450 Wire Wire Line 20350 4450 20800 4450 Wire Wire Line @@ -264,24 +253,24 @@ Wire Wire Line 7300 6300 7300 6350 Wire Wire Line 7100 6350 7100 6300 -Connection ~ 13900 6300 +Connection ~ 18100 8550 Wire Wire Line - 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2 13900 7850 +P 18100 10100 +F 0 "U1" H 18100 10200 70 0000 C CNN +F 1 "XC6SLX45FGG484" H 18100 10000 70 0000 C CNN + 2 18100 10100 1 0 0 -1 $EndComp $EndSCHEMATC diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 6bdd808..405ddd4 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 08 Aug 2010 05:52:09 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 03:34:05 PM COT LIBS:power,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./xue-rnc.cache EELAYER 24 0 EELAYER END diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 8d4a5e7..4bd8bbf 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,9 +1,9 @@ -EESchema Schematic File Version 2 date Sun 08 Aug 2010 05:52:09 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 03:34:05 PM COT LIBS:power,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./xue-rnc.cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 2 6 +Sheet 3 6 Title "" Date "" Rev "" @@ -13,90 +13,129 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Connection ~ 2150 3900 Wire Wire Line - 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H 1850 2250 60 0000 C CNN +F 0 "U6" H 1850 2250 60 0000 C CNN F 1 "MIC2550AYTS" H 2000 3150 60 0000 C CNN 1 2000 2750 1 0 0 -1 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 94f59dc..bfbe1bf 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,9 +1,9 @@ -EESchema Schematic File Version 2 date Sun 08 Aug 2010 05:52:09 PM COT +EESchema Schematic File Version 2 date Mon 09 Aug 2010 03:34:05 PM COT LIBS:power,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./xue-rnc.cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 3 6 +Sheet 4 6 Title "" Date "4 aug 2010" Rev "" @@ -14,299 +14,301 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-Wire Wire Line - 3800 5850 3150 5850 -Wire Wire Line - 3150 4700 3700 4700 -Wire Wire Line - 3700 4700 3700 4650 -Wire Wire Line - 3700 4650 3800 4650 -Wire Wire Line - 8500 5700 7850 5700 -Wire Wire Line - 9200 5600 9400 5600 -Wire Wire Line - 9400 5800 9200 5800 -Wire Wire Line - 9400 5700 9000 5700 -Wire Wire Line - 5600 5750 6700 5750 -Wire Wire Line - 6700 5750 6700 5350 -Wire Wire Line - 6700 5350 9400 5350 -Connection ~ 9150 4950 -Wire Wire Line - 8900 4950 9400 4950 -Connection ~ 9200 4850 -Wire Wire Line - 8900 4850 9400 4850 -Wire Wire Line - 9400 4750 5600 4750 -Wire Wire Line - 3700 5650 3800 5650 -Wire Wire Line - 3700 4450 3800 4450 -Wire Wire Line - 3800 4550 3700 4550 -Wire Wire Line - 3800 5050 3750 5050 -Wire Bus Line - 6500 6150 6500 6450 -Wire Wire Line - 5600 6050 6400 6050 -Wire Wire Line - 5600 5850 5650 5850 -Wire Wire Line - 5600 5250 6400 5250 -Wire Wire Line - 5600 5050 6400 5050 -Wire Bus Line - 6650 4950 6500 4950 -Wire Wire Line - 5600 4850 5650 4850 -Connection ~ 4800 6650 -Wire Wire Line - 4800 6550 4800 6650 -Connection ~ 4600 6650 -Wire Wire Line - 4600 6550 4600 6650 -Wire Wire Line - 5000 6550 5000 6650 -Wire Wire Line - 5000 6650 4400 6650 -Wire Wire Line - 4400 6650 4400 6550 -Wire Wire Line - 4500 6550 4500 6650 -Connection ~ 4500 6650 -Connection ~ 4700 6650 -Wire Wire Line - 4900 6650 4900 6550 -Connection ~ 4900 6650 -Wire Wire Line - 5600 4450 6050 4450 -Wire Wire Line - 5600 4950 5650 4950 -Wire Bus Line - 6500 4950 6500 5250 -Wire Wire Line - 5600 5450 5650 5450 -Wire Wire Line - 5600 5150 6400 5150 -Wire Wire Line - 5600 5350 6400 5350 -Wire Wire Line - 5650 5950 5600 5950 -Wire Wire Line - 6400 6150 5600 6150 -Wire Bus Line - 6500 6450 6650 6450 -Wire Wire Line - 3700 4350 3800 4350 -Wire Wire Line - 3800 5750 3700 5750 -Wire Wire Line - 9400 4650 5600 4650 -Wire Wire Line - 9400 5150 9200 5150 -Wire Wire Line - 9200 5150 9200 4850 -Wire Wire Line - 9400 5050 9150 5050 -Wire Wire Line - 9150 5050 9150 4950 -Wire Wire Line - 6600 5250 6600 5650 -Wire Wire Line - 6600 5250 9400 5250 -Wire Wire Line - 6600 5650 5600 5650 -Wire Wire Line - 9400 5900 9000 5900 -Wire Wire Line - 9200 5800 9200 5500 -Wire Wire Line - 9200 5500 8950 5500 -Connection ~ 9200 5600 -Wire Wire Line - 7850 5900 8500 5900 -Wire Wire Line - 3800 4750 3750 4750 -Wire Wire Line - 3750 4750 3750 4800 -Wire Wire Line - 3750 4800 3150 4800 -Wire Wire Line - 3800 5950 3150 5950 -Wire Wire Line - 5850 6350 6400 6350 -Wire Wire Line - 8250 3900 8250 3800 -Connection ~ 8250 3800 -Wire Wire Line - 8150 3750 8150 3800 -Connection ~ 8150 3800 -Wire Wire Line - 8050 4400 8050 4750 -Connection ~ 8050 4750 -Wire Wire Line - 8450 4400 8450 5350 -Connection ~ 8450 5350 -Wire Wire Line - 4800 3950 4800 3850 -Wire Wire Line - 4800 3850 4900 3850 -Wire Wire Line - 4900 3850 4900 3950 -Wire Wire Line - 10250 5800 10500 5800 -Wire Wire Line - 10500 5800 10500 6000 -Wire Wire Line - 10500 6650 10500 6500 -Wire Wire Line - 5600 6950 5600 6900 -Wire Wire Line - 5600 6900 5300 6900 -Wire Wire Line - 5300 6900 5300 6950 -Wire Wire Line - 5450 7500 5450 7400 -Connection ~ 5450 7400 -Wire Wire Line - 3800 5550 3650 5550 -Wire Wire Line - 3650 5150 3650 5300 -Wire Wire Line - 2850 1100 2850 1150 -Connection ~ 2850 1100 -Wire Wire Line - 1600 1100 1600 1150 -Connection ~ 1900 1100 -Wire Wire Line - 1600 1650 1600 1550 -Wire Wire Line - 2850 1650 2850 1550 -Connection ~ 3150 1650 -Wire Wire Line - 1300 950 1300 1150 -Connection ~ 1300 1100 -Wire Wire Line - 4600 3950 4600 3400 -Wire Wire Line - 3150 1650 1300 1650 -Wire Wire Line - 3150 1100 2700 1100 -Wire Wire Line - 1900 2500 1350 2500 -Wire Wire Line - 2500 2500 3000 2500 + 1650 2950 1650 3050 Wire Wire Line 3800 2500 3600 2500 Wire Wire Line - 1650 2950 1650 3050 -Connection ~ 1650 3050 + 2500 2500 3000 2500 Wire Wire Line - 2750 2550 2750 2100 + 1900 2500 1350 2500 Wire Wire Line - 2750 2100 3500 2100 + 3150 1100 2700 1100 Wire Wire Line - 1350 2550 1350 2100 + 1300 1650 3150 1650 Wire Wire Line - 1350 2100 2050 2100 + 4600 3950 4600 3400 +Connection ~ 1300 1100 Wire Wire Line - 4500 3950 4500 3400 + 1300 950 1300 1150 +Connection ~ 3150 1650 +Wire Wire Line + 2850 1650 2850 1550 +Wire Wire Line + 1600 1650 1600 1550 +Connection ~ 1900 1100 +Wire Wire Line + 1600 1100 1600 1150 +Connection ~ 2850 1100 +Wire Wire Line + 2850 1100 2850 1150 +Wire Wire Line + 3650 5150 3650 5300 +Wire Wire Line + 3800 5550 3650 5550 +Connection ~ 5450 7400 +Wire Wire Line + 5450 7500 5450 7400 +Wire Wire Line + 5300 6950 5300 6900 +Wire Wire Line + 5300 6900 5600 6900 +Wire Wire Line + 5600 6900 5600 6950 +Wire Wire Line + 10500 6650 10500 6500 +Wire Wire Line + 10500 6000 10500 5800 +Wire Wire Line + 10500 5800 10250 5800 +Wire Wire Line + 4900 3950 4900 3850 +Wire Wire Line + 4900 3850 4800 3850 +Wire Wire Line + 4800 3850 4800 3950 +Connection ~ 8450 5350 +Wire Wire Line + 8450 4400 8450 5350 +Connection ~ 8050 4750 +Wire Wire Line + 8050 4400 8050 4750 +Connection ~ 8150 3800 +Wire Wire Line + 8150 3750 8150 3800 +Connection ~ 8250 3800 +Wire Wire Line + 8250 3900 8250 3800 +Wire Wire Line + 5850 6350 6400 6350 +Wire Wire Line + 3800 5950 3150 5950 +Wire Wire Line + 3150 4800 3750 4800 +Wire Wire Line + 3750 4800 3750 4750 +Wire Wire Line + 3750 4750 3800 4750 +Wire Wire Line + 7850 5900 8500 5900 +Connection ~ 9200 5600 +Wire Wire Line + 8950 5500 9200 5500 +Wire Wire Line + 9200 5500 9200 5800 +Wire Wire Line + 9400 5900 9000 5900 +Wire Wire Line + 5600 5650 6600 5650 +Wire Wire Line + 9400 5250 6600 5250 +Wire Wire Line + 6600 5250 6600 5650 +Wire Wire Line + 9150 4950 9150 5050 +Wire Wire Line + 9150 5050 9400 5050 +Wire Wire Line + 9200 4850 9200 5150 +Wire Wire Line + 9200 5150 9400 5150 +Wire Wire Line + 9400 4650 5600 4650 +Wire Wire Line + 3800 5750 3700 5750 +Wire Wire Line + 3700 4350 3800 4350 +Wire Bus Line + 6650 6450 6500 6450 +Wire Wire Line + 6400 6150 5600 6150 +Wire Wire Line + 5650 5950 5600 5950 +Wire Wire Line + 5600 5350 6400 5350 +Wire Wire Line + 5600 5150 6400 5150 +Wire Wire Line + 5600 5450 5650 5450 +Wire Bus Line + 6500 5250 6500 4950 +Wire Wire Line + 5600 4950 5650 4950 +Connection ~ 4900 6650 +Wire Wire Line + 4900 6650 4900 6550 +Connection ~ 4700 6650 +Connection ~ 4500 6650 +Wire Wire Line + 4500 6550 4500 6650 +Wire Wire Line + 4400 6550 4400 6650 +Wire Wire Line + 4400 6650 5000 6650 +Wire Wire Line + 5000 6650 5000 6550 +Wire Wire Line + 4600 6550 4600 6650 +Connection ~ 4600 6650 +Wire Wire Line + 4800 6550 4800 6650 +Connection ~ 4800 6650 +Wire Wire Line + 5600 4850 5650 4850 +Wire Bus Line + 6500 4950 6650 4950 +Wire Wire Line + 5600 5050 6400 5050 +Wire Wire Line + 5600 5250 6400 5250 +Wire Wire Line + 5600 5850 5650 5850 +Wire Wire Line + 5600 6050 6400 6050 +Wire Bus Line + 6500 6450 6500 6150 +Wire Wire Line + 3800 5050 3750 5050 +Wire Wire Line + 3800 4550 3700 4550 +Wire Wire Line + 3700 4450 3800 4450 +Wire Wire Line + 3700 5650 3800 5650 +Wire Wire Line + 9400 4750 5600 4750 +Wire Wire Line + 8900 4850 9400 4850 +Connection ~ 9200 4850 +Wire Wire Line + 8900 4950 9400 4950 +Connection ~ 9150 4950 +Wire Wire Line + 9400 5350 6700 5350 +Wire Wire Line + 6700 5350 6700 5750 +Wire Wire Line + 6700 5750 5600 5750 +Wire Wire Line + 9400 5700 9000 5700 +Wire Wire Line + 9200 5800 9400 5800 +Wire Wire Line + 9200 5600 9400 5600 +Wire Wire Line + 8500 5700 7850 5700 +Wire Wire Line + 3800 4650 3700 4650 +Wire Wire Line + 3700 4650 3700 4700 +Wire Wire Line + 3700 4700 3150 4700 +Wire Wire Line + 3800 5850 3150 5850 +Wire Wire Line + 5850 6250 6400 6250 +Wire Wire Line + 7850 3900 7850 3800 +Wire Wire Line + 7850 3800 8450 3800 +Wire Wire Line + 8450 3800 8450 3900 +Wire Wire Line + 8050 3900 8050 3800 +Connection ~ 8050 3800 +Wire Wire Line + 7850 4400 7850 4650 +Connection ~ 7850 4650 +Wire Wire Line + 8250 4400 8250 5250 +Connection ~ 8250 5250 +Wire Wire Line + 4700 6700 4700 6550 +Wire Wire Line + 4850 3850 4850 3750 +Connection ~ 4850 3850 +Wire Wire Line + 10750 6000 10750 5900 +Connection ~ 10500 5900 +Wire Wire Line + 10750 5900 10250 5900 +Wire Wire Line + 10750 6400 10750 6600 +Wire Wire Line + 10750 6600 10500 6600 +Connection ~ 10500 6600 +Wire Wire Line + 5300 7350 5300 7400 +Wire Wire Line + 5300 7400 5600 7400 +Wire Wire Line + 5600 7400 5600 7350 +Wire Wire Line + 5450 6800 5450 6900 +Connection ~ 5450 6900 +Wire Wire Line + 3150 5550 3100 5550 +Wire Wire Line + 3450 5150 3800 5150 +Connection ~ 3650 5150 +Wire Wire Line + 3150 5300 3100 5300 +Connection ~ 3150 1100 +Wire Wire Line + 1900 1100 1900 1150 +Wire Wire Line + 1300 1100 2100 1100 +Connection ~ 1600 1100 +Wire Wire Line + 1900 1650 1900 1550 +Connection ~ 1600 1650 +Wire Wire Line + 3150 1650 3150 1550 +Connection ~ 2850 1650 +Wire Wire Line + 1300 1750 1300 1550 +Connection ~ 1300 1650 +Connection ~ 1900 1650 +Wire Wire Line + 3150 1150 3150 900 +Wire Wire Line + 3150 900 4000 900 +Wire Wire Line + 1650 2550 1650 2500 +Connection ~ 1650 2500 +Connection ~ 2750 2500 +Wire Wire Line + 3800 2950 3800 3050 +Wire Wire Line + 3800 3050 1350 3050 +Wire Wire Line + 1350 2950 1350 3250 +Wire Wire Line + 2750 2950 2750 3050 +Connection ~ 2750 3050 +Wire Wire Line + 3800 2550 3800 2100 +Wire Wire Line + 3800 2100 4400 2100 +Connection ~ 3800 2500 +Wire Wire Line + 4400 3950 4400 3400 +Wire Wire Line + 4700 3950 4700 3400 +NoConn ~ 5600 4450 +NoConn ~ 5600 5550 Text Label 4700 3400 3 40 ~ 0 ETH_PLL1.8V Text Label 4500 3400 3 40 ~ 0 @@ -664,6 +666,6 @@ Entry Wire Line 6400 5250 6500 5150 Entry Wire Line 6400 5350 6500 5250 -Text HLabel 6050 4450 2 60 Input ~ 0 +Text HLabel 5700 4550 2 60 Input ~ 0 ETH_CLK $EndSCHEMATC diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 063085e..fb741f0 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,26 +1,22 @@ -PCBNEW-BOARD Version 1 date Sun 08 Aug 2010 09:46:38 AM COT - -# Created by Pcbnew(2010-07-15 BZR 2414)-unstable +PCBNEW-BOARD Version 1 date Mon 09 Aug 2010 03:33:55 PM COT $GENERAL LayerCount 4 Ly 1FFF8007 -EnabledLayers 1FFF8007 -Links 233 -NoConn 233 -Di 28232 5405 47187 31125 +Links 288 +NoConn 288 +Di -500 -500 65516 48783 Ndraw 0 Ntrack 0 Nzone 0 -BoardThickness 630 -Nmodule 6 -Nnets 69 +Nmodule 41 +Nnets 110 $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "8 aug 2010" +Date "9 aug 2010" Rev "" Comp "" Comment1 "" @@ -38,20 +34,18 @@ Layer[1] Inner2 signal Layer[2] Inner3 signal Layer[15] Front signal TrackWidth 80 +TrackWidthHistory 80 TrackClearence 100 ZoneClearence 200 -TrackMinWidth 80 DrawSegmWidth 150 EdgeSegmWidth 150 ViaSize 350 ViaDrill 250 -ViaMinSize 350 -ViaMinDrill 200 +ViaAltDrill 250 +ViaSizeHistory 350 MicroViaSize 200 MicroViaDrill 50 MicroViasAllowed 0 -MicroViaMinSize 200 -MicroViaMinDrill 50 TextPcbWidth 120 TextPcbSize 600 800 EdgeModWidth 150 @@ -59,7 +53,6 @@ TextModSize 600 600 TextModWidth 120 PadSize 600 600 PadDrill 320 -Pad2MaskClearance 100 AuxiliaryAxisOrg 0 0 $EndSETUP @@ -68,360 +61,445 @@ Na 0 "" St ~ $EndEQUIPOT $EQUIPOT -Na 1 "/DDR_Banks/M0_A11" +Na 1 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 2 "/DDR_Banks/M0_A2" +Na 2 "/FPGA_Spartan6/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 3 "/DDR_Banks/M0_A6" +Na 3 "N-000122" St ~ $EndEQUIPOT $EQUIPOT -Na 4 "/DDR_Banks/M0_A9" +Na 4 "/DDR_Banks/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/DDR_Banks/M0_BA0" +Na 5 "N-000120" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_BA1" +Na 6 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_CAS#" +Na 7 "N-000121" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_DQ1" +Na 8 "/DDR_Banks/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_DQ12" +Na 9 "/DDR_Banks/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_DQ4" +Na 10 "/DDR_Banks/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_DQ7" +Na 11 "N-000119" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_DQ8" +Na 12 "/DDR_Banks/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_LDM" +Na 13 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_UDQS" +Na 14 "/DDR_Banks/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_WE#" +Na 15 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/Ethernet_Phy/ETH_INT" +Na 16 "/DDR_Banks/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/FPGA_Spartan6/M0_A0" +Na 17 "/DDR_Banks/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/FPGA_Spartan6/M0_A1" +Na 18 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/FPGA_Spartan6/M0_A10" +Na 19 "/DDR_Banks/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/FPGA_Spartan6/M0_A12" +Na 20 "/DDR_Banks/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/FPGA_Spartan6/M0_A3" +Na 21 "/DDR_Banks/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/FPGA_Spartan6/M0_A4" +Na 22 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/FPGA_Spartan6/M0_A5" +Na 23 "/DDR_Banks/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/FPGA_Spartan6/M0_A7" +Na 24 "/DDR_Banks/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/FPGA_Spartan6/M0_A8" +Na 25 "/DDR_Banks/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/FPGA_Spartan6/M0_CKE" +Na 26 "/DDR_Banks/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/FPGA_Spartan6/M0_CLK" +Na 27 "/DDR_Banks/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/FPGA_Spartan6/M0_CLK#" +Na 28 "/DDR_Banks/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/FPGA_Spartan6/M0_DQ0" +Na 29 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/FPGA_Spartan6/M0_DQ10" +Na 30 "/DDR_Banks/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/FPGA_Spartan6/M0_DQ11" +Na 31 "/DDR_Banks/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/FPGA_Spartan6/M0_DQ13" +Na 32 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/FPGA_Spartan6/M0_DQ14" +Na 33 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/FPGA_Spartan6/M0_DQ15" +Na 34 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/FPGA_Spartan6/M0_DQ2" +Na 35 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/FPGA_Spartan6/M0_DQ3" +Na 36 "/DDR_Banks/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/FPGA_Spartan6/M0_DQ5" +Na 37 "/DDR_Banks/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/FPGA_Spartan6/M0_DQ6" +Na 38 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/FPGA_Spartan6/M0_DQ9" +Na 39 "/DDR_Banks/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/FPGA_Spartan6/M0_LDQS" +Na 40 "N-000118" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/FPGA_Spartan6/M0_RAS#" +Na 41 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/FPGA_Spartan6/M0_UDM" +Na 42 "/DDR_Banks/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/FPGA_Spartan6/M1_A0" +Na 43 "/DDR_Banks/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/FPGA_Spartan6/M1_A1" +Na 44 "/DDR_Banks/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/FPGA_Spartan6/M1_A10" +Na 45 "/DDR_Banks/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/FPGA_Spartan6/M1_A11" +Na 46 "/DDR_Banks/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/FPGA_Spartan6/M1_A12" +Na 47 "/DDR_Banks/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/FPGA_Spartan6/M1_A2" +Na 48 "/DDR_Banks/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/FPGA_Spartan6/M1_A3" +Na 49 "/DDR_Banks/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/FPGA_Spartan6/M1_A4" +Na 50 "/DDR_Banks/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/FPGA_Spartan6/M1_A5" +Na 51 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Spartan6/M1_A6" +Na 52 "/DDR_Banks/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Spartan6/M1_A7" +Na 53 "/DDR_Banks/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Spartan6/M1_A8" +Na 54 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Spartan6/M1_A9" +Na 55 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/Non_volatile_memories/FRB_N" +Na 56 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "3.3V" +Na 57 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "GND" +Na 58 "/DDR_Banks/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "N-000036" +Na 59 "/DDR_Banks/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "N-000039" +Na 60 "/DDR_Banks/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "N-000106" +Na 61 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "N-000200" +Na 62 "/DDR_Banks/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "N-000201" +Na 63 "/DDR_Banks/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "N-000212" +Na 64 "/DDR_Banks/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "N-000213" +Na 65 "/DDR_Banks/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "N-000214" +Na 66 "/DDR_Banks/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "N-000403" +Na 67 "/DDR_Banks/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "N-000404" +Na 68 "/DDR_Banks/M0_DQ9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 69 "/DDR_Banks/M0_DQ8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 70 "/DDR_Banks/M1_DQ8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 71 "/DDR_Banks/M1_DQ9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 72 "/DDR_Banks/M0_DQ11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 73 "/DDR_Banks/M0_DQ10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 74 "/DDR_Banks/M1_DQ10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 75 "/DDR_Banks/M1_DQ11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 76 "/DDR_Banks/M0_UDQS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 77 "N-000123" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 78 "/DDR_Banks/M1_UDQS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 79 "/DDR_Banks/M0_DQ13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 80 "/DDR_Banks/M0_DQ12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 81 "/DDR_Banks/M1_DQ12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 82 "/DDR_Banks/M1_DQ13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 83 "/DDR_Banks/M0_DQ15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 84 "/DDR_Banks/M0_DQ14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 85 "/DDR_Banks/M1_DQ14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 86 "/DDR_Banks/M1_DQ15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 87 "N-000068" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 88 "/ETH_MDIO" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 89 "/Ethernet_Phy/ETH_PLL1.8V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 90 "N-000391" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 91 "N-000386" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 92 "/Ethernet_Phy/ETH_A3.3V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 93 "N-000384" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 94 "/Ethernet_Phy/ETH_LED0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 95 "/Ethernet_Phy/ETH_LED1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 96 "/Ethernet_Phy/ETH_A1.8V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 97 "N-000385" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 98 "N-000392" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 99 "/Ethernet_Phy/ETH_1.8V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 100 "/Non_volatile_memories/FRB_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 101 "N-000046" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 102 "N-000048" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 103 "N-000409" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 104 "N-000389" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 105 "N-000393" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 106 "N-000411" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 107 "N-000388" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 108 "N-000410" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 109 "N-000412" St ~ $EndEQUIPOT -$NCLASS -Name "Default" -Desc "This is the default net class." -Clearance 100 -TrackWidth 80 -ViaDia 350 -ViaDrill 250 -uViaDia 200 -uViaDrill 50 -AddNet "" -AddNet "/DDR_Banks/M0_A11" -AddNet "/DDR_Banks/M0_A2" -AddNet "/DDR_Banks/M0_A6" -AddNet "/DDR_Banks/M0_A9" -AddNet "/DDR_Banks/M0_BA0" -AddNet "/DDR_Banks/M0_BA1" -AddNet "/DDR_Banks/M0_CAS#" -AddNet "/DDR_Banks/M0_DQ1" -AddNet "/DDR_Banks/M0_DQ12" -AddNet "/DDR_Banks/M0_DQ4" -AddNet "/DDR_Banks/M0_DQ7" -AddNet "/DDR_Banks/M0_DQ8" -AddNet "/DDR_Banks/M0_LDM" -AddNet "/DDR_Banks/M0_UDQS" -AddNet "/DDR_Banks/M0_WE#" -AddNet "/Ethernet_Phy/ETH_INT" -AddNet "/FPGA_Spartan6/M0_A0" -AddNet "/FPGA_Spartan6/M0_A1" -AddNet "/FPGA_Spartan6/M0_A10" -AddNet "/FPGA_Spartan6/M0_A12" -AddNet "/FPGA_Spartan6/M0_A3" -AddNet "/FPGA_Spartan6/M0_A4" -AddNet "/FPGA_Spartan6/M0_A5" -AddNet "/FPGA_Spartan6/M0_A7" -AddNet "/FPGA_Spartan6/M0_A8" -AddNet "/FPGA_Spartan6/M0_CKE" -AddNet "/FPGA_Spartan6/M0_CLK" -AddNet "/FPGA_Spartan6/M0_CLK#" -AddNet "/FPGA_Spartan6/M0_DQ0" -AddNet "/FPGA_Spartan6/M0_DQ10" -AddNet "/FPGA_Spartan6/M0_DQ11" -AddNet "/FPGA_Spartan6/M0_DQ13" -AddNet "/FPGA_Spartan6/M0_DQ14" -AddNet "/FPGA_Spartan6/M0_DQ15" -AddNet "/FPGA_Spartan6/M0_DQ2" -AddNet "/FPGA_Spartan6/M0_DQ3" -AddNet "/FPGA_Spartan6/M0_DQ5" -AddNet "/FPGA_Spartan6/M0_DQ6" -AddNet "/FPGA_Spartan6/M0_DQ9" -AddNet "/FPGA_Spartan6/M0_LDQS" -AddNet "/FPGA_Spartan6/M0_RAS#" -AddNet "/FPGA_Spartan6/M0_UDM" -AddNet "/FPGA_Spartan6/M1_A0" -AddNet "/FPGA_Spartan6/M1_A1" -AddNet "/FPGA_Spartan6/M1_A10" -AddNet "/FPGA_Spartan6/M1_A11" -AddNet "/FPGA_Spartan6/M1_A12" -AddNet "/FPGA_Spartan6/M1_A2" -AddNet "/FPGA_Spartan6/M1_A3" -AddNet "/FPGA_Spartan6/M1_A4" -AddNet "/FPGA_Spartan6/M1_A5" -AddNet "/FPGA_Spartan6/M1_A6" -AddNet "/FPGA_Spartan6/M1_A7" -AddNet "/FPGA_Spartan6/M1_A8" -AddNet "/FPGA_Spartan6/M1_A9" -AddNet "/Non_volatile_memories/FRB_N" -AddNet "3.3V" -AddNet "GND" -AddNet "N-000036" -AddNet "N-000039" -AddNet "N-000106" -AddNet "N-000200" -AddNet "N-000201" -AddNet "N-000212" -AddNet "N-000213" -AddNet "N-000214" -AddNet "N-000403" -AddNet "N-000404" -$EndNCLASS $MODULE FGG484bga-p10 -Po 38000 14500 0 15 4C4325AE 4C4328D9 ~~ +Po 56450 33930 0 15 4C4325AE 4C431E53 ~~ Li FGG484bga-p10 -Sc 4C4328D9 +Sc 4C431E53 AR /4C431A63/4C431E53 Op 0 0 0 At SMD @@ -439,7 +517,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -4133 -4133 $EndPAD $PAD @@ -467,7 +545,7 @@ $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/Ethernet_Phy/ETH_INT" +Ne 2 "/FPGA_Spartan6/ETH_INT" Po -2558 -4133 $EndPAD $PAD @@ -586,7 +664,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 4133 -4133 $EndPAD $PAD @@ -614,14 +692,14 @@ $PAD Sh "B4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "N-000214" +Ne 3 "N-000122" Po -2952 -3739 $EndPAD $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -2558 -3739 $EndPAD $PAD @@ -635,7 +713,7 @@ $PAD Sh "B7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "N-000214" +Ne 3 "N-000122" Po -1771 -3739 $EndPAD $PAD @@ -649,7 +727,7 @@ $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -983 -3739 $EndPAD $PAD @@ -663,7 +741,7 @@ $PAD Sh "B11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "N-000214" +Ne 3 "N-000122" Po -196 -3739 $EndPAD $PAD @@ -677,7 +755,7 @@ $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 590 -3739 $EndPAD $PAD @@ -691,7 +769,7 @@ $PAD Sh "B15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "N-000214" +Ne 3 "N-000122" Po 1377 -3739 $EndPAD $PAD @@ -705,7 +783,7 @@ $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 2165 -3739 $EndPAD $PAD @@ -719,7 +797,7 @@ $PAD Sh "B19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "N-000214" +Ne 3 "N-000122" Po 2952 -3739 $EndPAD $PAD @@ -747,14 +825,14 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "/DDR_Banks/M0_A11" +Ne 4 "/DDR_Banks/M0_A11" Po -4133 -3346 $EndPAD $PAD Sh "C2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -3739 -3346 $EndPAD $PAD @@ -880,35 +958,35 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 6 "/DDR_Banks/M1_A8" Po 3346 -3346 $EndPAD $PAD Sh "C21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "N-000106" +Ne 7 "N-000121" Po 3739 -3346 $EndPAD $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 8 "/DDR_Banks/M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/FPGA_Spartan6/M0_A12" +Ne 9 "/DDR_Banks/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/FPGA_Spartan6/M0_CKE" +Ne 10 "/DDR_Banks/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -922,7 +1000,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1006,7 +1084,7 @@ $PAD Sh "D16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po 1771 -2952 $EndPAD $PAD @@ -1020,7 +1098,7 @@ $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 2558 -2952 $EndPAD $PAD @@ -1041,35 +1119,35 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 12 "/DDR_Banks/M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 13 "/DDR_Banks/M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/DDR_Banks/M0_A9" +Ne 14 "/DDR_Banks/M0_A9" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/FPGA_Spartan6/M0_A8" +Ne 15 "/DDR_Banks/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1097,7 +1175,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -1771 -2558 $EndPAD $PAD @@ -1111,7 +1189,7 @@ $PAD Sh "E9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "N-000214" +Ne 3 "N-000122" Po -983 -2558 $EndPAD $PAD @@ -1125,7 +1203,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -196 -2558 $EndPAD $PAD @@ -1139,7 +1217,7 @@ $PAD Sh "E13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "N-000214" +Ne 3 "N-000122" Po 590 -2558 $EndPAD $PAD @@ -1153,7 +1231,7 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 1377 -2558 $EndPAD $PAD @@ -1167,7 +1245,7 @@ $PAD Sh "E17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "N-000214" +Ne 3 "N-000122" Po 2165 -2558 $EndPAD $PAD @@ -1181,28 +1259,28 @@ $PAD Sh "E19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "N-000106" +Ne 7 "N-000121" Po 2952 -2558 $EndPAD $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 16 "/DDR_Banks/M1_A7" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 17 "/DDR_Banks/M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -1216,21 +1294,21 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_WE#" +Ne 18 "/DDR_Banks/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/FPGA_Spartan6/M0_A4" +Ne 19 "/DDR_Banks/M0_A4" Po -3346 -2165 $EndPAD $PAD Sh "F4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -2952 -2165 $EndPAD $PAD @@ -1244,7 +1322,7 @@ $PAD Sh "F6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -2165 -2165 $EndPAD $PAD @@ -1279,7 +1357,7 @@ $PAD Sh "F11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po -196 -2165 $EndPAD $PAD @@ -1335,63 +1413,63 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 20 "/DDR_Banks/M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 21 "/DDR_Banks/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 22 "/DDR_Banks/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 23 "/DDR_Banks/M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_BA1" +Ne 0 "" Po -4133 -1771 $EndPAD $PAD Sh "G2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -3739 -1771 $EndPAD $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_BA0" +Ne 0 "" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/FPGA_Spartan6/M0_A10" +Ne 24 "/DDR_Banks/M0_A10" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -2558 -1771 $EndPAD $PAD @@ -1426,7 +1504,7 @@ $PAD Sh "G10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "N-000214" +Ne 3 "N-000122" Po -590 -1771 $EndPAD $PAD @@ -1440,7 +1518,7 @@ $PAD Sh "G12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po 196 -1771 $EndPAD $PAD @@ -1454,7 +1532,7 @@ $PAD Sh "G14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "N-000214" +Ne 3 "N-000122" Po 983 -1771 $EndPAD $PAD @@ -1482,28 +1560,28 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 25 "/DDR_Banks/M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 26 "/DDR_Banks/M1_A3" Po 3346 -1771 $EndPAD $PAD Sh "G21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "N-000106" +Ne 7 "N-000121" Po 3739 -1771 $EndPAD $PAD @@ -1517,49 +1595,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/FPGA_Spartan6/M0_A1" +Ne 27 "/DDR_Banks/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/FPGA_Spartan6/M0_A0" +Ne 28 "/DDR_Banks/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/FPGA_Spartan6/M0_CLK#" +Ne 29 "/DDR_Banks/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/FPGA_Spartan6/M0_CLK" +Ne 30 "/DDR_Banks/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/DDR_Banks/M0_A2" +Ne 31 "/DDR_Banks/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/FPGA_Spartan6/M0_A7" +Ne 32 "/DDR_Banks/M0_A7" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -1771 -1377 $EndPAD $PAD @@ -1573,7 +1651,7 @@ $PAD Sh "H9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po -983 -1377 $EndPAD $PAD @@ -1615,7 +1693,7 @@ $PAD Sh "H15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po 1377 -1377 $EndPAD $PAD @@ -1643,63 +1721,63 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 33 "/DDR_Banks/M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 34 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 35 "/DDR_Banks/M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 36 "/DDR_Banks/M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/FPGA_Spartan6/M0_DQ5" +Ne 37 "/DDR_Banks/M0_DQ5" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_DQ4" +Ne 38 "/DDR_Banks/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/DDR_Banks/M0_A6" +Ne 39 "/DDR_Banks/M0_A6" Po -2952 -983 $EndPAD $PAD Sh "J5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -2558 -983 $EndPAD $PAD @@ -1720,56 +1798,56 @@ $PAD Sh "J8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po -1377 -983 $EndPAD $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -983 -983 $EndPAD $PAD Sh "J10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po -590 -983 $EndPAD $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -196 -983 $EndPAD $PAD Sh "J12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po 196 -983 $EndPAD $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 590 -983 $EndPAD $PAD Sh "J14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po 983 -983 $EndPAD $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 1377 -983 $EndPAD $PAD @@ -1790,77 +1868,77 @@ $PAD Sh "J18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "N-000106" +Ne 7 "N-000121" Po 2558 -983 $EndPAD $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 41 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 42 "/DDR_Banks/M1_DQ4" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 43 "/DDR_Banks/M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_DQ7" +Ne 44 "/DDR_Banks/M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/FPGA_Spartan6/M0_DQ6" +Ne 45 "/DDR_Banks/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/FPGA_Spartan6/M0_A5" +Ne 46 "/DDR_Banks/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_CAS#" +Ne 47 "/DDR_Banks/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/FPGA_Spartan6/M0_RAS#" +Ne 48 "/DDR_Banks/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/FPGA_Spartan6/M0_A3" +Ne 49 "/DDR_Banks/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -1881,49 +1959,49 @@ $PAD Sh "K9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po -983 -590 $EndPAD $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -590 -590 $EndPAD $PAD Sh "K11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po -196 -590 $EndPAD $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 196 -590 $EndPAD $PAD Sh "K13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po 590 -590 $EndPAD $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 983 -590 $EndPAD $PAD Sh "K15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po 1377 -590 $EndPAD $PAD @@ -1951,28 +2029,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 50 "/DDR_Banks/M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 51 "/DDR_Banks/M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 52 "/DDR_Banks/M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 53 "/DDR_Banks/M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -1986,28 +2064,28 @@ $PAD Sh "L2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -3739 -196 $EndPAD $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/FPGA_Spartan6/M0_LDQS" +Ne 54 "/DDR_Banks/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_LDM" +Ne 55 "/DDR_Banks/M0_LDM" Po -2952 -196 $EndPAD $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -2558 -196 $EndPAD $PAD @@ -2021,56 +2099,56 @@ $PAD Sh "L7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -1771 -196 $EndPAD $PAD Sh "L8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po -1377 -196 $EndPAD $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -983 -196 $EndPAD $PAD Sh "L10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po -590 -196 $EndPAD $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -196 -196 $EndPAD $PAD Sh "L12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po 196 -196 $EndPAD $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 590 -196 $EndPAD $PAD Sh "L14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po 983 -196 $EndPAD $PAD @@ -2084,7 +2162,7 @@ $PAD Sh "L16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "N-000106" +Ne 7 "N-000121" Po 1771 -196 $EndPAD $PAD @@ -2098,28 +2176,28 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 56 "/DDR_Banks/M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 57 "/DDR_Banks/M1_LDQS" Po 3346 -196 $EndPAD $PAD Sh "L21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "N-000106" +Ne 7 "N-000121" Po 3739 -196 $EndPAD $PAD @@ -2133,21 +2211,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/FPGA_Spartan6/M0_DQ3" +Ne 58 "/DDR_Banks/M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/FPGA_Spartan6/M0_DQ2" +Ne 59 "/DDR_Banks/M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/FPGA_Spartan6/M0_UDM" +Ne 60 "/DDR_Banks/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2175,7 +2253,7 @@ $PAD Sh "M7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/FPGA_Spartan6/M1_A0" +Ne 0 "" Po -1771 196 $EndPAD $PAD @@ -2189,49 +2267,49 @@ $PAD Sh "M9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po -983 196 $EndPAD $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -590 196 $EndPAD $PAD Sh "M11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po -196 196 $EndPAD $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 196 196 $EndPAD $PAD Sh "M13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po 590 196 $EndPAD $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 983 196 $EndPAD $PAD Sh "M15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po 1377 196 $EndPAD $PAD @@ -2266,42 +2344,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 61 "/DDR_Banks/M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 62 "/DDR_Banks/M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 63 "/DDR_Banks/M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_DQ1" +Ne 64 "/DDR_Banks/M0_DQ1" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/FPGA_Spartan6/M0_DQ0" +Ne 65 "/DDR_Banks/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -2315,70 +2393,70 @@ $PAD Sh "N5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -2558 590 $EndPAD $PAD Sh "N6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/FPGA_Spartan6/M1_A2" +Ne 0 "" Po -2165 590 $EndPAD $PAD Sh "N7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/FPGA_Spartan6/M1_A1" +Ne 0 "" Po -1771 590 $EndPAD $PAD Sh "N8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po -1377 590 $EndPAD $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -983 590 $EndPAD $PAD Sh "N10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po -590 590 $EndPAD $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -196 590 $EndPAD $PAD Sh "N12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po 196 590 $EndPAD $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 590 590 $EndPAD $PAD Sh "N14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po 983 590 $EndPAD $PAD @@ -2399,14 +2477,14 @@ $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 2165 590 $EndPAD $PAD Sh "N18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "N-000106" +Ne 7 "N-000121" Po 2558 590 $EndPAD $PAD @@ -2420,35 +2498,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 66 "/DDR_Banks/M1_DQ0" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 67 "/DDR_Banks/M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/FPGA_Spartan6/M0_DQ9" +Ne 68 "/DDR_Banks/M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_DQ8" +Ne 69 "/DDR_Banks/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -2469,70 +2547,70 @@ $PAD Sh "P5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/M1_A7" +Ne 0 "" Po -2558 983 $EndPAD $PAD Sh "P6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/M1_A8" +Ne 0 "" Po -2165 983 $EndPAD $PAD Sh "P7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/M1_A9" +Ne 0 "" Po -1771 983 $EndPAD $PAD Sh "P8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/FPGA_Spartan6/M1_A10" +Ne 0 "" Po -1377 983 $EndPAD $PAD Sh "P9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po -983 983 $EndPAD $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -590 983 $EndPAD $PAD Sh "P11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po -196 983 $EndPAD $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 196 983 $EndPAD $PAD Sh "P13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po 590 983 $EndPAD $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 983 983 $EndPAD $PAD @@ -2581,35 +2659,35 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 70 "/DDR_Banks/M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 71 "/DDR_Banks/M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/FPGA_Spartan6/M0_DQ11" +Ne 72 "/DDR_Banks/M0_DQ11" Po -4133 1377 $EndPAD $PAD Sh "R2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -3739 1377 $EndPAD $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/FPGA_Spartan6/M0_DQ10" +Ne 73 "/DDR_Banks/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -2623,14 +2701,14 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -2558 1377 $EndPAD $PAD Sh "R6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po -2165 1377 $EndPAD $PAD @@ -2658,7 +2736,7 @@ $PAD Sh "R10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po -590 1377 $EndPAD $PAD @@ -2672,7 +2750,7 @@ $PAD Sh "R12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po 196 1377 $EndPAD $PAD @@ -2686,7 +2764,7 @@ $PAD Sh "R14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "N-000201" +Ne 40 "N-000118" Po 983 1377 $EndPAD $PAD @@ -2714,7 +2792,7 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 2558 1377 $EndPAD $PAD @@ -2728,21 +2806,21 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 74 "/DDR_Banks/M1_DQ10" Po 3346 1377 $EndPAD $PAD Sh "R21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "N-000106" +Ne 7 "N-000121" Po 3739 1377 $EndPAD $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 75 "/DDR_Banks/M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -2756,21 +2834,21 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_UDQS" +Ne 76 "/DDR_Banks/M0_UDQS" Po -3739 1771 $EndPAD $PAD Sh "T3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/M1_A5" +Ne 0 "" Po -3346 1771 $EndPAD $PAD Sh "T4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/M1_A6" +Ne 0 "" Po -2952 1771 $EndPAD $PAD @@ -2805,7 +2883,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po -983 1771 $EndPAD $PAD @@ -2833,7 +2911,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po 590 1771 $EndPAD $PAD @@ -2889,7 +2967,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 78 "/DDR_Banks/M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -2903,35 +2981,35 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/FPGA_Spartan6/M0_DQ13" +Ne 79 "/DDR_Banks/M0_DQ13" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_DQ12" +Ne 80 "/DDR_Banks/M0_DQ12" Po -3346 2165 $EndPAD $PAD Sh "U4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Spartan6/M1_A4" +Ne 0 "" Po -2952 2165 $EndPAD $PAD Sh "U5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -2558 2165 $EndPAD $PAD @@ -2945,7 +3023,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -1771 2165 $EndPAD $PAD @@ -2973,7 +3051,7 @@ $PAD Sh "U11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po -196 2165 $EndPAD $PAD @@ -3022,7 +3100,7 @@ $PAD Sh "U18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "N-000106" +Ne 7 "N-000121" Po 2558 2165 $EndPAD $PAD @@ -3036,49 +3114,49 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 81 "/DDR_Banks/M1_DQ12" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 82 "/DDR_Banks/M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/FPGA_Spartan6/M0_DQ15" +Ne 83 "/DDR_Banks/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/FPGA_Spartan6/M0_DQ14" +Ne 84 "/DDR_Banks/M0_DQ14" Po -3739 2558 $EndPAD $PAD Sh "V3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/FPGA_Spartan6/M1_A3" +Ne 0 "" Po -3346 2558 $EndPAD $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -2952 2558 $EndPAD $PAD @@ -3092,7 +3170,7 @@ $PAD Sh "V6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "N-000200" +Ne 11 "N-000119" Po -2165 2558 $EndPAD $PAD @@ -3106,7 +3184,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po -1377 2558 $EndPAD $PAD @@ -3120,7 +3198,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -590 2558 $EndPAD $PAD @@ -3134,7 +3212,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po 196 2558 $EndPAD $PAD @@ -3148,7 +3226,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 983 2558 $EndPAD $PAD @@ -3162,7 +3240,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po 1771 2558 $EndPAD $PAD @@ -3197,35 +3275,35 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 85 "/DDR_Banks/M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 86 "/DDR_Banks/M1_DQ15" Po 4133 2558 $EndPAD $PAD Sh "W1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/FPGA_Spartan6/M1_A11" +Ne 0 "" Po -4133 2952 $EndPAD $PAD Sh "W2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "N-000212" +Ne 5 "N-000120" Po -3739 2952 $EndPAD $PAD Sh "W3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/FPGA_Spartan6/M1_A12" +Ne 0 "" Po -3346 2952 $EndPAD $PAD @@ -3239,7 +3317,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po -2558 2952 $EndPAD $PAD @@ -3253,7 +3331,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -1771 2952 $EndPAD $PAD @@ -3316,7 +3394,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 1771 2952 $EndPAD $PAD @@ -3337,7 +3415,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 2952 2952 $EndPAD $PAD @@ -3351,7 +3429,7 @@ $PAD Sh "W21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "N-000106" +Ne 7 "N-000121" Po 3739 2952 $EndPAD $PAD @@ -3533,7 +3611,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po -3346 3739 $EndPAD $PAD @@ -3547,7 +3625,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -2558 3739 $EndPAD $PAD @@ -3561,7 +3639,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po -1771 3739 $EndPAD $PAD @@ -3575,7 +3653,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -983 3739 $EndPAD $PAD @@ -3589,7 +3667,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po -196 3739 $EndPAD $PAD @@ -3603,7 +3681,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 590 3739 $EndPAD $PAD @@ -3617,7 +3695,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po 1377 3739 $EndPAD $PAD @@ -3631,7 +3709,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 2165 3739 $EndPAD $PAD @@ -3645,7 +3723,7 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "N-000213" +Ne 77 "N-000123" Po 2952 3739 $EndPAD $PAD @@ -3673,7 +3751,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -4133 4133 $EndPAD $PAD @@ -3820,14 +3898,14 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 $MODULE LQFP48 -Po 34843 7283 0 15 4C433D64 4C433DDA ~~ +Po 53590 25490 0 15 4C433D64 4C432132 ~~ Li LQFP48 -Sc 4C433DDA +Sc 4C432132 AR /4C4320F3/4C432132 Op 0 0 0 At SMD @@ -3842,7 +3920,7 @@ $PAD Sh "12" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "N-000403" +Ne 1 "GND" Po -1613 1082 $EndPAD $PAD @@ -3870,14 +3948,14 @@ $PAD Sh "8" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "N-000403" +Ne 1 "GND" Po -1613 295 $EndPAD $PAD Sh "7" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "N-000404" +Ne 87 "N-000068" Po -1613 98 $EndPAD $PAD @@ -3919,7 +3997,7 @@ $PAD Sh "1" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 88 "/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD @@ -3933,7 +4011,7 @@ $PAD Sh "47" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "N-000404" +Ne 89 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD @@ -3954,7 +4032,7 @@ $PAD Sh "44" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "N-000403" +Ne 1 "GND" Po -295 -1613 $EndPAD $PAD @@ -3975,56 +4053,56 @@ $PAD Sh "41" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 90 "N-000391" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 91 "N-000386" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "N-000403" +Ne 1 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "N-000404" +Ne 92 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 93 "N-000384" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/Ethernet_Phy/ETH_INT" +Ne 2 "/FPGA_Spartan6/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 94 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 95 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4052,21 +4130,21 @@ $PAD Sh "31" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "N-000404" +Ne 96 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 97 "N-000385" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 98 "N-000392" Po 1613 -491 $EndPAD $PAD @@ -4080,21 +4158,21 @@ $PAD Sh "35" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "N-000403" +Ne 1 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "N-000403" +Ne 1 "GND" Po 1613 -1082 $EndPAD $PAD Sh "13" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "N-000404" +Ne 99 "/Ethernet_Phy/ETH_1.8V" Po -1082 1613 $EndPAD $PAD @@ -4164,149 +4242,21 @@ $PAD Sh "23" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "N-000403" +Ne 1 "GND" Po 885 1613 $EndPAD $PAD Sh "24" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "N-000404" +Ne 87 "N-000068" Po 1082 1613 $EndPAD $EndMODULE LQFP48 -$MODULE MICROSD -Po 34449 25394 1800 0 4BD1D28F 4C4390A0 ~~ -Li MICROSD -Sc 4C4390A0 -AR /4C4227FE/4B76F5E2 -Op 0 0 0 -T0 1210 640 157 157 1800 20 M V 20 N"J1" -T1 0 -118 118 118 3600 20 M I 20 N"MICROSD" -DS -3450 -560 -3450 -5420 70 20 -DS -3450 -5420 -3400 -5470 70 20 -DS -3400 -5470 3340 -5470 70 20 -DS 3340 -5470 3340 240 70 20 -DS 3340 240 2330 240 70 20 -DS 2330 240 2330 470 70 20 -DS 2330 470 -2900 470 70 20 -DS -2900 470 -2900 260 70 20 -DS -2900 260 -3460 260 70 20 -DS -3460 260 -3460 -590 70 20 -DS -3610 -5620 -3610 620 10 24 -DS -3610 620 3490 620 10 24 -DS 3490 620 3490 -5620 10 24 -DS 3490 -5620 -3610 -5620 10 24 -$PAD -Sh "1" R 260 620 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 0 "" -Po 880 0 -$EndPAD -$PAD -Sh "2" R 260 620 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 0 "" -Po 450 0 -$EndPAD -$PAD -Sh "3" R 260 620 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 0 "" -Po 20 0 -$EndPAD -$PAD -Sh "4" R 260 620 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 0 "" -Po -420 0 -$EndPAD -$PAD -Sh "5" R 260 620 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 0 "" -Po -850 0 -$EndPAD -$PAD -Sh "6" R 260 620 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 0 "" -Po -1280 0 -$EndPAD -$PAD -Sh "7" R 260 620 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 0 "" -Po -1720 0 -$EndPAD -$PAD -Sh "8" R 260 620 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 0 "" -Po -2150 0 -$EndPAD -$PAD -Sh "CD" R 260 620 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 0 "" -Po -2580 0 -$EndPAD -$PAD -Sh "CASE" R 620 540 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 58 "GND" -Po 2690 -200 -$EndPAD -$PAD -Sh "H1" C 340 340 0 0 1800 -Dr 380 0 0 -At STD N 00C08001 -Ne 0 "" -Po -1950 -4140 -$EndPAD -$PAD -Sh "H2" C 340 340 0 0 1800 -Dr 380 0 0 -At STD N 00C08001 -Ne 0 "" -Po 1200 -4140 -$EndPAD -$PAD -Sh "CASE" R 460 860 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 58 "GND" -Po 3050 -3980 -$EndPAD -$PAD -Sh "CASE" R 460 860 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 58 "GND" -Po -3050 -3980 -$EndPAD -$PAD -Sh "COM" R 460 540 0 0 1800 -Dr 0 0 0 -At SMD N 00440001 -Ne 58 "GND" -Po -3060 -200 -$EndPAD -$EndMODULE MICROSD $MODULE NAND-48TSOP -Po 30906 24803 0 15 4B8F4C98 4C4390A1 ~~ +Po 49356 44233 0 15 4B8F4C98 4B76F108 ~~ Li NAND-48TSOP -Sc 4C4390A1 +Sc 4B76F108 AR /4C4227FE/4B76F108 Op 0 0 0 T0 -1816 4454 157 157 1800 20 N V 21 N"U5" @@ -4563,14 +4513,14 @@ $PAD Sh "6" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/Non_volatile_memories/FRB_N" +Ne 100 "/Non_volatile_memories/FRB_N" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/Non_volatile_memories/FRB_N" +Ne 100 "/Non_volatile_memories/FRB_N" Po -1090 3850 $EndPAD $PAD @@ -4605,14 +4555,14 @@ $PAD Sh "12" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "3.3V" +Ne 87 "N-000068" Po -100 3850 $EndPAD $PAD Sh "13" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 100 3850 $EndPAD $PAD @@ -4654,7 +4604,7 @@ $PAD Sh "19" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "3.3V" +Ne 87 "N-000068" Po 1280 3850 $EndPAD $PAD @@ -4773,14 +4723,14 @@ $PAD Sh "36" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 100 -3850 $EndPAD $PAD Sh "37" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "3.3V" +Ne 87 "N-000068" Po -100 -3850 $EndPAD $PAD @@ -4862,9 +4812,9 @@ Po -2270 -3850 $EndPAD $EndMODULE NAND-48TSOP $MODULE 60fbga_ddr -Po 30906 13780 1800 15 4C58C755 4C58CB97 ~~ +Po 47940 33390 1800 15 4C58C755 4C58C847 ~~ Li 60fbga_ddr -Sc 4C58CB97 +Sc 4C58C847 AR /4C421DD3/4C58C847 Op 0 0 0 At SMD @@ -4879,70 +4829,70 @@ $PAD Sh "A1" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -1259 -2165 $EndPAD $PAD Sh "A9" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 60 "N-000039" +Ne 101 "N-000046" Po 1259 -2165 $EndPAD $PAD Sh "B1" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/FPGA_Spartan6/M0_DQ14" +Ne 84 "/DDR_Banks/M0_DQ14" Po -1259 -1771 $EndPAD $PAD Sh "B9" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_DQ1" +Ne 64 "/DDR_Banks/M0_DQ1" Po 1259 -1771 $EndPAD $PAD Sh "C1" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_DQ12" +Ne 80 "/DDR_Banks/M0_DQ12" Po -1259 -1377 $EndPAD $PAD Sh "C9" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/FPGA_Spartan6/M0_DQ3" +Ne 58 "/DDR_Banks/M0_DQ3" Po 1259 -1377 $EndPAD $PAD Sh "D1" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/FPGA_Spartan6/M0_DQ10" +Ne 73 "/DDR_Banks/M0_DQ10" Po -1259 -983 $EndPAD $PAD Sh "D9" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/FPGA_Spartan6/M0_DQ5" +Ne 37 "/DDR_Banks/M0_DQ5" Po 1259 -983 $EndPAD $PAD Sh "E1" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_DQ8" +Ne 69 "/DDR_Banks/M0_DQ8" Po -1259 -590 $EndPAD $PAD Sh "E9" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_DQ7" +Ne 44 "/DDR_Banks/M0_DQ7" Po 1259 -590 $EndPAD $PAD @@ -4963,217 +4913,217 @@ $PAD Sh "A2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/FPGA_Spartan6/M0_DQ15" +Ne 83 "/DDR_Banks/M0_DQ15" Po -944 -2165 $EndPAD $PAD Sh "A3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -629 -2165 $EndPAD $PAD Sh "A7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 60 "N-000039" +Ne 101 "N-000046" Po 629 -2165 $EndPAD $PAD Sh "A8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/FPGA_Spartan6/M0_DQ0" +Ne 65 "/DDR_Banks/M0_DQ0" Po 944 -2165 $EndPAD $PAD Sh "B2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 60 "N-000039" +Ne 101 "N-000046" Po -944 -1771 $EndPAD $PAD Sh "B3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/FPGA_Spartan6/M0_DQ13" +Ne 79 "/DDR_Banks/M0_DQ13" Po -629 -1771 $EndPAD $PAD Sh "B7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/FPGA_Spartan6/M0_DQ2" +Ne 59 "/DDR_Banks/M0_DQ2" Po 629 -1771 $EndPAD $PAD Sh "B8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 944 -1771 $EndPAD $PAD Sh "C2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -944 -1377 $EndPAD $PAD Sh "C3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/FPGA_Spartan6/M0_DQ11" +Ne 72 "/DDR_Banks/M0_DQ11" Po -629 -1377 $EndPAD $PAD Sh "C7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_DQ4" +Ne 38 "/DDR_Banks/M0_DQ4" Po 629 -1377 $EndPAD $PAD Sh "C8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 60 "N-000039" +Ne 101 "N-000046" Po 944 -1377 $EndPAD $PAD Sh "D2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 60 "N-000039" +Ne 101 "N-000046" Po -944 -983 $EndPAD $PAD Sh "D3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/FPGA_Spartan6/M0_DQ9" +Ne 68 "/DDR_Banks/M0_DQ9" Po -629 -983 $EndPAD $PAD Sh "D7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/FPGA_Spartan6/M0_DQ6" +Ne 45 "/DDR_Banks/M0_DQ6" Po 629 -983 $EndPAD $PAD Sh "D8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 944 -983 $EndPAD $PAD Sh "E2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -944 -590 $EndPAD $PAD Sh "E3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_UDQS" +Ne 76 "/DDR_Banks/M0_UDQS" Po -629 -590 $EndPAD $PAD Sh "E7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/FPGA_Spartan6/M0_LDQS" +Ne 54 "/DDR_Banks/M0_LDQS" Po 629 -590 $EndPAD $PAD Sh "E8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 60 "N-000039" +Ne 101 "N-000046" Po 944 -590 $EndPAD $PAD Sh "F2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -944 -196 $EndPAD $PAD Sh "F3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/FPGA_Spartan6/M0_UDM" +Ne 60 "/DDR_Banks/M0_UDM" Po -629 -196 $EndPAD $PAD Sh "F7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_LDM" +Ne 55 "/DDR_Banks/M0_LDM" Po 629 -196 $EndPAD $PAD Sh "F8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 60 "N-000039" +Ne 101 "N-000046" Po 944 -196 $EndPAD $PAD Sh "G2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/FPGA_Spartan6/M0_CLK" +Ne 30 "/DDR_Banks/M0_CLK" Po -944 196 $EndPAD $PAD Sh "G3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/FPGA_Spartan6/M0_CLK#" +Ne 29 "/DDR_Banks/M0_CLK#" Po -629 196 $EndPAD $PAD Sh "G7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_WE#" +Ne 18 "/DDR_Banks/M0_WE#" Po 629 196 $EndPAD $PAD Sh "G8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_CAS#" +Ne 47 "/DDR_Banks/M0_CAS#" Po 944 196 $EndPAD $PAD Sh "H2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/FPGA_Spartan6/M0_A12" +Ne 9 "/DDR_Banks/M0_A12" Po -944 590 $EndPAD $PAD Sh "H3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/FPGA_Spartan6/M0_CKE" +Ne 10 "/DDR_Banks/M0_CKE" Po -629 590 $EndPAD $PAD Sh "H7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/FPGA_Spartan6/M0_RAS#" +Ne 48 "/DDR_Banks/M0_RAS#" Po 629 590 $EndPAD $PAD @@ -5187,119 +5137,119 @@ $PAD Sh "J2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 1 "/DDR_Banks/M0_A11" +Ne 4 "/DDR_Banks/M0_A11" Po -944 983 $EndPAD $PAD Sh "J3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/DDR_Banks/M0_A9" +Ne 14 "/DDR_Banks/M0_A9" Po -629 983 $EndPAD $PAD Sh "J7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_BA1" +Ne 0 "" Po 629 983 $EndPAD $PAD Sh "J8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_BA0" +Ne 0 "" Po 944 983 $EndPAD $PAD Sh "K2" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/FPGA_Spartan6/M0_A8" +Ne 15 "/DDR_Banks/M0_A8" Po -944 1377 $EndPAD $PAD Sh "K3" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/FPGA_Spartan6/M0_A7" +Ne 32 "/DDR_Banks/M0_A7" Po -629 1377 $EndPAD $PAD Sh "K7" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/FPGA_Spartan6/M0_A0" +Ne 28 "/DDR_Banks/M0_A0" Po 629 1377 $EndPAD $PAD Sh "K8" O 157 157 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/FPGA_Spartan6/M0_A10" +Ne 24 "/DDR_Banks/M0_A10" Po 944 1377 $EndPAD $PAD Sh "L2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/DDR_Banks/M0_A6" +Ne 39 "/DDR_Banks/M0_A6" Po -944 1771 $EndPAD $PAD Sh "L3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/FPGA_Spartan6/M0_A5" +Ne 46 "/DDR_Banks/M0_A5" Po -629 1771 $EndPAD $PAD Sh "L7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/DDR_Banks/M0_A2" +Ne 31 "/DDR_Banks/M0_A2" Po 629 1771 $EndPAD $PAD Sh "L8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/FPGA_Spartan6/M0_A1" +Ne 27 "/DDR_Banks/M0_A1" Po 944 1771 $EndPAD $PAD Sh "M2" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/FPGA_Spartan6/M0_A4" +Ne 19 "/DDR_Banks/M0_A4" Po -944 2165 $EndPAD $PAD Sh "M3" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -629 2165 $EndPAD $PAD Sh "M7" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 60 "N-000039" +Ne 101 "N-000046" Po 629 2165 $EndPAD $PAD Sh "M8" O 157 158 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/FPGA_Spartan6/M0_A3" +Ne 49 "/DDR_Banks/M0_A3" Po 944 2165 $EndPAD $EndMODULE 60fbga_ddr $MODULE 60fbga_ddr -Po 45079 12795 0 15 4C58C755 4C58CB99 ~~ +Po 63529 32225 0 15 4C58C755 4C58CA3A ~~ Li 60fbga_ddr -Sc 4C58CB99 +Sc 4C58CA3A AR /4C421DD3/4C58CA3A Op 0 0 0 At SMD @@ -5314,70 +5264,70 @@ $PAD Sh "A1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -1259 -2165 $EndPAD $PAD Sh "A9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "N-000036" +Ne 102 "N-000048" Po 1259 -2165 $EndPAD $PAD Sh "B1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 85 "/DDR_Banks/M1_DQ14" Po -1259 -1771 $EndPAD $PAD Sh "B9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 67 "/DDR_Banks/M1_DQ1" Po 1259 -1771 $EndPAD $PAD Sh "C1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 81 "/DDR_Banks/M1_DQ12" Po -1259 -1377 $EndPAD $PAD Sh "C9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 63 "/DDR_Banks/M1_DQ3" Po 1259 -1377 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 74 "/DDR_Banks/M1_DQ10" Po -1259 -983 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 43 "/DDR_Banks/M1_DQ5" Po 1259 -983 $EndPAD $PAD Sh "E1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 70 "/DDR_Banks/M1_DQ8" Po -1259 -590 $EndPAD $PAD Sh "E9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 53 "/DDR_Banks/M1_DQ7" Po 1259 -590 $EndPAD $PAD @@ -5398,217 +5348,217 @@ $PAD Sh "A2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 86 "/DDR_Banks/M1_DQ15" Po -944 -2165 $EndPAD $PAD Sh "A3" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -629 -2165 $EndPAD $PAD Sh "A7" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "N-000036" +Ne 102 "N-000048" Po 629 -2165 $EndPAD $PAD Sh "A8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 66 "/DDR_Banks/M1_DQ0" Po 944 -2165 $EndPAD $PAD Sh "B2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "N-000036" +Ne 102 "N-000048" Po -944 -1771 $EndPAD $PAD Sh "B3" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 82 "/DDR_Banks/M1_DQ13" Po -629 -1771 $EndPAD $PAD Sh "B7" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 62 "/DDR_Banks/M1_DQ2" Po 629 -1771 $EndPAD $PAD Sh "B8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 944 -1771 $EndPAD $PAD Sh "C2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -944 -1377 $EndPAD $PAD Sh "C3" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 75 "/DDR_Banks/M1_DQ11" Po -629 -1377 $EndPAD $PAD Sh "C7" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 42 "/DDR_Banks/M1_DQ4" Po 629 -1377 $EndPAD $PAD Sh "C8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "N-000036" +Ne 102 "N-000048" Po 944 -1377 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "N-000036" +Ne 102 "N-000048" Po -944 -983 $EndPAD $PAD Sh "D3" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 71 "/DDR_Banks/M1_DQ9" Po -629 -983 $EndPAD $PAD Sh "D7" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 52 "/DDR_Banks/M1_DQ6" Po 629 -983 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po 944 -983 $EndPAD $PAD Sh "E2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -944 -590 $EndPAD $PAD Sh "E3" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 78 "/DDR_Banks/M1_UDQS" Po -629 -590 $EndPAD $PAD Sh "E7" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 57 "/DDR_Banks/M1_LDQS" Po 629 -590 $EndPAD $PAD Sh "E8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "N-000036" +Ne 102 "N-000048" Po 944 -590 $EndPAD $PAD Sh "F2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -944 -196 $EndPAD $PAD Sh "F3" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 61 "/DDR_Banks/M1_UDM" Po -629 -196 $EndPAD $PAD Sh "F7" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 56 "/DDR_Banks/M1_LDM" Po 629 -196 $EndPAD $PAD Sh "F8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "N-000036" +Ne 102 "N-000048" Po 944 -196 $EndPAD $PAD Sh "G2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 34 "/DDR_Banks/M1_CLK" Po -944 196 $EndPAD $PAD Sh "G3" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 41 "/DDR_Banks/M1_CLK#" Po -629 196 $EndPAD $PAD Sh "G7" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 33 "/DDR_Banks/M1_WE#" Po 629 196 $EndPAD $PAD Sh "G8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 36 "/DDR_Banks/M1_CAS#" Po 944 196 $EndPAD $PAD Sh "H2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/FPGA_Spartan6/M1_A12" +Ne 13 "/DDR_Banks/M1_A12" Po -944 590 $EndPAD $PAD Sh "H3" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 12 "/DDR_Banks/M1_CKE" Po -629 590 $EndPAD $PAD Sh "H7" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 35 "/DDR_Banks/M1_RAS#" Po 629 590 $EndPAD $PAD @@ -5622,14 +5572,14 @@ $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/FPGA_Spartan6/M1_A11" +Ne 20 "/DDR_Banks/M1_A11" Po -944 983 $EndPAD $PAD Sh "J3" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/M1_A9" +Ne 8 "/DDR_Banks/M1_A9" Po -629 983 $EndPAD $PAD @@ -5650,87 +5600,1405 @@ $PAD Sh "K2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/M1_A8" +Ne 6 "/DDR_Banks/M1_A8" Po -944 1377 $EndPAD $PAD Sh "K3" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/M1_A7" +Ne 16 "/DDR_Banks/M1_A7" Po -629 1377 $EndPAD $PAD Sh "K7" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/FPGA_Spartan6/M1_A0" +Ne 22 "/DDR_Banks/M1_A0" Po 629 1377 $EndPAD $PAD Sh "K8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/FPGA_Spartan6/M1_A10" +Ne 25 "/DDR_Banks/M1_A10" Po 944 1377 $EndPAD $PAD Sh "L2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/M1_A6" +Ne 50 "/DDR_Banks/M1_A6" Po -944 1771 $EndPAD $PAD Sh "L3" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/M1_A5" +Ne 51 "/DDR_Banks/M1_A5" Po -629 1771 $EndPAD $PAD Sh "L7" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/FPGA_Spartan6/M1_A2" +Ne 17 "/DDR_Banks/M1_A2" Po 629 1771 $EndPAD $PAD Sh "L8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/FPGA_Spartan6/M1_A1" +Ne 23 "/DDR_Banks/M1_A1" Po 944 1771 $EndPAD $PAD Sh "M2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Spartan6/M1_A4" +Ne 21 "/DDR_Banks/M1_A4" Po -944 2165 $EndPAD $PAD Sh "M3" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "GND" +Ne 1 "GND" Po -629 2165 $EndPAD $PAD Sh "M7" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "N-000036" +Ne 102 "N-000048" Po 629 2165 $EndPAD $PAD Sh "M8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/FPGA_Spartan6/M1_A3" +Ne 26 "/DDR_Banks/M1_A3" Po 944 2165 $EndPAD $EndMODULE 60fbga_ddr +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5F2CA3 ~~ +Li 0402 +Sc 4C5F2CA3 +AR /4C5F1EDC/4C5F2CA3 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"V?" +T1 0 150 200 200 0 40 N I 25 N"V0402MHS03" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 103 "N-000409" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5F2CA3 ~~ +Li 0402 +Sc 4C5F2CA3 +AR /4C5F1EDC/4C5F2CA3 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"V?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D719D ~~ +Li 0402 +Sc 4C5D719D +AR /4C4320F3/4C5D719D +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R?" +T1 0 150 200 200 0 40 N I 25 N"220" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 104 "N-000389" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 94 "/Ethernet_Phy/ETH_LED0" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D7F39 ~~ +Li 0402 +Sc 4C5D7F39 +AR /4C4320F3/4C5D7F39 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D7ECF ~~ +Li 0402 +Sc 4C5D7ECF +AR /4C4320F3/4C5D7ECF +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D7DC4 ~~ +Li 0402 +Sc 4C5D7DC4 +AR /4C4320F3/4C5D7DC4 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D7AFE ~~ +Li 0402 +Sc 4C5D7AFE +AR /4C4320F3/4C5D7AFE +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D7AFC ~~ +Li 0402 +Sc 4C5D7AFC +AR /4C4320F3/4C5D7AFC +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D7AF9 ~~ +Li 0402 +Sc 4C5D7AF9 +AR /4C4320F3/4C5D7AF9 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D7AF7 ~~ +Li 0402 +Sc 4C5D7AF7 +AR /4C4320F3/4C5D7AF7 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D71DB ~~ +Li 0402 +Sc 4C5D71DB +AR /4C4320F3/4C5D71DB +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D719D ~~ +Li 0402 +Sc 4C5D719D +AR /4C4320F3/4C5D719D +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D7FB7 ~~ +Li 0402 +Sc 4C5D7FB7 +AR /4C4320F3/4C5D7FB7 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L?" +T1 0 150 200 200 0 40 N I 25 N"FB" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000068" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 92 "/Ethernet_Phy/ETH_A3.3V" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D80F3 ~~ +Li 0402 +Sc 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/4C4320F3/4C5D7DCB +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C?" +T1 0 150 200 200 0 40 N I 25 N"47nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 105 "N-000393" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5F2039 ~~ +Li 0402 +Sc 4C5F2039 +AR /4C5F1EDC/4C5F2039 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5F2037 ~~ +Li 0402 +Sc 4C5F2037 +AR /4C5F1EDC/4C5F2037 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5F2033 ~~ +Li 0402 +Sc 4C5F2033 +AR /4C5F1EDC/4C5F2033 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D8114 ~~ +Li 0402 +Sc 4C5D8114 +AR /4C4320F3/4C5D8114 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-305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 0 0 0 15 4C5FF890 4C5D7DCB ~~ +Li 0402 +Sc 4C5D7DCB +AR /4C4320F3/4C5D7DCB +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C?" +T1 0 150 200 200 0 40 N I 25 N"Val*" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 1210 +Po 36900 35050 900 15 4C5FF890 4C5F2B55 ~~ +Li 1210 +Sc 4C5F2B55 +AR /4C5F1EDC/4C5F2B55 +Op 0 0 0 +At SMD +T0 0 -150 200 200 900 40 N V 25 N"F?" +T1 0 150 200 200 900 40 N I 25 N"MICROSMD075F" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 106 "N-000411" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE MICROSD-500901 +Po 57990 45510 0 15 4C5F34DA 4B76F5E2 ~~ +Li MICROSD-500901 +Sc 4B76F5E2 +AR /4C4227FE/4B76F5E2 +Op 0 0 0 +T0 -160 -652 157 157 0 20 N V 21 N"J1" +T1 0 118 118 118 -1800 20 N I 21 N"MICROSD" +DS -2709 1675 -2709 -507 60 21 +DS -2707 3095 -2707 2747 60 21 +DS 2709 1699 2709 -500 60 21 +DS 2706 3088 2706 2767 60 21 +DS -1989 -1553 -1989 -1013 60 21 +DS -1989 -1013 1573 -1016 60 21 +DS 1573 -1016 1573 -1548 60 21 +DS -2707 -1555 2707 -1555 60 21 +DS -2707 3091 2707 3091 60 21 +$PAD +Sh "1" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 0 "" +Po -1299 0 +$EndPAD +$PAD +Sh "2" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 0 "" +Po -866 0 +$EndPAD +$PAD +Sh "3" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 0 "" +Po -433 0 +$EndPAD +$PAD +Sh "4" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 0 "" +Po 0 0 +$EndPAD +$PAD +Sh "5" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 0 "" +Po 433 0 +$EndPAD +$PAD +Sh "6" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 0 "" +Po 866 0 +$EndPAD +$PAD +Sh "7" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 0 "" +Po 1299 0 +$EndPAD +$PAD +Sh "8" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 0 "" +Po 1732 0 +$EndPAD +$PAD +Sh "CASE" R 571 787 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 1 "GND" +Po 2707 -1024 +$EndPAD +$PAD +Sh "CASE" R 571 787 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 1 "GND" +Po -2707 -1024 +$EndPAD +$PAD +Sh "CASE" R 571 787 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 1 "GND" +Po -2707 2244 +$EndPAD +$PAD +Sh "CASE" R 571 787 0 0 0 +Dr 0 0 0 +At STD N 00888000 +Ne 1 "GND" +Po 2707 2244 +$EndPAD +$EndMODULE MICROSD-500901 +$MODULE SD-48025 +Po 53840 15540 1800 15 00000000 4C5D6F5A ~~ +Li SD-48025 +Sc 4C5D6F5A +AR /4C4320F3/4C5D6F5A +Op 0 0 0 +T0 527 -694 157 157 1800 20 N V 21 N"J4" +T1 0 118 118 118 0 20 N I 21 N"RJ45-48025" +DS -3700 -5800 -3700 4300 60 21 +DS -3700 -5800 3700 -5800 60 21 +DS 3700 -5800 3700 4300 60 21 +DS -3700 4300 3700 4300 60 21 +$PAD +Sh "13" C 1646 1646 0 0 1800 +Dr 1252 0 0 +At STD N 0CC0FFFF +Ne 105 "N-000393" +Po 2250 0 +$EndPAD +$PAD +Sh "13" C 984 984 0 0 1800 +Dr 640 0 0 +At STD N 0CC0FFFF +Ne 105 "N-000393" +Po 3100 -1200 +$EndPAD +$PAD +Sh "14" C 1646 1646 0 0 1800 +Dr 1252 0 0 +At STD N 0CC0FFFF +Ne 105 "N-000393" +Po -2250 0 +$EndPAD +$PAD +Sh "14" C 984 984 0 0 1800 +Dr 640 0 0 +At STD N 0CC0FFFF +Ne 105 "N-000393" +Po -3100 -1200 +$EndPAD +$PAD +Sh "1" R 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 90 "N-000391" +Po -1750 -2500 +$EndPAD +$PAD +Sh "3" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 87 "N-000068" +Po -750 -2500 +$EndPAD +$PAD +Sh "5" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 1 "GND" +Po 250 -2500 +$EndPAD +$PAD +Sh "7" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 98 "N-000392" +Po 1250 -2500 +$EndPAD +$PAD +Sh "2" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 91 "N-000386" +Po -1250 -3500 +$EndPAD +$PAD +Sh "4" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 1 "GND" +Po -250 -3500 +$EndPAD +$PAD +Sh "6" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 87 "N-000068" +Po 750 -3500 +$EndPAD +$PAD +Sh "8" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 97 "N-000385" +Po 1750 -3500 +$EndPAD +$PAD +Sh "9" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 87 "N-000068" +Po -2150 -5400 +$EndPAD +$PAD +Sh "10" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 104 "N-000389" +Po -1150 -5400 +$EndPAD +$PAD +Sh "11" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 87 "N-000068" +Po 1150 -5400 +$EndPAD +$PAD +Sh "12" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 107 "N-000388" +Po 2150 -5400 +$EndPAD +$EndMODULE SD-48025 +$MODULE USB-48204 +Po 33090 37720 2700 15 4C5F28A8 4C5F23DD ~~ +Li USB-48204 +Sc 4C5F23DD +AR /4C5F1EDC/4C5F23DD +Op 0 0 0 +T0 120 -3162 157 157 2700 20 N V 21 N"J?" +T1 0 118 118 118 900 20 N I 21 N"USB-48204-0001" +DS -1499 5299 -1704 5299 60 21 +DS -1704 5299 -1704 5178 60 21 +DS -1704 5178 -1502 5178 60 21 +DS 1500 5298 1708 5298 60 21 +DS 1708 5298 1707 5180 60 21 +DS 1707 5180 1499 5181 60 21 +DS -1500 -3000 -1500 5300 60 21 +DS -1500 -3000 1500 -3000 60 21 +DS 1500 -3000 1500 5300 60 21 +DS -1500 5300 1500 5300 60 21 +$PAD +Sh "1" R 470 470 0 0 2700 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 106 "N-000411" +Po 0 -2362 +$EndPAD +$PAD +Sh "2" C 470 470 0 0 2700 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 103 "N-000409" +Po 0 -1575 +$EndPAD +$PAD +Sh "3" C 470 470 0 0 2700 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 108 "N-000410" +Po 0 -787 +$EndPAD +$PAD +Sh "3" C 470 470 0 0 2700 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 108 "N-000410" +Po 0 0 +$EndPAD +$PAD +Sh "S1" C 670 670 0 0 2700 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 109 "N-000412" +Po 1077 287 +$EndPAD +$PAD +Sh "S2" C 670 670 0 0 2700 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 109 "N-000412" +Po -1077 287 +$EndPAD +$PAD +Sh "S3" C 670 670 0 0 2700 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 109 "N-000412" +Po 1077 -2468 +$EndPAD +$PAD +Sh "S4" C 670 670 0 0 2700 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 109 "N-000412" +Po -1077 -2468 +$EndPAD +$EndMODULE USB-48204 +$MODULE TSSOP-14 +Po 39240 37670 900 15 4C60642A 4C5F2025 ~~ +Li TSSOP-14 +Sc 4C5F2025 +AR /4C5F1EDC/4C5F2025 +Op 0 0 0 +T0 50 -1822 276 276 900 69 N V 21 N"U6" +T1 70 1848 276 276 900 69 N I 21 N"MIC2550AYTS" +DC -738 409 -666 418 150 21 +DS 987 634 -984 628 150 21 +DS -984 628 -984 187 150 21 +DS -984 187 -726 187 150 21 +DS -726 187 -726 -185 150 21 +DS -726 -185 -987 -188 150 21 +DS -987 -188 -984 -649 150 21 +DS -984 -649 982 -650 150 21 +DS 982 -650 986 634 150 21 +DS -984 -787 984 -787 1 21 +DS 984 -787 984 787 1 21 +DS -984 787 984 787 1 21 +DS -984 -787 -984 787 1 21 +$PAD +Sh "1" R 137 570 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000068" +Po -767 1112 +$EndPAD +$PAD +Sh "2" R 137 570 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -511 1112 +$EndPAD +$PAD +Sh "3" R 137 570 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -255 1112 +$EndPAD +$PAD +Sh "4" R 137 570 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 1112 +$EndPAD +$PAD +Sh "5" R 137 570 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 255 1112 +$EndPAD +$PAD +Sh "6" R 137 570 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 511 1112 +$EndPAD +$PAD +Sh "7" R 137 570 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "GND" +Po 767 1112 +$EndPAD +$PAD +Sh "8" R 137 570 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "GND" +Po 767 -1112 +$EndPAD +$PAD +Sh "9" R 137 570 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 511 -1112 +$EndPAD +$PAD +Sh "10" R 137 570 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 103 "N-000409" +Po 255 -1112 +$EndPAD +$PAD +Sh "11" R 137 570 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 108 "N-000410" +Po 0 -1112 +$EndPAD +$PAD +Sh "12" R 137 570 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000068" +Po -255 -1112 +$EndPAD +$PAD +Sh "13" R 137 570 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -511 -1112 +$EndPAD +$PAD +Sh "14" R 137 570 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "N-000068" +Po -767 -1112 +$EndPAD +$EndMODULE TSSOP-14 $TRACK $EndTRACK $ZONE diff --git a/kicad/xue-rnc/xue-rnc.cache.dcm b/kicad/xue-rnc/xue-rnc.cache.dcm index 5fc3245..a95b60c 100644 --- a/kicad/xue-rnc/xue-rnc.cache.dcm +++ b/kicad/xue-rnc/xue-rnc.cache.dcm @@ -1,4 +1,4 @@ -EESchema-DOCLIB Version 2.0 Sun 08 Aug 2010 05:52:09 PM COT +EESchema-DOCLIB Version 2.0 Mon 09 Aug 2010 03:34:05 PM COT # $CMP C D Condensateur non polarise diff --git a/kicad/xue-rnc/xue-rnc.cache.lib b/kicad/xue-rnc/xue-rnc.cache.lib index 2a7ffb4..9416831 100644 --- a/kicad/xue-rnc/xue-rnc.cache.lib +++ b/kicad/xue-rnc/xue-rnc.cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version Sun 08 Aug 2010 05:52:09 PM COT +EESchema-LIBRARY Version Mon 09 Aug 2010 03:34:05 PM COT # # # C @@ -212,10 +212,10 @@ DEF MICROSMD075F F 0 40 N N 1 F N F0 "F" -50 100 60 H V C CNN F1 "MICROSMD075F" 0 -200 60 H V C CNN DRAW -P 3 0 1 0 150 100 150 100 150 100 N -S -150 50 100 -50 0 1 0 N -P 5 0 1 0 -100 -100 50 100 150 100 150 100 150 100 N P 3 0 1 0 -100 -100 -200 -100 -200 -100 N +P 5 0 1 0 -100 -100 50 100 150 100 150 100 150 100 N +S -150 50 100 -50 0 1 0 N +P 3 0 1 0 150 100 150 100 150 100 N X ~ 1 250 0 150 L 30 30 1 1 B X ~ 2 -300 0 150 R 30 30 1 1 B ENDDRAW diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp index eb194fa..badce76 100644 --- a/kicad/xue-rnc/xue-rnc.cmp +++ b/kicad/xue-rnc/xue-rnc.cmp @@ -1,94 +1,129 @@ -Cmp-Mod V01 Created by CVpcb (20090216-final) date = Sat 07 Aug 2010 12:37:39 PM COT +Cmp-Mod V01 Created by CVpcb (20090216-final) date = Mon 09 Aug 2010 03:24:50 PM COT BeginCmp TimeStamp = /4C4320F3/4C5D7DCB; Reference = C?; ValeurCmp = 47nF; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7E41; Reference = C?; ValeurCmp = 100nF; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7E43; Reference = C?; ValeurCmp = 100nF; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; Reference = C?; ValeurCmp = 1uF; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7FA1; Reference = C?; ValeurCmp = 100nF; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7FA3; Reference = C?; ValeurCmp = 100nF; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7FA5; Reference = C?; ValeurCmp = 1uF; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7FA7; Reference = C?; ValeurCmp = 100nF; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D80ED; Reference = C?; ValeurCmp = C; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D80F0; Reference = C?; ValeurCmp = C; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D8104; Reference = C?; ValeurCmp = C; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D8114; Reference = C?; ValeurCmp = C; -IdModule = ; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C5F2033; +Reference = C?; +ValeurCmp = 1uF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C5F2037; +Reference = C?; +ValeurCmp = 1uF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C5F2039; +Reference = C?; +ValeurCmp = 470nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C5F2D1E; +Reference = C?; +ValeurCmp = 4.7nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C5F2B55; +Reference = F?; +ValeurCmp = MICROSMD075F; +IdModule = 1210; EndCmp BeginCmp TimeStamp = /4C4227FE/4B76F5E2; Reference = J1; ValeurCmp = MICROSD; -IdModule = MICROSD; +IdModule = MICROSD-500901; EndCmp BeginCmp @@ -98,88 +133,102 @@ ValeurCmp = RJ45-48025; IdModule = SD-48025; EndCmp +BeginCmp +TimeStamp = /4C5F1EDC/4C5F23DD; +Reference = J?; +ValeurCmp = USB-48204-0001; +IdModule = USB-48204; +EndCmp + BeginCmp TimeStamp = /4C4320F3/4C5D7FB7; Reference = L?; ValeurCmp = FB; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D80F3; Reference = L?; ValeurCmp = INDUCTOR; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D810A; Reference = L?; ValeurCmp = INDUCTOR; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D719D; Reference = R?; ValeurCmp = 220; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D71DB; Reference = R?; ValeurCmp = 220; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7AF7; Reference = R?; ValeurCmp = 49.9; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7AF9; Reference = R?; ValeurCmp = 49.9; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7AFC; Reference = R?; ValeurCmp = 49.9; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7AFE; Reference = R?; ValeurCmp = 49.9; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7DC4; Reference = R?; ValeurCmp = 1M; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7ECF; Reference = R?; ValeurCmp = 6.65K; -IdModule = ; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7F39; Reference = R?; ValeurCmp = 4.7K; -IdModule = ; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C5F2D27; +Reference = R?; +ValeurCmp = 1M; +IdModule = 0402; EndCmp BeginCmp @@ -217,4 +266,25 @@ ValeurCmp = NAND; IdModule = NAND-48TSOP; EndCmp +BeginCmp +TimeStamp = /4C5F1EDC/4C5F2025; +Reference = U6; +ValeurCmp = MIC2550AYTS; +IdModule = TSSOP-14; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C5F2CA3; +Reference = V?; +ValeurCmp = V0402MHS03; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C5F1EDC/4C5F2CA7; +Reference = V?; +ValeurCmp = V0402MHS03; +IdModule = 0402; +EndCmp + EndListe diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index da814df..8a039c6 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,872 +1,960 @@ -# EESchema Netlist Version 1.1 created Sat 07 Aug 2010 12:37:39 PM COT +# EESchema Netlist Version 1.1 created Mon 09 Aug 2010 03:31:28 PM COT ( - ( /4C4320F3/4C5D7DCB $noname$ C? 47nF - ( 1 N-000418 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E41 $noname$ C? 100nF - ( 1 N-000061 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E43 $noname$ C? 100nF - ( 1 N-000061 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7F9F $noname$ C? 1uF - ( 1 N-000061 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA1 $noname$ C? 100nF - ( 1 N-000061 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA3 $noname$ C? 100nF - ( 1 N-000061 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA5 $noname$ C? 1uF - ( 1 /Etherne1 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA7 $noname$ C? 100nF - ( 1 /Etherne1 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D80ED $noname$ C? C - ( 1 /Etherne2 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D80F0 $noname$ C? C - ( 1 N-000409 ) - ( 2 N-000421 ) - ) - ( /4C4320F3/4C5D8104 $noname$ C? C - ( 1 /Etherne3 ) - ( 2 N-000421 ) - ) - ( /4C4320F3/4C5D8114 $noname$ C? C - ( 1 /Etherne4 ) - ( 2 N-000421 ) - ) - ( /4C4227FE/4B76F5E2 MICROSD J1 MICROSD - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) - ( 7 ? ) - ( 8 ? ) - ( CASE GND ) - ( CD ? ) - ( COM GND ) - ) - ( /4C4320F3/4C5D6F5A SD-48025 J4 RJ45-48025 - ( 1 N-000410 ) - ( 2 N-000416 ) - ( 3 N-000061 ) - ( 4 GND ) - ( 5 GND ) - ( 6 N-000061 ) - ( 7 N-000413 ) - ( 8 N-000417 ) - ( 9 N-000061 ) - ( 10 N-000412 ) - ( 11 N-000061 ) - ( 12 N-000414 ) - ( 13 N-000418 ) - ( 14 N-000418 ) - ) - ( /4C4320F3/4C5D7FB7 $noname$ L? FB - ( 1 N-000061 ) - ( 2 /Etherne1 ) - ) - ( /4C4320F3/4C5D80F3 $noname$ L? INDUCTOR - ( 1 N-000409 ) - ( 2 /Etherne3 ) - ) - ( /4C4320F3/4C5D810A $noname$ L? INDUCTOR - ( 1 /Etherne3 ) - ( 2 /Etherne4 ) - ) - ( /4C4320F3/4C5D719D $noname$ R? 220 - ( 1 N-000412 ) - ( 2 /Etherne5 ) - ) - ( /4C4320F3/4C5D71DB $noname$ R? 220 - ( 1 N-000414 ) - ( 2 /Etherne6 ) - ) - ( /4C4320F3/4C5D7AF7 $noname$ R? 49.9 - ( 1 N-000061 ) - ( 2 N-000413 ) - ) - ( /4C4320F3/4C5D7AF9 $noname$ R? 49.9 - ( 1 N-000061 ) - ( 2 N-000417 ) - ) - ( /4C4320F3/4C5D7AFC $noname$ R? 49.9 - ( 1 N-000061 ) - ( 2 N-000416 ) - ) - ( /4C4320F3/4C5D7AFE $noname$ R? 49.9 - ( 1 N-000061 ) - ( 2 N-000410 ) - ) - ( /4C4320F3/4C5D7DC4 $noname$ R? 1M - ( 1 N-000418 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7ECF $noname$ R? 6.65K - ( 1 N-000419 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7F39 $noname$ R? 4.7K - ( 1 /Etherne7 ) - ( 2 N-000061 ) - ) - ( /4C431A63/4C431E53 FGG484bga-p10 U1 XC6SLX45FGG484 - ( A1 GND ) - ( A2 ? ) - ( A4 ? ) - ( A5 /FPGA_Sp8 ) - ( A6 ? ) - ( A7 ? ) - ( A8 ? ) - ( A9 ? ) - ( A10 ? ) - ( A11 ? ) - ( A12 ? ) - ( A13 ? ) - ( A14 ? ) - ( A15 ? ) - ( A16 ? ) - ( A17 ? ) - ( A18 ? ) - ( A19 ? ) - ( A20 ? ) - ( A21 ? ) - ( A22 GND ) - ( AA1 ? ) - ( AA2 ? ) - ( AA3 N-000109 ) - ( AA4 ? ) - ( AA5 GND ) - ( AA6 ? ) - ( AA7 N-000109 ) - ( AA8 ? ) - ( AA9 GND ) - ( AA10 ? ) - ( AA11 N-000109 ) - ( AA12 ? ) + ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} + ( H9 N-000119 ) + ( U11 N-000119 ) + ( F11 N-000119 ) + ( R6 N-000119 ) + ( M15 N-000119 ) + ( V6 N-000119 ) + ( G12 N-000119 ) + ( H15 N-000119 ) + ( D16 N-000119 ) + ( K15 N-000119 ) + ( R12 N-000119 ) + ( N8 N-000119 ) + ( R10 N-000119 ) + ( L8 N-000119 ) + ( N10 N-000118 ) + ( P11 N-000118 ) + ( P13 N-000118 ) + ( P9 N-000118 ) + ( R14 N-000118 ) + ( N12 N-000118 ) + ( J10 N-000118 ) + ( J12 N-000118 ) + ( J14 N-000118 ) + ( J8 N-000118 ) + ( K11 N-000118 ) + ( K13 N-000118 ) + ( K9 N-000118 ) + ( L10 N-000118 ) + ( L12 N-000118 ) + ( L14 N-000118 ) + ( M11 N-000118 ) + ( M13 N-000118 ) + ( M9 N-000118 ) + ( N14 N-000118 ) + ( G13 ? ) + ( G8 ? ) + ( G9 ? ) + ( H10 ? ) + ( H11 ? ) + ( H12 ? ) + ( H13 ? ) + ( H14 ? ) + ( P16 ? ) + ( D13 ? ) + ( AA1 ? ) + ( N15 ? ) + ( G15 ? ) + ( E18 ? ) + ( A19 ? ) + ( C18 ? ) + ( G11 ? ) + ( F9 ? ) + ( F8 ? ) + ( F15 ? ) + ( F14 ? ) + ( F13 ? ) + ( F12 ? ) + ( F10 ? ) + ( E8 ? ) + ( E14 ? ) + ( E12 ? ) + ( E10 ? ) + ( D12 ? ) + ( P15 ? ) + ( R17 ? ) + ( Y22 ? ) + ( P10 GND ) + ( V10 GND ) + ( M10 GND ) + ( K10 GND ) + ( L13 GND ) + ( A1 GND ) + ( N13 GND ) + ( A22 GND ) + ( R5 GND ) ( AA13 GND ) - ( AA14 ? ) - ( AA15 N-000109 ) - ( AA16 ? ) + ( W19 GND ) ( AA17 GND ) + ( K14 GND ) + ( AA5 GND ) + ( L5 GND ) + ( AA9 GND ) + ( M14 GND ) + ( AB1 GND ) + ( N2 GND ) + ( AB22 GND ) + ( P14 GND ) + ( B13 GND ) + ( U21 GND ) + ( B17 GND ) + ( V4 GND ) + ( B5 GND ) + ( J9 GND ) + ( B9 GND ) + ( K12 GND ) + ( D18 GND ) + ( L11 GND ) + ( D4 GND ) + ( L18 GND ) + ( E11 GND ) + ( L9 GND ) + ( E15 GND ) + ( M12 GND ) + ( E2 GND ) + ( N11 GND ) + ( E21 GND ) + ( N17 GND ) + ( E7 GND ) + ( N21 GND ) + ( G18 GND ) + ( P12 GND ) + ( G5 GND ) + ( R18 GND ) + ( H7 GND ) + ( U2 GND ) + ( J11 GND ) + ( U7 GND ) + ( J13 GND ) + ( V14 GND ) + ( J15 GND ) + ( W16 GND ) + ( J2 GND ) + ( W7 GND ) + ( J21 GND ) + ( N9 GND ) + ( AA15 N-000123 ) + ( V16 N-000123 ) + ( T13 N-000123 ) + ( V8 N-000123 ) + ( V12 N-000123 ) + ( AA3 N-000123 ) + ( T9 N-000123 ) + ( AA19 N-000123 ) + ( AA11 N-000123 ) + ( W5 N-000123 ) + ( AA7 N-000123 ) + ( AA12 ? ) + ( AB12 ? ) + ( Y11 ? ) + ( AB11 ? ) + ( R11 ? ) + ( T11 ? ) + ( AA10 ? ) + ( AB10 ? ) + ( V11 ? ) + ( W11 ? ) + ( Y9 ? ) + ( AB9 ? ) + ( W10 ? ) + ( Y10 ? ) + ( AA8 ? ) + ( AB8 ? ) + ( W8 ? ) + ( V7 ? ) + ( W9 ? ) + ( Y8 ? ) + ( Y7 ? ) + ( AB7 ? ) + ( AA6 ? ) + ( AB6 ? ) + ( U9 ? ) + ( V9 ? ) + ( T8 ? ) + ( U8 ? ) + ( T10 ? ) + ( U10 ? ) + ( W6 ? ) + ( Y6 ? ) + ( Y5 ? ) + ( AB5 ? ) + ( AA4 ? ) + ( AB4 ? ) + ( Y3 ? ) + ( AB3 ? ) + ( R9 ? ) + ( R8 ? ) + ( T7 ? ) + ( R7 ? ) + ( W4 ? ) + ( Y4 ? ) + ( U6 ? ) + ( V5 ? ) + ( AA2 ? ) + ( AB2 ? ) + ( T6 ? ) + ( T5 ? ) + ( AB13 ? ) + ( Y13 ? ) + ( Y12 ? ) + ( W12 ? ) + ( R13 ? ) + ( T14 ? ) + ( U12 ? ) + ( T12 ? ) + ( AB15 ? ) + ( Y15 ? ) + ( Y14 ? ) + ( W14 ? ) + ( AB16 ? ) + ( AA16 ? ) + ( W13 ? ) + ( V13 ? ) + ( W15 ? ) + ( Y16 ? ) + ( AB14 ? ) + ( AA14 ? ) + ( AB17 ? ) + ( Y17 ? ) + ( AB18 ? ) ( AA18 ? ) - ( AA19 N-000109 ) + ( V15 ? ) + ( U15 ? ) + ( U13 ? ) + ( U14 ? ) + ( W17 ? ) + ( V17 ? ) + ( R15 ? ) + ( R16 ? ) + ( V18 ? ) + ( V19 ? ) + ( U16 ? ) + ( U17 ? ) + ( T15 ? ) + ( T16 ? ) + ( Y18 ? ) + ( W18 ? ) + ( AB19 ? ) + ( Y19 ? ) + ( T17 ? ) + ( T18 ? ) + ( AB20 ? ) ( AA20 ? ) + ( AB21 ? ) ( AA21 ? ) ( AA22 ? ) - ( AB1 GND ) - ( AB2 ? ) - ( AB3 ? ) - ( AB4 ? ) - ( AB5 ? ) - ( AB6 ? ) - ( AB7 ? ) - ( AB8 ? ) - ( AB9 ? ) - ( AB10 ? ) - ( AB11 ? ) - ( AB12 ? ) - ( AB13 ? ) - ( AB14 ? ) - ( AB15 ? ) - ( AB16 ? ) - ( AB17 ? ) - ( AB18 ? ) - ( AB19 ? ) - ( AB20 ? ) - ( AB21 ? ) - ( AB22 GND ) - ( B1 ? ) - ( B2 ? ) - ( B3 ? ) - ( B4 N-000108 ) - ( B5 GND ) - ( B6 ? ) - ( B7 N-000108 ) - ( B8 ? ) - ( B9 GND ) - ( B10 ? ) - ( B11 N-000108 ) - ( B12 ? ) - ( B13 GND ) - ( B14 ? ) - ( B15 N-000108 ) - ( B16 ? ) - ( B17 GND ) - ( B18 ? ) - ( B19 N-000108 ) - ( B20 ? ) - ( B21 ? ) - ( B22 ? ) - ( C1 /DDR_Ban9 ) - ( C2 N-000106 ) - ( C3 ? ) - ( C4 ? ) - ( C5 ? ) - ( C6 ? ) - ( C7 ? ) - ( C8 ? ) - ( C9 ? ) - ( C10 ? ) - ( C11 ? ) - ( C12 ? ) - ( C13 ? ) - ( C14 ? ) - ( C15 ? ) - ( C16 ? ) - ( C17 ? ) - ( C18 ? ) - ( C20 /DDR_Banks/M1_A8 ) - ( C21 N-000107 ) - ( C22 /DDR_Banks/M1_A9 ) - ( D1 /DDR_Ban10 ) - ( D2 ? ) - ( D3 ? ) - ( D4 GND ) - ( D5 ? ) - ( D6 ? ) - ( D7 ? ) - ( D8 ? ) - ( D9 ? ) - ( D10 ? ) - ( D11 ? ) - ( D12 ? ) - ( D13 ? ) - ( D14 ? ) - ( D15 ? ) - ( D16 N-000105 ) - ( D17 ? ) - ( D18 GND ) - ( D19 ? ) - ( D20 ? ) - ( D21 ? ) - ( D22 /DDR_Ban11 ) - ( E1 /DDR_Banks/M0_A9 ) - ( E2 GND ) - ( E3 /DDR_Banks/M0_A8 ) - ( E4 ? ) - ( E5 ? ) - ( E6 ? ) - ( E7 GND ) - ( E8 ? ) - ( E9 N-000108 ) - ( E10 ? ) - ( E11 GND ) - ( E12 ? ) - ( E13 N-000108 ) - ( E14 ? ) - ( E15 GND ) - ( E16 ? ) - ( E17 N-000108 ) - ( E18 ? ) - ( E19 N-000107 ) - ( E20 /DDR_Banks/M1_A7 ) - ( E21 GND ) - ( E22 /DDR_Banks/M1_A2 ) - ( F1 ? ) - ( F2 ? ) - ( F3 /DDR_Banks/M0_A4 ) - ( F4 N-000106 ) - ( F5 ? ) - ( F6 N-000106 ) - ( F7 ? ) - ( F8 ? ) - ( F9 ? ) - ( F10 ? ) - ( F11 N-000105 ) - ( F12 ? ) - ( F13 ? ) - ( F14 ? ) - ( F15 ? ) - ( F16 ? ) - ( F17 ? ) - ( F18 ? ) - ( F19 /DDR_Ban12 ) - ( F20 /DDR_Banks/M1_A4 ) - ( F21 /DDR_Banks/M1_A0 ) - ( F22 /DDR_Banks/M1_A1 ) - ( G1 ? ) - ( G2 N-000106 ) - ( G3 ? ) - ( G4 /DDR_Ban13 ) - ( G5 GND ) - ( G6 ? ) - ( G7 ? ) - ( G8 ? ) - ( G9 ? ) - ( G10 N-000108 ) - ( G11 ? ) - ( G12 N-000105 ) - ( G13 ? ) - ( G14 N-000108 ) - ( G15 ? ) - ( G16 ? ) - ( G17 ? ) - ( G18 GND ) - ( G19 /DDR_Ban14 ) - ( G20 /DDR_Banks/M1_A3 ) - ( G21 N-000107 ) - ( G22 ? ) - ( H1 /DDR_Banks/M0_A1 ) - ( H2 /DDR_Banks/M0_A0 ) - ( H3 /DDR_Ban15 ) - ( H4 /DDR_Ban16 ) - ( H5 /DDR_Banks/M0_A2 ) - ( H6 /DDR_Banks/M0_A7 ) - ( H7 GND ) - ( H8 ? ) - ( H9 N-000105 ) - ( H10 ? ) - ( H11 ? ) - ( H12 ? ) - ( H13 ? ) - ( H14 ? ) - ( H15 N-000105 ) - ( H16 ? ) - ( H17 ? ) - ( H18 ? ) - ( H19 ? ) - ( H20 /DDR_Ban17 ) - ( H21 ? ) - ( H22 ? ) - ( J1 /DDR_Ban18 ) - ( J2 GND ) - ( J3 /DDR_Ban19 ) - ( J4 /DDR_Banks/M0_A6 ) - ( J5 N-000106 ) - ( J6 ? ) - ( J7 ? ) - ( J8 N-000104 ) - ( J9 GND ) - ( J10 N-000104 ) - ( J11 GND ) - ( J12 N-000104 ) - ( J13 GND ) - ( J14 N-000104 ) - ( J15 GND ) - ( J16 ? ) - ( J17 ? ) - ( J18 N-000107 ) - ( J19 /DDR_Ban20 ) - ( J20 ? ) - ( J21 GND ) - ( J22 ? ) - ( K1 /DDR_Ban21 ) - ( K2 /DDR_Ban22 ) - ( K3 /DDR_Banks/M0_A5 ) - ( K4 ? ) - ( K5 ? ) - ( K6 /DDR_Banks/M0_A3 ) - ( K7 ? ) - ( K8 ? ) - ( K9 N-000104 ) - ( K10 GND ) - ( K11 N-000104 ) - ( K12 GND ) - ( K13 N-000104 ) - ( K14 GND ) - ( K15 N-000105 ) - ( K16 ? ) - ( K17 ? ) - ( K18 ? ) - ( K19 /DDR_Banks/M1_A6 ) - ( K20 /DDR_Banks/M1_A5 ) - ( K21 ? ) - ( K22 ? ) - ( L1 ? ) - ( L2 N-000106 ) - ( L3 ? ) - ( L4 ? ) - ( L5 GND ) - ( L6 ? ) - ( L7 N-000106 ) - ( L8 N-000105 ) - ( L9 GND ) - ( L10 N-000104 ) - ( L11 GND ) - ( L12 N-000104 ) - ( L13 GND ) - ( L14 N-000104 ) - ( L15 ? ) - ( L16 N-000107 ) - ( L17 ? ) - ( L18 GND ) - ( L19 ? ) - ( L20 ? ) - ( L21 N-000107 ) - ( L22 ? ) - ( M1 /DDR_Ban23 ) - ( M2 /DDR_Ban24 ) - ( M3 ? ) - ( M4 ? ) - ( M5 ? ) - ( M6 ? ) - ( M7 ? ) - ( M8 ? ) - ( M9 N-000104 ) - ( M10 GND ) - ( M11 N-000104 ) - ( M12 GND ) - ( M13 N-000104 ) - ( M14 GND ) - ( M15 N-000105 ) - ( M16 ? ) - ( M17 ? ) - ( M18 ? ) - ( M19 ? ) - ( M20 ? ) - ( M21 ? ) - ( M22 ? ) - ( N1 /DDR_Ban25 ) - ( N2 GND ) - ( N3 /DDR_Ban26 ) - ( N4 ? ) - ( N5 N-000106 ) - ( N6 ? ) - ( N7 ? ) - ( N8 N-000105 ) - ( N9 GND ) - ( N10 N-000104 ) - ( N11 GND ) - ( N12 N-000104 ) - ( N13 GND ) - ( N14 N-000104 ) - ( N15 ? ) - ( N16 ? ) - ( N17 GND ) - ( N18 N-000107 ) - ( N19 ? ) - ( N20 ? ) - ( N21 GND ) - ( N22 ? ) - ( P1 /DDR_Ban27 ) - ( P2 /DDR_Ban28 ) - ( P3 ? ) - ( P4 ? ) - ( P5 ? ) - ( P6 ? ) - ( P7 ? ) - ( P8 ? ) - ( P9 N-000104 ) - ( P10 GND ) - ( P11 N-000104 ) - ( P12 GND ) - ( P13 N-000104 ) - ( P14 GND ) - ( P15 ? ) - ( P16 ? ) - ( P17 ? ) - ( P18 ? ) - ( P19 ? ) - ( P20 ? ) - ( P21 ? ) - ( P22 ? ) - ( R1 /DDR_Ban29 ) - ( R2 N-000106 ) - ( R3 /DDR_Ban30 ) - ( R4 ? ) - ( R5 GND ) - ( R6 N-000105 ) - ( R7 ? ) - ( R8 ? ) - ( R9 ? ) - ( R10 N-000105 ) - ( R11 ? ) - ( R12 N-000105 ) - ( R13 ? ) - ( R14 N-000104 ) - ( R15 ? ) - ( R16 ? ) - ( R17 ? ) - ( R18 GND ) - ( R19 ? ) - ( R20 ? ) - ( R21 N-000107 ) - ( R22 ? ) - ( T1 ? ) - ( T2 ? ) - ( T3 ? ) - ( T4 ? ) - ( T5 ? ) - ( T6 ? ) - ( T7 ? ) - ( T8 ? ) - ( T9 N-000109 ) - ( T10 ? ) - ( T11 ? ) - ( T12 ? ) - ( T13 N-000109 ) - ( T14 ? ) - ( T15 ? ) - ( T16 ? ) - ( T17 ? ) - ( T18 ? ) - ( T19 ? ) - ( T20 ? ) - ( T21 ? ) - ( T22 ? ) - ( U1 /DDR_Ban31 ) - ( U2 GND ) - ( U3 /DDR_Ban32 ) - ( U4 ? ) - ( U5 N-000106 ) - ( U6 ? ) - ( U7 GND ) - ( U8 ? ) - ( U9 ? ) - ( U10 ? ) - ( U11 N-000105 ) - ( U12 ? ) - ( U13 ? ) - ( U14 ? ) - ( U15 ? ) - ( U16 ? ) - ( U17 ? ) - ( U18 N-000107 ) - ( U19 ? ) - ( U20 ? ) - ( U21 GND ) - ( U22 ? ) - ( V1 /DDR_Ban33 ) - ( V2 /DDR_Ban34 ) - ( V3 ? ) - ( V4 GND ) - ( V5 ? ) - ( V6 N-000105 ) - ( V7 ? ) - ( V8 N-000109 ) - ( V9 ? ) - ( V10 GND ) - ( V11 ? ) - ( V12 N-000109 ) - ( V13 ? ) - ( V14 GND ) - ( V15 ? ) - ( V16 N-000109 ) - ( V17 ? ) - ( V18 ? ) - ( V19 ? ) - ( V20 ? ) - ( V21 ? ) - ( V22 ? ) - ( W1 ? ) - ( W2 N-000106 ) - ( W3 ? ) - ( W4 ? ) - ( W5 N-000109 ) - ( W6 ? ) - ( W7 GND ) - ( W8 ? ) - ( W9 ? ) - ( W10 ? ) - ( W11 ? ) - ( W12 ? ) - ( W13 ? ) - ( W14 ? ) - ( W15 ? ) - ( W16 GND ) - ( W17 ? ) - ( W18 ? ) - ( W19 GND ) - ( W20 ? ) - ( W21 N-000107 ) - ( W22 ? ) - ( Y1 ? ) - ( Y3 ? ) - ( Y4 ? ) - ( Y5 ? ) - ( Y6 ? ) - ( Y7 ? ) - ( Y8 ? ) - ( Y9 ? ) - ( Y10 ? ) - ( Y11 ? ) - ( Y12 ? ) - ( Y13 ? ) - ( Y14 ? ) - ( Y15 ? ) - ( Y16 ? ) - ( Y17 ? ) - ( Y18 ? ) - ( Y19 ? ) - ( Y22 ? ) + ( W2 N-000120 ) + ( L2 N-000120 ) + ( L7 N-000120 ) + ( C2 N-000120 ) + ( N5 N-000120 ) + ( R2 N-000120 ) + ( U5 N-000120 ) + ( G2 N-000120 ) + ( F4 N-000120 ) + ( F6 N-000120 ) + ( J5 N-000120 ) + ( M3 /DDR_Banks/M0_UDM ) + ( L4 /DDR_Banks/M0_LDM ) + ( K5 /DDR_Banks/M0_RAS# ) + ( K4 /DDR_Banks/M0_CAS# ) + ( K3 /DDR_Banks/M0_A5 ) + ( J4 /DDR_Banks/M0_A6 ) + ( K6 /DDR_Banks/M0_A3 ) + ( J6 ? ) + ( H4 /DDR_Banks/M0_CLK ) + ( H3 /DDR_Banks/M0_CLK# ) + ( H2 /DDR_Banks/M0_A0 ) + ( H1 /DDR_Banks/M0_A1 ) + ( G3 ? ) + ( G1 ? ) + ( H6 /DDR_Banks/M0_A7 ) + ( H5 /DDR_Banks/M0_A2 ) + ( F2 /DDR_Banks/M0_WE# ) + ( F1 ? ) + ( G4 /DDR_Banks/M0_A10 ) + ( F3 /DDR_Banks/M0_A4 ) + ( E3 /DDR_Banks/M0_A8 ) + ( E1 /DDR_Banks/M0_A9 ) + ( D2 /DDR_Banks/M0_CKE ) + ( D1 /DDR_Banks/M0_A12 ) + ( C3 ? ) + ( C1 /DDR_Banks/M0_A11 ) + ( G6 ? ) + ( F5 ? ) + ( K7 ? ) + ( K8 ? ) + ( D5 ? ) + ( E4 ? ) + ( J7 ? ) + ( H8 ? ) + ( B2 ? ) + ( B1 ? ) + ( G7 ? ) + ( F7 ? ) + ( D3 ? ) + ( C4 ? ) + ( E5 ? ) + ( E6 ? ) + ( A2 ? ) + ( B3 ? ) + ( J1 /DDR_Banks/M0_DQ5 ) + ( J3 /DDR_Banks/M0_DQ4 ) + ( K1 /DDR_Banks/M0_DQ7 ) + ( K2 /DDR_Banks/M0_DQ6 ) + ( L1 ? ) + ( L3 /DDR_Banks/M0_LDQS ) + ( M1 /DDR_Banks/M0_DQ3 ) + ( M2 /DDR_Banks/M0_DQ2 ) + ( N1 /DDR_Banks/M0_DQ1 ) + ( N3 /DDR_Banks/M0_DQ0 ) + ( P1 /DDR_Banks/M0_DQ9 ) + ( P2 /DDR_Banks/M0_DQ8 ) + ( R1 /DDR_Banks/M0_DQ11 ) + ( R3 /DDR_Banks/M0_DQ10 ) + ( T1 ? ) + ( T2 /DDR_Banks/M0_UDQS ) + ( U1 /DDR_Banks/M0_DQ13 ) + ( U3 /DDR_Banks/M0_DQ12 ) + ( V1 /DDR_Banks/M0_DQ15 ) + ( V2 /DDR_Banks/M0_DQ14 ) + ( M4 ? ) + ( M5 ? ) + ( N4 ? ) + ( P3 ? ) + ( L6 ? ) + ( M6 ? ) + ( P4 ? ) + ( R4 ? ) + ( M8 ? ) + ( M7 ? ) + ( N7 ? ) + ( N6 ? ) + ( V3 ? ) + ( U4 ? ) + ( T3 ? ) + ( T4 ? ) + ( P5 ? ) + ( P6 ? ) + ( P7 ? ) + ( P8 ? ) + ( W1 ? ) + ( W3 ? ) + ( Y1 ? ) + ( W21 N-000121 ) + ( C21 N-000121 ) + ( G21 N-000121 ) + ( J18 N-000121 ) + ( L16 N-000121 ) + ( L21 N-000121 ) + ( N18 N-000121 ) + ( R21 N-000121 ) + ( U18 N-000121 ) + ( E19 N-000121 ) + ( L19 /DDR_Banks/M1_LDM ) + ( J20 /DDR_Banks/M1_DQ4 ) + ( J22 /DDR_Banks/M1_DQ5 ) + ( K21 /DDR_Banks/M1_DQ6 ) + ( K22 /DDR_Banks/M1_DQ7 ) + ( L20 /DDR_Banks/M1_LDQS ) + ( L22 ? ) + ( M21 /DDR_Banks/M1_DQ2 ) + ( M22 /DDR_Banks/M1_DQ3 ) + ( N20 /DDR_Banks/M1_DQ0 ) + ( N22 /DDR_Banks/M1_DQ1 ) + ( P21 /DDR_Banks/M1_DQ8 ) + ( P22 /DDR_Banks/M1_DQ9 ) + ( R20 /DDR_Banks/M1_DQ10 ) + ( R22 /DDR_Banks/M1_DQ11 ) + ( T21 /DDR_Banks/M1_UDQS ) + ( T22 ? ) + ( U20 /DDR_Banks/M1_DQ12 ) + ( U22 /DDR_Banks/M1_DQ13 ) + ( V21 /DDR_Banks/M1_DQ14 ) + ( V22 /DDR_Banks/M1_DQ15 ) + ( M19 ? ) + ( N19 ? ) + ( M16 ? ) + ( L15 ? ) + ( P19 ? ) + ( P20 ? ) + ( W20 ? ) + ( W22 ? ) + ( L17 ? ) + ( K18 ? ) + ( U19 ? ) + ( V20 ? ) + ( M17 ? ) + ( M18 ? ) + ( P17 ? ) + ( N16 ? ) + ( P18 ? ) + ( R19 ? ) + ( T19 ? ) + ( T20 ? ) + ( M20 /DDR_Banks/M1_UDM ) + ( H22 /DDR_Banks/M1_CAS# ) + ( H21 /DDR_Banks/M1_RAS# ) + ( K19 /DDR_Banks/M1_A6 ) + ( K20 /DDR_Banks/M1_A5 ) + ( G22 ? ) + ( G20 /DDR_Banks/M1_A3 ) + ( J19 /DDR_Banks/M1_CLK# ) + ( H20 /DDR_Banks/M1_CLK ) + ( F22 /DDR_Banks/M1_A1 ) + ( F21 /DDR_Banks/M1_A0 ) + ( K17 ? ) + ( J17 ? ) + ( E22 /DDR_Banks/M1_A2 ) + ( E20 /DDR_Banks/M1_A7 ) + ( H18 ? ) + ( H19 /DDR_Banks/M1_WE# ) + ( F20 /DDR_Banks/M1_A4 ) + ( G19 /DDR_Banks/M1_A10 ) + ( C22 /DDR_Banks/M1_A9 ) + ( C20 /DDR_Banks/M1_A8 ) + ( D22 /DDR_Banks/M1_A12 ) + ( D21 /DDR_Banks/M1_CKE ) + ( F19 /DDR_Banks/M1_A11 ) + ( F18 ? ) + ( D20 ? ) + ( D19 ? ) + ( H17 ? ) + ( H16 ? ) + ( J16 ? ) + ( K16 ? ) + ( A21 ? ) + ( A20 ? ) + ( B22 ? ) + ( B21 ? ) + ( F17 ? ) + ( F16 ? ) + ( G17 ? ) + ( G16 ? ) + ( B20 ? ) + ( B4 N-000122 ) + ( B7 N-000122 ) + ( E13 N-000122 ) + ( E17 N-000122 ) + ( G10 N-000122 ) + ( G14 N-000122 ) + ( B11 N-000122 ) + ( B15 N-000122 ) + ( B19 N-000122 ) + ( E9 N-000122 ) + ( A11 ? ) + ( D11 ? ) + ( C12 ? ) + ( B12 ? ) + ( A12 ? ) + ( C13 ? ) + ( A13 ? ) + ( D14 ? ) + ( C14 ? ) + ( B14 ? ) + ( A14 ? ) + ( C15 ? ) + ( A15 ? ) + ( D15 ? ) + ( C16 ? ) + ( B16 ? ) + ( A16 ? ) + ( C17 ? ) + ( A17 ? ) + ( B18 ? ) + ( A18 ? ) + ( E16 ? ) + ( D17 ? ) + ( C11 ? ) + ( A10 ? ) + ( B10 ? ) + ( C10 ? ) + ( D10 ? ) + ( D8 ? ) + ( D7 ? ) + ( A9 ? ) + ( C9 ? ) + ( C8 ? ) + ( D9 ? ) + ( A8 ? ) + ( B8 ? ) + ( A7 ? ) + ( C7 ? ) + ( A6 ? ) + ( B6 ? ) + ( C6 ? ) + ( D6 ? ) + ( A5 /FPGA_Spartan6/ETH_INT ) + ( C5 ? ) + ( A4 ? ) ) - ( /4C421DD3/4C58C847 60fbga_ddr U2 MT46V32M16FN - ( A1 GND ) - ( A2 /DDR_Ban33 ) - ( A3 GND ) - ( A7 N-000039 ) - ( A8 /DDR_Ban26 ) - ( A9 N-000039 ) - ( B1 /DDR_Ban34 ) - ( B2 N-000039 ) - ( B3 /DDR_Ban31 ) - ( B7 /DDR_Ban24 ) - ( B8 GND ) - ( B9 /DDR_Ban25 ) - ( C1 /DDR_Ban32 ) - ( C2 GND ) - ( C3 /DDR_Ban29 ) - ( C7 /DDR_Ban19 ) - ( C8 N-000039 ) - ( C9 /DDR_Ban23 ) - ( D1 /DDR_Ban30 ) - ( D2 N-000039 ) - ( D3 /DDR_Ban27 ) - ( D7 /DDR_Ban22 ) - ( D8 GND ) - ( D9 /DDR_Ban18 ) - ( E1 /DDR_Ban28 ) - ( E2 GND ) - ( E3 ? ) - ( E7 ? ) - ( E8 N-000039 ) - ( E9 /DDR_Ban21 ) - ( F1 ? ) - ( F2 GND ) - ( F3 ? ) - ( F7 ? ) - ( F8 N-000039 ) - ( F9 ? ) - ( G2 /DDR_Ban16 ) - ( G3 /DDR_Ban15 ) - ( G7 ? ) - ( G8 ? ) - ( H2 /DDR_Ban10 ) - ( H3 ? ) - ( H7 ? ) - ( H8 ? ) - ( J2 /DDR_Ban9 ) - ( J3 /DDR_Banks/M0_A9 ) - ( J7 ? ) - ( J8 ? ) - ( K2 /DDR_Banks/M0_A8 ) - ( K3 /DDR_Banks/M0_A7 ) - ( K7 /DDR_Banks/M0_A0 ) - ( K8 /DDR_Ban13 ) - ( L2 /DDR_Banks/M0_A6 ) - ( L3 /DDR_Banks/M0_A5 ) - ( L7 /DDR_Banks/M0_A2 ) - ( L8 /DDR_Banks/M0_A1 ) - ( M2 /DDR_Banks/M0_A4 ) - ( M3 GND ) - ( M7 N-000039 ) - ( M8 /DDR_Banks/M0_A3 ) + ( /4C5F1EDC/4C5F2D27 $noname R? 1M {Lib=R} + ( 1 N-000412 ) + ( 2 GND ) ) - ( /4C421DD3/4C58CA3A 60fbga_ddr U3 MT46V32M16FN - ( A1 GND ) - ( A2 ? ) - ( A3 GND ) - ( A7 N-000041 ) - ( A8 ? ) - ( A9 N-000041 ) - ( B1 ? ) - ( B2 N-000041 ) - ( B3 ? ) - ( B7 ? ) - ( B8 GND ) - ( B9 ? ) - ( C1 ? ) - ( C2 GND ) - ( C3 ? ) - ( C7 ? ) - ( C8 N-000041 ) - ( C9 ? ) - ( D1 ? ) - ( D2 N-000041 ) - ( D3 ? ) - ( D7 ? ) - ( D8 GND ) - ( D9 ? ) - ( E1 ? ) - ( E2 GND ) - ( E3 ? ) - ( E7 ? ) - ( E8 N-000041 ) - ( E9 ? ) - ( F1 ? ) - ( F2 GND ) - ( F3 ? ) - ( F7 ? ) - ( F8 N-000041 ) - ( F9 ? ) - ( G2 /DDR_Ban17 ) - ( G3 /DDR_Ban20 ) - ( G7 ? ) - ( G8 ? ) - ( H2 /DDR_Ban11 ) - ( H3 ? ) - ( H7 ? ) - ( H8 ? ) - ( J2 /DDR_Ban12 ) - ( J3 /DDR_Banks/M1_A9 ) - ( J7 ? ) - ( J8 ? ) - ( K2 /DDR_Banks/M1_A8 ) - ( K3 /DDR_Banks/M1_A7 ) - ( K7 /DDR_Banks/M1_A0 ) - ( K8 /DDR_Ban14 ) - ( L2 /DDR_Banks/M1_A6 ) - ( L3 /DDR_Banks/M1_A5 ) - ( L7 /DDR_Banks/M1_A2 ) - ( L8 /DDR_Banks/M1_A1 ) - ( M2 /DDR_Banks/M1_A4 ) - ( M3 GND ) - ( M7 N-000041 ) - ( M8 /DDR_Banks/M1_A3 ) + ( /4C5F1EDC/4C5F2D1E $noname C? 4.7nF {Lib=C} + ( 1 N-000412 ) + ( 2 GND ) ) - ( /4C4320F3/4C432132 LQFP48 U4 K8001 - ( 1 /Etherne7 ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) - ( 7 N-000061 ) - ( 8 GND ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 GND ) - ( 13 /Etherne2 ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ( 17 ? ) - ( 18 ? ) - ( 19 ? ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 GND ) - ( 24 N-000061 ) - ( 25 /FPGA_Sp8 ) - ( 26 /Etherne5 ) - ( 27 /Etherne6 ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 /Etherne3 ) - ( 32 N-000417 ) - ( 33 N-000413 ) - ( 34 ? ) - ( 35 GND ) - ( 36 GND ) - ( 37 N-000419 ) - ( 38 /Etherne1 ) - ( 39 GND ) - ( 40 N-000416 ) - ( 41 N-000410 ) - ( 42 ? ) - ( 43 ? ) - ( 44 GND ) - ( 45 ? ) - ( 46 ? ) - ( 47 /Etherne4 ) - ( 48 ? ) + ( /4C5F1EDC/4C5F2CA7 $noname V? V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000410 ) + ( 2 GND ) ) - ( /4C4227FE/4B76F108 NAND-48TSOP U5 NAND - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 /Non_vol35 ) - ( 7 /Non_vol35 ) - ( 8 ? ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 N-000061 ) - ( 13 GND ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ( 17 ? ) - ( 18 ? ) - ( 19 N-000061 ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 ? ) - ( 24 ? ) - ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 ? ) - ( 32 ? ) - ( 33 ? ) - ( 34 ? ) - ( 35 ? ) - ( 36 GND ) - ( 37 N-000061 ) - ( 38 ? ) - ( 39 ? ) - ( 40 ? ) - ( 41 ? ) - ( 42 ? ) - ( 43 ? ) - ( 44 ? ) - ( 45 ? ) - ( 46 ? ) - ( 47 ? ) - ( 48 ? ) + ( /4C5F1EDC/4C5F2CA3 $noname V? V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000409 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2B55 $noname F? MICROSMD075F {Lib=MICROSMD075F} + ( 1 N-000411 ) + ( 2 ? ) + ) + ( /4C5F1EDC/4C5F23DD $noname J? USB-48204-0001 {Lib=USB-48204-0001} + ( S1 N-000412 ) + ( S2 N-000412 ) + ( S3 N-000412 ) + ( S4 N-000412 ) + ( 1 N-000411 ) + ( 2 N-000409 ) + ( 3 N-000410 ) + ( 4 GND ) + ) + ( /4C5F1EDC/4C5F2039 $noname C? 470nF {Lib=C} + ( 1 N-000068 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2037 $noname C? 1uF {Lib=C} + ( 1 N-000068 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2033 $noname C? 1uF {Lib=C} + ( 1 N-000068 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} + ( 1 N-000068 ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 7 GND ) + ( 8 GND ) + ( 9 ? ) + ( 10 N-000409 ) + ( 11 N-000410 ) + ( 12 N-000068 ) + ( 14 N-000068 ) + ) + ( /4C4320F3/4C5D8114 $noname C? C {Lib=C} + ( 1 /Ethernet_Phy/ETH_PLL1.8V ) + ( 2 N-000395 ) + ) + ( /4C4320F3/4C5D810A $noname L? INDUCTOR {Lib=INDUCTOR} + ( 1 /Ethernet_Phy/ETH_A1.8V ) + ( 2 /Ethernet_Phy/ETH_PLL1.8V ) + ) + ( /4C4320F3/4C5D8104 $noname C? C {Lib=C} + ( 1 /Ethernet_Phy/ETH_A1.8V ) + ( 2 N-000395 ) + ) + ( /4C4320F3/4C5D80F3 $noname L? INDUCTOR {Lib=INDUCTOR} + ( 1 N-000394 ) + ( 2 /Ethernet_Phy/ETH_A1.8V ) + ) + ( /4C4320F3/4C5D80F0 $noname C? C {Lib=C} + ( 1 N-000394 ) + ( 2 N-000395 ) + ) + ( /4C4320F3/4C5D80ED $noname C? C {Lib=C} + ( 1 /Ethernet_Phy/ETH_1.8V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FB7 $noname L? FB {Lib=INDUCTOR} + ( 1 N-000068 ) + ( 2 /Ethernet_Phy/ETH_A3.3V ) + ) + ( /4C4320F3/4C5D7FA7 $noname C? 100nF {Lib=C} + ( 1 /Ethernet_Phy/ETH_A3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FA5 $noname C? 1uF {Lib=C} + ( 1 /Ethernet_Phy/ETH_A3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FA3 $noname C? 100nF {Lib=C} + ( 1 N-000068 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FA1 $noname C? 100nF {Lib=C} + ( 1 N-000068 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7F9F $noname C? 1uF {Lib=C} + ( 1 N-000068 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7F39 $noname R? 4.7K {Lib=R} + ( 1 /ETH_MDIO ) + ( 2 N-000068 ) + ) + ( /4C4320F3/4C5D7ECF $noname R? 6.65K {Lib=R} + ( 1 N-000384 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7E43 $noname C? 100nF {Lib=C} + ( 1 N-000068 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7E41 $noname C? 100nF {Lib=C} + ( 1 N-000068 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7DCB $noname C? 47nF {Lib=C} + ( 1 N-000393 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7DC4 $noname R? 1M {Lib=R} + ( 1 N-000393 ) + ( 2 GND ) + ) + ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} + ( 1 /ETH_MDIO ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 ? ) + ( 7 N-000068 ) + ( 8 GND ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 GND ) + ( 13 /Ethernet_Phy/ETH_1.8V ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ( 17 ? ) + ( 18 ? ) + ( 19 ? ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 GND ) + ( 24 N-000068 ) + ( 25 /FPGA_Spartan6/ETH_INT ) + ( 26 /Ethernet_Phy/ETH_LED0 ) + ( 27 /Ethernet_Phy/ETH_LED1 ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 /Ethernet_Phy/ETH_A1.8V ) + ( 32 N-000385 ) + ( 33 N-000392 ) + ( 34 ? ) + ( 35 GND ) + ( 36 GND ) + ( 37 N-000384 ) + ( 38 /Ethernet_Phy/ETH_A3.3V ) + ( 39 GND ) + ( 40 N-000386 ) + ( 41 N-000391 ) + ( 42 ? ) + ( 43 ? ) + ( 44 GND ) + ( 45 ? ) + ( 46 ? ) + ( 47 /Ethernet_Phy/ETH_PLL1.8V ) + ( 48 ? ) + ) + ( /4C4320F3/4C5D7AFE $noname R? 49.9 {Lib=R} + ( 1 N-000068 ) + ( 2 N-000391 ) + ) + ( /4C4320F3/4C5D7AFC $noname R? 49.9 {Lib=R} + ( 1 N-000068 ) + ( 2 N-000386 ) + ) + ( /4C4320F3/4C5D7AF9 $noname R? 49.9 {Lib=R} + ( 1 N-000068 ) + ( 2 N-000385 ) + ) + ( /4C4320F3/4C5D7AF7 $noname R? 49.9 {Lib=R} + ( 1 N-000068 ) + ( 2 N-000392 ) + ) + ( /4C4320F3/4C5D71DB $noname R? 220 {Lib=R} + ( 1 N-000388 ) + ( 2 /Ethernet_Phy/ETH_LED1 ) + ) + ( /4C4320F3/4C5D719D $noname R? 220 {Lib=R} + ( 1 N-000389 ) + ( 2 /Ethernet_Phy/ETH_LED0 ) + ) + ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} + ( 1 N-000391 ) + ( 2 N-000386 ) + ( 3 N-000068 ) + ( 4 GND ) + ( 5 GND ) + ( 6 N-000068 ) + ( 7 N-000392 ) + ( 8 N-000385 ) + ( 9 N-000068 ) + ( 10 N-000389 ) + ( 11 N-000068 ) + ( 12 N-000388 ) + ( 13 N-000393 ) + ( 14 N-000393 ) + ) + ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} + ( CASE GND ) + ( CD ? ) + ( COM GND ) + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 ? ) + ( 7 ? ) + ( 8 ? ) + ) + ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 /Non_volatile_memories/FRB_N ) + ( 7 /Non_volatile_memories/FRB_N ) + ( 8 ? ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 N-000068 ) + ( 13 GND ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ( 17 ? ) + ( 18 ? ) + ( 19 N-000068 ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 ? ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 ? ) + ( 32 ? ) + ( 33 ? ) + ( 34 ? ) + ( 35 ? ) + ( 36 GND ) + ( 37 N-000068 ) + ( 38 ? ) + ( 39 ? ) + ( 40 ? ) + ( 41 ? ) + ( 42 ? ) + ( 43 ? ) + ( 44 ? ) + ( 45 ? ) + ( 46 ? ) + ( 47 ? ) + ( 48 ? ) + ) + ( /4C421DD3/4C58CA3A 60fbga_ddr U3 MT46V32M16FN {Lib=MT46V32M16FN} + ( A7 N-000048 ) + ( F8 N-000048 ) + ( M7 N-000048 ) + ( A9 N-000048 ) + ( B2 N-000048 ) + ( C8 N-000048 ) + ( D2 N-000048 ) + ( E8 N-000048 ) + ( B7 /DDR_Banks/M1_DQ2 ) + ( C9 /DDR_Banks/M1_DQ3 ) + ( C7 /DDR_Banks/M1_DQ4 ) + ( D9 /DDR_Banks/M1_DQ5 ) + ( D7 /DDR_Banks/M1_DQ6 ) + ( E9 /DDR_Banks/M1_DQ7 ) + ( E1 /DDR_Banks/M1_DQ8 ) + ( D3 /DDR_Banks/M1_DQ9 ) + ( D1 /DDR_Banks/M1_DQ10 ) + ( C3 /DDR_Banks/M1_DQ11 ) + ( C1 /DDR_Banks/M1_DQ12 ) + ( B3 /DDR_Banks/M1_DQ13 ) + ( B1 /DDR_Banks/M1_DQ14 ) + ( A2 /DDR_Banks/M1_DQ15 ) + ( F7 /DDR_Banks/M1_LDM ) + ( E7 /DDR_Banks/M1_LDQS ) + ( F9 ? ) + ( H7 /DDR_Banks/M1_RAS# ) + ( F3 /DDR_Banks/M1_UDM ) + ( E3 /DDR_Banks/M1_UDQS ) + ( F1 ? ) + ( G7 /DDR_Banks/M1_WE# ) + ( B9 /DDR_Banks/M1_DQ1 ) + ( A8 /DDR_Banks/M1_DQ0 ) + ( H8 ? ) + ( G3 /DDR_Banks/M1_CLK# ) + ( G2 /DDR_Banks/M1_CLK ) + ( H3 /DDR_Banks/M1_CKE ) + ( G8 /DDR_Banks/M1_CAS# ) + ( J7 ? ) + ( J8 ? ) + ( H2 /DDR_Banks/M1_A12 ) + ( J2 /DDR_Banks/M1_A11 ) + ( K8 /DDR_Banks/M1_A10 ) + ( J3 /DDR_Banks/M1_A9 ) + ( K2 /DDR_Banks/M1_A8 ) + ( K3 /DDR_Banks/M1_A7 ) + ( L2 /DDR_Banks/M1_A6 ) + ( L3 /DDR_Banks/M1_A5 ) + ( M2 /DDR_Banks/M1_A4 ) + ( M8 /DDR_Banks/M1_A3 ) + ( L7 /DDR_Banks/M1_A2 ) + ( L8 /DDR_Banks/M1_A1 ) + ( K7 /DDR_Banks/M1_A0 ) + ( A3 GND ) + ( F2 GND ) + ( M3 GND ) + ( A1 GND ) + ( B8 GND ) + ( C2 GND ) + ( D8 GND ) + ( E2 GND ) + ) + ( /4C421DD3/4C58C847 60fbga_ddr U2 MT46V32M16FN {Lib=MT46V32M16FN} + ( A7 N-000046 ) + ( F8 N-000046 ) + ( M7 N-000046 ) + ( A9 N-000046 ) + ( B2 N-000046 ) + ( C8 N-000046 ) + ( D2 N-000046 ) + ( E8 N-000046 ) + ( B7 /DDR_Banks/M0_DQ2 ) + ( C9 /DDR_Banks/M0_DQ3 ) + ( C7 /DDR_Banks/M0_DQ4 ) + ( D9 /DDR_Banks/M0_DQ5 ) + ( D7 /DDR_Banks/M0_DQ6 ) + ( E9 /DDR_Banks/M0_DQ7 ) + ( E1 /DDR_Banks/M0_DQ8 ) + ( D3 /DDR_Banks/M0_DQ9 ) + ( D1 /DDR_Banks/M0_DQ10 ) + ( C3 /DDR_Banks/M0_DQ11 ) + ( C1 /DDR_Banks/M0_DQ12 ) + ( B3 /DDR_Banks/M0_DQ13 ) + ( B1 /DDR_Banks/M0_DQ14 ) + ( A2 /DDR_Banks/M0_DQ15 ) + ( F7 /DDR_Banks/M0_LDM ) + ( E7 /DDR_Banks/M0_LDQS ) + ( F9 ? ) + ( H7 /DDR_Banks/M0_RAS# ) + ( F3 /DDR_Banks/M0_UDM ) + ( E3 /DDR_Banks/M0_UDQS ) + ( F1 ? ) + ( G7 /DDR_Banks/M0_WE# ) + ( B9 /DDR_Banks/M0_DQ1 ) + ( A8 /DDR_Banks/M0_DQ0 ) + ( H8 ? ) + ( G3 /DDR_Banks/M0_CLK# ) + ( G2 /DDR_Banks/M0_CLK ) + ( H3 /DDR_Banks/M0_CKE ) + ( G8 /DDR_Banks/M0_CAS# ) + ( J7 ? ) + ( J8 ? ) + ( H2 /DDR_Banks/M0_A12 ) + ( J2 /DDR_Banks/M0_A11 ) + ( K8 /DDR_Banks/M0_A10 ) + ( J3 /DDR_Banks/M0_A9 ) + ( K2 /DDR_Banks/M0_A8 ) + ( K3 /DDR_Banks/M0_A7 ) + ( L2 /DDR_Banks/M0_A6 ) + ( L3 /DDR_Banks/M0_A5 ) + ( M2 /DDR_Banks/M0_A4 ) + ( M8 /DDR_Banks/M0_A3 ) + ( L7 /DDR_Banks/M0_A2 ) + ( L8 /DDR_Banks/M0_A1 ) + ( K7 /DDR_Banks/M0_A0 ) + ( A3 GND ) + ( F2 GND ) + ( M3 GND ) + ( A1 GND ) + ( B8 GND ) + ( C2 GND ) + ( D8 GND ) + ( E2 GND ) ) ) * { Allowed footprints by component: +$component R? + R? + SM0603 + SM0805 +$endlist $component C? SM* C? C1-1 +$endlist +$component C? SM* C? C1-1 +$endlist +$component C? SM* C? C1-1 +$endlist +$component C? SM* C? C1-1 +$endlist +$component C? SM* C? C1-1 +$endlist +$component C? SM* C? C1-1 +$endlist +$component C? SM* C? C1-1 +$endlist +$component C? SM* C? C1-1 +$endlist +$component C? SM* C? C1-1 +$endlist +$component C? SM* C? C1-1 +$endlist +$component C? SM* C? C1-1 +$endlist +$component C? + SM* + C? + C1-1 +$endlist +$component C? SM* C? C1-1 @@ -875,30 +963,626 @@ $component R? R? SM0603 SM0805 +$endlist +$component R? R? SM0603 SM0805 +$endlist +$component C? + SM* + C? + C1-1 +$endlist +$component C? + SM* + C? + C1-1 +$endlist +$component C? + SM* + C? + C1-1 +$endlist +$component R? R? SM0603 SM0805 +$endlist +$component R? R? SM0603 SM0805 +$endlist +$component R? R? SM0603 SM0805 +$endlist +$component R? R? SM0603 SM0805 +$endlist +$component R? R? SM0603 SM0805 +$endlist +$component R? R? SM0603 SM0805 +$endlist +$component R? R? SM0603 SM0805 $endlist $endfootprintlist } +{ Pin List by Nets +Net 9 "/ETH_MDIO" "ETH_MDIO" + R? 1 + U4 1 +Net 13 "/DDR Banks/M1_LDM" "M1_LDM" + U3 F7 + U1 L19 +Net 14 "/DDR Banks/M1_CKE" "M1_CKE" + U3 H3 + U1 D21 +Net 15 "/DDR Banks/M1_CAS#" "M1_CAS#" + U3 G8 + U1 H22 +Net 16 "/DDR Banks/M0_CKE" "M0_CKE" + U2 H3 + U1 D2 +Net 17 "/DDR Banks/M0_WE#" "M0_WE#" + U2 G7 + U1 F2 +Net 18 "/DDR Banks/M0_CAS#" "M0_CAS#" + U2 G8 + U1 K4 +Net 19 "/DDR Banks/M0_UDM" "M0_UDM" + U2 F3 + U1 M3 +Net 20 "/DDR Banks/M0_UDQS" "M0_UDQS" + U2 E3 + U1 T2 +Net 21 "/DDR Banks/M1_CLK#" "M1_CLK#" + U3 G3 + U1 J19 +Net 22 "/DDR Banks/M0_CLK#" "M0_CLK#" + U2 G3 + U1 H3 +Net 23 "/DDR Banks/M0_CLK" "M0_CLK" + U2 G2 + U1 H4 +Net 24 "/DDR Banks/M1_CLK" "M1_CLK" + U3 G2 + U1 H20 +Net 25 "/DDR Banks/M0_LDM" "M0_LDM" + U2 F7 + U1 L4 +Net 26 "/DDR Banks/M0_LDQS" "M0_LDQS" + U2 E7 + U1 L3 +Net 27 "/DDR Banks/M0_RAS#" "M0_RAS#" + U2 H7 + U1 K5 +Net 29 "/DDR Banks/M1_RAS#" "M1_RAS#" + U3 H7 + U1 H21 +Net 30 "/DDR Banks/M1_WE#" "M1_WE#" + U3 G7 + U1 H19 +Net 31 "/DDR Banks/M1_UDM" "M1_UDM" + U3 F3 + U1 M20 +Net 32 "/DDR Banks/M1_LDQS" "M1_LDQS" + U3 E7 + U1 L20 +Net 33 "/DDR Banks/M1_UDQS" "M1_UDQS" + U3 E3 + U1 T21 +Net 34 "/FPGA Spartan6/ETH_INT" "ETH_INT" + U1 A5 + U4 25 +Net 45 "GND" "GND" + U3 A3 + U3 F2 + U3 M3 + U3 A1 + U3 B8 + U3 C2 + U3 D8 + U3 E2 + U2 A3 + U2 F2 + U2 M3 + U2 A1 + U2 B8 + U2 C2 + U2 D8 + U2 E2 + J1 CASE + J1 CASE + J1 CASE + J1 COM + U5 36 + U5 13 + U1 P10 + U1 V10 + U1 M10 + U1 K10 + U1 L13 + U1 A1 + U1 N13 + U1 A22 + U1 R5 + U1 AA13 + U1 W19 + U1 AA17 + U1 K14 + U1 AA5 + U1 L5 + U1 AA9 + U1 M14 + U1 AB1 + U1 N2 + U1 AB22 + U1 P14 + U1 B13 + U1 U21 + U1 B17 + U1 V4 + U1 B5 + U1 J9 + U1 B9 + U1 K12 + U1 D18 + U1 L11 + U1 D4 + U1 L18 + U1 E11 + U1 L9 + U1 E15 + U1 M12 + U1 E2 + U1 N11 + U1 E21 + U1 N17 + U1 E7 + U1 N21 + U1 G18 + U1 P12 + U1 G5 + U1 R18 + U1 H7 + U1 U2 + U1 J11 + U1 U7 + U1 J13 + U1 V14 + U1 J15 + U1 W16 + U1 J2 + U1 W7 + U1 J21 + U1 N9 + C? 2 + C? 2 + C? 2 + C? 2 + C? 2 + C? 2 + R? 2 + C? 2 + C? 2 + C? 2 + R? 2 + U4 8 + U4 12 + U4 23 + U4 35 + U4 36 + U4 39 + U4 44 + J4 5 + J4 4 + R? 2 + C? 2 + V? 2 + V? 2 + J? 4 + C? 2 + C? 2 + C? 2 + U6 8 + U6 7 +Net 46 "" "" + U2 A7 + U2 F8 + U2 M7 + U2 A9 + U2 B2 + U2 C8 + U2 D2 + U2 E8 +Net 48 "" "" + U3 A7 + U3 F8 + U3 M7 + U3 A9 + U3 B2 + U3 C8 + U3 D2 + U3 E8 +Net 68 "" "" + U5 37 + U5 19 + U5 12 + L? 1 + C? 1 + C? 1 + C? 1 + R? 2 + C? 1 + C? 1 + U4 7 + U4 24 + R? 1 + R? 1 + R? 1 + R? 1 + J4 11 + J4 9 + J4 6 + J4 3 + C? 1 + C? 1 + C? 1 + U6 14 + U6 12 + U6 1 +Net 71 "/Non volatile memories/FRB_N" "FRB_N" + U5 7 + U5 6 +Net 118 "" "" + U1 N10 + U1 P11 + U1 P13 + U1 P9 + U1 R14 + U1 N12 + U1 J10 + U1 J12 + U1 J14 + U1 J8 + U1 K11 + U1 K13 + U1 K9 + U1 L10 + U1 L12 + U1 L14 + U1 M11 + U1 M13 + U1 M9 + U1 N14 +Net 119 "" "" + U1 H9 + U1 U11 + U1 F11 + U1 R6 + U1 M15 + U1 V6 + U1 G12 + U1 H15 + U1 D16 + U1 K15 + U1 R12 + U1 N8 + U1 R10 + U1 L8 +Net 120 "" "" + U1 W2 + U1 L2 + U1 L7 + U1 C2 + U1 N5 + U1 R2 + U1 U5 + U1 G2 + U1 F4 + U1 F6 + U1 J5 +Net 121 "" "" + U1 W21 + U1 C21 + U1 G21 + U1 J18 + U1 L16 + U1 L21 + U1 N18 + U1 R21 + U1 U18 + U1 E19 +Net 122 "" "" + U1 B4 + U1 B7 + U1 E13 + U1 E17 + U1 G10 + U1 G14 + U1 B11 + U1 B15 + U1 B19 + U1 E9 +Net 123 "" "" + U1 AA15 + U1 V16 + U1 T13 + U1 V8 + U1 V12 + U1 AA3 + U1 T9 + U1 AA19 + U1 AA11 + U1 W5 + U1 AA7 +Net 382 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + L? 1 + C? 1 + L? 2 + U4 31 +Net 383 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + L? 2 + C? 1 + C? 1 + U4 38 +Net 384 "" "" + R? 1 + U4 37 +Net 385 "" "" + U4 32 + R? 2 + J4 8 +Net 386 "" "" + U4 40 + R? 2 + J4 2 +Net 387 "/Ethernet Phy/ETH_LED1" "ETH_LED1" + U4 27 + R? 2 +Net 388 "" "" + R? 1 + J4 12 +Net 389 "" "" + R? 1 + J4 10 +Net 390 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + U4 26 + R? 2 +Net 391 "" "" + U4 41 + R? 2 + J4 1 +Net 392 "" "" + U4 33 + R? 2 + J4 7 +Net 393 "" "" + C? 1 + R? 1 + J4 13 + J4 14 +Net 394 "" "" + L? 1 + C? 1 +Net 395 "" "" + C? 2 + C? 2 + C? 2 +Net 396 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" + C? 1 + U4 13 +Net 397 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + C? 1 + L? 2 + U4 47 +Net 409 "" "" + V? 1 + V? 1 + J? 2 + U6 10 +Net 410 "" "" + V? 1 + V? 1 + J? 3 + U6 11 +Net 411 "" "" + F? 1 + J? 1 +Net 412 "" "" + R? 1 + C? 1 + J? S1 + J? S2 + J? S3 + J? S4 +Net 423 "/DDR Banks/M0_A0" "M0_A0" + U2 K7 + U1 H2 +Net 424 "/DDR Banks/M0_A1" "M0_A1" + U2 L8 + U1 H1 +Net 425 "/DDR Banks/M0_A2" "M0_A2" + U2 L7 + U1 H5 +Net 426 "/DDR Banks/M0_A3" "M0_A3" + U2 M8 + U1 K6 +Net 427 "/DDR Banks/M0_A4" "M0_A4" + U2 M2 + U1 F3 +Net 428 "/DDR Banks/M0_A5" "M0_A5" + U2 L3 + U1 K3 +Net 429 "/DDR Banks/M0_A6" "M0_A6" + U2 L2 + U1 J4 +Net 430 "/DDR Banks/M0_A7" "M0_A7" + U2 K3 + U1 H6 +Net 431 "/DDR Banks/M0_A8" "M0_A8" + U2 K2 + U1 E3 +Net 432 "/DDR Banks/M0_A9" "M0_A9" + U2 J3 + U1 E1 +Net 433 "/DDR Banks/M0_A10" "M0_A10" + U2 K8 + U1 G4 +Net 434 "/DDR Banks/M0_A11" "M0_A11" + U2 J2 + U1 C1 +Net 435 "/DDR Banks/M0_A12" "M0_A12" + U2 H2 + U1 D1 +Net 436 "/DDR Banks/M1_A0" "M1_A0" + U3 K7 + U1 F21 +Net 437 "/DDR Banks/M1_A1" "M1_A1" + U3 L8 + U1 F22 +Net 438 "/DDR Banks/M1_A2" "M1_A2" + U3 L7 + U1 E22 +Net 439 "/DDR Banks/M1_A3" "M1_A3" + U3 M8 + U1 G20 +Net 440 "/DDR Banks/M1_A4" "M1_A4" + U3 M2 + U1 F20 +Net 441 "/DDR Banks/M1_A5" "M1_A5" + U3 L3 + U1 K20 +Net 442 "/DDR Banks/M1_A6" "M1_A6" + U3 L2 + U1 K19 +Net 443 "/DDR Banks/M1_A7" "M1_A7" + U3 K3 + U1 E20 +Net 444 "/DDR Banks/M1_A8" "M1_A8" + U3 K2 + U1 C20 +Net 445 "/DDR Banks/M1_A9" "M1_A9" + U3 J3 + U1 C22 +Net 446 "/DDR Banks/M1_A10" "M1_A10" + U3 K8 + U1 G19 +Net 447 "/DDR Banks/M1_A11" "M1_A11" + U3 J2 + U1 F19 +Net 448 "/DDR Banks/M1_A12" "M1_A12" + U3 H2 + U1 D22 +Net 449 "/DDR Banks/M0_DQ0" "M0_DQ0" + U2 A8 + U1 N3 +Net 450 "/DDR Banks/M0_DQ1" "M0_DQ1" + U2 B9 + U1 N1 +Net 451 "/DDR Banks/M0_DQ2" "M0_DQ2" + U2 B7 + U1 M2 +Net 452 "/DDR Banks/M0_DQ3" "M0_DQ3" + U2 C9 + U1 M1 +Net 453 "/DDR Banks/M0_DQ4" "M0_DQ4" + U2 C7 + U1 J3 +Net 454 "/DDR Banks/M0_DQ5" "M0_DQ5" + U2 D9 + U1 J1 +Net 455 "/DDR Banks/M0_DQ6" "M0_DQ6" + U2 D7 + U1 K2 +Net 456 "/DDR Banks/M0_DQ7" "M0_DQ7" + U2 E9 + U1 K1 +Net 457 "/DDR Banks/M0_DQ8" "M0_DQ8" + U2 E1 + U1 P2 +Net 458 "/DDR Banks/M0_DQ9" "M0_DQ9" + U2 D3 + U1 P1 +Net 459 "/DDR Banks/M0_DQ10" "M0_DQ10" + U2 D1 + U1 R3 +Net 460 "/DDR Banks/M0_DQ11" "M0_DQ11" + U2 C3 + U1 R1 +Net 461 "/DDR Banks/M0_DQ12" "M0_DQ12" + U2 C1 + U1 U3 +Net 462 "/DDR Banks/M0_DQ13" "M0_DQ13" + U2 B3 + U1 U1 +Net 463 "/DDR Banks/M0_DQ14" "M0_DQ14" + U2 B1 + U1 V2 +Net 464 "/DDR Banks/M0_DQ15" "M0_DQ15" + U2 A2 + U1 V1 +Net 465 "/DDR Banks/M1_DQ0" "M1_DQ0" + U3 A8 + U1 N20 +Net 466 "/DDR Banks/M1_DQ1" "M1_DQ1" + U3 B9 + U1 N22 +Net 467 "/DDR Banks/M1_DQ2" "M1_DQ2" + U3 B7 + U1 M21 +Net 468 "/DDR Banks/M1_DQ3" "M1_DQ3" + U3 C9 + U1 M22 +Net 469 "/DDR Banks/M1_DQ4" "M1_DQ4" + U3 C7 + U1 J20 +Net 470 "/DDR Banks/M1_DQ5" "M1_DQ5" + U3 D9 + U1 J22 +Net 471 "/DDR Banks/M1_DQ6" "M1_DQ6" + U3 D7 + U1 K21 +Net 472 "/DDR Banks/M1_DQ7" "M1_DQ7" + U3 E9 + U1 K22 +Net 473 "/DDR Banks/M1_DQ8" "M1_DQ8" + U3 E1 + U1 P21 +Net 474 "/DDR Banks/M1_DQ9" "M1_DQ9" + U3 D3 + U1 P22 +Net 475 "/DDR Banks/M1_DQ10" "M1_DQ10" + U3 D1 + U1 R20 +Net 476 "/DDR Banks/M1_DQ11" "M1_DQ11" + U3 C3 + U1 R22 +Net 477 "/DDR Banks/M1_DQ12" "M1_DQ12" + U3 C1 + U1 U20 +Net 478 "/DDR Banks/M1_DQ13" "M1_DQ13" + U3 B3 + U1 U22 +Net 479 "/DDR Banks/M1_DQ14" "M1_DQ14" + U3 B1 + U1 V21 +Net 480 "/DDR Banks/M1_DQ15" "M1_DQ15" + U3 A2 + U1 V22 +} +#End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index ee5dae0..af4c7ae 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,43 +1,6 @@ -update=Sat 07 Aug 2010 12:36:31 PM COT +update=Mon 09 Aug 2010 03:20:50 PM COT version=1 -last_client=cvpcb -[pcbnew] -version=1 -PadDrlX=320 -PadDimH=600 -PadDimV=600 -BoardThickness=630 -SgPcb45=1 -TxtPcbV=800 -TxtPcbH=600 -TxtModV=600 -TxtModH=600 -TxtModW=120 -VEgarde=100 -DrawLar=150 -EdgeLar=150 -TxtLar=120 -MSegLar=150 -LastNetListRead=xue-rnc.net -[pcbnew/libraries] -LibDir= -LibName1=../modules/SD-48025 -LibName2=sockets -LibName3=connect -LibName4=discret -LibName5=pin_array -LibName6=divers -LibName7=libcms -LibName8=display -LibName9=valves -LibName10=led -LibName11=dip_sockets -LibName12=../modules/90vfbga_mobile_ddr -LibName13=../modules/FGG484bga-p10 -LibName14=../modules/LQFP48 -LibName15=../modules/48TSOP-NAND -LibName16=../modules/micro-sd -LibName17=../modules/60fbga_ddr +last_client=pcbnew [eeschema] version=1 LibDir= @@ -113,10 +76,70 @@ LibName37=valves version=1 RootSch= BoardNm= +[common] +NetDir= [cvpcb] version=1 NetIExt=net [cvpcb/libraries] EquName1=devcms -[common] -NetDir= +[pcbnew] +version=1 +PadDrlX=320 +PadDimH=600 +PadDimV=600 +ViaDiam=350 +ViaDril=250 +ViaAltD=250 +MViaDia=200 +MViaDrl=50 +Isol=100 +Countlayer=4 +Lpiste=80 +RouteTo=15 +RouteBo=0 +TypeVia=3 +Segm45=1 +Racc45=1 +SgPcb45=1 +TxtPcbV=800 +TxtPcbH=600 +TxtModV=600 +TxtModH=600 +TxtModW=120 +HPGLnum=1 +HPGdiam=15 +HPGLSpd=20 +HPGLrec=2 +HPGLorg=0 +VEgarde=100 +DrawLar=150 +EdgeLar=150 +TxtLar=120 +MSegLar=150 +WpenSer=10 +[pcbnew/libraries] +LibDir= +LibName1=/home/juan64bits/emQbit/xue/kicad/modules/stdpass +LibName2=../modules/SD-48025 +LibName3=/home/juan64bits/emQbit/xue/kicad/modules/USB-48204 +LibName4=/home/juan64bits/emQbit/xue/kicad/modules/TSSOP-14 +LibName5=/home/juan64bits/emQbit/xue/kicad/modules/SMB-0402 +LibName6=/home/juan64bits/emQbit/xue/kicad/modules/SD-48025 +LibName7=/home/juan64bits/emQbit/xue/kicad/modules/MICROSD-500901 +LibName8=sockets +LibName9=connect +LibName10=discret +LibName11=pin_array +LibName12=divers +LibName13=libcms +LibName14=display +LibName15=valves +LibName16=led +LibName17=dip_sockets +LibName18=../modules/90vfbga_mobile_ddr +LibName19=../modules/FGG484bga-p10 +LibName20=../modules/LQFP48 +LibName21=../modules/48TSOP-NAND +LibName22=../modules/micro-sd +LibName23=../modules/60fbga_ddr diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index a993df3..bd8a03f 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,42 +1,5 @@ -EESchema Schematic File Version 2 date Sun 08 Aug 2010 10:51:44 PM COT -LIBS:power -LIBS:rj45-48025 -LIBS:xue-nv -LIBS:xc6slx75fgg484 -LIBS:xc6slx45fgg484 -LIBS:micron_mobile_ddr -LIBS:micron_ddr_512Mb -LIBS:k8001 -LIBS:device -LIBS:transistors -LIBS:conn -LIBS:linear -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:special -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:valves -LIBS:xue-rnc-cache +EESchema Schematic File Version 2 date Mon 09 Aug 2010 03:34:05 PM COT +LIBS:power,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./xue-rnc.cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 @@ -50,6 +13,26 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Wire Line + 10650 5400 9300 5400 +Wire Wire Line + 10650 5200 9300 5200 +Wire Wire Line + 10650 5000 9300 5000 +Wire Wire Line + 9300 7800 10600 7800 +Wire Wire Line + 9300 7600 10600 7600 +Wire Wire Line + 9300 7400 10600 7400 +Wire Wire Line + 9300 7200 10600 7200 +Wire Wire Line + 10600 6900 9300 6900 +Wire Wire Line + 9300 6700 10600 6700 +Wire Wire Line + 9300 6500 10600 6500 Wire Bus Line 4700 3150 5950 3150 Wire Wire Line @@ -78,8 +61,6 @@ Wire Wire Line 5950 4100 4700 4100 Wire Wire Line 4700 6150 5950 6150 -Wire Wire Line - 9750 6350 9300 6350 Wire Bus Line 5950 5100 5950 5050 Wire Bus Line @@ -110,33 +91,62 @@ Wire Wire Line 4700 3350 5950 3350 Wire Bus Line 4700 2950 5950 2950 -$Sheet -S 10650 4900 1150 1100 -U 4C5F1EDC -F0 "USB" 60 -F1 "USB.sch" 60 -$EndSheet -$Sheet -S 9750 6250 1450 2200 -U 4C4320F3 -F0 "Ethernet Phy" 60 -F1 "eth_phy.sch" 60 -F2 "ETH_RXC" O L 9750 6500 60 -F3 "ETH_RST_N" I L 9750 6600 60 -F4 "ETH_CRS" O L 9750 6700 60 -F5 "ETH_COL" O L 9750 6800 60 -F6 "ETH_INT" O L 9750 6350 60 -F7 "ETH_MDIO" B L 9750 6900 60 -F8 "ETH_MDC" I L 9750 7000 60 -F9 "ETH_RXD[0..3]" O L 9750 7200 60 -F10 "ETH_RXDV" O L 9750 7300 60 -F11 "ETH_RXER" O L 9750 7400 60 -F12 "ETH_TXC" B L 9750 7500 60 -F13 "ETH_TXD[0..3]" I L 9750 7600 60 -F14 "ETH_TXEN" I L 9750 7700 60 -F15 "ETH_TXER" I L 9750 7800 60 -F16 "ETH_CLK" I L 9750 7900 60 -$EndSheet +Wire Wire Line + 9300 6350 10600 6350 +Wire Wire Line + 9300 6600 10600 6600 +Wire Wire Line + 9300 6800 10600 6800 +Wire Wire Line + 9300 7000 10600 7000 +Wire Wire Line + 9300 7300 10600 7300 +Wire Wire Line + 9300 7500 10600 7500 +Wire Wire Line + 9300 7700 10600 7700 +Wire Wire Line + 9300 7900 10600 7900 +Wire Wire Line + 10650 5100 9300 5100 +Wire Wire Line + 10650 5300 9300 5300 +Text HLabel 9300 5400 0 60 BiDi ~ 0 +USBA_VM +Text HLabel 9300 5300 0 60 BiDi ~ 0 +USBA_VP +Text HLabel 9300 5200 0 60 BiDi ~ 0 +USBA_RCV +Text HLabel 9300 5100 0 60 BiDi ~ 0 +USBA_OE_N +Text HLabel 9300 5000 0 60 BiDi ~ 0 +USBA_SPD +Text HLabel 9300 6900 0 60 BiDi ~ 0 +ETH_MDIO +Text HLabel 9300 7500 0 60 BiDi ~ 0 +ETH_TXC +Text HLabel 9300 7900 0 60 Input ~ 0 +ETH_CLK +Text HLabel 9300 7800 0 60 Input ~ 0 +ETH_TXER +Text HLabel 9300 7700 0 60 Input ~ 0 +ETH_TXEN +Text HLabel 9300 7600 0 60 Input ~ 0 +ETH_TXD[0..3] +Text HLabel 9300 7000 0 60 Input ~ 0 +ETH_MDC +Text HLabel 9300 6600 0 60 Input ~ 0 +ETH_RESET_N +Text HLabel 9300 7400 0 60 Output ~ 0 +ETH_RXER +Text HLabel 9300 7300 0 60 Output ~ 0 +ETH_RXDV +Text HLabel 9300 7200 0 60 Output ~ 0 +ETH_RXD[0..3] +Text HLabel 9300 6800 0 60 Output ~ 0 +ETH_COL +Text HLabel 9300 6700 0 60 Output ~ 0 +ETH_CRS $Sheet S 5950 2700 3350 5800 U 4C431A63 @@ -170,6 +180,45 @@ F26 "M1_LDM" O L 5950 3750 60 F27 "M1_UDQS" O L 5950 3350 60 F28 "M1_DQ[0..15]" B L 5950 2950 60 $EndSheet +Text HLabel 9300 6500 0 60 Output ~ 0 +ETH_RXC +Text HLabel 10650 5400 2 60 BiDi ~ 0 +USBA_VM +Text HLabel 10650 5300 2 60 BiDi ~ 0 +USBA_VP +Text HLabel 10650 5200 2 60 BiDi ~ 0 +USBA_RCV +Text HLabel 10650 5100 2 60 BiDi ~ 0 +USBA_OE_N +Text HLabel 10650 5000 2 60 BiDi ~ 0 +USBA_SPD +$Sheet +S 10650 4900 1150 650 +U 4C5F1EDC +F0 "USB" 60 +F1 "USB.sch" 60 +$EndSheet +$Sheet +S 10600 6250 1300 1800 +U 4C4320F3 +F0 "Ethernet Phy" 60 +F1 "eth_phy.sch" 60 +F2 "ETH_RXC" O L 10600 6500 60 +F3 "ETH_RST_N" I L 10600 6600 60 +F4 "ETH_CRS" O L 10600 6700 60 +F5 "ETH_COL" O L 10600 6800 60 +F6 "ETH_INT" O L 10600 6350 60 +F7 "ETH_MDIO" B L 10600 6900 60 +F8 "ETH_MDC" I L 10600 7000 60 +F9 "ETH_RXD[0..3]" O L 10600 7200 60 +F10 "ETH_RXDV" O L 10600 7300 60 +F11 "ETH_RXER" O L 10600 7400 60 +F12 "ETH_TXC" B L 10600 7500 60 +F13 "ETH_TXD[0..3]" I L 10600 7600 60 +F14 "ETH_TXEN" I L 10600 7700 60 +F15 "ETH_TXER" I L 10600 7800 60 +F16 "ETH_CLK" I L 10600 7900 60 +$EndSheet $Sheet S 10650 2700 1150 1850 U 4C4227FE