diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib
index a351a89..25f00cc 100644
--- a/kicad/xue-rnc/xue-rnc-cache.lib
+++ b/kicad/xue-rnc/xue-rnc-cache.lib
@@ -1,4 +1,4 @@
-EESchema-LIBRARY Version 2.3  Date: Wed 04 Aug 2010 12:20:40 PM COT
+EESchema-LIBRARY Version 2.3  Date: Sun 08 Aug 2010 09:24:40 PM COT
 #
 # GND
 #
diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd
index f5d91ff..063085e 100644
--- a/kicad/xue-rnc/xue-rnc.brd
+++ b/kicad/xue-rnc/xue-rnc.brd
@@ -1,4 +1,4 @@
-PCBNEW-BOARD Version 1 date Wed 04 Aug 2010 12:21:45 PM COT
+PCBNEW-BOARD Version 1 date Sun 08 Aug 2010 09:46:38 AM COT
 
 # Created by Pcbnew(2010-07-15 BZR 2414)-unstable
 
@@ -6,21 +6,21 @@ $GENERAL
 LayerCount 4
 Ly 1FFF8007
 EnabledLayers 1FFF8007
-Links 225
-NoConn 225
+Links 233
+NoConn 233
 Di 28232 5405 47187 31125
 Ndraw 0
 Ntrack 0
 Nzone 0
 BoardThickness 630
 Nmodule 6
-Nnets 61
+Nnets 69
 $EndGENERAL
 
 $SHEETDESCR
 Sheet A4 11700 8267
 Title ""
-Date "4 aug 2010"
+Date "8 aug 2010"
 Rev ""
 Comp ""
 Comment1 ""
@@ -68,95 +68,95 @@ Na 0 ""
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 1 "/DDR_Banks/M0_A1"
+Na 1 "/DDR_Banks/M0_A11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 2 "/DDR_Banks/M0_A8"
+Na 2 "/DDR_Banks/M0_A2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 3 "/DDR_Banks/M0_CLK#"
+Na 3 "/DDR_Banks/M0_A6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 4 "/DDR_Banks/M0_DQ1"
+Na 4 "/DDR_Banks/M0_A9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 5 "/DDR_Banks/M0_DQ2"
+Na 5 "/DDR_Banks/M0_BA0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 6 "/DDR_Banks/M0_DQ4"
+Na 6 "/DDR_Banks/M0_BA1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 7 "/DDR_Banks/M1_A0"
+Na 7 "/DDR_Banks/M0_CAS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 8 "/DDR_Banks/M1_A1"
+Na 8 "/DDR_Banks/M0_DQ1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 9 "/DDR_Banks/M1_A12"
+Na 9 "/DDR_Banks/M0_DQ12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 10 "/DDR_Banks/M1_A3"
+Na 10 "/DDR_Banks/M0_DQ4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 11 "/DDR_Banks/M1_A6"
+Na 11 "/DDR_Banks/M0_DQ7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 12 "/DDR_Banks/M1_A9"
+Na 12 "/DDR_Banks/M0_DQ8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 13 "/DDR_Banks/M1_CLK"
+Na 13 "/DDR_Banks/M0_LDM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 14 "/Ethernet_Phy/ETH_INT"
+Na 14 "/DDR_Banks/M0_UDQS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 15 "/FPGA_Spartan6/M0_A0"
+Na 15 "/DDR_Banks/M0_WE#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 16 "/FPGA_Spartan6/M0_A10"
+Na 16 "/Ethernet_Phy/ETH_INT"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 17 "/FPGA_Spartan6/M0_A11"
+Na 17 "/FPGA_Spartan6/M0_A0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 18 "/FPGA_Spartan6/M0_A12"
+Na 18 "/FPGA_Spartan6/M0_A1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 19 "/FPGA_Spartan6/M0_A2"
+Na 19 "/FPGA_Spartan6/M0_A10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 20 "/FPGA_Spartan6/M0_A3"
+Na 20 "/FPGA_Spartan6/M0_A12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 21 "/FPGA_Spartan6/M0_A4"
+Na 21 "/FPGA_Spartan6/M0_A3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 22 "/FPGA_Spartan6/M0_A5"
+Na 22 "/FPGA_Spartan6/M0_A4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 23 "/FPGA_Spartan6/M0_A6"
+Na 23 "/FPGA_Spartan6/M0_A5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -164,59 +164,59 @@ Na 24 "/FPGA_Spartan6/M0_A7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 25 "/FPGA_Spartan6/M0_A9"
+Na 25 "/FPGA_Spartan6/M0_A8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 26 "/FPGA_Spartan6/M0_CLK"
+Na 26 "/FPGA_Spartan6/M0_CKE"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 27 "/FPGA_Spartan6/M0_DQ0"
+Na 27 "/FPGA_Spartan6/M0_CLK"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 28 "/FPGA_Spartan6/M0_DQ10"
+Na 28 "/FPGA_Spartan6/M0_CLK#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 29 "/FPGA_Spartan6/M0_DQ11"
+Na 29 "/FPGA_Spartan6/M0_DQ0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 30 "/FPGA_Spartan6/M0_DQ12"
+Na 30 "/FPGA_Spartan6/M0_DQ10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 31 "/FPGA_Spartan6/M0_DQ13"
+Na 31 "/FPGA_Spartan6/M0_DQ11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 32 "/FPGA_Spartan6/M0_DQ14"
+Na 32 "/FPGA_Spartan6/M0_DQ13"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 33 "/FPGA_Spartan6/M0_DQ15"
+Na 33 "/FPGA_Spartan6/M0_DQ14"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 34 "/FPGA_Spartan6/M0_DQ3"
+Na 34 "/FPGA_Spartan6/M0_DQ15"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 35 "/FPGA_Spartan6/M0_DQ5"
+Na 35 "/FPGA_Spartan6/M0_DQ2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 36 "/FPGA_Spartan6/M0_DQ6"
+Na 36 "/FPGA_Spartan6/M0_DQ3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 37 "/FPGA_Spartan6/M0_DQ7"
+Na 37 "/FPGA_Spartan6/M0_DQ5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 38 "/FPGA_Spartan6/M0_DQ8"
+Na 38 "/FPGA_Spartan6/M0_DQ6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
@@ -224,87 +224,119 @@ Na 39 "/FPGA_Spartan6/M0_DQ9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 40 "/FPGA_Spartan6/M1_A10"
+Na 40 "/FPGA_Spartan6/M0_LDQS"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 41 "/FPGA_Spartan6/M1_A11"
+Na 41 "/FPGA_Spartan6/M0_RAS#"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 42 "/FPGA_Spartan6/M1_A2"
+Na 42 "/FPGA_Spartan6/M0_UDM"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 43 "/FPGA_Spartan6/M1_A4"
+Na 43 "/FPGA_Spartan6/M1_A0"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 44 "/FPGA_Spartan6/M1_A5"
+Na 44 "/FPGA_Spartan6/M1_A1"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 45 "/FPGA_Spartan6/M1_A7"
+Na 45 "/FPGA_Spartan6/M1_A10"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 46 "/FPGA_Spartan6/M1_A8"
+Na 46 "/FPGA_Spartan6/M1_A11"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 47 "/FPGA_Spartan6/M1_CLK#"
+Na 47 "/FPGA_Spartan6/M1_A12"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 48 "/Non_volatile_memories/FRB_N"
+Na 48 "/FPGA_Spartan6/M1_A2"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 49 "3.3V"
+Na 49 "/FPGA_Spartan6/M1_A3"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 50 "GND"
+Na 50 "/FPGA_Spartan6/M1_A4"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 51 "N-000036"
+Na 51 "/FPGA_Spartan6/M1_A5"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 52 "N-000040"
+Na 52 "/FPGA_Spartan6/M1_A6"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 53 "N-000130"
+Na 53 "/FPGA_Spartan6/M1_A7"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 54 "N-000138"
+Na 54 "/FPGA_Spartan6/M1_A8"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 55 "N-000169"
+Na 55 "/FPGA_Spartan6/M1_A9"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 56 "N-000170"
+Na 56 "/Non_volatile_memories/FRB_N"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 57 "N-000171"
+Na 57 "3.3V"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 58 "N-000172"
+Na 58 "GND"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 59 "N-000411"
+Na 59 "N-000036"
 St ~
 $EndEQUIPOT
 $EQUIPOT
-Na 60 "N-000412"
+Na 60 "N-000039"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 61 "N-000106"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 62 "N-000200"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 63 "N-000201"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 64 "N-000212"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 65 "N-000213"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 66 "N-000214"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 67 "N-000403"
+St ~
+$EndEQUIPOT
+$EQUIPOT
+Na 68 "N-000404"
 St ~
 $EndEQUIPOT
 $NCLASS
@@ -317,66 +349,74 @@ ViaDrill 250
 uViaDia 200
 uViaDrill 50
 AddNet ""
-AddNet "/DDR_Banks/M0_A1"
-AddNet "/DDR_Banks/M0_A8"
-AddNet "/DDR_Banks/M0_CLK#"
+AddNet "/DDR_Banks/M0_A11"
+AddNet "/DDR_Banks/M0_A2"
+AddNet "/DDR_Banks/M0_A6"
+AddNet "/DDR_Banks/M0_A9"
+AddNet "/DDR_Banks/M0_BA0"
+AddNet "/DDR_Banks/M0_BA1"
+AddNet "/DDR_Banks/M0_CAS#"
 AddNet "/DDR_Banks/M0_DQ1"
-AddNet "/DDR_Banks/M0_DQ2"
+AddNet "/DDR_Banks/M0_DQ12"
 AddNet "/DDR_Banks/M0_DQ4"
-AddNet "/DDR_Banks/M1_A0"
-AddNet "/DDR_Banks/M1_A1"
-AddNet "/DDR_Banks/M1_A12"
-AddNet "/DDR_Banks/M1_A3"
-AddNet "/DDR_Banks/M1_A6"
-AddNet "/DDR_Banks/M1_A9"
-AddNet "/DDR_Banks/M1_CLK"
+AddNet "/DDR_Banks/M0_DQ7"
+AddNet "/DDR_Banks/M0_DQ8"
+AddNet "/DDR_Banks/M0_LDM"
+AddNet "/DDR_Banks/M0_UDQS"
+AddNet "/DDR_Banks/M0_WE#"
 AddNet "/Ethernet_Phy/ETH_INT"
 AddNet "/FPGA_Spartan6/M0_A0"
+AddNet "/FPGA_Spartan6/M0_A1"
 AddNet "/FPGA_Spartan6/M0_A10"
-AddNet "/FPGA_Spartan6/M0_A11"
 AddNet "/FPGA_Spartan6/M0_A12"
-AddNet "/FPGA_Spartan6/M0_A2"
 AddNet "/FPGA_Spartan6/M0_A3"
 AddNet "/FPGA_Spartan6/M0_A4"
 AddNet "/FPGA_Spartan6/M0_A5"
-AddNet "/FPGA_Spartan6/M0_A6"
 AddNet "/FPGA_Spartan6/M0_A7"
-AddNet "/FPGA_Spartan6/M0_A9"
+AddNet "/FPGA_Spartan6/M0_A8"
+AddNet "/FPGA_Spartan6/M0_CKE"
 AddNet "/FPGA_Spartan6/M0_CLK"
+AddNet "/FPGA_Spartan6/M0_CLK#"
 AddNet "/FPGA_Spartan6/M0_DQ0"
 AddNet "/FPGA_Spartan6/M0_DQ10"
 AddNet "/FPGA_Spartan6/M0_DQ11"
-AddNet "/FPGA_Spartan6/M0_DQ12"
 AddNet "/FPGA_Spartan6/M0_DQ13"
 AddNet "/FPGA_Spartan6/M0_DQ14"
 AddNet "/FPGA_Spartan6/M0_DQ15"
+AddNet "/FPGA_Spartan6/M0_DQ2"
 AddNet "/FPGA_Spartan6/M0_DQ3"
 AddNet "/FPGA_Spartan6/M0_DQ5"
 AddNet "/FPGA_Spartan6/M0_DQ6"
-AddNet "/FPGA_Spartan6/M0_DQ7"
-AddNet "/FPGA_Spartan6/M0_DQ8"
 AddNet "/FPGA_Spartan6/M0_DQ9"
+AddNet "/FPGA_Spartan6/M0_LDQS"
+AddNet "/FPGA_Spartan6/M0_RAS#"
+AddNet "/FPGA_Spartan6/M0_UDM"
+AddNet "/FPGA_Spartan6/M1_A0"
+AddNet "/FPGA_Spartan6/M1_A1"
 AddNet "/FPGA_Spartan6/M1_A10"
 AddNet "/FPGA_Spartan6/M1_A11"
+AddNet "/FPGA_Spartan6/M1_A12"
 AddNet "/FPGA_Spartan6/M1_A2"
+AddNet "/FPGA_Spartan6/M1_A3"
 AddNet "/FPGA_Spartan6/M1_A4"
 AddNet "/FPGA_Spartan6/M1_A5"
+AddNet "/FPGA_Spartan6/M1_A6"
 AddNet "/FPGA_Spartan6/M1_A7"
 AddNet "/FPGA_Spartan6/M1_A8"
-AddNet "/FPGA_Spartan6/M1_CLK#"
+AddNet "/FPGA_Spartan6/M1_A9"
 AddNet "/Non_volatile_memories/FRB_N"
 AddNet "3.3V"
 AddNet "GND"
 AddNet "N-000036"
-AddNet "N-000040"
-AddNet "N-000130"
-AddNet "N-000138"
-AddNet "N-000169"
-AddNet "N-000170"
-AddNet "N-000171"
-AddNet "N-000172"
-AddNet "N-000411"
-AddNet "N-000412"
+AddNet "N-000039"
+AddNet "N-000106"
+AddNet "N-000200"
+AddNet "N-000201"
+AddNet "N-000212"
+AddNet "N-000213"
+AddNet "N-000214"
+AddNet "N-000403"
+AddNet "N-000404"
 $EndNCLASS
 $MODULE FGG484bga-p10
 Po 38000 14500 0 15 4C4325AE 4C4328D9 ~~
@@ -399,7 +439,7 @@ $PAD
 Sh "A1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -4133 -4133
 $EndPAD
 $PAD
@@ -427,7 +467,7 @@ $PAD
 Sh "A5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 14 "/Ethernet_Phy/ETH_INT"
+Ne 16 "/Ethernet_Phy/ETH_INT"
 Po -2558 -4133
 $EndPAD
 $PAD
@@ -546,7 +586,7 @@ $PAD
 Sh "A22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 4133 -4133
 $EndPAD
 $PAD
@@ -574,14 +614,14 @@ $PAD
 Sh "B4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "N-000138"
+Ne 66 "N-000214"
 Po -2952 -3739
 $EndPAD
 $PAD
 Sh "B5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -2558 -3739
 $EndPAD
 $PAD
@@ -595,7 +635,7 @@ $PAD
 Sh "B7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "N-000138"
+Ne 66 "N-000214"
 Po -1771 -3739
 $EndPAD
 $PAD
@@ -609,7 +649,7 @@ $PAD
 Sh "B9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -983 -3739
 $EndPAD
 $PAD
@@ -623,7 +663,7 @@ $PAD
 Sh "B11" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "N-000138"
+Ne 66 "N-000214"
 Po -196 -3739
 $EndPAD
 $PAD
@@ -637,7 +677,7 @@ $PAD
 Sh "B13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 590 -3739
 $EndPAD
 $PAD
@@ -651,7 +691,7 @@ $PAD
 Sh "B15" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "N-000138"
+Ne 66 "N-000214"
 Po 1377 -3739
 $EndPAD
 $PAD
@@ -665,7 +705,7 @@ $PAD
 Sh "B17" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 2165 -3739
 $EndPAD
 $PAD
@@ -679,7 +719,7 @@ $PAD
 Sh "B19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "N-000138"
+Ne 66 "N-000214"
 Po 2952 -3739
 $EndPAD
 $PAD
@@ -707,14 +747,14 @@ $PAD
 Sh "C1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 17 "/FPGA_Spartan6/M0_A11"
+Ne 1 "/DDR_Banks/M0_A11"
 Po -4133 -3346
 $EndPAD
 $PAD
 Sh "C2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -3739 -3346
 $EndPAD
 $PAD
@@ -840,35 +880,35 @@ $PAD
 Sh "C20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 46 "/FPGA_Spartan6/M1_A8"
+Ne 0 ""
 Po 3346 -3346
 $EndPAD
 $PAD
 Sh "C21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "N-000130"
+Ne 61 "N-000106"
 Po 3739 -3346
 $EndPAD
 $PAD
 Sh "C22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 12 "/DDR_Banks/M1_A9"
+Ne 0 ""
 Po 4133 -3346
 $EndPAD
 $PAD
 Sh "D1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 18 "/FPGA_Spartan6/M0_A12"
+Ne 20 "/FPGA_Spartan6/M0_A12"
 Po -4133 -2952
 $EndPAD
 $PAD
 Sh "D2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 26 "/FPGA_Spartan6/M0_CKE"
 Po -3739 -2952
 $EndPAD
 $PAD
@@ -882,7 +922,7 @@ $PAD
 Sh "D4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -2952 -2952
 $EndPAD
 $PAD
@@ -966,7 +1006,7 @@ $PAD
 Sh "D16" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po 1771 -2952
 $EndPAD
 $PAD
@@ -980,7 +1020,7 @@ $PAD
 Sh "D18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 2558 -2952
 $EndPAD
 $PAD
@@ -1008,28 +1048,28 @@ $PAD
 Sh "D22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 9 "/DDR_Banks/M1_A12"
+Ne 0 ""
 Po 4133 -2952
 $EndPAD
 $PAD
 Sh "E1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 25 "/FPGA_Spartan6/M0_A9"
+Ne 4 "/DDR_Banks/M0_A9"
 Po -4133 -2558
 $EndPAD
 $PAD
 Sh "E2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -3739 -2558
 $EndPAD
 $PAD
 Sh "E3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 2 "/DDR_Banks/M0_A8"
+Ne 25 "/FPGA_Spartan6/M0_A8"
 Po -3346 -2558
 $EndPAD
 $PAD
@@ -1057,7 +1097,7 @@ $PAD
 Sh "E7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -1771 -2558
 $EndPAD
 $PAD
@@ -1071,7 +1111,7 @@ $PAD
 Sh "E9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "N-000138"
+Ne 66 "N-000214"
 Po -983 -2558
 $EndPAD
 $PAD
@@ -1085,7 +1125,7 @@ $PAD
 Sh "E11" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -196 -2558
 $EndPAD
 $PAD
@@ -1099,7 +1139,7 @@ $PAD
 Sh "E13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "N-000138"
+Ne 66 "N-000214"
 Po 590 -2558
 $EndPAD
 $PAD
@@ -1113,7 +1153,7 @@ $PAD
 Sh "E15" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 1377 -2558
 $EndPAD
 $PAD
@@ -1127,7 +1167,7 @@ $PAD
 Sh "E17" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "N-000138"
+Ne 66 "N-000214"
 Po 2165 -2558
 $EndPAD
 $PAD
@@ -1141,28 +1181,28 @@ $PAD
 Sh "E19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "N-000130"
+Ne 61 "N-000106"
 Po 2952 -2558
 $EndPAD
 $PAD
 Sh "E20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 45 "/FPGA_Spartan6/M1_A7"
+Ne 0 ""
 Po 3346 -2558
 $EndPAD
 $PAD
 Sh "E21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 3739 -2558
 $EndPAD
 $PAD
 Sh "E22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 42 "/FPGA_Spartan6/M1_A2"
+Ne 0 ""
 Po 4133 -2558
 $EndPAD
 $PAD
@@ -1176,21 +1216,21 @@ $PAD
 Sh "F2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 15 "/DDR_Banks/M0_WE#"
 Po -3739 -2165
 $EndPAD
 $PAD
 Sh "F3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 21 "/FPGA_Spartan6/M0_A4"
+Ne 22 "/FPGA_Spartan6/M0_A4"
 Po -3346 -2165
 $EndPAD
 $PAD
 Sh "F4" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -2952 -2165
 $EndPAD
 $PAD
@@ -1204,7 +1244,7 @@ $PAD
 Sh "F6" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -2165 -2165
 $EndPAD
 $PAD
@@ -1239,7 +1279,7 @@ $PAD
 Sh "F11" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po -196 -2165
 $EndPAD
 $PAD
@@ -1295,63 +1335,63 @@ $PAD
 Sh "F19" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 41 "/FPGA_Spartan6/M1_A11"
+Ne 0 ""
 Po 2952 -2165
 $EndPAD
 $PAD
 Sh "F20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 43 "/FPGA_Spartan6/M1_A4"
+Ne 0 ""
 Po 3346 -2165
 $EndPAD
 $PAD
 Sh "F21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 7 "/DDR_Banks/M1_A0"
+Ne 0 ""
 Po 3739 -2165
 $EndPAD
 $PAD
 Sh "F22" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 8 "/DDR_Banks/M1_A1"
+Ne 0 ""
 Po 4133 -2165
 $EndPAD
 $PAD
 Sh "G1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 6 "/DDR_Banks/M0_BA1"
 Po -4133 -1771
 $EndPAD
 $PAD
 Sh "G2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -3739 -1771
 $EndPAD
 $PAD
 Sh "G3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 5 "/DDR_Banks/M0_BA0"
 Po -3346 -1771
 $EndPAD
 $PAD
 Sh "G4" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 16 "/FPGA_Spartan6/M0_A10"
+Ne 19 "/FPGA_Spartan6/M0_A10"
 Po -2952 -1771
 $EndPAD
 $PAD
 Sh "G5" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -2558 -1771
 $EndPAD
 $PAD
@@ -1386,7 +1426,7 @@ $PAD
 Sh "G10" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "N-000138"
+Ne 66 "N-000214"
 Po -590 -1771
 $EndPAD
 $PAD
@@ -1400,7 +1440,7 @@ $PAD
 Sh "G12" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po 196 -1771
 $EndPAD
 $PAD
@@ -1414,7 +1454,7 @@ $PAD
 Sh "G14" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 54 "N-000138"
+Ne 66 "N-000214"
 Po 983 -1771
 $EndPAD
 $PAD
@@ -1442,28 +1482,28 @@ $PAD
 Sh "G18" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 2558 -1771
 $EndPAD
 $PAD
 Sh "G19" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 40 "/FPGA_Spartan6/M1_A10"
+Ne 0 ""
 Po 2952 -1771
 $EndPAD
 $PAD
 Sh "G20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 10 "/DDR_Banks/M1_A3"
+Ne 0 ""
 Po 3346 -1771
 $EndPAD
 $PAD
 Sh "G21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "N-000130"
+Ne 61 "N-000106"
 Po 3739 -1771
 $EndPAD
 $PAD
@@ -1477,35 +1517,35 @@ $PAD
 Sh "H1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 1 "/DDR_Banks/M0_A1"
+Ne 18 "/FPGA_Spartan6/M0_A1"
 Po -4133 -1377
 $EndPAD
 $PAD
 Sh "H2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 15 "/FPGA_Spartan6/M0_A0"
+Ne 17 "/FPGA_Spartan6/M0_A0"
 Po -3739 -1377
 $EndPAD
 $PAD
 Sh "H3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 3 "/DDR_Banks/M0_CLK#"
+Ne 28 "/FPGA_Spartan6/M0_CLK#"
 Po -3346 -1377
 $EndPAD
 $PAD
 Sh "H4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 26 "/FPGA_Spartan6/M0_CLK"
+Ne 27 "/FPGA_Spartan6/M0_CLK"
 Po -2952 -1377
 $EndPAD
 $PAD
 Sh "H5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 19 "/FPGA_Spartan6/M0_A2"
+Ne 2 "/DDR_Banks/M0_A2"
 Po -2558 -1377
 $EndPAD
 $PAD
@@ -1519,7 +1559,7 @@ $PAD
 Sh "H7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -1771 -1377
 $EndPAD
 $PAD
@@ -1533,7 +1573,7 @@ $PAD
 Sh "H9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po -983 -1377
 $EndPAD
 $PAD
@@ -1575,7 +1615,7 @@ $PAD
 Sh "H15" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po 1377 -1377
 $EndPAD
 $PAD
@@ -1610,7 +1650,7 @@ $PAD
 Sh "H20" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 13 "/DDR_Banks/M1_CLK"
+Ne 0 ""
 Po 3346 -1377
 $EndPAD
 $PAD
@@ -1631,35 +1671,35 @@ $PAD
 Sh "J1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 35 "/FPGA_Spartan6/M0_DQ5"
+Ne 37 "/FPGA_Spartan6/M0_DQ5"
 Po -4133 -983
 $EndPAD
 $PAD
 Sh "J2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -3739 -983
 $EndPAD
 $PAD
 Sh "J3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 6 "/DDR_Banks/M0_DQ4"
+Ne 10 "/DDR_Banks/M0_DQ4"
 Po -3346 -983
 $EndPAD
 $PAD
 Sh "J4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 23 "/FPGA_Spartan6/M0_A6"
+Ne 3 "/DDR_Banks/M0_A6"
 Po -2952 -983
 $EndPAD
 $PAD
 Sh "J5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -2558 -983
 $EndPAD
 $PAD
@@ -1680,56 +1720,56 @@ $PAD
 Sh "J8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po -1377 -983
 $EndPAD
 $PAD
 Sh "J9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -983 -983
 $EndPAD
 $PAD
 Sh "J10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po -590 -983
 $EndPAD
 $PAD
 Sh "J11" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -196 -983
 $EndPAD
 $PAD
 Sh "J12" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po 196 -983
 $EndPAD
 $PAD
 Sh "J13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 590 -983
 $EndPAD
 $PAD
 Sh "J14" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po 983 -983
 $EndPAD
 $PAD
 Sh "J15" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 1377 -983
 $EndPAD
 $PAD
@@ -1750,14 +1790,14 @@ $PAD
 Sh "J18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "N-000130"
+Ne 61 "N-000106"
 Po 2558 -983
 $EndPAD
 $PAD
 Sh "J19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 47 "/FPGA_Spartan6/M1_CLK#"
+Ne 0 ""
 Po 2952 -983
 $EndPAD
 $PAD
@@ -1771,7 +1811,7 @@ $PAD
 Sh "J21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 3739 -983
 $EndPAD
 $PAD
@@ -1785,42 +1825,42 @@ $PAD
 Sh "K1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 37 "/FPGA_Spartan6/M0_DQ7"
+Ne 11 "/DDR_Banks/M0_DQ7"
 Po -4133 -590
 $EndPAD
 $PAD
 Sh "K2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 36 "/FPGA_Spartan6/M0_DQ6"
+Ne 38 "/FPGA_Spartan6/M0_DQ6"
 Po -3739 -590
 $EndPAD
 $PAD
 Sh "K3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 22 "/FPGA_Spartan6/M0_A5"
+Ne 23 "/FPGA_Spartan6/M0_A5"
 Po -3346 -590
 $EndPAD
 $PAD
 Sh "K4" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 7 "/DDR_Banks/M0_CAS#"
 Po -2952 -590
 $EndPAD
 $PAD
 Sh "K5" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 41 "/FPGA_Spartan6/M0_RAS#"
 Po -2558 -590
 $EndPAD
 $PAD
 Sh "K6" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 20 "/FPGA_Spartan6/M0_A3"
+Ne 21 "/FPGA_Spartan6/M0_A3"
 Po -2165 -590
 $EndPAD
 $PAD
@@ -1841,49 +1881,49 @@ $PAD
 Sh "K9" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po -983 -590
 $EndPAD
 $PAD
 Sh "K10" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -590 -590
 $EndPAD
 $PAD
 Sh "K11" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po -196 -590
 $EndPAD
 $PAD
 Sh "K12" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 196 -590
 $EndPAD
 $PAD
 Sh "K13" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po 590 -590
 $EndPAD
 $PAD
 Sh "K14" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 983 -590
 $EndPAD
 $PAD
 Sh "K15" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po 1377 -590
 $EndPAD
 $PAD
@@ -1911,14 +1951,14 @@ $PAD
 Sh "K19" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 11 "/DDR_Banks/M1_A6"
+Ne 0 ""
 Po 2952 -590
 $EndPAD
 $PAD
 Sh "K20" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 44 "/FPGA_Spartan6/M1_A5"
+Ne 0 ""
 Po 3346 -590
 $EndPAD
 $PAD
@@ -1946,28 +1986,28 @@ $PAD
 Sh "L2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -3739 -196
 $EndPAD
 $PAD
 Sh "L3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 40 "/FPGA_Spartan6/M0_LDQS"
 Po -3346 -196
 $EndPAD
 $PAD
 Sh "L4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 13 "/DDR_Banks/M0_LDM"
 Po -2952 -196
 $EndPAD
 $PAD
 Sh "L5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -2558 -196
 $EndPAD
 $PAD
@@ -1981,56 +2021,56 @@ $PAD
 Sh "L7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -1771 -196
 $EndPAD
 $PAD
 Sh "L8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po -1377 -196
 $EndPAD
 $PAD
 Sh "L9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -983 -196
 $EndPAD
 $PAD
 Sh "L10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po -590 -196
 $EndPAD
 $PAD
 Sh "L11" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -196 -196
 $EndPAD
 $PAD
 Sh "L12" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po 196 -196
 $EndPAD
 $PAD
 Sh "L13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 590 -196
 $EndPAD
 $PAD
 Sh "L14" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po 983 -196
 $EndPAD
 $PAD
@@ -2044,7 +2084,7 @@ $PAD
 Sh "L16" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "N-000130"
+Ne 61 "N-000106"
 Po 1771 -196
 $EndPAD
 $PAD
@@ -2058,7 +2098,7 @@ $PAD
 Sh "L18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 2558 -196
 $EndPAD
 $PAD
@@ -2079,7 +2119,7 @@ $PAD
 Sh "L21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "N-000130"
+Ne 61 "N-000106"
 Po 3739 -196
 $EndPAD
 $PAD
@@ -2093,21 +2133,21 @@ $PAD
 Sh "M1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 34 "/FPGA_Spartan6/M0_DQ3"
+Ne 36 "/FPGA_Spartan6/M0_DQ3"
 Po -4133 196
 $EndPAD
 $PAD
 Sh "M2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 5 "/DDR_Banks/M0_DQ2"
+Ne 35 "/FPGA_Spartan6/M0_DQ2"
 Po -3739 196
 $EndPAD
 $PAD
 Sh "M3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 42 "/FPGA_Spartan6/M0_UDM"
 Po -3346 196
 $EndPAD
 $PAD
@@ -2135,7 +2175,7 @@ $PAD
 Sh "M7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 43 "/FPGA_Spartan6/M1_A0"
 Po -1771 196
 $EndPAD
 $PAD
@@ -2149,49 +2189,49 @@ $PAD
 Sh "M9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po -983 196
 $EndPAD
 $PAD
 Sh "M10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -590 196
 $EndPAD
 $PAD
 Sh "M11" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po -196 196
 $EndPAD
 $PAD
 Sh "M12" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 196 196
 $EndPAD
 $PAD
 Sh "M13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po 590 196
 $EndPAD
 $PAD
 Sh "M14" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 983 196
 $EndPAD
 $PAD
 Sh "M15" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po 1377 196
 $EndPAD
 $PAD
@@ -2247,21 +2287,21 @@ $PAD
 Sh "N1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 4 "/DDR_Banks/M0_DQ1"
+Ne 8 "/DDR_Banks/M0_DQ1"
 Po -4133 590
 $EndPAD
 $PAD
 Sh "N2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -3739 590
 $EndPAD
 $PAD
 Sh "N3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 27 "/FPGA_Spartan6/M0_DQ0"
+Ne 29 "/FPGA_Spartan6/M0_DQ0"
 Po -3346 590
 $EndPAD
 $PAD
@@ -2275,70 +2315,70 @@ $PAD
 Sh "N5" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -2558 590
 $EndPAD
 $PAD
 Sh "N6" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 48 "/FPGA_Spartan6/M1_A2"
 Po -2165 590
 $EndPAD
 $PAD
 Sh "N7" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 44 "/FPGA_Spartan6/M1_A1"
 Po -1771 590
 $EndPAD
 $PAD
 Sh "N8" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po -1377 590
 $EndPAD
 $PAD
 Sh "N9" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -983 590
 $EndPAD
 $PAD
 Sh "N10" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po -590 590
 $EndPAD
 $PAD
 Sh "N11" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -196 590
 $EndPAD
 $PAD
 Sh "N12" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po 196 590
 $EndPAD
 $PAD
 Sh "N13" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 590 590
 $EndPAD
 $PAD
 Sh "N14" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po 983 590
 $EndPAD
 $PAD
@@ -2359,14 +2399,14 @@ $PAD
 Sh "N17" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 2165 590
 $EndPAD
 $PAD
 Sh "N18" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "N-000130"
+Ne 61 "N-000106"
 Po 2558 590
 $EndPAD
 $PAD
@@ -2387,7 +2427,7 @@ $PAD
 Sh "N21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 3739 590
 $EndPAD
 $PAD
@@ -2408,7 +2448,7 @@ $PAD
 Sh "P2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 38 "/FPGA_Spartan6/M0_DQ8"
+Ne 12 "/DDR_Banks/M0_DQ8"
 Po -3739 983
 $EndPAD
 $PAD
@@ -2429,70 +2469,70 @@ $PAD
 Sh "P5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 53 "/FPGA_Spartan6/M1_A7"
 Po -2558 983
 $EndPAD
 $PAD
 Sh "P6" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 54 "/FPGA_Spartan6/M1_A8"
 Po -2165 983
 $EndPAD
 $PAD
 Sh "P7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 55 "/FPGA_Spartan6/M1_A9"
 Po -1771 983
 $EndPAD
 $PAD
 Sh "P8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 45 "/FPGA_Spartan6/M1_A10"
 Po -1377 983
 $EndPAD
 $PAD
 Sh "P9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po -983 983
 $EndPAD
 $PAD
 Sh "P10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -590 983
 $EndPAD
 $PAD
 Sh "P11" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po -196 983
 $EndPAD
 $PAD
 Sh "P12" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 196 983
 $EndPAD
 $PAD
 Sh "P13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po 590 983
 $EndPAD
 $PAD
 Sh "P14" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 983 983
 $EndPAD
 $PAD
@@ -2555,21 +2595,21 @@ $PAD
 Sh "R1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 29 "/FPGA_Spartan6/M0_DQ11"
+Ne 31 "/FPGA_Spartan6/M0_DQ11"
 Po -4133 1377
 $EndPAD
 $PAD
 Sh "R2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -3739 1377
 $EndPAD
 $PAD
 Sh "R3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 28 "/FPGA_Spartan6/M0_DQ10"
+Ne 30 "/FPGA_Spartan6/M0_DQ10"
 Po -3346 1377
 $EndPAD
 $PAD
@@ -2583,14 +2623,14 @@ $PAD
 Sh "R5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -2558 1377
 $EndPAD
 $PAD
 Sh "R6" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po -2165 1377
 $EndPAD
 $PAD
@@ -2618,7 +2658,7 @@ $PAD
 Sh "R10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po -590 1377
 $EndPAD
 $PAD
@@ -2632,7 +2672,7 @@ $PAD
 Sh "R12" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po 196 1377
 $EndPAD
 $PAD
@@ -2646,7 +2686,7 @@ $PAD
 Sh "R14" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 57 "N-000171"
+Ne 63 "N-000201"
 Po 983 1377
 $EndPAD
 $PAD
@@ -2674,7 +2714,7 @@ $PAD
 Sh "R18" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 2558 1377
 $EndPAD
 $PAD
@@ -2695,7 +2735,7 @@ $PAD
 Sh "R21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "N-000130"
+Ne 61 "N-000106"
 Po 3739 1377
 $EndPAD
 $PAD
@@ -2716,21 +2756,21 @@ $PAD
 Sh "T2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 14 "/DDR_Banks/M0_UDQS"
 Po -3739 1771
 $EndPAD
 $PAD
 Sh "T3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 51 "/FPGA_Spartan6/M1_A5"
 Po -3346 1771
 $EndPAD
 $PAD
 Sh "T4" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 52 "/FPGA_Spartan6/M1_A6"
 Po -2952 1771
 $EndPAD
 $PAD
@@ -2765,7 +2805,7 @@ $PAD
 Sh "T9" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po -983 1771
 $EndPAD
 $PAD
@@ -2793,7 +2833,7 @@ $PAD
 Sh "T13" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po 590 1771
 $EndPAD
 $PAD
@@ -2863,35 +2903,35 @@ $PAD
 Sh "U1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 31 "/FPGA_Spartan6/M0_DQ13"
+Ne 32 "/FPGA_Spartan6/M0_DQ13"
 Po -4133 2165
 $EndPAD
 $PAD
 Sh "U2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -3739 2165
 $EndPAD
 $PAD
 Sh "U3" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 30 "/FPGA_Spartan6/M0_DQ12"
+Ne 9 "/DDR_Banks/M0_DQ12"
 Po -3346 2165
 $EndPAD
 $PAD
 Sh "U4" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 50 "/FPGA_Spartan6/M1_A4"
 Po -2952 2165
 $EndPAD
 $PAD
 Sh "U5" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -2558 2165
 $EndPAD
 $PAD
@@ -2905,7 +2945,7 @@ $PAD
 Sh "U7" O 158 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -1771 2165
 $EndPAD
 $PAD
@@ -2933,7 +2973,7 @@ $PAD
 Sh "U11" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po -196 2165
 $EndPAD
 $PAD
@@ -2982,7 +3022,7 @@ $PAD
 Sh "U18" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "N-000130"
+Ne 61 "N-000106"
 Po 2558 2165
 $EndPAD
 $PAD
@@ -3003,7 +3043,7 @@ $PAD
 Sh "U21" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 3739 2165
 $EndPAD
 $PAD
@@ -3017,28 +3057,28 @@ $PAD
 Sh "V1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 33 "/FPGA_Spartan6/M0_DQ15"
+Ne 34 "/FPGA_Spartan6/M0_DQ15"
 Po -4133 2558
 $EndPAD
 $PAD
 Sh "V2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 32 "/FPGA_Spartan6/M0_DQ14"
+Ne 33 "/FPGA_Spartan6/M0_DQ14"
 Po -3739 2558
 $EndPAD
 $PAD
 Sh "V3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 49 "/FPGA_Spartan6/M1_A3"
 Po -3346 2558
 $EndPAD
 $PAD
 Sh "V4" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -2952 2558
 $EndPAD
 $PAD
@@ -3052,7 +3092,7 @@ $PAD
 Sh "V6" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 58 "N-000172"
+Ne 62 "N-000200"
 Po -2165 2558
 $EndPAD
 $PAD
@@ -3066,7 +3106,7 @@ $PAD
 Sh "V8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po -1377 2558
 $EndPAD
 $PAD
@@ -3080,7 +3120,7 @@ $PAD
 Sh "V10" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -590 2558
 $EndPAD
 $PAD
@@ -3094,7 +3134,7 @@ $PAD
 Sh "V12" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po 196 2558
 $EndPAD
 $PAD
@@ -3108,7 +3148,7 @@ $PAD
 Sh "V14" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 983 2558
 $EndPAD
 $PAD
@@ -3122,7 +3162,7 @@ $PAD
 Sh "V16" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po 1771 2558
 $EndPAD
 $PAD
@@ -3171,21 +3211,21 @@ $PAD
 Sh "W1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 46 "/FPGA_Spartan6/M1_A11"
 Po -4133 2952
 $EndPAD
 $PAD
 Sh "W2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 56 "N-000170"
+Ne 64 "N-000212"
 Po -3739 2952
 $EndPAD
 $PAD
 Sh "W3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 47 "/FPGA_Spartan6/M1_A12"
 Po -3346 2952
 $EndPAD
 $PAD
@@ -3199,7 +3239,7 @@ $PAD
 Sh "W5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po -2558 2952
 $EndPAD
 $PAD
@@ -3213,7 +3253,7 @@ $PAD
 Sh "W7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -1771 2952
 $EndPAD
 $PAD
@@ -3276,7 +3316,7 @@ $PAD
 Sh "W16" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 1771 2952
 $EndPAD
 $PAD
@@ -3297,7 +3337,7 @@ $PAD
 Sh "W19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 2952 2952
 $EndPAD
 $PAD
@@ -3311,7 +3351,7 @@ $PAD
 Sh "W21" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 53 "N-000130"
+Ne 61 "N-000106"
 Po 3739 2952
 $EndPAD
 $PAD
@@ -3493,7 +3533,7 @@ $PAD
 Sh "AA3" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po -3346 3739
 $EndPAD
 $PAD
@@ -3507,7 +3547,7 @@ $PAD
 Sh "AA5" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -2558 3739
 $EndPAD
 $PAD
@@ -3521,7 +3561,7 @@ $PAD
 Sh "AA7" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po -1771 3739
 $EndPAD
 $PAD
@@ -3535,7 +3575,7 @@ $PAD
 Sh "AA9" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -983 3739
 $EndPAD
 $PAD
@@ -3549,7 +3589,7 @@ $PAD
 Sh "AA11" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po -196 3739
 $EndPAD
 $PAD
@@ -3563,7 +3603,7 @@ $PAD
 Sh "AA13" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 590 3739
 $EndPAD
 $PAD
@@ -3577,7 +3617,7 @@ $PAD
 Sh "AA15" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po 1377 3739
 $EndPAD
 $PAD
@@ -3591,7 +3631,7 @@ $PAD
 Sh "AA17" O 158 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 2165 3739
 $EndPAD
 $PAD
@@ -3605,7 +3645,7 @@ $PAD
 Sh "AA19" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 55 "N-000169"
+Ne 65 "N-000213"
 Po 2952 3739
 $EndPAD
 $PAD
@@ -3633,7 +3673,7 @@ $PAD
 Sh "AB1" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -4133 4133
 $EndPAD
 $PAD
@@ -3780,7 +3820,7 @@ $PAD
 Sh "AB22" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 4133 4133
 $EndPAD
 $EndMODULE  FGG484bga-p10
@@ -3802,7 +3842,7 @@ $PAD
 Sh "12" R 315 98 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "N-000411"
+Ne 67 "N-000403"
 Po -1613 1082
 $EndPAD
 $PAD
@@ -3830,14 +3870,14 @@ $PAD
 Sh "8" R 315 98 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "N-000411"
+Ne 67 "N-000403"
 Po -1613 295
 $EndPAD
 $PAD
 Sh "7" R 315 98 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 60 "N-000412"
+Ne 68 "N-000404"
 Po -1613 98
 $EndPAD
 $PAD
@@ -3893,7 +3933,7 @@ $PAD
 Sh "47" R 99 315 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 60 "N-000412"
+Ne 68 "N-000404"
 Po -885 -1613
 $EndPAD
 $PAD
@@ -3914,7 +3954,7 @@ $PAD
 Sh "44" R 98 315 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "N-000411"
+Ne 67 "N-000403"
 Po -295 -1613
 $EndPAD
 $PAD
@@ -3949,14 +3989,14 @@ $PAD
 Sh "39" R 99 315 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "N-000411"
+Ne 67 "N-000403"
 Po 688 -1613
 $EndPAD
 $PAD
 Sh "38" R 99 315 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 60 "N-000412"
+Ne 68 "N-000404"
 Po 885 -1613
 $EndPAD
 $PAD
@@ -3970,7 +4010,7 @@ $PAD
 Sh "25" R 315 98 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 14 "/Ethernet_Phy/ETH_INT"
+Ne 16 "/Ethernet_Phy/ETH_INT"
 Po 1613 1082
 $EndPAD
 $PAD
@@ -4012,7 +4052,7 @@ $PAD
 Sh "31" R 315 98 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 60 "N-000412"
+Ne 68 "N-000404"
 Po 1613 -98
 $EndPAD
 $PAD
@@ -4040,21 +4080,21 @@ $PAD
 Sh "35" R 315 99 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "N-000411"
+Ne 67 "N-000403"
 Po 1613 -885
 $EndPAD
 $PAD
 Sh "36" R 315 98 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "N-000411"
+Ne 67 "N-000403"
 Po 1613 -1082
 $EndPAD
 $PAD
 Sh "13" R 98 315 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 60 "N-000412"
+Ne 68 "N-000404"
 Po -1082 1613
 $EndPAD
 $PAD
@@ -4124,14 +4164,14 @@ $PAD
 Sh "23" R 99 315 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 59 "N-000411"
+Ne 67 "N-000403"
 Po 885 1613
 $EndPAD
 $PAD
 Sh "24" R 98 315 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 60 "N-000412"
+Ne 68 "N-000404"
 Po 1082 1613
 $EndPAD
 $EndMODULE  LQFP48
@@ -4224,7 +4264,7 @@ $PAD
 Sh "CASE" R 620 540 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 50 "GND"
+Ne 58 "GND"
 Po 2690 -200
 $EndPAD
 $PAD
@@ -4245,21 +4285,21 @@ $PAD
 Sh "CASE" R 460 860 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 50 "GND"
+Ne 58 "GND"
 Po 3050 -3980
 $EndPAD
 $PAD
 Sh "CASE" R 460 860 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 50 "GND"
+Ne 58 "GND"
 Po -3050 -3980
 $EndPAD
 $PAD
 Sh "COM" R 460 540 0 0 1800
 Dr 0 0 0
 At SMD N 00440001
-Ne 50 "GND"
+Ne 58 "GND"
 Po -3060 -200
 $EndPAD
 $EndMODULE  MICROSD
@@ -4523,14 +4563,14 @@ $PAD
 Sh "6" R 100 600 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 48 "/Non_volatile_memories/FRB_N"
+Ne 56 "/Non_volatile_memories/FRB_N"
 Po -1280 3850
 $EndPAD
 $PAD
 Sh "7" R 100 600 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 48 "/Non_volatile_memories/FRB_N"
+Ne 56 "/Non_volatile_memories/FRB_N"
 Po -1090 3850
 $EndPAD
 $PAD
@@ -4565,14 +4605,14 @@ $PAD
 Sh "12" R 100 600 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 49 "3.3V"
+Ne 57 "3.3V"
 Po -100 3850
 $EndPAD
 $PAD
 Sh "13" R 100 600 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 100 3850
 $EndPAD
 $PAD
@@ -4614,7 +4654,7 @@ $PAD
 Sh "19" R 100 600 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 49 "3.3V"
+Ne 57 "3.3V"
 Po 1280 3850
 $EndPAD
 $PAD
@@ -4733,14 +4773,14 @@ $PAD
 Sh "36" R 100 600 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 100 -3850
 $EndPAD
 $PAD
 Sh "37" R 100 600 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 49 "3.3V"
+Ne 57 "3.3V"
 Po -100 -3850
 $EndPAD
 $PAD
@@ -4839,70 +4879,70 @@ $PAD
 Sh "A1" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -1259 -2165
 $EndPAD
 $PAD
 Sh "A9" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "N-000040"
+Ne 60 "N-000039"
 Po 1259 -2165
 $EndPAD
 $PAD
 Sh "B1" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 32 "/FPGA_Spartan6/M0_DQ14"
+Ne 33 "/FPGA_Spartan6/M0_DQ14"
 Po -1259 -1771
 $EndPAD
 $PAD
 Sh "B9" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 4 "/DDR_Banks/M0_DQ1"
+Ne 8 "/DDR_Banks/M0_DQ1"
 Po 1259 -1771
 $EndPAD
 $PAD
 Sh "C1" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 30 "/FPGA_Spartan6/M0_DQ12"
+Ne 9 "/DDR_Banks/M0_DQ12"
 Po -1259 -1377
 $EndPAD
 $PAD
 Sh "C9" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 34 "/FPGA_Spartan6/M0_DQ3"
+Ne 36 "/FPGA_Spartan6/M0_DQ3"
 Po 1259 -1377
 $EndPAD
 $PAD
 Sh "D1" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 28 "/FPGA_Spartan6/M0_DQ10"
+Ne 30 "/FPGA_Spartan6/M0_DQ10"
 Po -1259 -983
 $EndPAD
 $PAD
 Sh "D9" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 35 "/FPGA_Spartan6/M0_DQ5"
+Ne 37 "/FPGA_Spartan6/M0_DQ5"
 Po 1259 -983
 $EndPAD
 $PAD
 Sh "E1" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 38 "/FPGA_Spartan6/M0_DQ8"
+Ne 12 "/DDR_Banks/M0_DQ8"
 Po -1259 -590
 $EndPAD
 $PAD
 Sh "E9" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 37 "/FPGA_Spartan6/M0_DQ7"
+Ne 11 "/DDR_Banks/M0_DQ7"
 Po 1259 -590
 $EndPAD
 $PAD
@@ -4923,91 +4963,91 @@ $PAD
 Sh "A2" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 33 "/FPGA_Spartan6/M0_DQ15"
+Ne 34 "/FPGA_Spartan6/M0_DQ15"
 Po -944 -2165
 $EndPAD
 $PAD
 Sh "A3" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -629 -2165
 $EndPAD
 $PAD
 Sh "A7" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "N-000040"
+Ne 60 "N-000039"
 Po 629 -2165
 $EndPAD
 $PAD
 Sh "A8" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 27 "/FPGA_Spartan6/M0_DQ0"
+Ne 29 "/FPGA_Spartan6/M0_DQ0"
 Po 944 -2165
 $EndPAD
 $PAD
 Sh "B2" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "N-000040"
+Ne 60 "N-000039"
 Po -944 -1771
 $EndPAD
 $PAD
 Sh "B3" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 31 "/FPGA_Spartan6/M0_DQ13"
+Ne 32 "/FPGA_Spartan6/M0_DQ13"
 Po -629 -1771
 $EndPAD
 $PAD
 Sh "B7" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 5 "/DDR_Banks/M0_DQ2"
+Ne 35 "/FPGA_Spartan6/M0_DQ2"
 Po 629 -1771
 $EndPAD
 $PAD
 Sh "B8" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 944 -1771
 $EndPAD
 $PAD
 Sh "C2" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -944 -1377
 $EndPAD
 $PAD
 Sh "C3" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 29 "/FPGA_Spartan6/M0_DQ11"
+Ne 31 "/FPGA_Spartan6/M0_DQ11"
 Po -629 -1377
 $EndPAD
 $PAD
 Sh "C7" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 6 "/DDR_Banks/M0_DQ4"
+Ne 10 "/DDR_Banks/M0_DQ4"
 Po 629 -1377
 $EndPAD
 $PAD
 Sh "C8" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "N-000040"
+Ne 60 "N-000039"
 Po 944 -1377
 $EndPAD
 $PAD
 Sh "D2" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "N-000040"
+Ne 60 "N-000039"
 Po -944 -983
 $EndPAD
 $PAD
@@ -5021,119 +5061,119 @@ $PAD
 Sh "D7" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 36 "/FPGA_Spartan6/M0_DQ6"
+Ne 38 "/FPGA_Spartan6/M0_DQ6"
 Po 629 -983
 $EndPAD
 $PAD
 Sh "D8" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 944 -983
 $EndPAD
 $PAD
 Sh "E2" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -944 -590
 $EndPAD
 $PAD
 Sh "E3" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 14 "/DDR_Banks/M0_UDQS"
 Po -629 -590
 $EndPAD
 $PAD
 Sh "E7" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 40 "/FPGA_Spartan6/M0_LDQS"
 Po 629 -590
 $EndPAD
 $PAD
 Sh "E8" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "N-000040"
+Ne 60 "N-000039"
 Po 944 -590
 $EndPAD
 $PAD
 Sh "F2" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -944 -196
 $EndPAD
 $PAD
 Sh "F3" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 42 "/FPGA_Spartan6/M0_UDM"
 Po -629 -196
 $EndPAD
 $PAD
 Sh "F7" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 13 "/DDR_Banks/M0_LDM"
 Po 629 -196
 $EndPAD
 $PAD
 Sh "F8" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "N-000040"
+Ne 60 "N-000039"
 Po 944 -196
 $EndPAD
 $PAD
 Sh "G2" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 26 "/FPGA_Spartan6/M0_CLK"
+Ne 27 "/FPGA_Spartan6/M0_CLK"
 Po -944 196
 $EndPAD
 $PAD
 Sh "G3" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 3 "/DDR_Banks/M0_CLK#"
+Ne 28 "/FPGA_Spartan6/M0_CLK#"
 Po -629 196
 $EndPAD
 $PAD
 Sh "G7" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 15 "/DDR_Banks/M0_WE#"
 Po 629 196
 $EndPAD
 $PAD
 Sh "G8" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 7 "/DDR_Banks/M0_CAS#"
 Po 944 196
 $EndPAD
 $PAD
 Sh "H2" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 18 "/FPGA_Spartan6/M0_A12"
+Ne 20 "/FPGA_Spartan6/M0_A12"
 Po -944 590
 $EndPAD
 $PAD
 Sh "H3" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 26 "/FPGA_Spartan6/M0_CKE"
 Po -629 590
 $EndPAD
 $PAD
 Sh "H7" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 41 "/FPGA_Spartan6/M0_RAS#"
 Po 629 590
 $EndPAD
 $PAD
@@ -5147,35 +5187,35 @@ $PAD
 Sh "J2" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 17 "/FPGA_Spartan6/M0_A11"
+Ne 1 "/DDR_Banks/M0_A11"
 Po -944 983
 $EndPAD
 $PAD
 Sh "J3" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 25 "/FPGA_Spartan6/M0_A9"
+Ne 4 "/DDR_Banks/M0_A9"
 Po -629 983
 $EndPAD
 $PAD
 Sh "J7" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 6 "/DDR_Banks/M0_BA1"
 Po 629 983
 $EndPAD
 $PAD
 Sh "J8" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 0 ""
+Ne 5 "/DDR_Banks/M0_BA0"
 Po 944 983
 $EndPAD
 $PAD
 Sh "K2" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 2 "/DDR_Banks/M0_A8"
+Ne 25 "/FPGA_Spartan6/M0_A8"
 Po -944 1377
 $EndPAD
 $PAD
@@ -5189,70 +5229,70 @@ $PAD
 Sh "K7" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 15 "/FPGA_Spartan6/M0_A0"
+Ne 17 "/FPGA_Spartan6/M0_A0"
 Po 629 1377
 $EndPAD
 $PAD
 Sh "K8" O 157 157 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 16 "/FPGA_Spartan6/M0_A10"
+Ne 19 "/FPGA_Spartan6/M0_A10"
 Po 944 1377
 $EndPAD
 $PAD
 Sh "L2" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 23 "/FPGA_Spartan6/M0_A6"
+Ne 3 "/DDR_Banks/M0_A6"
 Po -944 1771
 $EndPAD
 $PAD
 Sh "L3" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 22 "/FPGA_Spartan6/M0_A5"
+Ne 23 "/FPGA_Spartan6/M0_A5"
 Po -629 1771
 $EndPAD
 $PAD
 Sh "L7" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 19 "/FPGA_Spartan6/M0_A2"
+Ne 2 "/DDR_Banks/M0_A2"
 Po 629 1771
 $EndPAD
 $PAD
 Sh "L8" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 1 "/DDR_Banks/M0_A1"
+Ne 18 "/FPGA_Spartan6/M0_A1"
 Po 944 1771
 $EndPAD
 $PAD
 Sh "M2" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 21 "/FPGA_Spartan6/M0_A4"
+Ne 22 "/FPGA_Spartan6/M0_A4"
 Po -944 2165
 $EndPAD
 $PAD
 Sh "M3" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -629 2165
 $EndPAD
 $PAD
 Sh "M7" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 52 "N-000040"
+Ne 60 "N-000039"
 Po 629 2165
 $EndPAD
 $PAD
 Sh "M8" O 157 158 0 0 1800
 Dr 0 0 0
 At SMD N 00888000
-Ne 20 "/FPGA_Spartan6/M0_A3"
+Ne 21 "/FPGA_Spartan6/M0_A3"
 Po 944 2165
 $EndPAD
 $EndMODULE  60fbga_ddr
@@ -5274,14 +5314,14 @@ $PAD
 Sh "A1" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -1259 -2165
 $EndPAD
 $PAD
 Sh "A9" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "N-000036"
+Ne 59 "N-000036"
 Po 1259 -2165
 $EndPAD
 $PAD
@@ -5365,14 +5405,14 @@ $PAD
 Sh "A3" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -629 -2165
 $EndPAD
 $PAD
 Sh "A7" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "N-000036"
+Ne 59 "N-000036"
 Po 629 -2165
 $EndPAD
 $PAD
@@ -5386,7 +5426,7 @@ $PAD
 Sh "B2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "N-000036"
+Ne 59 "N-000036"
 Po -944 -1771
 $EndPAD
 $PAD
@@ -5407,14 +5447,14 @@ $PAD
 Sh "B8" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 944 -1771
 $EndPAD
 $PAD
 Sh "C2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -944 -1377
 $EndPAD
 $PAD
@@ -5435,14 +5475,14 @@ $PAD
 Sh "C8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "N-000036"
+Ne 59 "N-000036"
 Po 944 -1377
 $EndPAD
 $PAD
 Sh "D2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "N-000036"
+Ne 59 "N-000036"
 Po -944 -983
 $EndPAD
 $PAD
@@ -5463,14 +5503,14 @@ $PAD
 Sh "D8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po 944 -983
 $EndPAD
 $PAD
 Sh "E2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -944 -590
 $EndPAD
 $PAD
@@ -5491,14 +5531,14 @@ $PAD
 Sh "E8" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "N-000036"
+Ne 59 "N-000036"
 Po 944 -590
 $EndPAD
 $PAD
 Sh "F2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -944 -196
 $EndPAD
 $PAD
@@ -5519,21 +5559,21 @@ $PAD
 Sh "F8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "N-000036"
+Ne 59 "N-000036"
 Po 944 -196
 $EndPAD
 $PAD
 Sh "G2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 13 "/DDR_Banks/M1_CLK"
+Ne 0 ""
 Po -944 196
 $EndPAD
 $PAD
 Sh "G3" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 47 "/FPGA_Spartan6/M1_CLK#"
+Ne 0 ""
 Po -629 196
 $EndPAD
 $PAD
@@ -5554,7 +5594,7 @@ $PAD
 Sh "H2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 9 "/DDR_Banks/M1_A12"
+Ne 47 "/FPGA_Spartan6/M1_A12"
 Po -944 590
 $EndPAD
 $PAD
@@ -5582,14 +5622,14 @@ $PAD
 Sh "J2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 41 "/FPGA_Spartan6/M1_A11"
+Ne 46 "/FPGA_Spartan6/M1_A11"
 Po -944 983
 $EndPAD
 $PAD
 Sh "J3" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 12 "/DDR_Banks/M1_A9"
+Ne 55 "/FPGA_Spartan6/M1_A9"
 Po -629 983
 $EndPAD
 $PAD
@@ -5610,84 +5650,84 @@ $PAD
 Sh "K2" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 46 "/FPGA_Spartan6/M1_A8"
+Ne 54 "/FPGA_Spartan6/M1_A8"
 Po -944 1377
 $EndPAD
 $PAD
 Sh "K3" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 45 "/FPGA_Spartan6/M1_A7"
+Ne 53 "/FPGA_Spartan6/M1_A7"
 Po -629 1377
 $EndPAD
 $PAD
 Sh "K7" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 7 "/DDR_Banks/M1_A0"
+Ne 43 "/FPGA_Spartan6/M1_A0"
 Po 629 1377
 $EndPAD
 $PAD
 Sh "K8" O 157 157 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 40 "/FPGA_Spartan6/M1_A10"
+Ne 45 "/FPGA_Spartan6/M1_A10"
 Po 944 1377
 $EndPAD
 $PAD
 Sh "L2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 11 "/DDR_Banks/M1_A6"
+Ne 52 "/FPGA_Spartan6/M1_A6"
 Po -944 1771
 $EndPAD
 $PAD
 Sh "L3" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 44 "/FPGA_Spartan6/M1_A5"
+Ne 51 "/FPGA_Spartan6/M1_A5"
 Po -629 1771
 $EndPAD
 $PAD
 Sh "L7" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 42 "/FPGA_Spartan6/M1_A2"
+Ne 48 "/FPGA_Spartan6/M1_A2"
 Po 629 1771
 $EndPAD
 $PAD
 Sh "L8" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 8 "/DDR_Banks/M1_A1"
+Ne 44 "/FPGA_Spartan6/M1_A1"
 Po 944 1771
 $EndPAD
 $PAD
 Sh "M2" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 43 "/FPGA_Spartan6/M1_A4"
+Ne 50 "/FPGA_Spartan6/M1_A4"
 Po -944 2165
 $EndPAD
 $PAD
 Sh "M3" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 50 "GND"
+Ne 58 "GND"
 Po -629 2165
 $EndPAD
 $PAD
 Sh "M7" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 51 "N-000036"
+Ne 59 "N-000036"
 Po 629 2165
 $EndPAD
 $PAD
 Sh "M8" O 157 158 0 0 0
 Dr 0 0 0
 At SMD N 00888000
-Ne 10 "/DDR_Banks/M1_A3"
+Ne 49 "/FPGA_Spartan6/M1_A3"
 Po 944 2165
 $EndPAD
 $EndMODULE  60fbga_ddr