diff --git a/kicad/xue-rnc/DBG_PRG.sch b/kicad/xue-rnc/DBG_PRG.sch index 5ec3906..a1f9091 100644 --- a/kicad/xue-rnc/DBG_PRG.sch +++ b/kicad/xue-rnc/DBG_PRG.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 07:03:34 PM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:15:24 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 38b42b2..4bf376d 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 07:03:34 PM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:15:24 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -535,19 +535,19 @@ Entry Wire Line Entry Wire Line 10100 4400 10200 4500 $Comp -L GND #PWR16 +L GND #PWR071 U 1 1 4C699C4D P 9950 2100 -F 0 "#PWR16" H 9950 2100 30 0001 C CNN +F 0 "#PWR071" H 9950 2100 30 0001 C CNN F 1 "GND" H 9950 2030 30 0001 C CNN 1 9950 2100 1 0 0 -1 $EndComp $Comp -L GND #PWR8 +L GND #PWR072 U 1 1 4C699C48 P 4550 2150 -F 0 "#PWR8" H 4550 2150 30 0001 C CNN +F 0 "#PWR072" H 4550 2150 30 0001 C CNN F 1 "GND" H 4550 2080 30 0001 C CNN 1 4550 2150 1 0 0 -1 @@ -605,37 +605,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR10 +L GND #PWR073 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR10" H 6900 6200 30 0001 C CNN +F 0 "#PWR073" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR9 +L +2.5V #PWR074 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR9" H 6900 5750 20 0001 C CNN +F 0 "#PWR074" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR1 +L +2.5V #PWR075 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR1" H 1700 5750 20 0001 C CNN +F 0 "#PWR075" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR2 +L GND #PWR076 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR2" H 1700 6200 30 0001 C CNN +F 0 "#PWR076" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -651,19 +651,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR4 +L +2.5V #PWR077 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR4" H 3050 1700 20 0001 C CNN +F 0 "#PWR077" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR14 +L +2.5V #PWR078 U 1 1 4C61CFC6 P 8400 1700 -F 0 "#PWR14" H 8400 1650 20 0001 C CNN +F 0 "#PWR078" H 8400 1650 20 0001 C CNN F 1 "+2.5V" H 8400 1800 30 0000 C CNN 1 8400 1700 1 0 0 -1 @@ -729,37 +729,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR11 +L +2.5V #PWR079 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR11" H 8300 5700 20 0001 C CNN +F 0 "#PWR079" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR12 +L GND #PWR080 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR12" H 8300 6350 30 0001 C CNN +F 0 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2750 -1 0 0 1 $EndComp $Comp L R_PACK4 RP3 U 1 1 4C69D3A4 -P 14450 2300 -F 0 "RP3" H 14450 2750 40 0000 C CNN -F 1 "R_PACK4" H 14450 2250 40 0000 C CNN - 1 14450 2300 +P 13900 2250 +F 0 "RP3" H 13900 2700 40 0000 C CNN +F 1 "R_PACK4" H 13900 2200 40 0000 C CNN + 1 13900 2250 -1 0 0 1 $EndComp $Comp L R_PACK4 RP4 U 1 1 4C69D3A3 -P 16050 2200 -F 0 "RP4" H 16050 2650 40 0000 C CNN -F 1 "R_PACK4" H 16050 2150 40 0000 C CNN - 1 16050 2200 +P 15500 2150 +F 0 "RP4" H 15500 2600 40 0000 C CNN +F 1 "R_PACK4" H 15500 2100 40 0000 C CNN + 1 15500 2150 -1 0 0 1 $EndComp Text Label 17600 4100 2 60 ~ 0 @@ -2246,50 +2246,50 @@ Text Label 17050 5000 0 60 ~ 0 R_M1_RAS# Text Label 17050 5100 0 60 ~ 0 R_M1_CAS# -Text Label 14650 2350 0 60 ~ 0 +Text Label 14100 2300 0 60 ~ 0 R_M1_CAS# -Text Label 14650 2050 0 60 ~ 0 +Text Label 14100 2000 0 60 ~ 0 R_M1_RAS# -Text HLabel 13900 2050 0 60 Output ~ 0 +Text HLabel 13350 2000 0 60 Output ~ 0 M1_RAS# -Text HLabel 13900 2350 0 60 Output ~ 0 +Text HLabel 13350 2300 0 60 Output ~ 0 M1_CAS# $Comp L R_PACK4 RP2 U 1 1 4C69CEE8 -P 14450 1700 -F 0 "RP2" H 14450 2150 40 0000 C CNN -F 1 "R_PACK4" H 14450 1650 40 0000 C CNN - 1 14450 1700 +P 13900 1650 +F 0 "RP2" H 13900 2100 40 0000 C CNN +F 1 "R_PACK4" H 13900 1600 40 0000 C CNN + 1 13900 1650 -1 0 0 1 $EndComp -Text Label 14200 1850 2 60 ~ 0 +Text Label 13650 1800 2 60 ~ 0 M1_BA1 -Text Label 14200 1950 2 60 ~ 0 +Text Label 13650 1900 2 60 ~ 0 M1_BA0 -Text Label 14700 1450 0 60 ~ 0 +Text Label 14150 1400 0 60 ~ 0 R_M1_A0 -Text Label 14700 1350 0 60 ~ 0 +Text Label 14150 1300 0 60 ~ 0 R_M1_A1 -Text Label 14700 1150 0 60 ~ 0 +Text Label 14150 1100 0 60 ~ 0 R_M1_A3 -Text Label 14700 1250 0 60 ~ 0 +Text Label 14150 1200 0 60 ~ 0 R_M1_A2 -Text Label 13950 1250 0 60 ~ 0 +Text Label 13400 1200 0 60 ~ 0 M1_A2 -Text Label 13950 1150 0 60 ~ 0 +Text Label 13400 1100 0 60 ~ 0 M1_A3 -Text Label 13950 1350 0 60 ~ 0 +Text Label 13400 1300 0 60 ~ 0 M1_A1 -Text Label 13950 1450 0 60 ~ 0 +Text Label 13400 1400 0 60 ~ 0 M1_A0 $Comp L R_PACK4 RP1 U 1 1 4C69C6B2 -P 14450 1100 -F 0 "RP1" H 14450 1550 40 0000 C CNN -F 1 "R_PACK4" H 14450 1050 40 0000 C CNN - 1 14450 1100 +P 13900 1050 +F 0 "RP1" H 13900 1500 40 0000 C CNN +F 1 "R_PACK4" H 13900 1000 40 0000 C CNN + 1 13900 1050 -1 0 0 1 $EndComp Text Label 5750 6350 0 40 ~ 0 @@ -2297,28 +2297,28 @@ VCC02 Text GLabel 5300 6250 3 30 BiDi ~ 0 VCCO2 $Comp -L +3.3V #PWR30 +L +3.3V #PWR053 U 1 1 4C65CF66 P 1650 14300 -F 0 "#PWR30" H 1650 14260 30 0001 C CNN +F 0 "#PWR053" H 1650 14260 30 0001 C CNN F 1 "+3.3V" H 1650 14410 30 0000 C CNN 1 1650 14300 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR35 +L +2.5V #PWR054 U 1 1 4C65C84B P 4600 14300 -F 0 "#PWR35" H 4600 14250 20 0001 C CNN +F 0 "#PWR054" H 4600 14250 20 0001 C CNN F 1 "+2.5V" H 4600 14400 30 0000 C CNN 1 4600 14300 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR32 +L +2.5V #PWR055 U 1 1 4C65C837 P 4600 12350 -F 0 "#PWR32" H 4600 12300 20 0001 C CNN +F 0 "#PWR055" H 4600 12300 20 0001 C CNN F 1 "+2.5V" H 4600 12450 30 0000 C CNN 1 4600 12350 1 0 0 -1 @@ -2365,10 +2365,10 @@ F 1 "470nF" H 6050 12550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR33 +L GND #PWR056 U 1 1 4C656D9B P 4600 12950 -F 0 "#PWR33" H 4600 12950 30 0001 C CNN +F 0 "#PWR056" H 4600 12950 30 0001 C CNN F 1 "GND" H 4600 12880 30 0001 C CNN 1 4600 12950 1 0 0 -1 @@ -2430,10 +2430,10 @@ F 1 "470nF" H 6050 13550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR34 +L GND #PWR057 U 1 1 4C656D47 P 4600 13950 -F 0 "#PWR34" H 4600 13950 30 0001 C CNN +F 0 "#PWR057" H 4600 13950 30 0001 C CNN F 1 "GND" H 4600 13880 30 0001 C CNN 1 4600 13950 1 0 0 -1 @@ -2486,10 +2486,10 @@ F 1 "470nF" H 6050 14500 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR36 +L GND #PWR058 U 1 1 4C656CFD P 4600 14900 -F 0 "#PWR36" H 4600 14900 30 0001 C CNN +F 0 "#PWR058" H 4600 14900 30 0001 C CNN F 1 "GND" H 4600 14830 30 0001 C CNN 1 4600 14900 1 0 0 -1 @@ -2533,10 +2533,10 @@ F 1 "100uF" H 4650 14500 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR31 +L GND #PWR059 U 1 1 4C656CBC P 1650 14900 -F 0 "#PWR31" H 1650 14900 30 0001 C CNN +F 0 "#PWR059" H 1650 14900 30 0001 C CNN F 1 "GND" H 1650 14830 30 0001 C CNN 1 1650 14900 1 0 0 -1 @@ -2582,10 +2582,10 @@ $EndComp Text Notes 1750 13400 0 30 ~ 0 VCC_AUX Decoupling Capacitors (7) $Comp -L GND #PWR29 +L GND #PWR060 U 1 1 4C656C68 P 1650 14000 -F 0 "#PWR29" H 1650 14000 30 0001 C CNN +F 0 "#PWR060" H 1650 14000 30 0001 C CNN F 1 "GND" H 1650 13930 30 0001 C CNN 1 1650 14000 1 0 0 -1 @@ -2654,19 +2654,19 @@ F 1 "100uF" H 1700 13600 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR28 +L +2.5V #PWR061 U 1 1 4C656BBA P 1650 13400 -F 0 "#PWR28" H 1650 13350 20 0001 C CNN +F 0 "#PWR061" H 1650 13350 20 0001 C CNN F 1 "+2.5V" H 1650 13500 30 0000 C CNN 1 1650 13400 1 0 0 -1 $EndComp $Comp -L GND #PWR27 +L GND #PWR062 U 1 1 4C656BA8 P 1650 12950 -F 0 "#PWR27" H 1650 12950 30 0001 C CNN +F 0 "#PWR062" H 1650 12950 30 0001 C CNN F 1 "GND" H 1650 12880 30 0001 C CNN 1 1650 12950 1 0 0 -1 @@ -2701,10 +2701,10 @@ F 1 "4.7uF" H 2050 12550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR26 +L +1.2V #PWR063 U 1 1 4C656AA1 P 1650 12350 -F 0 "#PWR26" H 1650 12490 20 0001 C CNN +F 0 "#PWR063" H 1650 12490 20 0001 C CNN F 1 "+1.2V" H 1650 12460 30 0000 C CNN 1 1650 12350 1 0 0 -1 @@ -2769,46 +2769,46 @@ NF_RE_N Text HLabel 18000 7650 2 60 BiDi ~ 0 NF_RNB $Comp -L +3.3V #PWR40 +L +3.3V #PWR064 U 1 1 4C61E5B3 P 15900 6100 -F 0 "#PWR40" H 15900 6060 30 0001 C CNN +F 0 "#PWR064" H 15900 6060 30 0001 C CNN F 1 "+3.3V" H 15900 6210 30 0000 C CNN 1 15900 6100 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR42 +L +1.2V #PWR065 U 1 1 4C61E58C P 16500 9850 -F 0 "#PWR42" H 16500 9990 20 0001 C CNN +F 0 "#PWR065" H 16500 9990 20 0001 C CNN F 1 "+1.2V" H 16500 9960 30 0000 C CNN 1 16500 9850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR39 +L +2.5V #PWR066 U 1 1 4C61E577 P 15000 9850 -F 0 "#PWR39" H 15000 9800 20 0001 C CNN +F 0 "#PWR066" H 15000 9800 20 0001 C CNN F 1 "+2.5V" H 15000 9950 30 0000 C CNN 1 15000 9850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR43 +L +2.5V #PWR067 U 1 1 4C61E523 P 19700 650 -F 0 "#PWR43" H 19700 600 20 0001 C CNN +F 0 "#PWR067" H 19700 600 20 0001 C CNN F 1 "+2.5V" H 19700 750 30 0000 C CNN 1 19700 650 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR37 +L +2.5V #PWR068 U 1 1 4C61E51F P 8100 650 -F 0 "#PWR37" H 8100 600 20 0001 C CNN +F 0 "#PWR068" H 8100 600 20 0001 C CNN F 1 "+2.5V" H 8100 750 30 0000 C CNN 1 8100 650 1 0 0 -1 @@ -2836,35 +2836,35 @@ SD_CMD Text HLabel 18450 6750 2 60 BiDi ~ 0 SD_DAT[0..3] Entry Wire Line - 13750 1850 13850 1950 + 13200 1800 13300 1900 Entry Wire Line - 13750 1750 13850 1850 -Text Label 15100 1950 2 60 ~ 0 + 13200 1700 13300 1800 +Text Label 14550 1900 2 60 ~ 0 R_M1_BA0 -Text Label 15100 1850 2 60 ~ 0 +Text Label 14550 1800 2 60 ~ 0 R_M1_BA1 -Text HLabel 13650 1750 0 60 Output ~ 0 +Text HLabel 13100 1700 0 60 Output ~ 0 M1_BA[0..1] -Text HLabel 15750 3950 0 60 Output ~ 0 +Text HLabel 15200 3900 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR25 +L GND #PWR069 U 1 1 4C60C21D P 1600 5950 -F 0 "#PWR25" H 1600 5950 30 0001 C CNN +F 0 "#PWR069" H 1600 5950 30 0001 C CNN F 1 "GND" H 1600 5880 30 0001 C CNN 1 1600 5950 -1 0 0 -1 $EndComp -Text HLabel 22100 1800 2 60 BiDi ~ 0 +Text HLabel 17500 1600 0 60 BiDi ~ 0 USBA_VM -Text HLabel 22100 1700 2 60 BiDi ~ 0 +Text HLabel 17500 1500 0 60 BiDi ~ 0 USBA_VP -Text HLabel 22100 1600 2 60 BiDi ~ 0 +Text HLabel 17500 1400 0 60 BiDi ~ 0 USBA_RCV -Text HLabel 22100 1500 2 60 BiDi ~ 0 +Text HLabel 17500 1300 0 60 BiDi ~ 0 USBA_OE_N -Text HLabel 22100 1400 2 60 BiDi ~ 0 +Text HLabel 17500 1200 0 60 BiDi ~ 0 USBA_SPD Text HLabel 14200 6750 0 60 BiDi ~ 0 ETH_CLK @@ -2954,39 +2954,39 @@ Text Label 22050 3800 0 60 ~ 0 R_M1_DQ11 Text Label 22050 3900 0 60 ~ 0 R_M1_DQ10 -Text Label 12550 3000 0 60 ~ 0 +Text Label 12000 2950 0 60 ~ 0 M1_DQ6 -Text Label 12550 3100 0 60 ~ 0 +Text Label 12000 3050 0 60 ~ 0 M1_DQ7 -Text Label 12550 2900 0 60 ~ 0 +Text Label 12000 2850 0 60 ~ 0 M1_DQ5 -Text Label 12550 2800 0 60 ~ 0 +Text Label 12000 2750 0 60 ~ 0 M1_DQ4 -Text Label 12550 2600 0 60 ~ 0 +Text Label 12000 2550 0 60 ~ 0 M1_DQ2 -Text Label 12550 2700 0 60 ~ 0 +Text Label 12000 2650 0 60 ~ 0 M1_DQ3 -Text Label 12550 2500 0 60 ~ 0 +Text Label 12000 2450 0 60 ~ 0 M1_DQ1 -Text Label 12550 2400 0 60 ~ 0 +Text Label 12000 2350 0 60 ~ 0 M1_DQ0 -Text Label 12550 3400 0 60 ~ 0 +Text Label 12000 3350 0 60 ~ 0 M1_DQ10 -Text Label 12550 3500 0 60 ~ 0 +Text Label 12000 3450 0 60 ~ 0 M1_DQ11 -Text Label 12550 3300 0 60 ~ 0 +Text Label 12000 3250 0 60 ~ 0 M1_DQ9 -Text Label 12550 3200 0 60 ~ 0 +Text Label 12000 3150 0 60 ~ 0 M1_DQ8 -Text Label 12550 3600 0 60 ~ 0 +Text Label 12000 3550 0 60 ~ 0 M1_DQ12 -Text Label 12550 3700 0 60 ~ 0 +Text Label 12000 3650 0 60 ~ 0 M1_DQ13 -Text Label 12550 3900 0 60 ~ 0 +Text Label 12000 3850 0 60 ~ 0 M1_DQ15 -Text Label 12550 3800 0 60 ~ 0 +Text Label 12000 3750 0 60 ~ 0 M1_DQ14 -Text HLabel 12350 2300 0 60 BiDi ~ 0 +Text HLabel 11800 2250 0 60 BiDi ~ 0 M1_DQ[0..15] Text HLabel 1450 5700 0 60 Output ~ 0 M0_CS# @@ -3173,56 +3173,56 @@ Entry Wire Line Entry Wire Line 1150 1350 1250 1450 Entry Wire Line - 12450 850 12550 950 + 11900 800 12000 900 Entry Wire Line - 12450 950 12550 1050 + 11900 900 12000 1000 Entry Wire Line - 12450 1050 12550 1150 + 11900 1000 12000 1100 Entry Wire Line - 12450 1150 12550 1250 + 11900 1100 12000 1200 Entry Wire Line - 12450 1250 12550 1350 + 11900 1200 12000 1300 Entry Wire Line - 12450 1350 12550 1450 + 11900 1300 12000 1400 Entry Wire Line - 12450 1450 12550 1550 + 11900 1400 12000 1500 Entry Wire Line - 12450 1550 12550 1650 + 11900 1500 12000 1600 Entry Wire Line - 12450 1650 12550 1750 + 11900 1600 12000 1700 Entry Wire Line - 12450 1750 12550 1850 + 11900 1700 12000 1800 Entry Wire Line - 12450 1850 12550 1950 + 11900 1800 12000 1900 Entry Wire Line - 12450 1950 12550 2050 + 11900 1900 12000 2000 Entry Wire Line - 12450 2050 12550 2150 -Text Label 12650 1650 0 60 ~ 0 + 11900 2000 12000 2100 +Text Label 12100 1600 0 60 ~ 0 M1_A5 -Text Label 12650 1550 0 60 ~ 0 +Text Label 12100 1500 0 60 ~ 0 M1_A6 -Text Label 12650 1850 0 60 ~ 0 +Text Label 12100 1800 0 60 ~ 0 M1_A3 -Text Label 12650 2050 0 60 ~ 0 +Text Label 12100 2000 0 60 ~ 0 M1_A1 -Text Label 12650 2150 0 60 ~ 0 +Text Label 12100 2100 0 60 ~ 0 M1_A0 -Text Label 12650 1950 0 60 ~ 0 +Text Label 12100 1900 0 60 ~ 0 M1_A2 -Text Label 12650 1450 0 60 ~ 0 +Text Label 12100 1400 0 60 ~ 0 M1_A7 -Text Label 12650 1150 0 60 ~ 0 +Text Label 12100 1100 0 60 ~ 0 M1_A10 -Text Label 12650 1750 0 60 ~ 0 +Text Label 12100 1700 0 60 ~ 0 M1_A4 -Text Label 12650 1250 0 60 ~ 0 +Text Label 12100 1200 0 60 ~ 0 M1_A9 -Text Label 12650 1350 0 60 ~ 0 +Text Label 12100 1300 0 60 ~ 0 M1_A8 -Text Label 12650 1050 0 60 ~ 0 +Text Label 12100 1000 0 60 ~ 0 M1_A11 -Text Label 12650 950 0 60 ~ 0 +Text Label 12100 900 0 60 ~ 0 M1_A12 Text Label 17150 4900 0 60 ~ 0 R_M1_A6 @@ -3250,7 +3250,7 @@ Text Label 17150 4300 0 60 ~ 0 R_M1_A1 Text Label 17150 4200 0 60 ~ 0 R_M1_A0 -Text HLabel 12400 800 0 60 Output ~ 0 +Text HLabel 11850 750 0 60 Output ~ 0 M1_A[0..12] Text HLabel 14200 8750 0 60 BiDi ~ 0 ETH_INT @@ -3263,10 +3263,10 @@ M0_CLK Text HLabel 11150 4650 2 60 Output ~ 0 M0_CLK# $Comp -L GND #PWR41 +L GND #PWR070 U 1 1 4C439B7E P 16400 12650 -F 0 "#PWR41" H 16400 12650 30 0001 C CNN +F 0 "#PWR070" H 16400 12650 30 0001 C CNN F 1 "GND" H 16400 12580 30 0001 C CNN 1 16400 12650 -1 0 0 -1 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 9bde76c..2f5114c 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 07:03:34 PM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:15:24 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -244,19 +244,19 @@ F 1 "100nF" H 4000 5400 50 0000 L CNN -1 0 0 1 $EndComp $Comp -L GND #PWR24 +L GND #PWR013 U 1 1 4C65D6AB P 9350 3150 -F 0 "#PWR24" H 9350 3150 30 0001 C CNN +F 0 "#PWR013" H 9350 3150 30 0001 C CNN F 1 "GND" H 9350 3080 30 0001 C CNN 1 9350 3150 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR23 +L +3.3V #PWR014 U 1 1 4C65D69B P 9350 2650 -F 0 "#PWR23" H 9350 2610 30 0001 C CNN +F 0 "#PWR014" H 9350 2610 30 0001 C CNN F 1 "+3.3V" H 9350 2760 30 0000 C CNN 1 9350 2650 1 0 0 -1 @@ -320,10 +320,10 @@ SPI_DQ[0..3] Text HLabel 2450 1700 0 60 Input ~ 0 SPI_FLASH_CS# $Comp -L GND #PWR17 +L GND #PWR015 U 1 1 4C65ABE9 P 2650 2450 -F 0 "#PWR17" H 2650 2450 30 0001 C CNN +F 0 "#PWR015" H 2650 2450 30 0001 C CNN F 1 "GND" H 2650 2380 30 0001 C CNN 1 2650 2450 1 0 0 -1 @@ -356,19 +356,19 @@ Entry Wire Line Entry Wire Line 8150 3150 8250 3050 $Comp -L +3.3V #PWR21 +L +3.3V #PWR016 U 1 1 4C646C14 P 7950 2900 -F 0 "#PWR21" H 7950 2860 30 0001 C CNN +F 0 "#PWR016" H 7950 2860 30 0001 C CNN F 1 "+3.3V" H 7950 3010 30 0000 C CNN 1 7950 2900 1 0 0 -1 $EndComp $Comp -L GND #PWR22 +L GND #PWR017 U 1 1 4C646BEA P 7950 3000 -F 0 "#PWR22" H 7950 3000 30 0001 C CNN +F 0 "#PWR017" H 7950 3000 30 0001 C CNN F 1 "GND" H 7950 2930 30 0001 C CNN 1 7950 3000 1 0 0 -1 @@ -418,10 +418,10 @@ SD_DAT3 Text Label 4200 6100 0 30 ~ 0 SD_CMD $Comp -L GND #PWR18 +L GND #PWR018 U 1 1 4C61D875 P 3950 5800 -F 0 "#PWR18" H 3950 5800 30 0001 C CNN +F 0 "#PWR018" H 3950 5800 30 0001 C CNN F 1 "GND" H 3950 5730 30 0001 C CNN 1 3950 5800 1 0 0 -1 @@ -433,19 +433,19 @@ SD_DAT0 Text Label 4200 5850 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR20 +L GND #PWR019 U 1 1 4C438ADC P 5800 6200 -F 0 "#PWR20" H 5800 6200 30 0001 C CNN +F 0 "#PWR019" H 5800 6200 30 0001 C CNN F 1 "GND" H 5800 6130 30 0001 C CNN 1 5800 6200 1 0 0 -1 $EndComp $Comp -L GND #PWR19 +L GND #PWR020 U 1 1 4C438AD5 P 5350 6550 -F 0 "#PWR19" H 5350 6550 30 0001 C CNN +F 0 "#PWR020" H 5350 6550 30 0001 C CNN F 1 "GND" H 5350 6480 30 0001 C CNN 1 5350 6550 1 0 0 -1 diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index b646a6d..b2d07d0 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 07:03:34 PM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:15:24 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -186,19 +186,19 @@ Wire Wire Line Wire Wire Line 8000 2250 8000 2350 $Comp -L +3.3V #PWR71 +L +3.3V #PWR01 U 1 1 4C6D30A1 P 6150 1400 -F 0 "#PWR71" H 6150 1360 30 0001 C CNN +F 0 "#PWR01" H 6150 1360 30 0001 C CNN F 1 "+3.3V" H 6150 1510 30 0000 C CNN 1 6150 1400 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR77 +L +1.2V #PWR02 U 1 1 4C6D3097 P 9650 1400 -F 0 "#PWR77" H 9650 1540 20 0001 C CNN +F 0 "#PWR02" H 9650 1540 20 0001 C CNN F 1 "+1.2V" H 9650 1510 30 0000 C CNN 1 9650 1400 1 0 0 -1 @@ -234,10 +234,10 @@ F 2 "1206" H 9150 2100 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR72 +L GND #PWR03 U 1 1 4C6D2FD4 P 7200 2350 -F 0 "#PWR72" H 7200 2350 30 0001 C CNN +F 0 "#PWR03" H 7200 2350 30 0001 C CNN F 1 "GND" H 7200 2280 30 0001 C CNN 1 7200 2350 1 0 0 -1 @@ -283,37 +283,37 @@ F 2 "0402" H 9500 2100 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR76 +L GND #PWR04 U 1 1 4C6D2FCF P 9350 2350 -F 0 "#PWR76" H 9350 2350 30 0001 C CNN +F 0 "#PWR04" H 9350 2350 30 0001 C CNN F 1 "GND" H 9350 2280 30 0001 C CNN 1 9350 2350 1 0 0 -1 $EndComp $Comp -L GND #PWR75 +L GND #PWR05 U 1 1 4C6D2FCE P 8650 2350 -F 0 "#PWR75" H 8650 2350 30 0001 C CNN +F 0 "#PWR05" H 8650 2350 30 0001 C CNN F 1 "GND" H 8650 2280 30 0001 C CNN 1 8650 2350 1 0 0 -1 $EndComp $Comp -L GND #PWR69 +L GND #PWR06 U 1 1 4C6D2F47 P 5150 2350 -F 0 "#PWR69" H 5150 2350 30 0001 C CNN +F 0 "#PWR06" H 5150 2350 30 0001 C CNN F 1 "GND" H 5150 2280 30 0001 C CNN 1 5150 2350 1 0 0 -1 $EndComp $Comp -L GND #PWR70 +L GND #PWR07 U 1 1 4C6D2F41 P 5850 2350 -F 0 "#PWR70" H 5850 2350 30 0001 C CNN +F 0 "#PWR07" H 5850 2350 30 0001 C CNN F 1 "GND" H 5850 2280 30 0001 C CNN 1 5850 2350 1 0 0 -1 @@ -359,10 +359,10 @@ F 2 "0402" H 5150 2050 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR67 +L GND #PWR08 U 1 1 4C6D2CCE P 3700 2350 -F 0 "#PWR67" H 3700 2350 30 0001 C CNN +F 0 "#PWR08" H 3700 2350 30 0001 C CNN F 1 "GND" H 3700 2280 30 0001 C CNN 1 3700 2350 1 0 0 -1 @@ -398,19 +398,19 @@ F 2 "0805" H 3700 2050 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR73 +L GND #PWR09 U 1 1 4C6D2C02 P 8000 2350 -F 0 "#PWR73" H 8000 2350 30 0001 C CNN +F 0 "#PWR09" H 8000 2350 30 0001 C CNN F 1 "GND" H 8000 2280 30 0001 C CNN 1 8000 2350 1 0 0 -1 $EndComp $Comp -L GND #PWR68 +L GND #PWR010 U 1 1 4C6D2BFC P 4500 2350 -F 0 "#PWR68" H 4500 2350 30 0001 C CNN +F 0 "#PWR010" H 4500 2350 30 0001 C CNN F 1 "GND" H 4500 2280 30 0001 C CNN 1 4500 2350 1 0 0 -1 @@ -436,10 +436,10 @@ F 2 "SOT23-5" H 4400 1700 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR66 +L GND #PWR011 U 1 1 4C6C9F96 P 3000 6450 -F 0 "#PWR66" H 3000 6450 30 0001 C CNN +F 0 "#PWR011" H 3000 6450 30 0001 C CNN F 1 "GND" H 3000 6380 30 0001 C CNN 1 3000 6450 1 0 0 -1 @@ -455,10 +455,10 @@ F 2 "DFN10" H 2750 5200 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR74 +L GND #PWR012 U 1 1 4C69F7A5 P 8050 4950 -F 0 "#PWR74" H 8050 4950 30 0001 C CNN +F 0 "#PWR012" H 8050 4950 30 0001 C CNN F 1 "GND" H 8050 4880 30 0001 C CNN 1 8050 4950 1 0 0 -1 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index df5c2ee..f5d2880 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 07:03:34 PM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:15:24 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -60,6 +60,331 @@ Comment3 "" Comment4 "" $EndDescr $Comp +L C C86 +U 1 1 4C71C9C5 +P 7500 1500 +F 0 "C86" H 7550 1600 50 0000 L CNN +F 1 "1uF" H 7550 1400 50 0000 L CNN +F 2 "0603" H 7500 1500 60 0001 C CNN + 1 7500 1500 + 1 0 0 -1 +$EndComp +$Comp +L C C87 +U 1 1 4C71C9C4 +P 7850 1500 +F 0 "C87" H 7900 1600 50 0000 L CNN +F 1 "1uF" H 7900 1400 50 0000 L CNN +F 2 "0603" H 7850 1500 60 0001 C CNN + 1 7850 1500 + 1 0 0 -1 +$EndComp +$Comp +L C C88 +U 1 1 4C71C9C3 +P 8200 1500 +F 0 "C88" H 8250 1600 50 0000 L CNN +F 1 "470nF" H 8250 1400 50 0000 L CNN +F 2 "0402" H 8200 1500 60 0001 C CNN + 1 8200 1500 + 1 0 0 -1 +$EndComp +$Comp +L MICROSMD075F F2 +U 1 1 4C71C9C1 +P 9400 1700 +F 0 "F2" V 9350 1900 60 0000 C CNN +F 1 "MICROSMD075F" V 9450 2250 60 0000 C CNN +F 2 "1210" H 9400 1700 60 0001 C CNN + 1 9400 1700 + 0 1 1 0 +$EndComp +$Comp +L V0402MHS03 V6 +U 1 1 4C71C9C0 +P 8400 3200 +F 0 "V6" H 8500 3000 60 0000 C CNN +F 1 "V0402MHS03" H 8450 3200 60 0000 C CNN +F 2 "0603" H 8400 3200 60 0001 C CNN + 1 8400 3200 + 0 1 1 0 +$EndComp +$Comp +L V0402MHS03 V5 +U 1 1 4C71C9BF +P 8050 3200 +F 0 "V5" H 8150 3000 60 0000 C CNN +F 1 "V0402MHS03" H 8100 3200 60 0000 C CNN +F 2 "0603" H 8050 3200 60 0001 C CNN + 1 8050 3200 + 0 1 1 0 +$EndComp +$Comp +L C C89 +U 1 1 4C71C9BE +P 10500 3250 +F 0 "C89" H 10350 3350 50 0000 L CNN +F 1 "4.7nF" H 10200 3150 50 0000 L CNN +F 2 "0402" H 10500 3250 60 0001 C CNN + 1 10500 3250 + 1 0 0 -1 +$EndComp +$Comp +L R R31 +U 1 1 4C71C9BD +P 10800 3250 +F 0 "R31" V 10880 3250 50 0000 C CNN +F 1 "1M" V 10800 3250 50 0000 C CNN +F 2 "0402" H 10800 3250 60 0001 C CNN + 1 10800 3250 + 1 0 0 -1 +$EndComp +Text HLabel 6650 2650 0 40 BiDi ~ 0 +USBB_SPD +Text HLabel 6650 2750 0 40 BiDi ~ 0 +USBB_OE_N +Text HLabel 6650 2850 0 40 BiDi ~ 0 +USBB_RCV +Text HLabel 6650 2950 0 40 BiDi ~ 0 +USBB_VP +Text HLabel 6650 3050 0 40 BiDi ~ 0 +USBB_VM +$Comp +L GND #PWR021 +U 1 1 4C71C9BC +P 10650 3750 +F 0 "#PWR021" H 10650 3750 30 0001 C CNN +F 1 "GND" H 10650 3680 30 0001 C CNN + 1 10650 3750 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR022 +U 1 1 4C71C9BB +P 7200 3800 +F 0 "#PWR022" H 7200 3800 30 0001 C CNN +F 1 "GND" H 7200 3730 30 0001 C CNN + 1 7200 3800 + 1 0 0 -1 +$EndComp +$Comp +L +2.5V #PWR023 +U 1 1 4C71C9BA +P 6600 2450 +F 0 "#PWR023" H 6600 2400 20 0001 C CNN +F 1 "+2.5V" H 6600 2550 30 0000 C CNN + 1 6600 2450 + 1 0 0 -1 +$EndComp +$Comp +L INDUCTOR L11 +U 1 1 4C71C9B9 +P 9600 3350 +F 0 "L11" V 9550 3350 40 0000 C CNN +F 1 "FB" V 9700 3350 40 0000 C CNN +F 2 "0603" H 9600 3350 60 0001 C CNN + 1 9600 3350 + 1 0 0 -1 +$EndComp +$Comp +L INDUCTOR L10 +U 1 1 4C71C9B8 +P 9400 2350 +F 0 "L10" V 9350 2350 40 0000 C CNN +F 1 "FB" V 9500 2350 40 0000 C CNN +F 2 "0603" H 9400 2350 60 0001 C CNN + 1 9400 2350 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR024 +U 1 1 4C71C9B7 +P 9400 1350 +F 0 "#PWR024" H 9400 1440 20 0001 C CNN +F 1 "+5V" H 9400 1440 30 0000 C CNN + 1 9400 1350 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR025 +U 1 1 4C71C9B6 +P 9600 3700 +F 0 "#PWR025" H 9600 3700 30 0001 C CNN +F 1 "GND" H 9600 3630 30 0001 C CNN + 1 9600 3700 + 1 0 0 -1 +$EndComp +$Comp +L +2.5V #PWR026 +U 1 1 4C71C9B5 +P 8200 1100 +F 0 "#PWR026" H 8200 1050 20 0001 C CNN +F 1 "+2.5V" H 8200 1200 30 0000 C CNN + 1 8200 1100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR027 +U 1 1 4C71C9B4 +P 7650 1850 +F 0 "#PWR027" H 7650 1850 30 0001 C CNN +F 1 "GND" H 7650 1780 30 0001 C CNN + 1 7650 1850 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR028 +U 1 1 4C71C9B3 +P 8200 1850 +F 0 "#PWR028" H 8200 1850 30 0001 C CNN +F 1 "GND" H 8200 1780 30 0001 C CNN + 1 8200 1850 + 1 0 0 -1 +$EndComp +Connection ~ 7700 1200 +Wire Wire Line + 7500 1200 7850 1200 +Wire Wire Line + 7500 1200 7500 1300 +Connection ~ 7650 1800 +Wire Wire Line + 7500 1800 7850 1800 +Wire Wire Line + 7500 1800 7500 1700 +Wire Wire Line + 8200 1850 8200 1700 +Wire Wire Line + 9600 3050 9600 2950 +Wire Wire Line + 9400 1400 9400 1350 +Connection ~ 7550 2550 +Wire Wire Line + 7450 2550 7550 2550 +Wire Wire Line + 7450 2650 7550 2650 +Wire Wire Line + 7550 2650 7550 2400 +Wire Wire Line + 6600 2450 6600 2550 +Wire Wire Line + 7200 3800 7200 3350 +Wire Wire Line + 7950 3700 7950 3600 +Wire Wire Line + 7950 2750 7950 2950 +Wire Wire Line + 6700 2950 6650 2950 +Wire Wire Line + 6700 2750 6650 2750 +Wire Wire Line + 8300 3700 6550 3700 +Wire Wire Line + 6700 3150 6550 3150 +Connection ~ 7200 3700 +Wire Wire Line + 9600 2950 9700 2950 +Connection ~ 10500 2850 +Wire Wire Line + 10350 2850 10500 2850 +Wire Wire Line + 10500 3050 10500 2650 +Wire Wire Line + 10500 2650 10350 2650 +Connection ~ 10500 2950 +Wire Wire Line + 9400 2650 9700 2650 +Connection ~ 7950 2750 +Wire Wire Line + 7450 2750 8650 2750 +Wire Wire Line + 8650 2750 8650 2850 +Wire Wire Line + 8650 2850 9700 2850 +Wire Wire Line + 7450 2850 8600 2850 +Wire Wire Line + 8600 2850 8600 2800 +Wire Wire Line + 8600 2800 8700 2800 +Wire Wire Line + 8700 2800 8700 2750 +Wire Wire Line + 8700 2750 9700 2750 +Connection ~ 8300 2850 +Wire Wire Line + 10350 2950 10800 2950 +Wire Wire Line + 10800 2950 10800 3000 +Wire Wire Line + 10500 3450 10500 3650 +Wire Wire Line + 10500 3650 10800 3650 +Wire Wire Line + 10800 3650 10800 3500 +Wire Wire Line + 10350 2750 10500 2750 +Connection ~ 10500 2750 +Wire Wire Line + 10650 3650 10650 3750 +Connection ~ 10650 3650 +Connection ~ 7950 3700 +Wire Wire Line + 6600 2550 6700 2550 +Wire Wire Line + 6700 2650 6650 2650 +Wire Wire Line + 6700 2850 6650 2850 +Wire Wire Line + 6700 3050 6650 3050 +Wire Wire Line + 8300 2850 8300 2950 +Wire Wire Line + 8300 3700 8300 3600 +Wire Wire Line + 6550 3150 6550 3700 +Wire Wire Line + 9400 1950 9400 2050 +Wire Wire Line + 9600 3650 9600 3700 +Wire Wire Line + 7650 1800 7650 1850 +Wire Wire Line + 7850 1800 7850 1700 +Wire Wire Line + 7850 1200 7850 1300 +Wire Wire Line + 7700 1200 7700 1100 +Wire Wire Line + 8200 1300 8200 1100 +$Comp +L +3.3V #PWR029 +U 1 1 4C71C9B2 +P 7550 2400 +F 0 "#PWR029" H 7550 2360 30 0001 C CNN +F 1 "+3.3V" H 7550 2510 30 0000 C CNN + 1 7550 2400 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR030 +U 1 1 4C71C9B1 +P 7700 1100 +F 0 "#PWR030" H 7700 1060 30 0001 C CNN +F 1 "+3.3V" H 7700 1210 30 0000 C CNN + 1 7700 1100 + 1 0 0 -1 +$EndComp +$Comp +L MIC2550-MLF U13 +U 1 1 4C71C9B0 +P 7050 2750 +F 0 "U13" H 6900 2250 60 0000 C CNN +F 1 "MIC2550-MLF" H 7050 3150 60 0000 C CNN +F 2 "MLF16" H 7050 2750 60 0001 C CNN + 1 7050 2750 + 1 0 0 -1 +$EndComp +$Comp L MIC2550-MLF U7 U 1 1 4C71BA25 P 2050 6450 @@ -80,37 +405,37 @@ F 2 "MLF16" H 2000 2750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR55 +L +3.3V #PWR031 U 1 1 4C695F50 P 2700 4600 -F 0 "#PWR55" H 2700 4560 30 0001 C CNN +F 0 "#PWR031" H 2700 4560 30 0001 C CNN F 1 "+3.3V" H 2700 4710 30 0000 C CNN 1 2700 4600 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR51 +L +3.3V #PWR032 U 1 1 4C695F4B P 2550 6100 -F 0 "#PWR51" H 2550 6060 30 0001 C CNN +F 0 "#PWR032" H 2550 6060 30 0001 C CNN F 1 "+3.3V" H 2550 6210 30 0000 C CNN 1 2550 6100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR53 +L +3.3V #PWR033 U 1 1 4C695F43 P 2650 1100 -F 0 "#PWR53" H 2650 1060 30 0001 C CNN +F 0 "#PWR033" H 2650 1060 30 0001 C CNN F 1 "+3.3V" H 2650 1210 30 0000 C CNN 1 2650 1100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR50 +L +3.3V #PWR034 U 1 1 4C695F3B P 2500 2400 -F 0 "#PWR50" H 2500 2360 30 0001 C CNN +F 0 "#PWR034" H 2500 2360 30 0001 C CNN F 1 "+3.3V" H 2500 2510 30 0000 C CNN 1 2500 2400 1 0 0 -1 @@ -234,8 +559,6 @@ Wire Wire Line 4550 2950 4550 3050 Wire Wire Line 4600 6750 4600 6650 -Wire Wire Line - 4400 5100 4400 5050 Connection ~ 2550 6250 Wire Wire Line 2450 6250 2550 6250 @@ -323,8 +646,6 @@ Wire Wire Line 3300 7400 3300 7300 Wire Wire Line 1550 6850 1550 7400 -Wire Wire Line - 4400 5650 4400 5750 Wire Wire Line 4600 7350 4600 7400 Wire Wire Line @@ -346,55 +667,55 @@ Connection ~ 2650 1200 Wire Wire Line 3200 5000 3200 4550 $Comp -L +2.5V #PWR58 +L +2.5V #PWR035 U 1 1 4C695DCD P 3200 4550 -F 0 "#PWR58" H 3200 4500 20 0001 C CNN +F 0 "#PWR035" H 3200 4500 20 0001 C CNN F 1 "+2.5V" H 3200 4650 30 0000 C CNN 1 3200 4550 1 0 0 -1 $EndComp $Comp -L GND #PWR59 +L GND #PWR036 U 1 1 4C695F0A P 3200 5550 -F 0 "#PWR59" H 3200 5550 30 0001 C CNN +F 0 "#PWR036" H 3200 5550 30 0001 C CNN F 1 "GND" H 3200 5480 30 0001 C CNN 1 3200 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR54 +L GND #PWR037 U 1 1 4C695F09 P 2650 5550 -F 0 "#PWR54" H 2650 5550 30 0001 C CNN +F 0 "#PWR037" H 2650 5550 30 0001 C CNN F 1 "GND" H 2650 5480 30 0001 C CNN 1 2650 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR57 +L GND #PWR038 U 1 1 4C695DFE P 3150 1850 -F 0 "#PWR57" H 3150 1850 30 0001 C CNN +F 0 "#PWR038" H 3150 1850 30 0001 C CNN F 1 "GND" H 3150 1780 30 0001 C CNN 1 3150 1850 1 0 0 -1 $EndComp $Comp -L GND #PWR52 +L GND #PWR039 U 1 1 4C695DF8 P 2600 1850 -F 0 "#PWR52" H 2600 1850 30 0001 C CNN +F 0 "#PWR039" H 2600 1850 30 0001 C CNN F 1 "GND" H 2600 1780 30 0001 C CNN 1 2600 1850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR56 +L +2.5V #PWR040 U 1 1 4C695DA7 P 3150 1100 -F 0 "#PWR56" H 3150 1050 20 0001 C CNN +F 0 "#PWR040" H 3150 1050 20 0001 C CNN F 1 "+2.5V" H 3150 1200 30 0000 C CNN 1 3150 1100 1 0 0 -1 @@ -427,15 +748,6 @@ F 1 "470nF" H 3250 5100 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L MICROSMD075F F2 -U 1 1 4C6552BA -P 4400 5400 -F 0 "F2" V 4350 5600 60 0000 C CNN -F 1 "MICROSMD075F" V 4450 5950 60 0000 C CNN - 1 4400 5400 - 0 1 1 0 -$EndComp -$Comp L V0402MHS03 V4 U 1 1 4C6552B9 P 3400 6900 @@ -482,28 +794,28 @@ USBD_VP Text HLabel 1650 6750 0 40 BiDi ~ 0 USBD_VM $Comp -L GND #PWR65 +L GND #PWR041 U 1 1 4C6552B5 P 5650 7450 -F 0 "#PWR65" H 5650 7450 30 0001 C CNN +F 0 "#PWR041" H 5650 7450 30 0001 C CNN F 1 "GND" H 5650 7380 30 0001 C CNN 1 5650 7450 1 0 0 -1 $EndComp $Comp -L GND #PWR49 +L GND #PWR042 U 1 1 4C6552B4 P 2200 7500 -F 0 "#PWR49" H 2200 7500 30 0001 C CNN +F 0 "#PWR042" H 2200 7500 30 0001 C CNN F 1 "GND" H 2200 7430 30 0001 C CNN 1 2200 7500 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR47 +L +2.5V #PWR043 U 1 1 4C6552B2 P 1600 6150 -F 0 "#PWR47" H 1600 6100 20 0001 C CNN +F 0 "#PWR043" H 1600 6100 20 0001 C CNN F 1 "+2.5V" H 1600 6250 30 0000 C CNN 1 1600 6150 1 0 0 -1 @@ -519,47 +831,28 @@ F 2 "0603" H 4600 7050 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L INDUCTOR L6 -U 1 1 4C6552B0 -P 4400 6050 -F 0 "L6" V 4350 6050 40 0000 C CNN -F 1 "FB" V 4500 6050 40 0000 C CNN -F 2 "0603" H 4400 6050 60 0001 C CNN - 1 4400 6050 - 1 0 0 -1 -$EndComp -$Comp -L +5V #PWR61 -U 1 1 4C6552AF -P 4400 5050 -F 0 "#PWR61" H 4400 5140 20 0001 C CNN -F 1 "+5V" H 4400 5140 30 0000 C CNN - 1 4400 5050 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR63 +L GND #PWR044 U 1 1 4C6552AE P 4600 7400 -F 0 "#PWR63" H 4600 7400 30 0001 C CNN +F 0 "#PWR044" H 4600 7400 30 0001 C CNN F 1 "GND" H 4600 7330 30 0001 C CNN 1 4600 7400 1 0 0 -1 $EndComp $Comp -L GND #PWR62 +L GND #PWR045 U 1 1 4C63F2B5 P 4550 3700 -F 0 "#PWR62" H 4550 3700 30 0001 C CNN +F 0 "#PWR045" H 4550 3700 30 0001 C CNN F 1 "GND" H 4550 3630 30 0001 C CNN 1 4550 3700 1 0 0 -1 $EndComp $Comp -L +5V #PWR60 +L +5V #PWR046 U 1 1 4C63F295 P 4350 1350 -F 0 "#PWR60" H 4350 1440 20 0001 C CNN +F 0 "#PWR046" H 4350 1440 20 0001 C CNN F 1 "+5V" H 4350 1440 30 0000 C CNN 1 4350 1350 1 0 0 -1 @@ -585,28 +878,28 @@ F 2 "0603" H 4550 3350 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR46 +L +2.5V #PWR047 U 1 1 4C63EC16 P 1550 2450 -F 0 "#PWR46" H 1550 2400 20 0001 C CNN +F 0 "#PWR047" H 1550 2400 20 0001 C CNN F 1 "+2.5V" H 1550 2550 30 0000 C CNN 1 1550 2450 1 0 0 -1 $EndComp $Comp -L GND #PWR48 +L GND #PWR048 U 1 1 4C63EA1B P 2150 3800 -F 0 "#PWR48" H 2150 3800 30 0001 C CNN +F 0 "#PWR048" H 2150 3800 30 0001 C CNN F 1 "GND" H 2150 3730 30 0001 C CNN 1 2150 3800 1 0 0 -1 $EndComp $Comp -L GND #PWR64 +L GND #PWR049 U 1 1 4C63E9FA P 5600 3750 -F 0 "#PWR64" H 5600 3750 30 0001 C CNN +F 0 "#PWR049" H 5600 3750 30 0001 C CNN F 1 "GND" H 5600 3680 30 0001 C CNN 1 5600 3750 1 0 0 -1 @@ -647,6 +940,7 @@ U 1 1 4C5F2CA7 P 3000 3200 F 0 "V1" H 3100 3000 60 0000 C CNN F 1 "V0402MHS03" H 3050 3200 60 0000 C CNN +F 2 "0603" H 3000 3200 60 0001 C CNN 1 3000 3200 0 1 1 0 $EndComp @@ -656,6 +950,7 @@ U 1 1 4C5F2CA3 P 3350 3200 F 0 "V2" H 3450 3000 60 0000 C CNN F 1 "V0402MHS03" H 3400 3200 60 0000 C CNN +F 2 "0603" H 3350 3200 60 0001 C CNN 1 3350 3200 0 1 1 0 $EndComp diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index e3e7416..3bf2849 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 07:03:34 PM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + id="g29302"> + id="ellipse29304" /> + id="g29306"> + id="ellipse29308" /> + id="g29310"> + id="ellipse29312" /> + id="g29314"> + + + + id="ellipse29320" /> + id="g29322"> + id="ellipse29324" /> - - - - - - + id="g29326"> + id="ellipse29328" /> + id="g29330"> + id="ellipse29332" /> - - - + id="g29334"> + id="ellipse29336" /> - - - + id="g29338"> + id="ellipse29340" /> + id="g29342"> + + + + id="ellipse29348" /> + id="g29350"> + id="ellipse29352" /> + id="g29354"> + id="ellipse29356" /> - - - - - - + id="g29358"> + id="ellipse29360" /> + id="g29362"> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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id="ellipse29756" /> + id="g29758"> + id="ellipse29760" /> + id="g29762"> + id="ellipse29764" /> + id="g29766"> + id="ellipse29768" /> + id="g29770"> + id="ellipse29772" /> + id="g29774"> + id="ellipse29776" /> + id="g29778"> + id="ellipse29780" /> + id="g29782"> + id="ellipse29784" /> + id="g29786"> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + id="ellipse29928" /> - - - - - - + id="g29930"> + id="ellipse29932" /> + id="g29934"> + + + + id="ellipse29940" /> + id="g29942"> + id="ellipse29944" /> + id="g29946"> + id="ellipse29948" /> + id="g29950"> + + + + + + + + + + id="ellipse29964" /> + id="g29966"> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + id="ellipse30084" /> + id="g30086"> + id="ellipse30088" /> + id="g30090"> + id="ellipse30092" /> + id="g30094"> + id="ellipse30096" /> + id="g30098"> + id="ellipse30100" /> + id="g30102"> + id="ellipse30104" /> + id="g30106"> + id="ellipse30108" /> diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index df477b6..4eed0f1 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Sun 22 Aug 2010 07:03:34 PM COT +EESchema-LIBRARY Version 2.3 Date: Sun 22 Aug 2010 08:15:24 PM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index ee7d5a3..c12253c 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Sun 22 Aug 2010 07:04:51 PM COT +PCBNEW-BOARD Version 1 date Sun 22 Aug 2010 08:28:09 PM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -6,15 +6,15 @@ $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 13FF801F -Links 685 -NoConn 468 -Di 45200 12883 82198 50668 +Links 704 +NoConn 487 +Di 45200 12777 75973 50668 Ndraw 7 -Ntrack 1912 +Ntrack 1915 Nzone 0 BoardThickness 630 -Nmodule 164 -Nnets 258 +Nmodule 173 +Nnets 261 $EndGENERAL $SHEETDESCR @@ -90,915 +90,915 @@ Na 5 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DBG_PRG17" +Na 6 "/DBG_PRG/FPGA_TCK" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DBG_PRG18" +Na 7 "/DBG_PRG/FPGA_TDI" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DBG_PRG19" +Na 8 "/DBG_PRG/FPGA_TDO" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DBG_PRG20" +Na 9 "/DBG_PRG/FPGA_TMS" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Ban101" +Na 10 "/DDR_Banks/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Ban113" +Na 11 "/DDR_Banks/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Ban115" +Na 12 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Ban116" +Na 13 "/DDR_Banks/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Ban130" +Na 14 "/DDR_Banks/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Ban131" +Na 15 "/DDR_Banks/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Ban138" +Na 16 "/DDR_Banks/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Ban162" +Na 17 "/DDR_Banks/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Ban178" +Na 18 "/DDR_Banks/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Ban24" +Na 19 "/DDR_Banks/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Ban25" +Na 20 "/DDR_Banks/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Ban29" +Na 21 "/DDR_Banks/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Ban33" +Na 22 "/DDR_Banks/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Ban39" +Na 23 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Ban41" +Na 24 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Ban5" +Na 25 "/DDR_Banks/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Ban53" +Na 26 "/DDR_Banks/M0_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Ban54" +Na 27 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Ban6" +Na 28 "/DDR_Banks/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Ban62" +Na 29 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Ban70" +Na 30 "/DDR_Banks/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Ban79" +Na 31 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Ban80" +Na 32 "/DDR_Banks/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M0_A4" +Na 33 "/DDR_Banks/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M0_A7" +Na 34 "/DDR_Banks/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_A2" +Na 35 "/DDR_Banks/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/DDR_Banks/M1_A4" +Na 36 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/DDR_Banks/M1_A7" +Na 37 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M1_A9" +Na 38 "/DDR_Banks/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/Etherne1" +Na 39 "/DDR_Banks/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Etherne13" +Na 40 "/DDR_Banks/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Etherne14" +Na 41 "/DDR_Banks/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Etherne15" +Na 42 "/DDR_Banks/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Etherne16" +Na 43 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Etherne180" +Na 44 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Etherne182" +Na 45 "/DDR_Banks/M1_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Etherne185" +Na 46 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Etherne194" +Na 47 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Etherne195" +Na 48 "/Ethernet_Phy/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Etherne196" +Na 49 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Etherne2" +Na 50 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Etherne200" +Na 51 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/Etherne202" +Na 52 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/Etherne209" +Na 53 "/Ethernet_Phy/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/Etherne21" +Na 54 "/Ethernet_Phy/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/Etherne22" +Na 55 "/Ethernet_Phy/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/Etherne23" +Na 56 "/Ethernet_Phy/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/Etherne3" +Na 57 "/Ethernet_Phy/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/Etherne4" +Na 58 "/Ethernet_Phy/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Sp100" +Na 59 "/Ethernet_Phy/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Sp102" +Na 60 "/Ethernet_Phy/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Sp103" +Na 61 "/Ethernet_Phy/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Sp104" +Na 62 "/Ethernet_Phy/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Sp105" +Na 63 "/Ethernet_Phy/MAG_RX+" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Sp106" +Na 64 "/Ethernet_Phy/MAG_RX-" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Sp107" +Na 65 "/Ethernet_Phy/MAG_SHIELD" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Sp108" +Na 66 "/Ethernet_Phy/MAG_TX+" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Sp109" +Na 67 "/Ethernet_Phy/MAG_TX-" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Sp110" +Na 68 "/FPGA_Spartan6/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Sp111" +Na 69 "/FPGA_Spartan6/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Sp112" +Na 70 "/FPGA_Spartan6/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Sp114" +Na 71 "/FPGA_Spartan6/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Sp117" +Na 72 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Sp118" +Na 73 "/FPGA_Spartan6/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Sp119" +Na 74 "/FPGA_Spartan6/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Sp120" +Na 75 "/FPGA_Spartan6/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Sp121" +Na 76 "/FPGA_Spartan6/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Sp122" +Na 77 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Sp123" +Na 78 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Sp124" +Na 79 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Sp125" +Na 80 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Sp126" +Na 81 "/FPGA_Spartan6/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Sp127" +Na 82 "/FPGA_Spartan6/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Sp128" +Na 83 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Sp129" +Na 84 "/FPGA_Spartan6/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Sp132" +Na 85 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Sp133" +Na 86 "/FPGA_Spartan6/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Sp134" +Na 87 "/FPGA_Spartan6/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Sp135" +Na 88 "/FPGA_Spartan6/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Sp136" +Na 89 "/FPGA_Spartan6/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Sp137" +Na 90 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Sp139" +Na 91 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Sp140" +Na 92 "/FPGA_Spartan6/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Sp141" +Na 93 "/FPGA_Spartan6/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Sp142" +Na 94 "/FPGA_Spartan6/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Sp143" +Na 95 "/FPGA_Spartan6/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Sp144" +Na 96 "/FPGA_Spartan6/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Sp145" +Na 97 "/FPGA_Spartan6/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Sp146" +Na 98 "/FPGA_Spartan6/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Sp147" +Na 99 "/FPGA_Spartan6/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Sp148" +Na 100 "/FPGA_Spartan6/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Sp149" +Na 101 "/FPGA_Spartan6/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Sp150" +Na 102 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Sp151" +Na 103 "/FPGA_Spartan6/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Sp152" +Na 104 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Sp153" +Na 105 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Sp154" +Na 106 "/FPGA_Spartan6/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Sp155" +Na 107 "/FPGA_Spartan6/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Sp156" +Na 108 "/FPGA_Spartan6/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Sp157" +Na 109 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Sp158" +Na 110 "/FPGA_Spartan6/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Sp159" +Na 111 "/FPGA_Spartan6/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Sp160" +Na 112 "/FPGA_Spartan6/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Sp161" +Na 113 "/FPGA_Spartan6/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Sp163" +Na 114 "/FPGA_Spartan6/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Sp164" +Na 115 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Sp165" +Na 116 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Sp166" +Na 117 "/FPGA_Spartan6/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA_Sp167" +Na 118 "/FPGA_Spartan6/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Sp168" +Na 119 "/FPGA_Spartan6/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Sp169" +Na 120 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Sp170" +Na 121 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Sp171" +Na 122 "/FPGA_Spartan6/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Sp172" +Na 123 "/FPGA_Spartan6/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Sp173" +Na 124 "/FPGA_Spartan6/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Sp174" +Na 125 "/FPGA_Spartan6/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Sp175" +Na 126 "/FPGA_Spartan6/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Sp176" +Na 127 "/FPGA_Spartan6/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Sp177" +Na 128 "/FPGA_Spartan6/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/FPGA_Sp179" +Na 129 "/FPGA_Spartan6/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/FPGA_Sp181" +Na 130 "/FPGA_Spartan6/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/FPGA_Sp183" +Na 131 "/FPGA_Spartan6/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/FPGA_Sp184" +Na 132 "/FPGA_Spartan6/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/FPGA_Sp186" +Na 133 "/FPGA_Spartan6/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/FPGA_Sp187" +Na 134 "/FPGA_Spartan6/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/FPGA_Sp188" +Na 135 "/FPGA_Spartan6/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/FPGA_Sp190" +Na 136 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/FPGA_Sp191" +Na 137 "/FPGA_Spartan6/R_M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/FPGA_Sp192" +Na 138 "/FPGA_Spartan6/R_M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/FPGA_Sp193" +Na 139 "/FPGA_Spartan6/R_M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/FPGA_Sp197" +Na 140 "/FPGA_Spartan6/R_M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/FPGA_Sp198" +Na 141 "/FPGA_Spartan6/R_M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/FPGA_Sp199" +Na 142 "/FPGA_Spartan6/R_M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/FPGA_Sp201" +Na 143 "/FPGA_Spartan6/R_M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/FPGA_Sp203" +Na 144 "/FPGA_Spartan6/R_M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/FPGA_Sp204" +Na 145 "/FPGA_Spartan6/R_M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/FPGA_Sp206" +Na 146 "/FPGA_Spartan6/R_M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/FPGA_Sp210" +Na 147 "/FPGA_Spartan6/R_M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/FPGA_Sp211" +Na 148 "/FPGA_Spartan6/R_M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/FPGA_Sp212" +Na 149 "/FPGA_Spartan6/R_M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/FPGA_Sp216" +Na 150 "/FPGA_Spartan6/R_M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/FPGA_Sp217" +Na 151 "/FPGA_Spartan6/R_M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/FPGA_Sp218" +Na 152 "/FPGA_Spartan6/R_M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/FPGA_Sp219" +Na 153 "/FPGA_Spartan6/R_M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/FPGA_Sp220" +Na 154 "/FPGA_Spartan6/R_M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/FPGA_Sp26" +Na 155 "/FPGA_Spartan6/R_M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/FPGA_Sp27" +Na 156 "/FPGA_Spartan6/R_M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/FPGA_Sp28" +Na 157 "/FPGA_Spartan6/R_M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/FPGA_Sp30" +Na 158 "/FPGA_Spartan6/R_M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/FPGA_Sp31" +Na 159 "/FPGA_Spartan6/R_M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/FPGA_Sp32" +Na 160 "/FPGA_Spartan6/R_M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/FPGA_Sp34" +Na 161 "/FPGA_Spartan6/R_M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/FPGA_Sp35" +Na 162 "/FPGA_Spartan6/R_M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/FPGA_Sp36" +Na 163 "/FPGA_Spartan6/R_M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/FPGA_Sp37" +Na 164 "/FPGA_Spartan6/R_M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/FPGA_Sp38" +Na 165 "/FPGA_Spartan6/R_M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/FPGA_Sp40" +Na 166 "/FPGA_Spartan6/R_M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/FPGA_Sp42" +Na 167 "/FPGA_Spartan6/R_M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/FPGA_Sp43" +Na 168 "/FPGA_Spartan6/R_M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/FPGA_Sp44" +Na 169 "/FPGA_Spartan6/R_M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/FPGA_Sp45" +Na 170 "/FPGA_Spartan6/R_M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/FPGA_Sp46" +Na 171 "/FPGA_Spartan6/R_M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/FPGA_Sp47" +Na 172 "/FPGA_Spartan6/R_M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/FPGA_Sp48" +Na 173 "/FPGA_Spartan6/R_M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/FPGA_Sp49" +Na 174 "/FPGA_Spartan6/R_M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/FPGA_Sp50" +Na 175 "/FPGA_Spartan6/R_M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/FPGA_Sp51" +Na 176 "/FPGA_Spartan6/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/FPGA_Sp52" +Na 177 "/FPGA_Spartan6/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/FPGA_Sp55" +Na 178 "/FPGA_Spartan6/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/FPGA_Sp56" +Na 179 "/FPGA_Spartan6/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 180 "/FPGA_Sp57" +Na 180 "/FPGA_Spartan6/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/FPGA_Sp58" +Na 181 "/FPGA_Spartan6/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/FPGA_Sp59" +Na 182 "/FPGA_Spartan6/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/FPGA_Sp60" +Na 183 "/FPGA_Spartan6/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/FPGA_Sp61" +Na 184 "/FPGA_Spartan6/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "/FPGA_Sp63" +Na 185 "/FPGA_Spartan6/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "/FPGA_Sp64" +Na 186 "/FPGA_Spartan6/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "/FPGA_Sp65" +Na 187 "/FPGA_Spartan6/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "/FPGA_Sp66" +Na 188 "/FPGA_Spartan6/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "/FPGA_Sp67" +Na 189 "/FPGA_Spartan6/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "/FPGA_Sp68" +Na 190 "/FPGA_Spartan6/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "/FPGA_Sp69" +Na 191 "/FPGA_Spartan6/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "/FPGA_Sp71" +Na 192 "/FPGA_Spartan6/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "/FPGA_Sp72" +Na 193 "/FPGA_Spartan6/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "/FPGA_Sp73" +Na 194 "/FPGA_Spartan6/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "/FPGA_Sp74" +Na 195 "/FPGA_Spartan6/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "/FPGA_Sp75" +Na 196 "/FPGA_Spartan6/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "/FPGA_Sp76" +Na 197 "/FPGA_Spartan6/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "/FPGA_Sp77" +Na 198 "/FPGA_Spartan6/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "/FPGA_Sp78" +Na 199 "/FPGA_Spartan6/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "/FPGA_Sp81" +Na 200 "/FPGA_Spartan6/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 201 "/FPGA_Sp82" +Na 201 "/FPGA_Spartan6/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 202 "/FPGA_Sp83" +Na 202 "/FPGA_Spartan6/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 203 "/FPGA_Sp84" +Na 203 "/FPGA_Spartan6/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 204 "/FPGA_Sp85" +Na 204 "/FPGA_Spartan6/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 205 "/FPGA_Sp86" +Na 205 "/FPGA_Spartan6/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 206 "/FPGA_Sp87" +Na 206 "/FPGA_Spartan6/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 207 "/FPGA_Sp88" +Na 207 "/FPGA_Spartan6/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 208 "/FPGA_Sp89" +Na 208 "/FPGA_Spartan6/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 209 "/FPGA_Sp9" +Na 209 "/FPGA_Spartan6/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 210 "/FPGA_Sp90" +Na 210 "/FPGA_Spartan6/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 211 "/FPGA_Sp91" +Na 211 "/FPGA_Spartan6/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 212 "/FPGA_Sp92" +Na 212 "/FPGA_Spartan6/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 213 "/FPGA_Sp93" +Na 213 "/FPGA_Spartan6/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 214 "/FPGA_Sp94" +Na 214 "/FPGA_Spartan6/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 215 "/FPGA_Sp95" +Na 215 "/FPGA_Spartan6/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 216 "/FPGA_Sp96" +Na 216 "/FPGA_Spartan6/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 217 "/FPGA_Sp97" +Na 217 "/FPGA_Spartan6/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 218 "/FPGA_Sp98" +Na 218 "/FPGA_Spartan6/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 219 "/FPGA_Sp99" +Na 219 "/FPGA_Spartan6/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 220 "/Non_vol10" +Na 220 "/Non_volatile_memories/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 221 "/Non_vol11" +Na 221 "/Non_volatile_memories/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 222 "/Non_vol12" +Na 222 "/Non_volatile_memories/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 223 "/Non_vol189" +Na 223 "/Non_volatile_memories/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 224 "/Non_vol205" +Na 224 "/Non_volatile_memories/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 225 "/Non_vol207" +Na 225 "/Non_volatile_memories/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 226 "/Non_vol208" +Na 226 "/Non_volatile_memories/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 227 "/Non_vol213" +Na 227 "/Non_volatile_memories/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 228 "/Non_vol214" +Na 228 "/Non_volatile_memories/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 229 "/Non_vol215" +Na 229 "/Non_volatile_memories/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 230 "/Non_vol7" +Na 230 "/Non_volatile_memories/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 231 "/Non_vol8" +Na 231 "/USB/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 232 "/USB/USBA_OE_N" +Na 232 "/USB/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 233 "/USB/USBA_SPD" +Na 233 "/USB/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT @@ -1010,91 +1010,103 @@ Na 235 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 236 "N-000127" +Na 236 "N-000267" St ~ $EndEQUIPOT $EQUIPOT -Na 237 "N-000132" +Na 237 "N-000390" St ~ $EndEQUIPOT $EQUIPOT -Na 238 "N-000393" +Na 238 "N-000401" St ~ $EndEQUIPOT $EQUIPOT -Na 239 "N-000394" +Na 239 "N-000405" St ~ $EndEQUIPOT $EQUIPOT -Na 240 "N-000395" +Na 240 "N-000406" St ~ $EndEQUIPOT $EQUIPOT -Na 241 "N-000414" +Na 241 "N-000415" St ~ $EndEQUIPOT $EQUIPOT -Na 242 "N-000415" +Na 242 "N-000417" St ~ $EndEQUIPOT $EQUIPOT -Na 243 "N-000419" +Na 243 "N-000422" St ~ $EndEQUIPOT $EQUIPOT -Na 244 "N-000420" +Na 244 "N-000427" St ~ $EndEQUIPOT $EQUIPOT -Na 245 "N-000421" +Na 245 "N-000428" St ~ $EndEQUIPOT $EQUIPOT -Na 246 "N-000422" +Na 246 "N-000429" St ~ $EndEQUIPOT $EQUIPOT -Na 247 "N-000423" +Na 247 "N-000430" St ~ $EndEQUIPOT $EQUIPOT -Na 248 "N-000429" +Na 248 "N-000431" St ~ $EndEQUIPOT $EQUIPOT -Na 249 "N-000430" +Na 249 "N-000432" St ~ $EndEQUIPOT $EQUIPOT -Na 250 "N-000431" +Na 250 "N-000433" St ~ $EndEQUIPOT $EQUIPOT -Na 251 "N-000432" +Na 251 "N-000435" St ~ $EndEQUIPOT $EQUIPOT -Na 252 "N-000433" +Na 252 "N-000440" St ~ $EndEQUIPOT $EQUIPOT -Na 253 "N-000434" +Na 253 "N-000441" St ~ $EndEQUIPOT $EQUIPOT -Na 254 "N-000435" +Na 254 "N-000442" St ~ $EndEQUIPOT $EQUIPOT -Na 255 "N-000445" +Na 255 "N-000443" St ~ $EndEQUIPOT $EQUIPOT -Na 256 "N-000464" +Na 256 "N-000444" St ~ $EndEQUIPOT $EQUIPOT -Na 257 "VCCO2" +Na 257 "N-000445" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 258 "N-000455" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 259 "N-000474" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 260 "VCCO2" St ~ $EndEQUIPOT $NCLASS @@ -1107,256 +1119,259 @@ ViaDrill 79 uViaDia 197 uViaDrill 79 AddNet "" -AddNet "/DBG_PRG17" -AddNet "/DBG_PRG18" -AddNet "/DBG_PRG19" -AddNet "/DBG_PRG20" -AddNet "/DDR_Ban101" -AddNet "/DDR_Ban113" -AddNet "/DDR_Ban115" -AddNet "/DDR_Ban116" -AddNet "/DDR_Ban130" -AddNet "/DDR_Ban131" -AddNet "/DDR_Ban138" -AddNet "/DDR_Ban162" -AddNet "/DDR_Ban178" -AddNet "/DDR_Ban24" -AddNet "/DDR_Ban25" -AddNet "/DDR_Ban29" -AddNet "/DDR_Ban33" -AddNet "/DDR_Ban39" -AddNet "/DDR_Ban41" -AddNet "/DDR_Ban5" -AddNet "/DDR_Ban53" -AddNet "/DDR_Ban54" -AddNet "/DDR_Ban6" -AddNet "/DDR_Ban62" -AddNet "/DDR_Ban70" -AddNet "/DDR_Ban79" -AddNet "/DDR_Ban80" -AddNet "/DDR_Banks/M0_A4" +AddNet "/DBG_PRG/FPGA_TCK" +AddNet "/DBG_PRG/FPGA_TDI" +AddNet "/DBG_PRG/FPGA_TDO" +AddNet "/DBG_PRG/FPGA_TMS" +AddNet "/DDR_Banks/M0_A0" +AddNet "/DDR_Banks/M0_A5" AddNet "/DDR_Banks/M0_A7" -AddNet "/DDR_Banks/M1_A2" +AddNet "/DDR_Banks/M0_A9" +AddNet "/DDR_Banks/M0_BA1" +AddNet "/DDR_Banks/M0_CLK" +AddNet "/DDR_Banks/M0_DQ1" +AddNet "/DDR_Banks/M0_DQ10" +AddNet "/DDR_Banks/M0_DQ12" +AddNet "/DDR_Banks/M0_DQ14" +AddNet "/DDR_Banks/M0_DQ15" +AddNet "/DDR_Banks/M0_DQ5" +AddNet "/DDR_Banks/M0_DQ8" +AddNet "/DDR_Banks/M0_LDM" +AddNet "/DDR_Banks/M0_LDQS" +AddNet "/DDR_Banks/M0_RAS#" +AddNet "/DDR_Banks/M0_VREF" +AddNet "/DDR_Banks/M0_WE#" +AddNet "/DDR_Banks/M1_A11" +AddNet "/DDR_Banks/M1_A12" AddNet "/DDR_Banks/M1_A4" +AddNet "/DDR_Banks/M1_A5" +AddNet "/DDR_Banks/M1_A6" AddNet "/DDR_Banks/M1_A7" -AddNet "/DDR_Banks/M1_A9" -AddNet "/Etherne1" -AddNet "/Etherne13" -AddNet "/Etherne14" -AddNet "/Etherne15" -AddNet "/Etherne16" -AddNet "/Etherne180" -AddNet "/Etherne182" -AddNet "/Etherne185" -AddNet "/Etherne194" -AddNet "/Etherne195" -AddNet "/Etherne196" -AddNet "/Etherne2" -AddNet "/Etherne200" -AddNet "/Etherne202" -AddNet "/Etherne209" -AddNet "/Etherne21" -AddNet "/Etherne22" -AddNet "/Etherne23" -AddNet "/Etherne3" -AddNet "/Etherne4" -AddNet "/FPGA_Sp100" -AddNet "/FPGA_Sp102" -AddNet "/FPGA_Sp103" -AddNet "/FPGA_Sp104" -AddNet "/FPGA_Sp105" -AddNet "/FPGA_Sp106" -AddNet "/FPGA_Sp107" -AddNet "/FPGA_Sp108" -AddNet "/FPGA_Sp109" -AddNet "/FPGA_Sp110" -AddNet "/FPGA_Sp111" -AddNet "/FPGA_Sp112" -AddNet "/FPGA_Sp114" -AddNet "/FPGA_Sp117" -AddNet "/FPGA_Sp118" -AddNet "/FPGA_Sp119" -AddNet "/FPGA_Sp120" -AddNet "/FPGA_Sp121" -AddNet "/FPGA_Sp122" -AddNet "/FPGA_Sp123" -AddNet "/FPGA_Sp124" -AddNet "/FPGA_Sp125" -AddNet "/FPGA_Sp126" -AddNet "/FPGA_Sp127" -AddNet "/FPGA_Sp128" -AddNet "/FPGA_Sp129" -AddNet "/FPGA_Sp132" -AddNet "/FPGA_Sp133" -AddNet "/FPGA_Sp134" -AddNet "/FPGA_Sp135" -AddNet "/FPGA_Sp136" -AddNet "/FPGA_Sp137" -AddNet "/FPGA_Sp139" -AddNet "/FPGA_Sp140" -AddNet "/FPGA_Sp141" -AddNet "/FPGA_Sp142" -AddNet "/FPGA_Sp143" -AddNet "/FPGA_Sp144" -AddNet "/FPGA_Sp145" -AddNet "/FPGA_Sp146" -AddNet "/FPGA_Sp147" -AddNet "/FPGA_Sp148" -AddNet "/FPGA_Sp149" -AddNet "/FPGA_Sp150" -AddNet "/FPGA_Sp151" -AddNet "/FPGA_Sp152" -AddNet "/FPGA_Sp153" -AddNet "/FPGA_Sp154" -AddNet "/FPGA_Sp155" -AddNet "/FPGA_Sp156" -AddNet "/FPGA_Sp157" -AddNet "/FPGA_Sp158" -AddNet "/FPGA_Sp159" -AddNet "/FPGA_Sp160" -AddNet "/FPGA_Sp161" -AddNet "/FPGA_Sp163" -AddNet "/FPGA_Sp164" -AddNet "/FPGA_Sp165" -AddNet "/FPGA_Sp166" -AddNet "/FPGA_Sp167" -AddNet "/FPGA_Sp168" -AddNet "/FPGA_Sp169" -AddNet "/FPGA_Sp170" -AddNet "/FPGA_Sp171" -AddNet "/FPGA_Sp172" -AddNet "/FPGA_Sp173" -AddNet "/FPGA_Sp174" -AddNet "/FPGA_Sp175" -AddNet "/FPGA_Sp176" -AddNet "/FPGA_Sp177" -AddNet "/FPGA_Sp179" -AddNet "/FPGA_Sp181" -AddNet "/FPGA_Sp183" -AddNet "/FPGA_Sp184" -AddNet "/FPGA_Sp186" -AddNet "/FPGA_Sp187" -AddNet "/FPGA_Sp188" -AddNet "/FPGA_Sp190" -AddNet "/FPGA_Sp191" -AddNet "/FPGA_Sp192" -AddNet "/FPGA_Sp193" -AddNet "/FPGA_Sp197" -AddNet "/FPGA_Sp198" -AddNet "/FPGA_Sp199" -AddNet "/FPGA_Sp201" -AddNet "/FPGA_Sp203" -AddNet "/FPGA_Sp204" -AddNet "/FPGA_Sp206" -AddNet "/FPGA_Sp210" -AddNet "/FPGA_Sp211" -AddNet "/FPGA_Sp212" -AddNet "/FPGA_Sp216" -AddNet "/FPGA_Sp217" -AddNet "/FPGA_Sp218" -AddNet "/FPGA_Sp219" -AddNet "/FPGA_Sp220" -AddNet "/FPGA_Sp26" -AddNet "/FPGA_Sp27" -AddNet "/FPGA_Sp28" -AddNet "/FPGA_Sp30" -AddNet "/FPGA_Sp31" -AddNet "/FPGA_Sp32" -AddNet "/FPGA_Sp34" -AddNet "/FPGA_Sp35" -AddNet "/FPGA_Sp36" -AddNet "/FPGA_Sp37" -AddNet "/FPGA_Sp38" -AddNet "/FPGA_Sp40" -AddNet "/FPGA_Sp42" -AddNet "/FPGA_Sp43" -AddNet "/FPGA_Sp44" -AddNet "/FPGA_Sp45" -AddNet "/FPGA_Sp46" -AddNet "/FPGA_Sp47" -AddNet "/FPGA_Sp48" -AddNet "/FPGA_Sp49" -AddNet "/FPGA_Sp50" -AddNet "/FPGA_Sp51" -AddNet "/FPGA_Sp52" -AddNet "/FPGA_Sp55" -AddNet "/FPGA_Sp56" -AddNet "/FPGA_Sp57" -AddNet "/FPGA_Sp58" -AddNet "/FPGA_Sp59" -AddNet "/FPGA_Sp60" -AddNet "/FPGA_Sp61" -AddNet "/FPGA_Sp63" -AddNet "/FPGA_Sp64" -AddNet "/FPGA_Sp65" -AddNet "/FPGA_Sp66" -AddNet "/FPGA_Sp67" -AddNet "/FPGA_Sp68" -AddNet "/FPGA_Sp69" -AddNet "/FPGA_Sp71" -AddNet "/FPGA_Sp72" -AddNet "/FPGA_Sp73" -AddNet "/FPGA_Sp74" -AddNet "/FPGA_Sp75" -AddNet "/FPGA_Sp76" -AddNet "/FPGA_Sp77" -AddNet "/FPGA_Sp78" -AddNet "/FPGA_Sp81" -AddNet "/FPGA_Sp82" -AddNet "/FPGA_Sp83" -AddNet "/FPGA_Sp84" -AddNet "/FPGA_Sp85" -AddNet "/FPGA_Sp86" -AddNet "/FPGA_Sp87" -AddNet "/FPGA_Sp88" -AddNet "/FPGA_Sp89" -AddNet "/FPGA_Sp9" -AddNet "/FPGA_Sp90" -AddNet "/FPGA_Sp91" -AddNet "/FPGA_Sp92" -AddNet "/FPGA_Sp93" -AddNet "/FPGA_Sp94" -AddNet "/FPGA_Sp95" -AddNet "/FPGA_Sp96" -AddNet "/FPGA_Sp97" -AddNet "/FPGA_Sp98" -AddNet "/FPGA_Sp99" -AddNet "/Non_vol10" -AddNet "/Non_vol11" -AddNet "/Non_vol12" -AddNet "/Non_vol189" -AddNet "/Non_vol205" -AddNet "/Non_vol207" -AddNet "/Non_vol208" -AddNet "/Non_vol213" -AddNet "/Non_vol214" -AddNet "/Non_vol215" -AddNet "/Non_vol7" -AddNet "/Non_vol8" -AddNet "/USB/USBA_OE_N" +AddNet "/DDR_Banks/M1_BA0" +AddNet "/DDR_Banks/M1_CKE" +AddNet "/DDR_Banks/M1_CLK" +AddNet "/DDR_Banks/M1_CLK#" +AddNet "/DDR_Banks/M1_DQ12" +AddNet "/DDR_Banks/M1_DQ13" +AddNet "/DDR_Banks/M1_DQ2" +AddNet "/DDR_Banks/M1_DQ7" +AddNet "/DDR_Banks/M1_DQ8" +AddNet "/DDR_Banks/M1_RAS#" +AddNet "/DDR_Banks/M1_UDM" +AddNet "/DDR_Banks/M1_VREF" +AddNet "/Ethernet_Phy/ETH_A1.8V" +AddNet "/Ethernet_Phy/ETH_A3.3V" +AddNet "/Ethernet_Phy/ETH_CLK" +AddNet "/Ethernet_Phy/ETH_INT" +AddNet "/Ethernet_Phy/ETH_LED0" +AddNet "/Ethernet_Phy/ETH_LED1" +AddNet "/Ethernet_Phy/ETH_PLL1.8V" +AddNet "/Ethernet_Phy/ETH_RXC" +AddNet "/Ethernet_Phy/ETH_RXD0" +AddNet "/Ethernet_Phy/ETH_RXD2" +AddNet "/Ethernet_Phy/ETH_RXER" +AddNet "/Ethernet_Phy/ETH_TXC" +AddNet "/Ethernet_Phy/ETH_TXD0" +AddNet "/Ethernet_Phy/ETH_TXD2" +AddNet "/Ethernet_Phy/ETH_TXD3" +AddNet "/Ethernet_Phy/ETH_TXEN" +AddNet "/Ethernet_Phy/ETH_TXER" +AddNet "/Ethernet_Phy/MAG_RX+" +AddNet "/Ethernet_Phy/MAG_RX-" +AddNet "/Ethernet_Phy/MAG_SHIELD" +AddNet "/Ethernet_Phy/MAG_TX+" +AddNet "/Ethernet_Phy/MAG_TX-" +AddNet "/FPGA_Spartan6/ETH_COL" +AddNet "/FPGA_Spartan6/ETH_CRS" +AddNet "/FPGA_Spartan6/ETH_MDC" +AddNet "/FPGA_Spartan6/ETH_MDIO" +AddNet "/FPGA_Spartan6/ETH_RESET_N" +AddNet "/FPGA_Spartan6/ETH_RXD1" +AddNet "/FPGA_Spartan6/ETH_RXD3" +AddNet "/FPGA_Spartan6/ETH_RXDV" +AddNet "/FPGA_Spartan6/ETH_TXD1" +AddNet "/FPGA_Spartan6/M0_A1" +AddNet "/FPGA_Spartan6/M0_A10" +AddNet "/FPGA_Spartan6/M0_A11" +AddNet "/FPGA_Spartan6/M0_A12" +AddNet "/FPGA_Spartan6/M0_A2" +AddNet "/FPGA_Spartan6/M0_A3" +AddNet "/FPGA_Spartan6/M0_A4" +AddNet "/FPGA_Spartan6/M0_A6" +AddNet "/FPGA_Spartan6/M0_A8" +AddNet "/FPGA_Spartan6/M0_BA0" +AddNet "/FPGA_Spartan6/M0_CAS#" +AddNet "/FPGA_Spartan6/M0_CKE" +AddNet "/FPGA_Spartan6/M0_CLK#" +AddNet "/FPGA_Spartan6/M0_DQ0" +AddNet "/FPGA_Spartan6/M0_DQ11" +AddNet "/FPGA_Spartan6/M0_DQ13" +AddNet "/FPGA_Spartan6/M0_DQ2" +AddNet "/FPGA_Spartan6/M0_DQ3" +AddNet "/FPGA_Spartan6/M0_DQ4" +AddNet "/FPGA_Spartan6/M0_DQ6" +AddNet "/FPGA_Spartan6/M0_DQ7" +AddNet "/FPGA_Spartan6/M0_DQ9" +AddNet "/FPGA_Spartan6/M0_UDM" +AddNet "/FPGA_Spartan6/M0_UDQS" +AddNet "/FPGA_Spartan6/M1_A0" +AddNet "/FPGA_Spartan6/M1_A1" +AddNet "/FPGA_Spartan6/M1_A10" +AddNet "/FPGA_Spartan6/M1_A2" +AddNet "/FPGA_Spartan6/M1_A3" +AddNet "/FPGA_Spartan6/M1_A8" +AddNet "/FPGA_Spartan6/M1_A9" +AddNet "/FPGA_Spartan6/M1_BA1" +AddNet "/FPGA_Spartan6/M1_CAS#" +AddNet "/FPGA_Spartan6/M1_CS#" +AddNet "/FPGA_Spartan6/M1_DQ0" +AddNet "/FPGA_Spartan6/M1_DQ1" +AddNet "/FPGA_Spartan6/M1_DQ10" +AddNet "/FPGA_Spartan6/M1_DQ11" +AddNet "/FPGA_Spartan6/M1_DQ14" +AddNet "/FPGA_Spartan6/M1_DQ15" +AddNet "/FPGA_Spartan6/M1_DQ3" +AddNet "/FPGA_Spartan6/M1_DQ4" +AddNet "/FPGA_Spartan6/M1_DQ5" +AddNet "/FPGA_Spartan6/M1_DQ6" +AddNet "/FPGA_Spartan6/M1_DQ9" +AddNet "/FPGA_Spartan6/M1_LDM" +AddNet "/FPGA_Spartan6/M1_LDQS" +AddNet "/FPGA_Spartan6/M1_UDQS" +AddNet "/FPGA_Spartan6/M1_WE#" +AddNet "/FPGA_Spartan6/NF_D1" +AddNet "/FPGA_Spartan6/NF_D3" +AddNet "/FPGA_Spartan6/NF_D4" +AddNet "/FPGA_Spartan6/NF_D5" +AddNet "/FPGA_Spartan6/NF_D7" +AddNet "/FPGA_Spartan6/PROG_CCLK" +AddNet "/FPGA_Spartan6/PROG_CSO" +AddNet "/FPGA_Spartan6/PROG_MISO0" +AddNet "/FPGA_Spartan6/PROG_MISO1" +AddNet "/FPGA_Spartan6/PROG_MISO2" +AddNet "/FPGA_Spartan6/PROG_MISO3" +AddNet "/FPGA_Spartan6/R_M0_A0" +AddNet "/FPGA_Spartan6/R_M0_A1" +AddNet "/FPGA_Spartan6/R_M0_A10" +AddNet "/FPGA_Spartan6/R_M0_A11" +AddNet "/FPGA_Spartan6/R_M0_A12" +AddNet "/FPGA_Spartan6/R_M0_A2" +AddNet "/FPGA_Spartan6/R_M0_A3" +AddNet "/FPGA_Spartan6/R_M0_A4" +AddNet "/FPGA_Spartan6/R_M0_A5" +AddNet "/FPGA_Spartan6/R_M0_A6" +AddNet "/FPGA_Spartan6/R_M0_A7" +AddNet "/FPGA_Spartan6/R_M0_A8" +AddNet "/FPGA_Spartan6/R_M0_A9" +AddNet "/FPGA_Spartan6/R_M0_BA0" +AddNet "/FPGA_Spartan6/R_M0_BA1" +AddNet "/FPGA_Spartan6/R_M0_CAS#" +AddNet "/FPGA_Spartan6/R_M0_CKE" +AddNet "/FPGA_Spartan6/R_M0_DQ0" +AddNet "/FPGA_Spartan6/R_M0_DQ1" +AddNet "/FPGA_Spartan6/R_M0_DQ10" +AddNet "/FPGA_Spartan6/R_M0_DQ11" +AddNet "/FPGA_Spartan6/R_M0_DQ12" +AddNet "/FPGA_Spartan6/R_M0_DQ13" +AddNet "/FPGA_Spartan6/R_M0_DQ14" +AddNet "/FPGA_Spartan6/R_M0_DQ15" +AddNet "/FPGA_Spartan6/R_M0_DQ2" +AddNet "/FPGA_Spartan6/R_M0_DQ3" +AddNet "/FPGA_Spartan6/R_M0_DQ4" +AddNet "/FPGA_Spartan6/R_M0_DQ5" +AddNet "/FPGA_Spartan6/R_M0_DQ6" +AddNet "/FPGA_Spartan6/R_M0_DQ7" +AddNet "/FPGA_Spartan6/R_M0_DQ8" +AddNet "/FPGA_Spartan6/R_M0_DQ9" +AddNet "/FPGA_Spartan6/R_M0_LDM" +AddNet "/FPGA_Spartan6/R_M0_LDQS" +AddNet "/FPGA_Spartan6/R_M0_RAS#" +AddNet "/FPGA_Spartan6/R_M0_UDM" +AddNet "/FPGA_Spartan6/R_M0_UDQS" +AddNet "/FPGA_Spartan6/R_M0_WE#" +AddNet "/FPGA_Spartan6/R_M1_A0" +AddNet "/FPGA_Spartan6/R_M1_A1" +AddNet "/FPGA_Spartan6/R_M1_A10" +AddNet "/FPGA_Spartan6/R_M1_A11" +AddNet "/FPGA_Spartan6/R_M1_A12" +AddNet "/FPGA_Spartan6/R_M1_A2" +AddNet "/FPGA_Spartan6/R_M1_A3" +AddNet "/FPGA_Spartan6/R_M1_A5" +AddNet "/FPGA_Spartan6/R_M1_A6" +AddNet "/FPGA_Spartan6/R_M1_A7" +AddNet "/FPGA_Spartan6/R_M1_A8" +AddNet "/FPGA_Spartan6/R_M1_A9" +AddNet "/FPGA_Spartan6/R_M1_BA0" +AddNet "/FPGA_Spartan6/R_M1_BA1" +AddNet "/FPGA_Spartan6/R_M1_CAS#" +AddNet "/FPGA_Spartan6/R_M1_CKE" +AddNet "/FPGA_Spartan6/R_M1_CS#" +AddNet "/FPGA_Spartan6/R_M1_DQ0" +AddNet "/FPGA_Spartan6/R_M1_DQ1" +AddNet "/FPGA_Spartan6/R_M1_DQ10" +AddNet "/FPGA_Spartan6/R_M1_DQ11" +AddNet "/FPGA_Spartan6/R_M1_DQ12" +AddNet "/FPGA_Spartan6/R_M1_DQ13" +AddNet "/FPGA_Spartan6/R_M1_DQ14" +AddNet "/FPGA_Spartan6/R_M1_DQ15" +AddNet "/FPGA_Spartan6/R_M1_DQ2" +AddNet "/FPGA_Spartan6/R_M1_DQ3" +AddNet "/FPGA_Spartan6/R_M1_DQ4" +AddNet "/FPGA_Spartan6/R_M1_DQ5" +AddNet "/FPGA_Spartan6/R_M1_DQ6" +AddNet "/FPGA_Spartan6/R_M1_DQ7" +AddNet "/FPGA_Spartan6/R_M1_DQ8" +AddNet "/FPGA_Spartan6/R_M1_DQ9" +AddNet "/FPGA_Spartan6/R_M1_LDM" +AddNet "/FPGA_Spartan6/R_M1_LDQS" +AddNet "/FPGA_Spartan6/R_M1_RAS#" +AddNet "/FPGA_Spartan6/R_M1_UDM" +AddNet "/FPGA_Spartan6/R_M1_UDQS" +AddNet "/FPGA_Spartan6/R_M1_WE#" +AddNet "/FPGA_Spartan6/SD_CLK" +AddNet "/FPGA_Spartan6/SD_CMD" +AddNet "/FPGA_Spartan6/SD_DAT0" +AddNet "/FPGA_Spartan6/SD_DAT2" +AddNet "/FPGA_Spartan6/USBA_OE_N" +AddNet "/Non_volatile_memories/NF_ALE" +AddNet "/Non_volatile_memories/NF_CLE" +AddNet "/Non_volatile_memories/NF_CS1_N" +AddNet "/Non_volatile_memories/NF_D0" +AddNet "/Non_volatile_memories/NF_D2" +AddNet "/Non_volatile_memories/NF_D6" +AddNet "/Non_volatile_memories/NF_RE_N" +AddNet "/Non_volatile_memories/NF_RNB" +AddNet "/Non_volatile_memories/NF_WE_N" +AddNet "/Non_volatile_memories/SD_DAT1" +AddNet "/Non_volatile_memories/SD_DAT3" +AddNet "/USB/USBA_RCV" AddNet "/USB/USBA_SPD" +AddNet "/USB/USBA_VM" AddNet "/USB/USBA_VP" -AddNet "N-000127" -AddNet "N-000132" -AddNet "N-000393" -AddNet "N-000394" -AddNet "N-000395" -AddNet "N-000414" +AddNet "N-000267" +AddNet "N-000390" +AddNet "N-000401" +AddNet "N-000405" +AddNet "N-000406" AddNet "N-000415" -AddNet "N-000419" -AddNet "N-000420" -AddNet "N-000421" +AddNet "N-000417" AddNet "N-000422" -AddNet "N-000423" +AddNet "N-000427" +AddNet "N-000428" AddNet "N-000429" AddNet "N-000430" AddNet "N-000431" AddNet "N-000432" AddNet "N-000433" -AddNet "N-000434" AddNet "N-000435" +AddNet "N-000440" +AddNet "N-000441" +AddNet "N-000442" +AddNet "N-000443" +AddNet "N-000444" AddNet "N-000445" -AddNet "N-000464" +AddNet "N-000455" +AddNet "N-000474" $EndNCLASS $NCLASS Name "ADDRESS/DDR" @@ -1467,84 +1482,84 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Sp179" +Ne 48 "/Ethernet_Phy/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Etherne180" +Ne 73 "/FPGA_Spartan6/ETH_RXD1" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Sp181" +Ne 75 "/FPGA_Spartan6/ETH_RXDV" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Etherne182" +Ne 53 "/Ethernet_Phy/ETH_RXC" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Sp183" +Ne 60 "/Ethernet_Phy/ETH_TXD3" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Sp184" +Ne 68 "/FPGA_Spartan6/ETH_COL" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Etherne185" +Ne 49 "/Ethernet_Phy/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Sp186" +Ne 225 "/Non_volatile_memories/NF_D6" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Sp187" +Ne 128 "/FPGA_Spartan6/NF_D4" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_Sp188" +Ne 224 "/Non_volatile_memories/NF_D2" Po 590 -4133 $EndPAD $PAD Sh "A14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 223 "/Non_vol189" +Ne 220 "/Non_volatile_memories/NF_ALE" Po 983 -4133 $EndPAD $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_Sp190" +Ne 227 "/Non_volatile_memories/NF_RNB" Po 1377 -4133 $EndPAD $PAD @@ -1558,21 +1573,21 @@ $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 230 "/Non_vol7" +Ne 218 "/FPGA_Spartan6/SD_DAT2" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/Non_vol11" +Ne 217 "/FPGA_Spartan6/SD_DAT0" Po 2558 -4133 $EndPAD $PAD Sh "A19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DBG_PRG19" +Ne 8 "/DBG_PRG/FPGA_TDO" Po 2952 -4133 $EndPAD $PAD @@ -1635,7 +1650,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Etherne194" +Ne 54 "/Ethernet_Phy/ETH_RXD0" Po -2165 -3739 $EndPAD $PAD @@ -1649,7 +1664,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Etherne195" +Ne 56 "/Ethernet_Phy/ETH_RXER" Po -1377 -3739 $EndPAD $PAD @@ -1663,7 +1678,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Etherne196" +Ne 69 "/FPGA_Spartan6/ETH_CRS" Po -590 -3739 $EndPAD $PAD @@ -1677,7 +1692,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/FPGA_Sp197" +Ne 127 "/FPGA_Spartan6/NF_D3" Po 196 -3739 $EndPAD $PAD @@ -1691,7 +1706,7 @@ $PAD Sh "B14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/FPGA_Sp198" +Ne 221 "/Non_volatile_memories/NF_CLE" Po 983 -3739 $EndPAD $PAD @@ -1719,7 +1734,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "/Non_vol12" +Ne 229 "/Non_volatile_memories/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1733,7 +1748,7 @@ $PAD Sh "B20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 219 "/FPGA_Spartan6/USBA_OE_N" Po 3346 -3739 $EndPAD $PAD @@ -1754,7 +1769,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Sp172" +Ne 140 "/FPGA_Spartan6/R_M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1782,56 +1797,56 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/FPGA_Sp199" +Ne 74 "/FPGA_Spartan6/ETH_RXD3" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Etherne200" +Ne 55 "/Ethernet_Phy/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/FPGA_Sp201" +Ne 72 "/FPGA_Spartan6/ETH_RESET_N" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Etherne202" +Ne 57 "/Ethernet_Phy/ETH_TXC" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/FPGA_Sp203" +Ne 76 "/FPGA_Spartan6/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA_Sp204" +Ne 59 "/Ethernet_Phy/ETH_TXD2" Po -590 -3346 $EndPAD $PAD Sh "C11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 224 "/Non_vol205" +Ne 129 "/FPGA_Spartan6/NF_D5" Po -196 -3346 $EndPAD $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA_Sp206" +Ne 223 "/Non_volatile_memories/NF_D0" Po 196 -3346 $EndPAD $PAD @@ -1845,14 +1860,14 @@ $PAD Sh "C14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 225 "/Non_vol207" +Ne 228 "/Non_volatile_memories/NF_WE_N" Po 983 -3346 $EndPAD $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 226 "/Non_vol208" +Ne 226 "/Non_volatile_memories/NF_RE_N" Po 1377 -3346 $EndPAD $PAD @@ -1866,28 +1881,28 @@ $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "/Non_vol8" +Ne 230 "/Non_volatile_memories/SD_DAT3" Po 2165 -3346 $EndPAD $PAD Sh "C18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DBG_PRG18" +Ne 9 "/DBG_PRG/FPGA_TMS" Po 2558 -3346 $EndPAD $PAD Sh "C19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 232 "/USB/USBA_SPD" Po 2952 -3346 $EndPAD $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 208 "/FPGA_Sp89" +Ne 186 "/FPGA_Spartan6/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1901,21 +1916,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 210 "/FPGA_Sp90" +Ne 187 "/FPGA_Spartan6/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Sp171" +Ne 141 "/FPGA_Spartan6/R_M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/FPGA_Sp40" +Ne 153 "/FPGA_Spartan6/R_M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1943,42 +1958,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Etherne21" +Ne 71 "/FPGA_Spartan6/ETH_MDIO" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Etherne209" +Ne 70 "/FPGA_Spartan6/ETH_MDC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA_Sp210" +Ne 62 "/Ethernet_Phy/ETH_TXER" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA_Sp211" +Ne 61 "/Ethernet_Phy/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_Sp212" +Ne 58 "/Ethernet_Phy/ETH_TXD0" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 227 "/Non_vol213" +Ne 130 "/FPGA_Spartan6/NF_D7" Po -196 -2952 $EndPAD $PAD @@ -1999,14 +2014,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 228 "/Non_vol214" +Ne 126 "/FPGA_Spartan6/NF_D1" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "/Non_vol215" +Ne 222 "/Non_volatile_memories/NF_CS1_N" Po 1377 -2952 $EndPAD $PAD @@ -2020,7 +2035,7 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 209 "/FPGA_Sp9" +Ne 216 "/FPGA_Spartan6/SD_CMD" Po 2165 -2952 $EndPAD $PAD @@ -2048,21 +2063,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/FPGA_Sp26" +Ne 191 "/FPGA_Spartan6/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 212 "/FPGA_Sp92" +Ne 180 "/FPGA_Spartan6/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Sp173" +Ne 149 "/FPGA_Spartan6/R_M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -2076,7 +2091,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Sp174" +Ne 148 "/FPGA_Spartan6/R_M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -2167,7 +2182,7 @@ $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 220 "/Non_vol10" +Ne 215 "/FPGA_Spartan6/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -2181,7 +2196,7 @@ $PAD Sh "E18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DBG_PRG20" +Ne 7 "/DBG_PRG/FPGA_TDI" Po 2558 -2558 $EndPAD $PAD @@ -2195,7 +2210,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 204 "/FPGA_Sp85" +Ne 185 "/FPGA_Spartan6/R_M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -2209,7 +2224,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/FPGA_Sp44" +Ne 181 "/FPGA_Spartan6/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -2223,14 +2238,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Sp159" +Ne 175 "/FPGA_Spartan6/R_M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Sp168" +Ne 144 "/FPGA_Spartan6/R_M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -2321,7 +2336,7 @@ $PAD Sh "F16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 233 "/USB/USBA_VM" Po 1771 -2165 $EndPAD $PAD @@ -2342,7 +2357,7 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 211 "/FPGA_Sp91" +Ne 179 "/FPGA_Spartan6/R_M1_A11" Po 2952 -2165 $EndPAD $PAD @@ -2356,21 +2371,21 @@ $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/FPGA_Sp42" +Ne 176 "/FPGA_Spartan6/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/FPGA_Sp43" +Ne 177 "/FPGA_Spartan6/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Sp151" +Ne 151 "/FPGA_Spartan6/R_M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -2384,14 +2399,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Sp150" +Ne 150 "/FPGA_Spartan6/R_M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Sp152" +Ne 139 "/FPGA_Spartan6/R_M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -2468,21 +2483,21 @@ $PAD Sh "G15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DBG_PRG17" +Ne 6 "/DBG_PRG/FPGA_TCK" Po 1377 -1771 $EndPAD $PAD Sh "G16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 231 "/USB/USBA_RCV" Po 1771 -1771 $EndPAD $PAD Sh "G17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 234 "/USB/USBA_VP" Po 2165 -1771 $EndPAD $PAD @@ -2496,14 +2511,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/FPGA_Sp52" +Ne 178 "/FPGA_Spartan6/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/FPGA_Sp45" +Ne 182 "/FPGA_Spartan6/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2524,42 +2539,42 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Sp142" +Ne 138 "/FPGA_Spartan6/R_M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Sp141" +Ne 137 "/FPGA_Spartan6/R_M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_Sp35" +Ne 89 "/FPGA_Spartan6/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_Sp34" +Ne 15 "/DDR_Banks/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Sp143" +Ne 142 "/FPGA_Spartan6/R_M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Sp165" +Ne 147 "/FPGA_Spartan6/R_M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -2629,7 +2644,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/FPGA_Sp32" +Ne 192 "/FPGA_Spartan6/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -2650,35 +2665,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/FPGA_Sp59" +Ne 214 "/FPGA_Spartan6/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Ban25" +Ne 36 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/FPGA_Sp49" +Ne 211 "/FPGA_Spartan6/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/FPGA_Sp60" +Ne 190 "/FPGA_Spartan6/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Sp126" +Ne 165 "/FPGA_Spartan6/R_M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -2692,14 +2707,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Sp125" +Ne 164 "/FPGA_Spartan6/R_M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Sp166" +Ne 146 "/FPGA_Spartan6/R_M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2790,7 +2805,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/FPGA_Sp50" +Ne 188 "/FPGA_Spartan6/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2804,14 +2819,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Ban24" +Ne 37 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/FPGA_Sp65" +Ne 203 "/FPGA_Spartan6/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD @@ -2825,49 +2840,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/FPGA_Sp66" +Ne 204 "/FPGA_Spartan6/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Sp128" +Ne 167 "/FPGA_Spartan6/R_M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Sp127" +Ne 166 "/FPGA_Spartan6/R_M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Sp167" +Ne 145 "/FPGA_Spartan6/R_M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Sp160" +Ne 152 "/FPGA_Spartan6/R_M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Sp149" +Ne 172 "/FPGA_Spartan6/R_M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Sp144" +Ne 143 "/FPGA_Spartan6/R_M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2944,7 +2959,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/FPGA_Sp51" +Ne 189 "/FPGA_Spartan6/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2958,28 +2973,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 203 "/FPGA_Sp84" +Ne 184 "/FPGA_Spartan6/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 202 "/FPGA_Sp83" +Ne 183 "/FPGA_Spartan6/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/FPGA_Sp67" +Ne 205 "/FPGA_Spartan6/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/FPGA_Sp68" +Ne 206 "/FPGA_Spartan6/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -3000,14 +3015,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Sp157" +Ne 171 "/FPGA_Spartan6/R_M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Sp158" +Ne 170 "/FPGA_Spartan6/R_M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -3112,14 +3127,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/FPGA_Sp58" +Ne 209 "/FPGA_Spartan6/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 180 "/FPGA_Sp57" +Ne 210 "/FPGA_Spartan6/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -3140,21 +3155,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Sp136" +Ne 163 "/FPGA_Spartan6/R_M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Sp135" +Ne 162 "/FPGA_Spartan6/R_M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/FPGA_Sp38" +Ne 173 "/FPGA_Spartan6/R_M0_UDM" Po -3346 196 $EndPAD $PAD @@ -3259,7 +3274,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/FPGA_Sp216" +Ne 0 "" Po 2558 196 $EndPAD $PAD @@ -3273,28 +3288,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_Sp28" +Ne 212 "/FPGA_Spartan6/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 196 "/FPGA_Sp75" +Ne 201 "/FPGA_Spartan6/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 197 "/FPGA_Sp76" +Ne 202 "/FPGA_Spartan6/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Sp134" +Ne 155 "/FPGA_Spartan6/R_M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -3308,7 +3323,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Sp133" +Ne 154 "/FPGA_Spartan6/R_M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -3399,7 +3414,7 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/FPGA_Sp217" +Ne 0 "" Po 1771 590 $EndPAD $PAD @@ -3427,7 +3442,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 194 "/FPGA_Sp73" +Ne 193 "/FPGA_Spartan6/R_M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -3441,21 +3456,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 195 "/FPGA_Sp74" +Ne 194 "/FPGA_Spartan6/R_M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Sp118" +Ne 169 "/FPGA_Spartan6/R_M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Sp117" +Ne 168 "/FPGA_Spartan6/R_M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3560,14 +3575,14 @@ $PAD Sh "P17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 234 "/USB/USBA_VP" +Ne 0 "" Po 2165 983 $EndPAD $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 232 "/USB/USBA_OE_N" +Ne 0 "" Po 2558 983 $EndPAD $PAD @@ -3588,21 +3603,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Sp105" +Ne 207 "/FPGA_Spartan6/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Sp106" +Ne 208 "/FPGA_Spartan6/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Sp120" +Ne 157 "/FPGA_Spartan6/R_M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3616,7 +3631,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Sp119" +Ne 156 "/FPGA_Spartan6/R_M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3728,14 +3743,14 @@ $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 233 "/USB/USBA_SPD" +Ne 0 "" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Sp107" +Ne 195 "/FPGA_Spartan6/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3749,7 +3764,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Sp108" +Ne 196 "/FPGA_Spartan6/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3763,7 +3778,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/FPGA_Sp36" +Ne 174 "/FPGA_Spartan6/R_M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3784,7 +3799,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/FPGA_Sp218" +Ne 132 "/FPGA_Spartan6/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -3812,7 +3827,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -983 1771 $EndPAD $PAD @@ -3840,7 +3855,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po 590 1771 $EndPAD $PAD @@ -3896,7 +3911,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_Sp30" +Ne 213 "/FPGA_Spartan6/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3910,7 +3925,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Sp110" +Ne 159 "/FPGA_Spartan6/R_M0_DQ13" Po -4133 2165 $EndPAD $PAD @@ -3924,7 +3939,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Sp109" +Ne 158 "/FPGA_Spartan6/R_M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3994,14 +4009,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_Sp219" +Ne 136 "/FPGA_Spartan6/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_Sp220" +Ne 135 "/FPGA_Spartan6/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -4043,7 +4058,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/FPGA_Sp97" +Ne 197 "/FPGA_Spartan6/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -4057,21 +4072,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 218 "/FPGA_Sp98" +Ne 198 "/FPGA_Spartan6/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Sp112" +Ne 161 "/FPGA_Spartan6/R_M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Sp111" +Ne 160 "/FPGA_Spartan6/R_M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -4113,7 +4128,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -1377 2558 $EndPAD $PAD @@ -4141,7 +4156,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po 196 2558 $EndPAD $PAD @@ -4169,7 +4184,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po 1771 2558 $EndPAD $PAD @@ -4204,14 +4219,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 219 "/FPGA_Sp99" +Ne 199 "/FPGA_Spartan6/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Sp100" +Ne 200 "/FPGA_Spartan6/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -4246,7 +4261,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -2558 2952 $EndPAD $PAD @@ -4519,14 +4534,14 @@ $PAD Sh "Y22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 236 "N-000127" +Ne 236 "N-000267" Po 4133 3346 $EndPAD $PAD Sh "AA1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 237 "N-000132" +Ne 237 "N-000390" Po -4133 3739 $EndPAD $PAD @@ -4540,7 +4555,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -3346 3739 $EndPAD $PAD @@ -4568,7 +4583,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -1771 3739 $EndPAD $PAD @@ -4596,7 +4611,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -196 3739 $EndPAD $PAD @@ -4624,7 +4639,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po 1377 3739 $EndPAD $PAD @@ -4652,21 +4667,21 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po 2952 3739 $EndPAD $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA_Sp191" +Ne 134 "/FPGA_Spartan6/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/FPGA_Sp192" +Ne 131 "/FPGA_Spartan6/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -4813,7 +4828,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/FPGA_Sp193" +Ne 133 "/FPGA_Spartan6/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -4832,7 +4847,7 @@ Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 $MODULE DFN10 -Po 65354 43898 0 15 4C6C9E22 4C6C9ECB ~~ +Po 63598 21791 0 15 4C6C9E22 4C6C9ECB ~~ Li DFN10 Sc 4C6C9ECB AR /4C69ED5F/4C6C9DB9 @@ -4996,14 +5011,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/FPGA_Sp38" +Ne 173 "/FPGA_Spartan6/R_M0_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/DDR_Ban39" +Ne 99 "/FPGA_Spartan6/M0_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5024,14 +5039,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/FPGA_Sp36" +Ne 174 "/FPGA_Spartan6/R_M0_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/FPGA_Sp37" +Ne 100 "/FPGA_Spartan6/M0_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5052,14 +5067,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/FPGA_Sp40" +Ne 153 "/FPGA_Spartan6/R_M0_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Ban41" +Ne 88 "/FPGA_Spartan6/M0_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5080,14 +5095,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/FPGA_Sp34" +Ne 15 "/DDR_Banks/M0_CLK" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/FPGA_Sp35" +Ne 89 "/FPGA_Spartan6/M0_CLK#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5106,56 +5121,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 93 "/FPGA_Sp141" +Ne 137 "/FPGA_Spartan6/R_M0_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/FPGA_Sp142" +Ne 138 "/FPGA_Spartan6/R_M0_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/FPGA_Sp143" +Ne 142 "/FPGA_Spartan6/R_M0_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 96 "/FPGA_Sp144" +Ne 143 "/FPGA_Spartan6/R_M0_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 97 "/FPGA_Sp145" +Ne 82 "/FPGA_Spartan6/M0_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 98 "/FPGA_Sp146" +Ne 81 "/FPGA_Spartan6/M0_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 99 "/FPGA_Sp147" +Ne 77 "/FPGA_Spartan6/M0_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 100 "/FPGA_Sp148" +Ne 10 "/DDR_Banks/M0_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5174,56 +5189,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 101 "/FPGA_Sp149" +Ne 172 "/FPGA_Spartan6/R_M0_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 102 "/FPGA_Sp150" +Ne 150 "/FPGA_Spartan6/R_M0_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/FPGA_Sp151" +Ne 151 "/FPGA_Spartan6/R_M0_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/FPGA_Sp152" +Ne 139 "/FPGA_Spartan6/R_M0_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 105 "/FPGA_Sp153" +Ne 78 "/FPGA_Spartan6/M0_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 106 "/FPGA_Sp154" +Ne 14 "/DDR_Banks/M0_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/FPGA_Sp155" +Ne 86 "/FPGA_Spartan6/M0_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 108 "/FPGA_Sp156" +Ne 25 "/DDR_Banks/M0_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5242,56 +5257,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 109 "/FPGA_Sp157" +Ne 171 "/FPGA_Spartan6/R_M0_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 110 "/FPGA_Sp158" +Ne 170 "/FPGA_Spartan6/R_M0_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 111 "/FPGA_Sp159" +Ne 175 "/FPGA_Spartan6/R_M0_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 112 "/FPGA_Sp160" +Ne 152 "/FPGA_Spartan6/R_M0_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 113 "/FPGA_Sp161" +Ne 87 "/FPGA_Spartan6/M0_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 17 "/DDR_Ban162" +Ne 27 "/DDR_Banks/M0_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 114 "/FPGA_Sp163" +Ne 23 "/DDR_Banks/M0_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 115 "/FPGA_Sp164" +Ne 24 "/DDR_Banks/M0_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5310,56 +5325,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 116 "/FPGA_Sp165" +Ne 147 "/FPGA_Spartan6/R_M0_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 117 "/FPGA_Sp166" +Ne 146 "/FPGA_Spartan6/R_M0_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 118 "/FPGA_Sp167" +Ne 145 "/FPGA_Spartan6/R_M0_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 119 "/FPGA_Sp168" +Ne 144 "/FPGA_Spartan6/R_M0_A4" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M0_A4" +Ne 83 "/FPGA_Spartan6/M0_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 120 "/FPGA_Sp169" +Ne 11 "/DDR_Banks/M0_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 121 "/FPGA_Sp170" +Ne 84 "/FPGA_Spartan6/M0_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/DDR_Banks/M0_A7" +Ne 12 "/DDR_Banks/M0_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5378,56 +5393,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 122 "/FPGA_Sp171" +Ne 141 "/FPGA_Spartan6/R_M0_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 123 "/FPGA_Sp172" +Ne 140 "/FPGA_Spartan6/R_M0_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 124 "/FPGA_Sp173" +Ne 149 "/FPGA_Spartan6/R_M0_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 125 "/FPGA_Sp174" +Ne 148 "/FPGA_Spartan6/R_M0_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 126 "/FPGA_Sp175" +Ne 85 "/FPGA_Spartan6/M0_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 127 "/FPGA_Sp176" +Ne 13 "/DDR_Banks/M0_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 128 "/FPGA_Sp177" +Ne 79 "/FPGA_Spartan6/M0_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Ban178" +Ne 80 "/FPGA_Spartan6/M0_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5446,56 +5461,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 80 "/FPGA_Sp125" +Ne 164 "/FPGA_Spartan6/R_M0_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 81 "/FPGA_Sp126" +Ne 165 "/FPGA_Spartan6/R_M0_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 82 "/FPGA_Sp127" +Ne 166 "/FPGA_Spartan6/R_M0_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 83 "/FPGA_Sp128" +Ne 167 "/FPGA_Spartan6/R_M0_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Sp129" +Ne 97 "/FPGA_Spartan6/M0_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 14 "/DDR_Ban130" +Ne 96 "/FPGA_Spartan6/M0_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 15 "/DDR_Ban131" +Ne 21 "/DDR_Banks/M0_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 85 "/FPGA_Sp132" +Ne 95 "/FPGA_Spartan6/M0_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5514,56 +5529,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 86 "/FPGA_Sp133" +Ne 154 "/FPGA_Spartan6/R_M0_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 87 "/FPGA_Sp134" +Ne 155 "/FPGA_Spartan6/R_M0_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 88 "/FPGA_Sp135" +Ne 162 "/FPGA_Spartan6/R_M0_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 89 "/FPGA_Sp136" +Ne 163 "/FPGA_Spartan6/R_M0_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 90 "/FPGA_Sp137" +Ne 94 "/FPGA_Spartan6/M0_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 16 "/DDR_Ban138" +Ne 93 "/FPGA_Spartan6/M0_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 91 "/FPGA_Sp139" +Ne 16 "/DDR_Banks/M0_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 92 "/FPGA_Sp140" +Ne 90 "/FPGA_Spartan6/M0_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5582,56 +5597,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 72 "/FPGA_Sp117" +Ne 168 "/FPGA_Spartan6/R_M0_DQ8" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 73 "/FPGA_Sp118" +Ne 169 "/FPGA_Spartan6/R_M0_DQ9" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 74 "/FPGA_Sp119" +Ne 156 "/FPGA_Spartan6/R_M0_DQ10" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 75 "/FPGA_Sp120" +Ne 157 "/FPGA_Spartan6/R_M0_DQ11" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 76 "/FPGA_Sp121" +Ne 91 "/FPGA_Spartan6/M0_DQ11" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 77 "/FPGA_Sp122" +Ne 17 "/DDR_Banks/M0_DQ10" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 78 "/FPGA_Sp123" +Ne 98 "/FPGA_Spartan6/M0_DQ9" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 79 "/FPGA_Sp124" +Ne 22 "/DDR_Banks/M0_DQ8" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5650,61 +5665,61 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 67 "/FPGA_Sp109" +Ne 158 "/FPGA_Spartan6/R_M0_DQ12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 68 "/FPGA_Sp110" +Ne 159 "/FPGA_Spartan6/R_M0_DQ13" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 69 "/FPGA_Sp111" +Ne 160 "/FPGA_Spartan6/R_M0_DQ14" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 70 "/FPGA_Sp112" +Ne 161 "/FPGA_Spartan6/R_M0_DQ15" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 11 "/DDR_Ban113" +Ne 20 "/DDR_Banks/M0_DQ15" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 71 "/FPGA_Sp114" +Ne 19 "/DDR_Banks/M0_DQ14" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 12 "/DDR_Ban115" +Ne 92 "/FPGA_Spartan6/M0_DQ13" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 13 "/DDR_Ban116" +Ne 18 "/DDR_Banks/M0_DQ12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 $MODULE MLF20m1 -Po 65551 41732 0 15 4C69F3CC 4C69F729 ~~ +Po 63240 19370 0 15 4C69F3CC 4C69F729 ~~ Li MLF20m1 Sc 4C69F729 AR /4C69ED5F/4C69EE11 @@ -5903,14 +5918,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/FPGA_Sp30" +Ne 213 "/FPGA_Spartan6/R_M1_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/FPGA_Sp31" +Ne 124 "/FPGA_Spartan6/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5931,14 +5946,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/FPGA_Sp32" +Ne 192 "/FPGA_Spartan6/R_M1_CS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 22 "/DDR_Ban33" +Ne 110 "/FPGA_Spartan6/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5959,14 +5974,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/FPGA_Sp26" +Ne 191 "/FPGA_Spartan6/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/FPGA_Sp27" +Ne 35 "/DDR_Banks/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5987,14 +6002,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/FPGA_Sp28" +Ne 212 "/FPGA_Spartan6/R_M1_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 21 "/DDR_Ban29" +Ne 44 "/DDR_Banks/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6013,56 +6028,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 213 "/FPGA_Sp93" +Ne 116 "/FPGA_Spartan6/M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 214 "/FPGA_Sp94" +Ne 115 "/FPGA_Spartan6/M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 215 "/FPGA_Sp95" +Ne 39 "/DDR_Banks/M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 216 "/FPGA_Sp96" +Ne 38 "/DDR_Banks/M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 217 "/FPGA_Sp97" +Ne 197 "/FPGA_Spartan6/R_M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 218 "/FPGA_Sp98" +Ne 198 "/FPGA_Spartan6/R_M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 219 "/FPGA_Sp99" +Ne 199 "/FPGA_Spartan6/R_M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 59 "/FPGA_Sp100" +Ne 200 "/FPGA_Spartan6/R_M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6081,56 +6096,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 10 "/DDR_Ban101" +Ne 114 "/FPGA_Spartan6/M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 60 "/FPGA_Sp102" +Ne 113 "/FPGA_Spartan6/M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 61 "/FPGA_Sp103" +Ne 121 "/FPGA_Spartan6/M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 62 "/FPGA_Sp104" +Ne 42 "/DDR_Banks/M1_DQ8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 63 "/FPGA_Sp105" +Ne 207 "/FPGA_Spartan6/R_M1_DQ8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 64 "/FPGA_Sp106" +Ne 208 "/FPGA_Spartan6/R_M1_DQ9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 65 "/FPGA_Sp107" +Ne 195 "/FPGA_Spartan6/R_M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 66 "/FPGA_Sp108" +Ne 196 "/FPGA_Spartan6/R_M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6151,14 +6166,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 19 "/DDR_Ban24" +Ne 37 "/DDR_Banks/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/DDR_Ban25" +Ne 36 "/DDR_Banks/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6177,56 +6192,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 205 "/FPGA_Sp86" +Ne 29 "/DDR_Banks/M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 206 "/FPGA_Sp87" +Ne 28 "/DDR_Banks/M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_A9" +Ne 107 "/FPGA_Spartan6/M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 207 "/FPGA_Sp88" +Ne 106 "/FPGA_Spartan6/M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 208 "/FPGA_Sp89" +Ne 186 "/FPGA_Spartan6/R_M1_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 210 "/FPGA_Sp90" +Ne 187 "/FPGA_Spartan6/R_M1_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 211 "/FPGA_Sp91" +Ne 179 "/FPGA_Spartan6/R_M1_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 212 "/FPGA_Sp92" +Ne 180 "/FPGA_Spartan6/R_M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6245,28 +6260,28 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 37 "/DDR_Banks/M1_A7" +Ne 33 "/DDR_Banks/M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 200 "/FPGA_Sp81" +Ne 32 "/DDR_Banks/M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 201 "/FPGA_Sp82" +Ne 31 "/DDR_Banks/M1_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 36 "/DDR_Banks/M1_A4" +Ne 30 "/DDR_Banks/M1_A4" Po 295 -177 $EndPAD $PAD @@ -6280,21 +6295,21 @@ $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 202 "/FPGA_Sp83" +Ne 183 "/FPGA_Spartan6/R_M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 203 "/FPGA_Sp84" +Ne 184 "/FPGA_Spartan6/R_M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 204 "/FPGA_Sp85" +Ne 185 "/FPGA_Spartan6/R_M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6313,56 +6328,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 194 "/FPGA_Sp73" +Ne 193 "/FPGA_Spartan6/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 195 "/FPGA_Sp74" +Ne 194 "/FPGA_Spartan6/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 196 "/FPGA_Sp75" +Ne 201 "/FPGA_Spartan6/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 197 "/FPGA_Sp76" +Ne 202 "/FPGA_Spartan6/R_M1_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 198 "/FPGA_Sp77" +Ne 117 "/FPGA_Spartan6/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 199 "/FPGA_Sp78" +Ne 40 "/DDR_Banks/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/DDR_Ban79" +Ne 112 "/FPGA_Spartan6/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Ban80" +Ne 111 "/FPGA_Spartan6/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6381,56 +6396,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 180 "/FPGA_Sp57" +Ne 210 "/FPGA_Spartan6/R_M1_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/FPGA_Sp58" +Ne 209 "/FPGA_Spartan6/R_M1_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/FPGA_Sp59" +Ne 214 "/FPGA_Spartan6/R_M1_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/FPGA_Sp60" +Ne 190 "/FPGA_Spartan6/R_M1_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/FPGA_Sp61" +Ne 109 "/FPGA_Spartan6/M1_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/DDR_Ban62" +Ne 125 "/FPGA_Spartan6/M1_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 185 "/FPGA_Sp63" +Ne 122 "/FPGA_Spartan6/M1_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 186 "/FPGA_Sp64" +Ne 123 "/FPGA_Spartan6/M1_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6449,56 +6464,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 187 "/FPGA_Sp65" +Ne 203 "/FPGA_Spartan6/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 188 "/FPGA_Sp66" +Ne 204 "/FPGA_Spartan6/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 189 "/FPGA_Sp67" +Ne 205 "/FPGA_Spartan6/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 190 "/FPGA_Sp68" +Ne 206 "/FPGA_Spartan6/R_M1_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 191 "/FPGA_Sp69" +Ne 41 "/DDR_Banks/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Ban70" +Ne 120 "/FPGA_Spartan6/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 192 "/FPGA_Sp71" +Ne 119 "/FPGA_Spartan6/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 193 "/FPGA_Sp72" +Ne 118 "/FPGA_Spartan6/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6517,56 +6532,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 174 "/FPGA_Sp49" +Ne 211 "/FPGA_Spartan6/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 175 "/FPGA_Sp50" +Ne 188 "/FPGA_Spartan6/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 176 "/FPGA_Sp51" +Ne 189 "/FPGA_Spartan6/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 177 "/FPGA_Sp52" +Ne 178 "/FPGA_Spartan6/R_M1_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Ban53" +Ne 103 "/FPGA_Spartan6/M1_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Ban54" +Ne 108 "/FPGA_Spartan6/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 178 "/FPGA_Sp55" +Ne 34 "/DDR_Banks/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 179 "/FPGA_Sp56" +Ne 43 "/DDR_Banks/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6585,56 +6600,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/FPGA_Sp42" +Ne 176 "/FPGA_Spartan6/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/FPGA_Sp43" +Ne 177 "/FPGA_Spartan6/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/FPGA_Sp44" +Ne 181 "/FPGA_Spartan6/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/FPGA_Sp45" +Ne 182 "/FPGA_Spartan6/R_M1_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/FPGA_Sp46" +Ne 105 "/FPGA_Spartan6/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/DDR_Banks/M1_A2" +Ne 104 "/FPGA_Spartan6/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 172 "/FPGA_Sp47" +Ne 102 "/FPGA_Spartan6/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 173 "/FPGA_Sp48" +Ne 101 "/FPGA_Spartan6/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6683,14 +6698,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/Etherne1" +Ne 46 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 57 "/Etherne3" +Ne 52 "/Ethernet_Phy/ETH_PLL1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6718,7 +6733,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/Etherne1" +Ne 46 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6885,49 +6900,49 @@ $PAD Sh "8" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -750 -1050 $EndPAD $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/FPGA_Sp218" +Ne 132 "/FPGA_Spartan6/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_Sp219" +Ne 136 "/FPGA_Spartan6/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/FPGA_Sp192" +Ne 131 "/FPGA_Spartan6/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/FPGA_Sp193" +Ne 133 "/FPGA_Spartan6/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA_Sp191" +Ne 134 "/FPGA_Spartan6/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_Sp220" +Ne 135 "/FPGA_Spartan6/PROG_MISO2" Po 250 1050 $EndPAD $PAD @@ -7029,7 +7044,7 @@ Po 570 0 $EndPAD $EndMODULE 1210 $MODULE 1210 -Po 62900 29400 0 15 4C5FF890 4C656BF8 ~~ +Po 64610 29496 0 15 4C5FF890 4C656BF8 ~~ Li 1210 Sc 4C656BF8 AR /4C431A63/4C656BF8 @@ -7057,27 +7072,27 @@ Po 570 0 $EndPAD $EndMODULE 1210 $MODULE 1210 -Po 62500 27900 1800 15 4C5FF890 4C656CB7 ~~ +Po 61949 28925 900 15 4C5FF890 4C656CB7 ~~ Li 1210 Sc 4C656CB7 AR /4C431A63/4C656CB7 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C41" -T1 0 150 200 200 1800 40 N I 25 N"100uF" +T0 0 -150 200 200 900 40 N V 25 N"C41" +T1 0 150 200 200 900 40 N I 25 N"100uF" DS -798 542 -798 -542 50 21 DS -798 -542 798 -542 50 21 DS 798 -542 798 542 50 21 DS 798 542 -798 542 50 21 $PAD -Sh "1" R 355 984 0 0 1800 +Sh "1" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 4 "+3.3V" Po -570 0 $EndPAD $PAD -Sh "2" R 355 984 0 0 1800 +Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 235 "GND" @@ -7129,7 +7144,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -570 0 $EndPAD $PAD @@ -7225,29 +7240,29 @@ Po 373 0 $EndPAD $EndMODULE 0805 $MODULE 0805 -Po 60000 29700 0 0 4C5FF890 4C656CB9 ~~ +Po 60402 29224 0 15 4C5FF890 4C656CB9 ~~ Li 0805 Sc 4C656CB9 AR /4C431A63/4C656CB9 Op 0 0 0 At SMD -T0 0 150 200 200 0 40 M V 20 N"C44" -T1 0 -150 200 200 0 40 M I 20 N"4.7uF" -DS -561 -305 -561 305 50 20 -DS -561 305 561 305 50 20 -DS 561 305 561 -305 50 20 -DS 561 -305 -561 -305 50 20 +T0 0 -150 200 200 0 40 N V 21 N"C44" +T1 0 150 200 200 0 40 N I 21 N"4.7uF" +DS -561 305 -561 -305 50 21 +DS -561 -305 561 -305 50 21 +DS 561 -305 561 305 50 21 +DS 561 305 -561 305 50 21 $PAD Sh "1" R 275 510 0 0 0 Dr 0 0 0 -At SMD N 00440001 +At SMD N 00888000 Ne 4 "+3.3V" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 -At SMD N 00440001 +At SMD N 00888000 Ne 235 "GND" Po 373 0 $EndPAD @@ -7325,7 +7340,7 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -373 0 $EndPAD $PAD @@ -7605,7 +7620,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7689,7 +7704,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7773,7 +7788,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7829,7 +7844,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 257 "VCCO2" +Ne 260 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7840,36 +7855,8 @@ Ne 235 "GND" Po 176 0 $EndPAD $EndMODULE 0402 -$MODULE 1210 -Po 67160 19800 1800 15 4C5FF890 4C6552BA ~~ -Li 1210 -Sc 4C6552BA -AR /4C5F1EDC/4C6552BA -Op 0 0 0 -At SMD -T0 0 -150 200 200 1800 40 N V 25 N"F2" -T1 0 150 200 200 1800 40 N I 25 N"MICROSMD075F" -DS -798 542 -798 -542 50 21 -DS -798 -542 798 -542 50 21 -DS 798 -542 798 542 50 21 -DS 798 542 -798 542 50 21 -$PAD -Sh "1" R 355 984 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 243 "N-000419" -Po -570 0 -$EndPAD -$PAD -Sh "2" R 355 984 0 0 1800 -Dr 0 0 0 -At SMD N 00888000 -Ne 5 "+5V" -Po 570 0 -$EndPAD -$EndMODULE 1210 $MODULE 0805 -Po 66130 25290 0 15 4C5FF890 4C6552BE ~~ +Po 62236 25969 0 15 4C5FF890 4C6552BE ~~ Li 0805 Sc 4C6552BE AR /4C5F1EDC/4C6552BE @@ -7897,7 +7884,7 @@ Po 373 0 $EndPAD $EndMODULE 0805 $MODULE 0805 -Po 68490 25410 0 15 4C5FF890 4C6552BD ~~ +Po 63614 25996 0 15 4C5FF890 4C6552BD ~~ Li 0805 Sc 4C6552BD AR /4C5F1EDC/4C6552BD @@ -7925,7 +7912,7 @@ Po 373 0 $EndPAD $EndMODULE 0805 $MODULE 0603 -Po 68330 28770 0 15 4C5FF890 4C6552B8 ~~ +Po 63909 27335 0 15 4C5FF890 4C6552B8 ~~ Li 0603 Sc 4C6552B8 AR /4C5F1EDC/4C6552B8 @@ -7941,7 +7928,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 244 "N-000420" +Ne 244 "N-000427" Po -294 0 $EndPAD $PAD @@ -7953,7 +7940,7 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 68250 27490 0 15 4C5FF890 4C6552B9 ~~ +Po 63906 26791 0 15 4C5FF890 4C6552B9 ~~ Li 0603 Sc 4C6552B9 AR /4C5F1EDC/4C6552B9 @@ -7969,7 +7956,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 248 "N-000429" +Ne 243 "N-000422" Po -294 0 $EndPAD $PAD @@ -7981,7 +7968,7 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0402 -Po 65600 23720 0 15 4C5FF890 4C6552BC ~~ +Po 61756 26673 0 15 4C5FF890 4C6552BC ~~ Li 0402 Sc 4C6552BC AR /4C5F1EDC/4C6552BC @@ -8009,7 +7996,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 67770 21890 0 15 4C5FF890 4C6552B7 ~~ +Po 62925 24272 0 15 4C5FF890 4C6552B7 ~~ Li 0402 Sc 4C6552B7 AR /4C5F1EDC/4C6552B7 @@ -8025,7 +8012,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 249 "N-000430" +Ne 251 "N-000435" Po -176 0 $EndPAD $PAD @@ -8037,7 +8024,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 69610 22370 0 15 4C5FF890 4C6552B6 ~~ +Po 62957 24827 0 15 4C5FF890 4C6552B6 ~~ Li 0402 Sc 4C6552B6 AR /4C5F1EDC/4C6552B6 @@ -8053,7 +8040,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 249 "N-000430" +Ne 251 "N-000435" Po -176 0 $EndPAD $PAD @@ -8065,7 +8052,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0603 -Po 67040 22310 0 15 4C5FF890 4C6552B1 ~~ +Po 65161 26102 0 15 4C5FF890 4C6552B1 ~~ Li 0603 Sc 4C6552B1 AR /4C5F1EDC/4C6552B1 @@ -8093,85 +8080,57 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 65770 21890 0 15 4C5FF890 4C6552B0 ~~ -Li 0603 -Sc 4C6552B0 -AR /4C5F1EDC/4C6552B0 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"L6" -T1 0 150 200 200 0 40 N I 25 N"FB" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 -$PAD -Sh "1" R 197 354 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 243 "N-000419" -Po -294 0 -$EndPAD -$PAD -Sh "2" R 197 354 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 294 0 -$EndPAD -$EndMODULE 0603 -$MODULE 0603 -Po 63977 19488 0 15 4C5FF890 4C63F252 ~~ +Po 56894 21752 900 0 4C5FF890 4C63F252 ~~ Li 0603 Sc 4C63F252 AR /4C5F1EDC/4C63F252 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"L4" -T1 0 150 200 200 0 40 N I 25 N"FB" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 +T0 0 150 200 200 900 40 M V 20 N"L4" +T1 0 -150 200 200 900 40 M I 20 N"FB" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 $PAD -Sh "1" R 197 354 0 0 0 +Sh "1" R 197 354 0 0 900 Dr 0 0 0 -At SMD N 00888000 -Ne 247 "N-000423" +At SMD N 00440001 +Ne 249 "N-000432" Po -294 0 $EndPAD $PAD -Sh "2" R 197 354 0 0 0 +Sh "2" R 197 354 0 0 900 Dr 0 0 0 -At SMD N 00888000 -Ne 246 "N-000422" +At SMD N 00440001 +Ne 247 "N-000430" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 58920 19610 0 15 4C5FF890 4C63F248 ~~ +Po 54949 19354 900 0 4C5FF890 4C63F248 ~~ Li 0603 Sc 4C63F248 AR /4C5F1EDC/4C63F248 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"L5" -T1 0 150 200 200 0 40 N I 25 N"FB" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 +T0 0 150 200 200 900 40 M V 20 N"L5" +T1 0 -150 200 200 900 40 M I 20 N"FB" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 $PAD -Sh "1" R 197 354 0 0 0 +Sh "1" R 197 354 0 0 900 Dr 0 0 0 -At SMD N 00888000 -Ne 245 "N-000421" +At SMD N 00440001 +Ne 248 "N-000431" Po -294 0 $EndPAD $PAD -Sh "2" R 197 354 0 0 0 +Sh "2" R 197 354 0 0 900 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 235 "GND" Po 294 0 $EndPAD @@ -8193,7 +8152,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Ban6" +Ne 45 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD @@ -8564,7 +8523,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Ban6" +Ne 45 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8585,7 +8544,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Ban5" +Ne 26 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD @@ -8620,7 +8579,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Ban5" +Ne 26 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8648,7 +8607,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Ban6" +Ne 45 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8669,7 +8628,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Ban6" +Ne 45 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD @@ -8697,7 +8656,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Ban5" +Ne 26 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD @@ -8732,18 +8691,18 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Ban5" +Ne 26 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE USB-48204 -Po 56354 18323 1800 15 4C5F28A8 4C5F23DD ~~ +Po 56799 18303 1800 15 4C5F28A8 4C71CC3A ~~ Li USB-48204 -Sc 4C5F23DD +Sc 4C71CC3A AR /4C5F1EDC/4C5F23DD Op 0 0 0 T0 120 -3162 157 157 1800 20 N V 21 N"J5" -T1 0 118 118 118 0 20 N I 21 N"USB-48204-0001" +T1 0 118 118 118 3600 20 N I 21 N"USB-48204-0001" DS -1499 5299 -1704 5299 60 21 DS -1704 5299 -1704 5178 60 21 DS -1704 5178 -1502 5178 60 21 @@ -8758,61 +8717,61 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 246 "N-000422" +Ne 247 "N-000430" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 242 "N-000415" +Ne 245 "N-000428" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 250 "N-000431" +Ne 246 "N-000429" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 250 "N-000431" +Ne 246 "N-000429" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 241 "N-000414" +Ne 250 "N-000433" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 241 "N-000414" +Ne 250 "N-000433" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 241 "N-000414" +Ne 250 "N-000433" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 241 "N-000414" +Ne 250 "N-000433" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 $MODULE 1210 -Po 67126 18110 1800 15 4C5FF890 4C5F2B55 ~~ +Po 55681 22516 1800 15 4C5FF890 4C5F2B55 ~~ Li 1210 Sc 4C5F2B55 AR /4C5F1EDC/4C5F2B55 @@ -8828,7 +8787,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 247 "N-000423" +Ne 249 "N-000432" Po -570 0 $EndPAD $PAD @@ -8884,7 +8843,7 @@ $PAD Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Etherne2" +Ne 47 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD @@ -8896,141 +8855,141 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 63976 23031 1800 15 4C5FF890 4C5F2033 ~~ +Po 55500 26343 1800 0 4C5FF890 4C5F2033 ~~ Li 0603 Sc 4C5F2033 AR /4C5F1EDC/4C5F2033 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C13" -T1 0 150 200 200 1800 40 N I 25 N"1uF" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C13" +T1 0 -150 200 200 1800 40 M I 20 N"1uF" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 4 "+3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 58465 22441 1800 15 4C5FF890 4C5F2037 ~~ +Po 55484 25740 1800 0 4C5FF890 4C5F2037 ~~ Li 0603 Sc 4C5F2037 AR /4C5F1EDC/4C5F2037 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C14" -T1 0 150 200 200 1800 40 N I 25 N"1uF" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C14" +T1 0 -150 200 200 1800 40 M I 20 N"1uF" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 4 "+3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 59843 22638 1800 15 4C5FF890 4C5F2039 ~~ +Po 56791 25996 1800 0 4C5FF890 4C5F2039 ~~ Li 0603 Sc 4C5F2039 AR /4C5F1EDC/4C5F2039 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C15" -T1 0 150 200 200 1800 40 N I 25 N"470nF" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C15" +T1 0 -150 200 200 1800 40 M I 20 N"470nF" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 3 "+2.5V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 61280 20050 1800 15 4C5FF890 4C5F2CA7 ~~ +Po 55921 19366 2700 0 4C5FF890 4C5F2CA7 ~~ Li 0603 Sc 4C5F2CA7 AR /4C5F1EDC/4C5F2CA7 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"V1" -T1 0 150 200 200 1800 40 N I 25 N"V0402MHS03" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 +T0 0 150 200 200 2700 40 M V 20 N"V1" +T1 0 -150 200 200 2700 40 M I 20 N"V0402MHS03" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 $PAD -Sh "1" R 197 354 0 0 1800 +Sh "1" R 197 354 0 0 2700 Dr 0 0 0 -At SMD N 00888000 -Ne 250 "N-000431" +At SMD N 00440001 +Ne 246 "N-000429" Po -294 0 $EndPAD $PAD -Sh "2" R 197 354 0 0 1800 +Sh "2" R 197 354 0 0 2700 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 235 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 60918 22141 1800 15 4C5FF890 4C5F2CA3 ~~ +Po 57838 19354 900 0 4C5FF890 4C5F2CA3 ~~ Li 0603 Sc 4C5F2CA3 AR /4C5F1EDC/4C5F2CA3 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"V2" -T1 0 150 200 200 1800 40 N I 25 N"V0402MHS03" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 +T0 0 150 200 200 900 40 M V 20 N"V2" +T1 0 -150 200 200 900 40 M I 20 N"V0402MHS03" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 $PAD -Sh "1" R 197 354 0 0 1800 +Sh "1" R 197 354 0 0 900 Dr 0 0 0 -At SMD N 00888000 -Ne 242 "N-000415" +At SMD N 00440001 +Ne 245 "N-000428" Po -294 0 $EndPAD $PAD -Sh "2" R 197 354 0 0 1800 +Sh "2" R 197 354 0 0 900 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 235 "GND" Po 294 0 $EndPAD @@ -9164,7 +9123,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/Etherne1" +Ne 46 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD @@ -9192,7 +9151,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 50 "/Etherne2" +Ne 47 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD @@ -9220,7 +9179,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 57 "/Etherne3" +Ne 52 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD @@ -9304,7 +9263,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 58 "/Etherne4" +Ne 65 "/Ethernet_Phy/MAG_SHIELD" Po -176 0 $EndPAD $PAD @@ -9316,29 +9275,29 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 61090 23610 1800 15 4C5FF890 4C5F2D1E ~~ +Po 56665 17409 1800 0 4C5FF890 4C5F2D1E ~~ Li 0402 Sc 4C5F2D1E AR /4C5F1EDC/4C5F2D1E Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C16" -T1 0 150 200 200 1800 40 N I 25 N"4.7nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C16" +T1 0 -150 200 200 1800 40 M I 20 N"4.7nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 241 "N-000414" +At SMD N 00440001 +Ne 250 "N-000433" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 235 "GND" Po 176 0 $EndPAD @@ -9360,7 +9319,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 54 "/Etherne21" +Ne 71 "/FPGA_Spartan6/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -9388,7 +9347,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 240 "N-000395" +Ne 238 "N-000401" Po -176 0 $EndPAD $PAD @@ -9423,7 +9382,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Etherne13" +Ne 66 "/Ethernet_Phy/MAG_TX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9451,7 +9410,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Etherne14" +Ne 67 "/Ethernet_Phy/MAG_TX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9479,7 +9438,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/Etherne15" +Ne 63 "/Ethernet_Phy/MAG_RX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9507,7 +9466,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/Etherne16" +Ne 64 "/Ethernet_Phy/MAG_RX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9528,14 +9487,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 238 "N-000393" +Ne 239 "N-000405" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 55 "/Etherne22" +Ne 50 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9556,14 +9515,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 239 "N-000394" +Ne 240 "N-000406" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 56 "/Etherne23" +Ne 51 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9584,7 +9543,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 58 "/Etherne4" +Ne 65 "/Ethernet_Phy/MAG_SHIELD" Po -176 0 $EndPAD $PAD @@ -9596,29 +9555,29 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 61115 22732 1800 15 4C5FF890 4C5F2D27 ~~ +Po 56665 16760 1800 0 4C5FF890 4C5F2D27 ~~ Li 0402 Sc 4C5F2D27 AR /4C5F1EDC/4C5F2D27 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"R10" -T1 0 150 200 200 1800 40 N I 25 N"1M" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"R10" +T1 0 -150 200 200 1800 40 M I 20 N"1M" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 241 "N-000414" +At SMD N 00440001 +Ne 250 "N-000433" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 235 "GND" Po 176 0 $EndPAD @@ -9648,7 +9607,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Sp140" +Ne 90 "/FPGA_Spartan6/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -9662,14 +9621,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Sp139" +Ne 16 "/DDR_Banks/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Ban138" +Ne 93 "/FPGA_Spartan6/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -9683,14 +9642,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Sp137" +Ne 94 "/FPGA_Spartan6/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Sp132" +Ne 95 "/FPGA_Spartan6/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -9704,14 +9663,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Ban131" +Ne 21 "/DDR_Banks/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Ban130" +Ne 96 "/FPGA_Spartan6/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -9725,7 +9684,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Sp129" +Ne 97 "/FPGA_Spartan6/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -9746,7 +9705,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Sp164" +Ne 24 "/DDR_Banks/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -9774,28 +9733,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Sp163" +Ne 23 "/DDR_Banks/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Ban162" +Ne 27 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Sp161" +Ne 87 "/FPGA_Spartan6/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Sp156" +Ne 25 "/DDR_Banks/M0_RAS#" Po 1535 2176 $EndPAD $PAD @@ -9816,49 +9775,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Sp155" +Ne 86 "/FPGA_Spartan6/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Sp154" +Ne 14 "/DDR_Banks/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Sp153" +Ne 78 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Sp148" +Ne 10 "/DDR_Banks/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Sp147" +Ne 77 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Sp146" +Ne 81 "/FPGA_Spartan6/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Sp145" +Ne 82 "/FPGA_Spartan6/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -9879,56 +9838,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M0_A4" +Ne 83 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Sp169" +Ne 11 "/DDR_Banks/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Sp170" +Ne 84 "/FPGA_Spartan6/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M0_A7" +Ne 12 "/DDR_Banks/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Sp175" +Ne 85 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Sp176" +Ne 13 "/DDR_Banks/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Sp177" +Ne 79 "/FPGA_Spartan6/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Ban178" +Ne 80 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -9942,28 +9901,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_Sp35" +Ne 89 "/FPGA_Spartan6/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Ban41" +Ne 88 "/FPGA_Spartan6/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_Sp34" +Ne 15 "/DDR_Banks/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Ban39" +Ne 99 "/FPGA_Spartan6/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -9977,7 +9936,7 @@ $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Ban5" +Ne 26 "/DDR_Banks/M0_VREF" Po 255 -2176 $EndPAD $PAD @@ -9991,7 +9950,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/FPGA_Sp37" +Ne 100 "/FPGA_Spartan6/M0_UDQS" Po -255 -2176 $EndPAD $PAD @@ -10012,7 +9971,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Sp124" +Ne 22 "/DDR_Banks/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10026,14 +9985,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Sp123" +Ne 98 "/FPGA_Spartan6/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Sp122" +Ne 17 "/DDR_Banks/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -10047,14 +10006,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Sp121" +Ne 91 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Ban116" +Ne 18 "/DDR_Banks/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10068,14 +10027,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Ban115" +Ne 92 "/FPGA_Spartan6/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Sp114" +Ne 19 "/DDR_Banks/M0_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10089,7 +10048,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Ban113" +Ne 20 "/DDR_Banks/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10125,7 +10084,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Ban80" +Ne 111 "/FPGA_Spartan6/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -10139,14 +10098,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Ban79" +Ne 112 "/FPGA_Spartan6/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 199 "/FPGA_Sp78" +Ne 40 "/DDR_Banks/M1_DQ2" Po -3070 2176 $EndPAD $PAD @@ -10160,14 +10119,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 198 "/FPGA_Sp77" +Ne 117 "/FPGA_Spartan6/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 193 "/FPGA_Sp72" +Ne 118 "/FPGA_Spartan6/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -10181,14 +10140,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 192 "/FPGA_Sp71" +Ne 119 "/FPGA_Spartan6/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Ban70" +Ne 120 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -10202,7 +10161,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/FPGA_Sp69" +Ne 41 "/DDR_Banks/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -10223,7 +10182,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 186 "/FPGA_Sp64" +Ne 123 "/FPGA_Spartan6/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -10251,35 +10210,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "/FPGA_Sp63" +Ne 122 "/FPGA_Spartan6/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Ban62" +Ne 125 "/FPGA_Spartan6/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/FPGA_Sp61" +Ne 109 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/FPGA_Sp56" +Ne 43 "/DDR_Banks/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Ban33" +Ne 110 "/FPGA_Spartan6/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -10293,49 +10252,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/FPGA_Sp55" +Ne 34 "/DDR_Banks/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Ban54" +Ne 108 "/FPGA_Spartan6/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Ban53" +Ne 103 "/FPGA_Spartan6/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/FPGA_Sp48" +Ne 101 "/FPGA_Spartan6/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/FPGA_Sp47" +Ne 102 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_A2" +Ne 104 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/FPGA_Sp46" +Ne 105 "/FPGA_Spartan6/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -10356,56 +10315,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_A4" +Ne 30 "/DDR_Banks/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 201 "/FPGA_Sp82" +Ne 31 "/DDR_Banks/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 200 "/FPGA_Sp81" +Ne 32 "/DDR_Banks/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/DDR_Banks/M1_A7" +Ne 33 "/DDR_Banks/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 207 "/FPGA_Sp88" +Ne 106 "/FPGA_Spartan6/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_A9" +Ne 107 "/FPGA_Spartan6/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 206 "/FPGA_Sp87" +Ne 28 "/DDR_Banks/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 205 "/FPGA_Sp86" +Ne 29 "/DDR_Banks/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -10419,28 +10378,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Ban24" +Ne 37 "/DDR_Banks/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/FPGA_Sp27" +Ne 35 "/DDR_Banks/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Ban25" +Ne 36 "/DDR_Banks/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Ban29" +Ne 44 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD @@ -10454,7 +10413,7 @@ $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Ban6" +Ne 45 "/DDR_Banks/M1_VREF" Po 255 -2176 $EndPAD $PAD @@ -10468,7 +10427,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/FPGA_Sp31" +Ne 124 "/FPGA_Spartan6/M1_UDQS" Po -255 -2176 $EndPAD $PAD @@ -10489,7 +10448,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Sp104" +Ne 42 "/DDR_Banks/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10503,14 +10462,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Sp103" +Ne 121 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Sp102" +Ne 113 "/FPGA_Spartan6/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -10524,14 +10483,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Ban101" +Ne 114 "/FPGA_Spartan6/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 216 "/FPGA_Sp96" +Ne 38 "/DDR_Banks/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10545,14 +10504,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 215 "/FPGA_Sp95" +Ne 39 "/DDR_Banks/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 214 "/FPGA_Sp94" +Ne 115 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10566,7 +10525,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 213 "/FPGA_Sp93" +Ne 116 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10593,35 +10552,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 58 "/Etherne4" +Ne 65 "/Ethernet_Phy/MAG_SHIELD" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 58 "/Etherne4" +Ne 65 "/Ethernet_Phy/MAG_SHIELD" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 58 "/Etherne4" +Ne 65 "/Ethernet_Phy/MAG_SHIELD" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 58 "/Etherne4" +Ne 65 "/Ethernet_Phy/MAG_SHIELD" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 40 "/Etherne13" +Ne 66 "/Ethernet_Phy/MAG_TX+" Po -1750 -2500 $EndPAD $PAD @@ -10642,14 +10601,14 @@ $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 42 "/Etherne15" +Ne 63 "/Ethernet_Phy/MAG_RX+" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 41 "/Etherne14" +Ne 67 "/Ethernet_Phy/MAG_TX-" Po -1250 -3500 $EndPAD $PAD @@ -10670,7 +10629,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 43 "/Etherne16" +Ne 64 "/Ethernet_Phy/MAG_RX-" Po 1750 -3500 $EndPAD $PAD @@ -10684,7 +10643,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 238 "N-000393" +Ne 239 "N-000405" Po -1150 -5400 $EndPAD $PAD @@ -10698,12 +10657,12 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 239 "N-000394" +Ne 240 "N-000406" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 $MODULE MICROSD-500901 -Po 75850 29854 0 0 4C5F34DA 4B76F5E2 ~~ +Po 62118 16012 0 0 4C5F34DA 4B76F5E2 ~~ Li MICROSD-500901 Sc 4B76F5E2 AR /4C4227FE/4B76F5E2 @@ -10723,21 +10682,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 230 "/Non_vol7" +Ne 218 "/FPGA_Spartan6/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 231 "/Non_vol8" +Ne 230 "/Non_volatile_memories/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 209 "/FPGA_Sp9" +Ne 216 "/FPGA_Spartan6/SD_CMD" Po -433 0 $EndPAD $PAD @@ -10751,7 +10710,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 220 "/Non_vol10" +Ne 215 "/FPGA_Spartan6/SD_CLK" Po 433 0 $EndPAD $PAD @@ -10765,14 +10724,14 @@ $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 221 "/Non_vol11" +Ne 217 "/FPGA_Spartan6/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 222 "/Non_vol12" +Ne 229 "/Non_volatile_memories/SD_DAT1" Po 1732 0 $EndPAD $PAD @@ -11064,28 +11023,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_Sp190" +Ne 227 "/Non_volatile_memories/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_Sp190" +Ne 227 "/Non_volatile_memories/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 226 "/Non_vol208" +Ne 226 "/Non_volatile_memories/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "/Non_vol215" +Ne 222 "/Non_volatile_memories/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -11134,21 +11093,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/FPGA_Sp198" +Ne 221 "/Non_volatile_memories/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 223 "/Non_vol189" +Ne 220 "/Non_volatile_memories/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 225 "/Non_vol207" +Ne 228 "/Non_volatile_memories/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -11225,28 +11184,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA_Sp206" +Ne 223 "/Non_volatile_memories/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 228 "/Non_vol214" +Ne 126 "/FPGA_Spartan6/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_Sp188" +Ne 224 "/Non_volatile_memories/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/FPGA_Sp197" +Ne 127 "/FPGA_Spartan6/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -11309,28 +11268,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Sp187" +Ne 128 "/FPGA_Spartan6/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 224 "/Non_vol205" +Ne 129 "/FPGA_Spartan6/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Sp186" +Ne 225 "/Non_volatile_memories/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 227 "/Non_vol213" +Ne 130 "/FPGA_Spartan6/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -11387,21 +11346,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Etherne195" +Ne 56 "/Ethernet_Phy/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Etherne182" +Ne 53 "/Ethernet_Phy/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Sp181" +Ne 75 "/FPGA_Spartan6/ETH_RXDV" Po -1613 491 $EndPAD $PAD @@ -11422,63 +11381,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Etherne194" +Ne 54 "/Ethernet_Phy/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Etherne180" +Ne 73 "/FPGA_Spartan6/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Etherne200" +Ne 55 "/Ethernet_Phy/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/FPGA_Sp199" +Ne 74 "/FPGA_Spartan6/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Etherne209" +Ne 70 "/FPGA_Spartan6/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Etherne21" +Ne 71 "/FPGA_Spartan6/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/FPGA_Sp201" +Ne 72 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/Etherne3" +Ne 52 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Sp179" +Ne 48 "/Ethernet_Phy/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -11513,14 +11472,14 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Etherne13" +Ne 66 "/Ethernet_Phy/MAG_TX+" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Etherne14" +Ne 67 "/Ethernet_Phy/MAG_TX-" Po 491 -1613 $EndPAD $PAD @@ -11534,35 +11493,35 @@ $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Etherne2" +Ne 47 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 240 "N-000395" +Ne 238 "N-000401" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Etherne185" +Ne 49 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Etherne22" +Ne 50 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/Etherne23" +Ne 51 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -11590,21 +11549,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Etherne1" +Ne 46 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Etherne16" +Ne 64 "/Ethernet_Phy/MAG_RX-" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Etherne15" +Ne 63 "/Ethernet_Phy/MAG_RX+" Po 1613 -491 $EndPAD $PAD @@ -11639,63 +11598,63 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA_Sp210" +Ne 62 "/Ethernet_Phy/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Etherne202" +Ne 57 "/Ethernet_Phy/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA_Sp211" +Ne 61 "/Ethernet_Phy/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_Sp212" +Ne 58 "/Ethernet_Phy/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/FPGA_Sp203" +Ne 76 "/FPGA_Spartan6/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA_Sp204" +Ne 59 "/Ethernet_Phy/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Sp183" +Ne 60 "/Ethernet_Phy/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Sp184" +Ne 68 "/FPGA_Spartan6/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Etherne196" +Ne 69 "/FPGA_Spartan6/ETH_CRS" Po 688 1613 $EndPAD $PAD @@ -11742,7 +11701,7 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE SOT23-5 -Po 61220 48622 900 15 451B82FA 4C6D2BAF ~~ +Po 70669 16964 900 15 451B82FA 4C6D2BAF ~~ Li SOT23-5 Cd SOT23-5 Sc 4C6D2BAF @@ -11759,21 +11718,21 @@ $PAD Sh "1" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 253 "N-000434" +Ne 256 "N-000444" Po -375 500 $EndPAD $PAD Sh "3" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 255 "N-000445" +Ne 258 "N-000455" Po 375 500 $EndPAD $PAD Sh "5" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 254 "N-000435" +Ne 257 "N-000445" Po -375 -500 $EndPAD $PAD @@ -11787,7 +11746,7 @@ $PAD Sh "4" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 253 "N-000434" +Ne 256 "N-000444" Po 375 -500 $EndPAD $SHAPE3D @@ -11815,21 +11774,21 @@ $PAD Sh "1" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 251 "N-000432" +Ne 254 "N-000442" Po -375 500 $EndPAD $PAD Sh "3" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 256 "N-000464" +Ne 259 "N-000474" Po 375 500 $EndPAD $PAD Sh "5" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 252 "N-000433" +Ne 255 "N-000443" Po -375 -500 $EndPAD $PAD @@ -11843,7 +11802,7 @@ $PAD Sh "4" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 251 "N-000432" +Ne 254 "N-000442" Po 375 -500 $EndPAD $SHAPE3D @@ -11854,7 +11813,7 @@ Ro 0.000000 0.000000 0.000000 $EndSHAPE3D $EndMODULE SOT23-5 $MODULE 0402 -Po 63582 49213 2700 15 4C5FF890 4C6D30F3 ~~ +Po 73031 17555 2700 15 4C5FF890 4C6D30F3 ~~ Li 0402 Sc 4C6D30F3 AR /4C69ED5F/4C6D2C7F @@ -11877,12 +11836,12 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 254 "N-000435" +Ne 257 "N-000445" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 62401 49213 900 15 4C5FF890 4C6D30F5 ~~ +Po 71850 17555 900 15 4C5FF890 4C6D30F5 ~~ Li 0402 Sc 4C6D30F5 AR /4C69ED5F/4C6D2DBC @@ -11898,7 +11857,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 254 "N-000435" +Ne 257 "N-000445" Po -176 0 $EndPAD $PAD @@ -11910,7 +11869,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 62992 49213 2700 15 4C5FF890 4C6D30F7 ~~ +Po 72441 17555 2700 15 4C5FF890 4C6D30F7 ~~ Li 0402 Sc 4C6D30F7 AR /4C69ED5F/4C6D2DDD @@ -11933,12 +11892,12 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 254 "N-000435" +Ne 257 "N-000445" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 65945 48622 2700 15 4C5FF890 4C6D30F9 ~~ +Po 75394 16964 2700 15 4C5FF890 4C6D30F9 ~~ Li 0402 Sc 4C6D30F9 AR /4C69ED5F/4C6D2F0B @@ -12017,7 +11976,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 252 "N-000433" +Ne 255 "N-000443" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12038,7 +11997,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 252 "N-000433" +Ne 255 "N-000443" Po -176 0 $EndPAD $PAD @@ -12073,12 +12032,12 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 252 "N-000433" +Ne 255 "N-000443" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0805 -Po 60039 48622 2700 15 4C5FF890 4C6D3102 ~~ +Po 69488 16964 2700 15 4C5FF890 4C6D3102 ~~ Li 0805 Sc 4C6D3102 AR /4C69ED5F/4C6D2C7C @@ -12094,7 +12053,7 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 253 "N-000434" +Ne 256 "N-000444" Po -373 0 $EndPAD $PAD @@ -12122,7 +12081,7 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 251 "N-000432" +Ne 254 "N-000442" Po -373 0 $EndPAD $PAD @@ -12134,7 +12093,7 @@ Po 373 0 $EndPAD $EndMODULE 0805 $MODULE 1206 -Po 64763 48622 2700 15 4C5FF890 4C6D3105 ~~ +Po 74212 16964 2700 15 4C5FF890 4C6D3105 ~~ Li 1206 Sc 4C6D3105 AR /4C69ED5F/4C6D2C83 @@ -12190,7 +12149,7 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE 1210 -Po 62993 48031 1800 15 4C5FF890 4C6D3108 ~~ +Po 72442 16373 1800 15 4C5FF890 4C6D3108 ~~ Li 1210 Sc 4C6D3108 AR /4C69ED5F/4C6D2E6A @@ -12213,7 +12172,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 255 "N-000445" +Ne 258 "N-000455" Po 570 0 $EndPAD $EndMODULE 1210 @@ -12241,7 +12200,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 256 "N-000464" +Ne 259 "N-000474" Po 570 0 $EndPAD $EndMODULE 1210 @@ -12269,7 +12228,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 50 "/Etherne2" +Ne 47 "/Ethernet_Phy/ETH_A3.3V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -12297,7 +12256,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 236 "N-000127" +Ne 236 "N-000267" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12325,131 +12284,131 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 237 "N-000132" +Ne 237 "N-000390" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE pin_array_8x2 -Po 78098 24118 0 15 3FB38B89 4C716CF9 ~~ +Po 67276 22906 900 15 3FB38B89 4C716CF9 ~~ Li pin_array_8x2 Cd Double rangee de contacts 2 x 8 pins Kw CONN Sc 4C716CF9 AR /4C716A4D/4C716CAB Op 0 0 0 -T0 0 -1300 400 400 0 80 N V 21 N"J6" -T1 0 1300 400 400 0 80 N V 21 N"CONN_8X2" +T0 0 -1300 400 400 900 80 N V 21 N"J6" +T1 0 1300 400 400 900 80 N V 21 N"CONN_8X2" DS -3900 900 -3900 -900 120 21 DS -3900 -900 3900 -900 120 21 DS 3900 -900 3900 900 120 21 DS 3900 900 -3900 900 120 21 $PAD -Sh "1" R 600 600 0 0 0 +Sh "1" R 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF -Ne 6 "/DBG_PRG17" +Ne 6 "/DBG_PRG/FPGA_TCK" Po -3500 500 $EndPAD $PAD -Sh "2" C 600 600 0 0 0 +Sh "2" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po -3500 -500 $EndPAD $PAD -Sh "3" C 600 600 0 0 0 +Sh "3" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF -Ne 7 "/DBG_PRG18" +Ne 9 "/DBG_PRG/FPGA_TMS" Po -2500 500 $EndPAD $PAD -Sh "4" C 600 600 0 0 0 +Sh "4" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po -2500 -500 $EndPAD $PAD -Sh "5" C 600 600 0 0 0 +Sh "5" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF -Ne 8 "/DBG_PRG19" +Ne 8 "/DBG_PRG/FPGA_TDO" Po -1500 500 $EndPAD $PAD -Sh "6" C 600 600 0 0 0 +Sh "6" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po -1500 -500 $EndPAD $PAD -Sh "7" C 600 600 0 0 0 +Sh "7" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF -Ne 9 "/DBG_PRG20" +Ne 7 "/DBG_PRG/FPGA_TDI" Po -500 500 $EndPAD $PAD -Sh "8" C 600 600 0 0 0 +Sh "8" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po -500 -500 $EndPAD $PAD -Sh "9" C 600 600 0 0 0 +Sh "9" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po 500 500 $EndPAD $PAD -Sh "10" C 600 600 0 0 0 +Sh "10" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po 500 -500 $EndPAD $PAD -Sh "11" C 600 600 0 0 0 +Sh "11" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po 1500 500 $EndPAD $PAD -Sh "12" C 600 600 0 0 0 +Sh "12" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po 1500 -500 $EndPAD $PAD -Sh "13" C 600 600 0 0 0 +Sh "13" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po 2500 500 $EndPAD $PAD -Sh "14" C 600 600 0 0 0 +Sh "14" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po 2500 -500 $EndPAD $PAD -Sh "15" C 600 600 0 0 0 +Sh "15" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" Po 3500 500 $EndPAD $PAD -Sh "16" C 600 600 0 0 0 +Sh "16" C 600 600 0 0 900 Dr 400 0 0 At STD N 00E0FFFF Ne 0 "" @@ -12463,272 +12422,686 @@ Ro 0.000000 0.000000 0.000000 $EndSHAPE3D $EndMODULE pin_array_8x2 $MODULE MLF16 -Po 69598 31752 0 15 4C71B372 4C71BB0D ~~ +Po 57752 27272 0 0 4C71B372 4C71BB0D ~~ Li MLF16 Sc 4C71BB0D AR /4C5F1EDC/4C71BA25 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"U7" -T1 0 150 200 200 0 40 N I 25 N"MIC2550-MLF" -DC -669 -669 -669 -747 39 21 -DS -590 590 -590 -590 39 21 -DS -590 -590 590 -590 39 21 -DS 590 -590 590 590 39 21 -DS 590 590 -590 590 39 21 +T0 0 150 200 200 0 40 M V 20 N"U7" +T1 0 -150 200 200 0 40 M I 20 N"MIC2550-MLF" +DC -669 669 -669 747 39 20 +DS -590 -590 -590 590 39 20 +DS -590 590 590 590 39 20 +DS 590 590 590 -590 39 20 +DS 590 -590 -590 -590 39 20 $PAD Sh "PAD" R 590 590 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 0 "" Po 0 0 $EndPAD $PAD Sh "12" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 4 "+3.3V" -Po -295 491 +Po -295 -491 $EndPAD $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 0 "" -Po -295 -491 +Po -295 491 $EndPAD $PAD Sh "11" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 244 "N-000420" -Po -98 491 +At SMD N 00440001 +Ne 244 "N-000427" +Po -98 -491 $EndPAD $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 0 "" -Po -98 -491 +Po -98 491 $EndPAD $PAD Sh "10" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 248 "N-000429" -Po 98 491 +At SMD N 00440001 +Ne 243 "N-000422" +Po 98 -491 $EndPAD $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 0 "" -Po 98 -491 +Po 98 491 $EndPAD $PAD Sh "9" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 295 491 -$EndPAD -$PAD -Sh "4" R 98 157 0 0 0 -Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 0 "" Po 295 -491 $EndPAD $PAD +Sh "4" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 295 491 +$EndPAD +$PAD Sh "16" R 157 98 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -491 -295 -$EndPAD -$PAD -Sh "5" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 491 -295 -$EndPAD -$PAD -Sh "15" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 3 "+2.5V" -Po -491 -98 -$EndPAD -$PAD -Sh "6" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 235 "GND" -Po 491 -98 -$EndPAD -$PAD -Sh "14" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 4 "+3.3V" -Po -491 98 -$EndPAD -$PAD -Sh "7" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 235 "GND" -Po 491 98 -$EndPAD -$PAD -Sh "13" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 0 "" Po -491 295 $EndPAD $PAD -Sh "8" R 157 98 0 0 0 +Sh "5" R 157 98 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 0 "" Po 491 295 $EndPAD +$PAD +Sh "15" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -491 98 +$EndPAD +$PAD +Sh "6" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 235 "GND" +Po 491 98 +$EndPAD +$PAD +Sh "14" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -491 -98 +$EndPAD +$PAD +Sh "7" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 235 "GND" +Po 491 -98 +$EndPAD +$PAD +Sh "13" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -491 -295 +$EndPAD +$PAD +Sh "8" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 491 -295 +$EndPAD $EndMODULE MLF16 $MODULE MLF16 -Po 70441 37512 0 15 4C71B372 4C71BB0F ~~ +Po 55717 27272 0 0 4C71B372 4C71BB0F ~~ Li MLF16 Sc 4C71BB0F AR /4C5F1EDC/4C71BA1D Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"U6" -T1 0 150 200 200 0 40 N I 25 N"MIC2550-MLF" -DC -669 -669 -669 -747 39 21 -DS -590 590 -590 -590 39 21 -DS -590 -590 590 -590 39 21 -DS 590 -590 590 590 39 21 -DS 590 590 -590 590 39 21 +T0 0 150 200 200 0 40 M V 20 N"U6" +T1 0 -150 200 200 0 40 M I 20 N"MIC2550-MLF" +DC -669 669 -669 747 39 20 +DS -590 -590 -590 590 39 20 +DS -590 590 590 590 39 20 +DS 590 590 590 -590 39 20 +DS 590 -590 -590 -590 39 20 $PAD Sh "PAD" R 590 590 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 0 "" Po 0 0 $EndPAD $PAD Sh "12" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 4 "+3.3V" -Po -295 491 +Po -295 -491 $EndPAD $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 233 "/USB/USBA_SPD" -Po -295 -491 +At SMD N 00440001 +Ne 232 "/USB/USBA_SPD" +Po -295 491 $EndPAD $PAD Sh "11" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 250 "N-000431" -Po -98 491 +At SMD N 00440001 +Ne 246 "N-000429" +Po -98 -491 $EndPAD $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 151 "/FPGA_Sp217" -Po -98 -491 +At SMD N 00440001 +Ne 231 "/USB/USBA_RCV" +Po -98 491 $EndPAD $PAD Sh "10" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 242 "N-000415" -Po 98 491 +At SMD N 00440001 +Ne 245 "N-000428" +Po 98 -491 $EndPAD $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 234 "/USB/USBA_VP" -Po 98 -491 +Po 98 491 $EndPAD $PAD Sh "9" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 232 "/USB/USBA_OE_N" -Po 295 491 +At SMD N 00440001 +Ne 219 "/FPGA_Spartan6/USBA_OE_N" +Po 295 -491 $EndPAD $PAD Sh "4" R 98 157 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 150 "/FPGA_Sp216" -Po 295 -491 +At SMD N 00440001 +Ne 233 "/USB/USBA_VM" +Po 295 491 $EndPAD $PAD Sh "16" R 157 98 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po -491 -295 -$EndPAD -$PAD -Sh "5" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 0 "" -Po 491 -295 -$EndPAD -$PAD -Sh "15" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 3 "+2.5V" -Po -491 -98 -$EndPAD -$PAD -Sh "6" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 235 "GND" -Po 491 -98 -$EndPAD -$PAD -Sh "14" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 4 "+3.3V" -Po -491 98 -$EndPAD -$PAD -Sh "7" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 235 "GND" -Po 491 98 -$EndPAD -$PAD -Sh "13" R 157 98 0 0 0 -Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 0 "" Po -491 295 $EndPAD $PAD +Sh "5" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 491 295 +$EndPAD +$PAD +Sh "15" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -491 98 +$EndPAD +$PAD +Sh "6" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 235 "GND" +Po 491 98 +$EndPAD +$PAD +Sh "14" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -491 -98 +$EndPAD +$PAD +Sh "7" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 235 "GND" +Po 491 -98 +$EndPAD +$PAD +Sh "13" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -491 -295 +$EndPAD +$PAD Sh "8" R 157 98 0 0 0 Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 491 -295 +$EndPAD +$EndMODULE MLF16 +$MODULE 0402 +Po 47380 42317 0 15 4C5FF890 4C71CB3B ~~ +Li 0402 +Sc 4C71CB3B +AR /4C5F1EDC/4C71C9BD +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R31" +T1 0 150 200 200 0 40 N I 25 N"1M" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 253 "N-000441" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47380 42317 0 15 4C5FF890 4C71CB3D ~~ +Li 0402 +Sc 4C71CB3D +AR /4C5F1EDC/4C71C9BE +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C89" +T1 0 150 200 200 0 40 N I 25 N"4.7nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 253 "N-000441" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47380 42317 0 15 4C5FF890 4C71CB3F ~~ +Li 0402 +Sc 4C71CB3F +AR /4C5F1EDC/4C71C9C3 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C88" +T1 0 150 200 200 0 40 N I 25 N"470nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 47380 42317 0 15 4C5FF890 4C71CB40 ~~ +Li 0603 +Sc 4C71CB40 +AR /4C5F1EDC/4C71C9B8 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L10" +T1 0 150 200 200 0 40 N I 25 N"FB" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 241 "N-000415" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 At SMD N 00888000 Ne 0 "" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 47380 42317 0 15 4C5FF890 4C71CB42 ~~ +Li 0603 +Sc 4C71CB42 +AR /4C5F1EDC/4C71C9B9 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L11" +T1 0 150 200 200 0 40 N I 25 N"FB" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 47380 42317 0 15 4C5FF890 4C71CB44 ~~ +Li 0603 +Sc 4C71CB44 +AR /4C5F1EDC/4C71C9BF +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"V5" +T1 0 150 200 200 0 40 N I 25 N"V0402MHS03" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 242 "N-000417" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 47380 42317 0 15 4C5FF890 4C71CB46 ~~ +Li 0603 +Sc 4C71CB46 +AR /4C5F1EDC/4C71C9C0 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"V6" +T1 0 150 200 200 0 40 N I 25 N"V0402MHS03" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 252 "N-000440" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 47380 42317 0 15 4C5FF890 4C71CB48 ~~ +Li 0603 +Sc 4C71CB48 +AR /4C5F1EDC/4C71C9C4 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C87" +T1 0 150 200 200 0 40 N I 25 N"1uF" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 47380 42317 0 15 4C5FF890 4C71CB4A ~~ +Li 0603 +Sc 4C71CB4A +AR /4C5F1EDC/4C71C9C5 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C86" +T1 0 150 200 200 0 40 N I 25 N"1uF" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 1210 +Po 59748 22217 0 15 4C5FF890 4C71CB4B ~~ +Li 1210 +Sc 4C71CB4B +AR /4C5F1EDC/4C71C9C1 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"F2" +T1 0 150 200 200 0 40 N I 25 N"MICROSMD075F" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 241 "N-000415" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 5 "+5V" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE MLF16 +Po 50441 41610 0 0 4C71B372 4C71CB4C ~~ +Li MLF16 +Sc 4C71CB4C +AR /4C5F1EDC/4C71C9B0 +Op 0 0 0 +At SMD +T0 0 150 200 200 0 40 M V 20 N"U13" +T1 0 -150 200 200 0 40 M I 20 N"MIC2550-MLF" +DC -669 669 -669 747 39 20 +DS -590 -590 -590 590 39 20 +DS -590 590 590 590 39 20 +DS 590 590 590 -590 39 20 +DS 590 -590 -590 -590 39 20 +$PAD +Sh "PAD" R 590 590 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 0 0 +$EndPAD +$PAD +Sh "12" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -295 -491 +$EndPAD +$PAD +Sh "1" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -295 491 +$EndPAD +$PAD +Sh "11" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 242 "N-000417" +Po -98 -491 +$EndPAD +$PAD +Sh "2" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -98 491 +$EndPAD +$PAD +Sh "10" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 252 "N-000440" +Po 98 -491 +$EndPAD +$PAD +Sh "3" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 98 491 +$EndPAD +$PAD +Sh "9" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 295 -491 +$EndPAD +$PAD +Sh "4" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 295 491 +$EndPAD +$PAD +Sh "16" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -491 295 +$EndPAD +$PAD +Sh "5" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" Po 491 295 $EndPAD +$PAD +Sh "15" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -491 98 +$EndPAD +$PAD +Sh "6" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 235 "GND" +Po 491 98 +$EndPAD +$PAD +Sh "14" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -491 -98 +$EndPAD +$PAD +Sh "7" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 235 "GND" +Po 491 -98 +$EndPAD +$PAD +Sh "13" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -491 -295 +$EndPAD +$PAD +Sh "8" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 491 -295 +$EndPAD $EndMODULE MLF16 $COTATION Ge 0 25 0 @@ -12791,6 +13164,16 @@ Po 3 50069 27352 50069 27352 157 -1 De 15 1 2 0 0 Po 0 50071 27354 50069 27352 79 -1 De 15 0 2 0 0 +Po 3 58228 31224 58228 31224 157 -1 +De 15 1 3 0 0 +Po 0 58040 31412 58228 31224 79 -1 +De 15 0 3 0 0 +Po 0 58040 31426 58040 31412 79 -1 +De 15 0 3 0 800 +Po 0 58224 31220 58224 31209 79 -1 +De 0 0 3 0 0 +Po 0 58228 31224 58224 31220 79 -1 +De 0 0 3 0 0 Po 0 49556 39693 49556 39198 79 -1 De 15 0 3 0 800 Po 3 49539 39118 49539 39118 157 -1 @@ -12867,10 +13250,6 @@ Po 0 59221 31820 59221 31815 79 -1 De 15 0 3 0 800 Po 0 59221 31815 59394 31642 79 -1 De 15 0 3 0 0 -Po 0 58040 31426 58040 31412 79 -1 -De 15 0 3 0 800 -Po 0 58040 31412 58228 31224 79 -1 -De 15 0 3 0 0 Po 0 46323 30583 46323 29507 79 -1 De 15 0 3 0 0 Po 0 46323 29507 46430 29400 79 -1 @@ -13251,2843 +13630,2909 @@ Po 3 53317 30472 53317 30472 157 -1 De 15 1 4 0 0 Po 0 53317 30443 53317 30472 79 -1 De 15 0 4 0 0 -Po 0 47362 38082 47260 38082 39 -1 -De 0 0 11 0 800 -Po 0 46858 38484 46643 38484 39 -1 -De 15 0 11 0 400 -Po 0 46972 38370 46858 38484 39 -1 -De 15 0 11 0 0 -Po 3 46972 38370 46972 38370 157 -1 -De 15 1 11 0 0 -Po 0 47260 38082 46972 38370 39 -1 -De 0 0 11 0 0 -Po 0 47362 37689 47028 37689 39 -1 -De 0 0 12 0 800 -Po 0 47001 37716 46643 37716 39 -1 -De 15 0 12 0 400 -Po 0 47028 37689 47001 37716 39 -1 -De 15 0 12 0 0 -Po 3 47028 37689 47028 37689 157 -1 -De 15 1 12 0 0 -Po 0 46643 37204 46900 37204 39 -1 -De 15 0 13 0 800 -Po 0 47188 37492 47362 37492 39 -1 -De 0 0 13 0 400 -Po 0 47035 37339 47188 37492 39 -1 -De 0 0 13 0 0 -Po 3 47035 37339 47035 37339 157 -1 -De 15 1 13 0 0 -Po 0 46900 37204 47035 37339 39 -1 -De 15 0 13 0 0 -Po 0 49846 36142 50666 36142 39 -1 -De 0 0 14 0 800 -Po 0 50705 36181 50995 36181 39 -1 -De 15 0 14 0 400 -Po 0 50685 36161 50705 36181 39 -1 -De 15 0 14 0 0 -Po 3 50685 36161 50685 36161 157 -1 -De 15 1 14 0 0 -Po 0 50666 36142 50685 36161 39 -1 -De 0 0 14 0 0 -Po 0 49846 36338 50056 36338 39 -1 -De 0 0 15 0 800 -Po 0 50161 36437 50995 36437 39 -1 -De 15 0 15 0 400 -Po 0 50059 36335 50161 36437 39 -1 -De 15 0 15 0 0 -Po 3 50059 36335 50059 36335 157 -1 -De 15 1 15 0 0 -Po 0 50056 36338 50059 36335 39 -1 -De 0 0 15 0 0 -Po 0 49838 37693 50661 37693 39 -1 -De 0 0 16 0 800 -Po 0 50684 37716 50995 37716 39 -1 -De 15 0 16 0 400 -Po 0 50661 37693 50684 37716 39 -1 -De 15 0 16 0 0 -Po 3 50661 37693 50661 37693 157 -1 -De 15 1 16 0 0 -Po 0 49795 33823 50165 33823 39 -1 -De 0 0 17 0 800 -Po 0 50730 33623 50995 33623 39 -1 -De 15 0 17 0 400 -Po 0 50713 33606 50730 33623 39 -1 -De 15 0 17 0 0 -Po 0 50382 33606 50713 33606 39 -1 -De 15 0 17 0 0 -Po 3 50382 33606 50382 33606 157 -1 -De 15 1 17 0 0 -Po 0 50165 33823 50382 33606 39 -1 -De 0 0 17 0 0 -Po 0 47941 31937 47657 31937 39 -1 -De 0 0 18 0 800 -Po 0 47460 32599 46643 32599 39 -1 -De 15 0 18 0 400 -Po 0 47583 32476 47460 32599 39 -1 -De 15 0 18 0 0 -Po 0 47583 32011 47583 32476 39 -1 -De 15 0 18 0 0 -Po 0 47657 31937 47583 32011 39 -1 -De 15 0 18 0 0 -Po 3 47657 31937 47657 31937 157 -1 -De 15 1 18 0 0 -Po 0 46643 33879 47916 33879 39 -1 -De 15 0 23 0 800 -Po 0 48102 34055 48151 34055 39 -1 -De 0 0 23 0 400 -Po 0 47921 33874 48102 34055 39 -1 -De 0 0 23 0 0 -Po 3 47921 33874 47921 33874 157 -1 -De 15 1 23 0 0 -Po 0 47916 33879 47921 33874 39 -1 -De 15 0 23 0 0 -Po 0 46643 33367 47765 33367 39 -1 -De 15 0 24 0 800 -Po 0 48072 33189 48151 33268 39 -1 -De 0 0 24 0 400 -Po 0 47933 33189 48072 33189 39 -1 -De 0 0 24 0 0 -Po 0 47923 33199 47933 33189 39 -1 -De 0 0 24 0 0 -Po 3 47923 33199 47923 33199 157 -1 -De 15 1 24 0 0 -Po 0 47923 33209 47923 33199 39 -1 -De 15 0 24 0 0 -Po 0 47765 33367 47923 33209 39 -1 -De 15 0 24 0 0 -Po 0 46643 34391 47017 34391 79 -1 -De 15 0 25 0 800 -Po 0 47265 34290 47265 34154 79 -1 -De 0 0 25 0 400 -Po 0 47165 34390 47265 34290 79 -1 -De 0 0 25 0 0 -Po 0 47018 34390 47165 34390 79 -1 -De 0 0 25 0 0 -Po 3 47018 34390 47018 34390 157 -1 -De 15 1 25 0 0 -Po 0 47017 34391 47018 34390 79 -1 -De 15 0 25 0 0 -Po 0 47265 34646 47265 34154 79 -1 -De 0 0 25 0 C00 -Po 0 47265 33661 47265 34154 79 -1 -De 0 0 25 0 C00 -Po 0 47265 33169 47265 33661 79 -1 -De 0 0 25 0 C00 -Po 0 47937 31535 47145 31535 39 -1 -De 0 0 33 0 800 -Po 0 46843 30808 46643 30808 39 -1 -De 15 0 33 0 400 -Po 0 46941 30906 46843 30808 39 -1 -De 15 0 33 0 0 -Po 3 46941 30906 46941 30906 157 -1 -De 15 1 33 0 0 -Po 0 46941 31331 46941 30906 39 -1 -De 0 0 33 0 0 -Po 0 47145 31535 46941 31331 39 -1 -De 0 0 33 0 0 -Po 0 47937 30945 47646 30945 39 -1 -De 0 0 34 0 800 -Po 0 47417 31576 46643 31576 39 -1 -De 15 0 34 0 400 -Po 0 47575 31418 47417 31576 39 -1 -De 15 0 34 0 0 -Po 0 47575 31016 47575 31418 39 -1 -De 15 0 34 0 0 -Po 0 47646 30945 47575 31016 39 -1 -De 15 0 34 0 0 -Po 3 47646 30945 47646 30945 157 -1 -De 15 1 34 0 0 -Po 0 48577 24659 48579 24661 118 -1 -De 15 0 39 0 800 -Po 0 48528 25455 48499 25484 118 -1 -De 0 0 39 0 400 -Po 0 48528 25126 48528 25455 118 -1 -De 0 0 39 0 0 -Po 3 48528 25126 48528 25126 157 -1 -De 15 1 39 0 0 -Po 0 48579 25075 48528 25126 118 -1 -De 15 0 39 0 0 -Po 0 48579 24661 48579 25075 118 -1 -De 15 0 39 0 0 -Po 0 48499 25878 48499 25484 118 -1 -De 0 0 39 0 C00 -Po 0 47867 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58806 28196 58806 28197 39 -1 +De 15 0 227 0 0 +Po 0 58806 28197 57890 29113 39 -1 +De 15 0 227 0 0 +Po 0 57890 29113 57898 29105 39 -1 +De 15 0 227 0 0 +Po 0 60630 27434 60304 27434 39 -1 De 15 0 227 0 800 -Po 0 55945 31232 55953 31232 39 -1 +Po 0 60311 27296 60363 27244 39 -1 De 15 0 227 0 0 -Po 0 55953 31232 55957 31232 39 -1 +Po 0 60311 27427 60311 27296 39 -1 De 15 0 227 0 0 -Po 0 55933 31220 55945 31232 39 -1 +Po 0 60304 27434 60311 27427 39 -1 De 15 0 227 0 0 -Po 3 55933 31220 55933 31220 157 -1 -De 15 1 227 0 0 -Po 0 56071 31082 55933 31220 39 -1 -De 3 0 227 0 0 -Po 0 56071 29960 56071 31082 39 -1 -De 3 0 227 0 0 -Po 0 55032 28921 56071 29960 39 -1 -De 3 0 227 0 0 -Po 0 54606 28921 55032 28921 39 -1 -De 3 0 227 0 0 -Po 0 54409 28724 54606 28921 39 -1 -De 3 0 227 0 0 -Po 3 54409 28724 54409 28724 157 -1 -De 15 1 227 0 0 -Po 0 54390 28724 54409 28724 39 -1 +Po 0 60363 27244 60630 27244 39 -1 +De 15 0 227 0 400 +Po 0 60630 27244 60363 27244 39 -1 +De 15 0 227 0 800 +Po 0 59715 27287 58806 28196 39 -1 De 15 0 227 0 0 -Po 0 54382 28716 54390 28724 39 -1 +Po 0 58806 28196 58800 28202 39 -1 De 15 0 227 0 0 -Po 0 54382 28582 54382 28716 39 -1 +Po 0 60320 27287 59715 27287 39 -1 De 15 0 227 0 0 -Po 0 53434 27634 54382 28582 39 -1 +Po 0 60363 27244 60320 27287 39 -1 De 15 0 227 0 0 -Po 0 53437 24874 53504 24874 39 -1 -De 15 0 228 0 0 -Po 0 57252 31421 57252 31426 39 -1 -De 15 0 228 0 400 -Po 0 57075 31244 57252 31421 39 -1 -De 15 0 228 0 0 -Po 3 57075 31244 57075 31244 157 -1 -De 15 1 228 0 0 -Po 0 57059 31228 57075 31244 39 -1 -De 3 0 228 0 0 -Po 0 56429 31228 57059 31228 39 -1 -De 3 0 228 0 0 -Po 0 56272 31071 56429 31228 39 -1 -De 3 0 228 0 0 -Po 0 56272 29981 56272 31071 39 -1 -De 3 0 228 0 0 -Po 0 53669 27378 56272 29981 39 -1 -De 3 0 228 0 0 -Po 0 53669 25079 53669 27378 39 -1 -De 3 0 228 0 0 -Po 0 53520 24890 53669 25079 39 -1 -De 3 0 228 0 0 -Po 3 53520 24890 53520 24890 157 -1 -De 15 1 228 0 0 -Po 0 53504 24874 53520 24890 39 -1 -De 15 0 228 0 0 -Po 0 53461 24874 53476 24874 39 -1 -De 15 0 228 0 0 -Po 0 52930 24874 53437 24874 39 -1 +Po 0 60630 25074 60209 25074 39 -1 De 15 0 228 0 800 -Po 0 53437 24874 53461 24874 39 -1 +Po 0 57063 30843 57252 31032 39 -1 +De 15 0 228 0 400 +Po 0 57063 29213 57063 30843 39 -1 De 15 0 228 0 0 -Po 0 53461 24874 53457 24874 39 -1 +Po 0 59472 26804 57063 29213 39 -1 +De 15 0 228 0 0 +Po 0 59472 25811 59472 26804 39 -1 +De 15 0 228 0 0 +Po 0 60209 25074 59472 25811 39 -1 De 15 0 228 0 0 -Po 0 57571 29370 57571 29976 39 -1 -De 3 0 229 0 0 -Po 0 57271 31054 57445 31228 39 -1 -De 3 0 229 0 0 -Po 0 57271 30276 57271 31054 39 -1 -De 3 0 229 0 0 -Po 0 57571 29976 57271 30276 39 -1 -De 3 0 229 0 0 -Po 0 57646 31426 57643 31426 39 -1 -De 15 0 229 0 800 -Po 3 57445 31228 57445 31228 157 -1 -De 15 1 229 0 0 -Po 0 57643 31426 57445 31228 39 -1 -De 15 0 229 0 0 -Po 0 57441 31224 57441 31213 39 -1 -De 3 0 229 0 0 -Po 0 57445 31228 57441 31224 39 -1 -De 3 0 229 0 0 -Po 0 58327 28390 58217 28500 39 -1 -De 15 0 229 0 0 -Po 0 57567 29374 57567 29378 39 -1 -De 0 0 229 0 0 -Po 0 57567 29378 57567 29382 39 -1 -De 0 0 229 0 0 -Po 0 57571 29370 57567 29374 39 -1 -De 0 0 229 0 0 -Po 3 57571 29370 57571 29370 157 -1 -De 15 1 229 0 0 -Po 0 57586 29355 57571 29370 39 -1 -De 15 0 229 0 0 -Po 0 57586 29131 57586 29355 39 -1 -De 15 0 229 0 0 -Po 0 58217 28500 57586 29131 39 -1 -De 15 0 229 0 0 -Po 0 59873 26844 58327 28390 39 -1 -De 15 0 229 0 0 -Po 0 58327 28390 58324 28393 39 -1 -De 15 0 229 0 0 -Po 0 60630 26844 59873 26844 39 -1 -De 15 0 229 0 800 Po 0 48416 39693 48416 39180 79 -1 De 15 0 235 0 800 Po 0 48421 39165 48421 39173 79 -1 @@ -16579,28 +16958,28 @@ Po 3 48967 28159 48967 28159 157 -1 De 15 1 235 0 0 Po 0 48970 28156 48967 28159 79 -1 De 15 0 235 0 0 -Po 0 50207 24130 50207 23890 39 -1 -De 0 0 238 0 800 -Po 0 50207 23890 51374 22723 39 -1 -De 0 0 238 0 400 -Po 0 48889 24124 48074 23309 39 -1 -De 0 0 239 0 800 -Po 0 48074 23309 48074 22723 39 -1 -De 0 0 239 0 400 Po 0 47062 25190 46708 25190 39 -1 -De 15 0 240 0 800 +De 15 0 238 0 800 Po 0 46973 25193 47043 25263 39 -1 -De 0 0 240 0 400 +De 0 0 238 0 400 Po 0 46713 25193 46973 25193 39 -1 -De 0 0 240 0 0 +De 0 0 238 0 0 Po 0 46717 25161 46713 25193 39 -1 -De 0 0 240 0 0 +De 0 0 238 0 0 Po 3 46717 25161 46717 25161 157 -1 -De 15 1 240 0 0 +De 15 1 238 0 0 Po 0 46709 25191 46717 25161 39 -1 -De 15 0 240 0 0 +De 15 0 238 0 0 Po 0 46708 25190 46709 25191 39 -1 -De 15 0 240 0 0 +De 15 0 238 0 0 +Po 0 50207 24130 50207 23890 39 -1 +De 0 0 239 0 800 +Po 0 50207 23890 51374 22723 39 -1 +De 0 0 239 0 400 +Po 0 48889 24124 48074 23309 39 -1 +De 0 0 240 0 800 +Po 0 48074 23309 48074 22723 39 -1 +De 0 0 240 0 400 $EndTRACK $ZONE $EndZONE diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index e14a624..b9ba3c6 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,1744 +1,1730 @@ -# EESchema Netlist Version 1.1 created Sun 22 Aug 2010 07:04:19 PM COT +# EESchema Netlist Version 1.1 created Sun 22 Aug 2010 08:15:22 PM COT ( - ( /4C4320F3/4C5D7F9F 0603 C1 1uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D80ED 0402 C2 1uF - ( 1 +1.8V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA1 0402 C3 100nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D80F0 0402 C4 100nF - ( 1 +1.8V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA3 0402 C5 100nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D8104 0402 C6 100nF - ( 1 /Etherne1 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA5 0603 C7 1uF - ( 1 /Etherne2 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7FA7 0402 C8 100nF - ( 1 /Etherne2 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D8114 0402 C9 100nF - ( 1 /Etherne3 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E41 0402 C10 100nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E43 0402 C11 100nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7DCB 0402 C12 47nF - ( 1 /Etherne4 ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2033 0603 C13 1uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2037 0603 C14 1uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2039 0603 C15 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2D1E 0402 C16 4.7nF - ( 1 N-000414 ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CC73 0402 C17 100nF - ( 1 +2.5V ) - ( 2 /DDR_Ban5 ) - ) - ( /4C421DD3/4C61CC96 0402 C18 100nF - ( 1 /DDR_Ban5 ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CCE3 0402 C19 100nF - ( 1 +2.5V ) - ( 2 /DDR_Ban6 ) - ) - ( /4C421DD3/4C61CCE2 0402 C20 100nF - ( 1 /DDR_Ban6 ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF2F 0603 C21 1uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CEB9 0402 C22 100nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CEF7 0402 C23 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF17 0402 C24 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF16 0402 C25 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF27 0402 C26 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA0 0603 C27 1uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA5 0402 C28 100nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA4 0402 C29 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA2 0402 C30 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA3 0402 C31 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA1 0402 C32 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61D151 1206 C33 10uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61D1D4 1206 C34 10uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552BE 0805 C35 1uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552BD 0805 C36 1uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552BC 0402 C37 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C6552B7 0402 C38 4.7nF - ( 1 N-000430 ) - ( 2 GND ) - ) - ( /4C431A63/4C656A80 1210 C39 100uF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656BF8 1210 C40 100uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CB7 1210 C41 100uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656ABD 0805 C42 4.7uF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656BF9 0805 C43 4.7uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CB9 0805 C44 4.7uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656AC0 0402 C45 470nF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C16 0805 C46 4.7uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CBA 0402 C47 470nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656AC2 0402 C48 470nF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C24 0402 C49 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CBB 0402 C50 470nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C27 0402 C51 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656BFA 0402 C52 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C49 0402 C53 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D97 1210 C54 100uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D43 1210 C55 100uF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656CF9 1210 C56 100uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D98 0805 C57 4.7uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D44 0805 C58 4.7uF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656CFA 0805 C59 4.7uF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D99 0402 C60 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D45 0402 C61 470nF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656CFB 0402 C62 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D9A 0402 C63 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D46 0402 C64 470nF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656CFC 0402 C65 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D9D 0402 C66 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D49 0402 C67 470nF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656D08 0402 C68 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D53 0402 C69 470nF - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C421DD3/4C65D2A9 0402 C70 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C65D28E 0402 C71 10nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C4227FE/4C65D661 0402 C72 100nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4227FE/4C65D67C 0402 C73 100nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4227FE/4C65D681 0603 C74 1uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C4227FE/4C6969AB 0402 C75 100nF - ( 1 GND ) - ( 2 +3.3V ) - ) - ( /4C431A63/4C6B29A3 0402 C76 470nF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C6B29DA 0402 C77 470nF - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2C7C 0805 C78 4.7uF - ( 1 N-000434 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2C7F 0402 C79 22pF - ( 1 +3.3V ) - ( 2 N-000435 ) - ) - ( /4C69ED5F/4C6D2C83 1206 C80 10uF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2F0B 0402 C81 100nF - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2FD7 0805 C82 4.7uF - ( 1 N-000432 ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2FD6 0402 C83 22pF - ( 1 +1.2V ) - ( 2 N-000433 ) - ) - ( /4C69ED5F/4C6D2FD5 1206 C84 10uF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C69ED5F/4C6D2FD0 0402 C85 100nF - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C5F1EDC/4C5F2B55 1210 F1 MICROSMD075F - ( 1 N-000423 ) - ( 2 +5V ) - ) - ( /4C5F1EDC/4C6552BA 1210 F2 MICROSMD075F - ( 1 N-000419 ) - ( 2 +5V ) - ) - ( /4C4227FE/4B76F5E2 MICROSD-500901 J1 MICROSD - ( 1 /Non_vol7 ) - ( 2 /Non_vol8 ) - ( 3 /FPGA_Sp9 ) - ( 4 +3.3V ) - ( 5 /Non_vol10 ) - ( 6 GND ) - ( 7 /Non_vol11 ) - ( 8 /Non_vol12 ) + ( /4C716A4D/4C716CAB $noname J6 CONN_8X2 {Lib=CONN_8X2} + ( 1 /DBG_PRG/FPGA_TCK ) + ( 2 ? ) + ( 3 /DBG_PRG/FPGA_TMS ) + ( 4 ? ) + ( 5 /DBG_PRG/FPGA_TDO ) + ( 6 ? ) + ( 7 /DBG_PRG/FPGA_TDI ) + ( 8 ? ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 ? ) + ( 13 ? ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ) + ( /4C69ED5F/4C6D2FD7 0805 C82 4.7uF {Lib=CAP} + ( 1 N-000442 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2FD6 0402 C83 22pF {Lib=CAP} + ( 1 +1.2V ) + ( 2 N-000443 ) + ) + ( /4C69ED5F/4C6D2FD5 1206 C84 10uF {Lib=CAP} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2FD3 0402 R27 R {Lib=R} + ( 1 N-000443 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2FD2 0402 R28 R {Lib=R} + ( 1 +1.2V ) + ( 2 N-000443 ) + ) + ( /4C69ED5F/4C6D2FD1 1210 L9 2.2uH {Lib=INDUCTOR} + ( 1 +1.2V ) + ( 2 N-000474 ) + ) + ( /4C69ED5F/4C6D2FD0 0402 C85 100nF {Lib=CAP} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2F0B 0402 C81 100nF {Lib=CAP} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2E6A 1210 L8 2.2uH {Lib=INDUCTOR} + ( 1 +3.3V ) + ( 2 N-000455 ) + ) + ( /4C69ED5F/4C6D2DDD 0402 R26 R {Lib=R} + ( 1 +3.3V ) + ( 2 N-000445 ) + ) + ( /4C69ED5F/4C6D2DBC 0402 R25 R {Lib=R} + ( 1 N-000445 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2C83 1206 C80 10uF {Lib=CAP} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2C7F 0402 C79 22pF {Lib=CAP} + ( 1 +3.3V ) + ( 2 N-000445 ) + ) + ( /4C69ED5F/4C6D2C7C 0805 C78 4.7uF {Lib=CAP} + ( 1 N-000444 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2AE0 SOT23-5 U12 A7108 {Lib=A7108} + ( 1 N-000442 ) + ( 2 GND ) + ( 3 N-000474 ) + ( 4 N-000442 ) + ( 5 N-000443 ) + ) + ( /4C69ED5F/4C6D2AA5 SOT23-5 U11 A7108 {Lib=A7108} + ( 1 N-000444 ) + ( 2 GND ) + ( 3 N-000455 ) + ( 4 N-000444 ) + ( 5 N-000445 ) + ) + ( /4C69ED5F/4C6C9DB9 DFN10 U10 A7130 {Lib=A7130} + ( PAD GND ) + ( 1 ? ) + ( 2 GND ) + ( 3 ? ) + ( 4 ? ) + ( 5 GND ) + ( 6 ? ) + ( 7 ? ) + ( 8 ? ) + ( 9 ? ) + ( 10 ? ) + ) + ( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF} + ( PAD GND ) + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 ? ) + ( 7 ? ) + ( 8 GND ) + ( 9 ? ) + ( 10 ? ) + ( 11 ? ) + ( 12 ? ) + ( 13 ? ) + ( 14 ? ) + ( 15 ? ) + ( 16 ? ) + ( 17 ? ) + ( 18 ? ) + ( 19 ? ) + ( 20 ? ) + ) + ( /4C4227FE/4C6969AB $noname C75 100nF {Lib=C} + ( 1 GND ) + ( 2 +3.3V ) + ) + ( /4C4227FE/4C65D681 0603 C74 1uF {Lib=CAP} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65D67C 0402 C73 100nF {Lib=CAP} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65D661 0402 C72 100nF {Lib=CAP} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB} + ( 1 /FPGA_Spartan6/PROG_CSO ) + ( 2 /FPGA_Spartan6/PROG_MISO1 ) + ( 3 /FPGA_Spartan6/PROG_MISO2 ) + ( 4 GND ) + ( 5 /FPGA_Spartan6/PROG_MISO0 ) + ( 6 /FPGA_Spartan6/PROG_CCLK ) + ( 7 /FPGA_Spartan6/PROG_MISO3 ) + ( 8 VCCO2 ) + ) + ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} ( CASE GND ) - ( CD ? ) - ( COM GND ) + ( COM GND ) + ( CD ? ) + ( 1 /FPGA_Spartan6/SD_DAT2 ) + ( 2 /Non_volatile_memories/SD_DAT3 ) + ( 3 /FPGA_Spartan6/SD_CMD ) + ( 4 +3.3V ) + ( 5 /FPGA_Spartan6/SD_CLK ) + ( 6 GND ) + ( 7 /FPGA_Spartan6/SD_DAT0 ) + ( 8 /Non_volatile_memories/SD_DAT1 ) ) - ( /4C4320F3/4C5D6F5A SD-48025 J4 RJ45-48025 - ( 1 /Etherne13 ) - ( 2 /Etherne14 ) - ( 3 +3.3V ) - ( 4 GND ) - ( 5 GND ) - ( 6 +3.3V ) - ( 7 /Etherne15 ) - ( 8 /Etherne16 ) - ( 9 +3.3V ) - ( 10 N-000393 ) - ( 11 +3.3V ) - ( 12 N-000394 ) - ( 13 /Etherne4 ) - ( 14 /Etherne4 ) + ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 /Non_volatile_memories/NF_RNB ) + ( 7 /Non_volatile_memories/NF_RNB ) + ( 8 /Non_volatile_memories/NF_RE_N ) + ( 9 /Non_volatile_memories/NF_CS1_N ) + ( 10 ? ) + ( 11 ? ) + ( 12 +3.3V ) + ( 13 GND ) + ( 14 ? ) + ( 15 ? ) + ( 16 /Non_volatile_memories/NF_CLE ) + ( 17 /Non_volatile_memories/NF_ALE ) + ( 18 /Non_volatile_memories/NF_WE_N ) + ( 19 +3.3V ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 ? ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 ? ) + ( 29 /Non_volatile_memories/NF_D0 ) + ( 30 /FPGA_Spartan6/NF_D1 ) + ( 31 /Non_volatile_memories/NF_D2 ) + ( 32 /FPGA_Spartan6/NF_D3 ) + ( 33 ? ) + ( 34 ? ) + ( 35 ? ) + ( 36 GND ) + ( 37 +3.3V ) + ( 38 ? ) + ( 39 ? ) + ( 40 ? ) + ( 41 /FPGA_Spartan6/NF_D4 ) + ( 42 /FPGA_Spartan6/NF_D5 ) + ( 43 /Non_volatile_memories/NF_D6 ) + ( 44 /FPGA_Spartan6/NF_D7 ) + ( 45 ? ) + ( 46 ? ) + ( 47 ? ) + ( 48 ? ) ) - ( /4C5F1EDC/4C5F23DD USB-48204 J5 USB-48204-0001 - ( 1 N-000422 ) - ( 2 N-000415 ) - ( 3 N-000431 ) - ( 4 N-000421 ) - ( S1 N-000414 ) - ( S2 N-000414 ) - ( S3 N-000414 ) - ( S4 N-000414 ) + ( /4C5F1EDC/4C71C9C5 0603 C86 1uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C716A4D/4C716CAB pin_array_8x2 J6 CONN_8X2 - ( 1 /DBG_PRG17 ) - ( 2 ? ) - ( 3 /DBG_PRG18 ) - ( 4 ? ) - ( 5 /DBG_PRG19 ) - ( 6 ? ) - ( 7 /DBG_PRG20 ) - ( 8 ? ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 ? ) - ( 13 ? ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) + ( /4C5F1EDC/4C71C9C4 0603 C87 1uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D80F3 0402 L1 FB - ( 1 +1.8V ) - ( 2 /Etherne1 ) + ( /4C5F1EDC/4C71C9C3 0402 C88 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7FB7 0603 L2 FB - ( 1 +3.3V ) - ( 2 /Etherne2 ) + ( /4C5F1EDC/4C71C9C1 1210 F2 MICROSMD075F {Lib=MICROSMD075F} + ( 1 N-000415 ) + ( 2 +5V ) ) - ( /4C4320F3/4C5D810A 0402 L3 FB - ( 1 /Etherne1 ) - ( 2 /Etherne3 ) + ( /4C5F1EDC/4C71C9C0 0603 V6 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000440 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C63F252 0603 L4 FB - ( 1 N-000423 ) - ( 2 N-000422 ) + ( /4C5F1EDC/4C71C9BF 0603 V5 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000417 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C63F248 0603 L5 FB - ( 1 N-000421 ) - ( 2 GND ) + ( /4C5F1EDC/4C71C9BE 0402 C89 4.7nF {Lib=C} + ( 1 N-000441 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B0 0603 L6 FB - ( 1 N-000419 ) - ( 2 ? ) + ( /4C5F1EDC/4C71C9BD 0402 R31 1M {Lib=R} + ( 1 N-000441 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B1 0603 L7 FB - ( 1 ? ) - ( 2 GND ) + ( /4C5F1EDC/4C71C9B9 0603 L11 FB {Lib=INDUCTOR} + ( 1 ? ) + ( 2 GND ) ) - ( /4C69ED5F/4C6D2E6A 1210 L8 2.2uH - ( 1 +3.3V ) - ( 2 N-000445 ) + ( /4C5F1EDC/4C71C9B8 0603 L10 FB {Lib=INDUCTOR} + ( 1 N-000415 ) + ( 2 ? ) ) - ( /4C69ED5F/4C6D2FD1 1210 L9 2.2uH - ( 1 +1.2V ) - ( 2 N-000464 ) + ( /4C5F1EDC/4C71C9B0 MLF16 U13 MIC2550-MLF {Lib=MIC2550-MLF} + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 6 GND ) + ( 7 GND ) + ( 9 ? ) + ( 10 N-000440 ) + ( 11 N-000417 ) + ( 12 +3.3V ) + ( 14 +3.3V ) + ( 15 +2.5V ) ) - ( /4C4320F3/4C5D7F39 0402 R1 4.7K - ( 1 /Etherne21 ) - ( 2 +3.3V ) + ( /4C5F1EDC/4C71BA25 MLF16 U7 MIC2550-MLF {Lib=MIC2550-MLF} + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 6 GND ) + ( 7 GND ) + ( 9 ? ) + ( 10 N-000422 ) + ( 11 N-000427 ) + ( 12 +3.3V ) + ( 14 +3.3V ) + ( 15 +2.5V ) ) - ( /4C4320F3/4C5D7ECF 0402 R2 6.65K - ( 1 N-000395 ) - ( 2 GND ) + ( /4C5F1EDC/4C71BA1D MLF16 U6 MIC2550-MLF {Lib=MIC2550-MLF} + ( 1 /USB/USBA_SPD ) + ( 2 /USB/USBA_RCV ) + ( 3 /USB/USBA_VP ) + ( 4 /USB/USBA_VM ) + ( 6 GND ) + ( 7 GND ) + ( 9 /FPGA_Spartan6/USBA_OE_N ) + ( 10 N-000428 ) + ( 11 N-000429 ) + ( 12 +3.3V ) + ( 14 +3.3V ) + ( 15 +2.5V ) ) - ( /4C4320F3/4C5D7AFE 0402 R3 49.9 - ( 1 +3.3V ) - ( 2 /Etherne13 ) + ( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7AFC 0402 R4 49.9 - ( 1 +3.3V ) - ( 2 /Etherne14 ) + ( /4C5F1EDC/4C6552BD $noname C36 1uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7AF7 0402 R5 49.9 - ( 1 +3.3V ) - ( 2 /Etherne15 ) + ( /4C5F1EDC/4C6552BC $noname C37 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7AF9 0402 R6 49.9 - ( 1 +3.3V ) - ( 2 /Etherne16 ) + ( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000422 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D719D 0402 R7 220 - ( 1 N-000393 ) - ( 2 /Etherne22 ) + ( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000427 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D71DB 0402 R8 220 - ( 1 N-000394 ) - ( 2 /Etherne23 ) + ( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C} + ( 1 N-000435 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7DC4 0402 R9 1M - ( 1 /Etherne4 ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R} + ( 1 N-000435 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2D27 0402 R10 1M - ( 1 N-000414 ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} + ( 1 ? ) + ( 2 GND ) ) - ( /4C421DD3/4C61CD4A 0402 R11 1K_1% - ( 1 +2.5V ) - ( 2 /DDR_Ban5 ) + ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} + ( 1 N-000432 ) + ( 2 N-000430 ) ) - ( /4C421DD3/4C61CDB5 0402 R12 1K_1% - ( 1 /DDR_Ban5 ) - ( 2 GND ) + ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} + ( 1 N-000431 ) + ( 2 GND ) ) - ( /4C421DD3/4C61CE31 0402 R13 1K_1% - ( 1 +2.5V ) - ( 2 /DDR_Ban6 ) + ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} + ( 1 N-000433 ) + ( 2 GND ) ) - ( /4C421DD3/4C61CE30 0402 R14 1K_1% - ( 1 /DDR_Ban6 ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} + ( 1 N-000433 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B6 0402 R15 1M - ( 1 N-000430 ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000429 ) + ( 2 GND ) ) - ( /4C431A63/4C69DF7A 0402 R16 120 - ( 1 /DDR_Ban24 ) - ( 2 /DDR_Ban25 ) + ( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 {Lib=V0402MHS03} + ( 1 N-000428 ) + ( 2 GND ) ) - ( /4C431A63/4C69E7F8 0402 R17 33 - ( 1 /FPGA_Sp26 ) - ( 2 /FPGA_Sp27 ) + ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} + ( 1 N-000432 ) + ( 2 +5V ) ) - ( /4C431A63/4C69E7C2 0402 R18 33 - ( 1 /FPGA_Sp28 ) - ( 2 /DDR_Ban29 ) + ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} + ( S1 N-000433 ) + ( S2 N-000433 ) + ( S3 N-000433 ) + ( S4 N-000433 ) + ( 1 N-000430 ) + ( 2 N-000428 ) + ( 3 N-000429 ) + ( 4 N-000431 ) ) - ( /4C431A63/4C69E7DD 0402 R19 33 - ( 1 /FPGA_Sp30 ) - ( 2 /FPGA_Sp31 ) + ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C431A63/4C69E92D 0402 R20 33 - ( 1 /FPGA_Sp32 ) - ( 2 /DDR_Ban33 ) + ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C431A63/4C6B1B90 0402 R21 120 - ( 1 /FPGA_Sp34 ) - ( 2 /FPGA_Sp35 ) + ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C431A63/4C6B216D 0402 R22 33 - ( 1 /FPGA_Sp36 ) - ( 2 /FPGA_Sp37 ) + ( /4C431A63/4C7168DD 0402 R30 330 {Lib=R} + ( 1 +3.3V ) + ( 2 N-000267 ) ) - ( /4C431A63/4C6B216E 0402 R23 33 - ( 1 /FPGA_Sp38 ) - ( 2 /DDR_Ban39 ) + ( /4C431A63/4C716877 0402 R29 4.7k {Lib=R} + ( 1 +3.3V ) + ( 2 N-000390 ) ) - ( /4C431A63/4C6B216B 0402 R24 33 - ( 1 /FPGA_Sp40 ) - ( 2 /DDR_Ban41 ) + ( /4C431A63/4C6B29DA 0402 C77 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) ) - ( /4C69ED5F/4C6D2DBC 0402 R25 R - ( 1 N-000435 ) - ( 2 GND ) + ( /4C431A63/4C6B29A3 0402 C76 470nF {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) ) - ( /4C69ED5F/4C6D2DDD 0402 R26 R - ( 1 +3.3V ) - ( 2 N-000435 ) + ( /4C431A63/4C6B216E 0402 R23 33 {Lib=R} + ( 1 /FPGA_Spartan6/R_M0_UDM ) + ( 2 /FPGA_Spartan6/M0_UDM ) ) - ( /4C69ED5F/4C6D2FD3 0402 R27 R - ( 1 N-000433 ) - ( 2 GND ) + ( /4C431A63/4C6B216D 0402 R22 33 {Lib=R} + ( 1 /FPGA_Spartan6/R_M0_UDQS ) + ( 2 /FPGA_Spartan6/M0_UDQS ) ) - ( /4C69ED5F/4C6D2FD2 0402 R28 R - ( 1 +1.2V ) - ( 2 N-000433 ) + ( /4C431A63/4C6B216B 0402 R24 33 {Lib=R} + ( 1 /FPGA_Spartan6/R_M0_CKE ) + ( 2 /FPGA_Spartan6/M0_CKE ) ) - ( /4C431A63/4C716877 0402 R29 4.7k - ( 1 +3.3V ) - ( 2 N-000132 ) + ( /4C431A63/4C6B1B90 0402 R21 120 {Lib=R} + ( 1 /DDR_Banks/M0_CLK ) + ( 2 /FPGA_Spartan6/M0_CLK# ) ) - ( /4C431A63/4C7168DD 0402 R30 330 - ( 1 +3.3V ) - ( 2 N-000127 ) + ( /4C431A63/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_A0 ) + ( 2 /FPGA_Spartan6/R_M0_A1 ) + ( 3 /FPGA_Spartan6/R_M0_A2 ) + ( 4 /FPGA_Spartan6/R_M0_A3 ) + ( 5 /FPGA_Spartan6/M0_A3 ) + ( 6 /FPGA_Spartan6/M0_A2 ) + ( 7 /FPGA_Spartan6/M0_A1 ) + ( 8 /DDR_Banks/M0_A0 ) ) - ( /4C431A63/4C69C6B2 R_PACK4-0402 RP1 R_PACK4 - ( 1 /FPGA_Sp42 ) - ( 2 /FPGA_Sp43 ) - ( 3 /FPGA_Sp44 ) - ( 4 /FPGA_Sp45 ) - ( 5 /FPGA_Sp46 ) - ( 6 /DDR_Banks/M1_A2 ) - ( 7 /FPGA_Sp47 ) - ( 8 /FPGA_Sp48 ) + ( /4C431A63/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_RAS# ) + ( 2 /FPGA_Spartan6/R_M0_BA0 ) + ( 3 /FPGA_Spartan6/R_M0_BA1 ) + ( 4 /FPGA_Spartan6/R_M0_A10 ) + ( 5 /FPGA_Spartan6/M0_A10 ) + ( 6 /DDR_Banks/M0_BA1 ) + ( 7 /FPGA_Spartan6/M0_BA0 ) + ( 8 /DDR_Banks/M0_RAS# ) ) - ( /4C431A63/4C69CEE8 R_PACK4-0402 RP2 R_PACK4 - ( 1 /FPGA_Sp49 ) - ( 2 /FPGA_Sp50 ) - ( 3 /FPGA_Sp51 ) - ( 4 /FPGA_Sp52 ) - ( 5 /DDR_Ban53 ) - ( 6 /DDR_Ban54 ) - ( 7 /FPGA_Sp55 ) - ( 8 /FPGA_Sp56 ) + ( /4C431A63/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_LDQS ) + ( 2 /FPGA_Spartan6/R_M0_LDM ) + ( 3 /FPGA_Spartan6/R_M0_WE# ) + ( 4 /FPGA_Spartan6/R_M0_CAS# ) + ( 5 /FPGA_Spartan6/M0_CAS# ) + ( 6 /DDR_Banks/M0_WE# ) + ( 7 /DDR_Banks/M0_LDM ) + ( 8 /DDR_Banks/M0_LDQS ) ) - ( /4C431A63/4C69D3A4 R_PACK4-0402 RP3 R_PACK4 - ( 1 /FPGA_Sp57 ) - ( 2 /FPGA_Sp58 ) - ( 3 /FPGA_Sp59 ) - ( 4 /FPGA_Sp60 ) - ( 5 /FPGA_Sp61 ) - ( 6 /DDR_Ban62 ) - ( 7 /FPGA_Sp63 ) - ( 8 /FPGA_Sp64 ) + ( /4C431A63/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_A7 ) + ( 2 /FPGA_Spartan6/R_M0_A6 ) + ( 3 /FPGA_Spartan6/R_M0_A5 ) + ( 4 /FPGA_Spartan6/R_M0_A4 ) + ( 5 /FPGA_Spartan6/M0_A4 ) + ( 6 /DDR_Banks/M0_A5 ) + ( 7 /FPGA_Spartan6/M0_A6 ) + ( 8 /DDR_Banks/M0_A7 ) ) - ( /4C431A63/4C69D3A3 R_PACK4-0402 RP4 R_PACK4 - ( 1 /FPGA_Sp65 ) - ( 2 /FPGA_Sp66 ) - ( 3 /FPGA_Sp67 ) - ( 4 /FPGA_Sp68 ) - ( 5 /FPGA_Sp69 ) - ( 6 /DDR_Ban70 ) - ( 7 /FPGA_Sp71 ) - ( 8 /FPGA_Sp72 ) + ( /4C431A63/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_A12 ) + ( 2 /FPGA_Spartan6/R_M0_A11 ) + ( 3 /FPGA_Spartan6/R_M0_A9 ) + ( 4 /FPGA_Spartan6/R_M0_A8 ) + ( 5 /FPGA_Spartan6/M0_A8 ) + ( 6 /DDR_Banks/M0_A9 ) + ( 7 /FPGA_Spartan6/M0_A11 ) + ( 8 /FPGA_Spartan6/M0_A12 ) ) - ( /4C431A63/4C69D3A9 R_PACK4-0402 RP5 R_PACK4 - ( 1 /FPGA_Sp73 ) - ( 2 /FPGA_Sp74 ) - ( 3 /FPGA_Sp75 ) - ( 4 /FPGA_Sp76 ) - ( 5 /FPGA_Sp77 ) - ( 6 /FPGA_Sp78 ) - ( 7 /DDR_Ban79 ) - ( 8 /DDR_Ban80 ) + ( /4C431A63/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_DQ4 ) + ( 2 /FPGA_Spartan6/R_M0_DQ5 ) + ( 3 /FPGA_Spartan6/R_M0_DQ6 ) + ( 4 /FPGA_Spartan6/R_M0_DQ7 ) + ( 5 /FPGA_Spartan6/M0_DQ7 ) + ( 6 /FPGA_Spartan6/M0_DQ6 ) + ( 7 /DDR_Banks/M0_DQ5 ) + ( 8 /FPGA_Spartan6/M0_DQ4 ) ) - ( /4C431A63/4C69DA8A R_PACK4-0402 RP6 R_PACK4 - ( 1 /DDR_Banks/M1_A7 ) - ( 2 /FPGA_Sp81 ) - ( 3 /FPGA_Sp82 ) - ( 4 /DDR_Banks/M1_A4 ) - ( 5 ? ) - ( 6 /FPGA_Sp83 ) - ( 7 /FPGA_Sp84 ) - ( 8 /FPGA_Sp85 ) + ( /4C431A63/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_DQ0 ) + ( 2 /FPGA_Spartan6/R_M0_DQ1 ) + ( 3 /FPGA_Spartan6/R_M0_DQ2 ) + ( 4 /FPGA_Spartan6/R_M0_DQ3 ) + ( 5 /FPGA_Spartan6/M0_DQ3 ) + ( 6 /FPGA_Spartan6/M0_DQ2 ) + ( 7 /DDR_Banks/M0_DQ1 ) + ( 8 /FPGA_Spartan6/M0_DQ0 ) ) - ( /4C431A63/4C69DC05 R_PACK4-0402 RP7 R_PACK4 - ( 1 /FPGA_Sp86 ) - ( 2 /FPGA_Sp87 ) - ( 3 /DDR_Banks/M1_A9 ) - ( 4 /FPGA_Sp88 ) - ( 5 /FPGA_Sp89 ) - ( 6 /FPGA_Sp90 ) - ( 7 /FPGA_Sp91 ) - ( 8 /FPGA_Sp92 ) + ( /4C431A63/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_DQ8 ) + ( 2 /FPGA_Spartan6/R_M0_DQ9 ) + ( 3 /FPGA_Spartan6/R_M0_DQ10 ) + ( 4 /FPGA_Spartan6/R_M0_DQ11 ) + ( 5 /FPGA_Spartan6/M0_DQ11 ) + ( 6 /DDR_Banks/M0_DQ10 ) + ( 7 /FPGA_Spartan6/M0_DQ9 ) + ( 8 /DDR_Banks/M0_DQ8 ) ) - ( /4C431A63/4C69E299 R_PACK4-0402 RP8 R_PACK4 - ( 1 /FPGA_Sp93 ) - ( 2 /FPGA_Sp94 ) - ( 3 /FPGA_Sp95 ) - ( 4 /FPGA_Sp96 ) - ( 5 /FPGA_Sp97 ) - ( 6 /FPGA_Sp98 ) - ( 7 /FPGA_Sp99 ) - ( 8 /FPGA_Sp100 ) + ( /4C431A63/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_DQ12 ) + ( 2 /FPGA_Spartan6/R_M0_DQ13 ) + ( 3 /FPGA_Spartan6/R_M0_DQ14 ) + ( 4 /FPGA_Spartan6/R_M0_DQ15 ) + ( 5 /DDR_Banks/M0_DQ15 ) + ( 6 /DDR_Banks/M0_DQ14 ) + ( 7 /FPGA_Spartan6/M0_DQ13 ) + ( 8 /DDR_Banks/M0_DQ12 ) ) - ( /4C431A63/4C69E3A6 R_PACK4-0402 RP9 R_PACK4 - ( 1 /DDR_Ban101 ) - ( 2 /FPGA_Sp102 ) - ( 3 /FPGA_Sp103 ) - ( 4 /FPGA_Sp104 ) - ( 5 /FPGA_Sp105 ) - ( 6 /FPGA_Sp106 ) - ( 7 /FPGA_Sp107 ) - ( 8 /FPGA_Sp108 ) + ( /4C431A63/4C69E7DD 0402 R19 33 {Lib=R} + ( 1 /FPGA_Spartan6/R_M1_UDQS ) + ( 2 /FPGA_Spartan6/M1_UDQS ) ) - ( /4C431A63/4C69FC19 R_PACK4-0402 RP10 R_PACK4 - ( 1 /FPGA_Sp109 ) - ( 2 /FPGA_Sp110 ) - ( 3 /FPGA_Sp111 ) - ( 4 /FPGA_Sp112 ) - ( 5 /DDR_Ban113 ) - ( 6 /FPGA_Sp114 ) - ( 7 /DDR_Ban115 ) - ( 8 /DDR_Ban116 ) + ( /4C431A63/4C69E92D 0402 R20 33 {Lib=R} + ( 1 /FPGA_Spartan6/R_M1_CS# ) + ( 2 /FPGA_Spartan6/M1_CS# ) ) - ( /4C431A63/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 - ( 1 /FPGA_Sp117 ) - ( 2 /FPGA_Sp118 ) - ( 3 /FPGA_Sp119 ) - ( 4 /FPGA_Sp120 ) - ( 5 /FPGA_Sp121 ) - ( 6 /FPGA_Sp122 ) - ( 7 /FPGA_Sp123 ) - ( 8 /FPGA_Sp124 ) + ( /4C431A63/4C69E7F8 0402 R17 33 {Lib=R} + ( 1 /FPGA_Spartan6/R_M1_CKE ) + ( 2 /DDR_Banks/M1_CKE ) ) - ( /4C431A63/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 - ( 1 /FPGA_Sp125 ) - ( 2 /FPGA_Sp126 ) - ( 3 /FPGA_Sp127 ) - ( 4 /FPGA_Sp128 ) - ( 5 /FPGA_Sp129 ) - ( 6 /DDR_Ban130 ) - ( 7 /DDR_Ban131 ) - ( 8 /FPGA_Sp132 ) + ( /4C431A63/4C69E7C2 0402 R18 33 {Lib=R} + ( 1 /FPGA_Spartan6/R_M1_UDM ) + ( 2 /DDR_Banks/M1_UDM ) ) - ( /4C431A63/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 - ( 1 /FPGA_Sp133 ) - ( 2 /FPGA_Sp134 ) - ( 3 /FPGA_Sp135 ) - ( 4 /FPGA_Sp136 ) - ( 5 /FPGA_Sp137 ) - ( 6 /DDR_Ban138 ) - ( 7 /FPGA_Sp139 ) - ( 8 /FPGA_Sp140 ) + ( /4C431A63/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/M1_DQ11 ) + ( 2 /FPGA_Spartan6/M1_DQ10 ) + ( 3 /FPGA_Spartan6/M1_DQ9 ) + ( 4 /DDR_Banks/M1_DQ8 ) + ( 5 /FPGA_Spartan6/R_M1_DQ8 ) + ( 6 /FPGA_Spartan6/R_M1_DQ9 ) + ( 7 /FPGA_Spartan6/R_M1_DQ10 ) + ( 8 /FPGA_Spartan6/R_M1_DQ11 ) ) - ( /4C431A63/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 - ( 1 /FPGA_Sp141 ) - ( 2 /FPGA_Sp142 ) - ( 3 /FPGA_Sp143 ) - ( 4 /FPGA_Sp144 ) - ( 5 /FPGA_Sp145 ) - ( 6 /FPGA_Sp146 ) - ( 7 /FPGA_Sp147 ) - ( 8 /FPGA_Sp148 ) + ( /4C431A63/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/M1_DQ15 ) + ( 2 /FPGA_Spartan6/M1_DQ14 ) + ( 3 /DDR_Banks/M1_DQ13 ) + ( 4 /DDR_Banks/M1_DQ12 ) + ( 5 /FPGA_Spartan6/R_M1_DQ12 ) + ( 6 /FPGA_Spartan6/R_M1_DQ13 ) + ( 7 /FPGA_Spartan6/R_M1_DQ14 ) + ( 8 /FPGA_Spartan6/R_M1_DQ15 ) ) - ( /4C431A63/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 - ( 1 /FPGA_Sp149 ) - ( 2 /FPGA_Sp150 ) - ( 3 /FPGA_Sp151 ) - ( 4 /FPGA_Sp152 ) - ( 5 /FPGA_Sp153 ) - ( 6 /FPGA_Sp154 ) - ( 7 /FPGA_Sp155 ) - ( 8 /FPGA_Sp156 ) + ( /4C431A63/4C69DF7A 0402 R16 120 {Lib=R} + ( 1 /DDR_Banks/M1_CLK# ) + ( 2 /DDR_Banks/M1_CLK ) ) - ( /4C431A63/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 - ( 1 /FPGA_Sp157 ) - ( 2 /FPGA_Sp158 ) - ( 3 /FPGA_Sp159 ) - ( 4 /FPGA_Sp160 ) - ( 5 /FPGA_Sp161 ) - ( 6 /DDR_Ban162 ) - ( 7 /FPGA_Sp163 ) - ( 8 /FPGA_Sp164 ) + ( /4C431A63/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4} + ( 1 /DDR_Banks/M1_A12 ) + ( 2 /DDR_Banks/M1_A11 ) + ( 3 /FPGA_Spartan6/M1_A9 ) + ( 4 /FPGA_Spartan6/M1_A8 ) + ( 5 /FPGA_Spartan6/R_M1_A8 ) + ( 6 /FPGA_Spartan6/R_M1_A9 ) + ( 7 /FPGA_Spartan6/R_M1_A11 ) + ( 8 /FPGA_Spartan6/R_M1_A12 ) ) - ( /4C431A63/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 - ( 1 /FPGA_Sp165 ) - ( 2 /FPGA_Sp166 ) - ( 3 /FPGA_Sp167 ) - ( 4 /FPGA_Sp168 ) - ( 5 /DDR_Banks/M0_A4 ) - ( 6 /FPGA_Sp169 ) - ( 7 /FPGA_Sp170 ) - ( 8 /DDR_Banks/M0_A7 ) + ( /4C431A63/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4} + ( 1 /DDR_Banks/M1_A7 ) + ( 2 /DDR_Banks/M1_A6 ) + ( 3 /DDR_Banks/M1_A5 ) + ( 4 /DDR_Banks/M1_A4 ) + ( 5 ? ) + ( 6 /FPGA_Spartan6/R_M1_A5 ) + ( 7 /FPGA_Spartan6/R_M1_A6 ) + ( 8 /FPGA_Spartan6/R_M1_A7 ) ) - ( /4C431A63/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 - ( 1 /FPGA_Sp171 ) - ( 2 /FPGA_Sp172 ) - ( 3 /FPGA_Sp173 ) - ( 4 /FPGA_Sp174 ) - ( 5 /FPGA_Sp175 ) - ( 6 /FPGA_Sp176 ) - ( 7 /FPGA_Sp177 ) - ( 8 /DDR_Ban178 ) + ( /4C431A63/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M1_DQ0 ) + ( 2 /FPGA_Spartan6/R_M1_DQ1 ) + ( 3 /FPGA_Spartan6/R_M1_DQ2 ) + ( 4 /FPGA_Spartan6/R_M1_DQ3 ) + ( 5 /FPGA_Spartan6/M1_DQ3 ) + ( 6 /DDR_Banks/M1_DQ2 ) + ( 7 /FPGA_Spartan6/M1_DQ1 ) + ( 8 /FPGA_Spartan6/M1_DQ0 ) ) - ( /4C431A63/4C431E53 FGG484BGA-P10 U1 XC6SLX45FGG484 - ( A1 GND ) - ( A2 ? ) - ( A3 ? ) - ( A4 /FPGA_Sp179 ) - ( A5 /Etherne180 ) - ( A6 /FPGA_Sp181 ) - ( A7 /Etherne182 ) - ( A8 /FPGA_Sp183 ) - ( A9 /FPGA_Sp184 ) - ( A10 /Etherne185 ) - ( A11 /FPGA_Sp186 ) - ( A12 /FPGA_Sp187 ) - ( A13 /FPGA_Sp188 ) - ( A14 /Non_vol189 ) - ( A15 /FPGA_Sp190 ) - ( A16 ? ) - ( A17 /Non_vol7 ) - ( A18 /Non_vol11 ) - ( A19 /DBG_PRG19 ) - ( A20 ? ) - ( A21 ? ) - ( A22 GND ) - ( AA1 N-000132 ) - ( AA2 ? ) - ( AA3 VCCO2 ) - ( AA4 ? ) - ( AA5 GND ) - ( AA6 ? ) - ( AA7 VCCO2 ) - ( AA8 ? ) - ( AA9 GND ) - ( AA10 ? ) - ( AA11 VCCO2 ) - ( AA12 ? ) - ( AA13 GND ) - ( AA14 ? ) - ( AA15 VCCO2 ) - ( AA16 ? ) - ( AA17 GND ) - ( AA18 ? ) - ( AA19 VCCO2 ) - ( AA20 /FPGA_Sp191 ) - ( AA21 /FPGA_Sp192 ) - ( AA22 ? ) - ( AB1 GND ) - ( AB2 ? ) - ( AB3 ? ) - ( AB4 ? ) - ( AB5 ? ) - ( AB6 ? ) - ( AB7 ? ) - ( AB8 ? ) - ( AB9 ? ) - ( AB10 ? ) - ( AB11 ? ) - ( AB12 ? ) - ( AB13 ? ) - ( AB14 ? ) - ( AB15 ? ) - ( AB16 ? ) - ( AB17 ? ) - ( AB18 ? ) + ( /4C431A63/4C69D3A4 $noname RP3 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M1_LDQS ) + ( 2 /FPGA_Spartan6/R_M1_LDM ) + ( 3 /FPGA_Spartan6/R_M1_WE# ) + ( 4 /FPGA_Spartan6/R_M1_CAS# ) + ( 5 /FPGA_Spartan6/M1_CAS# ) + ( 6 /FPGA_Spartan6/M1_WE# ) + ( 7 /FPGA_Spartan6/M1_LDM ) + ( 8 /FPGA_Spartan6/M1_LDQS ) + ) + ( /4C431A63/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M1_DQ4 ) + ( 2 /FPGA_Spartan6/R_M1_DQ5 ) + ( 3 /FPGA_Spartan6/R_M1_DQ6 ) + ( 4 /FPGA_Spartan6/R_M1_DQ7 ) + ( 5 /DDR_Banks/M1_DQ7 ) + ( 6 /FPGA_Spartan6/M1_DQ6 ) + ( 7 /FPGA_Spartan6/M1_DQ5 ) + ( 8 /FPGA_Spartan6/M1_DQ4 ) + ) + ( /4C431A63/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M1_RAS# ) + ( 2 /FPGA_Spartan6/R_M1_BA0 ) + ( 3 /FPGA_Spartan6/R_M1_BA1 ) + ( 4 /FPGA_Spartan6/R_M1_A10 ) + ( 5 /FPGA_Spartan6/M1_A10 ) + ( 6 /FPGA_Spartan6/M1_BA1 ) + ( 7 /DDR_Banks/M1_BA0 ) + ( 8 /DDR_Banks/M1_RAS# ) + ) + ( /4C431A63/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M1_A0 ) + ( 2 /FPGA_Spartan6/R_M1_A1 ) + ( 3 /FPGA_Spartan6/R_M1_A2 ) + ( 4 /FPGA_Spartan6/R_M1_A3 ) + ( 5 /FPGA_Spartan6/M1_A3 ) + ( 6 /FPGA_Spartan6/M1_A2 ) + ( 7 /FPGA_Spartan6/M1_A1 ) + ( 8 /FPGA_Spartan6/M1_A0 ) + ) + ( /4C431A63/4C656D9D $noname C66 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D9A $noname C63 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D99 $noname C60 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D98 $noname C57 4.7uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D97 $noname C54 100uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D53 $noname C69 470nF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D49 $noname C67 470nF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D46 $noname C64 470nF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D45 $noname C61 470nF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D44 $noname C58 4.7uF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D43 $noname C55 100uF {Lib=C} + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D08 $noname C68 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CFC $noname C65 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CFB $noname C62 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CFA $noname C59 4.7uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CF9 $noname C56 100uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CBB $noname C50 470nF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CBA $noname C47 470nF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CB9 $noname C44 4.7uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CB7 $noname C41 100uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C49 $noname C53 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C27 $noname C51 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C24 $noname C49 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C16 $noname C46 4.7uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656BFA $noname C52 470nF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656BF9 $noname C43 4.7uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656BF8 $noname C40 100uF {Lib=C} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656AC2 $noname C48 470nF {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C656AC0 $noname C45 470nF {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C656ABD $noname C42 4.7uF {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C656A80 $noname C39 100uF {Lib=C} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} + ( H8 ? ) + ( P7 ? ) + ( N7 ? ) + ( M7 ? ) + ( L7 +2.5V ) + ( K7 ? ) + ( J7 ? ) + ( G7 ? ) + ( F7 ? ) + ( P6 ? ) + ( N6 ? ) + ( M6 ? ) + ( L6 ? ) + ( K6 /FPGA_Spartan6/R_M0_A3 ) + ( J6 ? ) + ( H6 /FPGA_Spartan6/R_M0_A7 ) + ( G6 ? ) + ( F6 +2.5V ) + ( E6 ? ) + ( U5 +2.5V ) + ( P5 ? ) + ( N5 +2.5V ) + ( M5 ? ) + ( K5 /FPGA_Spartan6/R_M0_RAS# ) + ( J5 +2.5V ) + ( H5 /FPGA_Spartan6/R_M0_A2 ) + ( F5 ? ) + ( E5 ? ) + ( D5 ? ) + ( U4 ? ) + ( K21 /FPGA_Spartan6/R_M1_DQ6 ) + ( H21 /FPGA_Spartan6/R_M1_RAS# ) + ( G21 +2.5V ) + ( F21 /FPGA_Spartan6/R_M1_A0 ) + ( D21 /FPGA_Spartan6/R_M1_CKE ) + ( C21 +2.5V ) + ( B21 ? ) + ( A21 ? ) + ( W20 ? ) + ( V20 ? ) + ( U20 /FPGA_Spartan6/R_M1_DQ12 ) + ( T20 ? ) + ( R20 /FPGA_Spartan6/R_M1_DQ10 ) + ( P20 ? ) + ( N20 /FPGA_Spartan6/R_M1_DQ0 ) + ( M20 /FPGA_Spartan6/R_M1_UDM ) + ( L20 /FPGA_Spartan6/R_M1_LDQS ) + ( K20 /FPGA_Spartan6/R_M1_A5 ) + ( J20 /FPGA_Spartan6/R_M1_DQ4 ) + ( H20 /DDR_Banks/M1_CLK ) + ( G20 /FPGA_Spartan6/R_M1_A3 ) + ( F20 ? ) + ( E20 /FPGA_Spartan6/R_M1_A7 ) + ( D20 ? ) + ( C20 /FPGA_Spartan6/R_M1_A8 ) + ( B20 /FPGA_Spartan6/USBA_OE_N ) + ( A20 ? ) + ( P8 ? ) + ( M8 ? ) + ( K8 ? ) + ( Y2 ? ) + ( W2 +2.5V ) + ( V2 /FPGA_Spartan6/R_M0_DQ14 ) + ( T2 /FPGA_Spartan6/R_M0_UDQS ) + ( R2 +2.5V ) + ( P2 /FPGA_Spartan6/R_M0_DQ8 ) + ( M2 /FPGA_Spartan6/R_M0_DQ2 ) + ( L2 +2.5V ) + ( K2 /FPGA_Spartan6/R_M0_DQ6 ) + ( H2 /FPGA_Spartan6/R_M0_A0 ) + ( G2 +2.5V ) + ( F2 /FPGA_Spartan6/R_M0_WE# ) + ( D2 /FPGA_Spartan6/R_M0_CKE ) + ( C2 +2.5V ) + ( B2 ? ) + ( A2 ? ) + ( Y1 ? ) + ( W1 ? ) + ( V1 /FPGA_Spartan6/R_M0_DQ15 ) + ( U1 /FPGA_Spartan6/R_M0_DQ13 ) + ( T1 ? ) + ( R1 /FPGA_Spartan6/R_M0_DQ11 ) + ( P1 /FPGA_Spartan6/R_M0_DQ9 ) + ( N1 /FPGA_Spartan6/R_M0_DQ1 ) + ( M1 /FPGA_Spartan6/R_M0_DQ3 ) + ( L1 ? ) + ( K1 /FPGA_Spartan6/R_M0_DQ7 ) + ( J1 /FPGA_Spartan6/R_M0_DQ5 ) + ( H1 /FPGA_Spartan6/R_M0_A1 ) + ( G1 /FPGA_Spartan6/R_M0_BA1 ) + ( T4 ? ) + ( R4 ? ) + ( P4 ? ) + ( N4 ? ) + ( M4 ? ) + ( L4 /FPGA_Spartan6/R_M0_LDM ) + ( K4 /FPGA_Spartan6/R_M0_CAS# ) + ( J4 /FPGA_Spartan6/R_M0_A6 ) + ( H4 /DDR_Banks/M0_CLK ) + ( G4 /FPGA_Spartan6/R_M0_A10 ) + ( F4 +2.5V ) + ( E4 ? ) + ( C4 ? ) + ( W3 ? ) + ( V3 ? ) + ( U3 /FPGA_Spartan6/R_M0_DQ12 ) + ( T3 ? ) + ( R3 /FPGA_Spartan6/R_M0_DQ10 ) + ( P3 ? ) + ( N3 /FPGA_Spartan6/R_M0_DQ0 ) + ( M3 /FPGA_Spartan6/R_M0_UDM ) + ( L3 /FPGA_Spartan6/R_M0_LDQS ) + ( K3 /FPGA_Spartan6/R_M0_A5 ) + ( J3 /FPGA_Spartan6/R_M0_DQ4 ) + ( H3 /FPGA_Spartan6/M0_CLK# ) + ( G3 /FPGA_Spartan6/R_M0_BA0 ) + ( F3 /FPGA_Spartan6/R_M0_A4 ) + ( E3 /FPGA_Spartan6/R_M0_A8 ) + ( D3 ? ) + ( C3 ? ) + ( B3 ? ) + ( G10 +3.3V ) + ( D10 /Ethernet_Phy/ETH_TXD0 ) + ( C10 /Ethernet_Phy/ETH_TXD2 ) + ( B10 /FPGA_Spartan6/ETH_CRS ) + ( A10 /Ethernet_Phy/ETH_INT ) + ( E9 +3.3V ) + ( D9 /Ethernet_Phy/ETH_TXEN ) + ( C9 /FPGA_Spartan6/ETH_TXD1 ) + ( A9 /FPGA_Spartan6/ETH_COL ) + ( D8 /Ethernet_Phy/ETH_TXER ) + ( C8 /Ethernet_Phy/ETH_TXC ) + ( B8 /Ethernet_Phy/ETH_RXER ) + ( A8 /Ethernet_Phy/ETH_TXD3 ) + ( D7 /FPGA_Spartan6/ETH_MDC ) + ( C7 /FPGA_Spartan6/ETH_RESET_N ) + ( B7 +3.3V ) + ( A7 /Ethernet_Phy/ETH_RXC ) + ( D6 /FPGA_Spartan6/ETH_MDIO ) + ( C6 /Ethernet_Phy/ETH_RXD2 ) + ( B6 /Ethernet_Phy/ETH_RXD0 ) + ( A6 /FPGA_Spartan6/ETH_RXDV ) + ( C5 /FPGA_Spartan6/ETH_RXD3 ) + ( A5 /FPGA_Spartan6/ETH_RXD1 ) + ( B4 +3.3V ) + ( A4 /Ethernet_Phy/ETH_CLK ) + ( A3 ? ) + ( U19 ? ) + ( T19 ? ) + ( R19 ? ) + ( P19 ? ) + ( B19 +3.3V ) + ( B18 /Non_volatile_memories/SD_DAT1 ) + ( A18 /FPGA_Spartan6/SD_DAT0 ) + ( E17 +3.3V ) + ( D17 /FPGA_Spartan6/SD_CMD ) + ( C17 /Non_volatile_memories/SD_DAT3 ) + ( A17 /FPGA_Spartan6/SD_DAT2 ) + ( E16 /FPGA_Spartan6/SD_CLK ) + ( C16 ? ) + ( B16 ? ) + ( A16 ? ) + ( D15 /Non_volatile_memories/NF_CS1_N ) + ( C15 /Non_volatile_memories/NF_RE_N ) + ( B15 +3.3V ) + ( A15 /Non_volatile_memories/NF_RNB ) + ( G14 +3.3V ) + ( D14 /FPGA_Spartan6/NF_D1 ) + ( C14 /Non_volatile_memories/NF_WE_N ) + ( B14 /Non_volatile_memories/NF_CLE ) + ( A14 /Non_volatile_memories/NF_ALE ) + ( E13 +3.3V ) + ( C13 ? ) + ( A13 /Non_volatile_memories/NF_D2 ) + ( C12 /Non_volatile_memories/NF_D0 ) + ( B12 /FPGA_Spartan6/NF_D3 ) + ( A12 /FPGA_Spartan6/NF_D4 ) + ( D11 /FPGA_Spartan6/NF_D7 ) + ( C11 /FPGA_Spartan6/NF_D5 ) + ( B11 +3.3V ) + ( A11 /Non_volatile_memories/NF_D6 ) + ( J16 ? ) + ( H16 /FPGA_Spartan6/R_M1_CS# ) + ( G16 /USB/USBA_RCV ) + ( F16 /USB/USBA_VM ) + ( L15 ? ) + ( W22 ? ) + ( V22 /FPGA_Spartan6/R_M1_DQ15 ) + ( U22 /FPGA_Spartan6/R_M1_DQ13 ) + ( T22 ? ) + ( R22 /FPGA_Spartan6/R_M1_DQ11 ) + ( P22 /FPGA_Spartan6/R_M1_DQ9 ) + ( N22 /FPGA_Spartan6/R_M1_DQ1 ) + ( M22 /FPGA_Spartan6/R_M1_DQ3 ) + ( L22 ? ) + ( K22 /FPGA_Spartan6/R_M1_DQ7 ) + ( J22 /FPGA_Spartan6/R_M1_DQ5 ) + ( H22 /FPGA_Spartan6/R_M1_CAS# ) + ( G22 ? ) + ( F22 /FPGA_Spartan6/R_M1_A1 ) + ( E22 /FPGA_Spartan6/R_M1_A2 ) + ( D22 /FPGA_Spartan6/R_M1_A12 ) + ( C22 /FPGA_Spartan6/R_M1_A9 ) + ( B22 ? ) + ( W21 +2.5V ) + ( V21 /FPGA_Spartan6/R_M1_DQ14 ) + ( T21 /FPGA_Spartan6/R_M1_UDQS ) + ( R21 +2.5V ) + ( P21 /FPGA_Spartan6/R_M1_DQ8 ) + ( M21 /FPGA_Spartan6/R_M1_DQ2 ) + ( L21 +2.5V ) + ( N19 ? ) + ( M19 ? ) + ( L19 /FPGA_Spartan6/R_M1_LDM ) + ( K19 /FPGA_Spartan6/R_M1_A6 ) + ( J19 /DDR_Banks/M1_CLK# ) + ( H19 /FPGA_Spartan6/R_M1_WE# ) + ( G19 /FPGA_Spartan6/R_M1_A10 ) + ( F19 /FPGA_Spartan6/R_M1_A11 ) + ( E19 +2.5V ) + ( D19 ? ) + ( C19 /USB/USBA_SPD ) + ( U18 +2.5V ) + ( P18 ? ) + ( N18 +2.5V ) + ( M18 ? ) + ( K18 ? ) + ( J18 +2.5V ) + ( H18 ? ) + ( F18 ? ) + ( P17 ? ) + ( M17 ? ) + ( L17 ? ) + ( K17 /FPGA_Spartan6/R_M1_BA1 ) + ( J17 /FPGA_Spartan6/R_M1_BA0 ) + ( H17 ? ) + ( G17 /USB/USBA_VP ) + ( F17 ? ) + ( N16 ? ) + ( M16 ? ) + ( L16 +2.5V ) + ( K16 ? ) + ( J14 +1.2V ) + ( H14 ? ) + ( F14 ? ) + ( E14 ? ) + ( P13 +1.2V ) + ( N13 GND ) + ( M13 +1.2V ) + ( L13 GND ) + ( K13 +1.2V ) + ( J13 GND ) + ( H13 ? ) + ( G13 ? ) + ( F13 ? ) + ( D13 ? ) + ( B13 GND ) + ( Y22 N-000267 ) + ( A22 GND ) + ( R12 +2.5V ) + ( P12 GND ) + ( N12 +1.2V ) + ( M12 GND ) + ( L12 +1.2V ) + ( K12 GND ) + ( J12 +1.2V ) + ( H12 ? ) + ( G12 +2.5V ) + ( F12 ? ) + ( E12 ? ) + ( D12 ? ) + ( AB1 GND ) + ( A19 /DBG_PRG/FPGA_TDO ) + ( R18 GND ) + ( L18 GND ) + ( G18 GND ) + ( E18 /DBG_PRG/FPGA_TDI ) + ( D18 GND ) + ( C18 /DBG_PRG/FPGA_TMS ) + ( R17 ? ) + ( N17 GND ) + ( B17 GND ) + ( W16 GND ) + ( P16 ? ) + ( D16 +2.5V ) + ( AA5 GND ) + ( P15 ? ) + ( N15 GND ) + ( M15 +2.5V ) + ( K15 +2.5V ) + ( J15 GND ) + ( H15 +2.5V ) + ( G15 /DBG_PRG/FPGA_TCK ) + ( F15 ? ) + ( E15 GND ) + ( V14 GND ) + ( R14 +1.2V ) + ( P14 GND ) + ( N14 +1.2V ) + ( M14 GND ) + ( L14 +1.2V ) + ( K14 GND ) + ( L9 GND ) + ( K9 +1.2V ) + ( J9 GND ) + ( H9 +2.5V ) + ( G9 ? ) + ( F9 ? ) + ( B9 GND ) + ( N8 +2.5V ) + ( L8 +2.5V ) + ( J8 +1.2V ) + ( G8 ? ) + ( F8 ? ) + ( E8 ? ) + ( W7 GND ) + ( U7 GND ) + ( H7 GND ) + ( E7 GND ) + ( V6 +2.5V ) + ( R6 +2.5V ) + ( R5 GND ) + ( L5 GND ) + ( G5 GND ) + ( B5 GND ) + ( V4 GND ) + ( D4 GND ) + ( U2 GND ) + ( N2 GND ) + ( J2 GND ) + ( E2 GND ) + ( A1 GND ) + ( AA1 N-000390 ) + ( U21 GND ) + ( N21 GND ) + ( J21 GND ) + ( E21 GND ) + ( U11 +2.5V ) + ( P11 +1.2V ) + ( N11 GND ) + ( M11 +1.2V ) + ( L11 GND ) + ( K11 +1.2V ) + ( J11 GND ) + ( H11 ? ) + ( G11 ? ) + ( F11 +2.5V ) + ( E11 GND ) + ( Y20 +3.3V ) + ( V10 GND ) + ( R10 +2.5V ) + ( P10 GND ) + ( N10 +1.2V ) + ( M10 GND ) + ( L10 +1.2V ) + ( K10 GND ) + ( J10 +1.2V ) + ( H10 ? ) + ( F10 ? ) + ( E10 ? ) + ( P9 +1.2V ) + ( N9 GND ) + ( M9 +1.2V ) + ( V19 ? ) + ( AB8 ? ) + ( AA8 ? ) + ( Y18 ? ) + ( W18 ? ) + ( V18 ? ) + ( T18 ? ) + ( AB7 ? ) + ( AA7 VCCO2 ) + ( Y17 ? ) + ( W17 ? ) + ( V17 ? ) + ( U17 ? ) + ( T17 ? ) + ( AB6 ? ) + ( AA6 ? ) + ( Y16 ? ) + ( V16 VCCO2 ) + ( U16 ? ) + ( T16 ? ) + ( R16 ? ) + ( AB5 ? ) + ( Y15 ? ) + ( W15 ? ) + ( V15 ? ) + ( U15 ? ) + ( T15 ? ) + ( R15 ? ) + ( AB4 ? ) + ( AA4 ? ) + ( F1 ? ) + ( E1 /FPGA_Spartan6/R_M0_A9 ) + ( D1 /FPGA_Spartan6/R_M0_A12 ) + ( C1 /FPGA_Spartan6/R_M0_A11 ) + ( B1 ? ) ( AB19 ? ) - ( AB20 /FPGA_Sp193 ) + ( AA19 VCCO2 ) + ( AB18 ? ) + ( AA18 ? ) + ( AB17 ? ) + ( AB16 ? ) + ( AA16 ? ) + ( AB15 ? ) + ( AA15 VCCO2 ) + ( AB14 ? ) + ( AA14 ? ) + ( AB13 ? ) + ( AA22 ? ) + ( AB12 ? ) + ( AA12 ? ) ( AB21 ? ) + ( AA21 /FPGA_Spartan6/PROG_CCLK ) + ( AB11 ? ) + ( AA11 VCCO2 ) + ( AB20 /FPGA_Spartan6/PROG_MISO0 ) + ( AA20 /FPGA_Spartan6/PROG_MISO1 ) + ( AB10 ? ) + ( AA10 ? ) + ( AB9 ? ) + ( Y19 ? ) + ( V9 ? ) + ( U9 ? ) + ( T9 VCCO2 ) + ( R9 ? ) + ( Y8 ? ) + ( W8 ? ) + ( V8 VCCO2 ) + ( U8 ? ) + ( T8 ? ) + ( R8 ? ) + ( Y7 ? ) + ( V7 ? ) + ( T7 ? ) + ( R7 ? ) + ( Y6 ? ) + ( W6 ? ) + ( U6 ? ) + ( T6 ? ) + ( Y5 ? ) + ( W5 VCCO2 ) + ( V5 ? ) + ( T5 /FPGA_Spartan6/PROG_CSO ) + ( Y4 ? ) + ( W4 ? ) + ( Y3 ? ) + ( AA17 GND ) + ( AA13 GND ) ( AB22 GND ) - ( B1 ? ) - ( B2 ? ) - ( B3 ? ) - ( B4 +3.3V ) - ( B5 GND ) - ( B6 /Etherne194 ) - ( B7 +3.3V ) - ( B8 /Etherne195 ) - ( B9 GND ) - ( B10 /Etherne196 ) - ( B11 +3.3V ) - ( B12 /FPGA_Sp197 ) - ( B13 GND ) - ( B14 /FPGA_Sp198 ) - ( B15 +3.3V ) - ( B16 ? ) - ( B17 GND ) - ( B18 /Non_vol12 ) - ( B19 +3.3V ) - ( B20 ? ) - ( B21 ? ) - ( B22 ? ) - ( C1 /FPGA_Sp172 ) - ( C2 +2.5V ) - ( C3 ? ) - ( C4 ? ) - ( C5 /FPGA_Sp199 ) - ( C6 /Etherne200 ) - ( C7 /FPGA_Sp201 ) - ( C8 /Etherne202 ) - ( C9 /FPGA_Sp203 ) - ( C10 /FPGA_Sp204 ) - ( C11 /Non_vol205 ) - ( C12 /FPGA_Sp206 ) - ( C13 ? ) - ( C14 /Non_vol207 ) - ( C15 /Non_vol208 ) - ( C16 ? ) - ( C17 /Non_vol8 ) - ( C18 /DBG_PRG18 ) - ( C19 ? ) - ( C20 /FPGA_Sp89 ) - ( C21 +2.5V ) - ( C22 /FPGA_Sp90 ) - ( D1 /FPGA_Sp171 ) - ( D2 /FPGA_Sp40 ) - ( D3 ? ) - ( D4 GND ) - ( D5 ? ) - ( D6 /Etherne21 ) - ( D7 /Etherne209 ) - ( D8 /FPGA_Sp210 ) - ( D9 /FPGA_Sp211 ) - ( D10 /FPGA_Sp212 ) - ( D11 /Non_vol213 ) - ( D12 ? ) - ( D13 ? ) - ( D14 /Non_vol214 ) - ( D15 /Non_vol215 ) - ( D16 +2.5V ) - ( D17 /FPGA_Sp9 ) - ( D18 GND ) - ( D19 ? ) - ( D20 ? ) - ( D21 /FPGA_Sp26 ) - ( D22 /FPGA_Sp92 ) - ( E1 /FPGA_Sp173 ) - ( E2 GND ) - ( E3 /FPGA_Sp174 ) - ( E4 ? ) - ( E5 ? ) - ( E6 ? ) - ( E7 GND ) - ( E8 ? ) - ( E9 +3.3V ) - ( E10 ? ) - ( E11 GND ) - ( E12 ? ) - ( E13 +3.3V ) - ( E14 ? ) - ( E15 GND ) - ( E16 /Non_vol10 ) - ( E17 +3.3V ) - ( E18 /DBG_PRG20 ) - ( E19 +2.5V ) - ( E20 /FPGA_Sp85 ) - ( E21 GND ) - ( E22 /FPGA_Sp44 ) - ( F1 ? ) - ( F2 /FPGA_Sp159 ) - ( F3 /FPGA_Sp168 ) - ( F4 +2.5V ) - ( F5 ? ) - ( F6 +2.5V ) - ( F7 ? ) - ( F8 ? ) - ( F9 ? ) - ( F10 ? ) - ( F11 +2.5V ) - ( F12 ? ) - ( F13 ? ) - ( F14 ? ) - ( F15 ? ) - ( F16 ? ) - ( F17 ? ) - ( F18 ? ) - ( F19 /FPGA_Sp91 ) - ( F20 ? ) - ( F21 /FPGA_Sp42 ) - ( F22 /FPGA_Sp43 ) - ( G1 /FPGA_Sp151 ) - ( G2 +2.5V ) - ( G3 /FPGA_Sp150 ) - ( G4 /FPGA_Sp152 ) - ( G5 GND ) - ( G6 ? ) - ( G7 ? ) - ( G8 ? ) - ( G9 ? ) - ( G10 +3.3V ) - ( G11 ? ) - ( G12 +2.5V ) - ( G13 ? ) - ( G14 +3.3V ) - ( G15 /DBG_PRG17 ) - ( G16 ? ) - ( G17 ? ) - ( G18 GND ) - ( G19 /FPGA_Sp52 ) - ( G20 /FPGA_Sp45 ) - ( G21 +2.5V ) - ( G22 ? ) - ( H1 /FPGA_Sp142 ) - ( H2 /FPGA_Sp141 ) - ( H3 /FPGA_Sp35 ) - ( H4 /FPGA_Sp34 ) - ( H5 /FPGA_Sp143 ) - ( H6 /FPGA_Sp165 ) - ( H7 GND ) - ( H8 ? ) - ( H9 +2.5V ) - ( H10 ? ) - ( H11 ? ) - ( H12 ? ) - ( H13 ? ) - ( H14 ? ) - ( H15 +2.5V ) - ( H16 /FPGA_Sp32 ) - ( H17 ? ) - ( H18 ? ) - ( H19 /FPGA_Sp59 ) - ( H20 /DDR_Ban25 ) - ( H21 /FPGA_Sp49 ) - ( H22 /FPGA_Sp60 ) - ( J1 /FPGA_Sp126 ) - ( J2 GND ) - ( J3 /FPGA_Sp125 ) - ( J4 /FPGA_Sp166 ) - ( J5 +2.5V ) - ( J6 ? ) - ( J7 ? ) - ( J8 +1.2V ) - ( J9 GND ) - ( J10 +1.2V ) - ( J11 GND ) - ( J12 +1.2V ) - ( J13 GND ) - ( J14 +1.2V ) - ( J15 GND ) - ( J16 ? ) - ( J17 /FPGA_Sp50 ) - ( J18 +2.5V ) - ( J19 /DDR_Ban24 ) - ( J20 /FPGA_Sp65 ) - ( J21 GND ) - ( J22 /FPGA_Sp66 ) - ( K1 /FPGA_Sp128 ) - ( K2 /FPGA_Sp127 ) - ( K3 /FPGA_Sp167 ) - ( K4 /FPGA_Sp160 ) - ( K5 /FPGA_Sp149 ) - ( K6 /FPGA_Sp144 ) - ( K7 ? ) - ( K8 ? ) - ( K9 +1.2V ) - ( K10 GND ) - ( K11 +1.2V ) - ( K12 GND ) - ( K13 +1.2V ) - ( K14 GND ) - ( K15 +2.5V ) - ( K16 ? ) - ( K17 /FPGA_Sp51 ) - ( K18 ? ) - ( K19 /FPGA_Sp84 ) - ( K20 /FPGA_Sp83 ) - ( K21 /FPGA_Sp67 ) - ( K22 /FPGA_Sp68 ) - ( L1 ? ) - ( L2 +2.5V ) - ( L3 /FPGA_Sp157 ) - ( L4 /FPGA_Sp158 ) - ( L5 GND ) - ( L6 ? ) - ( L7 +2.5V ) - ( L8 +2.5V ) - ( L9 GND ) - ( L10 +1.2V ) - ( L11 GND ) - ( L12 +1.2V ) - ( L13 GND ) - ( L14 +1.2V ) - ( L15 ? ) - ( L16 +2.5V ) - ( L17 ? ) - ( L18 GND ) - ( L19 /FPGA_Sp58 ) - ( L20 /FPGA_Sp57 ) - ( L21 +2.5V ) - ( L22 ? ) - ( M1 /FPGA_Sp136 ) - ( M2 /FPGA_Sp135 ) - ( M3 /FPGA_Sp38 ) - ( M4 ? ) - ( M5 ? ) - ( M6 ? ) - ( M7 ? ) - ( M8 ? ) - ( M9 +1.2V ) - ( M10 GND ) - ( M11 +1.2V ) - ( M12 GND ) - ( M13 +1.2V ) - ( M14 GND ) - ( M15 +2.5V ) - ( M16 ? ) - ( M17 ? ) - ( M18 /FPGA_Sp216 ) - ( M19 ? ) - ( M20 /FPGA_Sp28 ) - ( M21 /FPGA_Sp75 ) - ( M22 /FPGA_Sp76 ) - ( N1 /FPGA_Sp134 ) - ( N2 GND ) - ( N3 /FPGA_Sp133 ) - ( N4 ? ) - ( N5 +2.5V ) - ( N6 ? ) - ( N7 ? ) - ( N8 +2.5V ) - ( N9 GND ) - ( N10 +1.2V ) - ( N11 GND ) - ( N12 +1.2V ) - ( N13 GND ) - ( N14 +1.2V ) - ( N15 GND ) - ( N16 /FPGA_Sp217 ) - ( N17 GND ) - ( N18 +2.5V ) - ( N19 ? ) - ( N20 /FPGA_Sp73 ) - ( N21 GND ) - ( N22 /FPGA_Sp74 ) - ( P1 /FPGA_Sp118 ) - ( P2 /FPGA_Sp117 ) - ( P3 ? ) - ( P4 ? ) - ( P5 ? ) - ( P6 ? ) - ( P7 ? ) - ( P8 ? ) - ( P9 +1.2V ) - ( P10 GND ) - ( P11 +1.2V ) - ( P12 GND ) - ( P13 +1.2V ) - ( P14 GND ) - ( P15 ? ) - ( P16 ? ) - ( P17 /USB/USBA_VP ) - ( P18 /USB/USBA_OE_N ) - ( P19 ? ) - ( P20 ? ) - ( P21 /FPGA_Sp105 ) - ( P22 /FPGA_Sp106 ) - ( R1 /FPGA_Sp120 ) - ( R2 +2.5V ) - ( R3 /FPGA_Sp119 ) - ( R4 ? ) - ( R5 GND ) - ( R6 +2.5V ) - ( R7 ? ) - ( R8 ? ) - ( R9 ? ) - ( R10 +2.5V ) - ( R11 ? ) - ( R12 +2.5V ) - ( R13 ? ) - ( R14 +1.2V ) - ( R15 ? ) - ( R16 ? ) - ( R17 ? ) - ( R18 GND ) - ( R19 /USB/USBA_SPD ) - ( R20 /FPGA_Sp107 ) - ( R21 +2.5V ) - ( R22 /FPGA_Sp108 ) - ( T1 ? ) - ( T2 /FPGA_Sp36 ) - ( T3 ? ) - ( T4 ? ) - ( T5 /FPGA_Sp218 ) - ( T6 ? ) - ( T7 ? ) - ( T8 ? ) - ( T9 VCCO2 ) - ( T10 ? ) - ( T11 ? ) - ( T12 ? ) - ( T13 VCCO2 ) - ( T14 ? ) - ( T15 ? ) - ( T16 ? ) - ( T17 ? ) - ( T18 ? ) - ( T19 ? ) - ( T20 ? ) - ( T21 /FPGA_Sp30 ) - ( T22 ? ) - ( U1 /FPGA_Sp110 ) - ( U2 GND ) - ( U3 /FPGA_Sp109 ) - ( U4 ? ) - ( U5 +2.5V ) - ( U6 ? ) - ( U7 GND ) - ( U8 ? ) - ( U9 ? ) - ( U10 ? ) - ( U11 +2.5V ) - ( U12 ? ) - ( U13 /FPGA_Sp219 ) - ( U14 /FPGA_Sp220 ) - ( U15 ? ) - ( U16 ? ) - ( U17 ? ) - ( U18 +2.5V ) - ( U19 ? ) - ( U20 /FPGA_Sp97 ) - ( U21 GND ) - ( U22 /FPGA_Sp98 ) - ( V1 /FPGA_Sp112 ) - ( V2 /FPGA_Sp111 ) - ( V3 ? ) - ( V4 GND ) - ( V5 ? ) - ( V6 +2.5V ) - ( V7 ? ) - ( V8 VCCO2 ) - ( V9 ? ) - ( V10 GND ) - ( V11 ? ) - ( V12 VCCO2 ) - ( V13 ? ) - ( V14 GND ) - ( V15 ? ) - ( V16 VCCO2 ) - ( V17 ? ) - ( V18 ? ) - ( V19 ? ) - ( V20 ? ) - ( V21 /FPGA_Sp99 ) - ( V22 /FPGA_Sp100 ) - ( W1 ? ) - ( W2 +2.5V ) - ( W3 ? ) - ( W4 ? ) - ( W5 VCCO2 ) - ( W6 ? ) - ( W7 GND ) - ( W8 ? ) - ( W9 ? ) - ( W10 ? ) - ( W11 ? ) - ( W12 ? ) - ( W13 ? ) - ( W14 ? ) - ( W15 ? ) - ( W16 GND ) - ( W17 ? ) - ( W18 ? ) - ( W19 GND ) - ( W20 ? ) - ( W21 +2.5V ) - ( W22 ? ) - ( Y1 ? ) - ( Y2 ? ) - ( Y3 ? ) - ( Y4 ? ) - ( Y5 ? ) - ( Y6 ? ) - ( Y7 ? ) - ( Y8 ? ) - ( Y9 ? ) - ( Y10 ? ) - ( Y11 ? ) - ( Y12 ? ) - ( Y13 ? ) - ( Y14 ? ) - ( Y15 ? ) - ( Y16 ? ) - ( Y17 ? ) - ( Y18 ? ) - ( Y19 ? ) - ( Y20 +3.3V ) - ( Y21 ? ) - ( Y22 N-000127 ) + ( AA9 GND ) + ( W19 GND ) + ( Y14 ? ) + ( W14 ? ) + ( U14 /FPGA_Spartan6/PROG_MISO2 ) + ( T14 ? ) + ( AB3 ? ) + ( AA3 VCCO2 ) + ( Y13 ? ) + ( W13 ? ) + ( V13 ? ) + ( U13 /FPGA_Spartan6/PROG_MISO3 ) + ( T13 VCCO2 ) + ( R13 ? ) + ( AB2 ? ) + ( AA2 ? ) + ( Y12 ? ) + ( W12 ? ) + ( V12 VCCO2 ) + ( U12 ? ) + ( T12 ? ) + ( Y21 ? ) + ( Y11 ? ) + ( W11 ? ) + ( V11 ? ) + ( T11 ? ) + ( R11 ? ) + ( Y10 ? ) + ( W10 ? ) + ( U10 ? ) + ( T10 ? ) + ( Y9 ? ) + ( W9 ? ) ) - ( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG - ( 1 +2.5V ) - ( 2 /FPGA_Sp140 ) - ( 3 +2.5V ) - ( 4 /FPGA_Sp139 ) - ( 5 /DDR_Ban138 ) - ( 6 GND ) - ( 7 /FPGA_Sp137 ) - ( 8 /FPGA_Sp132 ) - ( 9 +2.5V ) - ( 10 /DDR_Ban131 ) - ( 11 /DDR_Ban130 ) - ( 12 GND ) - ( 13 /FPGA_Sp129 ) - ( 14 ? ) - ( 15 +2.5V ) - ( 16 /FPGA_Sp164 ) - ( 17 ? ) - ( 18 +2.5V ) - ( 19 ? ) - ( 20 /FPGA_Sp163 ) - ( 21 /DDR_Ban162 ) - ( 22 /FPGA_Sp161 ) - ( 23 /FPGA_Sp156 ) - ( 24 GND ) - ( 25 ? ) - ( 26 /FPGA_Sp155 ) - ( 27 /FPGA_Sp154 ) - ( 28 /FPGA_Sp153 ) - ( 29 /FPGA_Sp148 ) - ( 30 /FPGA_Sp147 ) - ( 31 /FPGA_Sp146 ) - ( 32 /FPGA_Sp145 ) - ( 33 +2.5V ) - ( 34 GND ) - ( 35 /DDR_Banks/M0_A4 ) - ( 36 /FPGA_Sp169 ) - ( 37 /FPGA_Sp170 ) - ( 38 /DDR_Banks/M0_A7 ) - ( 39 /FPGA_Sp175 ) - ( 40 /FPGA_Sp176 ) - ( 41 /FPGA_Sp177 ) - ( 42 /DDR_Ban178 ) - ( 43 ? ) - ( 44 /FPGA_Sp35 ) - ( 45 /DDR_Ban41 ) - ( 46 /FPGA_Sp34 ) - ( 47 /DDR_Ban39 ) - ( 48 GND ) - ( 49 /DDR_Ban5 ) - ( 50 ? ) - ( 51 /FPGA_Sp37 ) - ( 52 GND ) - ( 53 ? ) - ( 54 /FPGA_Sp124 ) - ( 55 +2.5V ) - ( 56 /FPGA_Sp123 ) - ( 57 /FPGA_Sp122 ) - ( 58 GND ) - ( 59 /FPGA_Sp121 ) - ( 60 /DDR_Ban116 ) - ( 61 +2.5V ) - ( 62 /DDR_Ban115 ) - ( 63 /FPGA_Sp114 ) - ( 64 GND ) - ( 65 /DDR_Ban113 ) - ( 66 GND ) + ( /4C4320F3/4C5D8114 $noname C9 100nF {Lib=C} + ( 1 /Ethernet_Phy/ETH_PLL1.8V ) + ( 2 GND ) ) - ( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG - ( 1 +2.5V ) - ( 2 /DDR_Ban80 ) - ( 3 +2.5V ) - ( 4 /DDR_Ban79 ) - ( 5 /FPGA_Sp78 ) - ( 6 GND ) - ( 7 /FPGA_Sp77 ) - ( 8 /FPGA_Sp72 ) - ( 9 +2.5V ) - ( 10 /FPGA_Sp71 ) - ( 11 /DDR_Ban70 ) - ( 12 GND ) - ( 13 /FPGA_Sp69 ) - ( 14 ? ) - ( 15 +2.5V ) - ( 16 /FPGA_Sp64 ) - ( 17 ? ) - ( 18 +2.5V ) - ( 19 ? ) - ( 20 /FPGA_Sp63 ) - ( 21 /DDR_Ban62 ) - ( 22 /FPGA_Sp61 ) - ( 23 /FPGA_Sp56 ) - ( 24 /DDR_Ban33 ) - ( 25 ? ) - ( 26 /FPGA_Sp55 ) - ( 27 /DDR_Ban54 ) - ( 28 /DDR_Ban53 ) - ( 29 /FPGA_Sp48 ) - ( 30 /FPGA_Sp47 ) - ( 31 /DDR_Banks/M1_A2 ) - ( 32 /FPGA_Sp46 ) - ( 33 +2.5V ) - ( 34 GND ) - ( 35 /DDR_Banks/M1_A4 ) - ( 36 /FPGA_Sp82 ) - ( 37 /FPGA_Sp81 ) - ( 38 /DDR_Banks/M1_A7 ) - ( 39 /FPGA_Sp88 ) - ( 40 /DDR_Banks/M1_A9 ) - ( 41 /FPGA_Sp87 ) - ( 42 /FPGA_Sp86 ) - ( 43 ? ) - ( 44 /DDR_Ban24 ) - ( 45 /FPGA_Sp27 ) - ( 46 /DDR_Ban25 ) - ( 47 /DDR_Ban29 ) - ( 48 GND ) - ( 49 /DDR_Ban6 ) - ( 50 ? ) - ( 51 /FPGA_Sp31 ) - ( 52 GND ) - ( 53 ? ) - ( 54 /FPGA_Sp104 ) - ( 55 +2.5V ) - ( 56 /FPGA_Sp103 ) - ( 57 /FPGA_Sp102 ) - ( 58 GND ) - ( 59 /DDR_Ban101 ) - ( 60 /FPGA_Sp96 ) - ( 61 +2.5V ) - ( 62 /FPGA_Sp95 ) - ( 63 /FPGA_Sp94 ) - ( 64 GND ) - ( 65 /FPGA_Sp93 ) - ( 66 GND ) + ( /4C4320F3/4C5D810A 0402 L3 FB {Lib=INDUCTOR} + ( 1 /Ethernet_Phy/ETH_A1.8V ) + ( 2 /Ethernet_Phy/ETH_PLL1.8V ) ) - ( /4C4320F3/4C432132 LQFP48 U4 K8001 - ( 1 /Etherne21 ) - ( 2 /Etherne209 ) - ( 3 /FPGA_Sp199 ) - ( 4 /Etherne200 ) - ( 5 /Etherne180 ) - ( 6 /Etherne194 ) - ( 7 +3.3V ) - ( 8 GND ) - ( 9 /FPGA_Sp181 ) - ( 10 /Etherne182 ) - ( 11 /Etherne195 ) - ( 12 GND ) - ( 13 +1.8V ) - ( 14 /FPGA_Sp210 ) - ( 15 /Etherne202 ) - ( 16 /FPGA_Sp211 ) - ( 17 /FPGA_Sp212 ) - ( 18 /FPGA_Sp203 ) - ( 19 /FPGA_Sp204 ) - ( 20 /FPGA_Sp183 ) - ( 21 /FPGA_Sp184 ) - ( 22 /Etherne196 ) - ( 23 GND ) - ( 24 +3.3V ) - ( 25 /Etherne185 ) - ( 26 /Etherne22 ) - ( 27 /Etherne23 ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 /Etherne1 ) - ( 32 /Etherne16 ) - ( 33 /Etherne15 ) - ( 34 ? ) - ( 35 GND ) - ( 36 GND ) - ( 37 N-000395 ) - ( 38 /Etherne2 ) - ( 39 GND ) - ( 40 /Etherne14 ) - ( 41 /Etherne13 ) - ( 42 ? ) - ( 43 ? ) - ( 44 GND ) - ( 45 ? ) - ( 46 /FPGA_Sp179 ) - ( 47 /Etherne3 ) - ( 48 /FPGA_Sp201 ) + ( /4C4320F3/4C5D8104 $noname C6 100nF {Lib=C} + ( 1 /Ethernet_Phy/ETH_A1.8V ) + ( 2 GND ) ) - ( /4C4227FE/4B76F108 NAND-48TSOP U5 NAND - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 /FPGA_Sp190 ) - ( 7 /FPGA_Sp190 ) - ( 8 /Non_vol208 ) - ( 9 /Non_vol215 ) - ( 10 ? ) - ( 11 ? ) - ( 12 +3.3V ) - ( 13 GND ) - ( 14 ? ) - ( 15 ? ) - ( 16 /FPGA_Sp198 ) - ( 17 /Non_vol189 ) - ( 18 /Non_vol207 ) - ( 19 +3.3V ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 ? ) - ( 24 ? ) - ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 ? ) - ( 29 /FPGA_Sp206 ) - ( 30 /Non_vol214 ) - ( 31 /FPGA_Sp188 ) - ( 32 /FPGA_Sp197 ) - ( 33 ? ) - ( 34 ? ) - ( 35 ? ) - ( 36 GND ) - ( 37 +3.3V ) - ( 38 ? ) - ( 39 ? ) - ( 40 ? ) - ( 41 /FPGA_Sp187 ) - ( 42 /Non_vol205 ) - ( 43 /FPGA_Sp186 ) - ( 44 /Non_vol213 ) - ( 45 ? ) - ( 46 ? ) - ( 47 ? ) - ( 48 ? ) + ( /4C4320F3/4C5D80F3 0402 L1 FB {Lib=INDUCTOR} + ( 1 +1.8V ) + ( 2 /Ethernet_Phy/ETH_A1.8V ) ) - ( /4C5F1EDC/4C71BA1D MLF16 U6 MIC2550-MLF - ( 1 /USB/USBA_SPD ) - ( 2 /FPGA_Sp217 ) - ( 3 /USB/USBA_VP ) - ( 4 /FPGA_Sp216 ) - ( 6 GND ) - ( 7 GND ) - ( 9 /USB/USBA_OE_N ) - ( 10 N-000415 ) - ( 11 N-000431 ) - ( 12 +3.3V ) - ( 14 +3.3V ) - ( 15 +2.5V ) + ( /4C4320F3/4C5D80F0 $noname C4 100nF {Lib=C} + ( 1 +1.8V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C71BA25 MLF16 U7 MIC2550-MLF - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 6 GND ) - ( 7 GND ) - ( 9 ? ) - ( 10 N-000429 ) - ( 11 N-000420 ) - ( 12 +3.3V ) - ( 14 +3.3V ) - ( 15 +2.5V ) + ( /4C4320F3/4C5D80ED $noname C2 1uF {Lib=C} + ( 1 +1.8V ) + ( 2 GND ) ) - ( /4C4227FE/4C65A75D SO8E U8 X25X64MB - ( 1 /FPGA_Sp218 ) - ( 2 /FPGA_Sp191 ) - ( 3 /FPGA_Sp220 ) - ( 4 GND ) - ( 5 /FPGA_Sp193 ) - ( 6 /FPGA_Sp192 ) - ( 7 /FPGA_Sp219 ) - ( 8 VCCO2 ) + ( /4C4320F3/4C5D7FB7 0402 L2 FB {Lib=INDUCTOR} + ( 1 +3.3V ) + ( 2 /Ethernet_Phy/ETH_A3.3V ) ) - ( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) - ( 7 ? ) - ( 8 GND ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 ? ) - ( 13 ? ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ( 17 ? ) - ( 18 ? ) - ( 19 ? ) - ( 20 ? ) - ( PAD GND ) + ( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C} + ( 1 /Ethernet_Phy/ETH_A3.3V ) + ( 2 GND ) ) - ( /4C69ED5F/4C6C9DB9 DFN10 U10 A7130 - ( 1 ? ) - ( 2 GND ) - ( 3 ? ) - ( 4 ? ) - ( 5 GND ) - ( 6 ? ) - ( 7 ? ) - ( 8 ? ) - ( 9 ? ) - ( 10 ? ) - ( PAD GND ) + ( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C} + ( 1 /Ethernet_Phy/ETH_A3.3V ) + ( 2 GND ) ) - ( /4C69ED5F/4C6D2AA5 SOT23-5 U11 A7108 - ( 1 N-000434 ) - ( 2 GND ) - ( 3 N-000445 ) - ( 4 N-000434 ) - ( 5 N-000435 ) + ( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C69ED5F/4C6D2AE0 SOT23-5 U12 A7108 - ( 1 N-000432 ) - ( 2 GND ) - ( 3 N-000464 ) - ( 4 N-000432 ) - ( 5 N-000433 ) + ( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 - ( 1 N-000431 ) - ( 2 GND ) + ( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 - ( 1 N-000415 ) - ( 2 GND ) + ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} + ( 1 /FPGA_Spartan6/ETH_MDIO ) + ( 2 +3.3V ) ) - ( /4C5F1EDC/4C6552B8 0603 V3 V0402MHS03 - ( 1 N-000420 ) - ( 2 GND ) + ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} + ( 1 N-000401 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B9 0603 V4 V0402MHS03 - ( 1 N-000429 ) - ( 2 GND ) + ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} + ( 1 /Ethernet_Phy/MAG_SHIELD ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} + ( 1 /Ethernet_Phy/MAG_SHIELD ) + ( 2 GND ) + ) + ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} + ( 1 /FPGA_Spartan6/ETH_MDIO ) + ( 2 /FPGA_Spartan6/ETH_MDC ) + ( 3 /FPGA_Spartan6/ETH_RXD3 ) + ( 4 /Ethernet_Phy/ETH_RXD2 ) + ( 5 /FPGA_Spartan6/ETH_RXD1 ) + ( 6 /Ethernet_Phy/ETH_RXD0 ) + ( 7 +3.3V ) + ( 8 GND ) + ( 9 /FPGA_Spartan6/ETH_RXDV ) + ( 10 /Ethernet_Phy/ETH_RXC ) + ( 11 /Ethernet_Phy/ETH_RXER ) + ( 12 GND ) + ( 13 +1.8V ) + ( 14 /Ethernet_Phy/ETH_TXER ) + ( 15 /Ethernet_Phy/ETH_TXC ) + ( 16 /Ethernet_Phy/ETH_TXEN ) + ( 17 /Ethernet_Phy/ETH_TXD0 ) + ( 18 /FPGA_Spartan6/ETH_TXD1 ) + ( 19 /Ethernet_Phy/ETH_TXD2 ) + ( 20 /Ethernet_Phy/ETH_TXD3 ) + ( 21 /FPGA_Spartan6/ETH_COL ) + ( 22 /FPGA_Spartan6/ETH_CRS ) + ( 23 GND ) + ( 24 +3.3V ) + ( 25 /Ethernet_Phy/ETH_INT ) + ( 26 /Ethernet_Phy/ETH_LED0 ) + ( 27 /Ethernet_Phy/ETH_LED1 ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 /Ethernet_Phy/ETH_A1.8V ) + ( 32 /Ethernet_Phy/MAG_RX- ) + ( 33 /Ethernet_Phy/MAG_RX+ ) + ( 34 ? ) + ( 35 GND ) + ( 36 GND ) + ( 37 N-000401 ) + ( 38 /Ethernet_Phy/ETH_A3.3V ) + ( 39 GND ) + ( 40 /Ethernet_Phy/MAG_TX- ) + ( 41 /Ethernet_Phy/MAG_TX+ ) + ( 42 ? ) + ( 43 ? ) + ( 44 GND ) + ( 45 ? ) + ( 46 /Ethernet_Phy/ETH_CLK ) + ( 47 /Ethernet_Phy/ETH_PLL1.8V ) + ( 48 /FPGA_Spartan6/ETH_RESET_N ) + ) + ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} + ( 1 +3.3V ) + ( 2 /Ethernet_Phy/MAG_TX+ ) + ) + ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} + ( 1 +3.3V ) + ( 2 /Ethernet_Phy/MAG_TX- ) + ) + ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} + ( 1 +3.3V ) + ( 2 /Ethernet_Phy/MAG_RX- ) + ) + ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} + ( 1 +3.3V ) + ( 2 /Ethernet_Phy/MAG_RX+ ) + ) + ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} + ( 1 N-000406 ) + ( 2 /Ethernet_Phy/ETH_LED1 ) + ) + ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} + ( 1 N-000405 ) + ( 2 /Ethernet_Phy/ETH_LED0 ) + ) + ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} + ( 1 /Ethernet_Phy/MAG_TX+ ) + ( 2 /Ethernet_Phy/MAG_TX- ) + ( 3 +3.3V ) + ( 4 GND ) + ( 5 GND ) + ( 6 +3.3V ) + ( 7 /Ethernet_Phy/MAG_RX+ ) + ( 8 /Ethernet_Phy/MAG_RX- ) + ( 9 +3.3V ) + ( 10 N-000405 ) + ( 11 +3.3V ) + ( 12 N-000406 ) + ( 13 /Ethernet_Phy/MAG_SHIELD ) + ( 14 /Ethernet_Phy/MAG_SHIELD ) + ) + ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} + ( 1 +2.5V ) + ( 2 /FPGA_Spartan6/M1_DQ0 ) + ( 3 +2.5V ) + ( 4 /FPGA_Spartan6/M1_DQ1 ) + ( 5 /DDR_Banks/M1_DQ2 ) + ( 6 GND ) + ( 7 /FPGA_Spartan6/M1_DQ3 ) + ( 8 /FPGA_Spartan6/M1_DQ4 ) + ( 9 +2.5V ) + ( 10 /FPGA_Spartan6/M1_DQ5 ) + ( 11 /FPGA_Spartan6/M1_DQ6 ) + ( 12 GND ) + ( 13 /DDR_Banks/M1_DQ7 ) + ( 14 ? ) + ( 15 +2.5V ) + ( 16 /FPGA_Spartan6/M1_LDQS ) + ( 17 ? ) + ( 18 +2.5V ) + ( 19 ? ) + ( 20 /FPGA_Spartan6/M1_LDM ) + ( 21 /FPGA_Spartan6/M1_WE# ) + ( 22 /FPGA_Spartan6/M1_CAS# ) + ( 23 /DDR_Banks/M1_RAS# ) + ( 24 /FPGA_Spartan6/M1_CS# ) + ( 25 ? ) + ( 26 /DDR_Banks/M1_BA0 ) + ( 27 /FPGA_Spartan6/M1_BA1 ) + ( 28 /FPGA_Spartan6/M1_A10 ) + ( 29 /FPGA_Spartan6/M1_A0 ) + ( 30 /FPGA_Spartan6/M1_A1 ) + ( 31 /FPGA_Spartan6/M1_A2 ) + ( 32 /FPGA_Spartan6/M1_A3 ) + ( 33 +2.5V ) + ( 34 GND ) + ( 35 /DDR_Banks/M1_A4 ) + ( 36 /DDR_Banks/M1_A5 ) + ( 37 /DDR_Banks/M1_A6 ) + ( 38 /DDR_Banks/M1_A7 ) + ( 39 /FPGA_Spartan6/M1_A8 ) + ( 40 /FPGA_Spartan6/M1_A9 ) + ( 41 /DDR_Banks/M1_A11 ) + ( 42 /DDR_Banks/M1_A12 ) + ( 43 ? ) + ( 44 /DDR_Banks/M1_CLK# ) + ( 45 /DDR_Banks/M1_CKE ) + ( 46 /DDR_Banks/M1_CLK ) + ( 47 /DDR_Banks/M1_UDM ) + ( 48 GND ) + ( 49 /DDR_Banks/M1_VREF ) + ( 50 ? ) + ( 51 /FPGA_Spartan6/M1_UDQS ) + ( 52 GND ) + ( 53 ? ) + ( 54 /DDR_Banks/M1_DQ8 ) + ( 55 +2.5V ) + ( 56 /FPGA_Spartan6/M1_DQ9 ) + ( 57 /FPGA_Spartan6/M1_DQ10 ) + ( 58 GND ) + ( 59 /FPGA_Spartan6/M1_DQ11 ) + ( 60 /DDR_Banks/M1_DQ12 ) + ( 61 +2.5V ) + ( 62 /DDR_Banks/M1_DQ13 ) + ( 63 /FPGA_Spartan6/M1_DQ14 ) + ( 64 GND ) + ( 65 /FPGA_Spartan6/M1_DQ15 ) + ( 66 GND ) + ) + ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C65D28E 0402 C71 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61D1D4 1206 C34 10uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61D151 1206 C33 10uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R} + ( 1 +2.5V ) + ( 2 /DDR_Banks/M1_VREF ) + ) + ( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R} + ( 1 /DDR_Banks/M1_VREF ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R} + ( 1 /DDR_Banks/M0_VREF ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R} + ( 1 +2.5V ) + ( 2 /DDR_Banks/M0_VREF ) + ) + ( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 /DDR_Banks/M1_VREF ) + ) + ( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP} + ( 1 /DDR_Banks/M1_VREF ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP} + ( 1 /DDR_Banks/M0_VREF ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 /DDR_Banks/M0_VREF ) + ) + ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} + ( 1 +2.5V ) + ( 2 /FPGA_Spartan6/M0_DQ0 ) + ( 3 +2.5V ) + ( 4 /DDR_Banks/M0_DQ1 ) + ( 5 /FPGA_Spartan6/M0_DQ2 ) + ( 6 GND ) + ( 7 /FPGA_Spartan6/M0_DQ3 ) + ( 8 /FPGA_Spartan6/M0_DQ4 ) + ( 9 +2.5V ) + ( 10 /DDR_Banks/M0_DQ5 ) + ( 11 /FPGA_Spartan6/M0_DQ6 ) + ( 12 GND ) + ( 13 /FPGA_Spartan6/M0_DQ7 ) + ( 14 ? ) + ( 15 +2.5V ) + ( 16 /DDR_Banks/M0_LDQS ) + ( 17 ? ) + ( 18 +2.5V ) + ( 19 ? ) + ( 20 /DDR_Banks/M0_LDM ) + ( 21 /DDR_Banks/M0_WE# ) + ( 22 /FPGA_Spartan6/M0_CAS# ) + ( 23 /DDR_Banks/M0_RAS# ) + ( 24 GND ) + ( 25 ? ) + ( 26 /FPGA_Spartan6/M0_BA0 ) + ( 27 /DDR_Banks/M0_BA1 ) + ( 28 /FPGA_Spartan6/M0_A10 ) + ( 29 /DDR_Banks/M0_A0 ) + ( 30 /FPGA_Spartan6/M0_A1 ) + ( 31 /FPGA_Spartan6/M0_A2 ) + ( 32 /FPGA_Spartan6/M0_A3 ) + ( 33 +2.5V ) + ( 34 GND ) + ( 35 /FPGA_Spartan6/M0_A4 ) + ( 36 /DDR_Banks/M0_A5 ) + ( 37 /FPGA_Spartan6/M0_A6 ) + ( 38 /DDR_Banks/M0_A7 ) + ( 39 /FPGA_Spartan6/M0_A8 ) + ( 40 /DDR_Banks/M0_A9 ) + ( 41 /FPGA_Spartan6/M0_A11 ) + ( 42 /FPGA_Spartan6/M0_A12 ) + ( 43 ? ) + ( 44 /FPGA_Spartan6/M0_CLK# ) + ( 45 /FPGA_Spartan6/M0_CKE ) + ( 46 /DDR_Banks/M0_CLK ) + ( 47 /FPGA_Spartan6/M0_UDM ) + ( 48 GND ) + ( 49 /DDR_Banks/M0_VREF ) + ( 50 ? ) + ( 51 /FPGA_Spartan6/M0_UDQS ) + ( 52 GND ) + ( 53 ? ) + ( 54 /DDR_Banks/M0_DQ8 ) + ( 55 +2.5V ) + ( 56 /FPGA_Spartan6/M0_DQ9 ) + ( 57 /DDR_Banks/M0_DQ10 ) + ( 58 GND ) + ( 59 /FPGA_Spartan6/M0_DQ11 ) + ( 60 /DDR_Banks/M0_DQ12 ) + ( 61 +2.5V ) + ( 62 /FPGA_Spartan6/M0_DQ13 ) + ( 63 /DDR_Banks/M0_DQ14 ) + ( 64 GND ) + ( 65 /DDR_Banks/M0_DQ15 ) + ( 66 GND ) ) ) * { Allowed footprints by component: -$component C1 +$component C82 SM* C? C1-1 $endlist -$component C2 +$component C83 SM* C? C1-1 $endlist -$component C3 +$component C84 SM* C? C1-1 $endlist -$component C4 +$component R27 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R28 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C85 SM* C? C1-1 $endlist -$component C5 +$component C81 SM* C? C1-1 $endlist -$component C6 +$component R26 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R25 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C80 SM* C? C1-1 $endlist -$component C7 +$component C79 SM* C? C1-1 $endlist -$component C8 +$component C78 SM* C? C1-1 $endlist -$component C9 +$component C75 SM* C? C1-1 $endlist -$component C10 +$component C74 SM* C? C1-1 $endlist -$component C11 +$component C73 SM* C? C1-1 $endlist -$component C12 +$component C72 SM* C? C1-1 $endlist -$component C13 +$component C86 SM* C? C1-1 $endlist -$component C14 +$component C87 SM* C? C1-1 $endlist -$component C15 +$component C88 SM* C? C1-1 $endlist -$component C16 +$component C89 SM* C? C1-1 $endlist -$component C17 - SM* - C? - C1-1 -$endlist -$component C18 - SM* - C? - C1-1 -$endlist -$component C19 - SM* - C? - C1-1 -$endlist -$component C20 - SM* - C? - C1-1 -$endlist -$component C21 - SM* - C? - C1-1 -$endlist -$component C22 - SM* - C? - C1-1 -$endlist -$component C23 - SM* - C? - C1-1 -$endlist -$component C24 - SM* - C? - C1-1 -$endlist -$component C25 - SM* - C? - C1-1 -$endlist -$component C26 - SM* - C? - C1-1 -$endlist -$component C27 - SM* - C? - C1-1 -$endlist -$component C28 - SM* - C? - C1-1 -$endlist -$component C29 - SM* - C? - C1-1 -$endlist -$component C30 - SM* - C? - C1-1 -$endlist -$component C31 - SM* - C? - C1-1 -$endlist -$component C32 - SM* - C? - C1-1 -$endlist -$component C33 - SM* - C? - C1-1 -$endlist -$component C34 - SM* - C? - C1-1 +$component R31 + R? + SM0603 + SM0805 + R?-* $endlist $component C35 SM* @@ -1760,290 +1746,7 @@ $component C38 C? C1-1 $endlist -$component C39 - SM* - C? - C1-1 -$endlist -$component C40 - SM* - C? - C1-1 -$endlist -$component C41 - SM* - C? - C1-1 -$endlist -$component C42 - SM* - C? - C1-1 -$endlist -$component C43 - SM* - C? - C1-1 -$endlist -$component C44 - SM* - C? - C1-1 -$endlist -$component C45 - SM* - C? - C1-1 -$endlist -$component C46 - SM* - C? - C1-1 -$endlist -$component C47 - SM* - C? - C1-1 -$endlist -$component C48 - SM* - C? - C1-1 -$endlist -$component C49 - SM* - C? - C1-1 -$endlist -$component C50 - SM* - C? - C1-1 -$endlist -$component C51 - SM* - C? - C1-1 -$endlist -$component C52 - SM* - C? - C1-1 -$endlist -$component C53 - SM* - C? - C1-1 -$endlist -$component C54 - SM* - C? - C1-1 -$endlist -$component C55 - SM* - C? - C1-1 -$endlist -$component C56 - SM* - C? - C1-1 -$endlist -$component C57 - SM* - C? - C1-1 -$endlist -$component C58 - SM* - C? - C1-1 -$endlist -$component C59 - SM* - C? - C1-1 -$endlist -$component C60 - SM* - C? - C1-1 -$endlist -$component C61 - SM* - C? - C1-1 -$endlist -$component C62 - SM* - C? - C1-1 -$endlist -$component C63 - SM* - C? - C1-1 -$endlist -$component C64 - SM* - C? - C1-1 -$endlist -$component C65 - SM* - C? - C1-1 -$endlist -$component C66 - SM* - C? - C1-1 -$endlist -$component C67 - SM* - C? - C1-1 -$endlist -$component C68 - SM* - C? - C1-1 -$endlist -$component C69 - SM* - C? - C1-1 -$endlist -$component C70 - SM* - C? - C1-1 -$endlist -$component C71 - SM* - C? - C1-1 -$endlist -$component C72 - SM* - C? - C1-1 -$endlist -$component C73 - SM* - C? - C1-1 -$endlist -$component C74 - SM* - C? - C1-1 -$endlist -$component C75 - SM* - C? - C1-1 -$endlist -$component C76 - SM* - C? - C1-1 -$endlist -$component C77 - SM* - C? - C1-1 -$endlist -$component C78 - SM* - C? - C1-1 -$endlist -$component C79 - SM* - C? - C1-1 -$endlist -$component C80 - SM* - C? - C1-1 -$endlist -$component C81 - SM* - C? - C1-1 -$endlist -$component C82 - SM* - C? - C1-1 -$endlist -$component C83 - SM* - C? - C1-1 -$endlist -$component C84 - SM* - C? - C1-1 -$endlist -$component C85 - SM* - C? - C1-1 -$endlist -$component R1 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R2 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R3 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R4 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R5 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R6 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R7 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R8 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R9 +$component R15 R? SM0603 SM0805 @@ -2055,49 +1758,67 @@ $component R10 SM0805 R?-* $endlist -$component R11 +$component C16 + SM* + C? + C1-1 +$endlist +$component C15 + SM* + C? + C1-1 +$endlist +$component C14 + SM* + C? + C1-1 +$endlist +$component C13 + SM* + C? + C1-1 +$endlist +$component R30 R? SM0603 SM0805 R?-* $endlist -$component R12 +$component R29 R? SM0603 SM0805 R?-* $endlist -$component R13 +$component C77 + SM* + C? + C1-1 +$endlist +$component C76 + SM* + C? + C1-1 +$endlist +$component R23 R? SM0603 SM0805 R?-* $endlist -$component R14 +$component R22 R? SM0603 SM0805 R?-* $endlist -$component R15 +$component R24 R? SM0603 SM0805 R?-* $endlist -$component R16 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R17 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R18 +$component R21 R? SM0603 SM0805 @@ -2115,65 +1836,1644 @@ $component R20 SM0805 R?-* $endlist -$component R21 +$component R17 R? SM0603 SM0805 R?-* $endlist -$component R22 +$component R18 R? SM0603 SM0805 R?-* $endlist -$component R23 +$component R16 R? SM0603 SM0805 R?-* $endlist -$component R24 +$component C66 + SM* + C? + C1-1 +$endlist +$component C63 + SM* + C? + C1-1 +$endlist +$component C60 + SM* + C? + C1-1 +$endlist +$component C57 + SM* + C? + C1-1 +$endlist +$component C54 + SM* + C? + C1-1 +$endlist +$component C69 + SM* + C? + C1-1 +$endlist +$component C67 + SM* + C? + C1-1 +$endlist +$component C64 + SM* + C? + C1-1 +$endlist +$component C61 + SM* + C? + C1-1 +$endlist +$component C58 + SM* + C? + C1-1 +$endlist +$component C55 + SM* + C? + C1-1 +$endlist +$component C68 + SM* + C? + C1-1 +$endlist +$component C65 + SM* + C? + C1-1 +$endlist +$component C62 + SM* + C? + C1-1 +$endlist +$component C59 + SM* + C? + C1-1 +$endlist +$component C56 + SM* + C? + C1-1 +$endlist +$component C50 + SM* + C? + C1-1 +$endlist +$component C47 + SM* + C? + C1-1 +$endlist +$component C44 + SM* + C? + C1-1 +$endlist +$component C41 + SM* + C? + C1-1 +$endlist +$component C53 + SM* + C? + C1-1 +$endlist +$component C51 + SM* + C? + C1-1 +$endlist +$component C49 + SM* + C? + C1-1 +$endlist +$component C46 + SM* + C? + C1-1 +$endlist +$component C52 + SM* + C? + C1-1 +$endlist +$component C43 + SM* + C? + C1-1 +$endlist +$component C40 + SM* + C? + C1-1 +$endlist +$component C48 + SM* + C? + C1-1 +$endlist +$component C45 + SM* + C? + C1-1 +$endlist +$component C42 + SM* + C? + C1-1 +$endlist +$component C39 + SM* + C? + C1-1 +$endlist +$component C9 + SM* + C? + C1-1 +$endlist +$component C6 + SM* + C? + C1-1 +$endlist +$component C4 + SM* + C? + C1-1 +$endlist +$component C2 + SM* + C? + C1-1 +$endlist +$component C8 + SM* + C? + C1-1 +$endlist +$component C7 + SM* + C? + C1-1 +$endlist +$component C5 + SM* + C? + C1-1 +$endlist +$component C3 + SM* + C? + C1-1 +$endlist +$component C1 + SM* + C? + C1-1 +$endlist +$component R1 R? SM0603 SM0805 R?-* $endlist -$component R25 +$component R2 R? SM0603 SM0805 R?-* $endlist -$component R26 +$component C11 + SM* + C? + C1-1 +$endlist +$component C10 + SM* + C? + C1-1 +$endlist +$component C12 + SM* + C? + C1-1 +$endlist +$component R9 R? SM0603 SM0805 R?-* $endlist -$component R27 +$component R3 R? SM0603 SM0805 R?-* $endlist -$component R28 +$component R4 R? SM0603 SM0805 R?-* $endlist -$component R29 +$component R6 R? SM0603 SM0805 R?-* $endlist -$component R30 +$component R5 R? SM0603 SM0805 R?-* $endlist +$component R8 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R7 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C70 + SM* + C? + C1-1 +$endlist +$component C71 + SM* + C? + C1-1 +$endlist +$component C34 + SM* + C? + C1-1 +$endlist +$component C33 + SM* + C? + C1-1 +$endlist +$component C28 + SM* + C? + C1-1 +$endlist +$component C29 + SM* + C? + C1-1 +$endlist +$component C31 + SM* + C? + C1-1 +$endlist +$component C30 + SM* + C? + C1-1 +$endlist +$component C32 + SM* + C? + C1-1 +$endlist +$component C27 + SM* + C? + C1-1 +$endlist +$component C21 + SM* + C? + C1-1 +$endlist +$component C26 + SM* + C? + C1-1 +$endlist +$component C24 + SM* + C? + C1-1 +$endlist +$component C25 + SM* + C? + C1-1 +$endlist +$component C23 + SM* + C? + C1-1 +$endlist +$component C22 + SM* + C? + C1-1 +$endlist +$component R13 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R14 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R12 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R11 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C19 + SM* + C? + C1-1 +$endlist +$component C20 + SM* + C? + C1-1 +$endlist +$component C18 + SM* + C? + C1-1 +$endlist +$component C17 + SM* + C? + C1-1 +$endlist $endfootprintlist } +{ Pin List by Nets +Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" + U1 T5 + U8 1 +Net 2 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" + U1 AA21 + U8 6 +Net 3 "/Non volatile memories/NF_RNB" "NF_RNB" + U1 A15 + U5 7 + U5 6 +Net 4 "/Non volatile memories/NF_RE_N" "NF_RE_N" + U1 C15 + U5 8 +Net 5 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" + U1 D15 + U5 9 +Net 6 "/Non volatile memories/NF_ALE" "NF_ALE" + U1 A14 + U5 17 +Net 7 "/Non volatile memories/NF_WE_N" "NF_WE_N" + U1 C14 + U5 18 +Net 8 "/FPGA Spartan6/ETH_COL" "ETH_COL" + U4 21 + U1 A9 +Net 9 "/Ethernet Phy/ETH_TXC" "ETH_TXC" + U4 15 + U1 C8 +Net 10 "/Ethernet Phy/ETH_RXC" "ETH_RXC" + U4 10 + U1 A7 +Net 11 "/USB/USBA_SPD" "USBA_SPD" + U6 1 + U1 C19 +Net 12 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" + U1 B20 + U6 9 +Net 13 "/USB/USBA_RCV" "USBA_RCV" + U6 2 + U1 G16 +Net 14 "/USB/USBA_VP" "USBA_VP" + U1 G17 + U6 3 +Net 15 "/USB/USBA_VM" "USBA_VM" + U6 4 + U1 F16 +Net 16 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" + U1 B10 + U4 22 +Net 17 "/FPGA Spartan6/SD_CLK" "SD_CLK" + J1 5 + U1 E16 +Net 18 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" + U1 D7 + U4 2 +Net 19 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" + U4 1 + R1 1 + U1 D6 +Net 20 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" + U4 48 + U1 C7 +Net 21 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" + U1 A6 + U4 9 +Net 22 "/Ethernet Phy/ETH_RXER" "ETH_RXER" + U1 B8 + U4 11 +Net 23 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" + U1 D9 + U4 16 +Net 24 "/FPGA Spartan6/M1_CS#" "M1_CS#" + U3 24 + R20 2 +Net 25 "/DDR Banks/M1_UDM" "M1_UDM" + U3 47 + R18 2 +Net 26 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" + U3 16 + RP3 8 +Net 27 "/FPGA Spartan6/M1_LDM" "M1_LDM" + RP3 7 + U3 20 +Net 28 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" + U3 51 + R19 2 +Net 29 "/FPGA Spartan6/M0_UDQS" "M0_UDQS" + R22 2 + U2 51 +Net 30 "/DDR Banks/M0_LDM" "M0_LDM" + RP16 7 + U2 20 +Net 31 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" + U3 22 + RP3 5 +Net 32 "/DDR Banks/M1_CKE" "M1_CKE" + R17 2 + U3 45 +Net 33 "/DDR Banks/M1_CLK" "M1_CLK" + U1 H20 + U3 46 + R16 2 +Net 34 "/DDR Banks/M1_CLK#" "M1_CLK#" + U1 J19 + U3 44 + R16 1 +Net 35 "GND" "GND" + C63 2 + C60 2 + U2 34 + U3 58 + C21 2 + C34 2 + C26 2 + C71 2 + C70 2 + C66 2 + C24 2 + C25 2 + C27 2 + C23 2 + U1 R5 + U1 E7 + U1 H7 + U1 U7 + U1 W7 + U1 L13 + U1 N13 + U1 K14 + U1 M14 + U1 P14 + U1 V14 + U1 J2 + U2 58 + U2 48 + U1 N2 + U1 U2 + U1 D4 + U1 V4 + U1 B5 + U1 G5 + U1 L5 + L11 2 + U1 W16 + U1 B17 + U1 N17 + U1 L11 + U1 N11 + U1 E21 + U1 J21 + U1 N21 + U1 U21 + U1 AB1 + C32 2 + U1 K12 + C30 2 + U1 M12 + C31 2 + U1 P12 + C29 2 + U1 A22 + C28 2 + U1 B13 + U1 J13 + C33 2 + U1 E15 + C9 2 + C6 2 + C4 2 + C2 2 + U1 J15 + C8 2 + C7 2 + U1 N15 + U1 AA5 + U5 13 + J4 4 + J4 5 + U4 39 + U5 36 + R2 2 + C11 2 + U4 44 + U4 35 + C74 2 + C75 1 + U4 36 + U4 12 + U4 23 + C10 2 + C12 2 + R9 2 + C72 2 + C73 2 + U4 8 + C5 2 + C3 2 + C1 2 + U8 4 + U2 64 + C18 2 + C49 2 + C20 2 + C46 2 + C52 2 + C43 2 + C40 2 + R12 2 + C48 2 + C45 2 + R14 2 + C42 2 + C39 2 + C22 2 + U2 24 + C57 2 + C54 2 + C69 2 + C67 2 + U2 52 + U2 12 + C64 2 + C61 2 + C58 2 + U2 66 + J1 CASE + J1 CASE + J1 CASE + J1 COM + J1 6 + U2 6 + C55 2 + C68 2 + C65 2 + C62 2 + C59 2 + C56 2 + C50 2 + C47 2 + C44 2 + C41 2 + C53 2 + C51 2 + C13 2 + C14 2 + U7 7 + U6 6 + U6 7 + R10 2 + L5 2 + C15 2 + V2 2 + V1 2 + C16 2 + U3 64 + U13 6 + U3 34 + U13 7 + U3 52 + U7 6 + U3 12 + C81 2 + U9 8 + U9 PAD + U11 2 + U10 2 + U10 5 + U10 PAD + C80 2 + R25 2 + C78 2 + U12 2 + R27 2 + C85 2 + C82 2 + C84 2 + U1 P10 + U1 AB22 + U1 AA13 + L7 2 + U1 AA17 + U1 L18 + U1 R18 + U1 E11 + C38 2 + U1 W19 + U1 AA9 + R15 2 + U1 A1 + U1 V10 + U1 B9 + C77 2 + C76 2 + C35 2 + C86 2 + C36 2 + V3 2 + V4 2 + C37 2 + U1 M10 + C87 2 + U1 K10 + U1 N9 + U1 L9 + U1 J9 + R31 2 + U3 48 + C88 2 + V6 2 + U3 66 + V5 2 + C89 2 + U1 J11 + U1 D18 + U1 G18 + U1 E2 + U3 6 +Net 36 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" + U1 H3 + U2 44 + R21 2 +Net 37 "/DDR Banks/M0_CLK" "M0_CLK" + U1 H4 + R21 1 + U2 46 +Net 38 "/FPGA Spartan6/M0_CKE" "M0_CKE" + U2 45 + R24 2 +Net 39 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" + RP16 5 + U2 22 +Net 40 "/FPGA Spartan6/M1_WE#" "M1_WE#" + RP3 6 + U3 21 +Net 41 "/DDR Banks/M1_RAS#" "M1_RAS#" + U3 23 + RP2 8 +Net 42 "/DDR Banks/M0_RAS#" "M0_RAS#" + U2 23 + RP15 8 +Net 43 "/DDR Banks/M0_WE#" "M0_WE#" + U2 21 + RP16 6 +Net 44 "/Ethernet Phy/ETH_INT" "ETH_INT" + U4 25 + U1 A10 +Net 45 "/Ethernet Phy/ETH_CLK" "ETH_CLK" + U1 A4 + U4 46 +Net 46 "/Ethernet Phy/ETH_TXER" "ETH_TXER" + U1 D8 + U4 14 +Net 47 "/DDR Banks/M0_LDQS" "M0_LDQS" + RP16 8 + U2 16 +Net 48 "/FPGA Spartan6/M0_UDM" "M0_UDM" + U2 47 + R23 2 +Net 49 "/Non volatile memories/NF_CLE" "NF_CLE" + U1 B14 + U5 16 +Net 50 "/FPGA Spartan6/SD_CMD" "SD_CMD" + U1 D17 + J1 3 +Net 51 "/DBG_PRG/FPGA_TCK" "FPGA_TCK" + U1 G15 + J6 1 +Net 52 "/DBG_PRG/FPGA_TMS" "FPGA_TMS" + J6 3 + U1 C18 +Net 53 "/DBG_PRG/FPGA_TDI" "FPGA_TDI" + J6 7 + U1 E18 +Net 54 "/DBG_PRG/FPGA_TDO" "FPGA_TDO" + U1 A19 + J6 5 +Net 59 "+2.5V" "+2.5V" + C70 1 + U3 15 + C60 1 + U1 R2 + C63 1 + U1 C21 + U1 J5 + U1 N5 + U1 U5 + U1 F6 + U1 L7 + C66 1 + U3 1 + U1 W2 + U3 55 + U3 18 + C34 1 + U13 15 + U1 F4 + C71 1 + U3 33 + U1 C2 + U1 G2 + U1 L2 + U2 1 + C68 1 + U2 3 + U2 9 + R13 1 + R11 1 + C49 1 + C51 1 + C53 1 + C56 1 + C59 1 + C62 1 + C17 1 + C65 1 + U2 18 + U2 61 + U2 33 + C54 1 + C57 1 + C40 1 + C19 1 + C43 1 + C52 1 + C46 1 + U2 15 + U2 55 + U1 H15 + U1 K15 + U1 M15 + U1 D16 + U1 U11 + C27 1 + U1 G12 + U1 L16 + C28 1 + C29 1 + U1 R12 + C31 1 + C37 1 + C30 1 + C32 1 + U1 N8 + U1 L8 + U1 H9 + C77 1 + U1 R10 + U1 V6 + U1 R6 + C88 1 + U1 F11 + C23 1 + C25 1 + C24 1 + C26 1 + C21 1 + U3 61 + U1 J18 + U1 N18 + U1 U18 + U1 E19 + U1 G21 + U1 L21 + U1 R21 + U3 9 + C22 1 + C33 1 + U3 3 + U1 W21 + U7 15 + C15 1 + U6 15 +Net 62 "/DDR Banks/M0_VREF" "M0_VREF" + C18 1 + R11 2 + R12 1 + U2 49 + C17 2 +Net 63 "/DDR Banks/M1_VREF" "M1_VREF" + C19 2 + R14 1 + R13 2 + C20 1 + U3 49 +Net 102 "+3.3V" "+3.3V" + U1 E13 + R5 1 + U1 B11 + U1 G10 + U1 B4 + U1 B7 + C75 2 + R30 1 + U1 B19 + U5 12 + C80 1 + U1 E17 + R29 1 + C79 1 + U1 G14 + U1 B15 + U1 Y20 + R6 1 + R4 1 + R26 1 + C3 1 + U4 7 + L2 1 + C5 1 + L8 1 + C35 1 + C36 1 + C11 1 + R1 2 + C81 1 + C86 1 + C1 1 + C87 1 + U4 24 + C74 1 + C73 1 + C72 1 + C10 1 + J4 11 + J4 9 + J4 6 + U6 14 + U6 12 + U7 14 + U7 12 + C14 1 + C50 1 + C47 1 + C44 1 + C41 1 + J1 4 + U5 19 + U5 37 + U13 14 + U13 12 + C13 1 + R3 1 + U1 E9 + J4 3 +Net 103 "VCCO2" "VCCO2" + U8 8 + C61 1 + U1 AA11 + C64 1 + C58 1 + C67 1 + C69 1 + C55 1 + U1 AA15 + U1 V16 + U1 AA19 + U1 AA7 + U1 T13 + U1 V12 + U1 AA3 + U1 V8 + U1 T9 + U1 W5 +Net 105 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" + RP3 4 + U1 H22 +Net 106 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" + U1 H19 + RP3 3 +Net 107 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" + RP3 2 + U1 L19 +Net 108 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" + RP3 1 + U1 L20 +Net 109 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" + U1 K17 + RP2 3 +Net 110 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" + RP2 2 + U1 J17 +Net 111 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" + U1 H21 + RP2 1 +Net 120 "/FPGA Spartan6/R_M0_A3" "R_M0_A3" + RP14 4 + U1 K6 +Net 122 "/FPGA Spartan6/R_M0_A7" "R_M0_A7" + U1 H6 + RP17 1 +Net 127 "/FPGA Spartan6/R_M0_A2" "R_M0_A2" + RP14 3 + U1 H5 +Net 136 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" + U1 F21 + RP1 1 +Net 137 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" + R17 1 + U1 D21 +Net 142 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" + RP8 5 + U1 U20 +Net 144 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" + RP9 7 + U1 R20 +Net 146 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" + U1 N20 + RP5 1 +Net 147 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" + RP6 6 + U1 K20 +Net 148 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" + U1 J20 + RP4 1 +Net 149 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" + U1 G20 + RP1 4 +Net 151 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" + RP6 8 + U1 E20 +Net 153 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" + U1 C20 + RP7 5 +Net 162 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" + U1 P2 + RP11 1 +Net 163 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" + RP13 3 + U1 M2 +Net 164 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" + U1 K2 + RP12 3 +Net 165 "/FPGA Spartan6/R_M0_A0" "R_M0_A0" + U1 H2 + RP14 1 +Net 170 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" + RP10 4 + U1 V1 +Net 171 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" + RP10 2 + U1 U1 +Net 173 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" + U1 R1 + RP11 4 +Net 174 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" + RP11 2 + U1 P1 +Net 175 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" + RP13 2 + U1 N1 +Net 176 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" + U1 M1 + RP13 4 +Net 178 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" + U1 K1 + RP12 4 +Net 179 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" + RP12 2 + U1 J1 +Net 180 "/FPGA Spartan6/R_M0_A1" "R_M0_A1" + U1 H1 + RP14 2 +Net 181 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1" + U1 G1 + RP15 3 +Net 183 "/FPGA Spartan6/R_M0_A9" "R_M0_A9" + U1 E1 + RP18 3 +Net 184 "/FPGA Spartan6/R_M0_A12" "R_M0_A12" + U1 D1 + RP18 1 +Net 185 "/FPGA Spartan6/R_M0_A11" "R_M0_A11" + U1 C1 + RP18 2 +Net 188 "/FPGA Spartan6/R_M0_A6" "R_M0_A6" + U1 J4 + RP17 2 +Net 189 "/FPGA Spartan6/R_M0_A10" "R_M0_A10" + U1 G4 + RP15 4 +Net 194 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" + U1 U3 + RP10 1 +Net 196 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10" + U1 R3 + RP11 3 +Net 198 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" + U1 N3 + RP13 1 +Net 199 "/FPGA Spartan6/R_M0_LDQS" "R_M0_LDQS" + RP16 1 + U1 L3 +Net 200 "/FPGA Spartan6/R_M0_A5" "R_M0_A5" + RP17 3 + U1 K3 +Net 201 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" + RP12 1 + U1 J3 +Net 202 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0" + U1 G3 + RP15 2 +Net 203 "/FPGA Spartan6/R_M0_A4" "R_M0_A4" + U1 F3 + RP17 4 +Net 204 "/FPGA Spartan6/R_M0_A8" "R_M0_A8" + U1 E3 + RP18 4 +Net 209 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" + RP10 3 + U1 V2 +Net 210 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS" + U1 T2 + R22 1 +Net 224 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" + RP8 8 + U1 V22 +Net 225 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" + U1 U22 + RP8 6 +Net 227 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" + U1 R22 + RP9 8 +Net 228 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" + RP9 6 + U1 P22 +Net 229 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" + RP5 2 + U1 N22 +Net 230 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" + RP5 4 + U1 M22 +Net 232 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" + RP4 4 + U1 K22 +Net 233 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" + U1 J22 + RP4 2 +Net 235 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" + RP1 2 + U1 F22 +Net 236 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" + RP1 3 + U1 E22 +Net 237 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" + U1 D22 + RP7 8 +Net 238 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" + RP7 6 + U1 C22 +Net 240 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" + RP8 7 + U1 V21 +Net 241 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" + RP9 5 + U1 P21 +Net 242 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" + U1 M21 + RP5 3 +Net 243 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" + U1 K21 + RP4 3 +Net 244 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" + RP6 7 + U1 K19 +Net 245 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" + RP2 4 + U1 G19 +Net 246 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" + U1 F19 + RP7 7 +Net 262 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" + R20 1 + U1 H16 +Net 267 "" "" + R30 2 + U1 Y22 +Net 278 "+1.2V" "+1.2V" + C83 1 + C76 1 + C84 1 + R28 1 + L9 1 + C85 1 + C42 1 + C45 1 + C48 1 + U1 M9 + U1 P9 + U1 J10 + U1 N12 + U1 L12 + U1 L10 + U1 N10 + U1 J8 + U1 K11 + U1 K13 + U1 M13 + U1 P13 + U1 J14 + U1 L14 + U1 N14 + U1 R14 + U1 M11 + U1 P11 + U1 J12 + U1 K9 + C39 1 +Net 384 "/FPGA Spartan6/R_M0_CAS#" "R_M0_CAS#" + RP16 4 + U1 K4 +Net 385 "/FPGA Spartan6/R_M0_WE#" "R_M0_WE#" + RP16 3 + U1 F2 +Net 386 "/FPGA Spartan6/R_M0_RAS#" "R_M0_RAS#" + RP15 1 + U1 K5 +Net 387 "/FPGA Spartan6/R_M0_CKE" "R_M0_CKE" + R24 1 + U1 D2 +Net 388 "/FPGA Spartan6/R_M0_UDM" "R_M0_UDM" + R23 1 + U1 M3 +Net 389 "/FPGA Spartan6/R_M0_LDM" "R_M0_LDM" + RP16 2 + U1 L4 +Net 390 "" "" + U1 AA1 + R29 2 +Net 391 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" + R19 1 + U1 T21 +Net 392 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" + U1 M20 + R18 1 +Net 395 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + U4 31 + L1 2 + C6 1 + L3 1 +Net 398 "/Ethernet Phy/ETH_LED1" "ETH_LED1" + U4 27 + R8 2 +Net 401 "" "" + U4 37 + R2 1 +Net 403 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD" + J4 14 + R9 1 + C12 1 + J4 13 +Net 404 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + U4 26 + R7 2 +Net 405 "" "" + R7 1 + J4 10 +Net 406 "" "" + R8 1 + J4 12 +Net 407 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + L2 2 + U4 38 + C8 1 + C7 1 +Net 408 "+1.8V" "+1.8V" + C2 1 + C4 1 + L1 1 + U4 13 +Net 409 "/Ethernet Phy/MAG_TX-" "MAG_TX-" + R4 2 + J4 2 + U4 40 +Net 410 "/Ethernet Phy/MAG_RX-" "MAG_RX-" + J4 8 + U4 32 + R6 2 +Net 411 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + L3 2 + U4 47 + C9 1 +Net 412 "/Ethernet Phy/MAG_RX+" "MAG_RX+" + U4 33 + J4 7 + R5 2 +Net 413 "/Ethernet Phy/MAG_TX+" "MAG_TX+" + R3 2 + U4 41 + J4 1 +Net 415 "" "" + L10 1 + F2 1 +Net 416 "+5V" "+5V" + F2 2 + F1 2 +Net 417 "" "" + U13 11 + V5 1 + V5 1 +Net 422 "" "" + U7 10 + V4 1 + V4 1 +Net 427 "" "" + V3 1 + V3 1 + U7 11 +Net 428 "" "" + U6 10 + V2 1 + J5 2 + V2 1 +Net 429 "" "" + V1 1 + J5 3 + V1 1 + U6 11 +Net 430 "" "" + J5 1 + L4 2 +Net 431 "" "" + L5 1 + J5 4 +Net 432 "" "" + L4 1 + F1 1 +Net 433 "" "" + J5 S4 + C16 1 + J5 S3 + J5 S2 + J5 S1 + R10 1 +Net 435 "" "" + C38 1 + R15 1 +Net 440 "" "" + V6 1 + V6 1 + U13 10 +Net 441 "" "" + R31 1 + C89 1 +Net 442 "" "" + C82 1 + U12 1 + U12 4 +Net 443 "" "" + U12 5 + R27 1 + R28 2 + C83 2 +Net 444 "" "" + U11 4 + U11 1 + C78 1 +Net 445 "" "" + C79 2 + R25 1 + R26 2 + U11 5 +Net 455 "" "" + L8 2 + U11 3 +Net 474 "" "" + U12 3 + L9 2 +Net 487 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" + U8 7 + U1 U13 +Net 488 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" + U1 U14 + U8 3 +Net 489 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" + U1 AA20 + U8 2 +Net 490 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" + U8 5 + U1 AB20 +Net 491 "/FPGA Spartan6/NF_D7" "NF_D7" + U5 44 + U1 D11 +Net 492 "/Non volatile memories/NF_D6" "NF_D6" + U1 A11 + U5 43 +Net 493 "/FPGA Spartan6/NF_D5" "NF_D5" + U5 42 + U1 C11 +Net 494 "/FPGA Spartan6/NF_D4" "NF_D4" + U1 A12 + U5 41 +Net 495 "/FPGA Spartan6/NF_D3" "NF_D3" + U1 B12 + U5 32 +Net 496 "/Non volatile memories/NF_D2" "NF_D2" + U1 A13 + U5 31 +Net 497 "/FPGA Spartan6/NF_D1" "NF_D1" + U5 30 + U1 D14 +Net 498 "/Non volatile memories/NF_D0" "NF_D0" + U5 29 + U1 C12 +Net 499 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" + U1 A8 + U4 20 +Net 500 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" + U4 19 + U1 C10 +Net 501 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" + U1 C9 + U4 18 +Net 502 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" + U1 D10 + U4 17 +Net 503 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" + U4 3 + U1 C5 +Net 504 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" + U1 C6 + U4 4 +Net 505 "/FPGA Spartan6/ETH_RXD1" "ETH_RXD1" + U1 A5 + U4 5 +Net 506 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" + U1 B6 + U4 6 +Net 507 "/DDR Banks/M0_BA1" "M0_BA1" + RP15 6 + U2 27 +Net 508 "/FPGA Spartan6/M0_BA0" "M0_BA0" + RP15 7 + U2 26 +Net 509 "/FPGA Spartan6/M1_BA1" "M1_BA1" + RP2 6 + U3 27 +Net 510 "/DDR Banks/M1_BA0" "M1_BA0" + U3 26 + RP2 7 +Net 511 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" + RP8 1 + U3 65 +Net 512 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" + U3 63 + RP8 2 +Net 513 "/DDR Banks/M1_DQ13" "M1_DQ13" + RP8 3 + U3 62 +Net 514 "/DDR Banks/M1_DQ12" "M1_DQ12" + U3 60 + RP8 4 +Net 515 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" + RP9 1 + U3 59 +Net 516 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" + U3 57 + RP9 2 +Net 517 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" + RP9 3 + U3 56 +Net 518 "/DDR Banks/M1_DQ8" "M1_DQ8" + U3 54 + RP9 4 +Net 519 "/Non volatile memories/SD_DAT3" "SD_DAT3" + U1 C17 + J1 2 +Net 520 "/FPGA Spartan6/SD_DAT2" "SD_DAT2" + J1 1 + U1 A17 +Net 521 "/Non volatile memories/SD_DAT1" "SD_DAT1" + J1 8 + U1 B18 +Net 522 "/FPGA Spartan6/SD_DAT0" "SD_DAT0" + J1 7 + U1 A18 +Net 523 "/DDR Banks/M1_A6" "M1_A6" + U3 37 + RP6 2 +Net 524 "/DDR Banks/M1_A5" "M1_A5" + U3 36 + RP6 3 +Net 525 "/DDR Banks/M1_A4" "M1_A4" + U3 35 + RP6 4 +Net 526 "/FPGA Spartan6/M1_A3" "M1_A3" + U3 32 + RP1 5 +Net 527 "/FPGA Spartan6/M1_A2" "M1_A2" + RP1 6 + U3 31 +Net 528 "/FPGA Spartan6/M1_A1" "M1_A1" + RP1 7 + U3 30 +Net 529 "/FPGA Spartan6/M1_A0" "M1_A0" + U3 29 + RP1 8 +Net 530 "/FPGA Spartan6/M0_A12" "M0_A12" + RP18 8 + U2 42 +Net 531 "/FPGA Spartan6/M0_A11" "M0_A11" + RP18 7 + U2 41 +Net 532 "/FPGA Spartan6/M0_A10" "M0_A10" + RP15 5 + U2 28 +Net 533 "/DDR Banks/M0_A9" "M0_A9" + U2 40 + RP18 6 +Net 534 "/FPGA Spartan6/M0_A8" "M0_A8" + U2 39 + RP18 5 +Net 535 "/DDR Banks/M0_A7" "M0_A7" + U2 38 + RP17 8 +Net 536 "/FPGA Spartan6/M0_A6" "M0_A6" + RP17 7 + U2 37 +Net 537 "/DDR Banks/M1_DQ7" "M1_DQ7" + RP4 5 + U3 13 +Net 538 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" + U3 11 + RP4 6 +Net 539 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" + RP4 7 + U3 10 +Net 540 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" + RP4 8 + U3 8 +Net 541 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" + U3 7 + RP5 5 +Net 542 "/DDR Banks/M1_DQ2" "M1_DQ2" + U3 5 + RP5 6 +Net 543 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" + RP5 7 + U3 4 +Net 544 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" + RP5 8 + U3 2 +Net 545 "/DDR Banks/M1_A12" "M1_A12" + U3 42 + RP7 1 +Net 546 "/DDR Banks/M1_A11" "M1_A11" + U3 41 + RP7 2 +Net 547 "/FPGA Spartan6/M1_A10" "M1_A10" + RP2 5 + U3 28 +Net 548 "/FPGA Spartan6/M1_A9" "M1_A9" + RP7 3 + U3 40 +Net 549 "/FPGA Spartan6/M1_A8" "M1_A8" + RP7 4 + U3 39 +Net 550 "/DDR Banks/M1_A7" "M1_A7" + U3 38 + RP6 1 +Net 551 "/DDR Banks/M0_DQ1" "M0_DQ1" + U2 4 + RP13 7 +Net 552 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" + U2 2 + RP13 8 +Net 553 "/DDR Banks/M0_A5" "M0_A5" + U2 36 + RP17 6 +Net 554 "/FPGA Spartan6/M0_A4" "M0_A4" + U2 35 + RP17 5 +Net 555 "/FPGA Spartan6/M0_A3" "M0_A3" + RP14 5 + U2 32 +Net 556 "/FPGA Spartan6/M0_A2" "M0_A2" + RP14 6 + U2 31 +Net 557 "/FPGA Spartan6/M0_A1" "M0_A1" + U2 30 + RP14 7 +Net 558 "/DDR Banks/M0_A0" "M0_A0" + U2 29 + RP14 8 +Net 559 "/DDR Banks/M0_DQ15" "M0_DQ15" + U2 65 + RP10 5 +Net 560 "/DDR Banks/M0_DQ14" "M0_DQ14" + RP10 6 + U2 63 +Net 561 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" + U2 62 + RP10 7 +Net 562 "/DDR Banks/M0_DQ12" "M0_DQ12" + U2 60 + RP10 8 +Net 563 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" + U2 59 + RP11 5 +Net 564 "/DDR Banks/M0_DQ10" "M0_DQ10" + U2 57 + RP11 6 +Net 565 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" + RP11 7 + U2 56 +Net 566 "/DDR Banks/M0_DQ8" "M0_DQ8" + U2 54 + RP11 8 +Net 567 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" + U2 13 + RP12 5 +Net 568 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" + RP12 6 + U2 11 +Net 569 "/DDR Banks/M0_DQ5" "M0_DQ5" + RP12 7 + U2 10 +Net 570 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" + U2 8 + RP12 8 +Net 571 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" + RP13 5 + U2 7 +Net 572 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" + U2 5 + RP13 6 +} +#End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 1acb272..9b5d30c 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Sun 22 Aug 2010 07:04:53 PM COT +update=Sun 22 Aug 2010 08:28:20 PM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index ac1b428..d731688 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 22 Aug 2010 07:03:34 PM COT +EESchema Schematic File Version 2 date Sun 22 Aug 2010 08:15:24 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03