diff --git a/kicad/library/pasives-connectors.lib b/kicad/library/pasives-connectors.lib new file mode 100644 index 0000000..343a7ce --- /dev/null +++ b/kicad/library/pasives-connectors.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 Date: Tue 10 Aug 2010 04:58:24 PM COT +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "Cap" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +S -50 -25 -50 -25 0 1 0 N +S -50 -25 50 -25 0 1 20 N +S -50 25 50 25 0 1 20 N +X ~ 1 0 100 65 D 40 40 1 1 P +X ~ 2 0 -100 65 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 9292acd..5802e47 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT +EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -40,6 +40,7 @@ LIBS:opto LIBS:atmel LIBS:contrib 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2 "0402" H 9850 1850 60 0001 C CNN + 1 9850 1850 + 1 0 0 -1 +$EndComp +$Comp +L +2.5V #PWR016 +U 1 1 4C61CE2F +P 9850 1000 +F 0 "#PWR016" H 9850 950 20 0001 C CNN +F 1 "+2.5V" H 9850 1100 30 0000 C CNN + 1 9850 1000 + 1 0 0 -1 +$EndComp +$Comp +L +2.5V #PWR017 +U 1 1 4C61CDF1 +P 4550 900 +F 0 "#PWR017" H 4550 850 20 0001 C CNN +F 1 "+2.5V" H 4550 1000 30 0000 C CNN + 1 4550 900 + 1 0 0 -1 +$EndComp +$Comp +L R R12 +U 1 1 4C61CDB5 +P 4550 1750 +F 0 "R12" V 4630 1750 50 0000 C CNN +F 1 "1K 1%" V 4550 1750 50 0000 C CNN +F 2 "0402" H 4550 1750 60 0001 C CNN + 1 4550 1750 + 1 0 0 -1 +$EndComp +$Comp +L R R11 +U 1 1 4C61CD4A +P 4550 1200 +F 0 "R11" V 4630 1200 50 0000 C CNN +F 1 "1K 1%" V 4550 1200 50 0000 C CNN +F 2 "0402" H 4550 1200 60 0001 C CNN + 1 4550 1200 + 1 0 0 -1 +$EndComp +$Comp +L CAP C19 +U 1 1 4C61CCE3 +P 10150 1300 +F 0 "C19" H 10200 1400 50 0000 L CNN +F 1 "100nF" H 10200 1200 50 0000 L CNN +F 2 "0402" H 10150 1300 60 0001 C CNN + 1 10150 1300 + 1 0 0 -1 +$EndComp +$Comp +L CAP C20 +U 1 1 4C61CCE2 +P 10150 1850 +F 0 "C20" H 10200 1950 50 0000 L CNN +F 1 "100nF" H 10200 1750 50 0000 L CNN +F 2 "0402" H 10150 1850 60 0001 C CNN + 1 10150 1850 + 1 0 0 -1 +$EndComp +$Comp +L CAP C18 +U 1 1 4C61CC96 +P 4850 1750 +F 0 "C18" H 4900 1850 50 0000 L CNN +F 1 "100nF" H 4900 1650 50 0000 L CNN +F 2 "0402" H 4850 1750 60 0001 C CNN + 1 4850 1750 + 1 0 0 -1 +$EndComp +$Comp +L CAP C17 +U 1 1 4C61CC73 +P 4850 1200 +F 0 "C17" H 4900 1300 50 0000 L CNN +F 1 "100nF" H 4900 1100 50 0000 L CNN +F 2 "0402" H 4850 1200 60 0001 C CNN + 1 4850 1200 + 1 0 0 -1 +$EndComp $Comp L MT46V32M16TG U3 U 1 1 4C609C8E @@ -386,13 +839,13 @@ F 1 "MT46V32M16TG" H 3100 3350 70 0000 C CNN 1 3100 3450 1 0 0 -1 $EndComp -Text HLabel 4950 5700 2 60 BiDi ~ 0 +Text HLabel 4950 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR04 +L GND #PWR018 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR04" H 3000 5200 30 0001 C CNN +F 0 "#PWR018" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -557,11 +1010,11 @@ Entry Wire Line 6750 4250 6650 4350 Entry Wire Line 9950 4650 10050 4750 -Text Label 6798 4800 0 60 ~ 0 +Text Label 6798 4650 0 60 ~ 0 M1_DQ4 -Text Label 6798 4900 0 60 ~ 0 +Text Label 6798 4550 0 60 ~ 0 M1_DQ3 -Text Label 6798 5000 0 60 ~ 0 +Text Label 6798 4450 0 60 ~ 0 M1_DQ2 Text Label 6848 4350 0 60 ~ 0 M1_DQ1 @@ -686,14 +1139,14 @@ Entry Wire Line Entry Wire Line 9950 3650 10050 3750 $Comp -L GND #PWR05 +L GND #PWR019 U 1 1 4C437C3F P 8250 5200 -F 0 "#PWR05" H 8250 5200 30 0001 C CNN +F 0 "#PWR019" H 8250 5200 30 0001 C CNN F 1 "GND" H 8250 5130 30 0001 C CNN 1 8250 5200 1 0 0 -1 $EndComp -Text HLabel 10200 5700 2 60 BiDi ~ 0 +Text HLabel 10200 5400 2 60 BiDi ~ 0 M1_DQ[0..15] $EndSCHEMATC diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index e7618a7..88c24e8 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT +EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -40,6 +40,7 @@ LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves +LIBS:pasives-connectors LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END @@ -54,21 +55,16 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Text HLabel 12400 5450 0 60 Output ~ 0 -M1_CS# -$Comp -L GND #PWR? -U 1 1 4C60C24F -P 12550 5700 -F 0 "#PWR?" H 12550 5700 30 0001 C CNN -F 1 "GND" H 12550 5630 30 0001 C CNN - 1 12550 5700 - -1 0 0 -1 -$EndComp +Wire Bus Line + 13300 4350 13400 4350 +Wire Bus Line + 13400 4350 13400 4450 Wire Wire Line - 12550 5450 12550 5700 + 13500 4550 13900 4550 Wire Wire Line - 12400 5450 12550 5450 + 12550 5700 12550 5450 +Wire Wire Line + 12550 5450 12400 5450 Wire Wire Line 1450 5700 1600 5700 Wire Wire Line @@ -104,39 +100,39 @@ Wire Bus Line Wire Wire Line 18300 4950 18750 4950 Wire Wire Line - 12500 4700 12050 4700 + 12150 4700 11700 4700 Wire Wire Line - 12500 4900 12050 4900 + 12150 4900 11700 4900 Wire Wire Line - 12500 5000 12050 5000 + 12150 5000 11700 5000 Wire Wire Line - 12500 4800 12050 4800 + 12150 4800 11700 4800 Wire Wire Line - 12500 4400 12050 4400 + 12150 4400 11700 4400 Wire Wire Line - 12500 4600 12050 4600 + 12150 4600 11700 4600 Wire Wire Line - 12500 4500 12050 4500 + 12150 4500 11700 4500 Wire Wire Line - 12500 4300 12050 4300 + 12150 4300 11700 4300 Wire Wire Line - 12500 3700 12050 3700 + 12150 3700 11700 3700 Wire Wire Line - 12500 3500 12050 3500 + 12150 3500 11700 3500 Wire Wire Line - 12500 3600 12050 3600 + 12150 3600 11700 3600 Wire Wire Line - 12500 3800 12050 3800 + 12150 3800 11700 3800 Wire Wire Line - 12500 4000 12050 4000 + 12150 4000 11700 4000 Wire Wire Line - 12500 4200 12050 4200 + 12150 4200 11700 4200 Wire Wire Line - 12500 3900 12050 3900 + 12150 3900 11700 3900 Wire Wire Line - 12500 4100 12050 4100 + 12150 4100 11700 4100 Wire Bus Line - 12500 3250 12600 3250 + 12150 3250 12250 3250 Wire Wire Line 13500 3450 13900 3450 Wire Wire Line @@ -166,31 +162,31 @@ Wire Wire Line Wire Wire Line 3200 3500 2750 3500 Wire Wire Line - 12700 2250 12300 2250 + 12200 2250 11800 2250 Wire Wire Line - 12700 2350 12300 2350 + 12200 2350 11800 2350 Wire Wire Line - 12700 2550 12300 2550 + 12200 2550 11800 2550 Wire Wire Line - 12700 2750 12300 2750 + 12200 2750 11800 2750 Wire Wire Line - 12700 1650 12300 1650 + 12200 1650 11800 1650 Wire Wire Line - 12700 1750 12300 1750 + 12200 1750 11800 1750 Wire Wire Line - 12700 2050 12300 2050 + 12200 2050 11800 2050 Wire Wire Line - 12700 1950 12300 1950 + 12200 1950 11800 1950 Wire Wire Line - 12700 2450 12300 2450 + 12200 2450 11800 2450 Wire Wire Line - 12700 1850 12300 1850 + 12200 1850 11800 1850 Wire Wire Line - 12700 2150 12300 2150 + 12200 2150 11800 2150 Wire Wire Line - 12700 2650 12300 2650 + 12200 2650 11800 2650 Wire Wire Line - 12700 2850 12300 2850 + 12200 2850 11800 2850 Wire Wire Line 13900 4950 13550 4950 Connection ~ 5750 6900 @@ -625,9 +621,9 @@ Wire Wire Line Wire Wire Line 13900 4850 13550 4850 Wire Bus Line - 12200 2750 12200 1500 + 11700 2750 11700 1500 Wire Bus Line - 12200 1500 11800 1500 + 11700 1500 11300 1500 Wire Bus Line 1050 1300 1450 1300 Wire Bus Line @@ -765,7 +761,7 @@ Wire Wire Line Wire Wire Line 18300 5250 18750 5250 Wire Bus Line - 12600 3250 12600 4900 + 12250 3250 12250 4900 Wire Wire Line 18750 4450 18300 4450 Wire Wire Line @@ -824,11 +820,44 @@ Wire Wire Line 14150 10750 14200 10750 Wire Wire Line 1600 5700 1600 5950 +Wire Bus Line + 8050 4200 7900 4200 +Wire Bus Line + 7900 4200 7900 4300 +Wire Wire Line + 13900 4450 13500 4450 +Entry Wire Line + 13400 4450 13500 4550 +Entry Wire Line + 13400 4350 13500 4450 +Text Label 13850 4550 2 60 ~ 0 +M1_BA1 +Text Label 13850 4450 2 60 ~ 0 +M1_BA0 +Text HLabel 13300 4350 0 60 Output ~ 0 +M1_BA[0..1] +Entry Wire Line + 7800 4400 7900 4300 +Entry Wire Line + 7800 4300 7900 4200 +Text HLabel 8050 4200 2 60 Output ~ 0 +M0_BA[0..1] +Text HLabel 12400 5450 0 60 Output ~ 0 +M1_CS# $Comp -L GND #PWR? +L GND #PWR01 +U 1 1 4C60C24F +P 12550 5700 +F 0 "#PWR01" H 12550 5700 30 0001 C CNN +F 1 "GND" H 12550 5630 30 0001 C CNN + 1 12550 5700 + -1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 U 1 1 4C60C21D P 1600 5950 -F 0 "#PWR?" H 1600 5950 30 0001 C CNN +F 0 "#PWR02" H 1600 5950 30 0001 C CNN F 1 "GND" H 1600 5880 30 0001 C CNN 1 1600 5950 -1 0 0 -1 @@ -932,70 +961,70 @@ M1_DQ11 Text Label 18350 4450 0 60 ~ 0 M1_DQ10 Entry Wire Line - 12500 5000 12600 4900 + 12150 5000 12250 4900 Entry Wire Line - 12500 4900 12600 4800 + 12150 4900 12250 4800 Entry Wire Line - 12500 4800 12600 4700 + 12150 4800 12250 4700 Entry Wire Line - 12500 4700 12600 4600 + 12150 4700 12250 4600 Entry Wire Line - 12500 4600 12600 4500 + 12150 4600 12250 4500 Entry Wire Line - 12500 4500 12600 4400 + 12150 4500 12250 4400 Entry Wire Line - 12500 4400 12600 4300 + 12150 4400 12250 4300 Entry Wire Line - 12500 4300 12600 4200 + 12150 4300 12250 4200 Entry Wire Line - 12500 4200 12600 4100 + 12150 4200 12250 4100 Entry Wire Line - 12500 4100 12600 4000 + 12150 4100 12250 4000 Entry Wire Line - 12500 4000 12600 3900 + 12150 4000 12250 3900 Entry Wire Line - 12500 3900 12600 3800 + 12150 3900 12250 3800 Entry Wire Line - 12500 3800 12600 3700 + 12150 3800 12250 3700 Entry Wire Line - 12500 3700 12600 3600 + 12150 3700 12250 3600 Entry Wire Line - 12500 3600 12600 3500 + 12150 3600 12250 3500 Entry Wire Line - 12500 3500 12600 3400 -Text Label 12050 4100 0 60 ~ 0 + 12150 3500 12250 3400 +Text Label 11700 4100 0 60 ~ 0 M1_DQ6 -Text Label 12050 4200 0 60 ~ 0 +Text Label 11700 4200 0 60 ~ 0 M1_DQ7 -Text Label 12050 4000 0 60 ~ 0 +Text Label 11700 4000 0 60 ~ 0 M1_DQ5 -Text Label 12050 3900 0 60 ~ 0 +Text Label 11700 3900 0 60 ~ 0 M1_DQ4 -Text Label 12050 3700 0 60 ~ 0 +Text Label 11700 3700 0 60 ~ 0 M1_DQ2 -Text Label 12050 3800 0 60 ~ 0 +Text Label 11700 3800 0 60 ~ 0 M1_DQ3 -Text Label 12050 3600 0 60 ~ 0 +Text Label 11700 3600 0 60 ~ 0 M1_DQ1 -Text Label 12050 3500 0 60 ~ 0 +Text Label 11700 3500 0 60 ~ 0 M1_DQ0 -Text Label 12050 4500 0 60 ~ 0 +Text Label 11700 4500 0 60 ~ 0 M1_DQ10 -Text Label 12050 4600 0 60 ~ 0 +Text Label 11700 4600 0 60 ~ 0 M1_DQ11 -Text Label 12050 4400 0 60 ~ 0 +Text Label 11700 4400 0 60 ~ 0 M1_DQ9 -Text Label 12050 4300 0 60 ~ 0 +Text Label 11700 4300 0 60 ~ 0 M1_DQ8 -Text Label 12050 4700 0 60 ~ 0 +Text Label 11700 4700 0 60 ~ 0 M1_DQ12 -Text Label 12050 4800 0 60 ~ 0 +Text Label 11700 4800 0 60 ~ 0 M1_DQ13 -Text Label 12050 5000 0 60 ~ 0 +Text Label 11700 5000 0 60 ~ 0 M1_DQ15 -Text Label 12050 4900 0 60 ~ 0 +Text Label 11700 4900 0 60 ~ 0 M1_DQ14 -Text HLabel 12500 3250 0 60 BiDi ~ 0 +Text HLabel 12150 3250 0 60 BiDi ~ 0 M1_DQ[0..15] Text HLabel 1450 5700 0 60 Output ~ 0 M0_CS# @@ -1198,31 +1227,31 @@ Entry Wire Line Entry Wire Line 1450 1350 1550 1450 Entry Wire Line - 12200 1550 12300 1650 + 11700 1550 11800 1650 Entry Wire Line - 12200 1650 12300 1750 + 11700 1650 11800 1750 Entry Wire Line - 12200 1750 12300 1850 + 11700 1750 11800 1850 Entry Wire Line - 12200 1850 12300 1950 + 11700 1850 11800 1950 Entry Wire Line - 12200 1950 12300 2050 + 11700 1950 11800 2050 Entry Wire Line - 12200 2050 12300 2150 + 11700 2050 11800 2150 Entry Wire Line - 12200 2150 12300 2250 + 11700 2150 11800 2250 Entry Wire Line - 12200 2250 12300 2350 + 11700 2250 11800 2350 Entry Wire Line - 12200 2350 12300 2450 + 11700 2350 11800 2450 Entry Wire Line - 12200 2450 12300 2550 + 11700 2450 11800 2550 Entry Wire Line - 12200 2550 12300 2650 + 11700 2550 11800 2650 Entry Wire Line - 12200 2650 12300 2750 + 11700 2650 11800 2750 Entry Wire Line - 12200 2750 12300 2850 + 11700 2750 11800 2850 Text HLabel 13550 5550 0 60 Output ~ 0 M1_CAS# Text HLabel 13500 3450 0 60 Output ~ 0 @@ -1239,31 +1268,31 @@ Text HLabel 18750 5750 2 60 Output ~ 0 M1_LDM Text HLabel 18750 4250 2 60 Output ~ 0 M1_UDQS -Text Label 12400 2350 0 60 ~ 0 +Text Label 11900 2350 0 60 ~ 0 M1_A5 -Text Label 12400 2250 0 60 ~ 0 +Text Label 11900 2250 0 60 ~ 0 M1_A6 -Text Label 12400 2550 0 60 ~ 0 +Text Label 11900 2550 0 60 ~ 0 M1_A3 -Text Label 12400 2750 0 60 ~ 0 +Text Label 11900 2750 0 60 ~ 0 M1_A1 -Text Label 12400 2850 0 60 ~ 0 +Text Label 11900 2850 0 60 ~ 0 M1_A0 -Text Label 12400 2650 0 60 ~ 0 +Text Label 11900 2650 0 60 ~ 0 M1_A2 -Text Label 12400 2150 0 60 ~ 0 +Text Label 11900 2150 0 60 ~ 0 M1_A7 -Text Label 12400 1850 0 60 ~ 0 +Text Label 11900 1850 0 60 ~ 0 M1_A10 -Text Label 12400 2450 0 60 ~ 0 +Text Label 11900 2450 0 60 ~ 0 M1_A4 -Text Label 12400 1950 0 60 ~ 0 +Text Label 11900 1950 0 60 ~ 0 M1_A9 -Text Label 12400 2050 0 60 ~ 0 +Text Label 11900 2050 0 60 ~ 0 M1_A8 -Text Label 12400 1750 0 60 ~ 0 +Text Label 11900 1750 0 60 ~ 0 M1_A11 -Text Label 12400 1650 0 60 ~ 0 +Text Label 11900 1650 0 60 ~ 0 M1_A12 Text Label 13500 5350 0 60 ~ 0 M1_A6 @@ -1291,7 +1320,7 @@ Text Label 13500 4750 0 60 ~ 0 M1_A1 Text Label 13500 4650 0 60 ~ 0 M1_A0 -Text HLabel 11800 1500 0 60 Output ~ 0 +Text HLabel 11300 1500 0 60 Output ~ 0 M1_A[0..12] Text HLabel 14150 8950 0 60 BiDi ~ 0 ETH_INT @@ -1304,10 +1333,10 @@ M0_CLK Text HLabel 7750 4700 2 60 Output ~ 0 M0_CLK# $Comp -L GND #PWR01 +L GND #PWR03 U 1 1 4C439B7E P 13950 15700 -F 0 "#PWR01" H 13950 15700 30 0001 C CNN +F 0 "#PWR03" H 13950 15700 30 0001 C CNN F 1 "GND" H 13950 15630 30 0001 C CNN 1 13950 15700 -1 0 0 -1 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 418303d..421e381 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT +EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -40,6 +40,7 @@ LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves +LIBS:pasives-connectors LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END @@ -172,19 +173,19 @@ Wire Wire Line 4400 5750 4400 5950 Connection ~ 4400 5850 $Comp -L GND #PWR02 +L GND #PWR04 U 1 1 4C438ADC P 4400 5950 -F 0 "#PWR02" H 4400 5950 30 0001 C CNN +F 0 "#PWR04" H 4400 5950 30 0001 C CNN F 1 "GND" H 4400 5880 30 0001 C CNN 1 4400 5950 1 0 0 -1 $EndComp $Comp -L GND #PWR03 +L GND #PWR05 U 1 1 4C438AD5 P 3950 6300 -F 0 "#PWR03" H 3950 6300 30 0001 C CNN +F 0 "#PWR05" H 3950 6300 30 0001 C CNN F 1 "GND" H 3950 6230 30 0001 C CNN 1 3950 6300 1 0 0 -1 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 67b040e..008fc83 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT +EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -40,6 +40,7 @@ LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves +LIBS:pasives-connectors LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 003222f..6e33358 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT +EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -40,6 +40,7 @@ LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves +LIBS:pasives-connectors LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END diff --git a/kicad/xue-rnc/xue-rnc-cache.dcm b/kicad/xue-rnc/xue-rnc-cache.dcm new file mode 100644 index 0000000..da67cae --- /dev/null +++ b/kicad/xue-rnc/xue-rnc-cache.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 Date: Tue 10 Aug 2010 04:56:38 PM COT +# +#End Doc Library diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 07d3966..c25dd91 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,17 @@ -EESchema-LIBRARY Version 2.3 Date: Mon 09 Aug 2010 10:11:04 PM COT +EESchema-LIBRARY Version 2.3 Date: Tue 10 Aug 2010 05:37:13 PM COT +# +# +2.5V +# +DEF +2.5V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -50 20 H I C CNN +F1 "+2.5V" 0 100 30 H V C CNN +ALIAS +2,5V +DRAW +X +2.5V 1 0 0 0 U 20 30 0 0 W N +C 0 60 20 0 1 0 N +P 3 0 1 0 0 0 0 40 0 40 N +ENDDRAW +ENDDEF # # C # @@ -18,6 +31,25 @@ X ~ 2 0 -200 170 U 40 40 1 1 P ENDDRAW ENDDEF # +# Cap +# +DEF Cap C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "Cap" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +S -50 -25 -50 -25 0 1 0 N +S -50 -25 50 -25 0 1 20 N +S -50 25 50 25 0 1 20 N +X ~ 1 0 100 65 D 40 40 1 1 P +X ~ 2 0 -100 65 U 40 40 1 1 P +ENDDRAW +ENDDEF +# # GND # DEF ~GND #PWR 0 0 Y Y 1 F P diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 198e8cc..2579dbb 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,20 +1,20 @@ -PCBNEW-BOARD Version 1 date Mon 09 Aug 2010 10:24:02 PM COT +PCBNEW-BOARD Version 1 date Tue 10 Aug 2010 05:36:58 PM COT -# Created by Pcbnew(2010-07-15 BZR 2414)-unstable +# Created by Pcbnew(2010-07-27 BZR 2423)-unstable $GENERAL LayerCount 4 Ly 1FFF8007 EnabledLayers 1FFF8007 -Links 337 -NoConn 337 -Di 25909 11079 66209 48965 +Links 405 +NoConn 405 +Di 25909 11079 68175 48965 Ndraw 0 Ntrack 0 Nzone 0 BoardThickness 630 -Nmodule 41 -Nnets 109 +Nmodule 63 +Nnets 136 $EndGENERAL $SHEETDESCR @@ -68,435 +68,543 @@ Na 0 "" St ~ $EndEQUIPOT $EQUIPOT -Na 1 "/DDR_Banks/M0_A1" +Na 1 "+2.5V" St ~ $EndEQUIPOT $EQUIPOT -Na 2 "/DDR_Banks/M0_A10" +Na 2 "/DDR_Banks/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 3 "/DDR_Banks/M0_A12" +Na 3 "/DDR_Banks/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 4 "/DDR_Banks/M0_A6" +Na 4 "/DDR_Banks/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/DDR_Banks/M0_A7" +Na 5 "/DDR_Banks/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_CAS#" +Na 6 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_CLK#" +Na 7 "/DDR_Banks/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_DQ10" +Na 8 "/DDR_Banks/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_DQ3" +Na 9 "/DDR_Banks/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_DQ8" +Na 10 "/DDR_Banks/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_LDM" +Na 11 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_LDQS" +Na 12 "/DDR_Banks/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_RAS#" +Na 13 "/DDR_Banks/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_UDQS" +Na 14 "/DDR_Banks/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M1_A12" +Na 15 "/DDR_Banks/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M1_A3" +Na 16 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M1_A5" +Na 17 "/DDR_Banks/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M1_A6" +Na 18 "/DDR_Banks/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M1_A7" +Na 19 "/DDR_Banks/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M1_DQ10" +Na 20 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M1_DQ11" +Na 21 "/DDR_Banks/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M1_DQ14" +Na 22 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_DQ15" +Na 23 "/DDR_Banks/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_DQ5" +Na 24 "/DDR_Banks/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_DQ8" +Na 25 "/DDR_Banks/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_LDQS" +Na 26 "/DDR_Banks/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_UDM" +Na 27 "/DDR_Banks/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_WE#" +Na 28 "/DDR_Banks/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/ETH_MDIO" +Na 29 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/Ethernet_Phy/ETH_1.8V" +Na 30 "/DDR_Banks/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/Ethernet_Phy/ETH_A1.8V" +Na 31 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/Ethernet_Phy/ETH_A3.3V" +Na 32 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/Ethernet_Phy/ETH_INT" +Na 33 "/DDR_Banks/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/Ethernet_Phy/ETH_LED0" +Na 34 "/DDR_Banks/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/Ethernet_Phy/ETH_LED1" +Na 35 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/Ethernet_Phy/ETH_PLL1.8V" +Na 36 "/DDR_Banks/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/FPGA_Spartan6/M0_A0" +Na 37 "/DDR_Banks/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/FPGA_Spartan6/M0_A11" +Na 38 "/DDR_Banks/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/FPGA_Spartan6/M0_A2" +Na 39 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/FPGA_Spartan6/M0_A3" +Na 40 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/FPGA_Spartan6/M0_A4" +Na 41 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/FPGA_Spartan6/M0_A5" +Na 42 "/DDR_Banks/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/FPGA_Spartan6/M0_A8" +Na 43 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/FPGA_Spartan6/M0_A9" +Na 44 "/Ethernet_Phy/ETH_1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/FPGA_Spartan6/M0_CKE" +Na 45 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/FPGA_Spartan6/M0_CLK" +Na 46 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/FPGA_Spartan6/M0_DQ0" +Na 47 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/FPGA_Spartan6/M0_DQ1" +Na 48 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/FPGA_Spartan6/M0_DQ11" +Na 49 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/FPGA_Spartan6/M0_DQ12" +Na 50 "/Ethernet_Phy/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/FPGA_Spartan6/M0_DQ13" +Na 51 "/Ethernet_Phy/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Spartan6/M0_DQ14" +Na 52 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Spartan6/M0_DQ15" +Na 53 "/Ethernet_Phy/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Spartan6/M0_DQ2" +Na 54 "/Ethernet_Phy/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Spartan6/M0_DQ4" +Na 55 "/Ethernet_Phy/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/M0_DQ5" +Na 56 "/Ethernet_Phy/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/M0_DQ6" +Na 57 "/Ethernet_Phy/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/M0_DQ7" +Na 58 "/FPGA_Spartan6/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/M0_DQ9" +Na 59 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/M0_UDM" +Na 60 "/FPGA_Spartan6/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/M0_WE#" +Na 61 "/FPGA_Spartan6/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/M1_A0" +Na 62 "/FPGA_Spartan6/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/M1_A1" +Na 63 "/FPGA_Spartan6/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/M1_A10" +Na 64 "/FPGA_Spartan6/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/M1_A11" +Na 65 "/FPGA_Spartan6/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/M1_A2" +Na 66 "/FPGA_Spartan6/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/M1_A4" +Na 67 "/FPGA_Spartan6/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/M1_A8" +Na 68 "/FPGA_Spartan6/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M1_A9" +Na 69 "/FPGA_Spartan6/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M1_CAS#" +Na 70 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M1_CKE" +Na 71 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M1_CLK" +Na 72 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M1_CLK#" +Na 73 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M1_DQ0" +Na 74 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M1_DQ1" +Na 75 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M1_DQ12" +Na 76 "/FPGA_Spartan6/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M1_DQ13" +Na 77 "/FPGA_Spartan6/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M1_DQ6" +Na 78 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M1_DQ7" +Na 79 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M1_DQ9" +Na 80 "/FPGA_Spartan6/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M1_LDM" +Na 81 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M1_RAS#" +Na 82 "/FPGA_Spartan6/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M1_UDQS" +Na 83 "/FPGA_Spartan6/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/Non_volatile_memories/FRB_N" +Na 84 "/FPGA_Spartan6/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "3.3V" +Na 85 "/FPGA_Spartan6/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "GND" +Na 86 "/FPGA_Spartan6/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "N-000047" +Na 87 "/FPGA_Spartan6/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "N-000054" +Na 88 "/FPGA_Spartan6/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "N-000137" +Na 89 "/FPGA_Spartan6/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "N-000153" +Na 90 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "N-000154" +Na 91 "/FPGA_Spartan6/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "N-000155" +Na 92 "/FPGA_Spartan6/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "N-000156" +Na 93 "/FPGA_Spartan6/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "N-000157" +Na 94 "/FPGA_Spartan6/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "N-000396" +Na 95 "/FPGA_Spartan6/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "N-000398" +Na 96 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "N-000399" +Na 97 "/FPGA_Spartan6/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "N-000400" +Na 98 "/FPGA_Spartan6/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "N-000405" +Na 99 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "N-000406" +Na 100 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "N-000407" +Na 101 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "N-000408" +Na 102 "/FPGA_Spartan6/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "N-000416" +Na 103 "/FPGA_Spartan6/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "N-000417" +Na 104 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "N-000419" +Na 105 "/FPGA_Spartan6/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "N-000420" +Na 106 "/FPGA_Spartan6/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "N-000425" +Na 107 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "N-000426" +Na 108 "/FPGA_Spartan6/M1_RAS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 109 "/Non_volatile_memories/FRB_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 110 "3.3V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 111 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 112 "N-000040" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 113 "N-000041" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 114 "N-000042" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 115 "N-000044" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 116 "N-000119" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 117 "N-000120" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 118 "N-000121" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 119 "N-000122" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 120 "N-000123" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 121 "N-000124" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 122 "N-000375" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 123 "N-000376" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 124 "N-000378" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 125 "N-000379" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 126 "N-000380" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 127 "N-000381" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 128 "N-000383" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 129 "N-000385" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 130 "N-000386" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 131 "N-000387" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 132 "N-000388" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 133 "N-000389" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 134 "N-000394" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 135 "N-000395" St ~ $EndEQUIPOT $NCLASS @@ -509,114 +617,141 @@ ViaDrill 250 uViaDia 200 uViaDrill 50 AddNet "" -AddNet "/DDR_Banks/M0_A1" -AddNet "/DDR_Banks/M0_A10" -AddNet "/DDR_Banks/M0_A12" +AddNet "+2.5V" +AddNet "/DDR_Banks/M0_A2" +AddNet "/DDR_Banks/M0_A3" +AddNet "/DDR_Banks/M0_A5" AddNet "/DDR_Banks/M0_A6" AddNet "/DDR_Banks/M0_A7" +AddNet "/DDR_Banks/M0_A9" AddNet "/DDR_Banks/M0_CAS#" +AddNet "/DDR_Banks/M0_CKE" +AddNet "/DDR_Banks/M0_CLK" AddNet "/DDR_Banks/M0_CLK#" -AddNet "/DDR_Banks/M0_DQ10" +AddNet "/DDR_Banks/M0_DQ13" +AddNet "/DDR_Banks/M0_DQ15" +AddNet "/DDR_Banks/M0_DQ2" AddNet "/DDR_Banks/M0_DQ3" +AddNet "/DDR_Banks/M0_DQ4" +AddNet "/DDR_Banks/M0_DQ7" AddNet "/DDR_Banks/M0_DQ8" -AddNet "/DDR_Banks/M0_LDM" +AddNet "/DDR_Banks/M0_DQ9" AddNet "/DDR_Banks/M0_LDQS" -AddNet "/DDR_Banks/M0_RAS#" AddNet "/DDR_Banks/M0_UDQS" -AddNet "/DDR_Banks/M1_A12" +AddNet "/DDR_Banks/M0_WE#" +AddNet "/DDR_Banks/M1_A10" +AddNet "/DDR_Banks/M1_A11" +AddNet "/DDR_Banks/M1_A2" AddNet "/DDR_Banks/M1_A3" -AddNet "/DDR_Banks/M1_A5" -AddNet "/DDR_Banks/M1_A6" +AddNet "/DDR_Banks/M1_A4" AddNet "/DDR_Banks/M1_A7" +AddNet "/DDR_Banks/M1_A8" +AddNet "/DDR_Banks/M1_A9" +AddNet "/DDR_Banks/M1_CLK" +AddNet "/DDR_Banks/M1_CLK#" +AddNet "/DDR_Banks/M1_DQ0" +AddNet "/DDR_Banks/M1_DQ1" AddNet "/DDR_Banks/M1_DQ10" AddNet "/DDR_Banks/M1_DQ11" -AddNet "/DDR_Banks/M1_DQ14" -AddNet "/DDR_Banks/M1_DQ15" -AddNet "/DDR_Banks/M1_DQ5" -AddNet "/DDR_Banks/M1_DQ8" +AddNet "/DDR_Banks/M1_DQ2" +AddNet "/DDR_Banks/M1_DQ4" +AddNet "/DDR_Banks/M1_LDM" AddNet "/DDR_Banks/M1_LDQS" AddNet "/DDR_Banks/M1_UDM" +AddNet "/DDR_Banks/M1_UDQS" AddNet "/DDR_Banks/M1_WE#" -AddNet "/ETH_MDIO" AddNet "/Ethernet_Phy/ETH_1.8V" AddNet "/Ethernet_Phy/ETH_A1.8V" AddNet "/Ethernet_Phy/ETH_A3.3V" AddNet "/Ethernet_Phy/ETH_INT" AddNet "/Ethernet_Phy/ETH_LED0" AddNet "/Ethernet_Phy/ETH_LED1" +AddNet "/Ethernet_Phy/ETH_MDC" +AddNet "/Ethernet_Phy/ETH_MDIO" AddNet "/Ethernet_Phy/ETH_PLL1.8V" +AddNet "/Ethernet_Phy/ETH_RXC" +AddNet "/Ethernet_Phy/ETH_RXDV" +AddNet "/Ethernet_Phy/ETH_RXER" +AddNet "/Ethernet_Phy/ETH_TXD1" +AddNet "/Ethernet_Phy/ETH_TXEN" +AddNet "/FPGA_Spartan6/ETH_CLK" +AddNet "/FPGA_Spartan6/ETH_RESET_N" +AddNet "/FPGA_Spartan6/ETH_RXD0" +AddNet "/FPGA_Spartan6/ETH_RXD1" +AddNet "/FPGA_Spartan6/ETH_RXD2" +AddNet "/FPGA_Spartan6/ETH_RXD3" +AddNet "/FPGA_Spartan6/ETH_TXC" +AddNet "/FPGA_Spartan6/ETH_TXD0" +AddNet "/FPGA_Spartan6/ETH_TXD2" +AddNet "/FPGA_Spartan6/ETH_TXD3" +AddNet "/FPGA_Spartan6/ETH_TXER" AddNet "/FPGA_Spartan6/M0_A0" +AddNet "/FPGA_Spartan6/M0_A1" +AddNet "/FPGA_Spartan6/M0_A10" AddNet "/FPGA_Spartan6/M0_A11" -AddNet "/FPGA_Spartan6/M0_A2" -AddNet "/FPGA_Spartan6/M0_A3" +AddNet "/FPGA_Spartan6/M0_A12" AddNet "/FPGA_Spartan6/M0_A4" -AddNet "/FPGA_Spartan6/M0_A5" AddNet "/FPGA_Spartan6/M0_A8" -AddNet "/FPGA_Spartan6/M0_A9" -AddNet "/FPGA_Spartan6/M0_CKE" -AddNet "/FPGA_Spartan6/M0_CLK" +AddNet "/FPGA_Spartan6/M0_BA0" +AddNet "/FPGA_Spartan6/M0_BA1" AddNet "/FPGA_Spartan6/M0_DQ0" AddNet "/FPGA_Spartan6/M0_DQ1" +AddNet "/FPGA_Spartan6/M0_DQ10" AddNet "/FPGA_Spartan6/M0_DQ11" AddNet "/FPGA_Spartan6/M0_DQ12" -AddNet "/FPGA_Spartan6/M0_DQ13" AddNet "/FPGA_Spartan6/M0_DQ14" -AddNet "/FPGA_Spartan6/M0_DQ15" -AddNet "/FPGA_Spartan6/M0_DQ2" -AddNet "/FPGA_Spartan6/M0_DQ4" AddNet "/FPGA_Spartan6/M0_DQ5" AddNet "/FPGA_Spartan6/M0_DQ6" -AddNet "/FPGA_Spartan6/M0_DQ7" -AddNet "/FPGA_Spartan6/M0_DQ9" +AddNet "/FPGA_Spartan6/M0_LDM" +AddNet "/FPGA_Spartan6/M0_RAS#" AddNet "/FPGA_Spartan6/M0_UDM" -AddNet "/FPGA_Spartan6/M0_WE#" AddNet "/FPGA_Spartan6/M1_A0" AddNet "/FPGA_Spartan6/M1_A1" -AddNet "/FPGA_Spartan6/M1_A10" -AddNet "/FPGA_Spartan6/M1_A11" -AddNet "/FPGA_Spartan6/M1_A2" -AddNet "/FPGA_Spartan6/M1_A4" -AddNet "/FPGA_Spartan6/M1_A8" -AddNet "/FPGA_Spartan6/M1_A9" +AddNet "/FPGA_Spartan6/M1_A12" +AddNet "/FPGA_Spartan6/M1_A5" +AddNet "/FPGA_Spartan6/M1_A6" +AddNet "/FPGA_Spartan6/M1_BA0" +AddNet "/FPGA_Spartan6/M1_BA1" AddNet "/FPGA_Spartan6/M1_CAS#" AddNet "/FPGA_Spartan6/M1_CKE" -AddNet "/FPGA_Spartan6/M1_CLK" -AddNet "/FPGA_Spartan6/M1_CLK#" -AddNet "/FPGA_Spartan6/M1_DQ0" -AddNet "/FPGA_Spartan6/M1_DQ1" AddNet "/FPGA_Spartan6/M1_DQ12" AddNet "/FPGA_Spartan6/M1_DQ13" +AddNet "/FPGA_Spartan6/M1_DQ14" +AddNet "/FPGA_Spartan6/M1_DQ15" +AddNet "/FPGA_Spartan6/M1_DQ3" +AddNet "/FPGA_Spartan6/M1_DQ5" AddNet "/FPGA_Spartan6/M1_DQ6" AddNet "/FPGA_Spartan6/M1_DQ7" +AddNet "/FPGA_Spartan6/M1_DQ8" AddNet "/FPGA_Spartan6/M1_DQ9" -AddNet "/FPGA_Spartan6/M1_LDM" AddNet "/FPGA_Spartan6/M1_RAS#" -AddNet "/FPGA_Spartan6/M1_UDQS" AddNet "/Non_volatile_memories/FRB_N" AddNet "3.3V" AddNet "GND" -AddNet "N-000047" -AddNet "N-000054" -AddNet "N-000137" -AddNet "N-000153" -AddNet "N-000154" -AddNet "N-000155" -AddNet "N-000156" -AddNet "N-000157" -AddNet "N-000396" -AddNet "N-000398" -AddNet "N-000399" -AddNet "N-000400" -AddNet "N-000405" -AddNet "N-000406" -AddNet "N-000407" -AddNet "N-000408" -AddNet "N-000416" -AddNet "N-000417" -AddNet "N-000419" -AddNet "N-000420" -AddNet "N-000425" -AddNet "N-000426" +AddNet "N-000040" +AddNet "N-000041" +AddNet "N-000042" +AddNet "N-000044" +AddNet "N-000119" +AddNet "N-000120" +AddNet "N-000121" +AddNet "N-000122" +AddNet "N-000123" +AddNet "N-000124" +AddNet "N-000375" +AddNet "N-000376" +AddNet "N-000378" +AddNet "N-000379" +AddNet "N-000380" +AddNet "N-000381" +AddNet "N-000383" +AddNet "N-000385" +AddNet "N-000386" +AddNet "N-000387" +AddNet "N-000388" +AddNet "N-000389" +AddNet "N-000394" +AddNet "N-000395" $EndNCLASS $MODULE FGG484bga-p10 Po 56450 33930 0 15 4C4325AE 4C431E53 ~~ @@ -639,7 +774,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -4133 -4133 $EndPAD $PAD @@ -667,42 +802,42 @@ $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/Ethernet_Phy/ETH_INT" +Ne 47 "/Ethernet_Phy/ETH_INT" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 63 "/FPGA_Spartan6/ETH_RXD3" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 61 "/FPGA_Spartan6/ETH_RXD1" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 54 "/Ethernet_Phy/ETH_RXDV" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 65 "/FPGA_Spartan6/ETH_TXD0" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 58 "/FPGA_Spartan6/ETH_CLK" Po -590 -4133 $EndPAD $PAD @@ -786,7 +921,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 4133 -4133 $EndPAD $PAD @@ -814,56 +949,56 @@ $PAD Sh "B4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000137" +Ne 117 "N-000120" Po -2952 -3739 $EndPAD $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2558 -3739 $EndPAD $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 59 "/FPGA_Spartan6/ETH_RESET_N" Po -2165 -3739 $EndPAD $PAD Sh "B7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000137" +Ne 117 "N-000120" Po -1771 -3739 $EndPAD $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 60 "/FPGA_Spartan6/ETH_RXD0" Po -1377 -3739 $EndPAD $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -983 -3739 $EndPAD $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 53 "/Ethernet_Phy/ETH_RXC" Po -590 -3739 $EndPAD $PAD Sh "B11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000137" +Ne 117 "N-000120" Po -196 -3739 $EndPAD $PAD @@ -877,7 +1012,7 @@ $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 590 -3739 $EndPAD $PAD @@ -891,7 +1026,7 @@ $PAD Sh "B15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000137" +Ne 117 "N-000120" Po 1377 -3739 $EndPAD $PAD @@ -905,7 +1040,7 @@ $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 2165 -3739 $EndPAD $PAD @@ -919,7 +1054,7 @@ $PAD Sh "B19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000137" +Ne 117 "N-000120" Po 2952 -3739 $EndPAD $PAD @@ -947,14 +1082,14 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/FPGA_Spartan6/M0_A11" +Ne 72 "/FPGA_Spartan6/M0_A11" Po -4133 -3346 $EndPAD $PAD Sh "C2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -3739 -3346 $EndPAD $PAD @@ -982,35 +1117,35 @@ $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 51 "/Ethernet_Phy/ETH_MDIO" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 62 "/FPGA_Spartan6/ETH_RXD2" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 68 "/FPGA_Spartan6/ETH_TXER" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 57 "/Ethernet_Phy/ETH_TXEN" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 64 "/FPGA_Spartan6/ETH_TXC" Po -590 -3346 $EndPAD $PAD @@ -1080,35 +1215,35 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M1_A8" +Ne 29 "/DDR_Banks/M1_A8" Po 3346 -3346 $EndPAD $PAD Sh "C21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000155" +Ne 116 "N-000119" Po 3739 -3346 $EndPAD $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M1_A9" +Ne 30 "/DDR_Banks/M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/DDR_Banks/M0_A12" +Ne 73 "/FPGA_Spartan6/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/FPGA_Spartan6/M0_CKE" +Ne 9 "/DDR_Banks/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1122,7 +1257,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1136,35 +1271,35 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 50 "/Ethernet_Phy/ETH_MDC" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 56 "/Ethernet_Phy/ETH_TXD1" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 66 "/FPGA_Spartan6/ETH_TXD2" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 55 "/Ethernet_Phy/ETH_RXER" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 67 "/FPGA_Spartan6/ETH_TXD3" Po -590 -2952 $EndPAD $PAD @@ -1206,7 +1341,7 @@ $PAD Sh "D16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po 1771 -2952 $EndPAD $PAD @@ -1220,7 +1355,7 @@ $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 2558 -2952 $EndPAD $PAD @@ -1241,35 +1376,35 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M1_CKE" +Ne 97 "/FPGA_Spartan6/M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M1_A12" +Ne 91 "/FPGA_Spartan6/M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/FPGA_Spartan6/M0_A9" +Ne 7 "/DDR_Banks/M0_A9" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/FPGA_Spartan6/M0_A8" +Ne 75 "/FPGA_Spartan6/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1297,7 +1432,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -1771 -2558 $EndPAD $PAD @@ -1311,7 +1446,7 @@ $PAD Sh "E9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000137" +Ne 117 "N-000120" Po -983 -2558 $EndPAD $PAD @@ -1339,7 +1474,7 @@ $PAD Sh "E13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000137" +Ne 117 "N-000120" Po 590 -2558 $EndPAD $PAD @@ -1353,7 +1488,7 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 1377 -2558 $EndPAD $PAD @@ -1367,7 +1502,7 @@ $PAD Sh "E17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000137" +Ne 117 "N-000120" Po 2165 -2558 $EndPAD $PAD @@ -1381,28 +1516,28 @@ $PAD Sh "E19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000155" +Ne 116 "N-000119" Po 2952 -2558 $EndPAD $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M1_A7" +Ne 28 "/DDR_Banks/M1_A7" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M1_A2" +Ne 25 "/DDR_Banks/M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -1416,21 +1551,21 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/M0_WE#" +Ne 22 "/DDR_Banks/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/FPGA_Spartan6/M0_A4" +Ne 74 "/FPGA_Spartan6/M0_A4" Po -3346 -2165 $EndPAD $PAD Sh "F4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -2952 -2165 $EndPAD $PAD @@ -1444,7 +1579,7 @@ $PAD Sh "F6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -2165 -2165 $EndPAD $PAD @@ -1479,7 +1614,7 @@ $PAD Sh "F11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po -196 -2165 $EndPAD $PAD @@ -1535,63 +1670,63 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M1_A11" +Ne 24 "/DDR_Banks/M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M1_A4" +Ne 27 "/DDR_Banks/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/M1_A0" +Ne 89 "/FPGA_Spartan6/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M1_A1" +Ne 90 "/FPGA_Spartan6/M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 77 "/FPGA_Spartan6/M0_BA1" Po -4133 -1771 $EndPAD $PAD Sh "G2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -3739 -1771 $EndPAD $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 76 "/FPGA_Spartan6/M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/DDR_Banks/M0_A10" +Ne 71 "/FPGA_Spartan6/M0_A10" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2558 -1771 $EndPAD $PAD @@ -1626,7 +1761,7 @@ $PAD Sh "G10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000137" +Ne 117 "N-000120" Po -590 -1771 $EndPAD $PAD @@ -1640,7 +1775,7 @@ $PAD Sh "G12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po 196 -1771 $EndPAD $PAD @@ -1654,7 +1789,7 @@ $PAD Sh "G14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "N-000137" +Ne 117 "N-000120" Po 983 -1771 $EndPAD $PAD @@ -1682,28 +1817,28 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M1_A10" +Ne 23 "/DDR_Banks/M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M1_A3" +Ne 26 "/DDR_Banks/M1_A3" Po 3346 -1771 $EndPAD $PAD Sh "G21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000155" +Ne 116 "N-000119" Po 3739 -1771 $EndPAD $PAD @@ -1717,49 +1852,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "/DDR_Banks/M0_A1" +Ne 70 "/FPGA_Spartan6/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/FPGA_Spartan6/M0_A0" +Ne 69 "/FPGA_Spartan6/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_CLK#" +Ne 11 "/DDR_Banks/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/FPGA_Spartan6/M0_CLK" +Ne 10 "/DDR_Banks/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/FPGA_Spartan6/M0_A2" +Ne 2 "/DDR_Banks/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_A7" +Ne 6 "/DDR_Banks/M0_A7" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -1771 -1377 $EndPAD $PAD @@ -1773,7 +1908,7 @@ $PAD Sh "H9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po -983 -1377 $EndPAD $PAD @@ -1815,7 +1950,7 @@ $PAD Sh "H15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po 1377 -1377 $EndPAD $PAD @@ -1843,63 +1978,63 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_WE#" +Ne 43 "/DDR_Banks/M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M1_CLK" +Ne 31 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M1_RAS#" +Ne 108 "/FPGA_Spartan6/M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M1_CAS#" +Ne 96 "/FPGA_Spartan6/M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/M0_DQ5" +Ne 84 "/FPGA_Spartan6/M0_DQ5" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/M0_DQ4" +Ne 16 "/DDR_Banks/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/DDR_Banks/M0_A6" +Ne 5 "/DDR_Banks/M0_A6" Po -2952 -983 $EndPAD $PAD Sh "J5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -2558 -983 $EndPAD $PAD @@ -1920,56 +2055,56 @@ $PAD Sh "J8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po -1377 -983 $EndPAD $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -983 -983 $EndPAD $PAD Sh "J10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po -590 -983 $EndPAD $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -196 -983 $EndPAD $PAD Sh "J12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po 196 -983 $EndPAD $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 590 -983 $EndPAD $PAD Sh "J14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po 983 -983 $EndPAD $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 1377 -983 $EndPAD $PAD @@ -1983,84 +2118,84 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 94 "/FPGA_Spartan6/M1_BA0" Po 2165 -983 $EndPAD $PAD Sh "J18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000155" +Ne 116 "N-000119" Po 2558 -983 $EndPAD $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M1_CLK#" +Ne 32 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 38 "/DDR_Banks/M1_DQ4" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_DQ5" +Ne 103 "/FPGA_Spartan6/M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/M0_DQ7" +Ne 17 "/DDR_Banks/M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/M0_DQ6" +Ne 85 "/FPGA_Spartan6/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/FPGA_Spartan6/M0_A5" +Ne 4 "/DDR_Banks/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_CAS#" +Ne 8 "/DDR_Banks/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_RAS#" +Ne 87 "/FPGA_Spartan6/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/FPGA_Spartan6/M0_A3" +Ne 3 "/DDR_Banks/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2081,21 +2216,21 @@ $PAD Sh "K9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po -983 -590 $EndPAD $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -590 -590 $EndPAD $PAD Sh "K11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po -196 -590 $EndPAD $PAD @@ -2109,21 +2244,21 @@ $PAD Sh "K13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po 590 -590 $EndPAD $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 983 -590 $EndPAD $PAD Sh "K15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po 1377 -590 $EndPAD $PAD @@ -2137,7 +2272,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 95 "/FPGA_Spartan6/M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2151,28 +2286,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M1_A6" +Ne 93 "/FPGA_Spartan6/M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M1_A5" +Ne 92 "/FPGA_Spartan6/M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M1_DQ6" +Ne 104 "/FPGA_Spartan6/M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M1_DQ7" +Ne 105 "/FPGA_Spartan6/M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2186,28 +2321,28 @@ $PAD Sh "L2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -3739 -196 $EndPAD $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_LDQS" +Ne 20 "/DDR_Banks/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_LDM" +Ne 86 "/FPGA_Spartan6/M0_LDM" Po -2952 -196 $EndPAD $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2558 -196 $EndPAD $PAD @@ -2221,56 +2356,56 @@ $PAD Sh "L7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -1771 -196 $EndPAD $PAD Sh "L8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po -1377 -196 $EndPAD $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -983 -196 $EndPAD $PAD Sh "L10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po -590 -196 $EndPAD $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -196 -196 $EndPAD $PAD Sh "L12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po 196 -196 $EndPAD $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 590 -196 $EndPAD $PAD Sh "L14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po 983 -196 $EndPAD $PAD @@ -2284,7 +2419,7 @@ $PAD Sh "L16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000155" +Ne 116 "N-000119" Po 1771 -196 $EndPAD $PAD @@ -2298,28 +2433,28 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M1_LDM" +Ne 39 "/DDR_Banks/M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_LDQS" +Ne 40 "/DDR_Banks/M1_LDQS" Po 3346 -196 $EndPAD $PAD Sh "L21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000155" +Ne 116 "N-000119" Po 3739 -196 $EndPAD $PAD @@ -2333,21 +2468,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_DQ3" +Ne 15 "/DDR_Banks/M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/M0_DQ2" +Ne 14 "/DDR_Banks/M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/M0_UDM" +Ne 88 "/FPGA_Spartan6/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2389,49 +2524,49 @@ $PAD Sh "M9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po -983 196 $EndPAD $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -590 196 $EndPAD $PAD Sh "M11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po -196 196 $EndPAD $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 196 196 $EndPAD $PAD Sh "M13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po 590 196 $EndPAD $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 983 196 $EndPAD $PAD Sh "M15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po 1377 196 $EndPAD $PAD @@ -2466,42 +2601,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_UDM" +Ne 41 "/DDR_Banks/M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 37 "/DDR_Banks/M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 102 "/FPGA_Spartan6/M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/FPGA_Spartan6/M0_DQ1" +Ne 79 "/FPGA_Spartan6/M0_DQ1" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/FPGA_Spartan6/M0_DQ0" +Ne 78 "/FPGA_Spartan6/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -2515,7 +2650,7 @@ $PAD Sh "N5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -2558 590 $EndPAD $PAD @@ -2536,49 +2671,49 @@ $PAD Sh "N8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po -1377 590 $EndPAD $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -983 590 $EndPAD $PAD Sh "N10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po -590 590 $EndPAD $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -196 590 $EndPAD $PAD Sh "N12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po 196 590 $EndPAD $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 590 590 $EndPAD $PAD Sh "N14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po 983 590 $EndPAD $PAD @@ -2599,14 +2734,14 @@ $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 2165 590 $EndPAD $PAD Sh "N18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000155" +Ne 116 "N-000119" Po 2558 590 $EndPAD $PAD @@ -2620,35 +2755,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M1_DQ0" +Ne 33 "/DDR_Banks/M1_DQ0" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M1_DQ1" +Ne 34 "/DDR_Banks/M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/M0_DQ9" +Ne 19 "/DDR_Banks/M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_DQ8" +Ne 18 "/DDR_Banks/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -2697,42 +2832,42 @@ $PAD Sh "P9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po -983 983 $EndPAD $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -590 983 $EndPAD $PAD Sh "P11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po -196 983 $EndPAD $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 196 983 $EndPAD $PAD Sh "P13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po 590 983 $EndPAD $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 983 983 $EndPAD $PAD @@ -2781,35 +2916,35 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_DQ8" +Ne 106 "/FPGA_Spartan6/M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M1_DQ9" +Ne 107 "/FPGA_Spartan6/M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/FPGA_Spartan6/M0_DQ11" +Ne 81 "/FPGA_Spartan6/M0_DQ11" Po -4133 1377 $EndPAD $PAD Sh "R2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -3739 1377 $EndPAD $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_DQ10" +Ne 80 "/FPGA_Spartan6/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -2823,14 +2958,14 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2558 1377 $EndPAD $PAD Sh "R6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po -2165 1377 $EndPAD $PAD @@ -2858,7 +2993,7 @@ $PAD Sh "R10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po -590 1377 $EndPAD $PAD @@ -2872,7 +3007,7 @@ $PAD Sh "R12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po 196 1377 $EndPAD $PAD @@ -2886,7 +3021,7 @@ $PAD Sh "R14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "N-000156" +Ne 119 "N-000122" Po 983 1377 $EndPAD $PAD @@ -2914,7 +3049,7 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 2558 1377 $EndPAD $PAD @@ -2928,21 +3063,21 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_DQ10" +Ne 35 "/DDR_Banks/M1_DQ10" Po 3346 1377 $EndPAD $PAD Sh "R21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000155" +Ne 116 "N-000119" Po 3739 1377 $EndPAD $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_DQ11" +Ne 36 "/DDR_Banks/M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -2956,7 +3091,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_UDQS" +Ne 21 "/DDR_Banks/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3005,7 +3140,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po -983 1771 $EndPAD $PAD @@ -3033,7 +3168,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po 590 1771 $EndPAD $PAD @@ -3089,7 +3224,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M1_UDQS" +Ne 42 "/DDR_Banks/M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3103,21 +3238,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/M0_DQ13" +Ne 12 "/DDR_Banks/M0_DQ13" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Spartan6/M0_DQ12" +Ne 82 "/FPGA_Spartan6/M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3131,7 +3266,7 @@ $PAD Sh "U5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -2558 2165 $EndPAD $PAD @@ -3145,7 +3280,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -1771 2165 $EndPAD $PAD @@ -3173,7 +3308,7 @@ $PAD Sh "U11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po -196 2165 $EndPAD $PAD @@ -3222,7 +3357,7 @@ $PAD Sh "U18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000155" +Ne 116 "N-000119" Po 2558 2165 $EndPAD $PAD @@ -3236,35 +3371,35 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M1_DQ12" +Ne 98 "/FPGA_Spartan6/M1_DQ12" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M1_DQ13" +Ne 99 "/FPGA_Spartan6/M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/M0_DQ15" +Ne 13 "/DDR_Banks/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/M0_DQ14" +Ne 83 "/FPGA_Spartan6/M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3278,7 +3413,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2952 2558 $EndPAD $PAD @@ -3292,7 +3427,7 @@ $PAD Sh "V6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "N-000157" +Ne 120 "N-000123" Po -2165 2558 $EndPAD $PAD @@ -3306,7 +3441,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po -1377 2558 $EndPAD $PAD @@ -3320,7 +3455,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -590 2558 $EndPAD $PAD @@ -3334,7 +3469,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po 196 2558 $EndPAD $PAD @@ -3348,7 +3483,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 983 2558 $EndPAD $PAD @@ -3362,7 +3497,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po 1771 2558 $EndPAD $PAD @@ -3397,14 +3532,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_DQ14" +Ne 100 "/FPGA_Spartan6/M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_DQ15" +Ne 101 "/FPGA_Spartan6/M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -3418,7 +3553,7 @@ $PAD Sh "W2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "N-000153" +Ne 121 "N-000124" Po -3739 2952 $EndPAD $PAD @@ -3439,7 +3574,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po -2558 2952 $EndPAD $PAD @@ -3453,7 +3588,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -1771 2952 $EndPAD $PAD @@ -3516,7 +3651,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 1771 2952 $EndPAD $PAD @@ -3537,7 +3672,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 2952 2952 $EndPAD $PAD @@ -3551,7 +3686,7 @@ $PAD Sh "W21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "N-000155" +Ne 116 "N-000119" Po 3739 2952 $EndPAD $PAD @@ -3733,7 +3868,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po -3346 3739 $EndPAD $PAD @@ -3747,7 +3882,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2558 3739 $EndPAD $PAD @@ -3761,7 +3896,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po -1771 3739 $EndPAD $PAD @@ -3775,7 +3910,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -983 3739 $EndPAD $PAD @@ -3789,7 +3924,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po -196 3739 $EndPAD $PAD @@ -3803,7 +3938,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 590 3739 $EndPAD $PAD @@ -3817,7 +3952,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po 1377 3739 $EndPAD $PAD @@ -3831,7 +3966,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 2165 3739 $EndPAD $PAD @@ -3845,7 +3980,7 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "N-000154" +Ne 118 "N-000121" Po 2952 3739 $EndPAD $PAD @@ -3873,7 +4008,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -4133 4133 $EndPAD $PAD @@ -4020,7 +4155,7 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 @@ -4042,105 +4177,105 @@ $PAD Sh "12" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -1613 1082 $EndPAD $PAD Sh "11" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 55 "/Ethernet_Phy/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 53 "/Ethernet_Phy/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 54 "/Ethernet_Phy/ETH_RXDV" Po -1613 491 $EndPAD $PAD Sh "8" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -1613 295 $EndPAD $PAD Sh "7" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -1613 98 $EndPAD $PAD Sh "6" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 60 "/FPGA_Spartan6/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 61 "/FPGA_Spartan6/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 62 "/FPGA_Spartan6/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 63 "/FPGA_Spartan6/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 50 "/Ethernet_Phy/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/ETH_MDIO" +Ne 51 "/Ethernet_Phy/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 59 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 52 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 58 "/FPGA_Spartan6/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -4154,7 +4289,7 @@ $PAD Sh "44" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -295 -1613 $EndPAD $PAD @@ -4175,56 +4310,56 @@ $PAD Sh "41" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "N-000398" +Ne 122 "N-000375" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "N-000408" +Ne 130 "N-000386" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Ethernet_Phy/ETH_A3.3V" +Ne 46 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "N-000406" +Ne 127 "N-000381" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/Ethernet_Phy/ETH_INT" +Ne 47 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Ethernet_Phy/ETH_LED0" +Ne 48 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_LED1" +Ne 49 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4252,21 +4387,21 @@ $PAD Sh "31" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A1.8V" +Ne 45 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "N-000407" +Ne 129 "N-000385" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "N-000399" +Ne 123 "N-000376" Po 1613 -491 $EndPAD $PAD @@ -4280,70 +4415,70 @@ $PAD Sh "35" R 315 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 1613 -1082 $EndPAD $PAD Sh "13" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/Ethernet_Phy/ETH_1.8V" +Ne 44 "/Ethernet_Phy/ETH_1.8V" Po -1082 1613 $EndPAD $PAD Sh "14" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 68 "/FPGA_Spartan6/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 64 "/FPGA_Spartan6/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 57 "/Ethernet_Phy/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 65 "/FPGA_Spartan6/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 56 "/Ethernet_Phy/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 66 "/FPGA_Spartan6/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 67 "/FPGA_Spartan6/ETH_TXD3" Po 295 1613 $EndPAD $PAD @@ -4364,14 +4499,14 @@ $PAD Sh "23" R 99 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 885 1613 $EndPAD $PAD Sh "24" R 98 315 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po 1082 1613 $EndPAD $EndMODULE LQFP48 @@ -4635,14 +4770,14 @@ $PAD Sh "6" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/Non_volatile_memories/FRB_N" +Ne 109 "/Non_volatile_memories/FRB_N" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/Non_volatile_memories/FRB_N" +Ne 109 "/Non_volatile_memories/FRB_N" Po -1090 3850 $EndPAD $PAD @@ -4677,14 +4812,14 @@ $PAD Sh "12" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -100 3850 $EndPAD $PAD Sh "13" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 100 3850 $EndPAD $PAD @@ -4726,7 +4861,7 @@ $PAD Sh "19" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po 1280 3850 $EndPAD $PAD @@ -4845,14 +4980,14 @@ $PAD Sh "36" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 100 -3850 $EndPAD $PAD Sh "37" R 100 600 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -100 -3850 $EndPAD $PAD @@ -5010,28 +5145,28 @@ $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 2707 -1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2707 -1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2707 2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 2707 2244 $EndPAD $EndMODULE MICROSD-500901 @@ -5051,112 +5186,112 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 98 "N-000400" +Ne 126 "N-000380" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 98 "N-000400" +Ne 126 "N-000380" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 98 "N-000400" +Ne 126 "N-000380" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 98 "N-000400" +Ne 126 "N-000380" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 96 "N-000398" +Ne 122 "N-000375" Po -1750 -2500 $EndPAD $PAD Sh "3" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 85 "3.3V" +Ne 110 "3.3V" Po -750 -2500 $EndPAD $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 86 "GND" +Ne 111 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 97 "N-000399" +Ne 123 "N-000376" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 102 "N-000408" +Ne 130 "N-000386" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 86 "GND" +Ne 111 "GND" Po -250 -3500 $EndPAD $PAD Sh "6" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 85 "3.3V" +Ne 110 "3.3V" Po 750 -3500 $EndPAD $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 101 "N-000407" +Ne 129 "N-000385" Po 1750 -3500 $EndPAD $PAD Sh "9" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 85 "3.3V" +Ne 110 "3.3V" Po -2150 -5400 $EndPAD $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 95 "N-000396" +Ne 125 "N-000379" Po -1150 -5400 $EndPAD $PAD Sh "11" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 85 "3.3V" +Ne 110 "3.3V" Po 1150 -5400 $EndPAD $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 99 "N-000405" +Ne 124 "N-000378" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -5185,7 +5320,7 @@ $PAD Sh "1" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -767 1112 $EndPAD $PAD @@ -5227,14 +5362,14 @@ $PAD Sh "7" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 767 1112 $EndPAD $PAD Sh "8" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 767 -1112 $EndPAD $PAD @@ -5248,21 +5383,21 @@ $PAD Sh "10" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "N-000419" +Ne 135 "N-000395" Po 255 -1112 $EndPAD $PAD Sh "11" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "N-000420" +Ne 133 "N-000389" Po 0 -1112 $EndPAD $PAD Sh "12" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -255 -1112 $EndPAD $PAD @@ -5276,7 +5411,7 @@ $PAD Sh "14" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -767 -1112 $EndPAD $EndMODULE TSSOP-14 @@ -5298,91 +5433,91 @@ $PAD Sh "1" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000047" +Ne 1 "+2.5V" Po -4094 2176 $EndPAD $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M1_DQ0" +Ne 33 "/DDR_Banks/M1_DQ0" Po -3838 2176 $EndPAD $PAD Sh "3" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000047" +Ne 1 "+2.5V" Po -3582 2176 $EndPAD $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M1_DQ1" +Ne 34 "/DDR_Banks/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 37 "/DDR_Banks/M1_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 102 "/FPGA_Spartan6/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 38 "/DDR_Banks/M1_DQ4" Po -2303 2176 $EndPAD $PAD Sh "9" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000047" +Ne 1 "+2.5V" Po -2047 2176 $EndPAD $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_DQ5" +Ne 103 "/FPGA_Spartan6/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M1_DQ6" +Ne 104 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M1_DQ7" +Ne 105 "/FPGA_Spartan6/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5396,14 +5531,14 @@ $PAD Sh "15" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000047" +Ne 1 "+2.5V" Po -511 2176 $EndPAD $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_LDQS" +Ne 40 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -5417,7 +5552,7 @@ $PAD Sh "18" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000047" +Ne 1 "+2.5V" Po 255 2176 $EndPAD $PAD @@ -5431,35 +5566,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M1_LDM" +Ne 39 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_WE#" +Ne 43 "/DDR_Banks/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M1_CAS#" +Ne 96 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M1_RAS#" +Ne 108 "/FPGA_Spartan6/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 1791 2176 $EndPAD $PAD @@ -5473,119 +5608,119 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 94 "/FPGA_Spartan6/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 95 "/FPGA_Spartan6/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M1_A10" +Ne 23 "/DDR_Banks/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/M1_A0" +Ne 89 "/FPGA_Spartan6/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M1_A1" +Ne 90 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M1_A2" +Ne 25 "/DDR_Banks/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M1_A3" +Ne 26 "/DDR_Banks/M1_A3" Po 3838 2176 $EndPAD $PAD Sh "33" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000047" +Ne 1 "+2.5V" Po 4094 2176 $EndPAD $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M1_A4" +Ne 27 "/DDR_Banks/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M1_A5" +Ne 92 "/FPGA_Spartan6/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M1_A6" +Ne 93 "/FPGA_Spartan6/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M1_A7" +Ne 28 "/DDR_Banks/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M1_A8" +Ne 29 "/DDR_Banks/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M1_A9" +Ne 30 "/DDR_Banks/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M1_A11" +Ne 24 "/DDR_Banks/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M1_A12" +Ne 91 "/FPGA_Spartan6/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -5599,42 +5734,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M1_CLK#" +Ne 32 "/DDR_Banks/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M1_CKE" +Ne 97 "/FPGA_Spartan6/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M1_CLK" +Ne 31 "/DDR_Banks/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_UDM" +Ne 41 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 113 "N-000041" Po 255 -2176 $EndPAD $PAD @@ -5648,14 +5783,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M1_UDQS" +Ne 42 "/DDR_Banks/M1_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -511 -2176 $EndPAD $PAD @@ -5669,91 +5804,91 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_DQ8" +Ne 106 "/FPGA_Spartan6/M1_DQ8" Po -1023 -2176 $EndPAD $PAD Sh "55" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000047" +Ne 1 "+2.5V" Po -1279 -2176 $EndPAD $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M1_DQ9" +Ne 107 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_DQ10" +Ne 35 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_DQ11" +Ne 36 "/DDR_Banks/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M1_DQ12" +Ne 98 "/FPGA_Spartan6/M1_DQ12" Po -2558 -2176 $EndPAD $PAD Sh "61" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "N-000047" +Ne 1 "+2.5V" Po -2814 -2176 $EndPAD $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M1_DQ13" +Ne 99 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_DQ14" +Ne 100 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_DQ15" +Ne 101 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -5775,91 +5910,91 @@ $PAD Sh "1" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000054" +Ne 1 "+2.5V" Po -4094 2176 $EndPAD $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/FPGA_Spartan6/M0_DQ0" +Ne 78 "/FPGA_Spartan6/M0_DQ0" Po -3838 2176 $EndPAD $PAD Sh "3" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000054" +Ne 1 "+2.5V" Po -3582 2176 $EndPAD $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/FPGA_Spartan6/M0_DQ1" +Ne 79 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/M0_DQ2" +Ne 14 "/DDR_Banks/M0_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_DQ3" +Ne 15 "/DDR_Banks/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/M0_DQ4" +Ne 16 "/DDR_Banks/M0_DQ4" Po -2303 2176 $EndPAD $PAD Sh "9" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000054" +Ne 1 "+2.5V" Po -2047 2176 $EndPAD $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/M0_DQ5" +Ne 84 "/FPGA_Spartan6/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/M0_DQ6" +Ne 85 "/FPGA_Spartan6/M0_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/M0_DQ7" +Ne 17 "/DDR_Banks/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5873,14 +6008,14 @@ $PAD Sh "15" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000054" +Ne 1 "+2.5V" Po -511 2176 $EndPAD $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_LDQS" +Ne 20 "/DDR_Banks/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -5894,7 +6029,7 @@ $PAD Sh "18" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000054" +Ne 1 "+2.5V" Po 255 2176 $EndPAD $PAD @@ -5908,35 +6043,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_LDM" +Ne 86 "/FPGA_Spartan6/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/M0_WE#" +Ne 22 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_CAS#" +Ne 8 "/DDR_Banks/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_RAS#" +Ne 87 "/FPGA_Spartan6/M0_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 1791 2176 $EndPAD $PAD @@ -5950,119 +6085,119 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 76 "/FPGA_Spartan6/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 77 "/FPGA_Spartan6/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/DDR_Banks/M0_A10" +Ne 71 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/FPGA_Spartan6/M0_A0" +Ne 69 "/FPGA_Spartan6/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "/DDR_Banks/M0_A1" +Ne 70 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/FPGA_Spartan6/M0_A2" +Ne 2 "/DDR_Banks/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/FPGA_Spartan6/M0_A3" +Ne 3 "/DDR_Banks/M0_A3" Po 3838 2176 $EndPAD $PAD Sh "33" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000054" +Ne 1 "+2.5V" Po 4094 2176 $EndPAD $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/FPGA_Spartan6/M0_A4" +Ne 74 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/FPGA_Spartan6/M0_A5" +Ne 4 "/DDR_Banks/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/DDR_Banks/M0_A6" +Ne 5 "/DDR_Banks/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_A7" +Ne 6 "/DDR_Banks/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/FPGA_Spartan6/M0_A8" +Ne 75 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/FPGA_Spartan6/M0_A9" +Ne 7 "/DDR_Banks/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/FPGA_Spartan6/M0_A11" +Ne 72 "/FPGA_Spartan6/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/DDR_Banks/M0_A12" +Ne 73 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6076,42 +6211,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_CLK#" +Ne 11 "/DDR_Banks/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/FPGA_Spartan6/M0_CKE" +Ne 9 "/DDR_Banks/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/FPGA_Spartan6/M0_CLK" +Ne 10 "/DDR_Banks/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/M0_UDM" +Ne 88 "/FPGA_Spartan6/M0_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 114 "N-000042" Po 255 -2176 $EndPAD $PAD @@ -6125,14 +6260,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_UDQS" +Ne 21 "/DDR_Banks/M0_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -511 -2176 $EndPAD $PAD @@ -6146,91 +6281,91 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_DQ8" +Ne 18 "/DDR_Banks/M0_DQ8" Po -1023 -2176 $EndPAD $PAD Sh "55" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000054" +Ne 1 "+2.5V" Po -1279 -2176 $EndPAD $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/M0_DQ9" +Ne 19 "/DDR_Banks/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_DQ10" +Ne 80 "/FPGA_Spartan6/M0_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/FPGA_Spartan6/M0_DQ11" +Ne 81 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Spartan6/M0_DQ12" +Ne 82 "/FPGA_Spartan6/M0_DQ12" Po -2558 -2176 $EndPAD $PAD Sh "61" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "N-000054" +Ne 1 "+2.5V" Po -2814 -2176 $EndPAD $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/M0_DQ13" +Ne 12 "/DDR_Banks/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/M0_DQ14" +Ne 83 "/FPGA_Spartan6/M0_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/M0_DQ15" +Ne 13 "/DDR_Banks/M0_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -6251,14 +6386,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000426" +Ne 134 "N-000394" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6279,14 +6414,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "N-000400" +Ne 126 "N-000380" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6307,14 +6442,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "N-000405" +Ne 124 "N-000378" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_LED1" +Ne 49 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6335,14 +6470,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "N-000396" +Ne 125 "N-000379" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Ethernet_Phy/ETH_LED0" +Ne 48 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6363,14 +6498,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "N-000407" +Ne 129 "N-000385" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6391,14 +6526,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "N-000399" +Ne 123 "N-000376" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6419,14 +6554,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "N-000408" +Ne 130 "N-000386" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6447,14 +6582,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "N-000398" +Ne 122 "N-000375" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6475,14 +6610,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "N-000406" +Ne 127 "N-000381" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6503,14 +6638,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/ETH_MDIO" +Ne 51 "/Ethernet_Phy/ETH_MDIO" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6531,14 +6666,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000426" +Ne 134 "N-000394" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6559,14 +6694,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "N-000400" +Ne 126 "N-000380" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6587,14 +6722,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6615,14 +6750,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6643,14 +6778,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 52 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "N-000416" +Ne 131 "N-000387" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6671,14 +6806,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Ethernet_Phy/ETH_A3.3V" +Ne 46 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6699,14 +6834,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A1.8V" +Ne 45 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "N-000416" +Ne 131 "N-000387" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6727,14 +6862,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6755,14 +6890,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "N-000417" +Ne 128 "N-000383" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "N-000416" +Ne 131 "N-000387" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6783,14 +6918,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6811,14 +6946,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/Ethernet_Phy/ETH_1.8V" +Ne 44 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6839,14 +6974,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "N-000419" +Ne 135 "N-000395" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -6867,14 +7002,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "N-000420" +Ne 133 "N-000389" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -6895,14 +7030,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A1.8V" +Ne 45 "/Ethernet_Phy/ETH_A1.8V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 52 "/Ethernet_Phy/ETH_PLL1.8V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -6923,14 +7058,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Ethernet_Phy/ETH_A3.3V" +Ne 46 "/Ethernet_Phy/ETH_A3.3V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -6951,14 +7086,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "N-000417" +Ne 128 "N-000383" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A1.8V" +Ne 45 "/Ethernet_Phy/ETH_A1.8V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -6979,14 +7114,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7007,14 +7142,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7035,14 +7170,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7063,14 +7198,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Ethernet_Phy/ETH_A3.3V" +Ne 46 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7091,14 +7226,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "3.3V" +Ne 110 "3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "GND" +Ne 111 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7119,7 +7254,7 @@ $PAD Sh "1" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "N-000425" +Ne 132 "N-000388" Po -570 0 $EndPAD $PAD @@ -7152,59 +7287,675 @@ $PAD Sh "1" R 470 470 0 0 0 Dr 360 0 0 At STD N 0CC0FFFF -Ne 107 "N-000425" +Ne 132 "N-000388" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 0 Dr 360 0 0 At STD N 0CC0FFFF -Ne 105 "N-000419" +Ne 135 "N-000395" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 0 Dr 360 0 0 At STD N 0CC0FFFF -Ne 106 "N-000420" +Ne 133 "N-000389" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 0 Dr 360 0 0 At STD N 0CC0FFFF -Ne 106 "N-000420" +Ne 133 "N-000389" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 0 Dr 532 0 0 At STD N 0CC0FFFF -Ne 108 "N-000426" +Ne 134 "N-000394" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 0 Dr 532 0 0 At STD N 0CC0FFFF -Ne 108 "N-000426" +Ne 134 "N-000394" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 0 Dr 532 0 0 At STD N 0CC0FFFF -Ne 108 "N-000426" +Ne 134 "N-000394" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 0 Dr 532 0 0 At STD N 0CC0FFFF -Ne 108 "N-000426" +Ne 134 "N-000394" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 +$MODULE 0402 +Po 45000 29500 0 15 4C5FF890 4C61CD11 ~~ +Li 0402 +Sc 4C61CD11 +AR /4C421DD3/4C61CC73 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C17" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 114 "N-000042" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 46000 29000 0 15 4C5FF890 4C61CD13 ~~ +Li 0402 +Sc 4C61CD13 +AR /4C421DD3/4C61CC96 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C18" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 114 "N-000042" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 115 "N-000044" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 63000 28500 0 15 4C5FF890 4C61CD15 ~~ +Li 0402 +Sc 4C61CD15 +AR /4C421DD3/4C61CCE2 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C20" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 113 "N-000041" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 112 "N-000040" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 64000 28500 0 15 4C5FF890 4C61CD17 ~~ +Li 0402 +Sc 4C61CD17 +AR /4C421DD3/4C61CCE3 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C19" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 113 "N-000041" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 45000 34500 0 15 4C5FF890 4C61D013 ~~ +Li 0402 +Sc 4C61D013 +AR /4C421DD3/4C61CD4A +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R11" +T1 0 150 200 200 0 40 N I 25 N"1K_1%" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 114 "N-000042" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 45000 33500 0 15 4C5FF890 4C61D015 ~~ +Li 0402 +Sc 4C61D015 +AR /4C421DD3/4C61CDB5 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R12" +T1 0 150 200 200 0 40 N I 25 N"1K_1%" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 114 "N-000042" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 115 "N-000044" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 65000 29000 0 15 4C5FF890 4C61D017 ~~ +Li 0402 +Sc 4C61D017 +AR /4C421DD3/4C61CE31 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R13" +T1 0 150 200 200 0 40 N I 25 N"1K_1%" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 113 "N-000041" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 45500 37000 0 15 4C5FF890 4C61D019 ~~ +Li 0402 +Sc 4C61D019 +AR /4C421DD3/4C61CEB9 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C22" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 46000 35000 0 15 4C5FF890 4C61D01B ~~ +Li 0402 +Sc 4C61D01B +AR /4C421DD3/4C61CEF7 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C23" +T1 0 150 200 200 0 40 N I 25 N"10nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 46000 30000 0 15 4C5FF890 4C61D01D ~~ +Li 0402 +Sc 4C61D01D +AR /4C421DD3/4C61CF16 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C25" +T1 0 150 200 200 0 40 N I 25 N"10nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 46000 32000 0 15 4C5FF890 4C61D01F ~~ +Li 0402 +Sc 4C61D01F +AR /4C421DD3/4C61CF17 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C24" +T1 0 150 200 200 0 40 N I 25 N"10nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 46000 33000 0 15 4C5FF890 4C61D021 ~~ +Li 0402 +Sc 4C61D021 +AR /4C421DD3/4C61CF27 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C26" +T1 0 150 200 200 0 40 N I 25 N"10nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 67000 36500 0 15 4C5FF890 4C61D023 ~~ +Li 0402 +Sc 4C61D023 +AR /4C421DD3/4C61CFA1 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C32" +T1 0 150 200 200 0 40 N I 25 N"10nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 67500 34000 0 15 4C5FF890 4C61D025 ~~ +Li 0402 +Sc 4C61D025 +AR /4C421DD3/4C61CFA2 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C30" +T1 0 150 200 200 0 40 N I 25 N"10nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 67500 35000 0 15 4C5FF890 4C61D027 ~~ +Li 0402 +Sc 4C61D027 +AR /4C421DD3/4C61CFA3 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C31" +T1 0 150 200 200 0 40 N I 25 N"10nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 67000 35500 0 15 4C5FF890 4C61D029 ~~ +Li 0402 +Sc 4C61D029 +AR /4C421DD3/4C61CFA4 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C29" +T1 0 150 200 200 0 40 N I 25 N"10nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 67500 32500 0 15 4C5FF890 4C61D02B ~~ +Li 0402 +Sc 4C61D02B +AR /4C421DD3/4C61CFA5 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C28" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 46000 31000 0 15 4C5FF890 4C61D02C ~~ +Li 0603 +Sc 4C61D02C +AR /4C421DD3/4C61CF2F +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C21" +T1 0 150 200 200 0 40 N I 25 N"1uF" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 66000 27500 0 15 4C5FF890 4C61D02E ~~ +Li 0603 +Sc 4C61D02E +AR /4C421DD3/4C61CFA0 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C27" +T1 0 150 200 200 0 40 N I 25 N"1uF" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0402 +Po 63000 29000 0 15 4C5FF890 4C61D035 ~~ +Li 0402 +Sc 4C61D035 +AR /4C421DD3/4C61CE30 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R14" +T1 0 150 200 200 0 40 N I 25 N"1K_1%" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 113 "N-000041" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 112 "N-000040" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 1206 +Po 49500 39000 0 15 4C5FF890 4C61D1B6 ~~ +Li 1206 +Sc 4C61D1B6 +AR /4C421DD3/4C61D151 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C33" +T1 0 150 200 200 0 40 N I 25 N"1uF" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 +$MODULE 1206 +Po 64000 39000 0 15 4C5FF890 4C61D46D ~~ +Li 1206 +Sc 4C61D46D +AR /4C421DD3/4C61D1D4 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C34" +T1 0 150 200 200 0 40 N I 25 N"1uF" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+2.5V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 $TRACK $EndTRACK $ZONE diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 3fa3938..bff8cd5 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,10 +1,10 @@ -# EESchema Netlist Version 1.1 created Mon 09 Aug 2010 10:11:11 PM COT +# EESchema Netlist Version 1.1 created Tue 10 Aug 2010 05:36:23 PM COT ( ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} ( P7 ? ) ( N7 ? ) ( M7 ? ) - ( L7 N-000153 ) + ( L7 N-000124 ) ( K7 ? ) ( J7 ? ) ( G7 ? ) @@ -13,28 +13,28 @@ ( N6 ? ) ( M6 ? ) ( L6 ? ) - ( K6 /FPGA_Spartan6/M0_A3 ) + ( K6 /DDR_Banks/M0_A3 ) ( J6 ? ) ( H6 /DDR_Banks/M0_A7 ) ( G6 ? ) - ( F6 N-000153 ) + ( F6 N-000124 ) ( E6 ? ) - ( U5 N-000153 ) + ( U5 N-000124 ) ( P5 ? ) - ( N5 N-000153 ) + ( N5 N-000124 ) ( M5 ? ) - ( K5 /DDR_Banks/M0_RAS# ) - ( J5 N-000153 ) - ( H5 /FPGA_Spartan6/M0_A2 ) + ( K5 /FPGA_Spartan6/M0_RAS# ) + ( J5 N-000124 ) + ( H5 /DDR_Banks/M0_A2 ) ( F5 ? ) ( E5 ? ) ( D5 ? ) ( U4 ? ) ( H21 /FPGA_Spartan6/M1_RAS# ) - ( G21 N-000155 ) + ( G21 N-000119 ) ( F21 /FPGA_Spartan6/M1_A0 ) ( D21 /FPGA_Spartan6/M1_CKE ) - ( C21 N-000155 ) + ( C21 N-000119 ) ( B21 ? ) ( A21 ? ) ( W20 ? ) @@ -43,17 +43,17 @@ ( T20 ? ) ( R20 /DDR_Banks/M1_DQ10 ) ( P20 ? ) - ( N20 /FPGA_Spartan6/M1_DQ0 ) + ( N20 /DDR_Banks/M1_DQ0 ) ( M20 /DDR_Banks/M1_UDM ) ( L20 /DDR_Banks/M1_LDQS ) - ( K20 /DDR_Banks/M1_A5 ) - ( J20 ? ) - ( H20 /FPGA_Spartan6/M1_CLK ) + ( K20 /FPGA_Spartan6/M1_A5 ) + ( J20 /DDR_Banks/M1_DQ4 ) + ( H20 /DDR_Banks/M1_CLK ) ( G20 /DDR_Banks/M1_A3 ) - ( F20 /FPGA_Spartan6/M1_A4 ) + ( F20 /DDR_Banks/M1_A4 ) ( E20 /DDR_Banks/M1_A7 ) ( D20 ? ) - ( C20 /FPGA_Spartan6/M1_A8 ) + ( C20 /DDR_Banks/M1_A8 ) ( B20 ? ) ( A20 ? ) ( P8 ? ) @@ -61,99 +61,99 @@ ( K8 ? ) ( H8 ? ) ( B3 ? ) - ( W2 N-000153 ) + ( W2 N-000124 ) ( V2 /FPGA_Spartan6/M0_DQ14 ) ( T2 /DDR_Banks/M0_UDQS ) - ( R2 N-000153 ) + ( R2 N-000124 ) ( P2 /DDR_Banks/M0_DQ8 ) - ( M2 /FPGA_Spartan6/M0_DQ2 ) - ( L2 N-000153 ) + ( M2 /DDR_Banks/M0_DQ2 ) + ( L2 N-000124 ) ( K2 /FPGA_Spartan6/M0_DQ6 ) ( H2 /FPGA_Spartan6/M0_A0 ) - ( G2 N-000153 ) - ( F2 /FPGA_Spartan6/M0_WE# ) - ( D2 /FPGA_Spartan6/M0_CKE ) - ( C2 N-000153 ) + ( G2 N-000124 ) + ( F2 /DDR_Banks/M0_WE# ) + ( D2 /DDR_Banks/M0_CKE ) + ( C2 N-000124 ) ( B2 ? ) ( A2 ? ) ( Y1 ? ) ( W1 ? ) - ( V1 /FPGA_Spartan6/M0_DQ15 ) - ( U1 /FPGA_Spartan6/M0_DQ13 ) + ( V1 /DDR_Banks/M0_DQ15 ) + ( U1 /DDR_Banks/M0_DQ13 ) ( T1 ? ) ( R1 /FPGA_Spartan6/M0_DQ11 ) - ( P1 /FPGA_Spartan6/M0_DQ9 ) + ( P1 /DDR_Banks/M0_DQ9 ) ( N1 /FPGA_Spartan6/M0_DQ1 ) ( M1 /DDR_Banks/M0_DQ3 ) ( L1 ? ) - ( K1 /FPGA_Spartan6/M0_DQ7 ) + ( K1 /DDR_Banks/M0_DQ7 ) ( J1 /FPGA_Spartan6/M0_DQ5 ) - ( H1 /DDR_Banks/M0_A1 ) - ( G1 ? ) + ( H1 /FPGA_Spartan6/M0_A1 ) + ( G1 /FPGA_Spartan6/M0_BA1 ) ( T4 ? ) ( R4 ? ) ( P4 ? ) ( N4 ? ) ( M4 ? ) - ( L4 /DDR_Banks/M0_LDM ) + ( L4 /FPGA_Spartan6/M0_LDM ) ( K4 /DDR_Banks/M0_CAS# ) ( J4 /DDR_Banks/M0_A6 ) - ( H4 /FPGA_Spartan6/M0_CLK ) - ( G4 /DDR_Banks/M0_A10 ) - ( F4 N-000153 ) + ( H4 /DDR_Banks/M0_CLK ) + ( G4 /FPGA_Spartan6/M0_A10 ) + ( F4 N-000124 ) ( E4 ? ) ( C4 ? ) ( W3 ? ) ( V3 ? ) ( U3 /FPGA_Spartan6/M0_DQ12 ) ( T3 ? ) - ( R3 /DDR_Banks/M0_DQ10 ) + ( R3 /FPGA_Spartan6/M0_DQ10 ) ( P3 ? ) ( N3 /FPGA_Spartan6/M0_DQ0 ) ( M3 /FPGA_Spartan6/M0_UDM ) ( L3 /DDR_Banks/M0_LDQS ) - ( K3 /FPGA_Spartan6/M0_A5 ) - ( J3 /FPGA_Spartan6/M0_DQ4 ) + ( K3 /DDR_Banks/M0_A5 ) + ( J3 /DDR_Banks/M0_DQ4 ) ( H3 /DDR_Banks/M0_CLK# ) - ( G3 ? ) + ( G3 /FPGA_Spartan6/M0_BA0 ) ( F3 /FPGA_Spartan6/M0_A4 ) ( E3 /FPGA_Spartan6/M0_A8 ) ( D3 ? ) ( C3 ? ) - ( G10 N-000137 ) - ( D10 ? ) - ( C10 ? ) - ( B10 ? ) - ( A10 ? ) - ( E9 N-000137 ) - ( D9 ? ) - ( C9 ? ) - ( A9 ? ) - ( D8 ? ) - ( C8 ? ) - ( B8 ? ) - ( A8 ? ) - ( D7 ? ) - ( C7 ? ) - ( B7 N-000137 ) - ( A7 ? ) - ( D6 ? ) - ( C6 ? ) - ( B6 ? ) - ( A6 ? ) + ( G10 N-000120 ) + ( D10 /FPGA_Spartan6/ETH_TXD3 ) + ( C10 /FPGA_Spartan6/ETH_TXC ) + ( B10 /Ethernet_Phy/ETH_RXC ) + ( A10 /FPGA_Spartan6/ETH_CLK ) + ( E9 N-000120 ) + ( D9 /Ethernet_Phy/ETH_RXER ) + ( C9 /Ethernet_Phy/ETH_TXEN ) + ( A9 /FPGA_Spartan6/ETH_TXD0 ) + ( D8 /FPGA_Spartan6/ETH_TXD2 ) + ( C8 /FPGA_Spartan6/ETH_TXER ) + ( B8 /FPGA_Spartan6/ETH_RXD0 ) + ( A8 /Ethernet_Phy/ETH_RXDV ) + ( D7 /Ethernet_Phy/ETH_TXD1 ) + ( C7 /FPGA_Spartan6/ETH_RXD2 ) + ( B7 N-000120 ) + ( A7 /FPGA_Spartan6/ETH_RXD1 ) + ( D6 /Ethernet_Phy/ETH_MDC ) + ( C6 /Ethernet_Phy/ETH_MDIO ) + ( B6 /FPGA_Spartan6/ETH_RESET_N ) + ( A6 /FPGA_Spartan6/ETH_RXD3 ) ( C5 ? ) ( A5 /Ethernet_Phy/ETH_INT ) - ( B4 N-000137 ) + ( B4 N-000120 ) ( A4 ? ) ( U19 ? ) ( T19 ? ) ( R19 ? ) ( P19 ? ) ( N19 ? ) - ( B19 N-000137 ) + ( B19 N-000120 ) ( B18 ? ) ( A18 ? ) - ( E17 N-000137 ) + ( E17 N-000120 ) ( D17 ? ) ( C17 ? ) ( A17 ? ) @@ -163,14 +163,14 @@ ( A16 ? ) ( D15 ? ) ( C15 ? ) - ( B15 N-000137 ) + ( B15 N-000120 ) ( A15 ? ) - ( G14 N-000137 ) + ( G14 N-000120 ) ( D14 ? ) ( C14 ? ) ( B14 ? ) ( A14 ? ) - ( E13 N-000137 ) + ( E13 N-000120 ) ( C13 ? ) ( A13 ? ) ( C12 ? ) @@ -178,77 +178,77 @@ ( A12 ? ) ( D11 ? ) ( C11 ? ) - ( B11 N-000137 ) + ( B11 N-000120 ) ( A11 ? ) ( H16 ? ) ( G16 ? ) ( F16 ? ) ( L15 ? ) ( W22 ? ) - ( V22 /DDR_Banks/M1_DQ15 ) + ( V22 /FPGA_Spartan6/M1_DQ15 ) ( U22 /FPGA_Spartan6/M1_DQ13 ) ( T22 ? ) ( R22 /DDR_Banks/M1_DQ11 ) ( P22 /FPGA_Spartan6/M1_DQ9 ) - ( N22 /FPGA_Spartan6/M1_DQ1 ) - ( M22 ? ) + ( N22 /DDR_Banks/M1_DQ1 ) + ( M22 /FPGA_Spartan6/M1_DQ3 ) ( L22 ? ) ( K22 /FPGA_Spartan6/M1_DQ7 ) - ( J22 /DDR_Banks/M1_DQ5 ) + ( J22 /FPGA_Spartan6/M1_DQ5 ) ( H22 /FPGA_Spartan6/M1_CAS# ) ( G22 ? ) ( F22 /FPGA_Spartan6/M1_A1 ) - ( E22 /FPGA_Spartan6/M1_A2 ) - ( D22 /DDR_Banks/M1_A12 ) - ( C22 /FPGA_Spartan6/M1_A9 ) + ( E22 /DDR_Banks/M1_A2 ) + ( D22 /FPGA_Spartan6/M1_A12 ) + ( C22 /DDR_Banks/M1_A9 ) ( B22 ? ) - ( W21 N-000155 ) - ( V21 /DDR_Banks/M1_DQ14 ) - ( T21 /FPGA_Spartan6/M1_UDQS ) - ( R21 N-000155 ) - ( P21 /DDR_Banks/M1_DQ8 ) - ( M21 ? ) - ( L21 N-000155 ) + ( W21 N-000119 ) + ( V21 /FPGA_Spartan6/M1_DQ14 ) + ( T21 /DDR_Banks/M1_UDQS ) + ( R21 N-000119 ) + ( P21 /FPGA_Spartan6/M1_DQ8 ) + ( M21 /DDR_Banks/M1_DQ2 ) + ( L21 N-000119 ) ( K21 /FPGA_Spartan6/M1_DQ6 ) ( M19 ? ) - ( L19 /FPGA_Spartan6/M1_LDM ) - ( K19 /DDR_Banks/M1_A6 ) - ( J19 /FPGA_Spartan6/M1_CLK# ) + ( L19 /DDR_Banks/M1_LDM ) + ( K19 /FPGA_Spartan6/M1_A6 ) + ( J19 /DDR_Banks/M1_CLK# ) ( H19 /DDR_Banks/M1_WE# ) - ( G19 /FPGA_Spartan6/M1_A10 ) - ( F19 /FPGA_Spartan6/M1_A11 ) - ( E19 N-000155 ) + ( G19 /DDR_Banks/M1_A10 ) + ( F19 /DDR_Banks/M1_A11 ) + ( E19 N-000119 ) ( D19 ? ) - ( U18 N-000155 ) + ( U18 N-000119 ) ( P18 ? ) - ( N18 N-000155 ) + ( N18 N-000119 ) ( M18 ? ) ( K18 ? ) - ( J18 N-000155 ) + ( J18 N-000119 ) ( H18 ? ) ( F18 ? ) ( P17 ? ) ( M17 ? ) ( L17 ? ) - ( K17 ? ) - ( J17 ? ) + ( K17 /FPGA_Spartan6/M1_BA1 ) + ( J17 /FPGA_Spartan6/M1_BA0 ) ( H17 ? ) ( G17 ? ) ( F17 ? ) ( N16 ? ) ( M16 ? ) - ( L16 N-000155 ) + ( L16 N-000119 ) ( K16 ? ) ( J16 ? ) - ( J14 N-000156 ) + ( J14 N-000122 ) ( H14 ? ) ( F14 ? ) ( E14 ? ) - ( P13 N-000156 ) + ( P13 N-000122 ) ( N13 GND ) - ( M13 N-000156 ) + ( M13 N-000122 ) ( L13 GND ) - ( K13 N-000156 ) + ( K13 N-000122 ) ( J13 GND ) ( H13 ? ) ( G13 ? ) @@ -257,15 +257,15 @@ ( B13 GND ) ( Y22 ? ) ( A22 GND ) - ( R12 N-000157 ) + ( R12 N-000123 ) ( P12 GND ) - ( N12 N-000156 ) + ( N12 N-000122 ) ( M12 GND ) - ( L12 N-000156 ) + ( L12 N-000122 ) ( K12 ? ) - ( J12 N-000156 ) + ( J12 N-000122 ) ( H12 ? ) - ( G12 N-000157 ) + ( G12 N-000123 ) ( F12 ? ) ( E12 ? ) ( D12 ? ) @@ -282,34 +282,34 @@ ( B17 GND ) ( W16 GND ) ( P16 ? ) - ( D16 N-000157 ) + ( D16 N-000123 ) ( AA5 GND ) ( P15 ? ) ( N15 ? ) - ( M15 N-000157 ) - ( K15 N-000157 ) + ( M15 N-000123 ) + ( K15 N-000123 ) ( J15 GND ) - ( H15 N-000157 ) + ( H15 N-000123 ) ( G15 ? ) ( F15 ? ) ( E15 GND ) ( V14 GND ) - ( R14 N-000156 ) + ( R14 N-000122 ) ( P14 GND ) - ( N14 N-000156 ) + ( N14 N-000122 ) ( M14 GND ) - ( L14 N-000156 ) + ( L14 N-000122 ) ( K14 GND ) ( L9 GND ) - ( K9 N-000156 ) + ( K9 N-000122 ) ( J9 GND ) - ( H9 N-000157 ) + ( H9 N-000123 ) ( G9 ? ) ( F9 ? ) ( B9 GND ) - ( N8 N-000157 ) - ( L8 N-000157 ) - ( J8 N-000156 ) + ( N8 N-000123 ) + ( L8 N-000123 ) + ( J8 N-000122 ) ( G8 ? ) ( F8 ? ) ( E8 ? ) @@ -317,8 +317,8 @@ ( U7 GND ) ( H7 GND ) ( E7 GND ) - ( V6 N-000157 ) - ( R6 N-000157 ) + ( V6 N-000123 ) + ( R6 N-000123 ) ( R5 GND ) ( L5 GND ) ( G5 GND ) @@ -335,31 +335,31 @@ ( N21 GND ) ( J21 GND ) ( E21 GND ) - ( U11 N-000157 ) - ( P11 N-000156 ) + ( U11 N-000123 ) + ( P11 N-000122 ) ( N11 GND ) - ( M11 N-000156 ) + ( M11 N-000122 ) ( L11 GND ) - ( K11 N-000156 ) + ( K11 N-000122 ) ( J11 GND ) ( H11 ? ) ( G11 ? ) - ( F11 N-000157 ) + ( F11 N-000123 ) ( E11 ? ) ( V10 GND ) - ( R10 N-000157 ) + ( R10 N-000123 ) ( P10 GND ) - ( N10 N-000156 ) + ( N10 N-000122 ) ( M10 GND ) - ( L10 N-000156 ) + ( L10 N-000122 ) ( K10 GND ) - ( J10 N-000156 ) + ( J10 N-000122 ) ( H10 ? ) ( F10 ? ) ( E10 ? ) - ( P9 N-000156 ) + ( P9 N-000122 ) ( N9 GND ) - ( M9 N-000156 ) + ( M9 N-000122 ) ( V19 ? ) ( AB8 ? ) ( AA8 ? ) @@ -368,7 +368,7 @@ ( V18 ? ) ( T18 ? ) ( AB7 ? ) - ( AA7 N-000154 ) + ( AA7 N-000121 ) ( Y17 ? ) ( W17 ? ) ( V17 ? ) @@ -377,7 +377,7 @@ ( AB6 ? ) ( AA6 ? ) ( Y16 ? ) - ( V16 N-000154 ) + ( V16 N-000121 ) ( U16 ? ) ( T16 ? ) ( R16 ? ) @@ -391,19 +391,19 @@ ( AB4 ? ) ( AA4 ? ) ( F1 ? ) - ( E1 /FPGA_Spartan6/M0_A9 ) - ( D1 /DDR_Banks/M0_A12 ) + ( E1 /DDR_Banks/M0_A9 ) + ( D1 /FPGA_Spartan6/M0_A12 ) ( C1 /FPGA_Spartan6/M0_A11 ) ( B1 ? ) ( AB19 ? ) - ( AA19 N-000154 ) + ( AA19 N-000121 ) ( AB18 ? ) ( AA18 ? ) ( AB17 ? ) ( AB16 ? ) ( AA16 ? ) ( AB15 ? ) - ( AA15 N-000154 ) + ( AA15 N-000121 ) ( AB14 ? ) ( AA14 ? ) ( AB13 ? ) @@ -413,7 +413,7 @@ ( AB21 ? ) ( AA21 ? ) ( AB11 ? ) - ( AA11 N-000154 ) + ( AA11 N-000121 ) ( AB20 ? ) ( AA20 ? ) ( AB10 ? ) @@ -422,11 +422,11 @@ ( Y19 ? ) ( V9 ? ) ( U9 ? ) - ( T9 N-000154 ) + ( T9 N-000121 ) ( R9 ? ) ( Y8 ? ) ( W8 ? ) - ( V8 N-000154 ) + ( V8 N-000121 ) ( U8 ? ) ( T8 ? ) ( R8 ? ) @@ -439,7 +439,7 @@ ( U6 ? ) ( T6 ? ) ( Y5 ? ) - ( W5 N-000154 ) + ( W5 N-000121 ) ( V5 ? ) ( T5 ? ) ( Y4 ? ) @@ -455,18 +455,18 @@ ( U14 ? ) ( T14 ? ) ( AB3 ? ) - ( AA3 N-000154 ) + ( AA3 N-000121 ) ( Y13 ? ) ( W13 ? ) ( V13 ? ) ( U13 ? ) - ( T13 N-000154 ) + ( T13 N-000121 ) ( R13 ? ) ( AB2 ? ) ( AA2 ? ) ( Y12 ? ) ( W12 ? ) - ( V12 N-000154 ) + ( V12 N-000121 ) ( U12 ? ) ( T12 ? ) ( Y11 ? ) @@ -482,33 +482,33 @@ ( W9 ? ) ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000426 ) + ( 1 N-000394 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000426 ) + ( 1 N-000394 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000420 ) + ( 1 N-000389 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000419 ) + ( 1 N-000395 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000425 ) + ( 1 N-000388 ) ( 2 ? ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000426 ) - ( S2 N-000426 ) - ( S3 N-000426 ) - ( S4 N-000426 ) - ( 1 N-000425 ) - ( 2 N-000419 ) - ( 3 N-000420 ) + ( S1 N-000394 ) + ( S2 N-000394 ) + ( S3 N-000394 ) + ( S4 N-000394 ) + ( 1 N-000388 ) + ( 2 N-000395 ) + ( 3 N-000389 ) ( 4 GND ) ) ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} @@ -532,14 +532,14 @@ ( 7 GND ) ( 8 GND ) ( 9 ? ) - ( 10 N-000419 ) - ( 11 N-000420 ) + ( 10 N-000395 ) + ( 11 N-000389 ) ( 12 3.3V ) ( 14 3.3V ) ) ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} ( 1 /Ethernet_Phy/ETH_PLL1.8V ) - ( 2 N-000416 ) + ( 2 N-000387 ) ) ( /4C4320F3/4C5D810A $noname L3 INDUCTOR {Lib=INDUCTOR} ( 1 /Ethernet_Phy/ETH_A1.8V ) @@ -547,15 +547,15 @@ ) ( /4C4320F3/4C5D8104 $noname C6 C {Lib=C} ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 N-000416 ) + ( 2 N-000387 ) ) ( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR} - ( 1 N-000417 ) + ( 1 N-000383 ) ( 2 /Ethernet_Phy/ETH_A1.8V ) ) ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} - ( 1 N-000417 ) - ( 2 N-000416 ) + ( 1 N-000383 ) + ( 2 N-000387 ) ) ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} ( 1 /Ethernet_Phy/ETH_1.8V ) @@ -586,11 +586,11 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} - ( 1 /ETH_MDIO ) + ( 1 /Ethernet_Phy/ETH_MDIO ) ( 2 3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000406 ) + ( 1 N-000381 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} @@ -602,34 +602,34 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000400 ) + ( 1 N-000380 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000400 ) + ( 1 N-000380 ) ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /ETH_MDIO ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) + ( 1 /Ethernet_Phy/ETH_MDIO ) + ( 2 /Ethernet_Phy/ETH_MDC ) + ( 3 /FPGA_Spartan6/ETH_RXD3 ) + ( 4 /FPGA_Spartan6/ETH_RXD2 ) + ( 5 /FPGA_Spartan6/ETH_RXD1 ) + ( 6 /FPGA_Spartan6/ETH_RXD0 ) ( 7 3.3V ) ( 8 GND ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) + ( 9 /Ethernet_Phy/ETH_RXDV ) + ( 10 /Ethernet_Phy/ETH_RXC ) + ( 11 /Ethernet_Phy/ETH_RXER ) ( 12 GND ) ( 13 /Ethernet_Phy/ETH_1.8V ) - ( 14 ? ) - ( 15 ? ) - ( 16 ? ) - ( 17 ? ) - ( 18 ? ) - ( 19 ? ) - ( 20 ? ) + ( 14 /FPGA_Spartan6/ETH_TXER ) + ( 15 /FPGA_Spartan6/ETH_TXC ) + ( 16 /Ethernet_Phy/ETH_TXEN ) + ( 17 /FPGA_Spartan6/ETH_TXD0 ) + ( 18 /Ethernet_Phy/ETH_TXD1 ) + ( 19 /FPGA_Spartan6/ETH_TXD2 ) + ( 20 /FPGA_Spartan6/ETH_TXD3 ) ( 21 ? ) ( 22 ? ) ( 23 GND ) @@ -641,63 +641,63 @@ ( 29 ? ) ( 30 ? ) ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000407 ) - ( 33 N-000399 ) + ( 32 N-000385 ) + ( 33 N-000376 ) ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000406 ) + ( 37 N-000381 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) - ( 40 N-000408 ) - ( 41 N-000398 ) + ( 40 N-000386 ) + ( 41 N-000375 ) ( 42 ? ) ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 ? ) + ( 46 /FPGA_Spartan6/ETH_CLK ) ( 47 /Ethernet_Phy/ETH_PLL1.8V ) - ( 48 ? ) + ( 48 /FPGA_Spartan6/ETH_RESET_N ) ) ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000398 ) + ( 2 N-000375 ) ) ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000408 ) + ( 2 N-000386 ) ) ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000407 ) + ( 2 N-000385 ) ) ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000399 ) + ( 2 N-000376 ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000405 ) + ( 1 N-000378 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000396 ) + ( 1 N-000379 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000398 ) - ( 2 N-000408 ) + ( 1 N-000375 ) + ( 2 N-000386 ) ( 3 3.3V ) ( 4 GND ) ( 5 GND ) ( 6 3.3V ) - ( 7 N-000399 ) - ( 8 N-000407 ) + ( 7 N-000376 ) + ( 8 N-000385 ) ( 9 3.3V ) - ( 10 N-000396 ) + ( 10 N-000379 ) ( 11 3.3V ) - ( 12 N-000405 ) - ( 13 N-000400 ) - ( 14 N-000400 ) + ( 12 N-000378 ) + ( 13 N-000380 ) + ( 14 N-000380 ) ) ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} ( CASE GND ) @@ -762,140 +762,228 @@ ( 47 ? ) ( 48 ? ) ) + ( /4C421DD3/4C61D1D4 1206 C34 1uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61D151 1206 C33 1uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R} + ( 1 +2.5V ) + ( 2 N-000041 ) + ) + ( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R} + ( 1 N-000041 ) + ( 2 N-000040 ) + ) + ( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R} + ( 1 N-000042 ) + ( 2 N-000044 ) + ) + ( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R} + ( 1 +2.5V ) + ( 2 N-000042 ) + ) + ( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 N-000041 ) + ) + ( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP} + ( 1 N-000041 ) + ( 2 N-000040 ) + ) + ( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP} + ( 1 N-000042 ) + ( 2 N-000044 ) + ) + ( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP} + ( 1 +2.5V ) + ( 2 N-000042 ) + ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} - ( 1 N-000047 ) - ( 2 /FPGA_Spartan6/M1_DQ0 ) - ( 3 N-000047 ) - ( 4 /FPGA_Spartan6/M1_DQ1 ) - ( 5 ? ) + ( 1 +2.5V ) + ( 2 /DDR_Banks/M1_DQ0 ) + ( 3 +2.5V ) + ( 4 /DDR_Banks/M1_DQ1 ) + ( 5 /DDR_Banks/M1_DQ2 ) ( 6 GND ) - ( 7 ? ) - ( 8 ? ) - ( 9 N-000047 ) - ( 10 /DDR_Banks/M1_DQ5 ) + ( 7 /FPGA_Spartan6/M1_DQ3 ) + ( 8 /DDR_Banks/M1_DQ4 ) + ( 9 +2.5V ) + ( 10 /FPGA_Spartan6/M1_DQ5 ) ( 11 /FPGA_Spartan6/M1_DQ6 ) ( 12 GND ) ( 13 /FPGA_Spartan6/M1_DQ7 ) ( 14 ? ) - ( 15 N-000047 ) + ( 15 +2.5V ) ( 16 /DDR_Banks/M1_LDQS ) ( 17 ? ) - ( 18 N-000047 ) + ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Spartan6/M1_LDM ) + ( 20 /DDR_Banks/M1_LDM ) ( 21 /DDR_Banks/M1_WE# ) ( 22 /FPGA_Spartan6/M1_CAS# ) ( 23 /FPGA_Spartan6/M1_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 /FPGA_Spartan6/M1_A10 ) + ( 26 /FPGA_Spartan6/M1_BA0 ) + ( 27 /FPGA_Spartan6/M1_BA1 ) + ( 28 /DDR_Banks/M1_A10 ) ( 29 /FPGA_Spartan6/M1_A0 ) ( 30 /FPGA_Spartan6/M1_A1 ) - ( 31 /FPGA_Spartan6/M1_A2 ) + ( 31 /DDR_Banks/M1_A2 ) ( 32 /DDR_Banks/M1_A3 ) - ( 33 N-000047 ) + ( 33 +2.5V ) ( 34 GND ) - ( 35 /FPGA_Spartan6/M1_A4 ) - ( 36 /DDR_Banks/M1_A5 ) - ( 37 /DDR_Banks/M1_A6 ) + ( 35 /DDR_Banks/M1_A4 ) + ( 36 /FPGA_Spartan6/M1_A5 ) + ( 37 /FPGA_Spartan6/M1_A6 ) ( 38 /DDR_Banks/M1_A7 ) - ( 39 /FPGA_Spartan6/M1_A8 ) - ( 40 /FPGA_Spartan6/M1_A9 ) - ( 41 /FPGA_Spartan6/M1_A11 ) - ( 42 /DDR_Banks/M1_A12 ) + ( 39 /DDR_Banks/M1_A8 ) + ( 40 /DDR_Banks/M1_A9 ) + ( 41 /DDR_Banks/M1_A11 ) + ( 42 /FPGA_Spartan6/M1_A12 ) ( 43 ? ) - ( 44 /FPGA_Spartan6/M1_CLK# ) + ( 44 /DDR_Banks/M1_CLK# ) ( 45 /FPGA_Spartan6/M1_CKE ) - ( 46 /FPGA_Spartan6/M1_CLK ) + ( 46 /DDR_Banks/M1_CLK ) ( 47 /DDR_Banks/M1_UDM ) ( 48 GND ) - ( 49 ? ) + ( 49 N-000041 ) ( 50 ? ) - ( 51 /FPGA_Spartan6/M1_UDQS ) + ( 51 /DDR_Banks/M1_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M1_DQ8 ) - ( 55 N-000047 ) + ( 54 /FPGA_Spartan6/M1_DQ8 ) + ( 55 +2.5V ) ( 56 /FPGA_Spartan6/M1_DQ9 ) ( 57 /DDR_Banks/M1_DQ10 ) ( 58 GND ) ( 59 /DDR_Banks/M1_DQ11 ) ( 60 /FPGA_Spartan6/M1_DQ12 ) - ( 61 N-000047 ) + ( 61 +2.5V ) ( 62 /FPGA_Spartan6/M1_DQ13 ) - ( 63 /DDR_Banks/M1_DQ14 ) + ( 63 /FPGA_Spartan6/M1_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M1_DQ15 ) + ( 65 /FPGA_Spartan6/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} - ( 1 N-000054 ) + ( 1 +2.5V ) ( 2 /FPGA_Spartan6/M0_DQ0 ) - ( 3 N-000054 ) + ( 3 +2.5V ) ( 4 /FPGA_Spartan6/M0_DQ1 ) - ( 5 /FPGA_Spartan6/M0_DQ2 ) + ( 5 /DDR_Banks/M0_DQ2 ) ( 6 GND ) ( 7 /DDR_Banks/M0_DQ3 ) - ( 8 /FPGA_Spartan6/M0_DQ4 ) - ( 9 N-000054 ) + ( 8 /DDR_Banks/M0_DQ4 ) + ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M0_DQ5 ) ( 11 /FPGA_Spartan6/M0_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Spartan6/M0_DQ7 ) + ( 13 /DDR_Banks/M0_DQ7 ) ( 14 ? ) - ( 15 N-000054 ) + ( 15 +2.5V ) ( 16 /DDR_Banks/M0_LDQS ) ( 17 ? ) - ( 18 N-000054 ) + ( 18 +2.5V ) ( 19 ? ) - ( 20 /DDR_Banks/M0_LDM ) - ( 21 /FPGA_Spartan6/M0_WE# ) + ( 20 /FPGA_Spartan6/M0_LDM ) + ( 21 /DDR_Banks/M0_WE# ) ( 22 /DDR_Banks/M0_CAS# ) - ( 23 /DDR_Banks/M0_RAS# ) + ( 23 /FPGA_Spartan6/M0_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 /DDR_Banks/M0_A10 ) + ( 26 /FPGA_Spartan6/M0_BA0 ) + ( 27 /FPGA_Spartan6/M0_BA1 ) + ( 28 /FPGA_Spartan6/M0_A10 ) ( 29 /FPGA_Spartan6/M0_A0 ) - ( 30 /DDR_Banks/M0_A1 ) - ( 31 /FPGA_Spartan6/M0_A2 ) - ( 32 /FPGA_Spartan6/M0_A3 ) - ( 33 N-000054 ) + ( 30 /FPGA_Spartan6/M0_A1 ) + ( 31 /DDR_Banks/M0_A2 ) + ( 32 /DDR_Banks/M0_A3 ) + ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M0_A4 ) - ( 36 /FPGA_Spartan6/M0_A5 ) + ( 36 /DDR_Banks/M0_A5 ) ( 37 /DDR_Banks/M0_A6 ) ( 38 /DDR_Banks/M0_A7 ) ( 39 /FPGA_Spartan6/M0_A8 ) - ( 40 /FPGA_Spartan6/M0_A9 ) + ( 40 /DDR_Banks/M0_A9 ) ( 41 /FPGA_Spartan6/M0_A11 ) - ( 42 /DDR_Banks/M0_A12 ) + ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) ( 44 /DDR_Banks/M0_CLK# ) - ( 45 /FPGA_Spartan6/M0_CKE ) - ( 46 /FPGA_Spartan6/M0_CLK ) + ( 45 /DDR_Banks/M0_CKE ) + ( 46 /DDR_Banks/M0_CLK ) ( 47 /FPGA_Spartan6/M0_UDM ) ( 48 GND ) - ( 49 ? ) + ( 49 N-000042 ) ( 50 ? ) ( 51 /DDR_Banks/M0_UDQS ) ( 52 GND ) ( 53 ? ) ( 54 /DDR_Banks/M0_DQ8 ) - ( 55 N-000054 ) - ( 56 /FPGA_Spartan6/M0_DQ9 ) - ( 57 /DDR_Banks/M0_DQ10 ) + ( 55 +2.5V ) + ( 56 /DDR_Banks/M0_DQ9 ) + ( 57 /FPGA_Spartan6/M0_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M0_DQ11 ) ( 60 /FPGA_Spartan6/M0_DQ12 ) - ( 61 N-000054 ) - ( 62 /FPGA_Spartan6/M0_DQ13 ) + ( 61 +2.5V ) + ( 62 /DDR_Banks/M0_DQ13 ) ( 63 /FPGA_Spartan6/M0_DQ14 ) ( 64 GND ) - ( 65 /FPGA_Spartan6/M0_DQ15 ) + ( 65 /DDR_Banks/M0_DQ15 ) ( 66 GND ) ) ) @@ -1041,54 +1129,243 @@ $component R7 SM0805 R?-* $endlist +$component C34 + SM* + C? + C1-1 +$endlist +$component C33 + SM* + C? + C1-1 +$endlist +$component C28 + SM* + C? + C1-1 +$endlist +$component C29 + SM* + C? + C1-1 +$endlist +$component C31 + SM* + C? + C1-1 +$endlist +$component C30 + SM* + C? + C1-1 +$endlist +$component C32 + SM* + C? + C1-1 +$endlist +$component C27 + SM* + C? + C1-1 +$endlist +$component C21 + SM* + C? + C1-1 +$endlist +$component C26 + SM* + C? + C1-1 +$endlist +$component C24 + SM* + C? + C1-1 +$endlist +$component C25 + SM* + C? + C1-1 +$endlist +$component C23 + SM* + C? + C1-1 +$endlist +$component C22 + SM* + C? + C1-1 +$endlist +$component R13 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R14 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R12 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R11 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C19 + SM* + C? + C1-1 +$endlist +$component C20 + SM* + C? + C1-1 +$endlist +$component C18 + SM* + C? + C1-1 +$endlist +$component C17 + SM* + C? + C1-1 +$endlist $endfootprintlist } { Pin List by Nets -Net 5 "/Ethernet Phy/ETH_INT" "ETH_INT" - U4 25 - U1 A5 -Net 6 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" +Net 1 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" U3 22 U1 H22 -Net 7 "/FPGA Spartan6/M1_CKE" "M1_CKE" - U1 D21 +Net 2 "/FPGA Spartan6/M1_CKE" "M1_CKE" U3 45 -Net 8 "/FPGA Spartan6/M1_CLK" "M1_CLK" - U1 H20 - U3 46 -Net 9 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" - U3 44 - U1 J19 -Net 10 "GND" "GND" - U3 58 - U2 6 - U2 66 + U1 D21 +Net 3 "/DDR Banks/M0_CKE" "M0_CKE" + U2 45 + U1 D2 +Net 4 "/DDR Banks/M0_CAS#" "M0_CAS#" + U1 K4 + U2 22 +Net 5 "/DDR Banks/M1_WE#" "M1_WE#" + U3 21 + U1 H19 +Net 6 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" + U1 H21 + U3 23 +Net 7 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" + U2 23 + U1 K5 +Net 8 "/DDR Banks/M0_WE#" "M0_WE#" + U1 F2 + U2 21 +Net 9 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" + U4 46 + U1 A10 +Net 10 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" + U4 15 + U1 C10 +Net 11 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" + U1 C9 + U4 16 +Net 12 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" + U4 14 + U1 C8 +Net 13 "/Ethernet Phy/ETH_RXER" "ETH_RXER" + U4 11 + U1 D9 +Net 14 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" + U1 A8 + U4 9 +Net 17 "/Ethernet Phy/ETH_RXC" "ETH_RXC" + U4 10 + U1 B10 +Net 23 "/Ethernet Phy/ETH_INT" "ETH_INT" + U1 A5 + U4 25 +Net 24 "/Ethernet Phy/ETH_MDC" "ETH_MDC" + U1 D6 + U4 2 +Net 25 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" + R1 1 + U4 1 + U1 C6 +Net 26 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" + U4 48 + U1 B6 +Net 27 "/DDR Banks/M1_LDM" "M1_LDM" + U3 20 + U1 L19 +Net 28 "/DDR Banks/M1_LDQS" "M1_LDQS" + U3 16 + U1 L20 +Net 29 "/DDR Banks/M1_UDM" "M1_UDM" + U3 47 + U1 M20 +Net 30 "GND" "GND" U2 48 - U2 58 + U2 66 + U2 6 + U2 52 + U2 12 J1 COM J1 CASE J1 CASE J1 CASE - U5 13 - U5 36 - U2 12 - U2 52 - U2 24 - U2 34 + U3 12 U2 64 + U2 34 + U2 24 + U2 58 + U3 58 + U3 52 + U3 6 + U3 24 U3 48 + U3 66 + U3 34 + U3 64 + U5 36 + U5 13 + C8 2 + C7 2 + C5 2 + C3 2 + C1 2 + R2 2 + C11 2 + C10 2 + C2 2 + U1 N13 + U1 L13 + U1 J13 + U1 AB1 + U1 M12 + U1 P12 + U1 A22 + U1 B13 U4 35 + U4 44 + U4 23 U4 36 U4 39 + C12 2 + R9 2 + U4 8 U4 12 - U4 23 - U4 44 - J4 5 J4 4 - C2 2 - C16 2 - V1 2 - V2 2 + J4 5 J5 4 C15 2 C14 2 @@ -1096,506 +1373,553 @@ Net 10 "GND" "GND" U6 7 U6 8 R10 2 - R2 2 - C11 2 - C10 2 - C12 2 - R9 2 - U4 8 - C1 2 - C3 2 - C5 2 - C7 2 - C8 2 - U1 B13 - U1 J13 - U1 L13 - U1 N13 - U1 K14 - U1 J21 - U1 N21 - U1 U21 - U1 AB1 - U1 M12 - U1 P12 - U1 A22 - U1 W16 - U1 R5 - U1 E7 - U1 H7 - U1 U7 - U1 W7 - U1 A1 - U1 E2 - U1 J2 - U1 M10 - U1 P10 - U1 V10 - U1 J11 - U1 L11 - U1 N11 - U1 E21 - U1 B9 - U1 J9 - U1 L9 - U1 N9 - U1 K10 - U1 B17 - U1 N17 - U1 D18 - U1 G18 - U1 L18 + C16 2 + V1 2 + V2 2 U1 R18 - U1 W19 - U1 AA9 - U1 AB22 - U1 AA13 - U1 AA17 - U1 M14 - U1 P14 - U1 V14 - U1 E15 - U1 J15 + U1 L18 + U1 G18 + U1 D18 + U1 N17 + U1 B17 + U1 W16 U1 AA5 - U1 N2 - U1 U2 - U1 D4 - U1 V4 - U1 B5 - U1 G5 + U1 J15 + U1 E15 + U1 V14 + U1 P14 + U1 U21 + U1 N21 + U1 J21 + U1 E21 + U1 N11 + U1 L11 + U1 J11 + U1 V10 + U1 P10 + U1 M10 + U1 K10 + U1 N9 + U1 L9 + U1 M14 + U1 K14 + U1 J9 + U1 B9 + U1 W7 + U1 U7 + U1 H7 + U1 E7 + U1 R5 U1 L5 - U3 24 - U3 34 - U3 64 - U3 66 - U3 6 - U3 12 - U3 52 -Net 11 "/DDR Banks/M0_CLK#" "M0_CLK#" - U1 H3 - U2 44 -Net 12 "/FPGA Spartan6/M0_CLK" "M0_CLK" - U2 46 - U1 H4 -Net 13 "/FPGA Spartan6/M0_CKE" "M0_CKE" - U2 45 - U1 D2 -Net 14 "/DDR Banks/M0_CAS#" "M0_CAS#" - U1 K4 - U2 22 -Net 15 "/DDR Banks/M1_WE#" "M1_WE#" - U3 21 - U1 H19 -Net 16 "/DDR Banks/M0_RAS#" "M0_RAS#" - U1 K5 - U2 23 -Net 17 "/FPGA Spartan6/M0_WE#" "M0_WE#" - U1 F2 - U2 21 -Net 18 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" - U1 H21 - U3 23 -Net 26 "/FPGA Spartan6/M1_LDM" "M1_LDM" - U1 L19 - U3 20 -Net 27 "/DDR Banks/M1_LDQS" "M1_LDQS" - U1 L20 - U3 16 -Net 28 "/DDR Banks/M1_UDM" "M1_UDM" - U1 M20 - U3 47 -Net 29 "/FPGA Spartan6/M0_UDM" "M0_UDM" - U1 M3 + U1 G5 + U1 B5 + U1 V4 + U1 D4 + U1 U2 + U1 N2 + U1 J2 + U1 E2 + U1 A1 + U1 AA17 + U1 AA13 + U1 AB22 + U1 AA9 + U1 W19 + C32 2 + C27 2 + C28 2 + C29 2 + C22 2 + C23 2 + C34 2 + C25 2 + C24 2 + C26 2 + C31 2 + C30 2 + C33 2 + C21 2 +Net 31 "/FPGA Spartan6/M0_UDM" "M0_UDM" U2 47 -Net 30 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" + U1 M3 +Net 32 "/DDR Banks/M1_UDQS" "M1_UDQS" U3 51 U1 T21 -Net 31 "/DDR Banks/M0_UDQS" "M0_UDQS" - U1 T2 +Net 33 "/DDR Banks/M0_UDQS" "M0_UDQS" U2 51 -Net 32 "/DDR Banks/M0_LDM" "M0_LDM" + U1 T2 +Net 34 "/FPGA Spartan6/M0_LDM" "M0_LDM" U1 L4 U2 20 -Net 33 "/DDR Banks/M0_LDQS" "M0_LDQS" +Net 35 "/DDR Banks/M0_LDQS" "M0_LDQS" U1 L3 U2 16 -Net 36 "/ETH_MDIO" "ETH_MDIO" - U4 1 - R1 1 -Net 47 "" "" - U3 9 - U3 55 - U3 15 - U3 1 - U3 3 - U3 61 +Net 36 "/DDR Banks/M1_CLK" "M1_CLK" + U1 H20 + U3 46 +Net 37 "/DDR Banks/M0_CLK#" "M0_CLK#" + U2 44 + U1 H3 +Net 38 "/DDR Banks/M0_CLK" "M0_CLK" + U2 46 + U1 H4 +Net 39 "/DDR Banks/M1_CLK#" "M1_CLK#" + U3 44 + U1 J19 +Net 40 "" "" + C20 2 + R14 2 +Net 41 "" "" + U3 49 + C20 1 + C19 2 + R14 1 + R13 2 +Net 42 "" "" + U2 49 + R11 2 + C17 2 + C18 1 + R12 1 +Net 43 "+2.5V" "+2.5V" + C29 1 + C22 1 + C30 1 + U2 55 U3 18 - U3 33 -Net 54 "" "" - U2 61 - U2 33 - U2 18 - U2 15 + C32 1 + U3 9 + C27 1 + C28 1 + C17 1 + U3 1 + C21 1 + U3 3 + U3 55 + U3 61 + R13 1 + R11 1 + C19 1 + C33 1 U2 3 U2 1 - U2 55 + U3 33 + U2 33 + C23 1 + C25 1 + C24 1 + U2 61 + C31 1 + C26 1 + C34 1 + U3 15 + U2 18 + U2 15 U2 9 -Net 117 "/Non volatile memories/FRB_N" "FRB_N" - U5 6 +Net 44 "" "" + C18 2 + R12 2 +Net 101 "/Non volatile memories/FRB_N" "FRB_N" U5 7 -Net 122 "3.3V" "3.3V" - C1 1 - C3 1 - U6 12 - C5 1 - U6 14 - R1 2 - J4 3 + U5 6 +Net 108 "3.3V" "3.3V" U4 7 - C14 1 - L2 1 - C15 1 - C10 1 - C11 1 - U5 12 - U5 19 - U5 37 - C13 1 - R3 1 - U4 24 - J4 6 J4 9 J4 11 - U6 1 - R5 1 - R6 1 + C14 1 + R3 1 R4 1 -Net 137 "" "" - U1 B4 - U1 B11 - U1 G10 - U1 B19 - U1 E17 - U1 E13 - U1 G14 - U1 E9 - U1 B15 - U1 B7 -Net 153 "" "" - U1 R2 - U1 L2 - U1 G2 - U1 C2 - U1 F4 - U1 N5 - U1 U5 - U1 F6 - U1 J5 - U1 L7 - U1 W2 -Net 154 "" "" - U1 AA19 - U1 AA11 - U1 AA15 - U1 AA7 - U1 AA3 - U1 T13 - U1 V12 - U1 V16 - U1 V8 - U1 W5 - U1 T9 -Net 155 "" "" - U1 U18 - U1 E19 + R6 1 + R5 1 + R1 2 + C15 1 + L2 1 + U5 19 + C5 1 + C13 1 + C3 1 + U6 14 + U5 37 + U6 12 + C11 1 + C10 1 + C1 1 + J4 6 + U4 24 + J4 3 + U5 12 + U6 1 +Net 119 "" "" + U1 J18 U1 L16 + U1 C21 + U1 G21 + U1 L21 U1 R21 U1 W21 - U1 L21 - U1 G21 - U1 C21 - U1 J18 U1 N18 -Net 156 "" "" - U1 K13 - U1 M13 - U1 P13 - U1 J14 - U1 J12 - U1 L12 - U1 N12 - U1 R14 + U1 E19 + U1 U18 +Net 120 "" "" + U1 B7 + U1 E9 + U1 B11 + U1 E13 + U1 G10 + U1 B4 + U1 G14 + U1 B15 + U1 B19 + U1 E17 +Net 121 "" "" + U1 V16 + U1 AA11 + U1 AA7 + U1 T9 + U1 V8 + U1 AA3 + U1 W5 + U1 T13 + U1 V12 + U1 AA19 + U1 AA15 +Net 122 "" "" + U1 J8 + U1 K9 U1 L14 - U1 N14 + U1 J14 + U1 P13 + U1 K11 + U1 M11 + U1 P11 + U1 N10 U1 L10 U1 J10 U1 P9 U1 M9 - U1 K9 - U1 J8 - U1 P11 - U1 M11 - U1 K11 - U1 N10 -Net 157 "" "" + U1 N14 + U1 R14 + U1 L12 + U1 N12 + U1 M13 + U1 K13 + U1 J12 +Net 123 "" "" + U1 G12 + U1 R10 + U1 F11 + U1 U11 U1 R12 - U1 D16 - U1 M15 - U1 H9 U1 N8 U1 L8 - U1 U11 - U1 K15 - U1 H15 - U1 F11 - U1 R10 U1 V6 U1 R6 - U1 G12 -Net 396 "" "" - R7 1 - J4 10 -Net 397 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - R7 2 + U1 H9 + U1 D16 + U1 M15 + U1 K15 + U1 H15 +Net 124 "" "" + U1 W2 + U1 F6 + U1 U5 + U1 N5 + U1 C2 + U1 J5 + U1 G2 + U1 L2 + U1 R2 + U1 F4 + U1 L7 +Net 365 "/Ethernet Phy/ETH_LED0" "ETH_LED0" U4 26 -Net 398 "" "" - U4 41 - R3 2 - J4 1 -Net 399 "" "" - J4 7 - R5 2 - U4 33 -Net 400 "" "" - C12 1 - R9 1 - J4 14 - J4 13 -Net 401 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" + R7 2 +Net 369 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" C2 1 U4 13 -Net 402 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - C9 1 - L3 2 +Net 370 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" U4 47 -Net 403 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - U4 38 - C7 1 - C8 1 - L2 2 -Net 404 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - R8 2 + L3 2 + C9 1 +Net 375 "" "" + R3 2 + J4 1 + U4 41 +Net 376 "" "" + U4 33 + J4 7 + R5 2 +Net 377 "/Ethernet Phy/ETH_LED1" "ETH_LED1" U4 27 -Net 405 "" "" - R8 1 + R8 2 +Net 378 "" "" J4 12 -Net 406 "" "" + R8 1 +Net 379 "" "" + R7 1 + J4 10 +Net 380 "" "" + J4 14 + J4 13 + C12 1 + R9 1 +Net 381 "" "" R2 1 U4 37 -Net 407 "" "" - R6 2 +Net 382 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + L1 2 + C6 1 + L3 1 + U4 31 +Net 383 "" "" + L1 1 + C4 1 +Net 384 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + L2 2 + C8 1 + U4 38 + C7 1 +Net 385 "" "" U4 32 J4 8 -Net 408 "" "" + R6 2 +Net 386 "" "" + U4 40 R4 2 J4 2 - U4 40 -Net 416 "" "" +Net 387 "" "" C4 2 C6 2 C9 2 -Net 417 "" "" - L1 1 - C4 1 -Net 418 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - L3 1 - C6 1 - U4 31 - L1 2 -Net 419 "" "" - J5 2 - V2 1 - V2 1 - U6 10 -Net 420 "" "" +Net 388 "" "" + F1 1 + J5 1 +Net 389 "" "" V1 1 V1 1 U6 11 J5 3 -Net 425 "" "" - J5 1 - F1 1 -Net 426 "" "" - J5 S1 - R10 1 +Net 394 "" "" C16 1 + J5 S1 J5 S2 J5 S3 J5 S4 -Net 438 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" - U1 N3 - U2 2 -Net 442 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" - U3 2 - U1 N20 -Net 443 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" - U3 4 - U1 N22 -Net 447 "/DDR Banks/M1_DQ5" "M1_DQ5" - U1 J22 - U3 10 -Net 448 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" - U3 11 - U1 K21 -Net 449 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" - U3 13 - U1 K22 -Net 450 "/DDR Banks/M1_DQ8" "M1_DQ8" - U1 P21 - U3 54 -Net 451 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" - U3 56 - U1 P22 -Net 452 "/DDR Banks/M1_DQ10" "M1_DQ10" - U1 R20 - U3 57 -Net 453 "/DDR Banks/M1_DQ15" "M1_DQ15" - U3 65 - U1 V22 -Net 454 "/DDR Banks/M1_DQ14" "M1_DQ14" - U3 63 - U1 V21 -Net 455 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" - U3 62 - U1 U22 -Net 456 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" - U1 U20 - U3 60 -Net 457 "/DDR Banks/M1_DQ11" "M1_DQ11" - U1 R22 - U3 59 -Net 458 "/FPGA Spartan6/M1_A0" "M1_A0" - U3 29 + R10 1 +Net 395 "" "" + U6 10 + J5 2 + V2 1 + V2 1 +Net 398 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" + U1 B8 + U4 6 +Net 399 "/FPGA Spartan6/ETH_RXD1" "ETH_RXD1" + U1 A7 + U4 5 +Net 400 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" + U1 C7 + U4 4 +Net 401 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" + U1 A6 + U4 3 +Net 402 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" + U1 A9 + U4 17 +Net 403 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" + U1 D7 + U4 18 +Net 404 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" + U4 19 + U1 D8 +Net 405 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" + U4 20 + U1 D10 +Net 406 "/FPGA Spartan6/M1_BA1" "M1_BA1" + U3 27 + U1 K17 +Net 407 "/FPGA Spartan6/M1_BA0" "M1_BA0" + U1 J17 + U3 26 +Net 408 "/FPGA Spartan6/M0_BA1" "M0_BA1" + U1 G1 + U2 27 +Net 409 "/FPGA Spartan6/M0_BA0" "M0_BA0" + U2 26 + U1 G3 +Net 410 "/FPGA Spartan6/M1_A0" "M1_A0" U1 F21 -Net 459 "/FPGA Spartan6/M1_A1" "M1_A1" + U3 29 +Net 411 "/FPGA Spartan6/M1_A1" "M1_A1" U3 30 U1 F22 -Net 460 "/FPGA Spartan6/M1_A2" "M1_A2" +Net 412 "/DDR Banks/M1_A2" "M1_A2" U1 E22 U3 31 -Net 461 "/DDR Banks/M1_A3" "M1_A3" +Net 413 "/DDR Banks/M1_A3" "M1_A3" U1 G20 U3 32 -Net 462 "/FPGA Spartan6/M1_A4" "M1_A4" - U1 F20 +Net 414 "/DDR Banks/M1_A4" "M1_A4" U3 35 -Net 463 "/DDR Banks/M1_A5" "M1_A5" + U1 F20 +Net 415 "/FPGA Spartan6/M1_A5" "M1_A5" U1 K20 U3 36 -Net 464 "/DDR Banks/M1_A6" "M1_A6" - U1 K19 +Net 416 "/FPGA Spartan6/M1_A6" "M1_A6" U3 37 -Net 465 "/DDR Banks/M1_A7" "M1_A7" - U1 E20 + U1 K19 +Net 417 "/DDR Banks/M1_A7" "M1_A7" U3 38 -Net 466 "/FPGA Spartan6/M1_A8" "M1_A8" + U1 E20 +Net 418 "/DDR Banks/M1_A8" "M1_A8" U3 39 U1 C20 -Net 467 "/FPGA Spartan6/M1_A9" "M1_A9" +Net 419 "/DDR Banks/M1_A9" "M1_A9" U1 C22 U3 40 -Net 468 "/FPGA Spartan6/M1_A10" "M1_A10" - U1 G19 +Net 420 "/DDR Banks/M1_A10" "M1_A10" U3 28 -Net 469 "/FPGA Spartan6/M1_A11" "M1_A11" + U1 G19 +Net 421 "/DDR Banks/M1_A11" "M1_A11" U1 F19 U3 41 -Net 470 "/DDR Banks/M1_A12" "M1_A12" - U3 42 +Net 422 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" + U1 V22 + U3 65 +Net 423 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" + U3 63 + U1 V21 +Net 424 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" + U1 U22 + U3 62 +Net 425 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" + U3 60 + U1 U20 +Net 426 "/DDR Banks/M1_DQ11" "M1_DQ11" + U3 59 + U1 R22 +Net 427 "/DDR Banks/M1_DQ10" "M1_DQ10" + U1 R20 + U3 57 +Net 428 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" + U1 P22 + U3 56 +Net 429 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" + U3 54 + U1 P21 +Net 430 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" + U3 13 + U1 K22 +Net 431 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" + U3 11 + U1 K21 +Net 432 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" + U3 10 + U1 J22 +Net 433 "/DDR Banks/M1_DQ4" "M1_DQ4" + U3 8 + U1 J20 +Net 434 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" + U3 7 + U1 M22 +Net 435 "/DDR Banks/M1_DQ2" "M1_DQ2" + U1 M21 + U3 5 +Net 436 "/DDR Banks/M1_DQ1" "M1_DQ1" + U1 N22 + U3 4 +Net 437 "/DDR Banks/M1_DQ0" "M1_DQ0" + U1 N20 + U3 2 +Net 438 "/FPGA Spartan6/M1_A12" "M1_A12" U1 D22 -Net 471 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" - U1 N1 - U2 4 -Net 472 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" - U1 M2 - U2 5 -Net 473 "/DDR Banks/M0_DQ3" "M0_DQ3" - U1 M1 - U2 7 -Net 474 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" - U1 J3 - U2 8 -Net 475 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" - U2 10 - U1 J1 -Net 476 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" - U2 11 - U1 K2 -Net 477 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" - U1 K1 - U2 13 -Net 478 "/DDR Banks/M0_DQ8" "M0_DQ8" - U1 P2 - U2 54 -Net 479 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" - U1 P1 - U2 56 -Net 480 "/DDR Banks/M0_DQ10" "M0_DQ10" - U2 57 - U1 R3 -Net 481 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" - U1 R1 - U2 59 -Net 482 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" - U2 60 - U1 U3 -Net 483 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" - U2 62 - U1 U1 -Net 484 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" + U3 42 +Net 439 "/DDR Banks/M0_DQ15" "M0_DQ15" + U2 65 + U1 V1 +Net 440 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" U2 63 U1 V2 -Net 485 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" - U1 V1 - U2 65 -Net 486 "/DDR Banks/M0_A12" "M0_A12" - U2 42 +Net 441 "/DDR Banks/M0_DQ13" "M0_DQ13" + U1 U1 + U2 62 +Net 442 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" + U1 U3 + U2 60 +Net 443 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" + U2 59 + U1 R1 +Net 444 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" + U1 R3 + U2 57 +Net 445 "/DDR Banks/M0_DQ9" "M0_DQ9" + U2 56 + U1 P1 +Net 446 "/DDR Banks/M0_DQ8" "M0_DQ8" + U1 P2 + U2 54 +Net 447 "/DDR Banks/M0_DQ7" "M0_DQ7" + U1 K1 + U2 13 +Net 448 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" + U1 K2 + U2 11 +Net 449 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" + U2 10 + U1 J1 +Net 450 "/DDR Banks/M0_DQ4" "M0_DQ4" + U2 8 + U1 J3 +Net 451 "/DDR Banks/M0_DQ3" "M0_DQ3" + U1 M1 + U2 7 +Net 452 "/DDR Banks/M0_DQ2" "M0_DQ2" + U2 5 + U1 M2 +Net 453 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" + U1 N1 + U2 4 +Net 454 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" + U2 2 + U1 N3 +Net 455 "/FPGA Spartan6/M0_A12" "M0_A12" U1 D1 -Net 487 "/FPGA Spartan6/M0_A11" "M0_A11" + U2 42 +Net 456 "/FPGA Spartan6/M0_A11" "M0_A11" U1 C1 U2 41 -Net 488 "/DDR Banks/M0_A10" "M0_A10" - U2 28 +Net 457 "/FPGA Spartan6/M0_A10" "M0_A10" U1 G4 -Net 489 "/FPGA Spartan6/M0_A9" "M0_A9" + U2 28 +Net 458 "/DDR Banks/M0_A9" "M0_A9" U2 40 U1 E1 -Net 490 "/FPGA Spartan6/M0_A8" "M0_A8" +Net 459 "/FPGA Spartan6/M0_A8" "M0_A8" U1 E3 U2 39 -Net 491 "/DDR Banks/M0_A7" "M0_A7" - U2 38 +Net 460 "/DDR Banks/M0_A7" "M0_A7" U1 H6 -Net 492 "/DDR Banks/M0_A6" "M0_A6" - U1 J4 + U2 38 +Net 461 "/DDR Banks/M0_A6" "M0_A6" U2 37 -Net 493 "/FPGA Spartan6/M0_A5" "M0_A5" - U2 36 + U1 J4 +Net 462 "/DDR Banks/M0_A5" "M0_A5" U1 K3 -Net 494 "/FPGA Spartan6/M0_A4" "M0_A4" - U2 35 + U2 36 +Net 463 "/FPGA Spartan6/M0_A4" "M0_A4" U1 F3 -Net 495 "/FPGA Spartan6/M0_A3" "M0_A3" + U2 35 +Net 464 "/DDR Banks/M0_A3" "M0_A3" U2 32 U1 K6 -Net 496 "/FPGA Spartan6/M0_A2" "M0_A2" - U1 H5 +Net 465 "/DDR Banks/M0_A2" "M0_A2" U2 31 -Net 497 "/DDR Banks/M0_A1" "M0_A1" + U1 H5 +Net 466 "/FPGA Spartan6/M0_A1" "M0_A1" U2 30 U1 H1 -Net 498 "/FPGA Spartan6/M0_A0" "M0_A0" - U1 H2 +Net 467 "/FPGA Spartan6/M0_A0" "M0_A0" U2 29 + U1 H2 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 8732c46..470452c 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,8 +1,17 @@ -update=Mon 09 Aug 2010 10:24:04 PM COT +update=Tue 10 Aug 2010 05:37:22 PM COT version=1 last_client=pcbnew [common] NetDir= +[general] +version=1 +RootSch= +BoardNm= +[cvpcb] +version=1 +NetIExt=net +[cvpcb/libraries] +EquName1=devcms [eeschema] version=1 LibDir= @@ -33,9 +42,9 @@ offY_E=0 RptD_X=0 RptD_Y=100 RptLab=1 -SimCmd= -UseNetN=0 LabSize=60 +PrintMonochrome=1 +ShowSheetReferenceAndTitleBlock=1 [eeschema/libraries] LibName1=power LibName2=../library/v0402mhs03 @@ -78,15 +87,7 @@ LibName38=opto LibName39=atmel LibName40=contrib LibName41=valves -[general] -version=1 -RootSch= -BoardNm= -[cvpcb] -version=1 -NetIExt=net -[cvpcb/libraries] -EquName1=devcms +LibName42=/stuff/devel/Qi/xue/kicad/library/pasives-connectors [pcbnew] version=1 PadDrlX=320 diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 822f7be..d0c82d9 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 09 Aug 2010 10:11:04 PM COT +EESchema Schematic File Version 2 date Tue 10 Aug 2010 05:37:13 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -40,6 +40,7 @@ LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves +LIBS:pasives-connectors LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END @@ -54,140 +55,104 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Wire Wire Line - 10650 5400 9300 5400 -Wire Wire Line - 10650 5200 9300 5200 -Wire Wire Line - 10650 5000 9300 5000 -Wire Wire Line - 9300 7800 10600 7800 -Wire Wire Line +Wire Bus Line + 10600 7200 9300 7200 +Wire Bus Line 9300 7600 10600 7600 Wire Wire Line - 9300 7400 10600 7400 -Wire Wire Line - 9300 7200 10600 7200 -Wire Wire Line - 10600 6900 9300 6900 -Wire Wire Line - 9300 6700 10600 6700 -Wire Wire Line - 9300 6500 10600 6500 -Wire Bus Line - 4700 3150 5950 3150 -Wire Wire Line - 4700 2800 5950 2800 -Wire Wire Line - 4700 3750 5950 3750 -Wire Wire Line - 4700 3900 5950 3900 -Wire Wire Line - 4700 4250 5950 4250 -Wire Wire Line - 4700 5950 5950 5950 -Wire Wire Line - 4700 6550 5950 6550 -Wire Bus Line - 4700 5250 5950 5250 -Wire Wire Line - 4700 6300 5950 6300 -Wire Wire Line - 4700 5700 5950 5700 -Wire Wire Line - 4700 5400 5950 5400 -Wire Bus Line - 4700 3050 5950 3050 -Wire Wire Line - 5950 4100 4700 4100 -Wire Wire Line - 4700 6150 5950 6150 -Wire Bus Line - 5950 5100 5950 5050 -Wire Bus Line - 5950 5050 4700 5050 -Wire Wire Line - 4700 6050 5950 6050 -Wire Wire Line - 4700 4000 5950 4000 -Wire Bus Line - 4700 5150 5950 5150 -Wire Wire Line - 4700 5800 5950 5800 -Wire Wire Line - 4700 5500 5950 5500 -Wire Wire Line - 4700 6400 5950 6400 -Wire Wire Line - 4700 4900 5950 4900 -Wire Wire Line - 4700 4350 5950 4350 -Wire Wire Line - 4700 4500 5950 4500 -Wire Wire Line - 4700 3650 5950 3650 -Wire Wire Line - 4700 3450 5950 3450 -Wire Wire Line - 4700 3350 5950 3350 -Wire Bus Line - 4700 2950 5950 2950 -Wire Wire Line - 9300 6350 10600 6350 -Wire Wire Line - 9300 6600 10600 6600 -Wire Wire Line - 9300 6800 10600 6800 -Wire Wire Line - 9300 7000 10600 7000 -Wire Wire Line - 9300 7300 10600 7300 -Wire Wire Line - 9300 7500 10600 7500 -Wire Wire Line - 9300 7700 10600 7700 -Wire Wire Line - 9300 7900 10600 7900 + 10650 5300 9300 5300 Wire Wire Line 10650 5100 9300 5100 Wire Wire Line - 10650 5300 9300 5300 -Text HLabel 9300 5400 0 60 BiDi ~ 0 -USBA_VM -Text HLabel 9300 5300 0 60 BiDi ~ 0 -USBA_VP -Text HLabel 9300 5200 0 60 BiDi ~ 0 -USBA_RCV -Text HLabel 9300 5100 0 60 BiDi ~ 0 -USBA_OE_N -Text HLabel 9300 5000 0 60 BiDi ~ 0 -USBA_SPD -Text HLabel 9300 6900 0 60 BiDi ~ 0 -ETH_MDIO -Text HLabel 9300 7500 0 60 BiDi ~ 0 -ETH_TXC -Text HLabel 9300 7900 0 60 Input ~ 0 -ETH_CLK -Text HLabel 9300 7800 0 60 Input ~ 0 -ETH_TXER -Text HLabel 9300 7700 0 60 Input ~ 0 -ETH_TXEN -Text HLabel 9300 7600 0 60 Input ~ 0 -ETH_TXD[0..3] -Text HLabel 9300 7000 0 60 Input ~ 0 -ETH_MDC -Text HLabel 9300 6600 0 60 Input ~ 0 -ETH_RESET_N -Text HLabel 9300 7400 0 60 Output ~ 0 -ETH_RXER -Text HLabel 9300 7300 0 60 Output ~ 0 -ETH_RXDV -Text HLabel 9300 7200 0 60 Output ~ 0 -ETH_RXD[0..3] -Text HLabel 9300 6800 0 60 Output ~ 0 -ETH_COL -Text HLabel 9300 6700 0 60 Output ~ 0 -ETH_CRS + 9300 7900 10600 7900 +Wire Wire Line + 9300 7700 10600 7700 +Wire Wire Line + 9300 7500 10600 7500 +Wire Wire Line + 9300 7300 10600 7300 +Wire Wire Line + 9300 7000 10600 7000 +Wire Wire Line + 9300 6800 10600 6800 +Wire Wire Line + 9300 6600 10600 6600 +Wire Wire Line + 9300 6350 10600 6350 +Wire Bus Line + 4700 2950 5950 2950 +Wire Wire Line + 4700 3350 5950 3350 +Wire Wire Line + 4700 3450 5950 3450 +Wire Wire Line + 4700 3650 5950 3650 +Wire Wire Line + 4700 4500 5950 4500 +Wire Wire Line + 4700 4350 5950 4350 +Wire Wire Line + 4700 4900 5950 4900 +Wire Wire Line + 4700 6400 5950 6400 +Wire Wire Line + 4700 5500 5950 5500 +Wire Wire Line + 4700 5800 5950 5800 +Wire Bus Line + 4700 5150 5950 5150 +Wire Wire Line + 4700 4000 5950 4000 +Wire Wire Line + 4700 6050 5950 6050 +Wire Bus Line + 4700 5050 5950 5050 +Wire Bus Line + 5950 5050 5950 5100 +Wire Wire Line + 4700 6150 5950 6150 +Wire Wire Line + 5950 4100 4700 4100 +Wire Bus Line + 4700 3050 5950 3050 +Wire Wire Line + 4700 5400 5950 5400 +Wire Wire Line + 4700 5700 5950 5700 +Wire Wire Line + 4700 6300 5950 6300 +Wire Bus Line + 4700 5250 5950 5250 +Wire Wire Line + 4700 6550 5950 6550 +Wire Wire Line + 4700 5950 5950 5950 +Wire Wire Line + 4700 4250 5950 4250 +Wire Wire Line + 4700 3900 5950 3900 +Wire Wire Line + 4700 3750 5950 3750 +Wire Wire Line + 4700 2800 5950 2800 +Wire Bus Line + 4700 3150 5950 3150 +Wire Wire Line + 9300 6500 10600 6500 +Wire Wire Line + 9300 6700 10600 6700 +Wire Wire Line + 10600 6900 9300 6900 +Wire Wire Line + 9300 7400 10600 7400 +Wire Wire Line + 9300 7800 10600 7800 +Wire Wire Line + 10650 5000 9300 5000 +Wire Wire Line + 10650 5200 9300 5200 +Wire Wire Line + 10650 5400 9300 5400 $Sheet S 5950 2700 3350 5800 U 4C431A63 @@ -197,32 +162,49 @@ F2 "M1_CLK" O L 5950 4000 60 F3 "M1_CLK#" O L 5950 4100 60 F4 "M0_CLK" O L 5950 6050 60 F5 "M0_CLK#" O L 5950 6150 60 -F6 "ETH_INT" I R 9300 6350 60 -F7 "M0_A[0..12]" O L 5950 5150 60 -F8 "M1_A[0..12]" O L 5950 3050 60 -F9 "M0_DQ[0..15]" B L 5950 5050 60 -F10 "M0_UDQS" O L 5950 5400 60 -F11 "M0_LDM" O L 5950 5800 60 -F12 "M0_LDQS" O L 5950 5500 60 -F13 "M0_UDM" O L 5950 5700 60 -F14 "M0_RAS#" O L 5950 6400 60 -F15 "M0_WE#" O L 5950 6550 60 -F16 "M0_CKE" O L 5950 5950 60 -F17 "M0_CAS#" O L 5950 6300 60 -F18 "M1_CAS#" O L 5950 4250 60 -F19 "M1_CKE" O L 5950 3900 60 -F20 "M0_CS#" O L 5950 4900 60 -F21 "M1_CS#" O L 5950 2800 60 -F22 "M1_WE#" O L 5950 4500 60 -F23 "M1_RAS#" O L 5950 4350 60 -F24 "M1_UDM" O L 5950 3650 60 -F25 "M1_LDQS" O L 5950 3450 60 -F26 "M1_LDM" O L 5950 3750 60 -F27 "M1_UDQS" O L 5950 3350 60 -F28 "M1_DQ[0..15]" B L 5950 2950 60 +F6 "M0_A[0..12]" O L 5950 5150 60 +F7 "M1_A[0..12]" O L 5950 3050 60 +F8 "M0_DQ[0..15]" B L 5950 5050 60 +F9 "M0_UDQS" O L 5950 5400 60 +F10 "M0_LDM" O L 5950 5800 60 +F11 "M0_LDQS" O L 5950 5500 60 +F12 "M0_UDM" O L 5950 5700 60 +F13 "M0_RAS#" O L 5950 6400 60 +F14 "M0_WE#" O L 5950 6550 60 +F15 "M0_CKE" O L 5950 5950 60 +F16 "M0_CAS#" O L 5950 6300 60 +F17 "M1_CAS#" O L 5950 4250 60 +F18 "M1_CKE" O L 5950 3900 60 +F19 "M0_CS#" O L 5950 4900 60 +F20 "M1_CS#" O L 5950 2800 60 +F21 "M1_WE#" O L 5950 4500 60 +F22 "M1_RAS#" O L 5950 4350 60 +F23 "M1_UDM" O L 5950 3650 60 +F24 "M1_LDQS" O L 5950 3450 60 +F25 "M1_LDM" O L 5950 3750 60 +F26 "M1_UDQS" O L 5950 3350 60 +F27 "M1_DQ[0..15]" B L 5950 2950 60 +F28 "M1_BA[0..1]" O L 5950 3150 60 +F29 "M0_BA[0..1]" O L 5950 5250 60 +F30 "USBA_VM" B R 9300 5400 60 +F31 "USBA_VP" B R 9300 5300 60 +F32 "USBA_RCV" B R 9300 5200 60 +F33 "USBA_OE_N" B R 9300 5100 60 +F34 "USBA_SPD" B R 9300 5000 60 +F35 "ETH_CLK" B R 9300 7900 60 +F36 "ETH_RXC" B R 9300 6500 60 +F37 "ETH_TXC" B R 9300 7500 60 +F38 "ETH_TXD[0..3]" O R 9300 7600 60 +F39 "ETH_TXEN" B R 9300 7700 60 +F40 "ETH_TXER" B R 9300 7800 60 +F41 "ETH_RXER" B R 9300 7400 60 +F42 "ETH_RXDV" B R 9300 7300 60 +F43 "ETH_RXD[0..3]" I R 9300 7200 60 +F44 "ETH_RESET_N" B R 9300 6600 60 +F45 "ETH_MDIO" B R 9300 6900 60 +F46 "ETH_MDC" B R 9300 7000 60 +F47 "ETH_INT" B R 9300 6350 60 $EndSheet -Text HLabel 9300 6500 0 60 Output ~ 0 -ETH_RXC Text HLabel 10650 5400 2 60 BiDi ~ 0 USBA_VM Text HLabel 10650 5300 2 60 BiDi ~ 0