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mirror of git://projects.qi-hardware.com/xue.git synced 2024-12-26 21:41:44 +02:00

Routing current sensors.

This commit is contained in:
Juan64Bits 2010-09-03 12:22:25 -05:00
parent 4402fb5f07
commit cb21a9a99f
14 changed files with 9126 additions and 8395 deletions

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 03 Sep 2010 10:34:12 AM COT
EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 03 Sep 2010 10:34:12 AM COT
EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 03 Sep 2010 10:34:12 AM COT
EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 03 Sep 2010 10:34:12 AM COT
EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 03 Sep 2010 10:34:12 AM COT
EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 03 Sep 2010 10:34:12 AM COT
EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
@ -59,16 +59,37 @@ Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text Notes 1550 4350 0 80 ~ 16
Labels problems!!
Connection ~ 7500 2950
Wire Wire Line
7300 2950 7500 2950
Connection ~ 7650 2700
Wire Wire Line
3050 1600 2600 1600
Wire Wire Line
3050 1600 3050 3900
Wire Wire Line
3050 3900 6900 3900
Wire Wire Line
6900 3900 6900 5600
Wire Wire Line
6900 5600 7350 5600
Wire Wire Line
7350 5600 7350 6100
Wire Wire Line
7350 6100 8250 6100
Wire Wire Line
7750 5100 8250 5100
Connection ~ 1250 5600
Wire Wire Line
1250 5650 1250 5600
Wire Wire Line
6050 3050 6050 3100
Wire Wire Line
2200 1100 2200 1600
Wire Wire Line
4450 750 4850 750
Wire Wire Line
7750 5100 8250 5100
Wire Wire Line
8250 6100 7750 6100
Wire Wire Line
6050 3050 6050 3100
Wire Wire Line
2550 1000 2850 1000
Wire Wire Line
@ -175,8 +196,6 @@ Connection ~ 6200 5950
Connection ~ 6200 5400
Wire Wire Line
8650 2200 8850 2200
Wire Wire Line
7300 2950 7350 2950
Wire Wire Line
6050 3650 6050 3600
Wire Wire Line
@ -188,10 +207,6 @@ Wire Wire Line
7500 3650 7500 3450
Wire Wire Line
7500 2700 7500 3250
Connection ~ 7500 2700
Wire Wire Line
7350 2950 7350 2700
Connection ~ 7350 2700
Wire Wire Line
7300 3050 7300 3650
Wire Wire Line
@ -371,12 +386,10 @@ Wire Wire Line
Connection ~ 10200 2700
Wire Wire Line
7650 2700 7650 3050
Connection ~ 7650 2700
Wire Wire Line
8150 3050 8250 3050
Wire Wire Line
7850 2700 7850 2200
Connection ~ 7850 2700
Wire Wire Line
7850 2200 8050 2200
Wire Wire Line
@ -410,13 +423,9 @@ Connection ~ 1400 5250
Wire Wire Line
1400 5250 1400 5500
Wire Wire Line
1400 5650 1400 5600
Wire Wire Line
1400 6200 1400 6150
1250 6200 1250 6150
Wire Wire Line
2550 5500 2500 5500
Wire Wire Line
1400 5600 1000 5600
Wire Wire Line
2700 6200 2700 5850
Wire Wire Line
@ -433,8 +442,6 @@ Wire Wire Line
Connection ~ 2350 750
Wire Wire Line
2850 1000 2850 850
Wire Wire Line
2600 1600 3000 1600
Wire Wire Line
8200 3050 8200 3500
Wire Wire Line
@ -461,13 +468,6 @@ Connection ~ 950 1100
Wire Wire Line
2600 1100 2550 1100
Connection ~ 2550 1100
Wire Wire Line
5800 3050 6200 3050
Connection ~ 6050 3050
Wire Wire Line
7000 2700 8250 2700
Wire Wire Line
8250 5200 7750 5200
Wire Wire Line
3850 750 3800 750
Wire Wire Line
@ -478,6 +478,25 @@ Connection ~ 4500 750
Wire Wire Line
2200 1600 2300 1600
Connection ~ 2300 1600
Wire Wire Line
5800 3050 6200 3050
Connection ~ 6050 3050
Wire Wire Line
1000 5600 1400 5600
Wire Wire Line
8250 5200 6700 5200
Wire Wire Line
6700 5200 6700 5000
Wire Wire Line
6700 5000 850 5000
Wire Wire Line
850 5000 850 5600
Wire Wire Line
850 5600 1250 5600
Connection ~ 7500 2700
Wire Wire Line
8250 2700 7000 2700
Connection ~ 7850 2700
Text Label 7200 5500 0 50 ~ 10
WATCHDOG
$Comp
@ -651,23 +670,23 @@ $EndComp
$Comp
L R R44
U 1 1 4C7D02E1
P 1400 5900
F 0 "R44" V 1480 5900 50 0000 C CNN
F 1 "R" V 1400 5900 50 0000 C CNN
F 2 "0402" H 1400 5900 60 0001 C CNN
1 1400 5900
P 1250 5900
F 0 "R44" V 1330 5900 50 0000 C CNN
F 1 "R" V 1250 5900 50 0000 C CNN
F 2 "0402" H 1250 5900 60 0001 C CNN
1 1250 5900
1 0 0 -1
$EndComp
$Comp
L GND #PWR028
U 1 1 4C7D02E0
P 1400 6200
F 0 "#PWR028" H 1400 6200 30 0001 C CNN
F 1 "GND" H 1400 6130 30 0001 C CNN
1 1400 6200
P 1250 6200
F 0 "#PWR028" H 1250 6200 30 0001 C CNN
F 1 "GND" H 1250 6130 30 0001 C CNN
1 1250 6200
1 0 0 -1
$EndComp
Text Label 2350 5250 0 30 ~ 0
Text Label 2350 5200 0 30 ~ 0
VIN_DC-DC-2.5
Text Label 7750 5100 0 60 ~ 12
Iout_5.0
@ -835,7 +854,7 @@ F 2 "0805" H 7500 3350 60 0001 C CNN
1 7500 3350
1 0 0 -1
$EndComp
Text Label 7150 2700 0 30 ~ 0
Text Label 7250 2550 0 30 ~ 0
VIN_DC-DC-5.0
$Comp
L GND #PWR035
@ -1104,9 +1123,9 @@ Text Label 3800 750 0 30 ~ 0
SW_3.3
Text Label 9100 750 0 30 ~ 0
SW_1.2
Text Label 2100 750 0 30 ~ 0
Text Label 2100 700 0 30 ~ 0
VIN_DC-DC-3.3
Text Label 7250 750 0 30 ~ 0
Text Label 7250 700 0 30 ~ 0
VIN_DC-DC-1.2
Text Label 9150 950 0 30 ~ 0
VFB1.2

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 03 Sep 2010 10:34:12 AM COT
EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 03 Sep 2010 10:34:12 AM COT
EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03

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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3 Date: Fri 03 Sep 2010 10:34:12 AM COT
EESchema-LIBRARY Version 2.3 Date: Fri 03 Sep 2010 12:20:25 PM COT
#
# +1.2V
#

File diff suppressed because it is too large Load Diff

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@ -1,4 +1,4 @@
Cmp-Mod V01 Created by CvPCB (2010-08-29 BZR 2460)-unstable date = Thu 02 Sep 2010 11:54:52 AM COT
Cmp-Mod V01 Created by CvPCB (2010-08-29 BZR 2460)-unstable date = Fri 03 Sep 2010 10:58:24 AM COT
BeginCmp
TimeStamp = /4C4320F3/4C5D7F9F;
@ -816,7 +816,7 @@ BeginCmp
TimeStamp = /4C69ED5F/4C7FD562;
Reference = P1;
ValeurCmp = AVR/PROG;
IdModule = pin_array_4x2;
IdModule = PIN_ARRAY_5x1;
EndCmp
BeginCmp

File diff suppressed because it is too large Load Diff

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@ -1,6 +1,6 @@
update=Thu 02 Sep 2010 06:11:47 PM COT
update=Fri 03 Sep 2010 12:20:20 PM COT
version=1
last_client=pcbnew
last_client=kicad
[common]
NetDir=
[eeschema]
@ -88,8 +88,6 @@ version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[general]
version=1
[pcbnew]
version=1
PadDrlX=360
@ -142,3 +140,5 @@ LibName29=../modules/DFN10
LibName30=../modules/MLF16
LibName31=../modules/USBD
LibName32=../modules/MLP6
[general]
version=1

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@ -1,4 +1,4 @@
EESchema Schematic File Version 2 date Fri 03 Sep 2010 10:34:12 AM COT
EESchema Schematic File Version 2 date Fri 03 Sep 2010 12:20:25 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03