From cf1645bb442041e059b1a8bc746340dd8c4260ff Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Mon, 16 Aug 2010 22:48:30 -0500 Subject: [PATCH] DDR0 termaintor placement --- kicad/xue-rnc/DRAM.sch | 2 +- kicad/xue-rnc/FPGA.sch | 2680 ++++++++++++++++--------------- kicad/xue-rnc/NV_MEMORIES.sch | 2 +- kicad/xue-rnc/PSU.sch | 2 +- kicad/xue-rnc/USB.sch | 2 +- kicad/xue-rnc/eth_phy.sch | 2 +- kicad/xue-rnc/xue-rnc-cache.lib | 2 +- kicad/xue-rnc/xue-rnc.brd | 2148 ++++++++++++++----------- kicad/xue-rnc/xue-rnc.cmp | 44 +- kicad/xue-rnc/xue-rnc.net | 1772 ++++++++++---------- kicad/xue-rnc/xue-rnc.pro | 2 +- kicad/xue-rnc/xue-rnc.sch | 2 +- 12 files changed, 3655 insertions(+), 3005 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 2f22d7b..4335db3 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 5cfbdef..70546b8 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -48,7 +48,7 @@ LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A2 23400 16535 -Sheet 4 7 +Sheet 5 7 Title "" Date "17 aug 2010" Rev "" @@ -58,1236 +58,1404 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Wire Line + 6000 5500 5450 5500 +Wire Wire Line + 6000 5400 5450 5400 +Wire Wire Line + 6000 5200 5450 5200 +Wire Wire Line + 6000 4800 5450 4800 +Wire Wire Line + 6000 4600 5450 4600 +Wire Wire Line + 6000 4500 5450 4500 +Wire Wire Line + 6000 4200 5450 4200 +Wire Wire Line + 6000 3800 5400 3800 +Wire Wire Line + 6000 3600 5400 3600 Wire Bus Line - 12400 800 12450 800 -Wire Wire Line - 17150 2400 17600 2400 -Wire Wire Line - 15750 3950 15800 3950 -Wire Wire Line - 16300 3650 16900 3650 -Wire Wire Line - 15750 3650 15800 3650 -Wire Wire Line - 22550 3700 22000 3700 -Wire Wire Line - 22000 3400 22550 3400 -Wire Wire Line - 22550 3300 22000 3300 -Wire Wire Line - 16250 1700 16700 1700 -Wire Wire Line - 16700 1900 16250 1900 -Wire Wire Line - 16700 2000 16250 2000 -Wire Wire Line - 16700 1800 16250 1800 -Wire Wire Line - 15850 1800 15400 1800 -Wire Wire Line - 15850 2000 15400 2000 -Wire Wire Line - 15850 1900 15400 1900 -Wire Wire Line - 15400 1700 15850 1700 -Wire Wire Line - 22000 4400 22500 4400 -Wire Wire Line - 22000 4200 22500 4200 -Wire Wire Line - 22000 4700 22500 4700 -Wire Wire Line - 22000 4800 22500 4800 -Wire Wire Line - 22000 4900 22500 4900 -Wire Wire Line - 22000 5000 22500 5000 -Wire Wire Line - 22000 5100 22500 5100 -Wire Wire Line - 22500 4000 22000 4000 -Wire Wire Line - 22550 3800 22000 3800 -Wire Wire Line - 15400 1100 15850 1100 -Wire Wire Line - 15850 1300 15400 1300 -Wire Wire Line - 15850 1400 15400 1400 -Wire Wire Line - 15850 1200 15400 1200 -Wire Wire Line - 16700 1200 16250 1200 -Wire Wire Line - 16700 1400 16250 1400 -Wire Wire Line - 16700 1300 16250 1300 -Wire Wire Line - 16250 1100 16700 1100 -Wire Wire Line - 17600 4900 17150 4900 -Wire Wire Line - 17600 4600 17150 4600 -Wire Wire Line - 16300 4400 16300 4300 -Wire Wire Line - 16200 4300 16900 4300 -Wire Wire Line - 16900 4300 16900 4400 -Wire Wire Line - 16900 4400 17600 4400 -Wire Wire Line - 17600 4200 17150 4200 -Wire Wire Line - 17600 3800 17150 3800 -Wire Wire Line - 14650 3750 15100 3750 -Wire Wire Line - 17600 3400 17150 3400 -Wire Wire Line - 17600 3200 17150 3200 -Wire Wire Line - 17600 2900 17150 2900 -Wire Wire Line - 14150 2550 14250 2550 -Wire Wire Line - 14150 2450 14250 2450 -Wire Wire Line - 16250 2250 16700 2250 -Wire Wire Line - 16700 2450 16250 2450 -Wire Wire Line - 16700 2550 16250 2550 -Wire Wire Line - 16700 2350 16250 2350 -Wire Wire Line - 15850 2350 15400 2350 -Wire Wire Line - 15850 2550 15400 2550 -Wire Wire Line - 15850 2450 15400 2450 -Wire Wire Line - 15400 2250 15850 2250 -Wire Wire Line - 16700 2950 16250 2950 -Wire Wire Line - 16700 3150 16250 3150 -Wire Wire Line - 16700 3050 16250 3050 -Wire Wire Line - 16250 2850 16700 2850 -Wire Wire Line - 15400 2850 15850 2850 -Wire Wire Line - 15850 3050 15400 3050 -Wire Wire Line - 15850 3150 15400 3150 -Wire Wire Line - 15850 2950 15400 2950 -Wire Wire Line - 17150 4000 17600 4000 -Wire Wire Line - 14650 2050 15150 2050 -Wire Wire Line - 17600 5100 17050 5100 -Wire Wire Line - 15150 2350 14650 2350 -Wire Wire Line - 15100 1850 14650 1850 -Wire Wire Line - 13950 1350 14250 1350 -Wire Wire Line - 13950 1250 14250 1250 -Wire Wire Line - 14650 1450 15100 1450 -Wire Wire Line - 14650 1250 15100 1250 -Wire Wire Line - 5300 6400 5300 6250 -Wire Wire Line - 15900 12400 15900 12500 -Wire Wire Line - 1650 7500 2250 7500 -Wire Wire Line - 1650 7600 2250 7600 -Wire Wire Line - 2700 7300 3300 7300 -Wire Wire Line - 2700 9100 3300 9100 -Wire Wire Line - 7300 6900 7900 6900 -Wire Wire Line - 18000 7750 17650 7750 -Wire Wire Line - 17650 7550 18000 7550 -Wire Wire Line - 17650 7350 18000 7350 -Wire Notes Line - 1350 12200 6750 12200 -Wire Notes Line - 1350 12200 1350 15000 -Wire Notes Line - 1350 15000 6750 15000 -Wire Notes Line - 6750 15000 6750 12200 -Connection ~ 6000 13400 -Wire Wire Line - 6350 13450 6350 13400 -Wire Wire Line - 6350 13400 4600 13400 -Connection ~ 5650 14350 -Wire Wire Line - 4600 14350 6000 14350 -Wire Wire Line - 6000 14350 6000 14400 -Connection ~ 3050 13950 -Wire Wire Line - 3050 13950 3050 13900 -Connection ~ 2350 13950 -Wire Wire Line - 2350 13950 2350 13900 -Wire Wire Line - 3700 13900 3700 13950 -Connection ~ 3050 13450 -Wire Wire Line - 3050 13450 3050 13500 -Connection ~ 2350 13450 -Wire Wire Line - 3700 13500 3700 13450 -Wire Wire Line - 3700 13450 1650 13450 -Connection ~ 1650 13450 -Connection ~ 2000 12900 -Wire Wire Line - 2000 12900 2000 12850 -Wire Wire Line - 2700 12850 2700 12900 -Wire Wire Line - 2700 12900 1650 12900 -Connection ~ 2000 12400 -Wire Wire Line - 2000 12400 2000 12450 -Wire Wire Line - 2700 12450 2700 12400 -Wire Wire Line - 2700 12400 1650 12400 + 12350 2300 12400 2300 Wire Bus Line - 18350 8750 18350 8050 + 12400 2300 12400 3800 Wire Wire Line - 14250 8550 14200 8550 -Wire Wire Line - 15000 9850 15000 10000 -Wire Bus Line - 18350 7050 18350 6750 -Wire Wire Line - 17650 7150 18250 7150 -Wire Wire Line - 17650 6950 18250 6950 -Wire Wire Line - 17650 6650 17800 6650 -Wire Bus Line - 10700 4300 10700 4200 -Wire Bus Line - 10700 4200 10850 4200 -Wire Wire Line - 1600 5950 1600 5700 -Wire Wire Line - 14200 8450 14250 8450 -Wire Wire Line - 14200 8250 14250 8250 -Wire Wire Line - 14250 8050 12950 8050 -Wire Wire Line - 14250 7850 12950 7850 -Wire Wire Line - 14200 7650 14250 7650 -Wire Wire Line - 14200 7450 14250 7450 -Wire Wire Line - 14250 7250 12950 7250 -Wire Wire Line - 14250 7050 12950 7050 -Wire Wire Line - 14200 6850 14250 6850 -Wire Wire Line - 14200 8750 14250 8750 -Wire Wire Line - 22000 1700 22100 1700 -Wire Wire Line - 22000 1500 22100 1500 -Wire Bus Line - 12850 7300 12850 6900 -Wire Wire Line - 22450 4100 22000 4100 -Wire Wire Line - 10550 4700 10200 4700 -Wire Wire Line - 10550 3400 10200 3400 -Wire Wire Line - 10500 5600 10200 5600 -Wire Wire Line - 10500 5400 10200 5400 -Wire Wire Line - 5600 5000 6000 5000 -Wire Wire Line - 1900 4700 1450 4700 -Wire Wire Line - 1900 4900 1450 4900 -Wire Wire Line - 1900 5000 1450 5000 -Wire Wire Line - 1900 4800 1450 4800 -Wire Wire Line - 1900 4400 1450 4400 -Wire Wire Line - 1900 4600 1450 4600 -Wire Wire Line - 1900 4500 1450 4500 -Wire Wire Line - 1900 4300 1450 4300 -Wire Wire Line - 1900 3700 1450 3700 -Wire Wire Line - 1900 3500 1450 3500 -Wire Wire Line - 1900 3600 1450 3600 -Wire Wire Line - 1900 3800 1450 3800 -Wire Wire Line - 1900 4000 1450 4000 -Wire Wire Line - 1900 4200 1450 4200 -Wire Wire Line - 1900 3900 1450 3900 -Wire Wire Line - 1900 4100 1450 4100 -Wire Wire Line - 6000 5200 5550 5200 -Wire Wire Line - 6000 5400 5550 5400 -Wire Wire Line - 6000 5300 5550 5300 -Wire Wire Line - 6000 5500 5550 5500 -Wire Wire Line - 6000 4900 5550 4900 -Wire Wire Line - 6000 4700 5550 4700 -Wire Wire Line - 6000 4600 5550 4600 -Wire Wire Line - 6000 4800 5550 4800 -Wire Wire Line - 6000 4400 5550 4400 -Wire Wire Line - 6000 4200 5550 4200 -Wire Wire Line - 6000 4300 5550 4300 -Wire Wire Line - 6000 4500 5550 4500 -Wire Wire Line - 6000 3900 5550 3900 -Wire Wire Line - 6000 3700 5550 3700 -Wire Wire Line - 10600 4600 10200 4600 -Wire Wire Line - 10600 5100 10200 5100 -Wire Wire Line - 10600 5200 10200 5200 -Wire Wire Line - 10600 4100 10200 4100 -Wire Wire Line - 10600 4300 10200 4300 -Wire Wire Line - 10600 4200 10200 4200 -Wire Wire Line - 10600 4400 10200 4400 -Wire Wire Line - 10600 4500 10200 4500 -Wire Wire Line - 10600 3300 10200 3300 -Wire Wire Line - 10600 3100 10200 3100 -Wire Wire Line - 10600 3500 10200 3500 -Wire Wire Line - 10600 3600 10200 3600 -Wire Wire Line - 10600 3800 10200 3800 -Wire Wire Line - 10600 5000 10200 5000 -Wire Wire Line - 10600 3700 10200 3700 -Wire Wire Line - 1950 2050 1550 2050 -Wire Wire Line - 1950 2150 1550 2150 -Wire Wire Line - 1950 2350 1550 2350 -Wire Wire Line - 1950 2550 1550 2550 -Wire Wire Line - 1950 1450 1550 1450 -Wire Wire Line - 1950 1550 1550 1550 -Wire Wire Line - 1950 1850 1550 1850 -Wire Wire Line - 1950 1750 1550 1750 -Wire Wire Line - 1950 2250 1550 2250 -Wire Wire Line - 1950 1650 1550 1650 -Wire Wire Line - 1950 1950 1550 1950 -Wire Wire Line - 1950 2450 1550 2450 -Wire Wire Line - 1950 2650 1550 2650 -Wire Bus Line - 1450 2550 1450 1300 -Wire Bus Line - 1450 1300 1050 1300 -Wire Bus Line - 12450 800 12450 2050 -Wire Wire Line - 17550 3500 17150 3500 -Connection ~ 5600 6350 -Wire Wire Line - 5600 6350 5600 6400 -Connection ~ 5400 6350 -Wire Wire Line - 5400 6350 5400 6400 -Connection ~ 5200 6350 -Wire Wire Line - 5200 6350 5200 6400 -Connection ~ 5000 6350 -Wire Wire Line - 5000 6350 5000 6400 -Wire Wire Line - 4800 6400 4800 6350 -Connection ~ 15950 6200 -Wire Wire Line - 15950 6200 15950 6250 -Connection ~ 15750 6200 -Wire Wire Line - 15750 6200 15750 6250 -Connection ~ 15550 6200 -Wire Wire Line - 15550 6200 15550 6250 -Connection ~ 16150 6200 -Wire Wire Line - 16150 6200 16150 6250 -Wire Wire Line - 16350 6250 16350 6200 -Wire Wire Line - 16350 6200 15450 6200 -Wire Wire Line - 15450 6200 15450 6250 -Connection ~ 20100 750 -Wire Wire Line - 20100 800 20100 750 -Connection ~ 19900 750 -Wire Wire Line - 19900 750 19900 800 -Connection ~ 19700 750 -Connection ~ 19500 750 -Wire Wire Line - 19500 750 19500 800 -Wire Wire Line - 20200 800 20200 750 -Wire Wire Line - 20200 750 19300 750 -Wire Wire Line - 19300 750 19300 800 -Connection ~ 7900 750 -Wire Wire Line - 7900 750 7900 800 -Connection ~ 7700 750 -Wire Wire Line - 7700 750 7700 800 -Connection ~ 8400 750 -Wire Wire Line - 8400 750 8400 800 -Connection ~ 8200 750 -Wire Wire Line - 8200 750 8200 800 -Wire Wire Line - 8600 800 8600 750 -Wire Wire Line - 8600 750 7600 750 -Wire Wire Line - 7600 750 7600 800 -Connection ~ 18700 12500 -Wire Wire Line - 18700 12500 18700 12400 -Connection ~ 18500 12500 -Wire Wire Line - 18500 12500 18500 12400 -Connection ~ 18300 12500 -Wire Wire Line - 18300 12500 18300 12400 -Connection ~ 18100 12500 -Wire Wire Line - 18100 12500 18100 12400 -Wire Wire Line - 18000 12500 18000 12400 -Connection ~ 17900 12500 -Connection ~ 17300 12500 -Wire Wire Line - 17300 12500 17300 12400 -Connection ~ 17100 12500 -Wire Wire Line - 17100 12500 17100 12400 -Connection ~ 16900 12500 -Wire Wire Line - 16900 12500 16900 12400 -Connection ~ 16700 12500 -Wire Wire Line - 16700 12500 16700 12400 -Connection ~ 16500 12500 -Wire Wire Line - 16500 12500 16500 12400 -Connection ~ 16300 12500 -Wire Wire Line - 16300 12500 16300 12400 -Connection ~ 16100 12500 -Wire Wire Line - 16100 12500 16100 12400 -Connection ~ 17400 12500 -Wire Wire Line - 17400 12500 17400 12400 -Connection ~ 17600 12500 -Wire Wire Line - 17600 12500 17600 12400 -Connection ~ 15800 12500 -Wire Wire Line - 15800 12500 15800 12400 -Connection ~ 15600 12500 -Wire Wire Line - 15600 12500 15600 12400 -Connection ~ 15400 12500 -Wire Wire Line - 15400 12500 15400 12400 -Connection ~ 15200 12500 -Wire Wire Line - 15200 12500 15200 12400 -Connection ~ 15900 12500 -Connection ~ 14900 12500 -Wire Wire Line - 14900 12500 14900 12400 -Connection ~ 14700 12500 -Wire Wire Line - 14700 12500 14700 12400 -Connection ~ 14500 12500 -Wire Wire Line - 14500 12500 14500 12400 -Connection ~ 14300 12500 -Wire Wire Line - 14300 12500 14300 12400 -Connection ~ 14100 12500 -Wire Wire Line - 14100 12500 14100 12400 -Connection ~ 13900 12500 -Wire Wire Line - 13900 12500 13900 12400 -Connection ~ 13700 12500 -Wire Wire Line - 13700 12500 13700 12400 -Connection ~ 13500 12500 -Wire Wire Line - 13500 12500 13500 12400 -Connection ~ 13300 12500 -Wire Wire Line - 13300 12500 13300 12400 -Wire Wire Line - 18900 12400 18900 12500 -Wire Wire Line - 18900 12500 13100 12500 -Wire Wire Line - 13100 12500 13100 12400 -Connection ~ 15300 9950 -Wire Wire Line - 15300 9950 15300 10000 -Connection ~ 15500 9950 -Wire Wire Line - 15500 10000 15500 9950 -Connection ~ 15000 9950 -Connection ~ 14800 9950 -Wire Wire Line - 14800 9950 14800 10000 -Connection ~ 14600 9950 -Wire Wire Line - 14600 9950 14600 10000 -Connection ~ 14400 9950 -Wire Wire Line - 14400 9950 14400 10000 -Connection ~ 17300 9950 -Wire Wire Line - 17300 9950 17300 10000 -Connection ~ 17100 9950 -Wire Wire Line - 17100 9950 17100 10000 -Connection ~ 16900 9950 -Wire Wire Line - 16900 9950 16900 10000 -Connection ~ 16700 9950 -Wire Wire Line - 16700 9950 16700 10000 -Connection ~ 16500 9950 -Connection ~ 16300 9950 -Wire Wire Line - 16300 9950 16300 10000 -Connection ~ 16100 9950 -Wire Wire Line - 16100 9950 16100 10000 -Connection ~ 15900 9950 -Wire Wire Line - 15900 9950 15900 10000 -Connection ~ 17500 9950 -Wire Wire Line - 17500 9950 17500 10000 -Wire Wire Line - 15600 10000 15600 9950 -Wire Wire Line - 15600 9950 14300 9950 -Wire Wire Line - 14300 9950 14300 10000 -Wire Wire Line - 15700 10000 15700 9950 -Wire Wire Line - 15700 9950 17600 9950 -Wire Wire Line - 17600 9950 17600 10000 -Wire Wire Line - 15800 9950 15800 10000 -Connection ~ 15800 9950 -Wire Wire Line - 16000 9950 16000 10000 -Connection ~ 16000 9950 -Wire Wire Line - 16200 9950 16200 10000 -Connection ~ 16200 9950 -Wire Wire Line - 16400 9950 16400 10000 -Connection ~ 16400 9950 -Wire Wire Line - 16600 9950 16600 10000 -Connection ~ 16600 9950 -Wire Wire Line - 16800 9950 16800 10000 -Connection ~ 16800 9950 -Wire Wire Line - 17000 9950 17000 10000 -Connection ~ 17000 9950 -Wire Wire Line - 17200 9950 17200 10000 -Connection ~ 17200 9950 -Wire Wire Line - 17400 9950 17400 10000 -Connection ~ 17400 9950 -Wire Wire Line - 14500 9950 14500 10000 -Connection ~ 14500 9950 -Wire Wire Line - 14700 9950 14700 10000 -Connection ~ 14700 9950 -Wire Wire Line - 14900 9950 14900 10000 -Connection ~ 14900 9950 -Wire Wire Line - 15100 9950 15100 10000 -Connection ~ 15100 9950 -Wire Wire Line - 15400 9950 15400 10000 -Connection ~ 15400 9950 -Wire Wire Line - 15200 9950 15200 10000 -Connection ~ 15200 9950 -Wire Wire Line - 13200 12400 13200 12500 -Connection ~ 13200 12500 -Wire Wire Line - 13400 12500 13400 12400 -Connection ~ 13400 12500 -Wire Wire Line - 13600 12500 13600 12400 -Connection ~ 13600 12500 -Wire Wire Line - 13800 12500 13800 12400 -Connection ~ 13800 12500 -Wire Wire Line - 14000 12500 14000 12400 -Connection ~ 14000 12500 -Wire Wire Line - 14200 12500 14200 12400 -Connection ~ 14200 12500 -Wire Wire Line - 14400 12500 14400 12400 -Connection ~ 14400 12500 -Wire Wire Line - 14600 12500 14600 12400 -Connection ~ 14600 12500 -Wire Wire Line - 14800 12500 14800 12400 -Connection ~ 14800 12500 -Wire Wire Line - 15000 12500 15000 12400 -Connection ~ 15000 12500 -Wire Wire Line - 15100 12500 15100 12400 -Connection ~ 15100 12500 -Wire Wire Line - 15300 12500 15300 12400 -Connection ~ 15300 12500 -Wire Wire Line - 15500 12500 15500 12400 -Connection ~ 15500 12500 -Wire Wire Line - 15700 12500 15700 12400 -Connection ~ 15700 12500 -Wire Wire Line - 17700 12500 17700 12400 -Connection ~ 17700 12500 -Wire Wire Line - 17500 12500 17500 12400 -Connection ~ 17500 12500 -Wire Wire Line - 16000 12500 16000 12400 -Connection ~ 16000 12500 -Wire Wire Line - 16200 12500 16200 12400 -Connection ~ 16200 12500 -Connection ~ 16400 12500 -Wire Wire Line - 16600 12500 16600 12400 -Connection ~ 16600 12500 -Wire Wire Line - 16800 12500 16800 12400 -Connection ~ 16800 12500 -Wire Wire Line - 17000 12500 17000 12400 -Connection ~ 17000 12500 -Wire Wire Line - 17200 12500 17200 12400 -Connection ~ 17200 12500 -Wire Wire Line - 17800 12500 17800 12400 -Connection ~ 17800 12500 -Connection ~ 18000 12500 -Wire Wire Line - 17900 12500 17900 12400 -Wire Wire Line - 18200 12500 18200 12400 -Connection ~ 18200 12500 -Wire Wire Line - 18400 12500 18400 12400 -Connection ~ 18400 12500 -Wire Wire Line - 18600 12500 18600 12400 -Connection ~ 18600 12500 -Wire Wire Line - 18800 12500 18800 12400 -Connection ~ 18800 12500 -Connection ~ 8100 750 -Wire Wire Line - 8100 800 8100 650 -Wire Wire Line - 8300 750 8300 800 -Connection ~ 8300 750 -Wire Wire Line - 8500 750 8500 800 -Connection ~ 8500 750 -Wire Wire Line - 7800 750 7800 800 -Connection ~ 7800 750 -Wire Wire Line - 8000 750 8000 800 -Connection ~ 8000 750 -Wire Wire Line - 19400 800 19400 750 -Connection ~ 19400 750 -Wire Wire Line - 19600 750 19600 800 -Connection ~ 19600 750 -Wire Wire Line - 19800 750 19800 800 -Connection ~ 19800 750 -Wire Wire Line - 20000 750 20000 800 -Connection ~ 20000 750 -Wire Wire Line - 19700 800 19700 650 -Wire Wire Line - 16250 6200 16250 6250 -Connection ~ 16250 6200 -Wire Wire Line - 16050 6200 16050 6250 -Connection ~ 16050 6200 -Wire Wire Line - 15650 6200 15650 6250 -Connection ~ 15650 6200 -Wire Wire Line - 15850 6200 15850 6250 -Connection ~ 15850 6200 -Wire Wire Line - 4800 6350 5800 6350 -Wire Wire Line - 5800 6350 5800 6400 -Wire Wire Line - 4900 6350 4900 6400 -Connection ~ 4900 6350 -Wire Wire Line - 5100 6350 5100 6400 -Connection ~ 5100 6350 -Connection ~ 5300 6350 -Wire Wire Line - 5500 6350 5500 6400 -Connection ~ 5500 6350 -Wire Wire Line - 5700 6400 5700 6350 -Connection ~ 5700 6350 -Wire Wire Line - 12950 2150 12550 2150 -Wire Wire Line - 12950 1950 12550 1950 -Wire Wire Line - 12950 1450 12550 1450 -Wire Wire Line - 12950 1150 12550 1150 -Wire Wire Line - 12950 1750 12550 1750 -Wire Wire Line - 12950 1250 12550 1250 -Wire Wire Line - 12950 1350 12550 1350 -Wire Wire Line - 12950 1050 12550 1050 -Wire Wire Line - 12950 950 12550 950 -Wire Wire Line - 12950 2050 12550 2050 -Wire Wire Line - 12950 1850 12550 1850 -Wire Wire Line - 12950 1650 12550 1650 -Wire Wire Line - 12950 1550 12550 1550 -Wire Wire Line - 6000 3600 5550 3600 -Wire Wire Line - 6000 3800 5550 3800 -Wire Bus Line - 1250 3300 1350 3300 -Wire Bus Line - 1350 3300 1350 4900 -Wire Wire Line - 5600 4000 6000 4000 -Wire Wire Line - 10200 5300 10500 5300 -Wire Wire Line - 10200 5500 10500 5500 -Wire Wire Line - 10550 4000 10200 4000 -Wire Wire Line - 10550 4800 10200 4800 -Wire Wire Line - 12950 3000 12500 3000 -Wire Wire Line - 12950 2800 12500 2800 -Wire Wire Line - 12950 3100 12500 3100 -Wire Wire Line - 12950 2900 12500 2900 -Wire Wire Line - 12950 2700 12500 2700 -Wire Wire Line - 12950 2500 12500 2500 -Wire Wire Line - 12950 2400 12500 2400 -Wire Wire Line - 12950 2600 12500 2600 -Wire Wire Line - 12950 3200 12500 3200 -Wire Wire Line - 12950 3400 12500 3400 -Wire Wire Line - 12950 3500 12500 3500 -Wire Wire Line - 12950 3300 12500 3300 -Wire Wire Line - 12950 3700 12500 3700 -Wire Wire Line - 12950 3900 12500 3900 -Wire Wire Line - 12950 3800 12500 3800 -Wire Wire Line - 12950 3600 12500 3600 -Wire Bus Line - 12850 6900 12750 6900 -Wire Bus Line - 12750 7700 12850 7700 -Wire Bus Line - 12850 7700 12850 8100 -Wire Wire Line - 22100 1400 22000 1400 -Wire Wire Line - 22000 1600 22100 1600 -Wire Wire Line - 22000 1800 22100 1800 -Wire Wire Line - 14200 6750 14250 6750 -Wire Wire Line - 14200 6950 14250 6950 -Wire Wire Line - 14250 7150 12950 7150 -Wire Wire Line - 14250 7350 12950 7350 -Wire Wire Line - 14200 7550 14250 7550 -Wire Wire Line - 14200 7750 14250 7750 -Wire Wire Line - 14250 7950 12950 7950 -Wire Wire Line - 14250 8150 12950 8150 -Wire Wire Line - 14200 8350 14250 8350 -Wire Wire Line - 1600 5700 1450 5700 -Wire Bus Line - 13750 1850 13750 1750 -Wire Bus Line - 13750 1750 13650 1750 -Wire Wire Line - 17650 6750 17800 6750 -Wire Wire Line - 18250 6850 17650 6850 -Wire Wire Line - 17650 7050 18250 7050 -Wire Bus Line - 18350 6750 18450 6750 -Wire Wire Line - 16500 9850 16500 10000 -Wire Wire Line - 15900 6200 15900 6100 -Connection ~ 15900 6200 -Wire Wire Line - 14250 8650 14200 8650 -Wire Wire Line - 17650 8350 18250 8350 -Wire Wire Line - 18250 8150 17650 8150 -Wire Wire Line - 17650 8250 18250 8250 -Wire Wire Line - 17650 8450 18250 8450 -Wire Wire Line - 17650 8850 18250 8850 -Wire Wire Line - 17650 8650 18250 8650 -Wire Wire Line - 18250 8550 17650 8550 -Wire Wire Line - 17650 8750 18250 8750 -Wire Bus Line - 18350 8050 18650 8050 -Wire Wire Line - 2350 12400 2350 12450 -Connection ~ 2350 12400 -Wire Wire Line - 1650 12350 1650 12450 -Connection ~ 1650 12400 -Wire Wire Line - 2350 12900 2350 12850 -Connection ~ 2350 12900 -Wire Wire Line - 1650 12950 1650 12850 -Connection ~ 1650 12900 -Wire Wire Line - 2000 13950 2000 13900 -Wire Wire Line - 2000 13500 2000 13450 -Wire Wire Line - 1650 13400 1650 13500 -Wire Wire Line - 1650 14000 1650 13900 -Wire Wire Line - 2350 13450 2350 13500 -Connection ~ 2000 13450 -Wire Wire Line - 3350 13450 3350 13500 -Connection ~ 3350 13450 -Wire Wire Line - 2700 13450 2700 13500 -Connection ~ 2700 13450 -Wire Wire Line - 3700 13950 1650 13950 -Connection ~ 2000 13950 -Connection ~ 1650 13950 -Wire Wire Line - 2700 13950 2700 13900 -Connection ~ 2700 13950 -Wire Wire Line - 3350 13950 3350 13900 -Connection ~ 3350 13950 -Connection ~ 2000 14850 -Wire Wire Line - 2000 14850 2000 14800 -Wire Wire Line - 2700 14800 2700 14850 -Wire Wire Line - 2700 14850 1650 14850 -Connection ~ 2000 14350 -Wire Wire Line - 2000 14350 2000 14400 -Wire Wire Line - 2700 14400 2700 14350 -Wire Wire Line - 2700 14350 1650 14350 -Wire Wire Line - 2350 14350 2350 14400 -Connection ~ 2350 14350 -Wire Wire Line - 1650 14300 1650 14400 -Connection ~ 1650 14350 -Wire Wire Line - 2350 14850 2350 14800 -Connection ~ 2350 14850 -Wire Wire Line - 1650 14900 1650 14800 -Connection ~ 1650 14850 -Connection ~ 4950 14850 -Wire Wire Line - 4950 14800 4950 14850 -Wire Wire Line - 5650 14850 5650 14800 -Connection ~ 4950 14350 -Wire Wire Line - 4950 14350 4950 14400 -Wire Wire Line - 5650 14400 5650 14350 -Wire Wire Line - 5300 14350 5300 14400 -Connection ~ 5300 14350 -Wire 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2250 2950 0 60 ~ 0 +M0_DQ0 +Text Label 2250 2850 0 60 ~ 0 +M0_DQ1 +Text Label 2250 2650 0 60 ~ 0 +M0_DQ3 +Text Label 2250 2750 0 60 ~ 0 +M0_DQ2 +Text Label 3100 2750 0 60 ~ 0 +R_M0_DQ2 +Text Label 3100 2650 0 60 ~ 0 +R_M0_DQ3 +Text Label 3100 2850 0 60 ~ 0 +R_M0_DQ1 +Text Label 3100 2950 0 60 ~ 0 +R_M0_DQ0 +Text Label 2250 2200 0 60 ~ 0 +M0_DQ6 +Text Label 2250 2100 0 60 ~ 0 +M0_DQ7 +Text Label 2250 2300 0 60 ~ 0 +M0_DQ5 +Text Label 2250 2400 0 60 ~ 0 +M0_DQ4 +Text Label 3100 2400 0 60 ~ 0 +R_M0_DQ4 +Text Label 3100 2300 0 60 ~ 0 +R_M0_DQ5 +Text Label 3100 2100 0 60 ~ 0 +R_M0_DQ7 +Text Label 3100 2200 0 60 ~ 0 +R_M0_DQ6 +$Comp +L R_PACK4 RP11 +U 1 1 4C69FCE6 +P 2900 1500 +F 0 "RP11" H 2900 1950 40 0000 C CNN +F 1 "R_PACK4" H 2900 1450 40 0000 C CNN +F 2 "R_PACK4-0402" H 2900 1500 60 0001 C CNN + 1 2900 1500 + -1 0 0 1 +$EndComp +Text Label 2250 1650 0 60 ~ 0 +M0_DQ10 +Text Label 2250 1550 0 60 ~ 0 +M0_DQ11 +Text Label 2250 1750 0 60 ~ 0 +M0_DQ9 +Text Label 2250 1850 0 60 ~ 0 +M0_DQ8 +Text Label 3100 1850 0 60 ~ 0 +R_M0_DQ8 +Text Label 3100 1750 0 60 ~ 0 +R_M0_DQ9 +Text Label 3100 1550 0 60 ~ 0 +R_M0_DQ11 +Text Label 3100 1650 0 60 ~ 0 +R_M0_DQ10 +Text Label 3100 1100 0 60 ~ 0 +R_M0_DQ14 +Text Label 3100 1000 0 60 ~ 0 +R_M0_DQ15 +Text Label 3100 1200 0 60 ~ 0 +R_M0_DQ13 +Text Label 3100 1300 0 60 ~ 0 +R_M0_DQ12 +Text Label 2250 1300 0 60 ~ 0 +M0_DQ12 +Text Label 2250 1200 0 60 ~ 0 +M0_DQ13 +Text Label 2250 1000 0 60 ~ 0 +M0_DQ15 +Text Label 2250 1100 0 60 ~ 0 +M0_DQ14 +$Comp +L R_PACK4 RP10 +U 1 1 4C69FC19 +P 2900 950 +F 0 "RP10" H 2900 1400 40 0000 C CNN +F 1 "R_PACK4" H 2900 900 40 0000 C CNN +F 2 "R_PACK4-0402" H 2900 950 60 0001 C CNN + 1 2900 950 + -1 0 0 1 +$EndComp Entry Wire Line 12400 2400 12500 2500 Entry Wire Line @@ -2413,38 +2581,38 @@ Text Label 1550 4200 0 60 ~ 0 M0_DQ7 Text Label 1550 4100 0 60 ~ 0 M0_DQ6 -Text Label 5550 5200 0 60 ~ 0 -M0_DQ6 -Text Label 5550 5300 0 60 ~ 0 -M0_DQ7 -Text Label 5550 5500 0 60 ~ 0 -M0_DQ5 -Text Label 5550 5400 0 60 ~ 0 -M0_DQ4 -Text Label 5550 4800 0 60 ~ 0 -M0_DQ2 -Text Label 5550 4900 0 60 ~ 0 -M0_DQ3 -Text Label 5550 4700 0 60 ~ 0 -M0_DQ1 -Text Label 5550 4600 0 60 ~ 0 -M0_DQ0 -Text Label 5550 4200 0 60 ~ 0 -M0_DQ10 -Text Label 5550 4300 0 60 ~ 0 -M0_DQ11 -Text Label 5550 4500 0 60 ~ 0 -M0_DQ9 -Text Label 5550 4400 0 60 ~ 0 -M0_DQ8 -Text Label 5550 3800 0 60 ~ 0 -M0_DQ12 -Text Label 5550 3900 0 60 ~ 0 -M0_DQ13 -Text Label 5550 3700 0 60 ~ 0 -M0_DQ15 -Text Label 5550 3600 0 60 ~ 0 -M0_DQ14 +Text Label 5450 5200 0 60 ~ 0 +R_M0_DQ6 +Text Label 5450 5300 0 60 ~ 0 +R_M0_DQ7 +Text Label 5450 5500 0 60 ~ 0 +R_M0_DQ5 +Text Label 5450 5400 0 60 ~ 0 +R_M0_DQ4 +Text Label 5450 4800 0 60 ~ 0 +R_M0_DQ2 +Text Label 5450 4900 0 60 ~ 0 +R_M0_DQ3 +Text Label 5450 4700 0 60 ~ 0 +R_M0_DQ1 +Text Label 5450 4600 0 60 ~ 0 +R_M0_DQ0 +Text Label 5450 4200 0 60 ~ 0 +R_M0_DQ10 +Text Label 5450 4300 0 60 ~ 0 +R_M0_DQ11 +Text Label 5450 4500 0 60 ~ 0 +R_M0_DQ9 +Text Label 5450 4400 0 60 ~ 0 +R_M0_DQ8 +Text Label 5400 3800 0 60 ~ 0 +R_M0_DQ12 +Text Label 5400 3900 0 60 ~ 0 +R_M0_DQ13 +Text Label 5400 3700 0 60 ~ 0 +R_M0_DQ15 +Text Label 5400 3600 0 60 ~ 0 +R_M0_DQ14 Text Label 10250 4600 0 60 ~ 0 M0_A0 Text Label 10250 5100 0 60 ~ 0 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 24ff1fc..9582c01 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index e01466a..553ca10 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 6d46284..ba7bcc0 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 8c2c111..5f7ac1d 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index fe316cd..1702d98 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Mon 16 Aug 2010 09:46:10 PM COT +EESchema-LIBRARY Version 2.3 Date: Mon 16 Aug 2010 10:43:45 PM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 7b81448..a86968f 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Mon 16 Aug 2010 09:47:05 PM COT +PCBNEW-BOARD Version 1 date Mon 16 Aug 2010 10:47:34 PM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -6,15 +6,15 @@ $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 1FFF801F -Links 595 -NoConn 595 +Links 611 +NoConn 611 Di 45200 13510 70149 50668 Ndraw 7 Ntrack 0 Nzone 0 BoardThickness 630 -Nmodule 129 -Nnets 207 +Nmodule 133 +Nnets 223 $EndGENERAL $SHEETDESCR @@ -90,319 +90,319 @@ Na 5 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A1" +Na 6 "/DDR_Banks/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_A11" +Na 7 "/DDR_Banks/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_A5" +Na 8 "/DDR_Banks/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_A7" +Na 9 "/DDR_Banks/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_BA0" +Na 10 "/DDR_Banks/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_BA1" +Na 11 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_CLK#" +Na 12 "/DDR_Banks/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_DQ13" +Na 13 "/DDR_Banks/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_DQ4" +Na 14 "/DDR_Banks/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_DQ5" +Na 15 "/DDR_Banks/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_DQ7" +Na 16 "/DDR_Banks/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_DQ9" +Na 17 "/DDR_Banks/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_LDQS" +Na 18 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_RAS#" +Na 19 "/DDR_Banks/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M0_UDM" +Na 20 "/DDR_Banks/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M0_UDQS" +Na 21 "/DDR_Banks/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M0_WE#" +Na 22 "/DDR_Banks/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_A3" +Na 23 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_A4" +Na 24 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_BA1" +Na 25 "/DDR_Banks/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_CLK" +Na 26 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_DQ10" +Na 27 "/DDR_Banks/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_DQ12" +Na 28 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_DQ14" +Na 29 "/DDR_Banks/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_DQ15" +Na 30 "/DDR_Banks/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_DQ6" +Na 31 "/DDR_Banks/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_DQ7" +Na 32 "/DDR_Banks/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_DQ9" +Na 33 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_LDM" +Na 34 "/DDR_Banks/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_LDQS" +Na 35 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/DDR_Banks/M1_RAS#" +Na 36 "/DDR_Banks/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/DDR_Banks/M1_UDQS" +Na 37 "/DDR_Banks/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M1_WE#" +Na 38 "/DDR_Banks/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/Ethernet_Phy/ETH_A1.8V" +Na 39 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Ethernet_Phy/ETH_A3.3V" +Na 40 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_CRS" +Na 41 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_INT" +Na 42 "/DDR_Banks/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_LED0" +Na 43 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_LED1" +Na 44 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_MDC" +Na 45 "/Ethernet_Phy/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_PLL1.8V" +Na 46 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_RXD1" +Na 47 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_RXD3" +Na 48 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_TXC" +Na 49 "/Ethernet_Phy/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/ETH_TXD2" +Na 50 "/Ethernet_Phy/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Ethernet_Phy/ETH_TXEN" +Na 51 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Spartan6/ETH_CLK" +Na 52 "/Ethernet_Phy/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Spartan6/ETH_COL" +Na 53 "/Ethernet_Phy/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Spartan6/ETH_MDIO" +Na 54 "/Ethernet_Phy/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Spartan6/ETH_RESET_N" +Na 55 "/Ethernet_Phy/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/ETH_RXC" +Na 56 "/Ethernet_Phy/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/ETH_RXD0" +Na 57 "/FPGA_Spartan6/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/ETH_RXD2" +Na 58 "/FPGA_Spartan6/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/ETH_RXDV" +Na 59 "/FPGA_Spartan6/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/ETH_RXER" +Na 60 "/FPGA_Spartan6/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/ETH_TXD0" +Na 61 "/FPGA_Spartan6/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/ETH_TXD1" +Na 62 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/ETH_TXD3" +Na 63 "/FPGA_Spartan6/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/ETH_TXER" +Na 64 "/FPGA_Spartan6/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/M0_A0" +Na 65 "/FPGA_Spartan6/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/M0_A10" +Na 66 "/FPGA_Spartan6/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/M0_A12" +Na 67 "/FPGA_Spartan6/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/M0_A2" +Na 68 "/FPGA_Spartan6/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_A3" +Na 69 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_A4" +Na 70 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_A6" +Na 71 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_A8" +Na 72 "/FPGA_Spartan6/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_A9" +Na 73 "/FPGA_Spartan6/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_CAS#" +Na 74 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_CKE" +Na 75 "/FPGA_Spartan6/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_CLK" +Na 76 "/FPGA_Spartan6/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_DQ0" +Na 77 "/FPGA_Spartan6/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_DQ1" +Na 78 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_DQ10" +Na 79 "/FPGA_Spartan6/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_DQ11" +Na 80 "/FPGA_Spartan6/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_DQ12" +Na 81 "/FPGA_Spartan6/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_DQ14" +Na 82 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_DQ15" +Na 83 "/FPGA_Spartan6/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_DQ2" +Na 84 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT @@ -410,11 +410,11 @@ Na 85 "/FPGA_Spartan6/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M0_DQ6" +Na 86 "/FPGA_Spartan6/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M0_DQ8" +Na 87 "/FPGA_Spartan6/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT @@ -422,43 +422,43 @@ Na 88 "/FPGA_Spartan6/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M1_A0" +Na 89 "/FPGA_Spartan6/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M1_A1" +Na 90 "/FPGA_Spartan6/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M1_A10" +Na 91 "/FPGA_Spartan6/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M1_A11" +Na 92 "/FPGA_Spartan6/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M1_A12" +Na 93 "/FPGA_Spartan6/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_A2" +Na 94 "/FPGA_Spartan6/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_A5" +Na 95 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_A6" +Na 96 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_A7" +Na 97 "/FPGA_Spartan6/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_A8" +Na 98 "/FPGA_Spartan6/M1_A6" St ~ $EndEQUIPOT $EQUIPOT @@ -466,63 +466,63 @@ Na 99 "/FPGA_Spartan6/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_BA0" +Na 100 "/FPGA_Spartan6/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_CAS#" +Na 101 "/FPGA_Spartan6/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_CKE" +Na 102 "/FPGA_Spartan6/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_CLK#" +Na 103 "/FPGA_Spartan6/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_CS#" +Na 104 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ0" +Na 105 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_DQ1" +Na 106 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_DQ11" +Na 107 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_DQ13" +Na 108 "/FPGA_Spartan6/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ2" +Na 109 "/FPGA_Spartan6/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_DQ3" +Na 110 "/FPGA_Spartan6/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_DQ4" +Na 111 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Spartan6/M1_DQ5" +Na 112 "/FPGA_Spartan6/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_DQ8" +Na 113 "/FPGA_Spartan6/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Spartan6/M1_UDM" +Na 114 "/FPGA_Spartan6/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT @@ -530,19 +530,19 @@ Na 115 "/FPGA_Spartan6/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/NF_D0" +Na 116 "/FPGA_Spartan6/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Spartan6/NF_D2" +Na 117 "/FPGA_Spartan6/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA_Spartan6/NF_D4" +Na 118 "/FPGA_Spartan6/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/NF_D6" +Na 119 "/FPGA_Spartan6/NF_D5" St ~ $EndEQUIPOT $EQUIPOT @@ -586,311 +586,375 @@ Na 129 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/FPGA_Spartan6/R_M1_A0" +Na 130 "/FPGA_Spartan6/R_M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/FPGA_Spartan6/R_M1_A1" +Na 131 "/FPGA_Spartan6/R_M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/FPGA_Spartan6/R_M1_A10" +Na 132 "/FPGA_Spartan6/R_M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/FPGA_Spartan6/R_M1_A11" +Na 133 "/FPGA_Spartan6/R_M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/FPGA_Spartan6/R_M1_A12" +Na 134 "/FPGA_Spartan6/R_M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/FPGA_Spartan6/R_M1_A2" +Na 135 "/FPGA_Spartan6/R_M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/FPGA_Spartan6/R_M1_A3" +Na 136 "/FPGA_Spartan6/R_M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/FPGA_Spartan6/R_M1_A5" +Na 137 "/FPGA_Spartan6/R_M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/FPGA_Spartan6/R_M1_A6" +Na 138 "/FPGA_Spartan6/R_M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/FPGA_Spartan6/R_M1_A7" +Na 139 "/FPGA_Spartan6/R_M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/FPGA_Spartan6/R_M1_A8" +Na 140 "/FPGA_Spartan6/R_M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/FPGA_Spartan6/R_M1_A9" +Na 141 "/FPGA_Spartan6/R_M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/FPGA_Spartan6/R_M1_BA0" +Na 142 "/FPGA_Spartan6/R_M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/FPGA_Spartan6/R_M1_BA1" +Na 143 "/FPGA_Spartan6/R_M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/FPGA_Spartan6/R_M1_CAS#" +Na 144 "/FPGA_Spartan6/R_M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/FPGA_Spartan6/R_M1_CKE" +Na 145 "/FPGA_Spartan6/R_M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/FPGA_Spartan6/R_M1_CS#" +Na 146 "/FPGA_Spartan6/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/FPGA_Spartan6/R_M1_DQ0" +Na 147 "/FPGA_Spartan6/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/FPGA_Spartan6/R_M1_DQ1" +Na 148 "/FPGA_Spartan6/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/FPGA_Spartan6/R_M1_DQ10" +Na 149 "/FPGA_Spartan6/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/FPGA_Spartan6/R_M1_DQ11" +Na 150 "/FPGA_Spartan6/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/FPGA_Spartan6/R_M1_DQ12" +Na 151 "/FPGA_Spartan6/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/FPGA_Spartan6/R_M1_DQ13" +Na 152 "/FPGA_Spartan6/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/FPGA_Spartan6/R_M1_DQ14" +Na 153 "/FPGA_Spartan6/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/FPGA_Spartan6/R_M1_DQ15" +Na 154 "/FPGA_Spartan6/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/FPGA_Spartan6/R_M1_DQ2" +Na 155 "/FPGA_Spartan6/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/FPGA_Spartan6/R_M1_DQ3" +Na 156 "/FPGA_Spartan6/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/FPGA_Spartan6/R_M1_DQ4" +Na 157 "/FPGA_Spartan6/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/FPGA_Spartan6/R_M1_DQ5" +Na 158 "/FPGA_Spartan6/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/FPGA_Spartan6/R_M1_DQ6" +Na 159 "/FPGA_Spartan6/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/FPGA_Spartan6/R_M1_DQ7" +Na 160 "/FPGA_Spartan6/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/FPGA_Spartan6/R_M1_DQ8" +Na 161 "/FPGA_Spartan6/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/FPGA_Spartan6/R_M1_DQ9" +Na 162 "/FPGA_Spartan6/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/FPGA_Spartan6/R_M1_LDM" +Na 163 "/FPGA_Spartan6/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/FPGA_Spartan6/R_M1_LDQS" +Na 164 "/FPGA_Spartan6/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/FPGA_Spartan6/R_M1_RAS#" +Na 165 "/FPGA_Spartan6/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/FPGA_Spartan6/R_M1_UDM" +Na 166 "/FPGA_Spartan6/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/FPGA_Spartan6/R_M1_UDQS" +Na 167 "/FPGA_Spartan6/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/FPGA_Spartan6/R_M1_WE#" +Na 168 "/FPGA_Spartan6/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/FPGA_Spartan6/SD_CLK" +Na 169 "/FPGA_Spartan6/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/FPGA_Spartan6/USBA_RCV" +Na 170 "/FPGA_Spartan6/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/FPGA_Spartan6/USBA_VM" +Na 171 "/FPGA_Spartan6/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/Non_volatile_memories/NF_ALE" +Na 172 "/FPGA_Spartan6/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/Non_volatile_memories/NF_CS1_N" +Na 173 "/FPGA_Spartan6/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/Non_volatile_memories/NF_D1" +Na 174 "/FPGA_Spartan6/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/Non_volatile_memories/NF_D3" +Na 175 "/FPGA_Spartan6/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/Non_volatile_memories/NF_D5" +Na 176 "/FPGA_Spartan6/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/Non_volatile_memories/SD_CMD" +Na 177 "/FPGA_Spartan6/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/Non_volatile_memories/SD_DAT0" +Na 178 "/FPGA_Spartan6/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/Non_volatile_memories/SD_DAT1" +Na 179 "/FPGA_Spartan6/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 180 "/Non_volatile_memories/SD_DAT2" +Na 180 "/FPGA_Spartan6/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/Non_volatile_memories/SD_DAT3" +Na 181 "/FPGA_Spartan6/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/USB/USBA_OE_N" +Na 182 "/FPGA_Spartan6/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/USB/USBA_SPD" +Na 183 "/FPGA_Spartan6/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/USB/USBA_VP" +Na 184 "/FPGA_Spartan6/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "GND" +Na 185 "/FPGA_Spartan6/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "N-000058" +Na 186 "/FPGA_Spartan6/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "N-000059" +Na 187 "/Non_volatile_memories/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "N-000358" +Na 188 "/Non_volatile_memories/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "N-000361" +Na 189 "/Non_volatile_memories/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "N-000370" +Na 190 "/Non_volatile_memories/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "N-000371" +Na 191 "/Non_volatile_memories/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "N-000372" +Na 192 "/Non_volatile_memories/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "N-000373" +Na 193 "/Non_volatile_memories/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "N-000374" +Na 194 "/Non_volatile_memories/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "N-000376" +Na 195 "/Non_volatile_memories/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "N-000383" +Na 196 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "N-000384" +Na 197 "/USB/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "N-000385" +Na 198 "/USB/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "N-000386" +Na 199 "/USB/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "N-000389" +Na 200 "/USB/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 201 "N-000390" +Na 201 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 202 "N-000391" +Na 202 "N-000058" St ~ $EndEQUIPOT $EQUIPOT -Na 203 "N-000392" +Na 203 "N-000059" St ~ $EndEQUIPOT $EQUIPOT -Na 204 "N-000393" +Na 204 "N-000374" St ~ $EndEQUIPOT $EQUIPOT -Na 205 "N-000394" +Na 205 "N-000377" St ~ $EndEQUIPOT $EQUIPOT -Na 206 "VCCO2" +Na 206 "N-000386" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 207 "N-000387" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 208 "N-000388" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 209 "N-000389" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 210 "N-000390" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 211 "N-000392" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 212 "N-000399" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 213 "N-000400" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 214 "N-000401" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 215 "N-000402" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 216 "N-000405" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 217 "N-000406" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 218 "N-000407" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 219 "N-000408" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 220 "N-000409" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 221 "N-000410" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 222 "VCCO2" St ~ $EndEQUIPOT $NCLASS @@ -908,120 +972,120 @@ AddNet "+1.8V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" -AddNet "/DDR_Banks/M0_A1" -AddNet "/DDR_Banks/M0_A11" -AddNet "/DDR_Banks/M0_A5" -AddNet "/DDR_Banks/M0_A7" -AddNet "/DDR_Banks/M0_BA0" +AddNet "/DDR_Banks/M0_A0" +AddNet "/DDR_Banks/M0_A10" AddNet "/DDR_Banks/M0_BA1" +AddNet "/DDR_Banks/M0_CKE" +AddNet "/DDR_Banks/M0_CLK" AddNet "/DDR_Banks/M0_CLK#" -AddNet "/DDR_Banks/M0_DQ13" +AddNet "/DDR_Banks/M0_DQ0" +AddNet "/DDR_Banks/M0_DQ1" +AddNet "/DDR_Banks/M0_DQ10" +AddNet "/DDR_Banks/M0_DQ12" +AddNet "/DDR_Banks/M0_DQ14" +AddNet "/DDR_Banks/M0_DQ2" AddNet "/DDR_Banks/M0_DQ4" -AddNet "/DDR_Banks/M0_DQ5" -AddNet "/DDR_Banks/M0_DQ7" +AddNet "/DDR_Banks/M0_DQ6" +AddNet "/DDR_Banks/M0_DQ8" AddNet "/DDR_Banks/M0_DQ9" -AddNet "/DDR_Banks/M0_LDQS" -AddNet "/DDR_Banks/M0_RAS#" -AddNet "/DDR_Banks/M0_UDM" AddNet "/DDR_Banks/M0_UDQS" AddNet "/DDR_Banks/M0_WE#" -AddNet "/DDR_Banks/M1_A3" -AddNet "/DDR_Banks/M1_A4" +AddNet "/DDR_Banks/M1_A0" +AddNet "/DDR_Banks/M1_A1" +AddNet "/DDR_Banks/M1_A5" +AddNet "/DDR_Banks/M1_A7" +AddNet "/DDR_Banks/M1_A8" +AddNet "/DDR_Banks/M1_BA0" AddNet "/DDR_Banks/M1_BA1" -AddNet "/DDR_Banks/M1_CLK" +AddNet "/DDR_Banks/M1_CAS#" +AddNet "/DDR_Banks/M1_CKE" +AddNet "/DDR_Banks/M1_CLK#" +AddNet "/DDR_Banks/M1_CS#" AddNet "/DDR_Banks/M1_DQ10" -AddNet "/DDR_Banks/M1_DQ12" -AddNet "/DDR_Banks/M1_DQ14" -AddNet "/DDR_Banks/M1_DQ15" -AddNet "/DDR_Banks/M1_DQ6" +AddNet "/DDR_Banks/M1_DQ11" AddNet "/DDR_Banks/M1_DQ7" AddNet "/DDR_Banks/M1_DQ9" AddNet "/DDR_Banks/M1_LDM" AddNet "/DDR_Banks/M1_LDQS" -AddNet "/DDR_Banks/M1_RAS#" +AddNet "/DDR_Banks/M1_UDM" AddNet "/DDR_Banks/M1_UDQS" -AddNet "/DDR_Banks/M1_WE#" AddNet "/Ethernet_Phy/ETH_A1.8V" AddNet "/Ethernet_Phy/ETH_A3.3V" -AddNet "/Ethernet_Phy/ETH_CRS" -AddNet "/Ethernet_Phy/ETH_INT" +AddNet "/Ethernet_Phy/ETH_COL" AddNet "/Ethernet_Phy/ETH_LED0" AddNet "/Ethernet_Phy/ETH_LED1" -AddNet "/Ethernet_Phy/ETH_MDC" AddNet "/Ethernet_Phy/ETH_PLL1.8V" +AddNet "/Ethernet_Phy/ETH_RXC" +AddNet "/Ethernet_Phy/ETH_RXD0" AddNet "/Ethernet_Phy/ETH_RXD1" +AddNet "/Ethernet_Phy/ETH_RXD2" AddNet "/Ethernet_Phy/ETH_RXD3" -AddNet "/Ethernet_Phy/ETH_TXC" -AddNet "/Ethernet_Phy/ETH_TXD2" -AddNet "/Ethernet_Phy/ETH_TXEN" +AddNet "/Ethernet_Phy/ETH_RXER" +AddNet "/Ethernet_Phy/ETH_TXD3" +AddNet "/Ethernet_Phy/ETH_TXER" AddNet "/FPGA_Spartan6/ETH_CLK" -AddNet "/FPGA_Spartan6/ETH_COL" +AddNet "/FPGA_Spartan6/ETH_CRS" +AddNet "/FPGA_Spartan6/ETH_INT" +AddNet "/FPGA_Spartan6/ETH_MDC" AddNet "/FPGA_Spartan6/ETH_MDIO" AddNet "/FPGA_Spartan6/ETH_RESET_N" -AddNet "/FPGA_Spartan6/ETH_RXC" -AddNet "/FPGA_Spartan6/ETH_RXD0" -AddNet "/FPGA_Spartan6/ETH_RXD2" AddNet "/FPGA_Spartan6/ETH_RXDV" -AddNet "/FPGA_Spartan6/ETH_RXER" +AddNet "/FPGA_Spartan6/ETH_TXC" AddNet "/FPGA_Spartan6/ETH_TXD0" AddNet "/FPGA_Spartan6/ETH_TXD1" -AddNet "/FPGA_Spartan6/ETH_TXD3" -AddNet "/FPGA_Spartan6/ETH_TXER" -AddNet "/FPGA_Spartan6/M0_A0" -AddNet "/FPGA_Spartan6/M0_A10" +AddNet "/FPGA_Spartan6/ETH_TXD2" +AddNet "/FPGA_Spartan6/ETH_TXEN" +AddNet "/FPGA_Spartan6/M0_A1" +AddNet "/FPGA_Spartan6/M0_A11" AddNet "/FPGA_Spartan6/M0_A12" AddNet "/FPGA_Spartan6/M0_A2" AddNet "/FPGA_Spartan6/M0_A3" AddNet "/FPGA_Spartan6/M0_A4" +AddNet "/FPGA_Spartan6/M0_A5" AddNet "/FPGA_Spartan6/M0_A6" +AddNet "/FPGA_Spartan6/M0_A7" AddNet "/FPGA_Spartan6/M0_A8" AddNet "/FPGA_Spartan6/M0_A9" +AddNet "/FPGA_Spartan6/M0_BA0" AddNet "/FPGA_Spartan6/M0_CAS#" -AddNet "/FPGA_Spartan6/M0_CKE" -AddNet "/FPGA_Spartan6/M0_CLK" -AddNet "/FPGA_Spartan6/M0_DQ0" -AddNet "/FPGA_Spartan6/M0_DQ1" -AddNet "/FPGA_Spartan6/M0_DQ10" AddNet "/FPGA_Spartan6/M0_DQ11" -AddNet "/FPGA_Spartan6/M0_DQ12" -AddNet "/FPGA_Spartan6/M0_DQ14" +AddNet "/FPGA_Spartan6/M0_DQ13" AddNet "/FPGA_Spartan6/M0_DQ15" -AddNet "/FPGA_Spartan6/M0_DQ2" AddNet "/FPGA_Spartan6/M0_DQ3" -AddNet "/FPGA_Spartan6/M0_DQ6" -AddNet "/FPGA_Spartan6/M0_DQ8" +AddNet "/FPGA_Spartan6/M0_DQ5" +AddNet "/FPGA_Spartan6/M0_DQ7" AddNet "/FPGA_Spartan6/M0_LDM" -AddNet "/FPGA_Spartan6/M1_A0" -AddNet "/FPGA_Spartan6/M1_A1" +AddNet "/FPGA_Spartan6/M0_LDQS" +AddNet "/FPGA_Spartan6/M0_RAS#" +AddNet "/FPGA_Spartan6/M0_UDM" AddNet "/FPGA_Spartan6/M1_A10" AddNet "/FPGA_Spartan6/M1_A11" AddNet "/FPGA_Spartan6/M1_A12" AddNet "/FPGA_Spartan6/M1_A2" -AddNet "/FPGA_Spartan6/M1_A5" +AddNet "/FPGA_Spartan6/M1_A3" +AddNet "/FPGA_Spartan6/M1_A4" AddNet "/FPGA_Spartan6/M1_A6" -AddNet "/FPGA_Spartan6/M1_A7" -AddNet "/FPGA_Spartan6/M1_A8" AddNet "/FPGA_Spartan6/M1_A9" -AddNet "/FPGA_Spartan6/M1_BA0" -AddNet "/FPGA_Spartan6/M1_CAS#" -AddNet "/FPGA_Spartan6/M1_CKE" -AddNet "/FPGA_Spartan6/M1_CLK#" -AddNet "/FPGA_Spartan6/M1_CS#" +AddNet "/FPGA_Spartan6/M1_CLK" AddNet "/FPGA_Spartan6/M1_DQ0" AddNet "/FPGA_Spartan6/M1_DQ1" -AddNet "/FPGA_Spartan6/M1_DQ11" +AddNet "/FPGA_Spartan6/M1_DQ12" AddNet "/FPGA_Spartan6/M1_DQ13" +AddNet "/FPGA_Spartan6/M1_DQ14" +AddNet "/FPGA_Spartan6/M1_DQ15" AddNet "/FPGA_Spartan6/M1_DQ2" AddNet "/FPGA_Spartan6/M1_DQ3" AddNet "/FPGA_Spartan6/M1_DQ4" AddNet "/FPGA_Spartan6/M1_DQ5" +AddNet "/FPGA_Spartan6/M1_DQ6" AddNet "/FPGA_Spartan6/M1_DQ8" -AddNet "/FPGA_Spartan6/M1_UDM" +AddNet "/FPGA_Spartan6/M1_RAS#" +AddNet "/FPGA_Spartan6/M1_WE#" AddNet "/FPGA_Spartan6/NF_CLE" -AddNet "/FPGA_Spartan6/NF_D0" +AddNet "/FPGA_Spartan6/NF_CS1_N" +AddNet "/FPGA_Spartan6/NF_D1" AddNet "/FPGA_Spartan6/NF_D2" -AddNet "/FPGA_Spartan6/NF_D4" -AddNet "/FPGA_Spartan6/NF_D6" +AddNet "/FPGA_Spartan6/NF_D5" AddNet "/FPGA_Spartan6/NF_D7" AddNet "/FPGA_Spartan6/NF_RE_N" AddNet "/FPGA_Spartan6/NF_RNB" @@ -1032,6 +1096,22 @@ AddNet "/FPGA_Spartan6/PROG_MISO0" AddNet "/FPGA_Spartan6/PROG_MISO1" AddNet "/FPGA_Spartan6/PROG_MISO2" AddNet "/FPGA_Spartan6/PROG_MISO3" +AddNet "/FPGA_Spartan6/R_M0_DQ0" +AddNet "/FPGA_Spartan6/R_M0_DQ1" +AddNet "/FPGA_Spartan6/R_M0_DQ10" +AddNet "/FPGA_Spartan6/R_M0_DQ11" +AddNet "/FPGA_Spartan6/R_M0_DQ12" +AddNet "/FPGA_Spartan6/R_M0_DQ13" +AddNet "/FPGA_Spartan6/R_M0_DQ14" +AddNet "/FPGA_Spartan6/R_M0_DQ15" +AddNet "/FPGA_Spartan6/R_M0_DQ2" +AddNet "/FPGA_Spartan6/R_M0_DQ3" +AddNet "/FPGA_Spartan6/R_M0_DQ4" +AddNet "/FPGA_Spartan6/R_M0_DQ5" +AddNet "/FPGA_Spartan6/R_M0_DQ6" +AddNet "/FPGA_Spartan6/R_M0_DQ7" +AddNet "/FPGA_Spartan6/R_M0_DQ8" +AddNet "/FPGA_Spartan6/R_M0_DQ9" AddNet "/FPGA_Spartan6/R_M1_A0" AddNet "/FPGA_Spartan6/R_M1_A1" AddNet "/FPGA_Spartan6/R_M1_A10" @@ -1071,43 +1151,43 @@ AddNet "/FPGA_Spartan6/R_M1_RAS#" AddNet "/FPGA_Spartan6/R_M1_UDM" AddNet "/FPGA_Spartan6/R_M1_UDQS" AddNet "/FPGA_Spartan6/R_M1_WE#" -AddNet "/FPGA_Spartan6/SD_CLK" -AddNet "/FPGA_Spartan6/USBA_RCV" -AddNet "/FPGA_Spartan6/USBA_VM" +AddNet "/FPGA_Spartan6/SD_DAT3" +AddNet "/FPGA_Spartan6/USBA_VP" AddNet "/Non_volatile_memories/NF_ALE" -AddNet "/Non_volatile_memories/NF_CS1_N" -AddNet "/Non_volatile_memories/NF_D1" +AddNet "/Non_volatile_memories/NF_D0" AddNet "/Non_volatile_memories/NF_D3" -AddNet "/Non_volatile_memories/NF_D5" +AddNet "/Non_volatile_memories/NF_D4" +AddNet "/Non_volatile_memories/NF_D6" +AddNet "/Non_volatile_memories/SD_CLK" AddNet "/Non_volatile_memories/SD_CMD" AddNet "/Non_volatile_memories/SD_DAT0" AddNet "/Non_volatile_memories/SD_DAT1" AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "/Non_volatile_memories/SD_DAT3" AddNet "/USB/USBA_OE_N" +AddNet "/USB/USBA_RCV" AddNet "/USB/USBA_SPD" -AddNet "/USB/USBA_VP" +AddNet "/USB/USBA_VM" AddNet "GND" AddNet "N-000058" AddNet "N-000059" -AddNet "N-000358" -AddNet "N-000361" -AddNet "N-000370" -AddNet "N-000371" -AddNet "N-000372" -AddNet "N-000373" AddNet "N-000374" -AddNet "N-000376" -AddNet "N-000383" -AddNet "N-000384" -AddNet "N-000385" +AddNet "N-000377" AddNet "N-000386" +AddNet "N-000387" +AddNet "N-000388" AddNet "N-000389" AddNet "N-000390" -AddNet "N-000391" AddNet "N-000392" -AddNet "N-000393" -AddNet "N-000394" +AddNet "N-000399" +AddNet "N-000400" +AddNet "N-000401" +AddNet "N-000402" +AddNet "N-000405" +AddNet "N-000406" +AddNet "N-000407" +AddNet "N-000408" +AddNet "N-000409" +AddNet "N-000410" AddNet "VCCO2" $EndNCLASS $MODULE 1206 @@ -1134,7 +1214,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -1159,7 +1239,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -4133 -4133 $EndPAD $PAD @@ -1180,49 +1260,49 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_CLK" +Ne 57 "/FPGA_Spartan6/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_RESET_N" +Ne 62 "/FPGA_Spartan6/ETH_RESET_N" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RXD0" +Ne 50 "/Ethernet_Phy/ETH_RXD0" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_RXER" +Ne 54 "/Ethernet_Phy/ETH_RXER" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_TXEN" +Ne 68 "/FPGA_Spartan6/ETH_TXEN" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_TXD3" +Ne 55 "/Ethernet_Phy/ETH_TXD3" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_INT" +Ne 59 "/FPGA_Spartan6/ETH_INT" Po -590 -4133 $EndPAD $PAD @@ -1236,14 +1316,14 @@ $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/Non_volatile_memories/NF_D3" +Ne 189 "/Non_volatile_memories/NF_D3" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/Non_volatile_memories/NF_D1" +Ne 117 "/FPGA_Spartan6/NF_D1" Po 590 -4133 $EndPAD $PAD @@ -1257,7 +1337,7 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/Non_volatile_memories/NF_ALE" +Ne 187 "/Non_volatile_memories/NF_ALE" Po 1377 -4133 $EndPAD $PAD @@ -1271,14 +1351,14 @@ $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 180 "/Non_volatile_memories/SD_DAT2" +Ne 196 "/Non_volatile_memories/SD_DAT2" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/Non_volatile_memories/SD_DAT0" +Ne 194 "/Non_volatile_memories/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -1306,7 +1386,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 4133 -4133 $EndPAD $PAD @@ -1341,14 +1421,14 @@ $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2558 -3739 $EndPAD $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_RXD1" +Ne 51 "/Ethernet_Phy/ETH_RXD1" Po -2165 -3739 $EndPAD $PAD @@ -1362,21 +1442,21 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_TXER" +Ne 56 "/Ethernet_Phy/ETH_TXER" Po -1377 -3739 $EndPAD $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -983 -3739 $EndPAD $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_COL" +Ne 45 "/Ethernet_Phy/ETH_COL" Po -590 -3739 $EndPAD $PAD @@ -1390,14 +1470,14 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/NF_D4" +Ne 190 "/Non_volatile_memories/NF_D4" Po 196 -3739 $EndPAD $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 590 -3739 $EndPAD $PAD @@ -1425,14 +1505,14 @@ $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 2165 -3739 $EndPAD $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/Non_volatile_memories/SD_DAT1" +Ne 195 "/Non_volatile_memories/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1467,7 +1547,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A11" +Ne 70 "/FPGA_Spartan6/M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1495,42 +1575,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_MDIO" +Ne 61 "/FPGA_Spartan6/ETH_MDIO" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RXD2" +Ne 52 "/Ethernet_Phy/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_RXDV" +Ne 63 "/FPGA_Spartan6/ETH_RXDV" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_TXD1" +Ne 66 "/FPGA_Spartan6/ETH_TXD1" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_TXD2" +Ne 67 "/FPGA_Spartan6/ETH_TXD2" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_CRS" +Ne 58 "/FPGA_Spartan6/ETH_CRS" Po -590 -3346 $EndPAD $PAD @@ -1544,14 +1624,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/Non_volatile_memories/NF_D5" +Ne 119 "/FPGA_Spartan6/NF_D5" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_D2" +Ne 118 "/FPGA_Spartan6/NF_D2" Po 590 -3346 $EndPAD $PAD @@ -1572,14 +1652,14 @@ $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/Non_volatile_memories/NF_CS1_N" +Ne 116 "/FPGA_Spartan6/NF_CS1_N" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/Non_volatile_memories/SD_DAT3" +Ne 185 "/FPGA_Spartan6/SD_DAT3" Po 2165 -3346 $EndPAD $PAD @@ -1600,7 +1680,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/FPGA_Spartan6/R_M1_A8" +Ne 156 "/FPGA_Spartan6/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1614,21 +1694,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/FPGA_Spartan6/R_M1_A9" +Ne 157 "/FPGA_Spartan6/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A12" +Ne 71 "/FPGA_Spartan6/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_CKE" +Ne 9 "/DDR_Banks/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1642,7 +1722,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1656,42 +1736,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_RXD3" +Ne 53 "/Ethernet_Phy/ETH_RXD3" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_TXC" +Ne 64 "/FPGA_Spartan6/ETH_TXC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_RXC" +Ne 49 "/Ethernet_Phy/ETH_RXC" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_TXD0" +Ne 65 "/FPGA_Spartan6/ETH_TXD0" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_MDC" +Ne 60 "/FPGA_Spartan6/ETH_MDC" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/NF_D6" +Ne 191 "/Non_volatile_memories/NF_D6" Po -196 -2952 $EndPAD $PAD @@ -1712,7 +1792,7 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_D0" +Ne 188 "/Non_volatile_memories/NF_D0" Po 983 -2952 $EndPAD $PAD @@ -1733,14 +1813,14 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/Non_volatile_memories/SD_CMD" +Ne 193 "/Non_volatile_memories/SD_CMD" Po 2165 -2952 $EndPAD $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 2558 -2952 $EndPAD $PAD @@ -1761,35 +1841,35 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA_Spartan6/R_M1_CKE" +Ne 161 "/FPGA_Spartan6/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Spartan6/R_M1_A12" +Ne 150 "/FPGA_Spartan6/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_A9" +Ne 79 "/FPGA_Spartan6/M0_A9" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_A8" +Ne 78 "/FPGA_Spartan6/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1817,7 +1897,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -1771 -2558 $EndPAD $PAD @@ -1845,7 +1925,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -196 -2558 $EndPAD $PAD @@ -1873,14 +1953,14 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 1377 -2558 $EndPAD $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/FPGA_Spartan6/SD_CLK" +Ne 192 "/Non_volatile_memories/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -1908,21 +1988,21 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/FPGA_Spartan6/R_M1_A7" +Ne 155 "/FPGA_Spartan6/R_M1_A7" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_Spartan6/R_M1_A2" +Ne 151 "/FPGA_Spartan6/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -1936,14 +2016,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_WE#" +Ne 23 "/DDR_Banks/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A4" +Ne 74 "/FPGA_Spartan6/M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -2055,7 +2135,7 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Spartan6/R_M1_A11" +Ne 149 "/FPGA_Spartan6/R_M1_A11" Po 2952 -2165 $EndPAD $PAD @@ -2069,21 +2149,21 @@ $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/R_M1_A0" +Ne 146 "/FPGA_Spartan6/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/R_M1_A1" +Ne 147 "/FPGA_Spartan6/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_BA1" +Ne 8 "/DDR_Banks/M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -2097,21 +2177,21 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_BA0" +Ne 80 "/FPGA_Spartan6/M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A10" +Ne 7 "/DDR_Banks/M0_A10" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2558 -1771 $EndPAD $PAD @@ -2202,21 +2282,21 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Spartan6/R_M1_A10" +Ne 148 "/FPGA_Spartan6/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_Spartan6/R_M1_A3" +Ne 152 "/FPGA_Spartan6/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2237,49 +2317,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A1" +Ne 69 "/FPGA_Spartan6/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A0" +Ne 6 "/DDR_Banks/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_CLK#" +Ne 11 "/DDR_Banks/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_CLK" +Ne 10 "/DDR_Banks/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A2" +Ne 72 "/FPGA_Spartan6/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A7" +Ne 77 "/FPGA_Spartan6/M0_A7" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -1771 -1377 $EndPAD $PAD @@ -2342,7 +2422,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA_Spartan6/R_M1_CS#" +Ne 162 "/FPGA_Spartan6/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -2363,56 +2443,56 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/FPGA_Spartan6/R_M1_WE#" +Ne 184 "/FPGA_Spartan6/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_CLK" +Ne 100 "/FPGA_Spartan6/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/FPGA_Spartan6/R_M1_RAS#" +Ne 181 "/FPGA_Spartan6/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/FPGA_Spartan6/R_M1_CAS#" +Ne 160 "/FPGA_Spartan6/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ5" +Ne 141 "/FPGA_Spartan6/R_M0_DQ5" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ4" +Ne 140 "/FPGA_Spartan6/R_M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A6" +Ne 76 "/FPGA_Spartan6/M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2447,7 +2527,7 @@ $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -983 -983 $EndPAD $PAD @@ -2461,7 +2541,7 @@ $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -196 -983 $EndPAD $PAD @@ -2475,7 +2555,7 @@ $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 590 -983 $EndPAD $PAD @@ -2489,7 +2569,7 @@ $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 1377 -983 $EndPAD $PAD @@ -2503,7 +2583,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/FPGA_Spartan6/R_M1_BA0" +Ne 158 "/FPGA_Spartan6/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2517,70 +2597,70 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_CLK#" +Ne 33 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_Spartan6/R_M1_DQ4" +Ne 173 "/FPGA_Spartan6/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_Spartan6/R_M1_DQ5" +Ne 174 "/FPGA_Spartan6/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ7" +Ne 143 "/FPGA_Spartan6/R_M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ6" +Ne 142 "/FPGA_Spartan6/R_M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A5" +Ne 75 "/FPGA_Spartan6/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_CAS#" +Ne 81 "/FPGA_Spartan6/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_RAS#" +Ne 90 "/FPGA_Spartan6/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A3" +Ne 73 "/FPGA_Spartan6/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2608,7 +2688,7 @@ $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -590 -590 $EndPAD $PAD @@ -2622,7 +2702,7 @@ $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 196 -590 $EndPAD $PAD @@ -2636,7 +2716,7 @@ $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 983 -590 $EndPAD $PAD @@ -2657,7 +2737,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/FPGA_Spartan6/R_M1_BA1" +Ne 159 "/FPGA_Spartan6/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2671,28 +2751,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/FPGA_Spartan6/R_M1_A6" +Ne 154 "/FPGA_Spartan6/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA_Spartan6/R_M1_A5" +Ne 153 "/FPGA_Spartan6/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/FPGA_Spartan6/R_M1_DQ6" +Ne 175 "/FPGA_Spartan6/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/FPGA_Spartan6/R_M1_DQ7" +Ne 176 "/FPGA_Spartan6/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2713,7 +2793,7 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_LDQS" +Ne 89 "/FPGA_Spartan6/M0_LDQS" Po -3346 -196 $EndPAD $PAD @@ -2727,7 +2807,7 @@ $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2558 -196 $EndPAD $PAD @@ -2755,7 +2835,7 @@ $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -983 -196 $EndPAD $PAD @@ -2769,7 +2849,7 @@ $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -196 -196 $EndPAD $PAD @@ -2783,7 +2863,7 @@ $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 590 -196 $EndPAD $PAD @@ -2818,21 +2898,21 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/FPGA_Spartan6/R_M1_LDM" +Ne 179 "/FPGA_Spartan6/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/FPGA_Spartan6/R_M1_LDQS" +Ne 180 "/FPGA_Spartan6/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -2853,21 +2933,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ3" +Ne 139 "/FPGA_Spartan6/R_M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ2" +Ne 138 "/FPGA_Spartan6/R_M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_UDM" +Ne 91 "/FPGA_Spartan6/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2916,7 +2996,7 @@ $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -590 196 $EndPAD $PAD @@ -2930,7 +3010,7 @@ $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 196 196 $EndPAD $PAD @@ -2944,7 +3024,7 @@ $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 983 196 $EndPAD $PAD @@ -2972,7 +3052,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/FPGA_Spartan6/USBA_VM" +Ne 200 "/USB/USBA_VM" Po 2558 196 $EndPAD $PAD @@ -2986,42 +3066,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/FPGA_Spartan6/R_M1_UDM" +Ne 182 "/FPGA_Spartan6/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/FPGA_Spartan6/R_M1_DQ2" +Ne 171 "/FPGA_Spartan6/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/FPGA_Spartan6/R_M1_DQ3" +Ne 172 "/FPGA_Spartan6/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ1" +Ne 131 "/FPGA_Spartan6/R_M0_DQ1" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ0" +Ne 130 "/FPGA_Spartan6/R_M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -3063,7 +3143,7 @@ $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -983 590 $EndPAD $PAD @@ -3077,7 +3157,7 @@ $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -196 590 $EndPAD $PAD @@ -3091,7 +3171,7 @@ $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 590 590 $EndPAD $PAD @@ -3112,14 +3192,14 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/FPGA_Spartan6/USBA_RCV" +Ne 198 "/USB/USBA_RCV" Po 1771 590 $EndPAD $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 2165 590 $EndPAD $PAD @@ -3140,35 +3220,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA_Spartan6/R_M1_DQ0" +Ne 163 "/FPGA_Spartan6/R_M1_DQ0" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA_Spartan6/R_M1_DQ1" +Ne 164 "/FPGA_Spartan6/R_M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ9" +Ne 145 "/FPGA_Spartan6/R_M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_DQ8" +Ne 144 "/FPGA_Spartan6/R_M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3224,7 +3304,7 @@ $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -590 983 $EndPAD $PAD @@ -3238,7 +3318,7 @@ $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 196 983 $EndPAD $PAD @@ -3252,7 +3332,7 @@ $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 983 983 $EndPAD $PAD @@ -3273,14 +3353,14 @@ $PAD Sh "P17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/USB/USBA_VP" +Ne 186 "/FPGA_Spartan6/USBA_VP" Po 2165 983 $EndPAD $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/USB/USBA_OE_N" +Ne 197 "/USB/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -3301,21 +3381,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_Spartan6/R_M1_DQ8" +Ne 177 "/FPGA_Spartan6/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_Spartan6/R_M1_DQ9" +Ne 178 "/FPGA_Spartan6/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ11" +Ne 133 "/FPGA_Spartan6/R_M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3329,7 +3409,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ10" +Ne 132 "/FPGA_Spartan6/R_M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3343,7 +3423,7 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2558 1377 $EndPAD $PAD @@ -3434,21 +3514,21 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 2558 1377 $EndPAD $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/USB/USBA_SPD" +Ne 199 "/USB/USBA_SPD" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_Spartan6/R_M1_DQ10" +Ne 165 "/FPGA_Spartan6/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3462,7 +3542,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/FPGA_Spartan6/R_M1_DQ11" +Ne 166 "/FPGA_Spartan6/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3476,7 +3556,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_UDQS" +Ne 22 "/DDR_Banks/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3525,7 +3605,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -983 1771 $EndPAD $PAD @@ -3553,7 +3633,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po 590 1771 $EndPAD $PAD @@ -3609,7 +3689,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/FPGA_Spartan6/R_M1_UDQS" +Ne 183 "/FPGA_Spartan6/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3623,21 +3703,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ13" +Ne 135 "/FPGA_Spartan6/R_M0_DQ13" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ12" +Ne 134 "/FPGA_Spartan6/R_M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3665,7 +3745,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -1771 2165 $EndPAD $PAD @@ -3756,35 +3836,35 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/FPGA_Spartan6/R_M1_DQ12" +Ne 167 "/FPGA_Spartan6/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/FPGA_Spartan6/R_M1_DQ13" +Ne 168 "/FPGA_Spartan6/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ15" +Ne 137 "/FPGA_Spartan6/R_M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ14" +Ne 136 "/FPGA_Spartan6/R_M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3798,7 +3878,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2952 2558 $EndPAD $PAD @@ -3826,7 +3906,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -1377 2558 $EndPAD $PAD @@ -3840,7 +3920,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -590 2558 $EndPAD $PAD @@ -3854,7 +3934,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po 196 2558 $EndPAD $PAD @@ -3868,7 +3948,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 983 2558 $EndPAD $PAD @@ -3882,7 +3962,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po 1771 2558 $EndPAD $PAD @@ -3917,14 +3997,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_Spartan6/R_M1_DQ14" +Ne 169 "/FPGA_Spartan6/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_Spartan6/R_M1_DQ15" +Ne 170 "/FPGA_Spartan6/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -3959,7 +4039,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -2558 2952 $EndPAD $PAD @@ -3973,7 +4053,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -1771 2952 $EndPAD $PAD @@ -4036,7 +4116,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 1771 2952 $EndPAD $PAD @@ -4057,7 +4137,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 2952 2952 $EndPAD $PAD @@ -4253,7 +4333,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -3346 3739 $EndPAD $PAD @@ -4267,7 +4347,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2558 3739 $EndPAD $PAD @@ -4281,7 +4361,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -1771 3739 $EndPAD $PAD @@ -4295,7 +4375,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -983 3739 $EndPAD $PAD @@ -4309,7 +4389,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -196 3739 $EndPAD $PAD @@ -4323,7 +4403,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 590 3739 $EndPAD $PAD @@ -4337,7 +4417,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po 1377 3739 $EndPAD $PAD @@ -4351,7 +4431,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 2165 3739 $EndPAD $PAD @@ -4365,7 +4445,7 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po 2952 3739 $EndPAD $PAD @@ -4393,7 +4473,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -4133 4133 $EndPAD $PAD @@ -4540,7 +4620,7 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 @@ -4562,35 +4642,35 @@ $PAD Sh "12" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -1613 1082 $EndPAD $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_RXER" +Ne 54 "/Ethernet_Phy/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_RXC" +Ne 49 "/Ethernet_Phy/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_RXDV" +Ne 63 "/FPGA_Spartan6/ETH_RXDV" Po -1613 491 $EndPAD $PAD Sh "8" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -1613 295 $EndPAD $PAD @@ -4604,63 +4684,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RXD0" +Ne 50 "/Ethernet_Phy/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_RXD1" +Ne 51 "/Ethernet_Phy/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RXD2" +Ne 52 "/Ethernet_Phy/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_RXD3" +Ne 53 "/Ethernet_Phy/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_MDC" +Ne 60 "/FPGA_Spartan6/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_MDIO" +Ne 61 "/FPGA_Spartan6/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_RESET_N" +Ne 62 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 48 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_CLK" +Ne 57 "/FPGA_Spartan6/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -4674,7 +4754,7 @@ $PAD Sh "44" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -295 -1613 $EndPAD $PAD @@ -4695,56 +4775,56 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 190 "N-000370" +Ne 206 "N-000386" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 192 "N-000372" +Ne 208 "N-000388" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_A3.3V" +Ne 44 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 188 "N-000358" +Ne 204 "N-000374" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_INT" +Ne 59 "/FPGA_Spartan6/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_LED0" +Ne 46 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_LED1" +Ne 47 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4772,21 +4852,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_A1.8V" +Ne 43 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 193 "N-000373" +Ne 209 "N-000389" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 191 "N-000371" +Ne 207 "N-000387" Po 1613 -491 $EndPAD $PAD @@ -4800,14 +4880,14 @@ $PAD Sh "35" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 1613 -1082 $EndPAD $PAD @@ -4821,70 +4901,70 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_TXER" +Ne 56 "/Ethernet_Phy/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_TXC" +Ne 64 "/FPGA_Spartan6/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_TXEN" +Ne 68 "/FPGA_Spartan6/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_TXD0" +Ne 65 "/FPGA_Spartan6/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_TXD1" +Ne 66 "/FPGA_Spartan6/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_TXD2" +Ne 67 "/FPGA_Spartan6/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_TXD3" +Ne 55 "/Ethernet_Phy/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_COL" +Ne 45 "/Ethernet_Phy/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_CRS" +Ne 58 "/FPGA_Spartan6/ETH_CRS" Po 688 1613 $EndPAD $PAD Sh "23" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 885 1613 $EndPAD $PAD @@ -5176,7 +5256,7 @@ $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/Non_volatile_memories/NF_CS1_N" +Ne 116 "/FPGA_Spartan6/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -5204,7 +5284,7 @@ $PAD Sh "13" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 100 3850 $EndPAD $PAD @@ -5232,7 +5312,7 @@ $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/Non_volatile_memories/NF_ALE" +Ne 187 "/Non_volatile_memories/NF_ALE" Po 880 3850 $EndPAD $PAD @@ -5316,28 +5396,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_D0" +Ne 188 "/Non_volatile_memories/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/Non_volatile_memories/NF_D1" +Ne 117 "/FPGA_Spartan6/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_D2" +Ne 118 "/FPGA_Spartan6/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/Non_volatile_memories/NF_D3" +Ne 189 "/Non_volatile_memories/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -5365,7 +5445,7 @@ $PAD Sh "36" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 100 -3850 $EndPAD $PAD @@ -5400,21 +5480,21 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/NF_D4" +Ne 190 "/Non_volatile_memories/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/Non_volatile_memories/NF_D5" +Ne 119 "/FPGA_Spartan6/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/NF_D6" +Ne 191 "/Non_volatile_memories/NF_D6" Po -1280 -3850 $EndPAD $PAD @@ -5474,21 +5554,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 180 "/Non_volatile_memories/SD_DAT2" +Ne 196 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 181 "/Non_volatile_memories/SD_DAT3" +Ne 185 "/FPGA_Spartan6/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 177 "/Non_volatile_memories/SD_CMD" +Ne 193 "/Non_volatile_memories/SD_CMD" Po -433 0 $EndPAD $PAD @@ -5502,56 +5582,56 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 169 "/FPGA_Spartan6/SD_CLK" +Ne 192 "/Non_volatile_memories/SD_CLK" Po 433 0 $EndPAD $PAD Sh "6" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 866 0 $EndPAD $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 178 "/Non_volatile_memories/SD_DAT0" +Ne 194 "/Non_volatile_memories/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 179 "/Non_volatile_memories/SD_DAT1" +Ne 195 "/Non_volatile_memories/SD_DAT1" Po 1732 0 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po -2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po -2707 -2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 2707 -2244 $EndPAD $EndMODULE MICROSD-500901 @@ -5571,35 +5651,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 195 "N-000376" +Ne 211 "N-000392" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 195 "N-000376" +Ne 211 "N-000392" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 195 "N-000376" +Ne 211 "N-000392" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 195 "N-000376" +Ne 211 "N-000392" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 190 "N-000370" +Ne 206 "N-000386" Po -1750 -2500 $EndPAD $PAD @@ -5613,28 +5693,28 @@ $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 185 "GND" +Ne 201 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 191 "N-000371" +Ne 207 "N-000387" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 192 "N-000372" +Ne 208 "N-000388" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 185 "GND" +Ne 201 "GND" Po -250 -3500 $EndPAD $PAD @@ -5648,7 +5728,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 193 "N-000373" +Ne 209 "N-000389" Po 1750 -3500 $EndPAD $PAD @@ -5662,7 +5742,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 194 "N-000374" +Ne 210 "N-000390" Po -1150 -5400 $EndPAD $PAD @@ -5676,7 +5756,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 189 "N-000361" +Ne 205 "N-000377" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -5712,28 +5792,28 @@ $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/USB/USBA_SPD" +Ne 199 "/USB/USBA_SPD" Po -511 -1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/FPGA_Spartan6/USBA_RCV" +Ne 198 "/USB/USBA_RCV" Po -255 -1112 $EndPAD $PAD Sh "4" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/USB/USBA_VP" +Ne 186 "/FPGA_Spartan6/USBA_VP" Po 0 -1112 $EndPAD $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/FPGA_Spartan6/USBA_VM" +Ne 200 "/USB/USBA_VM" Po 255 -1112 $EndPAD $PAD @@ -5747,35 +5827,35 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 767 -1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 767 1112 $EndPAD $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/USB/USBA_OE_N" +Ne 197 "/USB/USBA_OE_N" Po 511 1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 196 "N-000383" +Ne 212 "N-000399" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 202 "N-000391" +Ne 218 "N-000407" Po 0 1112 $EndPAD $PAD @@ -5825,7 +5905,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ0" +Ne 101 "/FPGA_Spartan6/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -5839,35 +5919,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ1" +Ne 102 "/FPGA_Spartan6/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ2" +Ne 107 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ3" +Ne 108 "/FPGA_Spartan6/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_DQ4" +Ne 109 "/FPGA_Spartan6/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -5881,28 +5961,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_DQ5" +Ne 110 "/FPGA_Spartan6/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ6" +Ne 111 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_DQ7" +Ne 37 "/DDR_Banks/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5923,7 +6003,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_LDQS" +Ne 40 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -5951,35 +6031,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_LDM" +Ne 39 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_WE#" +Ne 114 "/FPGA_Spartan6/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_CAS#" +Ne 31 "/DDR_Banks/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_RAS#" +Ne 113 "/FPGA_Spartan6/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_CS#" +Ne 34 "/DDR_Banks/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -5993,49 +6073,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_BA0" +Ne 29 "/DDR_Banks/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_BA1" +Ne 30 "/DDR_Banks/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A10" +Ne 92 "/FPGA_Spartan6/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A0" +Ne 24 "/DDR_Banks/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A1" +Ne 25 "/DDR_Banks/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A2" +Ne 95 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A3" +Ne 96 "/FPGA_Spartan6/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -6049,42 +6129,42 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A4" +Ne 97 "/FPGA_Spartan6/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A5" +Ne 26 "/DDR_Banks/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_A6" +Ne 98 "/FPGA_Spartan6/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_A7" +Ne 27 "/DDR_Banks/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_A8" +Ne 28 "/DDR_Banks/M1_A8" Po 2814 -2176 $EndPAD $PAD @@ -6098,14 +6178,14 @@ $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A11" +Ne 93 "/FPGA_Spartan6/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_A12" +Ne 94 "/FPGA_Spartan6/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -6119,42 +6199,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_CLK#" +Ne 33 "/DDR_Banks/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_CKE" +Ne 32 "/DDR_Banks/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_CLK" +Ne 100 "/FPGA_Spartan6/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/M1_UDM" +Ne 41 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 186 "N-000058" +Ne 202 "N-000058" Po 255 -2176 $EndPAD $PAD @@ -6168,14 +6248,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/DDR_Banks/M1_UDQS" +Ne 42 "/DDR_Banks/M1_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -511 -2176 $EndPAD $PAD @@ -6189,7 +6269,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_DQ8" +Ne 112 "/FPGA_Spartan6/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6203,35 +6283,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_DQ9" +Ne 38 "/DDR_Banks/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_DQ10" +Ne 35 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ11" +Ne 36 "/DDR_Banks/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_DQ12" +Ne 103 "/FPGA_Spartan6/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6245,40 +6325,40 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ13" +Ne 104 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_DQ14" +Ne 105 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ15" +Ne 106 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 $MODULE TSOP-66 -Po 48439 34575 900 15 4C6098A7 4C609B99 ~~ +Po 48819 34646 900 15 4C6098A7 4C609B99 ~~ Li TSOP-66 Sc 4C609B99 AR /4C421DD3/4C609B99 @@ -6302,7 +6382,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ0" +Ne 12 "/DDR_Banks/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -6316,21 +6396,21 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ1" +Ne 13 "/DDR_Banks/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ2" +Ne 17 "/DDR_Banks/M0_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2814 2176 $EndPAD $PAD @@ -6344,7 +6424,7 @@ $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ4" +Ne 18 "/DDR_Banks/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -6358,28 +6438,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ5" +Ne 86 "/FPGA_Spartan6/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ6" +Ne 19 "/DDR_Banks/M0_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ7" +Ne 87 "/FPGA_Spartan6/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -6400,7 +6480,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_LDQS" +Ne 89 "/FPGA_Spartan6/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -6435,28 +6515,28 @@ $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_WE#" +Ne 23 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_CAS#" +Ne 81 "/FPGA_Spartan6/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_RAS#" +Ne 90 "/FPGA_Spartan6/M0_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 1791 2176 $EndPAD $PAD @@ -6470,49 +6550,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_BA0" +Ne 80 "/FPGA_Spartan6/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_BA1" +Ne 8 "/DDR_Banks/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A10" +Ne 7 "/DDR_Banks/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A0" +Ne 6 "/DDR_Banks/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A1" +Ne 69 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A2" +Ne 72 "/FPGA_Spartan6/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A3" +Ne 73 "/FPGA_Spartan6/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -6526,63 +6606,63 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A4" +Ne 74 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A5" +Ne 75 "/FPGA_Spartan6/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A6" +Ne 76 "/FPGA_Spartan6/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A7" +Ne 77 "/FPGA_Spartan6/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_A8" +Ne 78 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_A9" +Ne 79 "/FPGA_Spartan6/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A11" +Ne 70 "/FPGA_Spartan6/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A12" +Ne 71 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6596,42 +6676,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_CLK#" +Ne 11 "/DDR_Banks/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_CKE" +Ne 9 "/DDR_Banks/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_CLK" +Ne 10 "/DDR_Banks/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_UDM" +Ne 91 "/FPGA_Spartan6/M0_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 187 "N-000059" +Ne 203 "N-000059" Po 255 -2176 $EndPAD $PAD @@ -6645,14 +6725,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_UDQS" +Ne 22 "/DDR_Banks/M0_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -511 -2176 $EndPAD $PAD @@ -6666,7 +6746,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_DQ8" +Ne 20 "/DDR_Banks/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6680,35 +6760,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ9" +Ne 21 "/DDR_Banks/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ10" +Ne 14 "/DDR_Banks/M0_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ11" +Ne 82 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ12" +Ne 15 "/DDR_Banks/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6722,35 +6802,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ13" +Ne 83 "/FPGA_Spartan6/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ14" +Ne 16 "/DDR_Banks/M0_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ15" +Ne 84 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -6771,14 +6851,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 198 "N-000385" +Ne 214 "N-000401" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6799,14 +6879,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 195 "N-000376" +Ne 211 "N-000392" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6827,14 +6907,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 189 "N-000361" +Ne 205 "N-000377" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 44 "/Ethernet_Phy/ETH_LED1" +Ne 47 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6855,14 +6935,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 194 "N-000374" +Ne 210 "N-000390" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/Ethernet_Phy/ETH_LED0" +Ne 46 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6890,7 +6970,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 193 "N-000373" +Ne 209 "N-000389" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6918,7 +6998,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 191 "N-000371" +Ne 207 "N-000387" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6946,7 +7026,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 192 "N-000372" +Ne 208 "N-000388" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6974,7 +7054,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 190 "N-000370" +Ne 206 "N-000386" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6995,14 +7075,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 188 "N-000358" +Ne 204 "N-000374" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7023,7 +7103,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 54 "/FPGA_Spartan6/ETH_MDIO" +Ne 61 "/FPGA_Spartan6/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -7051,14 +7131,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 198 "N-000385" +Ne 214 "N-000401" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7079,14 +7159,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 195 "N-000376" +Ne 211 "N-000392" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7114,7 +7194,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7142,7 +7222,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7163,14 +7243,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 48 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7191,14 +7271,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_A3.3V" +Ne 44 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7219,14 +7299,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/Ethernet_Phy/ETH_A1.8V" +Ne 43 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7254,7 +7334,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7282,7 +7362,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7310,7 +7390,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7338,7 +7418,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7359,14 +7439,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 196 "N-000383" +Ne 212 "N-000399" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7387,14 +7467,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 202 "N-000391" +Ne 218 "N-000407" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7422,7 +7502,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7450,7 +7530,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7478,7 +7558,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7499,14 +7579,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_A3.3V" +Ne 44 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7534,7 +7614,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7555,7 +7635,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 200 "N-000389" +Ne 216 "N-000405" Po -570 0 $EndPAD $PAD @@ -7588,89 +7668,89 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 201 "N-000390" +Ne 217 "N-000406" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 196 "N-000383" +Ne 212 "N-000399" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 202 "N-000391" +Ne 218 "N-000407" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 202 "N-000391" +Ne 218 "N-000407" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 198 "N-000385" +Ne 214 "N-000401" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 198 "N-000385" +Ne 214 "N-000401" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 198 "N-000385" +Ne 214 "N-000401" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 198 "N-000385" +Ne 214 "N-000401" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 $MODULE 0402 -Po 46667 33394 900 0 4C5FF890 4C61CC73 ~~ +Po 47638 33465 1800 0 4C5FF890 4C61CC73 ~~ Li 0402 Sc 4C61CC73 AR /4C421DD3/4C61CC73 Op 0 0 0 At SMD -T0 0 150 200 200 900 40 M V 20 N"C17" -T1 0 -150 200 200 900 40 M I 20 N"100nF" +T0 0 150 200 200 1800 40 M V 20 N"C17" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 900 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 Ne 3 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 900 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 187 "N-000059" +Ne 203 "N-000059" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 47061 34181 2700 0 4C5FF890 4C61CC96 ~~ +Po 47441 34055 2700 0 4C5FF890 4C61CC96 ~~ Li 0402 Sc 4C61CC96 AR /4C421DD3/4C61CC96 @@ -7686,14 +7766,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 187 "N-000059" +Ne 203 "N-000059" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7714,14 +7794,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 186 "N-000058" +Ne 202 "N-000058" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7749,40 +7829,40 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 186 "N-000058" +Ne 202 "N-000058" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 47061 33394 900 0 4C5FF890 4C61CD4A ~~ +Po 47638 33071 1800 0 4C5FF890 4C61CD4A ~~ Li 0402 Sc 4C61CD4A AR /4C421DD3/4C61CD4A Op 0 0 0 At SMD -T0 0 150 200 200 900 40 M V 20 N"R11" -T1 0 -150 200 200 900 40 M I 20 N"1K_1%" +T0 0 150 200 200 1800 40 M V 20 N"R11" +T1 0 -150 200 200 1800 40 M I 20 N"1K_1%" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 900 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 Ne 3 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 900 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 187 "N-000059" +Ne 203 "N-000059" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46667 34181 2700 0 4C5FF890 4C61CDB5 ~~ +Po 47835 34055 2700 0 4C5FF890 4C61CDB5 ~~ Li 0402 Sc 4C61CDB5 AR /4C421DD3/4C61CDB5 @@ -7798,14 +7878,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 187 "N-000059" +Ne 203 "N-000059" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7833,7 +7913,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 186 "N-000058" +Ne 202 "N-000058" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7861,7 +7941,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7889,7 +7969,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7917,12 +7997,12 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46864 37528 0 0 4C5FF890 4C61CF17 ~~ +Po 46260 37402 0 0 4C5FF890 4C61CF17 ~~ Li 0402 Sc 4C61CF17 AR /4C421DD3/4C61CF17 @@ -7945,7 +8025,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7973,7 +8053,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8001,7 +8081,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8029,7 +8109,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8057,12 +8137,12 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 62525 37351 0 0 4C5FF890 4C61CFA4 ~~ +Po 62402 37402 0 0 4C5FF890 4C61CFA4 ~~ Li 0402 Sc 4C61CFA4 AR /4C421DD3/4C61CFA4 @@ -8085,12 +8165,12 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 62525 35973 0 0 4C5FF890 4C61CFA5 ~~ +Po 62402 35827 0 0 4C5FF890 4C61CFA5 ~~ Li 0402 Sc 4C61CFA5 AR /4C421DD3/4C61CFA5 @@ -8113,7 +8193,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8141,7 +8221,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8169,7 +8249,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8190,14 +8270,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 186 "N-000058" +Ne 202 "N-000058" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8218,14 +8298,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 197 "N-000384" +Ne 213 "N-000400" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8246,14 +8326,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 200 "N-000389" +Ne 216 "N-000405" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "N-000390" +Ne 217 "N-000406" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8274,7 +8354,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 199 "N-000386" +Ne 215 "N-000402" Po -294 0 $EndPAD $PAD @@ -8309,7 +8389,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8330,14 +8410,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 205 "N-000394" +Ne 221 "N-000410" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8358,14 +8438,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 205 "N-000394" +Ne 221 "N-000410" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8393,7 +8473,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8414,14 +8494,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 203 "N-000392" +Ne 219 "N-000408" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8442,14 +8522,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 204 "N-000393" +Ne 220 "N-000409" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8477,7 +8557,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -8505,7 +8585,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -8526,7 +8606,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 199 "N-000386" +Ne 215 "N-000402" Po -570 0 $EndPAD $PAD @@ -8604,14 +8684,14 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 767 -1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 767 1112 $EndPAD $PAD @@ -8625,14 +8705,14 @@ $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 203 "N-000392" +Ne 219 "N-000408" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 204 "N-000393" +Ne 220 "N-000409" Po 0 1112 $EndPAD $PAD @@ -8674,14 +8754,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8709,7 +8789,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8730,14 +8810,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8765,7 +8845,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8793,7 +8873,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8814,14 +8894,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8849,7 +8929,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8877,7 +8957,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8898,14 +8978,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8933,7 +9013,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8961,7 +9041,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8989,7 +9069,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9017,7 +9097,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9045,7 +9125,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9073,7 +9153,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9101,7 +9181,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9129,7 +9209,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9157,7 +9237,7 @@ $PAD Sh "2" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9178,14 +9258,14 @@ $PAD Sh "1" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9213,7 +9293,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9241,7 +9321,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9269,7 +9349,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9297,7 +9377,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9325,7 +9405,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -9353,7 +9433,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9374,14 +9454,14 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9409,7 +9489,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9437,7 +9517,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9465,7 +9545,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9493,7 +9573,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -9521,7 +9601,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9549,7 +9629,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -9576,7 +9656,7 @@ $PAD Sh "8" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 206 "VCCO2" +Ne 222 "VCCO2" Po -750 -1050 $EndPAD $PAD @@ -9625,7 +9705,7 @@ $PAD Sh "4" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 750 1050 $EndPAD $SHAPE3D @@ -9659,7 +9739,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9687,7 +9767,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9715,7 +9795,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9743,7 +9823,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9771,7 +9851,7 @@ $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9799,7 +9879,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_A3.3V" +Ne 44 "/Ethernet_Phy/ETH_A3.3V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9827,7 +9907,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/Ethernet_Phy/ETH_A1.8V" +Ne 43 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9848,14 +9928,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/Ethernet_Phy/ETH_A1.8V" +Ne 43 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 48 "/Ethernet_Phy/ETH_PLL1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9876,7 +9956,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -176 0 $EndPAD $PAD @@ -9902,56 +9982,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 130 "/FPGA_Spartan6/R_M1_A0" +Ne 146 "/FPGA_Spartan6/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 131 "/FPGA_Spartan6/R_M1_A1" +Ne 147 "/FPGA_Spartan6/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 135 "/FPGA_Spartan6/R_M1_A2" +Ne 151 "/FPGA_Spartan6/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 136 "/FPGA_Spartan6/R_M1_A3" +Ne 152 "/FPGA_Spartan6/R_M1_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/DDR_Banks/M1_A3" +Ne 96 "/FPGA_Spartan6/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/FPGA_Spartan6/M1_A2" +Ne 95 "/FPGA_Spartan6/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 90 "/FPGA_Spartan6/M1_A1" +Ne 25 "/DDR_Banks/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 89 "/FPGA_Spartan6/M1_A0" +Ne 24 "/DDR_Banks/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -9970,56 +10050,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/FPGA_Spartan6/R_M1_RAS#" +Ne 181 "/FPGA_Spartan6/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/FPGA_Spartan6/R_M1_BA0" +Ne 158 "/FPGA_Spartan6/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/FPGA_Spartan6/R_M1_BA1" +Ne 159 "/FPGA_Spartan6/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 132 "/FPGA_Spartan6/R_M1_A10" +Ne 148 "/FPGA_Spartan6/R_M1_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 91 "/FPGA_Spartan6/M1_A10" +Ne 92 "/FPGA_Spartan6/M1_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M1_BA1" +Ne 30 "/DDR_Banks/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 100 "/FPGA_Spartan6/M1_BA0" +Ne 29 "/DDR_Banks/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 36 "/DDR_Banks/M1_RAS#" +Ne 113 "/FPGA_Spartan6/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10038,56 +10118,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/FPGA_Spartan6/R_M1_DQ4" +Ne 173 "/FPGA_Spartan6/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/FPGA_Spartan6/R_M1_DQ5" +Ne 174 "/FPGA_Spartan6/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/FPGA_Spartan6/R_M1_DQ6" +Ne 175 "/FPGA_Spartan6/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/FPGA_Spartan6/R_M1_DQ7" +Ne 176 "/FPGA_Spartan6/R_M1_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Banks/M1_DQ7" +Ne 37 "/DDR_Banks/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/DDR_Banks/M1_DQ6" +Ne 111 "/FPGA_Spartan6/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 112 "/FPGA_Spartan6/M1_DQ5" +Ne 110 "/FPGA_Spartan6/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 111 "/FPGA_Spartan6/M1_DQ4" +Ne 109 "/FPGA_Spartan6/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10106,56 +10186,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/FPGA_Spartan6/R_M1_LDQS" +Ne 180 "/FPGA_Spartan6/R_M1_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/FPGA_Spartan6/R_M1_LDM" +Ne 179 "/FPGA_Spartan6/R_M1_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/FPGA_Spartan6/R_M1_WE#" +Ne 184 "/FPGA_Spartan6/R_M1_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/FPGA_Spartan6/R_M1_CAS#" +Ne 160 "/FPGA_Spartan6/R_M1_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 101 "/FPGA_Spartan6/M1_CAS#" +Ne 31 "/DDR_Banks/M1_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_WE#" +Ne 114 "/FPGA_Spartan6/M1_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/DDR_Banks/M1_LDM" +Ne 39 "/DDR_Banks/M1_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/DDR_Banks/M1_LDQS" +Ne 40 "/DDR_Banks/M1_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10174,61 +10254,61 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 147 "/FPGA_Spartan6/R_M1_DQ0" +Ne 163 "/FPGA_Spartan6/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 148 "/FPGA_Spartan6/R_M1_DQ1" +Ne 164 "/FPGA_Spartan6/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/FPGA_Spartan6/R_M1_DQ2" +Ne 171 "/FPGA_Spartan6/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/FPGA_Spartan6/R_M1_DQ3" +Ne 172 "/FPGA_Spartan6/R_M1_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 110 "/FPGA_Spartan6/M1_DQ3" +Ne 108 "/FPGA_Spartan6/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 109 "/FPGA_Spartan6/M1_DQ2" +Ne 107 "/FPGA_Spartan6/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 106 "/FPGA_Spartan6/M1_DQ1" +Ne 102 "/FPGA_Spartan6/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 105 "/FPGA_Spartan6/M1_DQ0" +Ne 101 "/FPGA_Spartan6/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 $MODULE R_PACK4-0402 -Po 62795 30906 900 0 4C69A686 4C69DB1A ~~ +Po 62598 30906 900 0 4C69A686 4C69DB1A ~~ Li R_PACK4-0402 Sc 4C69DB1A AR /4C431A63/4C69DA8A @@ -10242,21 +10322,21 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 139 "/FPGA_Spartan6/R_M1_A7" +Ne 155 "/FPGA_Spartan6/R_M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 138 "/FPGA_Spartan6/R_M1_A6" +Ne 154 "/FPGA_Spartan6/R_M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 137 "/FPGA_Spartan6/R_M1_A5" +Ne 153 "/FPGA_Spartan6/R_M1_A5" Po 98 -177 $EndPAD $PAD @@ -10270,33 +10350,33 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Banks/M1_A4" +Ne 97 "/FPGA_Spartan6/M1_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/FPGA_Spartan6/M1_A5" +Ne 26 "/DDR_Banks/M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 96 "/FPGA_Spartan6/M1_A6" +Ne 98 "/FPGA_Spartan6/M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 97 "/FPGA_Spartan6/M1_A7" +Ne 27 "/DDR_Banks/M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 $MODULE R_PACK4-0402 -Po 62795 32087 900 0 4C69A686 4C69DCB4 ~~ +Po 62598 31890 900 0 4C69A686 4C69DCB4 ~~ Li R_PACK4-0402 Sc 4C69DCB4 AR /4C431A63/4C69DC05 @@ -10310,35 +10390,35 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 134 "/FPGA_Spartan6/R_M1_A12" +Ne 150 "/FPGA_Spartan6/R_M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 133 "/FPGA_Spartan6/R_M1_A11" +Ne 149 "/FPGA_Spartan6/R_M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 141 "/FPGA_Spartan6/R_M1_A9" +Ne 157 "/FPGA_Spartan6/R_M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 140 "/FPGA_Spartan6/R_M1_A8" +Ne 156 "/FPGA_Spartan6/R_M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 98 "/FPGA_Spartan6/M1_A8" +Ne 28 "/DDR_Banks/M1_A8" Po 295 177 $EndPAD $PAD @@ -10352,14 +10432,14 @@ $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 92 "/FPGA_Spartan6/M1_A11" +Ne 93 "/FPGA_Spartan6/M1_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 93 "/FPGA_Spartan6/M1_A12" +Ne 94 "/FPGA_Spartan6/M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10380,19 +10460,19 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/FPGA_Spartan6/M1_CLK#" +Ne 33 "/DDR_Banks/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Banks/M1_CLK" +Ne 100 "/FPGA_Spartan6/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE R_PACK4-0402 -Po 63189 36417 900 0 4C69A686 4C69E3EE ~~ +Po 62598 36614 900 0 4C69A686 4C69E3EE ~~ Li R_PACK4-0402 Sc 4C69E3EE AR /4C431A63/4C69E3A6 @@ -10406,61 +10486,61 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/FPGA_Spartan6/R_M1_DQ11" +Ne 166 "/FPGA_Spartan6/R_M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/FPGA_Spartan6/R_M1_DQ10" +Ne 165 "/FPGA_Spartan6/R_M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/FPGA_Spartan6/R_M1_DQ9" +Ne 178 "/FPGA_Spartan6/R_M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/FPGA_Spartan6/R_M1_DQ8" +Ne 177 "/FPGA_Spartan6/R_M1_DQ8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 113 "/FPGA_Spartan6/M1_DQ8" +Ne 112 "/FPGA_Spartan6/M1_DQ8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_DQ9" +Ne 38 "/DDR_Banks/M1_DQ9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Banks/M1_DQ10" +Ne 35 "/DDR_Banks/M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/FPGA_Spartan6/M1_DQ11" +Ne 36 "/DDR_Banks/M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 $MODULE R_PACK4-0402 -Po 63189 37992 900 0 4C69A686 4C69E3ED ~~ +Po 62598 38189 900 0 4C69A686 4C69E3ED ~~ Li R_PACK4-0402 Sc 4C69E3ED AR /4C431A63/4C69E299 @@ -10474,56 +10554,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 154 "/FPGA_Spartan6/R_M1_DQ15" +Ne 170 "/FPGA_Spartan6/R_M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/FPGA_Spartan6/R_M1_DQ14" +Ne 169 "/FPGA_Spartan6/R_M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 152 "/FPGA_Spartan6/R_M1_DQ13" +Ne 168 "/FPGA_Spartan6/R_M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 151 "/FPGA_Spartan6/R_M1_DQ12" +Ne 167 "/FPGA_Spartan6/R_M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M1_DQ12" +Ne 103 "/FPGA_Spartan6/M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 108 "/FPGA_Spartan6/M1_DQ13" +Ne 104 "/FPGA_Spartan6/M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/DDR_Banks/M1_DQ14" +Ne 105 "/FPGA_Spartan6/M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Banks/M1_DQ15" +Ne 106 "/FPGA_Spartan6/M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -10544,14 +10624,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/FPGA_Spartan6/R_M1_UDM" +Ne 182 "/FPGA_Spartan6/R_M1_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 114 "/FPGA_Spartan6/M1_UDM" +Ne 41 "/DDR_Banks/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10572,19 +10652,19 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 145 "/FPGA_Spartan6/R_M1_CKE" +Ne 161 "/FPGA_Spartan6/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 102 "/FPGA_Spartan6/M1_CKE" +Ne 32 "/DDR_Banks/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 63780 32677 0 0 4C5FF890 4C69EB27 ~~ +Po 62598 32677 0 0 4C5FF890 4C69EB27 ~~ Li 0402 Sc 4C69EB27 AR /4C431A63/4C69E92D @@ -10600,14 +10680,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 146 "/FPGA_Spartan6/R_M1_CS#" +Ne 162 "/FPGA_Spartan6/R_M1_CS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/FPGA_Spartan6/M1_CS#" +Ne 34 "/DDR_Banks/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10628,14 +10708,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/FPGA_Spartan6/R_M1_UDQS" +Ne 183 "/FPGA_Spartan6/R_M1_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 37 "/DDR_Banks/M1_UDQS" +Ne 42 "/DDR_Banks/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -10657,28 +10737,28 @@ $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po -235 -235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 235 -235 $EndPAD $PAD @@ -10790,7 +10870,7 @@ $PAD Sh "8" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "GND" +Ne 201 "GND" Po 688 0 $EndPAD $PAD @@ -10822,6 +10902,278 @@ Ne 0 "" Po 688 393 $EndPAD $EndMODULE MLF20m1 +$MODULE R_PACK4-0402 +Po 47638 37598 2700 0 4C69A686 4C6A0394 ~~ +Li R_PACK4-0402 +Sc 4C6A0394 +AR /4C431A63/4C69FC19 +Op 0 0 0 +T0 117 451 197 197 2700 49 M V 20 N"RP10" +T1 68 -436 157 157 2700 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 134 "/FPGA_Spartan6/R_M0_DQ12" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 135 "/FPGA_Spartan6/R_M0_DQ13" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 136 "/FPGA_Spartan6/R_M0_DQ14" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 137 "/FPGA_Spartan6/R_M0_DQ15" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 84 "/FPGA_Spartan6/M0_DQ15" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 16 "/DDR_Banks/M0_DQ14" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 83 "/FPGA_Spartan6/M0_DQ13" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 15 "/DDR_Banks/M0_DQ12" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 47638 36614 2700 0 4C69A686 4C6A0396 ~~ +Li R_PACK4-0402 +Sc 4C6A0396 +AR /4C431A63/4C69FCE6 +Op 0 0 0 +T0 117 451 197 197 2700 49 M V 20 N"RP11" +T1 68 -436 157 157 2700 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 144 "/FPGA_Spartan6/R_M0_DQ8" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 145 "/FPGA_Spartan6/R_M0_DQ9" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 132 "/FPGA_Spartan6/R_M0_DQ10" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 133 "/FPGA_Spartan6/R_M0_DQ11" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 82 "/FPGA_Spartan6/M0_DQ11" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 14 "/DDR_Banks/M0_DQ10" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 21 "/DDR_Banks/M0_DQ9" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 20 "/DDR_Banks/M0_DQ8" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 50000 37205 900 0 4C69A686 4C6A0398 ~~ +Li R_PACK4-0402 +Sc 4C6A0398 +AR /4C431A63/4C69FCE7 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP13" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 130 "/FPGA_Spartan6/R_M0_DQ0" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 131 "/FPGA_Spartan6/R_M0_DQ1" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 138 "/FPGA_Spartan6/R_M0_DQ2" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 139 "/FPGA_Spartan6/R_M0_DQ3" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 85 "/FPGA_Spartan6/M0_DQ3" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 17 "/DDR_Banks/M0_DQ2" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 13 "/DDR_Banks/M0_DQ1" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 12 "/DDR_Banks/M0_DQ0" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 50000 36220 900 0 4C69A686 4C6A039A ~~ +Li R_PACK4-0402 +Sc 4C6A039A +AR /4C431A63/4C69FCE8 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP12" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 140 "/FPGA_Spartan6/R_M0_DQ4" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 141 "/FPGA_Spartan6/R_M0_DQ5" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 142 "/FPGA_Spartan6/R_M0_DQ6" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 143 "/FPGA_Spartan6/R_M0_DQ7" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 87 "/FPGA_Spartan6/M0_DQ7" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 19 "/DDR_Banks/M0_DQ6" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 86 "/FPGA_Spartan6/M0_DQ5" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 18 "/DDR_Banks/M0_DQ4" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 $COTATION Ge 0 25 0 Va 35827 diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp index b249993..cbf5ece 100644 --- a/kicad/xue-rnc/xue-rnc.cmp +++ b/kicad/xue-rnc/xue-rnc.cmp @@ -1,4 +1,4 @@ -Cmp-Mod V01 Genere par PcbNew le Mon 16 Aug 2010 08:22:44 PM COT +Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Mon 16 Aug 2010 10:05:53 PM COT BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; @@ -721,6 +721,34 @@ ValeurCmp = 120; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C431A63/4C69E7F8; +Reference = R17; +ValeurCmp = 33; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C69E7C2; +Reference = R18; +ValeurCmp = 33; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C69E7DD; +Reference = R19; +ValeurCmp = 33; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C431A63/4C69E92D; +Reference = R20; +ValeurCmp = 33; +IdModule = 0402; +EndCmp + BeginCmp TimeStamp = /4C431A63/4C69C6B2; Reference = RP1; @@ -784,6 +812,13 @@ ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp +BeginCmp +TimeStamp = /4C431A63/4C69FC19; +Reference = RP10; +ValeurCmp = R_PACK4; +IdModule = R_PACK4-0402; +EndCmp + BeginCmp TimeStamp = /4C431A63/4C431E53; Reference = U1; @@ -840,6 +875,13 @@ ValeurCmp = X25X64MB; IdModule = SO8E; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4C69EE11; +Reference = U9; +ValeurCmp = ATTINY24A-MLF; +IdModule = MLF20m1; +EndCmp + BeginCmp TimeStamp = /4C5F1EDC/4C5F2CA7; Reference = V1; diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 57c543f..4c667d9 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,4 +1,4 @@ -# EESchema Netlist Version 1.1 created Mon 16 Aug 2010 09:46:17 PM COT +# EESchema Netlist Version 1.1 created Mon 16 Aug 2010 10:43:52 PM COT ( ( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF} ( PAD GND ) @@ -54,10 +54,10 @@ ( COM GND ) ( CD ? ) ( 1 /Non_volatile_memories/SD_DAT2 ) - ( 2 /Non_volatile_memories/SD_DAT3 ) + ( 2 /FPGA_Spartan6/SD_DAT3 ) ( 3 /Non_volatile_memories/SD_CMD ) ( 4 +3.3V ) - ( 5 /FPGA_Spartan6/SD_CLK ) + ( 5 /Non_volatile_memories/SD_CLK ) ( 6 GND ) ( 7 /Non_volatile_memories/SD_DAT0 ) ( 8 /Non_volatile_memories/SD_DAT1 ) @@ -71,7 +71,7 @@ ( 6 /FPGA_Spartan6/NF_RNB ) ( 7 /FPGA_Spartan6/NF_RNB ) ( 8 /FPGA_Spartan6/NF_RE_N ) - ( 9 /Non_volatile_memories/NF_CS1_N ) + ( 9 /FPGA_Spartan6/NF_CS1_N ) ( 10 ? ) ( 11 ? ) ( 12 +3.3V ) @@ -91,8 +91,8 @@ ( 26 ? ) ( 27 ? ) ( 28 ? ) - ( 29 /FPGA_Spartan6/NF_D0 ) - ( 30 /Non_volatile_memories/NF_D1 ) + ( 29 /Non_volatile_memories/NF_D0 ) + ( 30 /FPGA_Spartan6/NF_D1 ) ( 31 /FPGA_Spartan6/NF_D2 ) ( 32 /Non_volatile_memories/NF_D3 ) ( 33 ? ) @@ -103,9 +103,9 @@ ( 38 ? ) ( 39 ? ) ( 40 ? ) - ( 41 /FPGA_Spartan6/NF_D4 ) - ( 42 /Non_volatile_memories/NF_D5 ) - ( 43 /FPGA_Spartan6/NF_D6 ) + ( 41 /Non_volatile_memories/NF_D4 ) + ( 42 /FPGA_Spartan6/NF_D5 ) + ( 43 /Non_volatile_memories/NF_D6 ) ( 44 /FPGA_Spartan6/NF_D7 ) ( 45 ? ) ( 46 ? ) @@ -121,8 +121,8 @@ ( 7 GND ) ( 8 GND ) ( 9 ? ) - ( 10 N-000392 ) - ( 11 N-000393 ) + ( 10 N-000408 ) + ( 11 N-000409 ) ( 12 +3.3V ) ( 14 +3.3V ) ) @@ -139,23 +139,23 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552BA $noname F2 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000386 ) + ( 1 N-000402 ) ( 2 +5V ) ) ( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000392 ) + ( 1 N-000408 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000393 ) + ( 1 N-000409 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C} - ( 1 N-000394 ) + ( 1 N-000410 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R} - ( 1 N-000394 ) + ( 1 N-000410 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} @@ -163,46 +163,46 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552B0 0603 L6 FB {Lib=INDUCTOR} - ( 1 N-000386 ) + ( 1 N-000402 ) ( 2 ? ) ) ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000389 ) - ( 2 N-000390 ) + ( 1 N-000405 ) + ( 2 N-000406 ) ) ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000384 ) + ( 1 N-000400 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000385 ) + ( 1 N-000401 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000385 ) + ( 1 N-000401 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000391 ) + ( 1 N-000407 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000383 ) + ( 1 N-000399 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000389 ) + ( 1 N-000405 ) ( 2 +5V ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000385 ) - ( S2 N-000385 ) - ( S3 N-000385 ) - ( S4 N-000385 ) - ( 1 N-000390 ) - ( 2 N-000383 ) - ( 3 N-000391 ) - ( 4 N-000384 ) + ( S1 N-000401 ) + ( S2 N-000401 ) + ( S3 N-000401 ) + ( S4 N-000401 ) + ( 1 N-000406 ) + ( 2 N-000399 ) + ( 3 N-000407 ) + ( 4 N-000400 ) ) ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} ( 1 +2.5V ) @@ -219,32 +219,72 @@ ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) ( 2 /USB/USBA_SPD ) - ( 3 /FPGA_Spartan6/USBA_RCV ) - ( 4 /USB/USBA_VP ) - ( 5 /FPGA_Spartan6/USBA_VM ) + ( 3 /USB/USBA_RCV ) + ( 4 /FPGA_Spartan6/USBA_VP ) + ( 5 /USB/USBA_VM ) ( 7 GND ) ( 8 GND ) ( 9 /USB/USBA_OE_N ) - ( 10 N-000383 ) - ( 11 N-000391 ) + ( 10 N-000399 ) + ( 11 N-000407 ) ( 12 +3.3V ) ( 14 +3.3V ) ) + ( /4C431A63/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_DQ4 ) + ( 2 /FPGA_Spartan6/R_M0_DQ5 ) + ( 3 /FPGA_Spartan6/R_M0_DQ6 ) + ( 4 /FPGA_Spartan6/R_M0_DQ7 ) + ( 5 /FPGA_Spartan6/M0_DQ7 ) + ( 6 /DDR_Banks/M0_DQ6 ) + ( 7 /FPGA_Spartan6/M0_DQ5 ) + ( 8 /DDR_Banks/M0_DQ4 ) + ) + ( /4C431A63/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_DQ0 ) + ( 2 /FPGA_Spartan6/R_M0_DQ1 ) + ( 3 /FPGA_Spartan6/R_M0_DQ2 ) + ( 4 /FPGA_Spartan6/R_M0_DQ3 ) + ( 5 /FPGA_Spartan6/M0_DQ3 ) + ( 6 /DDR_Banks/M0_DQ2 ) + ( 7 /DDR_Banks/M0_DQ1 ) + ( 8 /DDR_Banks/M0_DQ0 ) + ) + ( /4C431A63/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_DQ8 ) + ( 2 /FPGA_Spartan6/R_M0_DQ9 ) + ( 3 /FPGA_Spartan6/R_M0_DQ10 ) + ( 4 /FPGA_Spartan6/R_M0_DQ11 ) + ( 5 /FPGA_Spartan6/M0_DQ11 ) + ( 6 /DDR_Banks/M0_DQ10 ) + ( 7 /DDR_Banks/M0_DQ9 ) + ( 8 /DDR_Banks/M0_DQ8 ) + ) + ( /4C431A63/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4} + ( 1 /FPGA_Spartan6/R_M0_DQ12 ) + ( 2 /FPGA_Spartan6/R_M0_DQ13 ) + ( 3 /FPGA_Spartan6/R_M0_DQ14 ) + ( 4 /FPGA_Spartan6/R_M0_DQ15 ) + ( 5 /FPGA_Spartan6/M0_DQ15 ) + ( 6 /DDR_Banks/M0_DQ14 ) + ( 7 /FPGA_Spartan6/M0_DQ13 ) + ( 8 /DDR_Banks/M0_DQ12 ) + ) ( /4C431A63/4C69E7DD 0402 R19 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_UDQS ) ( 2 /DDR_Banks/M1_UDQS ) ) ( /4C431A63/4C69E92D 0402 R20 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CS# ) - ( 2 /FPGA_Spartan6/M1_CS# ) + ( 2 /DDR_Banks/M1_CS# ) ) ( /4C431A63/4C69E7F8 0402 R17 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CKE ) - ( 2 /FPGA_Spartan6/M1_CKE ) + ( 2 /DDR_Banks/M1_CKE ) ) ( /4C431A63/4C69E7C2 0402 R18 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_UDM ) - ( 2 /FPGA_Spartan6/M1_UDM ) + ( 2 /DDR_Banks/M1_UDM ) ) ( /4C431A63/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ11 ) @@ -254,28 +294,28 @@ ( 5 /FPGA_Spartan6/M1_DQ8 ) ( 6 /DDR_Banks/M1_DQ9 ) ( 7 /DDR_Banks/M1_DQ10 ) - ( 8 /FPGA_Spartan6/M1_DQ11 ) + ( 8 /DDR_Banks/M1_DQ11 ) ) ( /4C431A63/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ15 ) ( 2 /FPGA_Spartan6/R_M1_DQ14 ) ( 3 /FPGA_Spartan6/R_M1_DQ13 ) ( 4 /FPGA_Spartan6/R_M1_DQ12 ) - ( 5 /DDR_Banks/M1_DQ12 ) + ( 5 /FPGA_Spartan6/M1_DQ12 ) ( 6 /FPGA_Spartan6/M1_DQ13 ) - ( 7 /DDR_Banks/M1_DQ14 ) - ( 8 /DDR_Banks/M1_DQ15 ) + ( 7 /FPGA_Spartan6/M1_DQ14 ) + ( 8 /FPGA_Spartan6/M1_DQ15 ) ) ( /4C431A63/4C69DF7A 0402 R16 120 {Lib=R} - ( 1 /FPGA_Spartan6/M1_CLK# ) - ( 2 /DDR_Banks/M1_CLK ) + ( 1 /DDR_Banks/M1_CLK# ) + ( 2 /FPGA_Spartan6/M1_CLK ) ) ( /4C431A63/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A12 ) ( 2 /FPGA_Spartan6/R_M1_A11 ) ( 3 /FPGA_Spartan6/R_M1_A9 ) ( 4 /FPGA_Spartan6/R_M1_A8 ) - ( 5 /FPGA_Spartan6/M1_A8 ) + ( 5 /DDR_Banks/M1_A8 ) ( 6 /FPGA_Spartan6/M1_A9 ) ( 7 /FPGA_Spartan6/M1_A11 ) ( 8 /FPGA_Spartan6/M1_A12 ) @@ -285,10 +325,10 @@ ( 2 /FPGA_Spartan6/R_M1_A6 ) ( 3 /FPGA_Spartan6/R_M1_A5 ) ( 4 ? ) - ( 5 /DDR_Banks/M1_A4 ) - ( 6 /FPGA_Spartan6/M1_A5 ) + ( 5 /FPGA_Spartan6/M1_A4 ) + ( 6 /DDR_Banks/M1_A5 ) ( 7 /FPGA_Spartan6/M1_A6 ) - ( 8 /FPGA_Spartan6/M1_A7 ) + ( 8 /DDR_Banks/M1_A7 ) ) ( /4C431A63/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ0 ) @@ -305,8 +345,8 @@ ( 2 /FPGA_Spartan6/R_M1_LDM ) ( 3 /FPGA_Spartan6/R_M1_WE# ) ( 4 /FPGA_Spartan6/R_M1_CAS# ) - ( 5 /FPGA_Spartan6/M1_CAS# ) - ( 6 /DDR_Banks/M1_WE# ) + ( 5 /DDR_Banks/M1_CAS# ) + ( 6 /FPGA_Spartan6/M1_WE# ) ( 7 /DDR_Banks/M1_LDM ) ( 8 /DDR_Banks/M1_LDQS ) ) @@ -316,7 +356,7 @@ ( 3 /FPGA_Spartan6/R_M1_DQ6 ) ( 4 /FPGA_Spartan6/R_M1_DQ7 ) ( 5 /DDR_Banks/M1_DQ7 ) - ( 6 /DDR_Banks/M1_DQ6 ) + ( 6 /FPGA_Spartan6/M1_DQ6 ) ( 7 /FPGA_Spartan6/M1_DQ5 ) ( 8 /FPGA_Spartan6/M1_DQ4 ) ) @@ -327,18 +367,18 @@ ( 4 /FPGA_Spartan6/R_M1_A10 ) ( 5 /FPGA_Spartan6/M1_A10 ) ( 6 /DDR_Banks/M1_BA1 ) - ( 7 /FPGA_Spartan6/M1_BA0 ) - ( 8 /DDR_Banks/M1_RAS# ) + ( 7 /DDR_Banks/M1_BA0 ) + ( 8 /FPGA_Spartan6/M1_RAS# ) ) ( /4C431A63/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A0 ) ( 2 /FPGA_Spartan6/R_M1_A1 ) ( 3 /FPGA_Spartan6/R_M1_A2 ) ( 4 /FPGA_Spartan6/R_M1_A3 ) - ( 5 /DDR_Banks/M1_A3 ) + ( 5 /FPGA_Spartan6/M1_A3 ) ( 6 /FPGA_Spartan6/M1_A2 ) - ( 7 /FPGA_Spartan6/M1_A1 ) - ( 8 /FPGA_Spartan6/M1_A0 ) + ( 7 /DDR_Banks/M1_A1 ) + ( 8 /DDR_Banks/M1_A0 ) ) ( /4C431A63/4C656D9D $noname C66 470nF {Lib=C} ( 1 +2.5V ) @@ -480,7 +520,7 @@ ( L6 ? ) ( K6 /FPGA_Spartan6/M0_A3 ) ( J6 ? ) - ( H6 /DDR_Banks/M0_A7 ) + ( H6 /FPGA_Spartan6/M0_A7 ) ( G6 ? ) ( F6 +2.5V ) ( E6 ? ) @@ -488,7 +528,7 @@ ( P5 ? ) ( N5 +2.5V ) ( M5 ? ) - ( K5 /DDR_Banks/M0_RAS# ) + ( K5 /FPGA_Spartan6/M0_RAS# ) ( J5 +2.5V ) ( H5 /FPGA_Spartan6/M0_A2 ) ( F5 ? ) @@ -514,7 +554,7 @@ ( L20 /FPGA_Spartan6/R_M1_LDQS ) ( K20 /FPGA_Spartan6/R_M1_A5 ) ( J20 /FPGA_Spartan6/R_M1_DQ4 ) - ( H20 /DDR_Banks/M1_CLK ) + ( H20 /FPGA_Spartan6/M1_CLK ) ( G20 /FPGA_Spartan6/R_M1_A3 ) ( F20 ? ) ( E20 /FPGA_Spartan6/R_M1_A7 ) @@ -527,33 +567,33 @@ ( K8 ? ) ( Y2 ? ) ( W2 +2.5V ) - ( V2 /FPGA_Spartan6/M0_DQ14 ) + ( V2 /FPGA_Spartan6/R_M0_DQ14 ) ( T2 /DDR_Banks/M0_UDQS ) ( R2 +2.5V ) - ( P2 /FPGA_Spartan6/M0_DQ8 ) - ( M2 /FPGA_Spartan6/M0_DQ2 ) + ( P2 /FPGA_Spartan6/R_M0_DQ8 ) + ( M2 /FPGA_Spartan6/R_M0_DQ2 ) ( L2 +2.5V ) - ( K2 /FPGA_Spartan6/M0_DQ6 ) - ( H2 /FPGA_Spartan6/M0_A0 ) + ( K2 /FPGA_Spartan6/R_M0_DQ6 ) + ( H2 /DDR_Banks/M0_A0 ) ( G2 +2.5V ) ( F2 /DDR_Banks/M0_WE# ) - ( D2 /FPGA_Spartan6/M0_CKE ) + ( D2 /DDR_Banks/M0_CKE ) ( C2 +2.5V ) ( B2 ? ) ( A2 ? ) ( Y1 ? ) ( W1 ? ) - ( V1 /FPGA_Spartan6/M0_DQ15 ) - ( U1 /DDR_Banks/M0_DQ13 ) + ( V1 /FPGA_Spartan6/R_M0_DQ15 ) + ( U1 /FPGA_Spartan6/R_M0_DQ13 ) ( T1 ? ) - ( R1 /FPGA_Spartan6/M0_DQ11 ) - ( P1 /DDR_Banks/M0_DQ9 ) - ( N1 /FPGA_Spartan6/M0_DQ1 ) - ( M1 /FPGA_Spartan6/M0_DQ3 ) + ( R1 /FPGA_Spartan6/R_M0_DQ11 ) + ( P1 /FPGA_Spartan6/R_M0_DQ9 ) + ( N1 /FPGA_Spartan6/R_M0_DQ1 ) + ( M1 /FPGA_Spartan6/R_M0_DQ3 ) ( L1 ? ) - ( K1 /DDR_Banks/M0_DQ7 ) - ( J1 /DDR_Banks/M0_DQ5 ) - ( H1 /DDR_Banks/M0_A1 ) + ( K1 /FPGA_Spartan6/R_M0_DQ7 ) + ( J1 /FPGA_Spartan6/R_M0_DQ5 ) + ( H1 /FPGA_Spartan6/M0_A1 ) ( G1 /DDR_Banks/M0_BA1 ) ( T4 ? ) ( R4 ? ) @@ -563,50 +603,50 @@ ( L4 /FPGA_Spartan6/M0_LDM ) ( K4 /FPGA_Spartan6/M0_CAS# ) ( J4 /FPGA_Spartan6/M0_A6 ) - ( H4 /FPGA_Spartan6/M0_CLK ) - ( G4 /FPGA_Spartan6/M0_A10 ) + ( H4 /DDR_Banks/M0_CLK ) + ( G4 /DDR_Banks/M0_A10 ) ( F4 +2.5V ) ( E4 ? ) ( C4 ? ) ( W3 ? ) ( V3 ? ) - ( U3 /FPGA_Spartan6/M0_DQ12 ) + ( U3 /FPGA_Spartan6/R_M0_DQ12 ) ( T3 ? ) - ( R3 /FPGA_Spartan6/M0_DQ10 ) + ( R3 /FPGA_Spartan6/R_M0_DQ10 ) ( P3 ? ) - ( N3 /FPGA_Spartan6/M0_DQ0 ) - ( M3 /DDR_Banks/M0_UDM ) - ( L3 /DDR_Banks/M0_LDQS ) - ( K3 /DDR_Banks/M0_A5 ) - ( J3 /DDR_Banks/M0_DQ4 ) + ( N3 /FPGA_Spartan6/R_M0_DQ0 ) + ( M3 /FPGA_Spartan6/M0_UDM ) + ( L3 /FPGA_Spartan6/M0_LDQS ) + ( K3 /FPGA_Spartan6/M0_A5 ) + ( J3 /FPGA_Spartan6/R_M0_DQ4 ) ( H3 /DDR_Banks/M0_CLK# ) - ( G3 /DDR_Banks/M0_BA0 ) + ( G3 /FPGA_Spartan6/M0_BA0 ) ( F3 /FPGA_Spartan6/M0_A4 ) ( E3 /FPGA_Spartan6/M0_A8 ) ( D3 ? ) ( C3 ? ) ( B3 ? ) ( G10 +3.3V ) - ( D10 /Ethernet_Phy/ETH_MDC ) - ( C10 /Ethernet_Phy/ETH_CRS ) - ( B10 /FPGA_Spartan6/ETH_COL ) - ( A10 /Ethernet_Phy/ETH_INT ) + ( D10 /FPGA_Spartan6/ETH_MDC ) + ( C10 /FPGA_Spartan6/ETH_CRS ) + ( B10 /Ethernet_Phy/ETH_COL ) + ( A10 /FPGA_Spartan6/ETH_INT ) ( E9 +3.3V ) ( D9 /FPGA_Spartan6/ETH_TXD0 ) - ( C9 /Ethernet_Phy/ETH_TXD2 ) - ( A9 /FPGA_Spartan6/ETH_TXD3 ) - ( D8 /FPGA_Spartan6/ETH_RXC ) + ( C9 /FPGA_Spartan6/ETH_TXD2 ) + ( A9 /Ethernet_Phy/ETH_TXD3 ) + ( D8 /Ethernet_Phy/ETH_RXC ) ( C8 /FPGA_Spartan6/ETH_TXD1 ) - ( B8 /FPGA_Spartan6/ETH_TXER ) - ( A8 /Ethernet_Phy/ETH_TXEN ) - ( D7 /Ethernet_Phy/ETH_TXC ) + ( B8 /Ethernet_Phy/ETH_TXER ) + ( A8 /FPGA_Spartan6/ETH_TXEN ) + ( D7 /FPGA_Spartan6/ETH_TXC ) ( C7 /FPGA_Spartan6/ETH_RXDV ) ( B7 +3.3V ) - ( A7 /FPGA_Spartan6/ETH_RXER ) + ( A7 /Ethernet_Phy/ETH_RXER ) ( D6 /Ethernet_Phy/ETH_RXD3 ) - ( C6 /FPGA_Spartan6/ETH_RXD2 ) + ( C6 /Ethernet_Phy/ETH_RXD2 ) ( B6 /Ethernet_Phy/ETH_RXD1 ) - ( A6 /FPGA_Spartan6/ETH_RXD0 ) + ( A6 /Ethernet_Phy/ETH_RXD0 ) ( C5 /FPGA_Spartan6/ETH_MDIO ) ( A5 /FPGA_Spartan6/ETH_RESET_N ) ( B4 +3.3V ) @@ -621,10 +661,10 @@ ( A18 /Non_volatile_memories/SD_DAT0 ) ( E17 +3.3V ) ( D17 /Non_volatile_memories/SD_CMD ) - ( C17 /Non_volatile_memories/SD_DAT3 ) + ( C17 /FPGA_Spartan6/SD_DAT3 ) ( A17 /Non_volatile_memories/SD_DAT2 ) - ( E16 /FPGA_Spartan6/SD_CLK ) - ( C16 /Non_volatile_memories/NF_CS1_N ) + ( E16 /Non_volatile_memories/SD_CLK ) + ( C16 /FPGA_Spartan6/NF_CS1_N ) ( B16 /FPGA_Spartan6/NF_RE_N ) ( A16 /FPGA_Spartan6/NF_RNB ) ( D15 /FPGA_Spartan6/NF_CLE ) @@ -632,17 +672,17 @@ ( B15 +3.3V ) ( A15 /Non_volatile_memories/NF_ALE ) ( G14 +3.3V ) - ( D14 /FPGA_Spartan6/NF_D0 ) + ( D14 /Non_volatile_memories/NF_D0 ) ( C14 ? ) ( B14 ? ) ( A14 ? ) ( E13 +3.3V ) ( C13 /FPGA_Spartan6/NF_D2 ) - ( A13 /Non_volatile_memories/NF_D1 ) - ( C12 /Non_volatile_memories/NF_D5 ) - ( B12 /FPGA_Spartan6/NF_D4 ) + ( A13 /FPGA_Spartan6/NF_D1 ) + ( C12 /FPGA_Spartan6/NF_D5 ) + ( B12 /Non_volatile_memories/NF_D4 ) ( A12 /Non_volatile_memories/NF_D3 ) - ( D11 /FPGA_Spartan6/NF_D6 ) + ( D11 /Non_volatile_memories/NF_D6 ) ( C11 ? ) ( B11 +3.3V ) ( A11 /FPGA_Spartan6/NF_D7 ) @@ -680,7 +720,7 @@ ( M19 ? ) ( L19 /FPGA_Spartan6/R_M1_LDM ) ( K19 /FPGA_Spartan6/R_M1_A6 ) - ( J19 /FPGA_Spartan6/M1_CLK# ) + ( J19 /DDR_Banks/M1_CLK# ) ( H19 /FPGA_Spartan6/R_M1_WE# ) ( G19 /FPGA_Spartan6/R_M1_A10 ) ( F19 /FPGA_Spartan6/R_M1_A11 ) @@ -690,12 +730,12 @@ ( U18 +2.5V ) ( P18 /USB/USBA_OE_N ) ( N18 +2.5V ) - ( M18 /FPGA_Spartan6/USBA_VM ) + ( M18 /USB/USBA_VM ) ( K18 ? ) ( J18 +2.5V ) ( H18 ? ) ( F18 ? ) - ( P17 /USB/USBA_VP ) + ( P17 /FPGA_Spartan6/USBA_VP ) ( M17 ? ) ( L17 ? ) ( K17 /FPGA_Spartan6/R_M1_BA1 ) @@ -703,7 +743,7 @@ ( H17 ? ) ( G17 ? ) ( F17 ? ) - ( N16 /FPGA_Spartan6/USBA_RCV ) + ( N16 /USB/USBA_RCV ) ( M16 ? ) ( L16 +2.5V ) ( K16 ? ) @@ -861,7 +901,7 @@ ( F1 ? ) ( E1 /FPGA_Spartan6/M0_A9 ) ( D1 /FPGA_Spartan6/M0_A12 ) - ( C1 /DDR_Banks/M0_A11 ) + ( C1 /FPGA_Spartan6/M0_A11 ) ( B1 ? ) ( AB19 ? ) ( AA19 VCCO2 ) @@ -1003,7 +1043,7 @@ ( 2 +3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000358 ) + ( 1 N-000374 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} @@ -1015,55 +1055,55 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000376 ) + ( 1 N-000392 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000376 ) + ( 1 N-000392 ) ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} ( 1 /FPGA_Spartan6/ETH_MDIO ) - ( 2 /Ethernet_Phy/ETH_MDC ) + ( 2 /FPGA_Spartan6/ETH_MDC ) ( 3 /Ethernet_Phy/ETH_RXD3 ) - ( 4 /FPGA_Spartan6/ETH_RXD2 ) + ( 4 /Ethernet_Phy/ETH_RXD2 ) ( 5 /Ethernet_Phy/ETH_RXD1 ) - ( 6 /FPGA_Spartan6/ETH_RXD0 ) + ( 6 /Ethernet_Phy/ETH_RXD0 ) ( 7 +3.3V ) ( 8 GND ) ( 9 /FPGA_Spartan6/ETH_RXDV ) - ( 10 /FPGA_Spartan6/ETH_RXC ) - ( 11 /FPGA_Spartan6/ETH_RXER ) + ( 10 /Ethernet_Phy/ETH_RXC ) + ( 11 /Ethernet_Phy/ETH_RXER ) ( 12 GND ) ( 13 +1.8V ) - ( 14 /FPGA_Spartan6/ETH_TXER ) - ( 15 /Ethernet_Phy/ETH_TXC ) - ( 16 /Ethernet_Phy/ETH_TXEN ) + ( 14 /Ethernet_Phy/ETH_TXER ) + ( 15 /FPGA_Spartan6/ETH_TXC ) + ( 16 /FPGA_Spartan6/ETH_TXEN ) ( 17 /FPGA_Spartan6/ETH_TXD0 ) ( 18 /FPGA_Spartan6/ETH_TXD1 ) - ( 19 /Ethernet_Phy/ETH_TXD2 ) - ( 20 /FPGA_Spartan6/ETH_TXD3 ) - ( 21 /FPGA_Spartan6/ETH_COL ) - ( 22 /Ethernet_Phy/ETH_CRS ) + ( 19 /FPGA_Spartan6/ETH_TXD2 ) + ( 20 /Ethernet_Phy/ETH_TXD3 ) + ( 21 /Ethernet_Phy/ETH_COL ) + ( 22 /FPGA_Spartan6/ETH_CRS ) ( 23 GND ) ( 24 +3.3V ) - ( 25 /Ethernet_Phy/ETH_INT ) + ( 25 /FPGA_Spartan6/ETH_INT ) ( 26 /Ethernet_Phy/ETH_LED0 ) ( 27 /Ethernet_Phy/ETH_LED1 ) ( 28 ? ) ( 29 ? ) ( 30 ? ) ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000373 ) - ( 33 N-000371 ) + ( 32 N-000389 ) + ( 33 N-000387 ) ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000358 ) + ( 37 N-000374 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) - ( 40 N-000372 ) - ( 41 N-000370 ) + ( 40 N-000388 ) + ( 41 N-000386 ) ( 42 ? ) ( 43 ? ) ( 44 GND ) @@ -1074,43 +1114,43 @@ ) ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000370 ) + ( 2 N-000386 ) ) ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000372 ) + ( 2 N-000388 ) ) ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000373 ) + ( 2 N-000389 ) ) ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000371 ) + ( 2 N-000387 ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000361 ) + ( 1 N-000377 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000374 ) + ( 1 N-000390 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000370 ) - ( 2 N-000372 ) + ( 1 N-000386 ) + ( 2 N-000388 ) ( 3 +3.3V ) ( 4 GND ) ( 5 GND ) ( 6 +3.3V ) - ( 7 N-000371 ) - ( 8 N-000373 ) + ( 7 N-000387 ) + ( 8 N-000389 ) ( 9 +3.3V ) - ( 10 N-000374 ) + ( 10 N-000390 ) ( 11 +3.3V ) - ( 12 N-000361 ) - ( 13 N-000376 ) - ( 14 N-000376 ) + ( 12 N-000377 ) + ( 13 N-000392 ) + ( 14 N-000392 ) ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) @@ -1123,7 +1163,7 @@ ( 8 /FPGA_Spartan6/M1_DQ4 ) ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M1_DQ5 ) - ( 11 /DDR_Banks/M1_DQ6 ) + ( 11 /FPGA_Spartan6/M1_DQ6 ) ( 12 GND ) ( 13 /DDR_Banks/M1_DQ7 ) ( 14 ? ) @@ -1133,33 +1173,33 @@ ( 18 +2.5V ) ( 19 ? ) ( 20 /DDR_Banks/M1_LDM ) - ( 21 /DDR_Banks/M1_WE# ) - ( 22 /FPGA_Spartan6/M1_CAS# ) - ( 23 /DDR_Banks/M1_RAS# ) - ( 24 /FPGA_Spartan6/M1_CS# ) + ( 21 /FPGA_Spartan6/M1_WE# ) + ( 22 /DDR_Banks/M1_CAS# ) + ( 23 /FPGA_Spartan6/M1_RAS# ) + ( 24 /DDR_Banks/M1_CS# ) ( 25 ? ) - ( 26 /FPGA_Spartan6/M1_BA0 ) + ( 26 /DDR_Banks/M1_BA0 ) ( 27 /DDR_Banks/M1_BA1 ) ( 28 /FPGA_Spartan6/M1_A10 ) - ( 29 /FPGA_Spartan6/M1_A0 ) - ( 30 /FPGA_Spartan6/M1_A1 ) + ( 29 /DDR_Banks/M1_A0 ) + ( 30 /DDR_Banks/M1_A1 ) ( 31 /FPGA_Spartan6/M1_A2 ) - ( 32 /DDR_Banks/M1_A3 ) + ( 32 /FPGA_Spartan6/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /DDR_Banks/M1_A4 ) - ( 36 /FPGA_Spartan6/M1_A5 ) + ( 35 /FPGA_Spartan6/M1_A4 ) + ( 36 /DDR_Banks/M1_A5 ) ( 37 /FPGA_Spartan6/M1_A6 ) - ( 38 /FPGA_Spartan6/M1_A7 ) - ( 39 /FPGA_Spartan6/M1_A8 ) + ( 38 /DDR_Banks/M1_A7 ) + ( 39 /DDR_Banks/M1_A8 ) ( 40 /FPGA_Spartan6/M1_A9 ) ( 41 /FPGA_Spartan6/M1_A11 ) ( 42 /FPGA_Spartan6/M1_A12 ) ( 43 ? ) - ( 44 /FPGA_Spartan6/M1_CLK# ) - ( 45 /FPGA_Spartan6/M1_CKE ) - ( 46 /DDR_Banks/M1_CLK ) - ( 47 /FPGA_Spartan6/M1_UDM ) + ( 44 /DDR_Banks/M1_CLK# ) + ( 45 /DDR_Banks/M1_CKE ) + ( 46 /FPGA_Spartan6/M1_CLK ) + ( 47 /DDR_Banks/M1_UDM ) ( 48 GND ) ( 49 N-000058 ) ( 50 ? ) @@ -1171,13 +1211,13 @@ ( 56 /DDR_Banks/M1_DQ9 ) ( 57 /DDR_Banks/M1_DQ10 ) ( 58 GND ) - ( 59 /FPGA_Spartan6/M1_DQ11 ) - ( 60 /DDR_Banks/M1_DQ12 ) + ( 59 /DDR_Banks/M1_DQ11 ) + ( 60 /FPGA_Spartan6/M1_DQ12 ) ( 61 +2.5V ) ( 62 /FPGA_Spartan6/M1_DQ13 ) - ( 63 /DDR_Banks/M1_DQ14 ) + ( 63 /FPGA_Spartan6/M1_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M1_DQ15 ) + ( 65 /FPGA_Spartan6/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} @@ -1278,68 +1318,68 @@ ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /FPGA_Spartan6/M0_DQ0 ) + ( 2 /DDR_Banks/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M0_DQ1 ) - ( 5 /FPGA_Spartan6/M0_DQ2 ) + ( 4 /DDR_Banks/M0_DQ1 ) + ( 5 /DDR_Banks/M0_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M0_DQ3 ) ( 8 /DDR_Banks/M0_DQ4 ) ( 9 +2.5V ) - ( 10 /DDR_Banks/M0_DQ5 ) - ( 11 /FPGA_Spartan6/M0_DQ6 ) + ( 10 /FPGA_Spartan6/M0_DQ5 ) + ( 11 /DDR_Banks/M0_DQ6 ) ( 12 GND ) - ( 13 /DDR_Banks/M0_DQ7 ) + ( 13 /FPGA_Spartan6/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /DDR_Banks/M0_LDQS ) + ( 16 /FPGA_Spartan6/M0_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) ( 20 /FPGA_Spartan6/M0_LDM ) ( 21 /DDR_Banks/M0_WE# ) ( 22 /FPGA_Spartan6/M0_CAS# ) - ( 23 /DDR_Banks/M0_RAS# ) + ( 23 /FPGA_Spartan6/M0_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 /DDR_Banks/M0_BA0 ) + ( 26 /FPGA_Spartan6/M0_BA0 ) ( 27 /DDR_Banks/M0_BA1 ) - ( 28 /FPGA_Spartan6/M0_A10 ) - ( 29 /FPGA_Spartan6/M0_A0 ) - ( 30 /DDR_Banks/M0_A1 ) + ( 28 /DDR_Banks/M0_A10 ) + ( 29 /DDR_Banks/M0_A0 ) + ( 30 /FPGA_Spartan6/M0_A1 ) ( 31 /FPGA_Spartan6/M0_A2 ) ( 32 /FPGA_Spartan6/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M0_A4 ) - ( 36 /DDR_Banks/M0_A5 ) + ( 36 /FPGA_Spartan6/M0_A5 ) ( 37 /FPGA_Spartan6/M0_A6 ) - ( 38 /DDR_Banks/M0_A7 ) + ( 38 /FPGA_Spartan6/M0_A7 ) ( 39 /FPGA_Spartan6/M0_A8 ) ( 40 /FPGA_Spartan6/M0_A9 ) - ( 41 /DDR_Banks/M0_A11 ) + ( 41 /FPGA_Spartan6/M0_A11 ) ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) ( 44 /DDR_Banks/M0_CLK# ) - ( 45 /FPGA_Spartan6/M0_CKE ) - ( 46 /FPGA_Spartan6/M0_CLK ) - ( 47 /DDR_Banks/M0_UDM ) + ( 45 /DDR_Banks/M0_CKE ) + ( 46 /DDR_Banks/M0_CLK ) + ( 47 /FPGA_Spartan6/M0_UDM ) ( 48 GND ) ( 49 N-000059 ) ( 50 ? ) ( 51 /DDR_Banks/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /FPGA_Spartan6/M0_DQ8 ) + ( 54 /DDR_Banks/M0_DQ8 ) ( 55 +2.5V ) ( 56 /DDR_Banks/M0_DQ9 ) - ( 57 /FPGA_Spartan6/M0_DQ10 ) + ( 57 /DDR_Banks/M0_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M0_DQ11 ) - ( 60 /FPGA_Spartan6/M0_DQ12 ) + ( 60 /DDR_Banks/M0_DQ12 ) ( 61 +2.5V ) - ( 62 /DDR_Banks/M0_DQ13 ) - ( 63 /FPGA_Spartan6/M0_DQ14 ) + ( 62 /FPGA_Spartan6/M0_DQ13 ) + ( 63 /DDR_Banks/M0_DQ14 ) ( 64 GND ) ( 65 /FPGA_Spartan6/M0_DQ15 ) ( 66 GND ) @@ -1851,16 +1891,16 @@ Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" Net 2 "/FPGA Spartan6/NF_RE_N" "NF_RE_N" U5 8 U1 B16 -Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" - U5 9 +Net 3 "/FPGA Spartan6/NF_CS1_N" "NF_CS1_N" U1 C16 + U5 9 Net 4 "/Non volatile memories/NF_ALE" "NF_ALE" - U1 A15 U5 17 -Net 5 "/Ethernet Phy/ETH_TXC" "ETH_TXC" + U1 A15 +Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" U4 15 U1 D7 -Net 6 "/FPGA Spartan6/ETH_RXC" "ETH_RXC" +Net 6 "/Ethernet Phy/ETH_RXC" "ETH_RXC" U4 10 U1 D8 Net 7 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" @@ -1872,55 +1912,55 @@ Net 8 "/USB/USBA_SPD" "USBA_SPD" Net 9 "/USB/USBA_OE_N" "USBA_OE_N" U6 9 U1 P18 -Net 10 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" - U1 N16 +Net 10 "/USB/USBA_RCV" "USBA_RCV" U6 3 -Net 11 "/USB/USBA_VP" "USBA_VP" + U1 N16 +Net 11 "/FPGA Spartan6/USBA_VP" "USBA_VP" U6 4 U1 P17 -Net 12 "/FPGA Spartan6/USBA_VM" "USBA_VM" - U1 M18 +Net 12 "/USB/USBA_VM" "USBA_VM" U6 5 -Net 13 "/FPGA Spartan6/ETH_COL" "ETH_COL" - U4 21 + U1 M18 +Net 13 "/Ethernet Phy/ETH_COL" "ETH_COL" U1 B10 -Net 14 "/Ethernet Phy/ETH_CRS" "ETH_CRS" - U4 22 + U4 21 +Net 14 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" U1 C10 -Net 15 "/FPGA Spartan6/SD_CLK" "SD_CLK" - U1 E16 + U4 22 +Net 15 "/Non volatile memories/SD_CLK" "SD_CLK" J1 5 -Net 16 "/Ethernet Phy/ETH_INT" "ETH_INT" + U1 E16 +Net 16 "/FPGA Spartan6/ETH_INT" "ETH_INT" U1 A10 U4 25 -Net 17 "/Ethernet Phy/ETH_MDC" "ETH_MDC" +Net 17 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" U4 2 U1 D10 Net 18 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" - U4 1 R1 1 U1 C5 + U4 1 Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" U1 A5 U4 48 Net 20 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" U1 C7 U4 9 -Net 21 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" +Net 21 "/Ethernet Phy/ETH_RXER" "ETH_RXER" U1 A7 U4 11 -Net 22 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" - U1 B8 +Net 22 "/Ethernet Phy/ETH_TXER" "ETH_TXER" U4 14 -Net 23 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" - U4 16 + U1 B8 +Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" U1 A8 -Net 24 "/FPGA Spartan6/M1_CS#" "M1_CS#" + U4 16 +Net 24 "/DDR Banks/M1_CS#" "M1_CS#" U3 24 R20 2 -Net 25 "/FPGA Spartan6/M1_UDM" "M1_UDM" - U3 47 +Net 25 "/DDR Banks/M1_UDM" "M1_UDM" R18 2 + U3 47 Net 26 "/DDR Banks/M1_LDQS" "M1_LDQS" RP3 8 U3 16 @@ -1936,79 +1976,117 @@ Net 29 "/DDR Banks/M0_UDQS" "M0_UDQS" Net 30 "/FPGA Spartan6/M0_LDM" "M0_LDM" U1 L4 U2 20 -Net 31 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" +Net 31 "/DDR Banks/M1_CAS#" "M1_CAS#" U3 22 RP3 5 -Net 32 "/FPGA Spartan6/M1_CKE" "M1_CKE" - U3 45 +Net 32 "/DDR Banks/M1_CKE" "M1_CKE" R17 2 -Net 33 "/DDR Banks/M1_CLK" "M1_CLK" + U3 45 +Net 33 "/FPGA Spartan6/M1_CLK" "M1_CLK" U1 H20 - U3 46 R16 2 -Net 34 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" + U3 46 +Net 34 "/DDR Banks/M1_CLK#" "M1_CLK#" U3 44 - U1 J19 R16 1 + U1 J19 Net 35 "GND" "GND" - C46 2 - C7 2 - C49 2 - C51 2 + C32 2 + U4 36 + U4 35 + C27 2 + U4 44 + C29 2 C5 2 C3 2 C1 2 + C31 2 U4 23 + C30 2 + C6 2 + C9 2 + C2 2 + U2 48 + U2 58 + C4 2 + C8 2 + C7 2 + U4 8 + U4 12 + U1 L11 + U1 N11 + C57 2 + U1 E21 + U1 J21 + U1 N21 + U1 U21 + U1 AB1 + U1 B9 + U1 J9 + C54 2 + U1 L9 + U1 P10 + C69 2 + U1 M10 + U1 K10 U5 13 - C12 2 - R9 2 - U5 36 + C67 2 + U1 N9 + C75 1 + U1 E7 + J1 6 + U1 H7 + U1 U7 + U1 W7 + C61 2 + C64 2 + C66 2 + C63 2 + U1 V10 + U1 E11 + U1 J11 + C60 2 + C41 2 + C74 2 C40 2 C43 2 - C4 2 - C2 2 C52 2 - C8 2 - U1 K12 - U1 M12 - U1 P12 - U1 AB1 - U1 U21 - U1 N21 - U1 J21 - U1 E21 - U1 N11 - U1 P14 - U1 M14 - U1 K14 - U1 N13 - U1 L13 - U1 J13 - U1 B13 - U1 A22 - U1 J9 - U1 B9 - U1 W7 - U1 U7 - U1 H7 - C72 2 - C73 2 - U4 36 - U4 35 + C46 2 + U5 36 + C49 2 + C51 2 U8 4 - U4 44 - C58 2 - C55 2 - C68 2 - C74 2 - C75 1 - U4 39 - C34 2 - C27 2 - C32 2 - C30 2 - C31 2 - C29 2 + C53 2 + C62 2 + C59 2 + C73 2 + C72 2 + C56 2 + C50 2 + C47 2 + C44 2 + C39 2 + U2 34 + U2 24 + C42 2 + C45 2 + C48 2 + U2 52 + U2 12 + U1 K14 + U1 M14 + U2 66 + C65 2 + U1 P14 + U1 V14 + U1 E15 + U2 64 + U1 J15 + C18 2 + U1 AA5 + C20 2 + U1 W16 + U1 B17 C28 2 C33 2 C22 2 @@ -2017,157 +2095,119 @@ Net 35 "GND" "GND" C24 2 C26 2 C21 2 + C34 2 + C71 2 + C70 2 + U1 AB22 + U1 AA13 + U1 AA17 + U1 A1 + U1 E2 + U1 J2 + U1 N2 + U1 U2 + U1 D4 + U1 V4 + U1 B5 + U1 G5 J1 CASE J1 CASE J1 CASE J1 COM - J1 6 - C39 2 - C42 2 - C45 2 - R2 2 - C48 2 - C11 2 - C10 2 - C71 2 - C70 2 - U2 34 - U2 24 - U2 52 - U2 12 - U2 66 - U2 64 - C18 2 - C20 2 - R12 2 - R14 2 - U2 6 - C63 2 - C69 2 - C54 2 - C57 2 - C60 2 - C56 2 - C53 2 - C41 2 - C50 2 - C47 2 - C44 2 - C66 2 - U1 AA5 - U1 J15 - U1 E15 - U1 V14 - U1 AA17 - U1 AA13 - U1 AB22 - U1 AA9 - U1 W19 - U4 12 - C65 2 - C62 2 - C59 2 - U1 E7 - U1 R5 U1 L5 - U1 G5 - U1 B5 - U1 V4 - U1 L11 - U1 J11 - U1 E11 - U1 V10 - U1 P10 - U1 M10 - U1 K10 - U1 N9 - U1 L9 - U4 8 - U1 R18 - U1 L18 - U1 G18 - U1 D18 + U1 R5 U1 N17 - U1 B17 - U1 W16 - C67 2 - C61 2 - C64 2 - C9 2 - C6 2 - U1 D4 - U1 U2 - U1 N2 - U1 J2 - U1 E2 - U1 A1 - L5 2 - U3 64 - C14 2 - U3 12 - V2 2 - U3 6 - C15 2 - U9 8 - U2 48 - U2 58 - L7 2 - U3 52 - C35 2 + U1 D18 + R12 2 + U1 K12 + U1 M12 + C68 2 + U1 P12 + R14 2 + U1 A22 + U1 B13 + U1 J13 + U1 L13 + C55 2 + U1 N13 + C58 2 + U1 G18 + U1 L18 + U1 R18 + U1 W19 + U1 AA9 + U2 6 + V3 2 + V4 2 + C37 2 C36 2 + C35 2 + L7 2 + R15 2 + C38 2 + U9 PAD + U9 8 + C13 2 + C14 2 + C15 2 + V2 2 + U7 8 + U7 7 + V1 2 + C16 2 + R10 2 + L5 2 U6 8 U6 7 - C37 2 - U9 PAD - J4 4 + U4 39 J4 5 - U7 7 - U7 8 - U3 48 - U3 58 - C13 2 - V4 2 - V3 2 - V1 2 - C38 2 - C16 2 - U3 34 - R10 2 - R15 2 + J4 4 + R2 2 + C11 2 + C10 2 + C12 2 + R9 2 U3 66 + U3 12 + U3 64 + U3 34 + U3 52 + U3 58 + U3 48 + U3 6 Net 36 "/DDR Banks/M0_CLK#" "M0_CLK#" U1 H3 U2 44 -Net 37 "/FPGA Spartan6/M0_CLK" "M0_CLK" +Net 37 "/DDR Banks/M0_CLK" "M0_CLK" U2 46 U1 H4 -Net 38 "/FPGA Spartan6/M0_CKE" "M0_CKE" - U2 45 +Net 38 "/DDR Banks/M0_CKE" "M0_CKE" U1 D2 + U2 45 Net 39 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" - U2 22 U1 K4 -Net 40 "/DDR Banks/M1_WE#" "M1_WE#" - U3 21 + U2 22 +Net 40 "/FPGA Spartan6/M1_WE#" "M1_WE#" RP3 6 -Net 41 "/DDR Banks/M1_RAS#" "M1_RAS#" + U3 21 +Net 41 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" U3 23 RP2 8 -Net 42 "/DDR Banks/M0_RAS#" "M0_RAS#" - U1 K5 +Net 42 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" U2 23 + U1 K5 Net 43 "/DDR Banks/M0_WE#" "M0_WE#" U2 21 U1 F2 -Net 44 "/DDR Banks/M0_LDQS" "M0_LDQS" +Net 44 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" U2 16 U1 L3 -Net 45 "/DDR Banks/M0_UDM" "M0_UDM" - U2 47 +Net 45 "/FPGA Spartan6/M0_UDM" "M0_UDM" U1 M3 + U2 47 Net 46 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" - U8 6 U1 AA21 + U8 6 Net 47 "/FPGA Spartan6/NF_RNB" "NF_RNB" U1 A16 U5 6 @@ -2176,680 +2216,728 @@ Net 48 "/FPGA Spartan6/NF_WE_N" "NF_WE_N" U5 18 U1 C15 Net 49 "/FPGA Spartan6/NF_CLE" "NF_CLE" - U1 D15 U5 16 + U1 D15 Net 50 "/Non volatile memories/SD_CMD" "SD_CMD" J1 3 U1 D17 Net 56 "+2.5V" "+2.5V" - U7 1 - U1 H15 - U1 K15 - U1 M15 - U1 D16 - U3 55 - U1 W21 - U6 1 - U1 R21 - U1 L21 - U1 G21 - U1 C21 - U3 1 - U1 F4 - U3 15 - U1 F6 - U1 U5 - U1 N5 - U1 J5 - U3 18 - U1 W2 - U3 33 - U1 R2 - U1 L2 - U1 G2 U1 C2 - U1 L7 - C46 1 - C52 1 - C43 1 - C40 1 U1 L16 - U3 61 U1 J18 - C15 1 - U1 N18 - U1 U18 - U1 E19 - C49 1 - U3 9 - U3 3 - C66 1 - C37 1 - C51 1 - C53 1 - U1 H9 - U1 N8 - U1 L8 - U1 V6 - U1 R6 - U1 F11 - C56 1 - U1 R10 - C59 1 - C62 1 - C65 1 - C68 1 - U2 1 - U2 3 - U2 9 - R13 1 - R11 1 - U1 R12 - U1 G12 - U1 U11 - C54 1 - C57 1 - C60 1 - C63 1 - C21 1 - C34 1 - C71 1 - C70 1 - C27 1 - C32 1 - C30 1 - C31 1 - C29 1 - C28 1 + U1 G21 + U1 L21 + U1 R21 C33 1 C22 1 C23 1 C25 1 C24 1 C26 1 - C19 1 + C21 1 + C34 1 + C71 1 + C70 1 + U2 33 U2 61 U2 18 - U2 33 - C17 1 + U1 W21 + U1 N18 + U1 U18 + U1 E19 + C27 1 + C32 1 + C30 1 + C31 1 + C29 1 + C28 1 + C37 1 + U3 33 + U3 15 + U7 1 + C15 1 + U6 1 + U1 L7 + U1 F6 + U1 U5 + U1 N5 + U1 C21 + U1 J5 + U3 61 + U1 F4 + U3 1 + U3 55 + U3 18 + U3 3 + U1 W2 + U1 R2 + U1 L2 + U1 G2 + U3 9 + U1 N8 + U1 L8 + C54 1 + U1 G12 + U1 U11 + C49 1 + U1 D16 + C51 1 + C57 1 + U1 R6 + C19 1 + U1 V6 + R11 1 + C53 1 + U1 F11 + C62 1 + C60 1 + C59 1 + C63 1 + C66 1 + C56 1 U2 55 + U2 3 + C65 1 + R13 1 U2 15 + U2 1 + C68 1 + U2 9 + U1 H15 + C17 1 + U1 K15 + U1 M15 + C46 1 + U1 H9 + U1 R10 + U1 R12 + C52 1 + C43 1 + C40 1 Net 58 "" "" - U3 49 - C19 2 - C20 1 - R14 1 R13 2 + R14 1 + U3 49 + C20 1 + C19 2 Net 59 "" "" - C17 2 C18 1 - R12 1 + C17 2 U2 49 R11 2 + R12 1 Net 98 "+3.3V" "+3.3V" - L2 1 - R5 1 - C74 1 - U4 7 - U6 12 - C44 1 - R6 1 - J1 4 - R4 1 - R3 1 - C41 1 - U7 14 U1 E17 - C11 1 - C14 1 - C73 1 - C13 1 - C72 1 - U1 B15 - C1 1 - U1 G14 - C3 1 - U1 E13 - C5 1 - C35 1 - C36 1 - U4 24 - R1 2 - U7 12 - C10 1 U1 B19 - U1 B7 + L2 1 + C5 1 + C3 1 + C1 1 + U6 14 + U6 12 + U7 12 + U1 G14 + U1 B15 + C41 1 + U4 24 + C14 1 + U4 7 + U1 E13 + U7 14 U5 19 - U1 B4 - U5 12 - J4 9 - J4 3 - J4 6 U5 37 - C47 1 + C13 1 J4 11 C75 2 - U6 14 - U1 E9 - U1 G10 - U1 B11 + U5 12 + C74 1 + C35 1 + C36 1 + J1 4 + C73 1 + C72 1 C50 1 + C47 1 + C44 1 + C11 1 + C10 1 + J4 9 + J4 6 + J4 3 + R5 1 + R6 1 + R4 1 + R3 1 + R1 2 + U1 B11 + U1 G10 + U1 E9 + U1 B7 + U1 B4 Net 99 "VCCO2" "VCCO2" - U1 V16 U1 AA19 - U1 V8 - U1 AA7 - U1 AA15 - U1 AA3 - U1 T13 + U1 V16 + C55 1 U1 W5 + U1 AA7 + U1 T13 + U1 AA3 + C58 1 U1 T9 + U1 V8 C69 1 + C61 1 + U1 V12 + U1 AA11 C67 1 C64 1 - U1 V12 - C61 1 + U1 AA15 U8 8 - U1 AA11 - C58 1 - C55 1 -Net 186 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" - U1 F21 - RP1 1 -Net 187 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" - RP6 1 - U1 E20 -Net 189 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" - U1 C20 - RP7 4 -Net 190 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" - RP1 4 - U1 G20 -Net 197 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" - U1 K19 - RP6 2 -Net 198 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" - RP2 4 - U1 G19 -Net 209 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" - U1 F22 - RP1 2 -Net 210 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" - U1 E22 - RP1 3 -Net 211 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" - RP7 1 - U1 D22 -Net 212 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" - U1 C22 - RP7 3 -Net 213 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" - U1 F19 - RP7 2 -Net 221 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" - RP2 3 - U1 K17 -Net 222 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" - U1 J17 - RP2 2 -Net 230 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" - RP2 1 - U1 H21 -Net 231 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" - RP3 4 - U1 H22 -Net 285 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" - R18 1 - U1 M20 -Net 286 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" - RP6 3 - U1 K20 -Net 302 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" - U1 D21 - R17 1 -Net 334 "+1.2V" "+1.2V" - U1 J12 - U1 P11 - U1 L12 - U1 M11 - U1 N12 - U1 R14 - C48 1 - C45 1 - C42 1 - U1 K9 - U1 J8 - C39 1 - U1 K11 - U1 N10 - U1 L10 - U1 J10 - U1 P9 - U1 M9 - U1 M13 - U1 N14 - U1 L14 - U1 P13 - U1 J14 - U1 K13 -Net 335 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" - U1 H19 - RP3 3 -Net 336 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" - U1 L19 - RP3 2 -Net 337 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" +Net 168 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" U1 R20 RP9 2 -Net 338 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" - U1 R22 - RP9 1 -Net 339 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" - U1 P22 - RP9 3 -Net 340 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" - RP8 4 +Net 169 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" U1 U20 -Net 341 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" - RP8 3 - U1 U22 -Net 342 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" - U1 V22 - RP8 1 -Net 343 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" - U1 V21 - RP8 2 -Net 344 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" - RP4 3 - U1 K21 -Net 345 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" - RP4 4 - U1 K22 -Net 346 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" - U1 J22 - RP4 2 -Net 347 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" - U1 J20 - RP4 1 -Net 348 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" - U1 P21 - RP9 4 -Net 349 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" - RP5 3 - U1 M21 -Net 350 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" - U1 M22 - RP5 4 -Net 351 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" - U1 N22 - RP5 2 -Net 352 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" + RP8 4 +Net 170 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" RP5 1 U1 N20 -Net 353 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" +Net 171 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" + U1 K20 + RP6 3 +Net 172 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" + U1 V2 + RP10 3 +Net 173 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" + RP10 1 + U1 U3 +Net 174 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" + RP11 2 + U1 P1 +Net 175 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10" + RP11 3 + U1 R3 +Net 176 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" + RP13 1 + U1 N3 +Net 177 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" + U1 M2 + RP13 3 +Net 178 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" + U1 J3 + RP12 1 +Net 179 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" + RP12 2 + U1 J1 +Net 180 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" + RP12 3 + U1 K2 +Net 187 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" + U1 K19 + RP6 2 +Net 188 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" + RP2 4 + U1 G19 +Net 189 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" + U1 F19 + RP7 2 +Net 193 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" + RP9 3 + U1 P22 +Net 194 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" + U1 N22 + RP5 2 +Net 195 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" + RP5 4 + U1 M22 +Net 197 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" + RP4 4 + U1 K22 +Net 198 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" + RP4 2 + U1 J22 +Net 200 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" + RP1 2 + U1 F22 +Net 201 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" + U1 E22 + RP1 3 +Net 202 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" + RP7 1 + U1 D22 +Net 203 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" + RP7 3 + U1 C22 +Net 205 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" + U1 V21 + RP8 2 +Net 206 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" + U1 P21 + RP9 4 +Net 207 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" + U1 M21 + RP5 3 +Net 208 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" + RP4 3 + U1 K21 +Net 209 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" + RP1 1 + U1 F21 +Net 214 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" + RP2 3 + U1 K17 +Net 215 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" + RP2 2 + U1 J17 +Net 226 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" + RP8 1 + U1 V22 +Net 227 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" + U1 U22 + RP8 3 +Net 229 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" + U1 R22 + RP9 1 +Net 230 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" + R18 1 + U1 M20 +Net 235 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" RP3 1 U1 L20 -Net 354 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" +Net 236 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" + RP3 2 + U1 L19 +Net 237 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" + RP3 3 + U1 H19 +Net 238 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" + R17 1 + U1 D21 +Net 261 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" + U1 V1 + RP10 4 +Net 262 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" + U1 U1 + RP10 2 +Net 264 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" + U1 R1 + RP11 4 +Net 265 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" + U1 N1 + RP13 2 +Net 266 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" + U1 M1 + RP13 4 +Net 268 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" + U1 K1 + RP12 4 +Net 337 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" + RP4 1 + U1 J20 +Net 338 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" + RP1 4 + U1 G20 +Net 340 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" + RP6 1 + U1 E20 +Net 342 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" + U1 C20 + RP7 4 +Net 352 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" + RP11 1 + U1 P2 +Net 367 "+1.2V" "+1.2V" + C48 1 + U1 P9 + U1 J10 + U1 L14 + U1 L10 + U1 N14 + U1 M11 + U1 R14 + U1 N10 + U1 J14 + U1 J12 + U1 L12 + U1 M9 + U1 N12 + U1 K9 + U1 K13 + U1 M13 + U1 P13 + U1 J8 + U1 P11 + C42 1 + C39 1 + U1 K11 + C45 1 +Net 368 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" + RP2 1 + U1 H21 +Net 369 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" + RP3 4 + U1 H22 +Net 370 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" U1 T21 R19 1 -Net 355 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" +Net 371 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" U1 H16 R20 1 -Net 356 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - L3 2 - C9 1 +Net 372 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" U4 47 -Net 357 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + C9 1 + L3 2 +Net 373 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" L2 2 C8 1 C7 1 U4 38 -Net 358 "" "" - U4 37 +Net 374 "" "" R2 1 -Net 361 "" "" - J4 12 + U4 37 +Net 377 "" "" R8 1 -Net 362 "/Ethernet Phy/ETH_LED1" "ETH_LED1" + J4 12 +Net 378 "/Ethernet Phy/ETH_LED1" "ETH_LED1" R8 2 U4 27 -Net 365 "/Ethernet Phy/ETH_LED0" "ETH_LED0" +Net 381 "/Ethernet Phy/ETH_LED0" "ETH_LED0" R7 2 U4 26 -Net 367 "+1.8V" "+1.8V" +Net 383 "+1.8V" "+1.8V" L1 1 U4 13 C4 1 C2 1 -Net 370 "" "" - J4 1 +Net 386 "" "" U4 41 + J4 1 R3 2 -Net 371 "" "" +Net 387 "" "" + J4 7 U4 33 R5 2 - J4 7 -Net 372 "" "" - R4 2 +Net 388 "" "" U4 40 + R4 2 J4 2 -Net 373 "" "" +Net 389 "" "" U4 32 R6 2 J4 8 -Net 374 "" "" +Net 390 "" "" J4 10 R7 1 -Net 375 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" +Net 391 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" L1 2 C6 1 L3 1 U4 31 -Net 376 "" "" +Net 392 "" "" + J4 13 + J4 14 C12 1 R9 1 - J4 14 - J4 13 -Net 383 "" "" - U6 10 - V2 1 +Net 399 "" "" V2 1 J5 2 -Net 384 "" "" + V2 1 + U6 10 +Net 400 "" "" J5 4 L5 1 -Net 385 "" "" - J5 S3 - J5 S2 +Net 401 "" "" + R10 1 J5 S1 + J5 S2 + J5 S3 J5 S4 C16 1 - R10 1 -Net 386 "" "" - L6 1 +Net 402 "" "" F2 1 -Net 388 "+5V" "+5V" + L6 1 +Net 404 "+5V" "+5V" F1 2 F2 2 -Net 389 "" "" +Net 405 "" "" F1 1 L4 1 -Net 390 "" "" +Net 406 "" "" J5 1 L4 2 -Net 391 "" "" - V1 1 - V1 1 +Net 407 "" "" U6 11 J5 3 -Net 392 "" "" + V1 1 + V1 1 +Net 408 "" "" + V4 1 U7 10 V4 1 - V4 1 -Net 393 "" "" +Net 409 "" "" + V3 1 U7 11 V3 1 - V3 1 -Net 394 "" "" - R15 1 +Net 410 "" "" C38 1 -Net 414 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" + R15 1 +Net 430 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" U8 7 U1 U13 -Net 415 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" +Net 431 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" U8 3 U1 U14 -Net 416 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" +Net 432 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" U8 2 U1 AA20 -Net 417 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" - U8 5 +Net 433 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" U1 AB20 -Net 418 "/FPGA Spartan6/NF_D7" "NF_D7" - U1 A11 + U8 5 +Net 434 "/FPGA Spartan6/NF_D7" "NF_D7" U5 44 -Net 419 "/FPGA Spartan6/NF_D6" "NF_D6" - U1 D11 + U1 A11 +Net 435 "/Non volatile memories/NF_D6" "NF_D6" U5 43 -Net 420 "/Non volatile memories/NF_D5" "NF_D5" + U1 D11 +Net 436 "/FPGA Spartan6/NF_D5" "NF_D5" U5 42 U1 C12 -Net 421 "/FPGA Spartan6/NF_D4" "NF_D4" - U1 B12 +Net 437 "/Non volatile memories/NF_D4" "NF_D4" U5 41 -Net 422 "/Non volatile memories/NF_D3" "NF_D3" + U1 B12 +Net 438 "/Non volatile memories/NF_D3" "NF_D3" U1 A12 U5 32 -Net 423 "/FPGA Spartan6/NF_D2" "NF_D2" +Net 439 "/FPGA Spartan6/NF_D2" "NF_D2" U1 C13 U5 31 -Net 424 "/Non volatile memories/NF_D1" "NF_D1" - U5 30 +Net 440 "/FPGA Spartan6/NF_D1" "NF_D1" U1 A13 -Net 425 "/FPGA Spartan6/NF_D0" "NF_D0" + U5 30 +Net 441 "/Non volatile memories/NF_D0" "NF_D0" U5 29 U1 D14 -Net 426 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" - U4 20 +Net 442 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" U1 A9 -Net 427 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" + U4 20 +Net 443 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" U1 C9 U4 19 -Net 428 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" +Net 444 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" U1 C8 U4 18 -Net 429 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" - U1 D9 +Net 445 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" U4 17 -Net 430 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" - U4 3 + U1 D9 +Net 446 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" U1 D6 -Net 431 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" - U1 C6 + U4 3 +Net 447 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" U4 4 -Net 432 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" + U1 C6 +Net 448 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" U1 B6 U4 5 -Net 433 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" +Net 449 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" U1 A6 U4 6 -Net 434 "/DDR Banks/M0_BA1" "M0_BA1" - U1 G1 +Net 450 "/DDR Banks/M0_BA1" "M0_BA1" U2 27 -Net 435 "/DDR Banks/M0_BA0" "M0_BA0" - U2 26 + U1 G1 +Net 451 "/FPGA Spartan6/M0_BA0" "M0_BA0" U1 G3 -Net 436 "/DDR Banks/M1_BA1" "M1_BA1" - RP2 6 + U2 26 +Net 452 "/DDR Banks/M1_BA1" "M1_BA1" U3 27 -Net 437 "/FPGA Spartan6/M1_BA0" "M1_BA0" + RP2 6 +Net 453 "/DDR Banks/M1_BA0" "M1_BA0" RP2 7 U3 26 -Net 438 "/DDR Banks/M1_DQ15" "M1_DQ15" - U3 65 +Net 454 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" RP8 8 -Net 439 "/DDR Banks/M1_DQ14" "M1_DQ14" + U3 65 +Net 455 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" RP8 7 U3 63 -Net 440 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" +Net 456 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" U3 62 RP8 6 -Net 441 "/DDR Banks/M1_DQ12" "M1_DQ12" +Net 457 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" RP8 5 U3 60 -Net 442 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" - RP9 8 +Net 458 "/DDR Banks/M1_DQ11" "M1_DQ11" U3 59 -Net 443 "/DDR Banks/M1_DQ10" "M1_DQ10" - RP9 7 + RP9 8 +Net 459 "/DDR Banks/M1_DQ10" "M1_DQ10" U3 57 -Net 444 "/Non volatile memories/SD_DAT3" "SD_DAT3" - J1 2 + RP9 7 +Net 460 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" U1 C17 -Net 445 "/Non volatile memories/SD_DAT2" "SD_DAT2" + J1 2 +Net 461 "/Non volatile memories/SD_DAT2" "SD_DAT2" U1 A17 J1 1 -Net 446 "/Non volatile memories/SD_DAT1" "SD_DAT1" +Net 462 "/Non volatile memories/SD_DAT1" "SD_DAT1" J1 8 U1 B18 -Net 447 "/Non volatile memories/SD_DAT0" "SD_DAT0" +Net 463 "/Non volatile memories/SD_DAT0" "SD_DAT0" U1 A18 J1 7 -Net 448 "/FPGA Spartan6/M1_A7" "M1_A7" - RP6 8 +Net 464 "/DDR Banks/M1_A7" "M1_A7" U3 38 -Net 449 "/FPGA Spartan6/M1_A6" "M1_A6" - U3 37 + RP6 8 +Net 465 "/FPGA Spartan6/M1_A6" "M1_A6" RP6 7 -Net 450 "/FPGA Spartan6/M1_A5" "M1_A5" + U3 37 +Net 466 "/DDR Banks/M1_A5" "M1_A5" RP6 6 U3 36 -Net 451 "/DDR Banks/M1_A4" "M1_A4" +Net 467 "/FPGA Spartan6/M1_A4" "M1_A4" U3 35 RP6 5 -Net 452 "/DDR Banks/M1_A3" "M1_A3" +Net 468 "/FPGA Spartan6/M1_A3" "M1_A3" U3 32 RP1 5 -Net 453 "/FPGA Spartan6/M1_A2" "M1_A2" - U3 31 +Net 469 "/FPGA Spartan6/M1_A2" "M1_A2" RP1 6 -Net 454 "/FPGA Spartan6/M1_A1" "M1_A1" - RP1 7 + U3 31 +Net 470 "/DDR Banks/M1_A1" "M1_A1" U3 30 -Net 455 "/FPGA Spartan6/M1_A0" "M1_A0" + RP1 7 +Net 471 "/DDR Banks/M1_A0" "M1_A0" U3 29 RP1 8 -Net 456 "/FPGA Spartan6/M0_A12" "M0_A12" +Net 472 "/FPGA Spartan6/M0_A12" "M0_A12" U1 D1 U2 42 -Net 457 "/DDR Banks/M0_A11" "M0_A11" - U1 C1 +Net 473 "/FPGA Spartan6/M0_A11" "M0_A11" U2 41 -Net 458 "/FPGA Spartan6/M0_A10" "M0_A10" + U1 C1 +Net 474 "/DDR Banks/M0_A10" "M0_A10" U2 28 U1 G4 -Net 459 "/FPGA Spartan6/M0_A9" "M0_A9" - U2 40 +Net 475 "/FPGA Spartan6/M0_A9" "M0_A9" U1 E1 -Net 460 "/FPGA Spartan6/M0_A8" "M0_A8" - U2 39 + U2 40 +Net 476 "/FPGA Spartan6/M0_A8" "M0_A8" U1 E3 -Net 461 "/DDR Banks/M0_A7" "M0_A7" - U2 38 + U2 39 +Net 477 "/FPGA Spartan6/M0_A7" "M0_A7" U1 H6 -Net 462 "/DDR Banks/M1_DQ9" "M1_DQ9" + U2 38 +Net 478 "/DDR Banks/M1_DQ9" "M1_DQ9" U3 56 RP9 6 -Net 463 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" +Net 479 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" RP9 5 U3 54 -Net 464 "/DDR Banks/M1_DQ7" "M1_DQ7" +Net 480 "/DDR Banks/M1_DQ7" "M1_DQ7" U3 13 RP4 5 -Net 465 "/DDR Banks/M1_DQ6" "M1_DQ6" +Net 481 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" U3 11 RP4 6 -Net 466 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" +Net 482 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" U3 10 RP4 7 -Net 467 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" +Net 483 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" U3 8 RP4 8 -Net 468 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" +Net 484 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" U3 7 RP5 5 -Net 469 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" +Net 485 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" U3 5 RP5 6 -Net 470 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" - RP5 7 +Net 486 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" U3 4 -Net 471 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" - U3 2 + RP5 7 +Net 487 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" RP5 8 -Net 472 "/FPGA Spartan6/M1_A12" "M1_A12" - U3 42 + U3 2 +Net 488 "/FPGA Spartan6/M1_A12" "M1_A12" RP7 8 -Net 473 "/FPGA Spartan6/M1_A11" "M1_A11" + U3 42 +Net 489 "/FPGA Spartan6/M1_A11" "M1_A11" RP7 7 U3 41 -Net 474 "/FPGA Spartan6/M1_A10" "M1_A10" - U3 28 +Net 490 "/FPGA Spartan6/M1_A10" "M1_A10" RP2 5 -Net 475 "/FPGA Spartan6/M1_A9" "M1_A9" + U3 28 +Net 491 "/FPGA Spartan6/M1_A9" "M1_A9" RP7 6 U3 40 -Net 476 "/FPGA Spartan6/M1_A8" "M1_A8" +Net 492 "/DDR Banks/M1_A8" "M1_A8" RP7 5 U3 39 -Net 477 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" +Net 493 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" U2 7 - U1 M1 -Net 478 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" + RP13 5 +Net 494 "/DDR Banks/M0_DQ2" "M0_DQ2" U2 5 - U1 M2 -Net 479 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" + RP13 6 +Net 495 "/DDR Banks/M0_DQ1" "M0_DQ1" + RP13 7 U2 4 - U1 N1 -Net 480 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" +Net 496 "/DDR Banks/M0_DQ0" "M0_DQ0" + RP13 8 U2 2 - U1 N3 -Net 481 "/FPGA Spartan6/M0_A6" "M0_A6" +Net 497 "/FPGA Spartan6/M0_A6" "M0_A6" U2 37 U1 J4 -Net 482 "/DDR Banks/M0_A5" "M0_A5" +Net 498 "/FPGA Spartan6/M0_A5" "M0_A5" U1 K3 U2 36 -Net 483 "/FPGA Spartan6/M0_A4" "M0_A4" - U2 35 +Net 499 "/FPGA Spartan6/M0_A4" "M0_A4" U1 F3 -Net 484 "/FPGA Spartan6/M0_A3" "M0_A3" - U1 K6 + U2 35 +Net 500 "/FPGA Spartan6/M0_A3" "M0_A3" U2 32 -Net 485 "/FPGA Spartan6/M0_A2" "M0_A2" - U2 31 + U1 K6 +Net 501 "/FPGA Spartan6/M0_A2" "M0_A2" U1 H5 -Net 486 "/DDR Banks/M0_A1" "M0_A1" - U2 30 + U2 31 +Net 502 "/FPGA Spartan6/M0_A1" "M0_A1" U1 H1 -Net 487 "/FPGA Spartan6/M0_A0" "M0_A0" + U2 30 +Net 503 "/DDR Banks/M0_A0" "M0_A0" U2 29 U1 H2 -Net 488 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" +Net 504 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" U2 65 - U1 V1 -Net 489 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" + RP10 5 +Net 505 "/DDR Banks/M0_DQ14" "M0_DQ14" + RP10 6 U2 63 - U1 V2 -Net 490 "/DDR Banks/M0_DQ13" "M0_DQ13" - U1 U1 +Net 506 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" U2 62 -Net 491 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" - U1 U3 + RP10 7 +Net 507 "/DDR Banks/M0_DQ12" "M0_DQ12" + RP10 8 U2 60 -Net 492 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" - U1 R1 +Net 508 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" + RP11 5 U2 59 -Net 493 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" - U1 R3 +Net 509 "/DDR Banks/M0_DQ10" "M0_DQ10" + RP11 6 U2 57 -Net 494 "/DDR Banks/M0_DQ9" "M0_DQ9" - U1 P1 +Net 510 "/DDR Banks/M0_DQ9" "M0_DQ9" U2 56 -Net 495 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" - U1 P2 + RP11 7 +Net 511 "/DDR Banks/M0_DQ8" "M0_DQ8" + RP11 8 U2 54 -Net 496 "/DDR Banks/M0_DQ7" "M0_DQ7" - U1 K1 +Net 512 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" U2 13 -Net 497 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" - U1 K2 + RP12 5 +Net 513 "/DDR Banks/M0_DQ6" "M0_DQ6" U2 11 -Net 498 "/DDR Banks/M0_DQ5" "M0_DQ5" + RP12 6 +Net 514 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" + RP12 7 U2 10 - U1 J1 -Net 499 "/DDR Banks/M0_DQ4" "M0_DQ4" +Net 515 "/DDR Banks/M0_DQ4" "M0_DQ4" U2 8 - U1 J3 + RP12 8 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index ba4848d..31f113f 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Mon 16 Aug 2010 09:47:07 PM COT +update=Mon 16 Aug 2010 10:47:37 PM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index fb23b73..c7f7e9c 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Mon 16 Aug 2010 09:46:10 PM COT +EESchema Schematic File Version 2 date Mon 16 Aug 2010 10:43:45 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03