From d499f7d46cc32ed204e1716a0f60f1588d5381d2 Mon Sep 17 00:00:00 2001 From: Juan64Bits Date: Sat, 16 Oct 2010 12:56:21 -0500 Subject: [PATCH] Adding FTDI to JTAG/PROG schematic page. --- kicad/library/ft2232c.bak | 65 + kicad/library/ft2232c.dcm | 3 + kicad/library/ft2232c.lib | 65 + kicad/modules/CRYSTAL.mod | 47 + kicad/modules/TP40R.mod | 21 + kicad/modules/TP66R.mod | 21 + kicad/xue-rnc/DBG_PRG.sch | 668 +- kicad/xue-rnc/DRAM.sch | 69 +- kicad/xue-rnc/FPGA_0_2_PROG.sch | 5 +- kicad/xue-rnc/FPGA_1_3.sch | 5 +- kicad/xue-rnc/NV_MEMORIES.sch | 37 +- kicad/xue-rnc/PSU.sch | 199 +- kicad/xue-rnc/USB.sch | 647 +- kicad/xue-rnc/eth_phy.sch | 5 +- kicad/xue-rnc/expantion.sch | 5 +- kicad/xue-rnc/sensor.sch | 5 +- kicad/xue-rnc/sensor_psu.sch | 5 +- kicad/xue-rnc/xue-rnc-cache.lib | 147 +- kicad/xue-rnc/xue-rnc.brd | 17887 ++++++++++++++++-------------- kicad/xue-rnc/xue-rnc.cmp | 302 +- kicad/xue-rnc/xue-rnc.net | 3609 +++--- kicad/xue-rnc/xue-rnc.pro | 10 +- kicad/xue-rnc/xue-rnc.sch | 83 +- 23 files changed, 13154 insertions(+), 10756 deletions(-) create mode 100644 kicad/library/ft2232c.bak create mode 100644 kicad/library/ft2232c.dcm create mode 100644 kicad/library/ft2232c.lib create mode 100644 kicad/modules/CRYSTAL.mod create mode 100755 kicad/modules/TP40R.mod create mode 100755 kicad/modules/TP66R.mod diff --git a/kicad/library/ft2232c.bak b/kicad/library/ft2232c.bak new file mode 100644 index 0000000..077c09f --- /dev/null +++ b/kicad/library/ft2232c.bak @@ -0,0 +1,65 @@ +EESchema-LIBRARY Version 2.3 Date: Fri 08 Oct 2010 09:24:54 AM COT +# +# FT2232C +# +DEF FT2232C IC 0 40 Y Y 1 L N +F0 "IC" 0 0 50 H V C CNN +F1 "FT2232C" 0 0 50 H V C CNN +F2 "ft2232c-LQFP" 0 150 50 H I C CNN +DRAW +P 2 1 0 0 800 1500 -800 1500 N +P 2 1 0 0 -800 1500 -800 -1600 N +P 2 1 0 0 -800 -1600 800 -1600 N +P 2 1 0 0 800 -1600 800 1500 N +X AVVC 46 -300 1700 200 D 40 40 1 1 B +X VCC0 3 -100 1700 200 D 40 40 1 1 B +X VCC1 42 0 1700 200 D 40 40 1 1 B +X VCCIOA 14 100 1700 200 D 40 40 1 1 B +X VCCIOB 31 200 1700 200 D 40 40 1 1 B +X PWREN# 41 1000 -1500 200 L 40 40 1 1 B +X SI/WUB 26 1000 -1400 200 L 40 40 1 1 B +X BCBUS3 27 1000 -1300 200 L 40 40 1 1 B +X BCBUS2 28 1000 -1200 200 L 40 40 1 1 B +X BCBUS1 29 1000 -1100 200 L 40 40 1 1 B +X BCBUS0 30 1000 -1000 200 L 40 40 1 1 B +X BDBUS7 32 1000 -800 200 L 40 40 1 1 B +X BDBUS6 33 1000 -700 200 L 40 40 1 1 B +X BDBUS5 35 1000 -600 200 L 40 40 1 1 B +X BDBUS4 36 1000 -500 200 L 40 40 1 1 B +X BDBUS3 37 1000 -400 200 L 40 40 1 1 B +X BDBUS2 38 1000 -300 200 L 40 40 1 1 B +X BDBUS1 39 1000 -200 200 L 40 40 1 1 B +X BDBUS0 40 1000 -100 200 L 40 40 1 1 B +X SI/WUA 10 1000 100 200 L 40 40 1 1 B +X ACBUS3 11 1000 200 200 L 40 40 1 1 B +X ACBUS2 12 1000 300 200 L 40 40 1 1 B +X ACBUS1 13 1000 400 200 L 40 40 1 1 B +X ACBUS0 15 1000 500 200 L 40 40 1 1 B +X ADBUS7 16 1000 700 200 L 40 40 1 1 B +X ADBUS6 17 1000 800 200 L 40 40 1 1 B +X ADBUS5 19 1000 900 200 L 40 40 1 1 B +X ADBUS4 20 1000 1000 200 L 40 40 1 1 B +X ADBUS3 21 1000 1100 200 L 40 40 1 1 B +X ADBUS2 22 1000 1200 200 L 40 40 1 1 B +X ADBUS1 23 1000 1300 200 L 40 40 1 1 B +X ADBUS0 24 1000 1400 200 L 40 40 1 1 B +X TEST 47 -1000 -1000 200 R 40 40 1 1 B +X EEDATA 2 -1000 -900 200 R 40 40 1 1 B +X EESK 1 -1000 -800 200 R 40 40 1 1 B +X EECS 48 -1000 -700 200 R 40 40 1 1 B +X XTOUT 44 -1000 -600 200 R 40 40 1 1 B +X XTIN 43 -1000 -300 200 R 40 40 1 1 B +X RESET# 4 -1000 0 200 R 40 40 1 1 B +X RSTOUT# 5 -1000 200 200 R 40 40 1 1 B +X USBDP 7 -1000 500 200 R 40 40 1 1 B +X USBDM 8 -1000 800 200 R 40 40 1 1 B +X 3V3OUT 6 -1000 1100 200 R 40 40 1 1 B +X AGND 45 -300 -1800 200 U 40 40 1 1 W +X GND3 34 -100 -1800 200 U 40 40 1 1 W +X GND2 25 0 -1800 200 U 40 40 1 1 W +X GND1 18 100 -1800 200 U 40 40 1 1 W +X GND0 9 200 -1800 200 U 40 40 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicad/library/ft2232c.dcm b/kicad/library/ft2232c.dcm new file mode 100644 index 0000000..ad40440 --- /dev/null +++ b/kicad/library/ft2232c.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 Date: 14.5.2010 ã. 10:46:10 +# +#End Doc Library diff --git a/kicad/library/ft2232c.lib b/kicad/library/ft2232c.lib new file mode 100644 index 0000000..7cd7a56 --- /dev/null +++ b/kicad/library/ft2232c.lib @@ -0,0 +1,65 @@ +EESchema-LIBRARY Version 2.3 Date: Sat 16 Oct 2010 10:27:32 AM COT +# +# FT2232C +# +DEF FT2232C IC 0 40 Y Y 1 F N +F0 "IC" -750 -1750 50 H V C CNN +F1 "FT2232C" -650 -1650 50 H V C CNN +F2 "ft2232c-LQFP" -50 0 50 H I C CNN +DRAW +P 2 1 0 0 -800 -1600 800 -1600 N +P 2 1 0 0 -800 1500 -800 -1600 N +P 2 1 0 0 800 -1600 800 1500 N +P 2 1 0 0 800 1500 -800 1500 N +X EESK 1 -1000 -800 200 R 40 40 1 1 B +X EEDATA 2 -1000 -900 200 R 40 40 1 1 B +X VCC0 3 -100 1700 200 D 40 40 1 1 B +X RESET# 4 -1000 0 200 R 40 40 1 1 B +X RSTOUT# 5 -1000 200 200 R 40 40 1 1 B +X 3V3OUT 6 -1000 1100 200 R 40 40 1 1 B +X USBDP 7 -1000 500 200 R 40 40 1 1 B +X USBDM 8 -1000 800 200 R 40 40 1 1 B +X GND0 9 200 -1800 200 U 40 40 1 1 W +X SI/WUA 10 1000 100 200 L 40 40 1 1 B +X ADBUS4/DTRA# 20 1000 1000 200 L 40 40 1 1 B +X BCBUS0/TXDENB 30 1000 -1000 200 L 40 40 1 1 B +X BDBUS0/TXDB 40 1000 -100 200 L 40 40 1 1 B +X ACBUS3/TXLEDA# 11 1000 200 200 L 40 40 1 1 B +X ADBUS3/CTSA# 21 1000 1100 200 L 40 40 1 1 B +X VCCIOB 31 200 1700 200 D 40 40 1 1 B +X PWREN# 41 1000 -1500 200 L 40 40 1 1 B +X ACBUS2/RXLEDA# 12 1000 300 200 L 40 40 1 1 B +X ADBUS2/RTSA# 22 1000 1200 200 L 40 40 1 1 B +X BDBUS7/RIB# 32 1000 -800 200 L 40 40 1 1 B +X VCC1 42 0 1700 200 D 40 40 1 1 B +X ACBUS1/SLEEPA# 13 1000 400 200 L 40 40 1 1 B +X ADBUS1/RXDA 23 1000 1300 200 L 40 40 1 1 B +X BDBUS6/DCDB# 33 1000 -700 200 L 40 40 1 1 B +X XTIN 43 -1000 -300 200 R 40 40 1 1 B +X VCCIOA 14 100 1700 200 D 40 40 1 1 B +X ADBUS0/TXDA 24 1000 1400 200 L 40 40 1 1 B +X GND3 34 -100 -1800 200 U 40 40 1 1 W +X XTOUT 44 -1000 -600 200 R 40 40 1 1 B +X ACBUS0/TXDENA 15 1000 500 200 L 40 40 1 1 B +X GND2 25 0 -1800 200 U 40 40 1 1 W +X BDBUS5/DSRB# 35 1000 -600 200 L 40 40 1 1 B +X AGND 45 -300 -1800 200 U 40 40 1 1 W +X ADBUS7/RIA# 16 1000 700 200 L 40 40 1 1 B +X SI/WUB 26 1000 -1400 200 L 40 40 1 1 B +X BDBUS4/DTRB# 36 1000 -500 200 L 40 40 1 1 B +X AVVC 46 -300 1700 200 D 40 40 1 1 B +X ADBUS6/DCDA# 17 1000 800 200 L 40 40 1 1 B +X TXLEDB# 27 1000 -1300 200 L 40 40 1 1 B +X BDBUS3/CTSA# 37 1000 -400 200 L 40 40 1 1 B +X TEST 47 -1000 -1000 200 R 40 40 1 1 B +X GND1 18 100 -1800 200 U 40 40 1 1 W +X BCBUS2/RXLEDB# 28 1000 -1200 200 L 40 40 1 1 B +X BDBUS2/RTSB# 38 1000 -300 200 L 40 40 1 1 B +X EECS 48 -1000 -700 200 R 40 40 1 1 B +X ADBUS5/DSRA# 19 1000 900 200 L 40 40 1 1 B +X BCBUS1/SLEEPB# 29 1000 -1100 200 L 40 40 1 1 B +X BDBUS1/RXDB 39 1000 -200 200 L 40 40 1 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicad/modules/CRYSTAL.mod b/kicad/modules/CRYSTAL.mod new file mode 100644 index 0000000..3d608ef --- /dev/null +++ b/kicad/modules/CRYSTAL.mod @@ -0,0 +1,47 @@ +PCBNEW-LibModule-V1 Sat 16 Oct 2010 12:25:05 PM COT +$INDEX +CRYSTAL +$EndINDEX +$MODULE CRYSTAL +Po 0 0 0 15 4CB9DFD5 4CB9DFA6 ~~ +Li CRYSTAL +Sc 4CB9DFA6 +AR /4C3D77D1 +Op 0 0 0 +T0 417 -1173 280 180 0 45 N V 21 N"CRYSTAL" +T1 394 961 600 600 0 120 N I 21 N"VAL**" +DC 0 433 -59 423 30 21 +DS -374 -955 -374 325 30 21 +DS -374 325 1240 325 30 21 +DS 1240 325 1240 -955 30 21 +DS 1240 -955 -374 -955 30 21 +$PAD +Sh "1" R 551 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 0 +$EndPAD +$PAD +Sh "3" R 551 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 866 0 +$EndPAD +$PAD +Sh "2" R 551 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 866 -630 +$EndPAD +$PAD +Sh "4" R 551 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 -630 +$EndPAD +$EndMODULE CRYSTAL +$EndLIBRARY diff --git a/kicad/modules/TP40R.mod b/kicad/modules/TP40R.mod new file mode 100755 index 0000000..bc607bf --- /dev/null +++ b/kicad/modules/TP40R.mod @@ -0,0 +1,21 @@ +PCBNEW-LibModule-V1 23/8/2009-00:50:44 +$INDEX +TP40R +$EndINDEX +$MODULE TP40R +Po 0 0 0 15 0 0 ~~ +Li TP40R +Sc 4A909090 +AR +Op 0 0 0 +T0 0 -1224 600 600 0 120 N I 21 "TP40R" +T1 0 2688 600 600 0 120 N V 21 "VAL" +DC 0 0 -270 0 50 21 +$PAD +Sh "1" C 394 394 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Po 0 0 +$EndPAD +$EndMODULE TP40R +$EndLIBRARY diff --git a/kicad/modules/TP66R.mod b/kicad/modules/TP66R.mod new file mode 100755 index 0000000..54d60ef --- /dev/null +++ b/kicad/modules/TP66R.mod @@ -0,0 +1,21 @@ +PCBNEW-LibModule-V1 23/8/2009-00:50:44 +$INDEX +TP66R +$EndINDEX +$MODULE TP66R +Po 0 0 0 15 0 0 ~~ +Li TP66R +Sc 4A909090 +AR +Op 0 0 0 +T0 0 -1224 600 600 0 120 N I 21 "TP66R" +T1 0 2688 600 600 0 120 N V 21 "VAL" +DC 0 0 -390 0 50 21 +$PAD +Sh "1" C 670 670 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Po 0 0 +$EndPAD +$EndMODULE TP66R +$EndLIBRARY diff --git a/kicad/xue-rnc/DBG_PRG.sch b/kicad/xue-rnc/DBG_PRG.sch index da9e8ed..31cd335 100644 --- a/kicad/xue-rnc/DBG_PRG.sch +++ b/kicad/xue-rnc/DBG_PRG.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 6 12 +Sheet 7 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" @@ -63,29 +64,654 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Wire Line + 8600 5650 8650 5650 +Wire Wire Line + 2350 3100 2350 3450 +Connection ~ 4750 4850 +Wire Wire Line + 4600 4850 6050 4850 +Wire Wire Line + 6050 4550 3850 4550 +Wire Wire Line + 3850 4550 3850 4950 +Wire Wire Line + 4300 3450 4900 3450 +Wire Wire Line + 2300 3550 2850 3550 +Connection ~ 2350 3400 +Wire Wire Line + 2300 3400 2350 3400 +Wire Wire Line + 1700 3700 1700 3450 +Connection ~ 1700 3500 +Wire Wire Line + 1850 3500 1700 3500 +Wire Wire Line + 1700 3450 1850 3450 +Connection ~ 1550 4300 +Wire Wire Line + 1550 4400 1550 4300 +Wire Wire Line + 1400 4150 1400 4300 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2850 3700 2 40 ~ 0 +5V_USB +$Comp +L GND #PWR036 +U 1 1 4CB9D316 +P 3100 3100 +F 0 "#PWR036" H 3100 3100 30 0001 C CNN +F 1 "GND" H 3100 3030 30 0001 C CNN + 1 3100 3100 + 0 -1 1 0 +$EndComp +$Comp +L GND #PWR037 +U 1 1 4CB9D314 +P 1550 4400 +F 0 "#PWR037" H 1550 4400 30 0001 C CNN +F 1 "GND" H 1550 4330 30 0001 C CNN + 1 1550 4400 + -1 0 0 -1 +$EndComp +$Comp +L R R69 +U 1 1 4CB9D313 +P 1400 3900 +F 0 "R69" V 1480 3900 50 0000 C CNN +F 1 "1M" V 1400 3900 50 0000 C CNN + 1 1400 3900 + -1 0 0 -1 +$EndComp +$Comp +L C C145 +U 1 1 4CB9D312 +P 1700 3900 +F 0 "C145" H 1550 4000 50 0000 L CNN +F 1 "4.7nF" H 1400 3800 50 0000 L CNN + 1 1700 3900 + -1 0 0 -1 +$EndComp +$Comp +L ZX62D-B-5P8 J8 +U 1 1 4CB9D311 +P 2000 3250 +F 0 "J8" H 1950 3750 60 0000 C CNN +F 1 "ZX62D-B-5P8" H 2000 3250 60 0000 C CNN +F 2 "ZX62D-B-5P8" H 2000 3250 60 0001 C CNN + 1 2000 3250 + 1 0 0 1 +$EndComp +Text Label 1200 3600 0 40 ~ 0 +USB_CASE_FTDI +Text Label 5100 5150 0 40 ~ 0 +VCC_USB +$Comp +L GND #PWR038 +U 1 1 4CB9CB19 +P 5950 5400 +F 0 "#PWR038" H 5950 5400 30 0001 C CNN +F 1 "GND" H 5950 5330 30 0001 C CNN + 1 5950 5400 + 1 0 0 -1 +$EndComp +Text Label 5550 4250 0 40 ~ 0 +VCC_USB +Text Label 5800 2750 2 40 ~ 0 +3.3V_USB +Text Label 7600 2400 2 40 ~ 0 +3.3V_USB +Text Label 6100 1450 0 40 ~ 0 +VCC_USB +Text Label 4650 1450 0 40 ~ 0 +5V_USB +$Comp +L GND #PWR039 +U 1 1 4CB9CA81 +P 5100 2000 +F 0 "#PWR039" H 5100 2000 30 0001 C CNN +F 1 "GND" H 5100 1930 30 0001 C CNN + 1 5100 2000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR040 +U 1 1 4CB9CA7B +P 5950 2000 +F 0 "#PWR040" H 5950 2000 30 0001 C CNN +F 1 "GND" H 5950 1930 30 0001 C CNN + 1 5950 2000 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR041 +U 1 1 4CB9CA74 +P 6400 2600 +F 0 "#PWR041" H 6400 2600 30 0001 C CNN +F 1 "GND" H 6400 2530 30 0001 C CNN + 1 6400 2600 + 1 0 0 -1 +$EndComp +$Comp +L FILTER FB1 +U 1 1 4CB9CA50 +P 2700 3100 +F 0 "FB1" H 2700 3250 60 0000 C CNN +F 1 "FILTER" H 2700 3000 60 0000 C CNN + 1 2700 3100 + 1 0 0 -1 +$EndComp +$Comp +L C C148 +U 1 1 4CB9C9AD +P 5100 1700 +F 0 "C148" H 5150 1800 50 0000 L CNN +F 1 "100nF" H 5150 1600 50 0000 L CNN + 1 5100 1700 + 1 0 0 -1 +$EndComp +$Comp +L R R74 +U 1 1 4CB9C9A3 +P 6400 1750 +F 0 "R74" V 6480 1750 50 0000 C CNN +F 1 "470" V 6400 1750 50 0000 C CNN + 1 6400 1750 + 1 0 0 -1 +$EndComp +$Comp +L C C151 +U 1 1 4CB9C996 +P 6400 2300 +F 0 "C151" H 6450 2400 50 0000 L CNN +F 1 "100nF" H 6450 2200 50 0000 L CNN + 1 6400 2300 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR042 +U 1 1 4CB9C97A +P 5500 3300 +F 0 "#PWR042" H 5500 3300 30 0001 C CNN +F 1 "GND" H 5500 3230 30 0001 C CNN + 1 5500 3300 + 1 0 0 -1 +$EndComp +$Comp +L C C149 +U 1 1 4CB9C965 +P 5500 3000 +F 0 "C149" H 5550 3100 50 0000 L CNN +F 1 "33nF" H 5550 2900 50 0000 L CNN + 1 5500 3000 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR043 +U 1 1 4CB9C923 +P 6750 6150 +F 0 "#PWR043" H 6750 6150 30 0001 C CNN +F 1 "GND" H 6750 6080 30 0001 C CNN + 1 6750 6150 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR044 +U 1 1 4CB9C911 +P 7100 6150 +F 0 "#PWR044" H 7100 6150 30 0001 C CNN +F 1 "GND" H 7100 6080 30 0001 C CNN + 1 7100 6150 + 1 0 0 -1 +$EndComp +$Comp +L R R71 +U 1 1 4CB9C8F8 +P 5150 3750 +F 0 "R71" V 5230 3750 50 0000 C CNN +F 1 "27" V 5150 3750 50 0000 C CNN + 1 5150 3750 + 0 1 1 0 +$EndComp +$Comp +L R R70 +U 1 1 4CB9C8F1 +P 5150 3450 +F 0 "R70" V 5230 3450 50 0000 C CNN +F 1 "27" V 5150 3450 50 0000 C CNN + 1 5150 3450 + 0 1 1 0 +$EndComp +$Comp +L R R73 +U 1 1 4CB9C8E1 +P 5750 5150 +F 0 "R73" V 5830 5150 50 0000 C CNN +F 1 "10K" V 5750 5150 50 0000 C CNN + 1 5750 5150 + 0 1 1 0 +$EndComp +$Comp +L R R72 +U 1 1 4CB9C8D7 +P 5750 4050 +F 0 "R72" V 5830 4050 50 0000 C CNN +F 1 "1.5K" V 5750 4050 50 0000 C CNN + 1 5750 4050 + 0 1 1 0 +$EndComp +$Comp +L +3.3V #PWR045 +U 1 1 4CB9C8C7 +P 8650 5650 +F 0 "#PWR045" H 8650 5610 30 0001 C CNN +F 1 "+3.3V" H 8650 5760 30 0000 C CNN + 1 8650 5650 + 0 1 1 0 +$EndComp +$Comp +L +3.3V #PWR046 +U 1 1 4CB9C8C2 +P 8650 4150 +F 0 "#PWR046" H 8650 4110 30 0001 C CNN +F 1 "+3.3V" H 8650 4260 30 0000 C CNN + 1 8650 4150 + 0 1 1 0 +$EndComp +$Comp +L R R76 +U 1 1 4CB9C8AC +P 8350 5650 +F 0 "R76" V 8430 5650 50 0000 C CNN +F 1 "10K" V 8350 5650 50 0000 C CNN + 1 8350 5650 + 0 1 1 0 +$EndComp +$Comp +L R R75 +U 1 1 4CB9C8A1 +P 8350 4150 +F 0 "R75" V 8430 4150 50 0000 C CNN +F 1 "10K" V 8350 4150 50 0000 C CNN + 1 8350 4150 + 0 1 1 0 +$EndComp +$Comp +L FT2232C IC1 +U 1 1 4CB9C4D7 +P 7050 4250 +F 0 "IC1" H 6300 2500 50 0000 C CNN +F 1 "FT2232D" H 6400 2600 50 0000 C CNN +F 2 "ft2232c-LQFP" H 7000 4250 50 0001 C CNN + 1 7050 4250 + 1 0 0 -1 +$EndComp +Text HLabel 8050 3050 2 60 BiDi ~ 0 FPGA_TDO -Text HLabel 1900 2300 0 60 BiDi ~ 0 +Text HLabel 8050 2950 2 60 BiDi ~ 0 FPGA_TDI -Wire Wire Line - 2150 2300 1900 2300 -Wire Wire Line - 2150 2100 1900 2100 -Text HLabel 1900 2100 0 60 BiDi ~ 0 +Text HLabel 8050 3150 2 60 BiDi ~ 0 FPGA_TMS -Text HLabel 1900 2000 0 60 BiDi ~ 0 +Text HLabel 8050 2850 2 60 BiDi ~ 0 FPGA_TCK -Wire Wire Line - 2150 2000 1900 2000 $EndSCHEMATC diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 9c81047..e9ba66a 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 9 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" @@ -539,19 +540,19 @@ Entry Wire Line Entry Wire Line 10100 4400 10200 4500 $Comp -L GND #PWR0103 +L GND #PWR0115 U 1 1 4C699C4D P 9950 2100 -F 0 "#PWR0103" H 9950 2100 30 0001 C CNN +F 0 "#PWR0115" H 9950 2100 30 0001 C CNN F 1 "GND" H 9950 2030 30 0001 C CNN 1 9950 2100 1 0 0 -1 $EndComp $Comp -L GND #PWR0104 +L GND #PWR0116 U 1 1 4C699C48 P 4550 2150 -F 0 "#PWR0104" H 4550 2150 30 0001 C CNN +F 0 "#PWR0116" H 4550 2150 30 0001 C CNN F 1 "GND" H 4550 2080 30 0001 C CNN 1 4550 2150 1 0 0 -1 @@ -609,37 +610,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR0105 +L GND #PWR0117 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR0105" H 6900 6200 30 0001 C CNN +F 0 "#PWR0117" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR0106 +L +2.5V #PWR0118 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR0106" H 6900 5750 20 0001 C CNN +F 0 "#PWR0118" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR0107 +L +2.5V #PWR0119 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR0107" H 1700 5750 20 0001 C CNN +F 0 "#PWR0119" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR0108 +L GND #PWR0120 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR0108" H 1700 6200 30 0001 C CNN +F 0 "#PWR0120" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -655,19 +656,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR0109 +L +2.5V #PWR0121 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR0109" H 3050 1700 20 0001 C CNN +F 0 "#PWR0121" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR0110 +L +2.5V #PWR0122 U 1 1 4C61CFC6 P 8400 1700 -F 0 "#PWR0110" H 8400 1650 20 0001 C CNN +F 0 "#PWR0122" H 8400 1650 20 0001 C CNN F 1 "+2.5V" H 8400 1800 30 0000 C CNN 1 8400 1700 1 0 0 -1 @@ -733,37 +734,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR0111 +L +2.5V #PWR0123 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR0111" H 8300 5700 20 0001 C CNN +F 0 "#PWR0123" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR0112 +L GND #PWR0124 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR0112" H 8300 6350 30 0001 C CNN +F 0 "#PWR0124" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR0113 +L GND #PWR0125 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR0113" H 3050 6350 30 0001 C CNN +F 0 "#PWR0125" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR0114 +L +2.5V #PWR0126 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR0114" H 3050 5700 20 0001 C CNN +F 0 "#PWR0126" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -849,19 +850,19 @@ F 2 "0402" H 9950 1750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR0115 +L +2.5V #PWR0127 U 1 1 4C61CE2F P 9950 800 -F 0 "#PWR0115" H 9950 750 20 0001 C CNN +F 0 "#PWR0127" H 9950 750 20 0001 C CNN F 1 "+2.5V" H 9950 900 30 0000 C CNN 1 9950 800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR0116 +L +2.5V #PWR0128 U 1 1 4C61CDF1 P 4550 850 -F 0 "#PWR0116" H 4550 800 20 0001 C CNN +F 0 "#PWR0128" H 4550 800 20 0001 C CNN F 1 "+2.5V" H 4550 950 30 0000 C CNN 1 4550 850 1 0 0 -1 @@ -944,10 +945,10 @@ $EndComp Text HLabel 5000 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR0117 +L GND #PWR0129 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR0117" H 3000 5200 30 0001 C CNN +F 0 "#PWR0129" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1223,10 +1224,10 @@ Entry Wire Line Entry Wire Line 10100 3600 10200 3700 $Comp -L GND #PWR0118 +L GND #PWR0130 U 1 1 4C437C3F P 8350 5150 -F 0 "#PWR0118" H 8350 5150 30 0001 C CNN +F 0 "#PWR0130" H 8350 5150 30 0001 C CNN F 1 "GND" H 8350 5080 30 0001 C CNN 1 8350 5150 1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA_0_2_PROG.sch b/kicad/xue-rnc/FPGA_0_2_PROG.sch index 3126881..81c3b95 100644 --- a/kicad/xue-rnc/FPGA_0_2_PROG.sch +++ b/kicad/xue-rnc/FPGA_0_2_PROG.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 5 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/FPGA_1_3.sch b/kicad/xue-rnc/FPGA_1_3.sch index 6a16797..2304421 100644 --- a/kicad/xue-rnc/FPGA_1_3.sch +++ b/kicad/xue-rnc/FPGA_1_3.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 6 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index f97d464..845c57f 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 6 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" @@ -248,19 +249,19 @@ F 1 "100nF" H 4000 5400 50 0000 L CNN -1 0 0 1 $EndComp $Comp -L GND #PWR072 +L GND #PWR084 U 1 1 4C65D6AB P 9350 3150 -F 0 "#PWR072" H 9350 3150 30 0001 C CNN +F 0 "#PWR084" H 9350 3150 30 0001 C CNN F 1 "GND" H 9350 3080 30 0001 C CNN 1 9350 3150 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR073 +L +3.3V #PWR085 U 1 1 4C65D69B P 9350 2650 -F 0 "#PWR073" H 9350 2610 30 0001 C CNN +F 0 "#PWR085" H 9350 2610 30 0001 C CNN F 1 "+3.3V" H 9350 2760 30 0000 C CNN 1 9350 2650 1 0 0 -1 @@ -324,10 +325,10 @@ SPI_DQ[0..3] Text HLabel 2450 1700 0 60 Input ~ 0 SPI_FLASH_CS# $Comp -L GND #PWR074 +L GND #PWR086 U 1 1 4C65ABE9 P 2650 2450 -F 0 "#PWR074" H 2650 2450 30 0001 C CNN +F 0 "#PWR086" H 2650 2450 30 0001 C CNN F 1 "GND" H 2650 2380 30 0001 C CNN 1 2650 2450 1 0 0 -1 @@ -360,19 +361,19 @@ Entry Wire Line Entry Wire Line 8150 3150 8250 3050 $Comp -L +3.3V #PWR075 +L +3.3V #PWR087 U 1 1 4C646C14 P 7950 2900 -F 0 "#PWR075" H 7950 2860 30 0001 C CNN +F 0 "#PWR087" H 7950 2860 30 0001 C CNN F 1 "+3.3V" H 7950 3010 30 0000 C CNN 1 7950 2900 1 0 0 -1 $EndComp $Comp -L GND #PWR076 +L GND #PWR088 U 1 1 4C646BEA P 7950 3000 -F 0 "#PWR076" H 7950 3000 30 0001 C CNN +F 0 "#PWR088" H 7950 3000 30 0001 C CNN F 1 "GND" H 7950 2930 30 0001 C CNN 1 7950 3000 1 0 0 -1 @@ -422,10 +423,10 @@ SD_DAT3 Text Label 4200 6100 0 30 ~ 0 SD_CMD $Comp -L GND #PWR077 +L GND #PWR089 U 1 1 4C61D875 P 3950 5800 -F 0 "#PWR077" H 3950 5800 30 0001 C CNN +F 0 "#PWR089" H 3950 5800 30 0001 C CNN F 1 "GND" H 3950 5730 30 0001 C CNN 1 3950 5800 1 0 0 -1 @@ -437,19 +438,19 @@ SD_DAT0 Text Label 4200 5850 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR078 +L GND #PWR090 U 1 1 4C438ADC P 5800 6200 -F 0 "#PWR078" H 5800 6200 30 0001 C CNN +F 0 "#PWR090" H 5800 6200 30 0001 C CNN F 1 "GND" H 5800 6130 30 0001 C CNN 1 5800 6200 1 0 0 -1 $EndComp $Comp -L GND #PWR079 +L GND #PWR091 U 1 1 4C438AD5 P 5350 6550 -F 0 "#PWR079" H 5350 6550 30 0001 C CNN +F 0 "#PWR091" H 5350 6550 30 0001 C CNN F 1 "GND" H 5350 6480 30 0001 C CNN 1 5350 6550 1 0 0 -1 diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index 45982b2..3a0afe9 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 7 12 +Sheet 8 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" @@ -63,6 +64,18 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Text Label 7400 6950 0 40 ~ 8 +AVR_RST +Wire Wire Line + 7900 6950 7400 6950 +Text HLabel 7900 6850 2 60 BiDi ~ 0 +AVR_MISO +Text HLabel 7900 6750 2 60 BiDi ~ 0 +AVR_MOSI +Text HLabel 7900 6950 2 60 BiDi ~ 0 +AVR_RST +Text HLabel 7900 6650 2 60 BiDi ~ 0 +AVR_SCK Connection ~ 6050 3050 Wire Wire Line 6200 3050 5650 3050 @@ -107,11 +120,11 @@ Wire Wire Line Wire Wire Line 7650 6300 8250 6300 Wire Wire Line - 7700 6950 7200 6950 + 7900 6750 7400 6750 Wire Wire Line - 7700 6750 7200 6750 + 7900 6650 7400 6650 Wire Wire Line - 7700 6850 7200 6850 + 7900 6850 7400 6850 Wire Wire Line 8250 5800 7750 5800 Wire Wire Line @@ -452,8 +465,6 @@ Wire Wire Line 8250 5700 7750 5700 Wire Wire Line 8250 6000 7750 6000 -Wire Wire Line - 7700 6650 7200 6650 Wire Wire Line 7150 6300 7150 6200 Wire Wire Line @@ -496,37 +507,37 @@ lout_2.5 Text Label 600 1100 0 40 ~ 0 lout_3.3 $Comp -L +BATT #PWR034 +L +BATT #PWR047 U 1 1 4C859B7F P 1000 5200 -F 0 "#PWR034" H 1000 5150 20 0001 C CNN +F 0 "#PWR047" H 1000 5150 20 0001 C CNN F 1 "+BATT" H 1000 5300 30 0000 C CNN 1 1000 5200 1 0 0 -1 $EndComp $Comp -L +BATT #PWR035 +L +BATT #PWR048 U 1 1 4C859B76 P 1000 700 -F 0 "#PWR035" H 1000 650 20 0001 C CNN +F 0 "#PWR048" H 1000 650 20 0001 C CNN F 1 "+BATT" H 1000 800 30 0000 C CNN 1 1000 700 1 0 0 -1 $EndComp $Comp -L +BATT #PWR036 +L +BATT #PWR049 U 1 1 4C859B70 P 6200 700 -F 0 "#PWR036" H 6200 650 20 0001 C CNN +F 0 "#PWR049" H 6200 650 20 0001 C CNN F 1 "+BATT" H 6200 800 30 0000 C CNN 1 6200 700 1 0 0 -1 $EndComp $Comp -L +BATT #PWR037 +L +BATT #PWR050 U 1 1 4C859B63 P 6100 2650 -F 0 "#PWR037" H 6100 2600 20 0001 C CNN +F 0 "#PWR050" H 6100 2600 20 0001 C CNN F 1 "+BATT" H 6100 2750 30 0000 C CNN 1 6100 2650 1 0 0 -1 @@ -536,19 +547,10 @@ lout_3.3 Text Label 7750 5100 0 40 Italic 0 3.3V_EN $Comp -L CONN_4 P1 -U 1 1 4C7FD562 -P 8050 6800 -F 0 "P1" V 8000 6800 50 0000 C CNN -F 1 "AVR/PROG" V 8100 6800 50 0000 C CNN - 1 8050 6800 - 1 0 0 -1 -$EndComp -$Comp -L +3.3V #PWR038 +L +3.3V #PWR051 U 1 1 4C7FD26A P 7350 4600 -F 0 "#PWR038" H 7350 4560 30 0001 C CNN +F 0 "#PWR051" H 7350 4560 30 0001 C CNN F 1 "+3.3V" H 7350 4710 30 0000 C CNN 1 7350 4600 1 0 0 -1 @@ -564,19 +566,19 @@ F 2 "0402" H 7350 4800 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR039 +L GND #PWR052 U 1 1 4C7FD265 P 7350 5050 -F 0 "#PWR039" H 7350 5050 30 0001 C CNN +F 0 "#PWR052" H 7350 5050 30 0001 C CNN F 1 "GND" H 7350 4980 30 0001 C CNN 1 7350 5050 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR040 +L +3.3V #PWR053 U 1 1 4C7FD257 P 7150 6200 -F 0 "#PWR040" H 7150 6160 30 0001 C CNN +F 0 "#PWR053" H 7150 6160 30 0001 C CNN F 1 "+3.3V" H 7150 6310 30 0000 C CNN 1 7150 6200 1 0 0 -1 @@ -590,26 +592,17 @@ F 1 "15K" V 7400 6300 50 0000 C CNN 1 7400 6300 0 1 1 0 $EndComp -$Comp -L GND #PWR041 -U 1 1 4C7FD21A -P 7200 6650 -F 0 "#PWR041" H 7200 6650 30 0001 C CNN -F 1 "GND" H 7200 6580 30 0001 C CNN - 1 7200 6650 - 0 1 1 0 -$EndComp -Text Label 7200 6850 0 40 ~ 8 +Text Label 7400 6850 0 40 ~ 8 AVR_MISO -Text Label 7200 6950 0 40 ~ 8 +Text Label 7400 6750 0 40 ~ 8 AVR_MOSI -Text Label 7200 6750 0 40 ~ 8 +Text Label 7400 6650 0 40 ~ 8 AVR_SCK $Comp -L +3.3V #PWR042 +L +3.3V #PWR054 U 1 1 4C7FCF14 P 8050 4700 -F 0 "#PWR042" H 8050 4660 30 0001 C CNN +F 0 "#PWR054" H 8050 4660 30 0001 C CNN F 1 "+3.3V" H 8050 4810 30 0000 C CNN 1 8050 4700 1 0 0 -1 @@ -671,10 +664,10 @@ pull up Text Notes 3750 6450 0 40 ~ 0 pulldown $Comp -L GND #PWR043 +L GND #PWR055 U 1 1 4C7D02E4 P 2500 6200 -F 0 "#PWR043" H 2500 6200 30 0001 C CNN +F 0 "#PWR055" H 2500 6200 30 0001 C CNN F 1 "GND" H 2500 6130 30 0001 C CNN 1 2500 6200 1 0 0 -1 @@ -710,10 +703,10 @@ F 2 "0402" H 1250 5900 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR044 +L GND #PWR056 U 1 1 4C7D02E0 P 1250 6200 -F 0 "#PWR044" H 1250 6200 30 0001 C CNN +F 0 "#PWR056" H 1250 6200 30 0001 C CNN F 1 "GND" H 1250 6130 30 0001 C CNN 1 1250 6200 1 0 0 -1 @@ -721,19 +714,19 @@ $EndComp Text Label 2350 5250 0 30 ~ 0 VIN_DC-DC-2.5 $Comp -L GND #PWR045 +L GND #PWR057 U 1 1 4C7C4DCE P 2700 6200 -F 0 "#PWR045" H 2700 6200 30 0001 C CNN +F 0 "#PWR057" H 2700 6200 30 0001 C CNN F 1 "GND" H 2700 6130 30 0001 C CNN 1 2700 6200 1 0 0 -1 $EndComp $Comp -L GND #PWR046 +L GND #PWR058 U 1 1 4C7C4DCA P 3350 6650 -F 0 "#PWR046" H 3350 6650 30 0001 C CNN +F 0 "#PWR058" H 3350 6650 30 0001 C CNN F 1 "GND" H 3350 6580 30 0001 C CNN 1 3350 6650 1 0 0 -1 @@ -775,28 +768,28 @@ F 1 "22uF" H 2750 5550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR047 +L +2.5V #PWR059 U 1 1 4C7C4D0B P 6400 5400 -F 0 "#PWR047" H 6400 5350 20 0001 C CNN +F 0 "#PWR059" H 6400 5350 20 0001 C CNN F 1 "+2.5V" H 6400 5500 30 0000 C CNN 1 6400 5400 1 0 0 -1 $EndComp $Comp -L GND #PWR048 +L GND #PWR060 U 1 1 4C7C4CF3 P 5500 6350 -F 0 "#PWR048" H 5500 6350 30 0001 C CNN +F 0 "#PWR060" H 5500 6350 30 0001 C CNN F 1 "GND" H 5500 6280 30 0001 C CNN 1 5500 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR049 +L GND #PWR061 U 1 1 4C7C4CF2 P 6200 6350 -F 0 "#PWR049" H 6200 6350 30 0001 C CNN +F 0 "#PWR061" H 6200 6350 30 0001 C CNN F 1 "GND" H 6200 6280 30 0001 C CNN 1 6200 6350 1 0 0 -1 @@ -866,10 +859,10 @@ VFB2.5 Text Label 5450 5400 0 30 ~ 0 SW_2.5 $Comp -L GND #PWR050 +L GND #PWR062 U 1 1 4C79C99F P 7500 3650 -F 0 "#PWR050" H 7500 3650 30 0001 C CNN +F 0 "#PWR062" H 7500 3650 30 0001 C CNN F 1 "GND" H 7500 3580 30 0001 C CNN 1 7500 3650 1 0 0 -1 @@ -887,10 +880,10 @@ $EndComp Text Label 7100 2700 0 30 ~ 0 VIN_DC-DC-5.0 $Comp -L GND #PWR051 +L GND #PWR063 U 1 1 4C79C99D P 6050 3650 -F 0 "#PWR051" H 6050 3650 30 0001 C CNN +F 0 "#PWR063" H 6050 3650 30 0001 C CNN F 1 "GND" H 6050 3580 30 0001 C CNN 1 6050 3650 1 0 0 -1 @@ -926,46 +919,46 @@ F 2 "MLP6" H 6750 3050 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR052 +L GND #PWR064 U 1 1 4C79C999 P 7300 3650 -F 0 "#PWR052" H 7300 3650 30 0001 C CNN +F 0 "#PWR064" H 7300 3650 30 0001 C CNN F 1 "GND" H 7300 3580 30 0001 C CNN 1 7300 3650 1 0 0 -1 $EndComp $Comp -L GND #PWR053 +L GND #PWR065 U 1 1 4C79C962 P 8850 3650 -F 0 "#PWR053" H 8850 3650 30 0001 C CNN +F 0 "#PWR065" H 8850 3650 30 0001 C CNN F 1 "GND" H 8850 3580 30 0001 C CNN 1 8850 3650 1 0 0 -1 $EndComp $Comp -L +5V #PWR054 +L +5V #PWR066 U 1 1 4C79C951 P 10300 2700 -F 0 "#PWR054" H 10300 2790 20 0001 C CNN +F 0 "#PWR066" H 10300 2790 20 0001 C CNN F 1 "+5V" H 10300 2790 30 0000 C CNN 1 10300 2700 1 0 0 -1 $EndComp $Comp -L GND #PWR055 +L GND #PWR067 U 1 1 4C79C8B4 P 9500 3650 -F 0 "#PWR055" H 9500 3650 30 0001 C CNN +F 0 "#PWR067" H 9500 3650 30 0001 C CNN F 1 "GND" H 9500 3580 30 0001 C CNN 1 9500 3650 1 0 0 -1 $EndComp $Comp -L GND #PWR056 +L GND #PWR068 U 1 1 4C79C8B3 P 10200 3650 -F 0 "#PWR056" H 10200 3650 30 0001 C CNN +F 0 "#PWR068" H 10200 3650 30 0001 C CNN F 1 "GND" H 10200 3580 30 0001 C CNN 1 10200 3650 1 0 0 -1 @@ -1059,10 +1052,10 @@ Text Label 7750 5300 0 40 Italic 0 Text Label 5900 1100 0 60 ~ 12 Iout_1.2 $Comp -L GND #PWR057 +L GND #PWR069 U 1 1 4C77073C P 7400 1700 -F 0 "#PWR057" H 7400 1700 30 0001 C CNN +F 0 "#PWR069" H 7400 1700 30 0001 C CNN F 1 "GND" H 7400 1630 30 0001 C CNN 1 7400 1700 1 0 0 -1 @@ -1098,19 +1091,19 @@ F 2 "0402" H 6300 1400 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR058 +L GND #PWR070 U 1 1 4C770711 P 6300 1700 -F 0 "#PWR058" H 6300 1700 30 0001 C CNN +F 0 "#PWR070" H 6300 1700 30 0001 C CNN F 1 "GND" H 6300 1630 30 0001 C CNN 1 6300 1700 1 0 0 -1 $EndComp $Comp -L GND #PWR059 +L GND #PWR071 U 1 1 4C77068E P 950 1700 -F 0 "#PWR059" H 950 1700 30 0001 C CNN +F 0 "#PWR071" H 950 1700 30 0001 C CNN F 1 "GND" H 950 1630 30 0001 C CNN 1 950 1700 1 0 0 -1 @@ -1158,19 +1151,19 @@ VFB1.2 Text Label 3850 950 0 30 ~ 0 VFB3.3 $Comp -L +3.3V #PWR060 +L +3.3V #PWR072 U 1 1 4C6D30A1 P 4850 750 -F 0 "#PWR060" H 4850 710 30 0001 C CNN +F 0 "#PWR072" H 4850 710 30 0001 C CNN F 1 "+3.3V" H 4850 860 30 0000 C CNN 1 4850 750 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR061 +L +1.2V #PWR073 U 1 1 4C6D3097 P 10150 750 -F 0 "#PWR061" H 10150 890 20 0001 C CNN +F 0 "#PWR073" H 10150 890 20 0001 C CNN F 1 "+1.2V" H 10150 860 30 0000 C CNN 1 10150 750 1 0 0 -1 @@ -1206,10 +1199,10 @@ F 2 "1206" H 9650 1450 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR062 +L GND #PWR074 U 1 1 4C6D2FD4 P 7550 1700 -F 0 "#PWR062" H 7550 1700 30 0001 C CNN +F 0 "#PWR074" H 7550 1700 30 0001 C CNN F 1 "GND" H 7550 1630 30 0001 C CNN 1 7550 1700 1 0 0 -1 @@ -1255,37 +1248,37 @@ F 2 "0402" H 10000 1450 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR063 +L GND #PWR075 U 1 1 4C6D2FCF P 9850 1700 -F 0 "#PWR063" H 9850 1700 30 0001 C CNN +F 0 "#PWR075" H 9850 1700 30 0001 C CNN F 1 "GND" H 9850 1630 30 0001 C CNN 1 9850 1700 1 0 0 -1 $EndComp $Comp -L GND #PWR064 +L GND #PWR076 U 1 1 4C6D2FCE P 9150 1700 -F 0 "#PWR064" H 9150 1700 30 0001 C CNN +F 0 "#PWR076" H 9150 1700 30 0001 C CNN F 1 "GND" H 9150 1630 30 0001 C CNN 1 9150 1700 1 0 0 -1 $EndComp $Comp -L GND #PWR065 +L GND #PWR077 U 1 1 4C6D2F47 P 3850 1700 -F 0 "#PWR065" H 3850 1700 30 0001 C CNN +F 0 "#PWR077" H 3850 1700 30 0001 C CNN F 1 "GND" H 3850 1630 30 0001 C CNN 1 3850 1700 1 0 0 -1 $EndComp $Comp -L GND #PWR066 +L GND #PWR078 U 1 1 4C6D2F41 P 4550 1700 -F 0 "#PWR066" H 4550 1700 30 0001 C CNN +F 0 "#PWR078" H 4550 1700 30 0001 C CNN F 1 "GND" H 4550 1630 30 0001 C CNN 1 4550 1700 1 0 0 -1 @@ -1331,10 +1324,10 @@ F 2 "0402" H 3850 1400 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR067 +L GND #PWR079 U 1 1 4C6D2CCE P 2300 1700 -F 0 "#PWR067" H 2300 1700 30 0001 C CNN +F 0 "#PWR079" H 2300 1700 30 0001 C CNN F 1 "GND" H 2300 1630 30 0001 C CNN 1 2300 1700 1 0 0 -1 @@ -1370,19 +1363,19 @@ F 2 "0805" H 2300 1400 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR068 +L GND #PWR080 U 1 1 4C6D2C02 P 8500 1700 -F 0 "#PWR068" H 8500 1700 30 0001 C CNN +F 0 "#PWR080" H 8500 1700 30 0001 C CNN F 1 "GND" H 8500 1630 30 0001 C CNN 1 8500 1700 1 0 0 -1 $EndComp $Comp -L GND #PWR069 +L GND #PWR081 U 1 1 4C6D2BFC P 3200 1700 -F 0 "#PWR069" H 3200 1700 30 0001 C CNN +F 0 "#PWR081" H 3200 1700 30 0001 C CNN F 1 "GND" H 3200 1630 30 0001 C CNN 1 3200 1700 1 0 0 -1 @@ -1408,10 +1401,10 @@ F 2 "SOT23-5" H 3100 1050 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR070 +L GND #PWR082 U 1 1 4C6C9F96 P 4500 6700 -F 0 "#PWR070" H 4500 6700 30 0001 C CNN +F 0 "#PWR082" H 4500 6700 30 0001 C CNN F 1 "GND" H 4500 6630 30 0001 C CNN 1 4500 6700 1 0 0 -1 @@ -1427,10 +1420,10 @@ F 2 "DFN10" H 4250 5450 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR071 +L GND #PWR083 U 1 1 4C69F7A5 P 8050 4950 -F 0 "#PWR071" H 8050 4950 30 0001 C CNN +F 0 "#PWR083" H 8050 4950 30 0001 C CNN F 1 "GND" H 8050 4880 30 0001 C CNN 1 8050 4950 1 0 0 -1 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 8619caa..903f3b0 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 -Sheet 7 12 +Sheet 10 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" @@ -63,278 +64,290 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Wire Wire Line - 2750 2850 3550 2850 -Connection ~ 3800 3700 -Connection ~ 3250 3700 -Wire Wire Line - 2900 3700 4075 3700 -Wire Wire Line - 3775 7225 3775 7400 -Wire Wire Line - 3525 7400 3525 7225 -Wire Wire Line - 2650 6550 4750 6550 -Connection ~ 3525 6450 -Wire Wire Line - 2650 6450 4500 6450 -Connection ~ 3800 2750 -Wire Wire Line - 3800 2975 3800 2750 -Wire Wire Line - 5000 2850 3600 2850 -Connection ~ 3300 6550 -Connection ~ 3975 6450 -Wire Wire Line - 3975 6350 3975 6450 -Wire Wire Line - 4750 6500 4500 6500 -Wire Wire Line - 4500 6500 4500 6450 -Wire Wire Line - 2000 6450 2150 6450 -Wire Wire Line - 1750 7050 1750 7150 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Line + 3525 7400 3525 7225 +Wire Wire Line + 3775 7400 3775 7225 +Wire Wire Line + 2900 3700 4075 3700 +Connection ~ 3250 3700 +Connection ~ 3800 3700 +Wire Wire Line + 3550 2850 2750 2850 $Comp L R R53 U 1 1 4C7D3661 @@ -363,10 +376,10 @@ F 1 "15k" V 3975 6100 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR080 +L +3.3V #PWR092 U 1 1 4C7D365E P 3975 5750 -F 0 "#PWR080" H 3975 5710 30 0001 C CNN +F 0 "#PWR092" H 3975 5710 30 0001 C CNN F 1 "+3.3V" H 3975 5860 30 0000 C CNN 1 3975 5750 1 0 0 -1 @@ -378,10 +391,10 @@ USBA_D- Text Label 4125 6550 0 40 ~ 0 USBD_D- $Comp -L GND #PWR081 +L GND #PWR093 U 1 1 4C7D3584 P 1750 7150 -F 0 "#PWR081" H 1750 7150 30 0001 C CNN +F 0 "#PWR093" H 1750 7150 30 0001 C CNN F 1 "GND" H 1750 7080 30 0001 C CNN 1 1750 7150 1 0 0 -1 @@ -405,10 +418,10 @@ F 1 "24" V 2400 6550 50 0000 C CNN 0 1 1 0 $EndComp $Comp -L GND #PWR082 +L GND #PWR094 U 1 1 4C7D353A P 1850 3450 -F 0 "#PWR082" H 1850 3450 30 0001 C CNN +F 0 "#PWR094" H 1850 3450 30 0001 C CNN F 1 "GND" H 1850 3380 30 0001 C CNN 1 1850 3450 1 0 0 -1 @@ -436,10 +449,10 @@ USB_CASE_DEV Text Label 5850 2950 0 40 ~ 0 USB_CASE_HOST $Comp -L +3.3V #PWR083 +L +3.3V #PWR095 U 1 1 4C7D32BA P 4350 2050 -F 0 "#PWR083" H 4350 2010 30 0001 C CNN +F 0 "#PWR095" H 4350 2010 30 0001 C CNN F 1 "+3.3V" H 4350 2160 30 0000 C CNN 1 4350 2050 1 0 0 -1 @@ -504,91 +517,91 @@ F 2 "MLF16" H 1700 2750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR084 +L +3.3V #PWR096 U 1 1 4C695F50 P 2700 4600 -F 0 "#PWR084" H 2700 4560 30 0001 C CNN +F 0 "#PWR096" H 2700 4560 30 0001 C CNN F 1 "+3.3V" H 2700 4710 30 0000 C CNN 1 2700 4600 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR085 +L +3.3V #PWR097 U 1 1 4C695F4B P 2100 6100 -F 0 "#PWR085" H 2100 6060 30 0001 C CNN +F 0 "#PWR097" H 2100 6060 30 0001 C CNN F 1 "+3.3V" H 2100 6210 30 0000 C CNN 1 2100 6100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR086 +L +3.3V #PWR098 U 1 1 4C695F43 P 2650 1100 -F 0 "#PWR086" H 2650 1060 30 0001 C CNN +F 0 "#PWR098" H 2650 1060 30 0001 C CNN F 1 "+3.3V" H 2650 1210 30 0000 C CNN 1 2650 1100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR087 +L +3.3V #PWR099 U 1 1 4C695F3B P 2200 2400 -F 0 "#PWR087" H 2200 2360 30 0001 C CNN +F 0 "#PWR099" H 2200 2360 30 0001 C CNN F 1 "+3.3V" H 2200 2510 30 0000 C CNN 1 2200 2400 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR088 +L +2.5V #PWR0100 U 1 1 4C695DCD P 3200 4550 -F 0 "#PWR088" H 3200 4500 20 0001 C CNN +F 0 "#PWR0100" H 3200 4500 20 0001 C CNN F 1 "+2.5V" H 3200 4650 30 0000 C CNN 1 3200 4550 1 0 0 -1 $EndComp $Comp -L GND #PWR089 +L GND #PWR0101 U 1 1 4C695F0A P 3200 5550 -F 0 "#PWR089" H 3200 5550 30 0001 C CNN +F 0 "#PWR0101" H 3200 5550 30 0001 C CNN F 1 "GND" H 3200 5480 30 0001 C CNN 1 3200 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR090 +L GND #PWR0102 U 1 1 4C695F09 P 2650 5550 -F 0 "#PWR090" H 2650 5550 30 0001 C CNN +F 0 "#PWR0102" H 2650 5550 30 0001 C CNN F 1 "GND" H 2650 5480 30 0001 C CNN 1 2650 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR091 +L GND #PWR0103 U 1 1 4C695DFE P 3150 1850 -F 0 "#PWR091" H 3150 1850 30 0001 C CNN +F 0 "#PWR0103" H 3150 1850 30 0001 C CNN F 1 "GND" H 3150 1780 30 0001 C CNN 1 3150 1850 1 0 0 -1 $EndComp $Comp -L GND #PWR092 +L GND #PWR0104 U 1 1 4C695DF8 P 2600 1850 -F 0 "#PWR092" H 2600 1850 30 0001 C CNN +F 0 "#PWR0104" H 2600 1850 30 0001 C CNN F 1 "GND" H 2600 1780 30 0001 C CNN 1 2600 1850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR093 +L +2.5V #PWR0105 U 1 1 4C695DA7 P 3150 1100 -F 0 "#PWR093" H 3150 1050 20 0001 C CNN +F 0 "#PWR0105" H 3150 1050 20 0001 C CNN F 1 "+2.5V" H 3150 1200 30 0000 C CNN 1 3150 1100 1 0 0 -1 @@ -669,28 +682,28 @@ USBD_VP Text HLabel 1200 6750 0 40 BiDi ~ 0 USBD_VM $Comp -L GND #PWR094 +L GND #PWR0106 U 1 1 4C6552B5 P 5500 7400 -F 0 "#PWR094" H 5500 7400 30 0001 C CNN +F 0 "#PWR0106" H 5500 7400 30 0001 C CNN F 1 "GND" H 5500 7330 30 0001 C CNN 1 5500 7400 1 0 0 -1 $EndComp $Comp -L GND #PWR095 +L GND #PWR0107 U 1 1 4C6552B4 P 3150 7500 -F 0 "#PWR095" H 3150 7500 30 0001 C CNN +F 0 "#PWR0107" H 3150 7500 30 0001 C CNN F 1 "GND" H 3150 7430 30 0001 C CNN 1 3150 7500 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR096 +L +2.5V #PWR0108 U 1 1 4C6552B2 P 1150 6150 -F 0 "#PWR096" H 1150 6100 20 0001 C CNN +F 0 "#PWR0108" H 1150 6100 20 0001 C CNN F 1 "+2.5V" H 1150 6250 30 0000 C CNN 1 1150 6150 1 0 0 -1 @@ -706,28 +719,28 @@ F 2 "0603" H 4650 7000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR097 +L GND #PWR0109 U 1 1 4C6552AE P 4650 7350 -F 0 "#PWR097" H 4650 7350 30 0001 C CNN +F 0 "#PWR0109" H 4650 7350 30 0001 C CNN F 1 "GND" H 4650 7280 30 0001 C CNN 1 4650 7350 1 0 0 -1 $EndComp $Comp -L GND #PWR098 +L GND #PWR0110 U 1 1 4C63F2B5 P 4900 3700 -F 0 "#PWR098" H 4900 3700 30 0001 C CNN +F 0 "#PWR0110" H 4900 3700 30 0001 C CNN F 1 "GND" H 4900 3630 30 0001 C CNN 1 4900 3700 1 0 0 -1 $EndComp $Comp -L +5V #PWR099 +L +5V #PWR0111 U 1 1 4C63F295 P 4700 1350 -F 0 "#PWR099" H 4700 1440 20 0001 C CNN +F 0 "#PWR0111" H 4700 1440 20 0001 C CNN F 1 "+5V" H 4700 1440 30 0000 C CNN 1 4700 1350 1 0 0 -1 @@ -753,28 +766,28 @@ F 2 "0603" H 4900 3350 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR0100 +L +2.5V #PWR0112 U 1 1 4C63EC16 P 1250 2450 -F 0 "#PWR0100" H 1250 2400 20 0001 C CNN +F 0 "#PWR0112" H 1250 2400 20 0001 C CNN F 1 "+2.5V" H 1250 2550 30 0000 C CNN 1 1250 2450 1 0 0 -1 $EndComp $Comp -L GND #PWR0101 +L GND #PWR0113 U 1 1 4C63EA1B P 3100 3800 -F 0 "#PWR0101" H 3100 3800 30 0001 C CNN +F 0 "#PWR0113" H 3100 3800 30 0001 C CNN F 1 "GND" H 3100 3730 30 0001 C CNN 1 3100 3800 1 0 0 -1 $EndComp $Comp -L GND #PWR0102 +L GND #PWR0114 U 1 1 4C63E9FA P 5950 3750 -F 0 "#PWR0102" H 5950 3750 30 0001 C CNN +F 0 "#PWR0114" H 5950 3750 30 0001 C CNN F 1 "GND" H 5950 3680 30 0001 C CNN 1 5950 3750 1 0 0 -1 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 259b547..719f7d1 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 8 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/expantion.sch b/kicad/xue-rnc/expantion.sch index 41d2c0c..fb3b3a9 100644 --- a/kicad/xue-rnc/expantion.sch +++ b/kicad/xue-rnc/expantion.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 2 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/sensor.sch b/kicad/xue-rnc/sensor.sch index 4705b4d..80318fb 100644 --- a/kicad/xue-rnc/sensor.sch +++ b/kicad/xue-rnc/sensor.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 3 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/sensor_psu.sch b/kicad/xue-rnc/sensor_psu.sch index 09c7d57..48a8ce4 100644 --- a/kicad/xue-rnc/sensor_psu.sch +++ b/kicad/xue-rnc/sensor_psu.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 3 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 0d85287..f1f04d6 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Tue 12 Oct 2010 10:05:38 PM COT +EESchema-LIBRARY Version 2.3 Date: Sat 16 Oct 2010 12:53:51 PM COT # # +1.2V # @@ -183,6 +183,18 @@ X ~ 2 0 -100 65 U 40 40 1 1 P ENDDRAW ENDDEF # +# CONN_1 +# +DEF ~CONN_1 P 0 30 N N 1 F N +F0 "P" 80 0 40 H V L CNN +F1 "CONN_1" 0 55 30 H I C CNN +DRAW +C 0 0 31 0 1 0 N +P 2 0 1 0 -30 0 -50 0 N +X 1 1 -150 0 100 R 60 60 1 1 P +ENDDRAW +ENDDEF +# # CONN_20X2 # DEF CONN_20X2 P 0 10 Y N 1 F N @@ -233,46 +245,6 @@ X P39 39 -400 -950 300 R 60 30 1 1 P I ENDDRAW ENDDEF # -# CONN_4 -# -DEF CONN_4 P 0 40 Y N 1 F N -F0 "P" -50 0 50 V V C CNN -F1 "CONN_4" 50 0 50 V V C CNN -DRAW -S -100 200 100 -200 0 1 0 N -X P1 1 -350 150 250 R 50 50 1 1 P I -X P2 2 -350 50 250 R 50 50 1 1 P I -X P3 3 -350 -50 250 R 50 50 1 1 P I -X P4 4 -350 -150 250 R 50 50 1 1 P I -ENDDRAW -ENDDEF -# -# CONN_8X2 -# -DEF CONN_8X2 P 0 40 Y Y 1 F N -F0 "P" 0 450 60 H V C CNN -F1 "CONN_8X2" 0 0 50 V V C CNN -DRAW -S -100 400 100 -400 0 1 0 N -X ~ 1 -400 350 300 R 60 60 1 1 P I -X ~ 2 400 350 300 L 60 60 1 1 P I -X ~ 3 -400 250 300 R 60 60 1 1 P I -X ~ 4 400 250 300 L 60 60 1 1 P I -X ~ 5 -400 150 300 R 60 60 1 1 P I -X ~ 6 400 150 300 L 60 60 1 1 P I -X ~ 7 -400 50 300 R 60 60 1 1 P I -X ~ 8 400 50 300 L 60 60 1 1 P I -X ~ 9 -400 -50 300 R 60 60 1 1 P I -X ~ 10 400 -50 300 L 60 60 1 1 P I -X ~ 11 -400 -150 300 R 60 60 1 1 P I -X ~ 12 400 -150 300 L 60 60 1 1 P I -X ~ 13 -400 -250 300 R 60 60 1 1 P I -X ~ 14 400 -250 300 L 60 60 1 1 P I -X ~ 15 -400 -350 300 R 60 60 1 1 P I -X ~ 16 400 -350 300 L 60 60 1 1 P I -ENDDRAW -ENDDEF -# # CP # DEF CP C 0 10 N N 1 F N @@ -291,6 +263,20 @@ X ~ 2 0 -200 150 U 40 40 1 1 P ENDDRAW ENDDEF # +# CRYSTAL +# +DEF CRYSTAL X 0 40 N N 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "CRYSTAL" 0 -150 60 H V C CNN +DRAW +P 2 0 1 16 -100 100 -100 -100 N +P 2 0 1 16 100 100 100 -100 N +P 5 0 1 12 -50 50 50 50 50 -50 -50 -50 -50 50 f +X 1 1 -300 0 200 R 40 40 1 1 P +X 2 2 300 0 200 L 40 40 1 1 P +ENDDRAW +ENDDEF +# # FAN4010 # DEF FAN4010 U 0 40 Y Y 1 F N @@ -307,6 +293,85 @@ X NC 6 550 -100 300 L 50 50 1 1 I N ENDDRAW ENDDEF # +# FILTER +# +DEF FILTER FB 0 40 Y N 1 F N +F0 "FB" 0 150 60 H V C CNN +F1 "FILTER" 0 -100 60 H V C CNN +DRAW +A -150 0 50 1 1799 0 1 0 N -100 0 -200 0 +A -50 0 50 1 1799 0 1 0 N 0 0 -100 0 +A 0 0 0 0 0 0 1 0 N 0 0 0 0 +A 50 0 50 1 1799 0 1 0 N 100 0 0 0 +A 150 0 50 1 1799 0 1 0 N 200 0 100 0 +S -225 75 225 -50 0 1 0 N +X 1 1 -350 0 150 R 40 40 1 1 P +X 2 2 350 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# FT2232C +# +DEF FT2232C IC 0 40 Y Y 1 F N +F0 "IC" -750 -1750 50 H V C CNN +F1 "FT2232C" -650 -1650 50 H V C CNN +F2 "ft2232c-LQFP" -50 0 50 H I C CNN +DRAW +P 2 1 0 0 -800 -1600 800 -1600 N +P 2 1 0 0 -800 1500 -800 -1600 N +P 2 1 0 0 800 -1600 800 1500 N +P 2 1 0 0 800 1500 -800 1500 N +X EESK 1 -1000 -800 200 R 40 40 1 1 B +X EEDATA 2 -1000 -900 200 R 40 40 1 1 B +X VCC0 3 -100 1700 200 D 40 40 1 1 B +X RESET# 4 -1000 0 200 R 40 40 1 1 B +X RSTOUT# 5 -1000 200 200 R 40 40 1 1 B +X 3V3OUT 6 -1000 1100 200 R 40 40 1 1 B +X USBDP 7 -1000 500 200 R 40 40 1 1 B +X USBDM 8 -1000 800 200 R 40 40 1 1 B +X GND0 9 200 -1800 200 U 40 40 1 1 W +X SI/WUA 10 1000 100 200 L 40 40 1 1 B +X ADBUS4/DTRA# 20 1000 1000 200 L 40 40 1 1 B +X BCBUS0/TXDENB 30 1000 -1000 200 L 40 40 1 1 B +X BDBUS0/TXDB 40 1000 -100 200 L 40 40 1 1 B +X ACBUS3/TXLEDA# 11 1000 200 200 L 40 40 1 1 B +X ADBUS3/CTSA# 21 1000 1100 200 L 40 40 1 1 B +X VCCIOB 31 200 1700 200 D 40 40 1 1 B +X PWREN# 41 1000 -1500 200 L 40 40 1 1 B +X ACBUS2/RXLEDA# 12 1000 300 200 L 40 40 1 1 B +X ADBUS2/RTSA# 22 1000 1200 200 L 40 40 1 1 B +X BDBUS7/RIB# 32 1000 -800 200 L 40 40 1 1 B +X VCC1 42 0 1700 200 D 40 40 1 1 B +X ACBUS1/SLEEPA# 13 1000 400 200 L 40 40 1 1 B +X ADBUS1/RXDA 23 1000 1300 200 L 40 40 1 1 B +X BDBUS6/DCDB# 33 1000 -700 200 L 40 40 1 1 B +X XTIN 43 -1000 -300 200 R 40 40 1 1 B +X VCCIOA 14 100 1700 200 D 40 40 1 1 B +X ADBUS0/TXDA 24 1000 1400 200 L 40 40 1 1 B +X GND3 34 -100 -1800 200 U 40 40 1 1 W +X XTOUT 44 -1000 -600 200 R 40 40 1 1 B +X ACBUS0/TXDENA 15 1000 500 200 L 40 40 1 1 B +X GND2 25 0 -1800 200 U 40 40 1 1 W +X BDBUS5/DSRB# 35 1000 -600 200 L 40 40 1 1 B +X AGND 45 -300 -1800 200 U 40 40 1 1 W +X ADBUS7/RIA# 16 1000 700 200 L 40 40 1 1 B +X SI/WUB 26 1000 -1400 200 L 40 40 1 1 B +X BDBUS4/DTRB# 36 1000 -500 200 L 40 40 1 1 B +X AVVC 46 -300 1700 200 D 40 40 1 1 B +X ADBUS6/DCDA# 17 1000 800 200 L 40 40 1 1 B +X TXLEDB# 27 1000 -1300 200 L 40 40 1 1 B +X BDBUS3/CTSA# 37 1000 -400 200 L 40 40 1 1 B +X TEST 47 -1000 -1000 200 R 40 40 1 1 B +X GND1 18 100 -1800 200 U 40 40 1 1 W +X BCBUS2/RXLEDB# 28 1000 -1200 200 L 40 40 1 1 B +X BDBUS2/RTSB# 38 1000 -300 200 L 40 40 1 1 B +X EECS 48 -1000 -700 200 R 40 40 1 1 B +X ADBUS5/DSRA# 19 1000 900 200 L 40 40 1 1 B +X BCBUS1/SLEEPB# 29 1000 -1100 200 L 40 40 1 1 B +X BDBUS1/RXDB 39 1000 -200 200 L 40 40 1 1 B +ENDDRAW +ENDDEF +# # GND # DEF ~GND #PWR 0 0 Y Y 1 F P diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 8fd2e80..f483d51 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Tue 12 Oct 2010 10:05:18 PM COT +PCBNEW-BOARD Version 1 date Sat 16 Oct 2010 12:53:53 PM COT # Created by Pcbnew(2010-06-08 BZR 2367)-stable @@ -6,21 +6,21 @@ $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 13FF801F -Links 991 -NoConn 56 -Di 45315 10115 72555 52832 -Ndraw 7 +Links 1041 +NoConn 106 +Di 32509 12894 67005 59759 +Ndraw 6 Ntrack 6250 Nzone 0 BoardThickness 630 -Nmodule 268 -Nnets 375 +Nmodule 286 +Nnets 407 $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" @@ -99,375 +99,375 @@ Na 5 "+BATT" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DBG_PRG/FPGA_TCK" +Na 6 "/DBG_PRG/3.3V_USB" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DBG_PRG/FPGA_TDI" +Na 7 "/DBG_PRG/5V_USB" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_A0" +Na 8 "/DBG_PRG/AVR_SCK" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_A1" +Na 9 "/DBG_PRG/FPGA_TDI" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_A11" +Na 10 "/DBG_PRG/FPGA_TMS" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_A12" +Na 11 "/DBG_PRG/FTDI_USB_DM" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_A6" +Na 12 "/DBG_PRG/FTDI_USB_DP" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_A7" +Na 13 "/DBG_PRG/USB_CASE_FTDI" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_A8" +Na 14 "/DBG_PRG/VCC_USB" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_BA0" +Na 15 "/DDR_Banks/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_CAS#" +Na 16 "/DDR_Banks/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_CKE" +Na 17 "/DDR_Banks/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_DQ0" +Na 18 "/DDR_Banks/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_DQ11" +Na 19 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M0_DQ12" +Na 20 "/DDR_Banks/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M0_DQ15" +Na 21 "/DDR_Banks/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M0_DQ5" +Na 22 "/DDR_Banks/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M0_DQ8" +Na 23 "/DDR_Banks/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M0_DQ9" +Na 24 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M0_RAS#" +Na 25 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M0_UDM" +Na 26 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M0_UDQS" +Na 27 "/DDR_Banks/M0_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M0_VREF" +Na 28 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_A0" +Na 29 "/DDR_Banks/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_A10" +Na 30 "/DDR_Banks/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_A11" +Na 31 "/DDR_Banks/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_A3" +Na 32 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_A8" +Na 33 "/DDR_Banks/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_BA0" +Na 34 "/DDR_Banks/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_BA1" +Na 35 "/DDR_Banks/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/DDR_Banks/M1_CAS#" +Na 36 "/DDR_Banks/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/DDR_Banks/M1_DQ12" +Na 37 "/DDR_Banks/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M1_DQ14" +Na 38 "/DDR_Banks/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/DDR_Banks/M1_DQ5" +Na 39 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/DDR_Banks/M1_DQ8" +Na 40 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/DDR_Banks/M1_DQ9" +Na 41 "/DDR_Banks/M1_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/DDR_Banks/M1_LDM" +Na 42 "/Ethernet_Phy/ETH_1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/DDR_Banks/M1_LDQS" +Na 43 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/DDR_Banks/M1_RAS#" +Na 44 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/DDR_Banks/M1_UDQS" +Na 45 "/Ethernet_Phy/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/DDR_Banks/M1_VREF" +Na 46 "/Ethernet_Phy/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_1.8V" +Na 47 "/Ethernet_Phy/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_A1.8V" +Na 48 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_A3.3V" +Na 49 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/ETH_CLK" +Na 50 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Ethernet_Phy/ETH_CRS" +Na 51 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/Ethernet_Phy/ETH_LED0" +Na 52 "/Ethernet_Phy/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/Ethernet_Phy/ETH_LED1" +Na 53 "/Ethernet_Phy/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/Ethernet_Phy/ETH_MDC" +Na 54 "/Ethernet_Phy/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/Ethernet_Phy/ETH_MDIO" +Na 55 "/Ethernet_Phy/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/Ethernet_Phy/ETH_PLL1.8V" +Na 56 "/Ethernet_Phy/MAG_RX+" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/Ethernet_Phy/ETH_RXC" +Na 57 "/Ethernet_Phy/MAG_RX-" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/Ethernet_Phy/ETH_RXD1" +Na 58 "/Ethernet_Phy/MAG_SHIELD" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/Ethernet_Phy/ETH_RXD2" +Na 59 "/Ethernet_Phy/MAG_TX+" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/Ethernet_Phy/ETH_RXD3" +Na 60 "/Ethernet_Phy/MAG_TX-" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/Ethernet_Phy/ETH_RXDV" +Na 61 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/Ethernet_Phy/ETH_RXER" +Na 62 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/Ethernet_Phy/ETH_TXC" +Na 63 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/Ethernet_Phy/ETH_TXD2" +Na 64 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/Ethernet_Phy/ETH_TXD3" +Na 65 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/Ethernet_Phy/MAG_RX+" +Na 66 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/Ethernet_Phy/MAG_RX-" +Na 67 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/Ethernet_Phy/MAG_SHIELD" +Na 68 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/Ethernet_Phy/MAG_TX+" +Na 69 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/Ethernet_Phy/MAG_TX-" +Na 70 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" +Na 71 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_INT" +Na 72 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" +Na 73 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" +Na 74 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_0" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" +Na 75 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" +Na 76 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" +Na 77 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER" +Na 78 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" +Na 79 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_18" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_10" +Na 80 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_2" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" +Na 81 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" +Na 82 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" +Na 83 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" +Na 84 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" +Na 85 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_25" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24" +Na 86 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_27" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_27" +Na 87 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" +Na 88 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" +Na 89 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" +Na 90 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" +Na 91 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" +Na 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46" +Na 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" +Na 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" +Na 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50" +Na 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56" +Na 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" +Na 98 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0" St ~ $EndEQUIPOT $EQUIPOT @@ -479,319 +479,319 @@ Na 100 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" +Na 101 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT4" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5" +Na 102 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8" +Na 103 "/FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK" +Na 104 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" +Na 105 "/FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" +Na 106 "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA,_Port0,_Port2,_PROG_IF/IS_LINE" +Na 107 "/FPGA,_Port0,_Port2,_PROG_IF/IS_TRIGGER" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" +Na 108 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY" +Na 109 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA,_Port0,_Port2,_PROG_IF/IS_TEST" +Na 110 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA,_Port0,_Port2,_PROG_IF/IS_TRIGGER" +Na 111 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CLE" +Na 112 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N" +Na 113 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D1" +Na 114 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D2" +Na 115 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" +Na 116 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" +Na 117 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" +Na 118 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" +Na 119 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TCK" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" +Na 120 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TDO" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N" +Na 121 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" +Na 122 "/FPGA_GPIOS/FPGA_BANK0_IO_10" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1" +Na 123 "/FPGA_GPIOS/FPGA_BANK0_IO_12" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" +Na 124 "/FPGA_GPIOS/FPGA_BANK0_IO_15" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" +Na 125 "/FPGA_GPIOS/FPGA_BANK0_IO_16" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TDO" +Na 126 "/FPGA_GPIOS/FPGA_BANK0_IO_28" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TMS" +Na 127 "/FPGA_GPIOS/FPGA_BANK0_IO_3" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0" +Na 128 "/FPGA_GPIOS/FPGA_BANK0_IO_30" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" +Na 129 "/FPGA_GPIOS/FPGA_BANK0_IO_45" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/FPGA_GPIOS/FPGA_BANK0_IO_0" +Na 130 "/FPGA_GPIOS/FPGA_BANK0_IO_46" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/FPGA_GPIOS/FPGA_BANK0_IO_11" +Na 131 "/FPGA_GPIOS/FPGA_BANK0_IO_48" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/FPGA_GPIOS/FPGA_BANK0_IO_15" +Na 132 "/FPGA_GPIOS/FPGA_BANK0_IO_5" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/FPGA_GPIOS/FPGA_BANK0_IO_16" +Na 133 "/FPGA_GPIOS/FPGA_BANK0_IO_50" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/FPGA_GPIOS/FPGA_BANK0_IO_18" +Na 134 "/FPGA_GPIOS/FPGA_BANK0_IO_52" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/FPGA_GPIOS/FPGA_BANK0_IO_2" +Na 135 "/FPGA_GPIOS/FPGA_BANK0_IO_56" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/FPGA_GPIOS/FPGA_BANK0_IO_20" +Na 136 "/FPGA_GPIOS/FPGA_BANK0_IO_6" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/FPGA_GPIOS/FPGA_BANK0_IO_25" +Na 137 "/FPGA_GPIOS/FPGA_BANK0_IO_7" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/FPGA_GPIOS/FPGA_BANK0_IO_28" +Na 138 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/FPGA_GPIOS/FPGA_BANK0_IO_29" +Na 139 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/FPGA_GPIOS/FPGA_BANK0_IO_3" +Na 140 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/FPGA_GPIOS/FPGA_BANK0_IO_30" +Na 141 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/FPGA_GPIOS/FPGA_BANK0_IO_32" +Na 142 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/FPGA_GPIOS/FPGA_BANK0_IO_39" +Na 143 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/FPGA_GPIOS/FPGA_BANK0_IO_45" +Na 144 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/FPGA_GPIOS/FPGA_BANK0_IO_5" +Na 145 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/FPGA_GPIOS/FPGA_BANK0_IO_52" +Na 146 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/FPGA_GPIOS/FPGA_BANK0_IO_6" +Na 147 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/FPGA_GPIOS/FPGA_BANK0_IO_7" +Na 148 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/FPGA_GPIOS/FPGA_BANK0_IO_8" +Na 149 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A10" +Na 150 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A2" +Na 151 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" +Na 152 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A4" +Na 153 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A5" +Na 154 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" +Na 155 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" +Na 156 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" +Na 157 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK#" +Na 158 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" +Na 159 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10" +Na 160 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" +Na 161 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" +Na 162 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" +Na 163 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" +Na 164 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" +Na 165 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" +Na 166 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7" +Na 167 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_LDM" +Na 168 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS" +Na 169 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" +Na 170 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" +Na 171 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A12" +Na 172 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A2" +Na 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" +Na 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" +Na 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" +Na 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A7" +Na 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" +Na 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" +Na 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT @@ -799,59 +799,59 @@ Na 180 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK#" +Na 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CS#" +Na 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0" +Na 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" +Na 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" +Na 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" +Na 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" +Na 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15" +Na 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" +Na 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" +Na 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4" +Na 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" +Na 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7" +Na 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDM" +Na 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT @@ -1179,71 +1179,71 @@ Na 275 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 276 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV" +Na 276 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 277 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VM" +Na 277 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 278 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" +Na 278 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 279 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VP" +Na 279 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 280 "/Image_Sensor/+1.8_VDD" +Na 280 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 281 "/Image_Sensor/+2.8_VAA" +Na 281 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 282 "/Image_Sensor/+2.8_VAAPIX" +Na 282 "/Image_Sensor/+1.8_VDD" St ~ $EndEQUIPOT $EQUIPOT -Na 283 "/Image_Sensor/+2.8_VDDIO" +Na 283 "/Image_Sensor/IS_DOUT1" St ~ $EndEQUIPOT $EQUIPOT -Na 284 "/Image_Sensor/+2.8_VDDPLL" +Na 284 "/Image_Sensor/IS_DOUT2" St ~ $EndEQUIPOT $EQUIPOT -Na 285 "/Image_Sensor/IS_DOUT0" +Na 285 "/Image_Sensor/IS_DOUT3" St ~ $EndEQUIPOT $EQUIPOT -Na 286 "/Image_Sensor/IS_DOUT1" +Na 286 "/Image_Sensor/IS_DOUT5" St ~ $EndEQUIPOT $EQUIPOT -Na 287 "/Image_Sensor/IS_DOUT2" +Na 287 "/Image_Sensor/IS_DOUT6" St ~ $EndEQUIPOT $EQUIPOT -Na 288 "/Image_Sensor/IS_DOUT4" +Na 288 "/Image_Sensor/IS_DOUT7" St ~ $EndEQUIPOT $EQUIPOT -Na 289 "/Image_Sensor/IS_DOUT6" +Na 289 "/Image_Sensor/IS_DOUT8" St ~ $EndEQUIPOT $EQUIPOT -Na 290 "/Image_Sensor/IS_DOUT7" +Na 290 "/Image_Sensor/IS_FRAME" St ~ $EndEQUIPOT $EQUIPOT -Na 291 "/Image_Sensor/IS_DOUT9" +Na 291 "/Image_Sensor/IS_I2C_ADDR" St ~ $EndEQUIPOT $EQUIPOT -Na 292 "/Image_Sensor/IS_I2C_ADDR" +Na 292 "/Image_Sensor/IS_LINE" St ~ $EndEQUIPOT $EQUIPOT @@ -1251,327 +1251,455 @@ Na 293 "/Image_Sensor/IS_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 294 "/Image_Sensor/IS_PIXEL" +Na 294 "/Image_Sensor/IS_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 295 "/Image_Sensor/IS_RESET_N" +Na 295 "/Image_Sensor/IS_SDA" St ~ $EndEQUIPOT $EQUIPOT -Na 296 "/Image_Sensor/IS_SDA" +Na 296 "/Image_Sensor/IS_STANDBY" St ~ $EndEQUIPOT $EQUIPOT -Na 297 "/Non_volatile_memories/NF_ALE" +Na 297 "/Image_Sensor/IS_TEST" St ~ $EndEQUIPOT $EQUIPOT -Na 298 "/Non_volatile_memories/NF_D0" +Na 298 "/Non_volatile_memories/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 299 "/Non_volatile_memories/NF_D3" +Na 299 "/Non_volatile_memories/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 300 "/Non_volatile_memories/NF_D5" +Na 300 "/Non_volatile_memories/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 301 "/Non_volatile_memories/SD_CLK" +Na 301 "/Non_volatile_memories/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 302 "/Non_volatile_memories/SD_CMD" +Na 302 "/Non_volatile_memories/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 303 "/Non_volatile_memories/SD_DAT1" +Na 303 "/Non_volatile_memories/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 304 "/Non_volatile_memories/SD_DAT3" +Na 304 "/Non_volatile_memories/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 305 "/Non_volatile_memories/SPI_DQ0" +Na 305 "/Non_volatile_memories/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 306 "/Non_volatile_memories/SPI_FLASH_CS#" +Na 306 "/Non_volatile_memories/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 307 "/PSU/1.2V_EN" +Na 307 "/Non_volatile_memories/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 308 "/PSU/2.5V_EN" +Na 308 "/Non_volatile_memories/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 309 "/PSU/3.3V_EN" +Na 309 "/Non_volatile_memories/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 310 "/PSU/5V_EN" +Na 310 "/Non_volatile_memories/SPI_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 311 "/PSU/AVR_MISO" +Na 311 "/Non_volatile_memories/SPI_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 312 "/PSU/AVR_MOSI" +Na 312 "/PSU/1.2V_EN" St ~ $EndEQUIPOT $EQUIPOT -Na 313 "/PSU/AVR_RST" +Na 313 "/PSU/2.5V_EN" St ~ $EndEQUIPOT $EQUIPOT -Na 314 "/PSU/AVR_SCK" +Na 314 "/PSU/3.3V_EN" St ~ $EndEQUIPOT $EQUIPOT -Na 315 "/PSU/Iout_1.2" +Na 315 "/PSU/5V_EN" St ~ $EndEQUIPOT $EQUIPOT -Na 316 "/PSU/SW_1.2" +Na 316 "/PSU/AVR_MISO" St ~ $EndEQUIPOT $EQUIPOT -Na 317 "/PSU/SW_2.5" +Na 317 "/PSU/AVR_MOSI" St ~ $EndEQUIPOT $EQUIPOT -Na 318 "/PSU/SW_3.3" +Na 318 "/PSU/AVR_RST" St ~ $EndEQUIPOT $EQUIPOT -Na 319 "/PSU/VFB1.2" +Na 319 "/PSU/Iout_1.2" St ~ $EndEQUIPOT $EQUIPOT -Na 320 "/PSU/VFB2.5" +Na 320 "/PSU/SW_1.2" St ~ $EndEQUIPOT $EQUIPOT -Na 321 "/PSU/VFB3.3" +Na 321 "/PSU/SW_2.5" St ~ $EndEQUIPOT $EQUIPOT -Na 322 "/PSU/VFB5.0" +Na 322 "/PSU/SW_3.3" St ~ $EndEQUIPOT $EQUIPOT -Na 323 "/PSU/VIN_DC-DC-1.2" +Na 323 "/PSU/VFB1.2" St ~ $EndEQUIPOT $EQUIPOT -Na 324 "/PSU/VIN_DC-DC-2.5" +Na 324 "/PSU/VFB2.5" St ~ $EndEQUIPOT $EQUIPOT -Na 325 "/PSU/VIN_DC-DC-3.3" +Na 325 "/PSU/VFB3.3" St ~ $EndEQUIPOT $EQUIPOT -Na 326 "/PSU/VIN_DC-DC-5.0" +Na 326 "/PSU/VFB5.0" St ~ $EndEQUIPOT $EQUIPOT -Na 327 "/PSU/lout_2.5" +Na 327 "/PSU/VIN_DC-DC-1.2" St ~ $EndEQUIPOT $EQUIPOT -Na 328 "/PSU/lout_3.3" +Na 328 "/PSU/VIN_DC-DC-2.5" St ~ $EndEQUIPOT $EQUIPOT -Na 329 "/PSU/lout_5.0" +Na 329 "/PSU/VIN_DC-DC-3.3" St ~ $EndEQUIPOT $EQUIPOT -Na 330 "/USB/USBA_D+" +Na 330 "/PSU/VIN_DC-DC-5.0" St ~ $EndEQUIPOT $EQUIPOT -Na 331 "/USB/USBA_D-" +Na 331 "/PSU/lout_2.5" St ~ $EndEQUIPOT $EQUIPOT -Na 332 "/USB/USBA_SPD" +Na 332 "/PSU/lout_3.3" St ~ $EndEQUIPOT $EQUIPOT -Na 333 "/USB/USBA_VP" +Na 333 "/PSU/lout_5.0" St ~ $EndEQUIPOT $EQUIPOT -Na 334 "/USB/USBD_D+" +Na 334 "/Snesor_PSU/+2.8_VAA" St ~ $EndEQUIPOT $EQUIPOT -Na 335 "/USB/USBD_D-" +Na 335 "/Snesor_PSU/+2.8_VAAPIX" St ~ $EndEQUIPOT $EQUIPOT -Na 336 "/USB/USBD_OE_N" +Na 336 "/Snesor_PSU/+2.8_VDDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 337 "/USB/USBD_RCV" +Na 337 "/Snesor_PSU/+2.8_VDDPLL" St ~ $EndEQUIPOT $EQUIPOT -Na 338 "/USB/USBD_SPD" +Na 338 "/USB/USBA_D+" St ~ $EndEQUIPOT $EQUIPOT -Na 339 "/USB/USB_CASE_DEV" +Na 339 "/USB/USBA_D-" St ~ $EndEQUIPOT $EQUIPOT -Na 340 "/USB/USB_CASE_HOST" +Na 340 "/USB/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 341 "GND" +Na 341 "/USB/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 342 "N-000115" +Na 342 "/USB/USBD_D+" St ~ $EndEQUIPOT $EQUIPOT -Na 343 "N-000148" +Na 343 "/USB/USBD_D-" St ~ $EndEQUIPOT $EQUIPOT -Na 344 "N-000163" +Na 344 "/USB/USBD_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 345 "N-000164" +Na 345 "/USB/USB_CASE_DEV" St ~ $EndEQUIPOT $EQUIPOT -Na 346 "N-000168" +Na 346 "/USB/USB_CASE_HOST" St ~ $EndEQUIPOT $EQUIPOT -Na 347 "N-000169" +Na 347 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 348 "N-000170" +Na 348 "N-000099" St ~ $EndEQUIPOT $EQUIPOT -Na 349 "N-000171" +Na 349 "N-000132" St ~ $EndEQUIPOT $EQUIPOT -Na 350 "N-000172" +Na 350 "N-000147" St ~ $EndEQUIPOT $EQUIPOT -Na 351 "N-000174" +Na 351 "N-000148" St ~ $EndEQUIPOT $EQUIPOT -Na 352 "N-000176" +Na 352 "N-000152" St ~ $EndEQUIPOT $EQUIPOT -Na 353 "N-000177" +Na 353 "N-000153" St ~ $EndEQUIPOT $EQUIPOT -Na 354 "N-000178" +Na 354 "N-000154" St ~ $EndEQUIPOT $EQUIPOT -Na 355 "N-000184" +Na 355 "N-000155" St ~ $EndEQUIPOT $EQUIPOT -Na 356 "N-000194" +Na 356 "N-000156" St ~ $EndEQUIPOT $EQUIPOT -Na 357 "N-000199" +Na 357 "N-000158" St ~ $EndEQUIPOT $EQUIPOT -Na 358 "N-000376" +Na 358 "N-000159" St ~ $EndEQUIPOT $EQUIPOT -Na 359 "N-000379" +Na 359 "N-000160" St ~ $EndEQUIPOT $EQUIPOT -Na 360 "N-000422" +Na 360 "N-000162" St ~ $EndEQUIPOT $EQUIPOT -Na 361 "N-000423" +Na 361 "N-000168" St ~ $EndEQUIPOT $EQUIPOT -Na 362 "N-000424" +Na 362 "N-000175" St ~ $EndEQUIPOT $EQUIPOT -Na 363 "N-000425" +Na 363 "N-000180" St ~ $EndEQUIPOT $EQUIPOT -Na 364 "N-000426" +Na 364 "N-000208" St ~ $EndEQUIPOT $EQUIPOT -Na 365 "N-000427" +Na 365 "N-000209" St ~ $EndEQUIPOT $EQUIPOT -Na 366 "N-000428" +Na 366 "N-000210" St ~ $EndEQUIPOT $EQUIPOT -Na 367 "N-000429" +Na 367 "N-000211" St ~ $EndEQUIPOT $EQUIPOT -Na 368 "N-000430" +Na 368 "N-000212" St ~ $EndEQUIPOT $EQUIPOT -Na 369 "N-000431" +Na 369 "N-000213" St ~ $EndEQUIPOT $EQUIPOT -Na 370 "N-000432" +Na 370 "N-000214" St ~ $EndEQUIPOT $EQUIPOT -Na 371 "N-000433" +Na 371 "N-000215" St ~ $EndEQUIPOT $EQUIPOT -Na 372 "N-000434" +Na 372 "N-000216" St ~ $EndEQUIPOT $EQUIPOT -Na 373 "N-000435" +Na 373 "N-000217" St ~ $EndEQUIPOT $EQUIPOT -Na 374 "N-000436" +Na 374 "N-000218" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 375 "N-000219" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 376 "N-000220" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 377 "N-000221" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 378 "N-000222" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 379 "N-000223" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 380 "N-000224" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 381 "N-000226" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 382 "N-000229" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 383 "N-000231" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 384 "N-000232" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 385 "N-000233" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 386 "N-000234" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 387 "N-000235" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 388 "N-000236" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 389 "N-000237" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 390 "N-000399" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 391 "N-000402" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 392 "N-000445" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 393 "N-000446" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 394 "N-000447" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 395 "N-000448" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 396 "N-000449" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 397 "N-000450" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 398 "N-000451" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 399 "N-000452" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 400 "N-000453" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 401 "N-000454" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 402 "N-000455" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 403 "N-000456" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 404 "N-000457" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 405 "N-000458" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 406 "N-000459" St ~ $EndEQUIPOT $NCLASS @@ -1585,195 +1713,195 @@ uViaDia 197 uViaDrill 79 AddNet "" AddNet "+BATT" -AddNet "/DBG_PRG/FPGA_TCK" +AddNet "/DBG_PRG/3.3V_USB" +AddNet "/DBG_PRG/5V_USB" +AddNet "/DBG_PRG/AVR_SCK" AddNet "/DBG_PRG/FPGA_TDI" -AddNet "/DDR_Banks/M0_A0" -AddNet "/DDR_Banks/M0_A1" +AddNet "/DBG_PRG/FPGA_TMS" +AddNet "/DBG_PRG/FTDI_USB_DM" +AddNet "/DBG_PRG/FTDI_USB_DP" +AddNet "/DBG_PRG/USB_CASE_FTDI" +AddNet "/DBG_PRG/VCC_USB" +AddNet "/DDR_Banks/M0_A10" AddNet "/DDR_Banks/M0_A11" -AddNet "/DDR_Banks/M0_A12" -AddNet "/DDR_Banks/M0_A6" -AddNet "/DDR_Banks/M0_A7" +AddNet "/DDR_Banks/M0_A4" +AddNet "/DDR_Banks/M0_A5" AddNet "/DDR_Banks/M0_A8" AddNet "/DDR_Banks/M0_BA0" -AddNet "/DDR_Banks/M0_CAS#" -AddNet "/DDR_Banks/M0_CKE" -AddNet "/DDR_Banks/M0_DQ0" +AddNet "/DDR_Banks/M0_BA1" +AddNet "/DDR_Banks/M0_DQ10" AddNet "/DDR_Banks/M0_DQ11" -AddNet "/DDR_Banks/M0_DQ12" -AddNet "/DDR_Banks/M0_DQ15" -AddNet "/DDR_Banks/M0_DQ5" -AddNet "/DDR_Banks/M0_DQ8" -AddNet "/DDR_Banks/M0_DQ9" -AddNet "/DDR_Banks/M0_RAS#" -AddNet "/DDR_Banks/M0_UDM" -AddNet "/DDR_Banks/M0_UDQS" +AddNet "/DDR_Banks/M0_DQ4" +AddNet "/DDR_Banks/M0_LDM" +AddNet "/DDR_Banks/M0_LDQS" AddNet "/DDR_Banks/M0_VREF" -AddNet "/DDR_Banks/M1_A0" -AddNet "/DDR_Banks/M1_A10" +AddNet "/DDR_Banks/M0_WE#" AddNet "/DDR_Banks/M1_A11" -AddNet "/DDR_Banks/M1_A3" -AddNet "/DDR_Banks/M1_A8" -AddNet "/DDR_Banks/M1_BA0" -AddNet "/DDR_Banks/M1_BA1" -AddNet "/DDR_Banks/M1_CAS#" -AddNet "/DDR_Banks/M1_DQ12" +AddNet "/DDR_Banks/M1_A2" +AddNet "/DDR_Banks/M1_CKE" +AddNet "/DDR_Banks/M1_CLK#" +AddNet "/DDR_Banks/M1_CS#" AddNet "/DDR_Banks/M1_DQ14" -AddNet "/DDR_Banks/M1_DQ5" -AddNet "/DDR_Banks/M1_DQ8" +AddNet "/DDR_Banks/M1_DQ15" +AddNet "/DDR_Banks/M1_DQ4" +AddNet "/DDR_Banks/M1_DQ7" AddNet "/DDR_Banks/M1_DQ9" AddNet "/DDR_Banks/M1_LDM" -AddNet "/DDR_Banks/M1_LDQS" -AddNet "/DDR_Banks/M1_RAS#" -AddNet "/DDR_Banks/M1_UDQS" +AddNet "/DDR_Banks/M1_UDM" AddNet "/DDR_Banks/M1_VREF" AddNet "/Ethernet_Phy/ETH_1.8V" AddNet "/Ethernet_Phy/ETH_A1.8V" AddNet "/Ethernet_Phy/ETH_A3.3V" AddNet "/Ethernet_Phy/ETH_CLK" +AddNet "/Ethernet_Phy/ETH_COL" AddNet "/Ethernet_Phy/ETH_CRS" +AddNet "/Ethernet_Phy/ETH_INT" AddNet "/Ethernet_Phy/ETH_LED0" AddNet "/Ethernet_Phy/ETH_LED1" -AddNet "/Ethernet_Phy/ETH_MDC" -AddNet "/Ethernet_Phy/ETH_MDIO" AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/ETH_RXC" -AddNet "/Ethernet_Phy/ETH_RXD1" AddNet "/Ethernet_Phy/ETH_RXD2" -AddNet "/Ethernet_Phy/ETH_RXD3" AddNet "/Ethernet_Phy/ETH_RXDV" -AddNet "/Ethernet_Phy/ETH_RXER" -AddNet "/Ethernet_Phy/ETH_TXC" -AddNet "/Ethernet_Phy/ETH_TXD2" -AddNet "/Ethernet_Phy/ETH_TXD3" +AddNet "/Ethernet_Phy/ETH_TXEN" +AddNet "/Ethernet_Phy/ETH_TXER" AddNet "/Ethernet_Phy/MAG_RX+" AddNet "/Ethernet_Phy/MAG_RX-" AddNet "/Ethernet_Phy/MAG_SHIELD" AddNet "/Ethernet_Phy/MAG_TX+" AddNet "/Ethernet_Phy/MAG_TX-" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_INT" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_0" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_10" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_18" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_2" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_25" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_27" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT4" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_LINE" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_TEST" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/IS_TRIGGER" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_CLE" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D0" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D1" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D2" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" +AddNet "/FPGA,_Port0,_Port2,_PROG_IF/S6_TCK" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/S6_TDO" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/S6_TMS" -AddNet "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0" AddNet "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_0" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_11" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_10" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_12" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_15" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_16" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_18" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_2" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_20" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_25" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_28" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_29" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_3" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_30" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_32" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_39" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_45" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_46" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_48" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_5" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_50" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_52" +AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_56" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_6" AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_7" -AddNet "/FPGA_GPIOS/FPGA_BANK0_IO_8" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A10" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A12" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A2" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A4" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A5" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A6" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS#" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK#" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_LDM" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A0" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A12" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A2" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A7" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK#" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CS#" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDM" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_LDQS" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS#" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/M1_WE#" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A0" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A1" @@ -1855,37 +1983,42 @@ AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE#" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV" -AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VM" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV" +AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" AddNet "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VP" AddNet "/Image_Sensor/+1.8_VDD" -AddNet "/Image_Sensor/+2.8_VAA" -AddNet "/Image_Sensor/+2.8_VAAPIX" -AddNet "/Image_Sensor/+2.8_VDDIO" -AddNet "/Image_Sensor/+2.8_VDDPLL" -AddNet "/Image_Sensor/IS_DOUT0" AddNet "/Image_Sensor/IS_DOUT1" AddNet "/Image_Sensor/IS_DOUT2" -AddNet "/Image_Sensor/IS_DOUT4" +AddNet "/Image_Sensor/IS_DOUT3" +AddNet "/Image_Sensor/IS_DOUT5" AddNet "/Image_Sensor/IS_DOUT6" AddNet "/Image_Sensor/IS_DOUT7" -AddNet "/Image_Sensor/IS_DOUT9" +AddNet "/Image_Sensor/IS_DOUT8" +AddNet "/Image_Sensor/IS_FRAME" AddNet "/Image_Sensor/IS_I2C_ADDR" +AddNet "/Image_Sensor/IS_LINE" AddNet "/Image_Sensor/IS_OE_N" -AddNet "/Image_Sensor/IS_PIXEL" AddNet "/Image_Sensor/IS_RESET_N" AddNet "/Image_Sensor/IS_SDA" +AddNet "/Image_Sensor/IS_STANDBY" +AddNet "/Image_Sensor/IS_TEST" AddNet "/Non_volatile_memories/NF_ALE" -AddNet "/Non_volatile_memories/NF_D0" -AddNet "/Non_volatile_memories/NF_D3" -AddNet "/Non_volatile_memories/NF_D5" +AddNet "/Non_volatile_memories/NF_CLE" +AddNet "/Non_volatile_memories/NF_CS1_N" +AddNet "/Non_volatile_memories/NF_D2" +AddNet "/Non_volatile_memories/NF_D7" +AddNet "/Non_volatile_memories/NF_RE_N" +AddNet "/Non_volatile_memories/NF_WE_N" AddNet "/Non_volatile_memories/SD_CLK" AddNet "/Non_volatile_memories/SD_CMD" +AddNet "/Non_volatile_memories/SD_DAT0" AddNet "/Non_volatile_memories/SD_DAT1" AddNet "/Non_volatile_memories/SD_DAT3" AddNet "/Non_volatile_memories/SPI_DQ0" -AddNet "/Non_volatile_memories/SPI_FLASH_CS#" +AddNet "/Non_volatile_memories/SPI_DQ1" AddNet "/PSU/1.2V_EN" AddNet "/PSU/2.5V_EN" AddNet "/PSU/3.3V_EN" @@ -1893,7 +2026,6 @@ AddNet "/PSU/5V_EN" AddNet "/PSU/AVR_MISO" AddNet "/PSU/AVR_MOSI" AddNet "/PSU/AVR_RST" -AddNet "/PSU/AVR_SCK" AddNet "/PSU/Iout_1.2" AddNet "/PSU/SW_2.5" AddNet "/PSU/VFB1.2" @@ -1907,46 +2039,74 @@ AddNet "/PSU/VIN_DC-DC-5.0" AddNet "/PSU/lout_2.5" AddNet "/PSU/lout_3.3" AddNet "/PSU/lout_5.0" -AddNet "/USB/USBA_SPD" -AddNet "/USB/USBA_VP" +AddNet "/Snesor_PSU/+2.8_VAA" +AddNet "/Snesor_PSU/+2.8_VAAPIX" +AddNet "/Snesor_PSU/+2.8_VDDIO" +AddNet "/Snesor_PSU/+2.8_VDDPLL" +AddNet "/USB/USBA_RCV" +AddNet "/USB/USBA_VM" AddNet "/USB/USBD_OE_N" -AddNet "/USB/USBD_RCV" -AddNet "/USB/USBD_SPD" AddNet "/USB/USB_CASE_DEV" AddNet "/USB/USB_CASE_HOST" -AddNet "N-000115" +AddNet "N-000099" +AddNet "N-000132" +AddNet "N-000147" AddNet "N-000148" -AddNet "N-000163" -AddNet "N-000164" +AddNet "N-000152" +AddNet "N-000153" +AddNet "N-000154" +AddNet "N-000155" +AddNet "N-000156" +AddNet "N-000158" +AddNet "N-000159" +AddNet "N-000160" +AddNet "N-000162" AddNet "N-000168" -AddNet "N-000169" -AddNet "N-000170" -AddNet "N-000171" -AddNet "N-000172" -AddNet "N-000174" -AddNet "N-000176" -AddNet "N-000177" -AddNet "N-000178" -AddNet "N-000184" -AddNet "N-000194" -AddNet "N-000199" -AddNet "N-000376" -AddNet "N-000379" -AddNet "N-000422" -AddNet "N-000423" -AddNet "N-000424" -AddNet "N-000425" -AddNet "N-000426" -AddNet "N-000427" -AddNet "N-000428" -AddNet "N-000429" -AddNet "N-000430" -AddNet "N-000431" -AddNet "N-000432" -AddNet "N-000433" -AddNet "N-000434" -AddNet "N-000435" -AddNet "N-000436" +AddNet "N-000175" +AddNet "N-000180" +AddNet "N-000208" +AddNet "N-000209" +AddNet "N-000210" +AddNet "N-000211" +AddNet "N-000212" +AddNet "N-000213" +AddNet "N-000214" +AddNet "N-000215" +AddNet "N-000216" +AddNet "N-000217" +AddNet "N-000218" +AddNet "N-000219" +AddNet "N-000220" +AddNet "N-000221" +AddNet "N-000222" +AddNet "N-000223" +AddNet "N-000224" +AddNet "N-000226" +AddNet "N-000229" +AddNet "N-000231" +AddNet "N-000232" +AddNet "N-000233" +AddNet "N-000234" +AddNet "N-000235" +AddNet "N-000236" +AddNet "N-000237" +AddNet "N-000399" +AddNet "N-000402" +AddNet "N-000445" +AddNet "N-000446" +AddNet "N-000447" +AddNet "N-000448" +AddNet "N-000449" +AddNet "N-000450" +AddNet "N-000451" +AddNet "N-000452" +AddNet "N-000453" +AddNet "N-000454" +AddNet "N-000455" +AddNet "N-000456" +AddNet "N-000457" +AddNet "N-000458" +AddNet "N-000459" $EndNCLASS $NCLASS Name "ADDRESS/DDR" @@ -2040,7 +2200,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -4133 -4133 $EndPAD $PAD @@ -2061,133 +2221,133 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_CLK" +Ne 45 "/Ethernet_Phy/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/Ethernet_Phy/ETH_RXD1" +Ne 66 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/Ethernet_Phy/ETH_RXDV" +Ne 53 "/Ethernet_Phy/ETH_RXDV" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/Ethernet_Phy/ETH_RXC" +Ne 64 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/Ethernet_Phy/ETH_TXD3" +Ne 73 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" +Ne 46 "/Ethernet_Phy/ETH_COL" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_INT" +Ne 48 "/Ethernet_Phy/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" +Ne 113 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" +Ne 111 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D2" +Ne 301 "/Non_volatile_memories/NF_D2" Po 590 -4133 $EndPAD $PAD Sh "A14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 297 "/Non_volatile_memories/NF_ALE" +Ne 298 "/Non_volatile_memories/NF_ALE" Po 983 -4133 $EndPAD $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" +Ne 114 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" +Ne 121 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 301 "/Non_volatile_memories/SD_CLK" +Ne 305 "/Non_volatile_memories/SD_CLK" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0" +Ne 307 "/Non_volatile_memories/SD_DAT0" Po 2558 -4133 $EndPAD $PAD Sh "A19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TDO" +Ne 120 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TDO" Po 2952 -4133 $EndPAD $PAD Sh "A20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 337 "/USB/USBD_RCV" +Ne 278 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV" Po 3346 -4133 $EndPAD $PAD Sh "A21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 336 "/USB/USBD_OE_N" +Ne 344 "/USB/USBD_OE_N" Po 3739 -4133 $EndPAD $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 4133 -4133 $EndPAD $PAD @@ -2222,14 +2382,14 @@ $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2558 -3739 $EndPAD $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" +Ne 65 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" Po -2165 -3739 $EndPAD $PAD @@ -2243,21 +2403,21 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/Ethernet_Phy/ETH_RXER" +Ne 68 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER" Po -1377 -3739 $EndPAD $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -983 -3739 $EndPAD $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_CRS" +Ne 47 "/Ethernet_Phy/ETH_CRS" Po -590 -3739 $EndPAD $PAD @@ -2271,21 +2431,21 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 299 "/Non_volatile_memories/NF_D3" +Ne 110 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" Po 196 -3739 $EndPAD $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 590 -3739 $EndPAD $PAD Sh "B14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CLE" +Ne 299 "/Non_volatile_memories/NF_CLE" Po 983 -3739 $EndPAD $PAD @@ -2299,21 +2459,21 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 304 "/Non_volatile_memories/SD_DAT3" +Ne 309 "/Non_volatile_memories/SD_DAT3" Po 1771 -3739 $EndPAD $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 2165 -3739 $EndPAD $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 303 "/Non_volatile_memories/SD_DAT1" +Ne 308 "/Non_volatile_memories/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -2327,21 +2487,21 @@ $PAD Sh "B20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 338 "/USB/USBD_SPD" +Ne 279 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" Po 3346 -3739 $EndPAD $PAD Sh "B21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 279 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VP" +Ne 281 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VP" Po 3739 -3739 $EndPAD $PAD Sh "B22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 278 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" +Ne 280 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" Po 4133 -3739 $EndPAD $PAD @@ -2376,56 +2536,56 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/Ethernet_Phy/ETH_RXD3" +Ne 67 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/Ethernet_Phy/ETH_RXD2" +Ne 52 "/Ethernet_Phy/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" +Ne 63 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/Ethernet_Phy/ETH_TXC" +Ne 69 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" +Ne 71 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/Ethernet_Phy/ETH_TXD2" +Ne 72 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" Po -590 -3346 $EndPAD $PAD Sh "C11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 300 "/Non_volatile_memories/NF_D5" +Ne 112 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" Po -196 -3346 $EndPAD $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 298 "/Non_volatile_memories/NF_D0" +Ne 108 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D0" Po 196 -3346 $EndPAD $PAD @@ -2439,21 +2599,21 @@ $PAD Sh "C14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N" +Ne 304 "/Non_volatile_memories/NF_WE_N" Po 983 -3346 $EndPAD $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" +Ne 303 "/Non_volatile_memories/NF_RE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 302 "/Non_volatile_memories/SD_CMD" +Ne 306 "/Non_volatile_memories/SD_CMD" Po 1771 -3346 $EndPAD $PAD @@ -2467,7 +2627,7 @@ $PAD Sh "C18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TMS" +Ne 10 "/DBG_PRG/FPGA_TMS" Po 2558 -3346 $EndPAD $PAD @@ -2523,7 +2683,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2952 -2952 $EndPAD $PAD @@ -2537,42 +2697,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/ETH_MDIO" +Ne 62 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_MDC" +Ne 61 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER" +Ne 55 "/Ethernet_Phy/ETH_TXER" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" +Ne 54 "/Ethernet_Phy/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" +Ne 70 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" +Ne 302 "/Non_volatile_memories/NF_D7" Po -196 -2952 $EndPAD $PAD @@ -2593,14 +2753,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D1" +Ne 109 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D1" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N" +Ne 300 "/Non_volatile_memories/NF_CS1_N" Po 1377 -2952 $EndPAD $PAD @@ -2621,21 +2781,21 @@ $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 2558 -2952 $EndPAD $PAD Sh "D19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 333 "/USB/USBA_VP" +Ne 277 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP" Po 2952 -2952 $EndPAD $PAD Sh "D20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 277 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VM" +Ne 341 "/USB/USBA_VM" Po 3346 -2952 $EndPAD $PAD @@ -2663,7 +2823,7 @@ $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -3739 -2558 $EndPAD $PAD @@ -2698,7 +2858,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -1771 -2558 $EndPAD $PAD @@ -2726,7 +2886,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -196 -2558 $EndPAD $PAD @@ -2754,7 +2914,7 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1377 -2558 $EndPAD $PAD @@ -2775,7 +2935,7 @@ $PAD Sh "E18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DBG_PRG/FPGA_TDI" +Ne 9 "/DBG_PRG/FPGA_TDI" Po 2558 -2558 $EndPAD $PAD @@ -2796,7 +2956,7 @@ $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 3739 -2558 $EndPAD $PAD @@ -2915,14 +3075,14 @@ $PAD Sh "F16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 332 "/USB/USBA_SPD" +Ne 276 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD" Po 1771 -2165 $EndPAD $PAD Sh "F17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 276 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV" +Ne 340 "/USB/USBA_RCV" Po 2165 -2165 $EndPAD $PAD @@ -2992,7 +3152,7 @@ $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2558 -1771 $EndPAD $PAD @@ -3062,7 +3222,7 @@ $PAD Sh "G15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DBG_PRG/FPGA_TCK" +Ne 119 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TCK" Po 1377 -1771 $EndPAD $PAD @@ -3083,7 +3243,7 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 2558 -1771 $EndPAD $PAD @@ -3132,14 +3292,14 @@ $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK#" +Ne 149 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" +Ne 148 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" Po -2952 -1377 $EndPAD $PAD @@ -3160,7 +3320,7 @@ $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -1771 -1377 $EndPAD $PAD @@ -3279,7 +3439,7 @@ $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -3739 -983 $EndPAD $PAD @@ -3328,7 +3488,7 @@ $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -983 -983 $EndPAD $PAD @@ -3342,7 +3502,7 @@ $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -196 -983 $EndPAD $PAD @@ -3356,7 +3516,7 @@ $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 590 -983 $EndPAD $PAD @@ -3370,7 +3530,7 @@ $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1377 -983 $EndPAD $PAD @@ -3398,7 +3558,7 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK#" +Ne 32 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD @@ -3412,7 +3572,7 @@ $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 3739 -983 $EndPAD $PAD @@ -3489,7 +3649,7 @@ $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -590 -590 $EndPAD $PAD @@ -3503,7 +3663,7 @@ $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 196 -590 $EndPAD $PAD @@ -3517,7 +3677,7 @@ $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 983 -590 $EndPAD $PAD @@ -3608,7 +3768,7 @@ $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2558 -196 $EndPAD $PAD @@ -3636,7 +3796,7 @@ $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -983 -196 $EndPAD $PAD @@ -3650,7 +3810,7 @@ $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -196 -196 $EndPAD $PAD @@ -3664,7 +3824,7 @@ $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 590 -196 $EndPAD $PAD @@ -3699,7 +3859,7 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 2558 -196 $EndPAD $PAD @@ -3797,7 +3957,7 @@ $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -590 196 $EndPAD $PAD @@ -3811,7 +3971,7 @@ $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 196 196 $EndPAD $PAD @@ -3825,7 +3985,7 @@ $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 983 196 $EndPAD $PAD @@ -3895,7 +4055,7 @@ $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -3739 590 $EndPAD $PAD @@ -3944,7 +4104,7 @@ $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -983 590 $EndPAD $PAD @@ -3958,7 +4118,7 @@ $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -196 590 $EndPAD $PAD @@ -3972,7 +4132,7 @@ $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 590 590 $EndPAD $PAD @@ -3986,7 +4146,7 @@ $PAD Sh "N15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1377 590 $EndPAD $PAD @@ -4000,7 +4160,7 @@ $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 2165 590 $EndPAD $PAD @@ -4028,7 +4188,7 @@ $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 3739 590 $EndPAD $PAD @@ -4105,7 +4265,7 @@ $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -590 983 $EndPAD $PAD @@ -4119,7 +4279,7 @@ $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 196 983 $EndPAD $PAD @@ -4133,7 +4293,7 @@ $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 983 983 $EndPAD $PAD @@ -4224,7 +4384,7 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2558 1377 $EndPAD $PAD @@ -4301,7 +4461,7 @@ $PAD Sh "R16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" +Ne 123 "/FPGA_GPIOS/FPGA_BANK0_IO_12" Po 1771 1377 $EndPAD $PAD @@ -4315,7 +4475,7 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 2558 1377 $EndPAD $PAD @@ -4378,7 +4538,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 306 "/Non_volatile_memories/SPI_FLASH_CS#" +Ne 116 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -4406,7 +4566,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -983 1771 $EndPAD $PAD @@ -4434,42 +4594,42 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po 590 1771 $EndPAD $PAD Sh "T14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" +Ne 90 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" Po 983 1771 $EndPAD $PAD Sh "T15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA_GPIOS/FPGA_BANK0_IO_7" +Ne 137 "/FPGA_GPIOS/FPGA_BANK0_IO_7" Po 1377 1771 $EndPAD $PAD Sh "T16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA_GPIOS/FPGA_BANK0_IO_6" +Ne 136 "/FPGA_GPIOS/FPGA_BANK0_IO_6" Po 1771 1771 $EndPAD $PAD Sh "T17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_GPIOS/FPGA_BANK0_IO_2" +Ne 80 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_2" Po 2165 1771 $EndPAD $PAD Sh "T18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" +Ne 75 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" Po 2558 1771 $EndPAD $PAD @@ -4511,7 +4671,7 @@ $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -3739 2165 $EndPAD $PAD @@ -4546,7 +4706,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -1771 2165 $EndPAD $PAD @@ -4567,7 +4727,7 @@ $PAD Sh "U10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56" +Ne 135 "/FPGA_GPIOS/FPGA_BANK0_IO_56" Po -590 2165 $EndPAD $PAD @@ -4588,35 +4748,35 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" +Ne 118 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" +Ne 117 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" Po 983 2165 $EndPAD $PAD Sh "U15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_GPIOS/FPGA_BANK0_IO_16" +Ne 125 "/FPGA_GPIOS/FPGA_BANK0_IO_16" Po 1377 2165 $EndPAD $PAD Sh "U16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" +Ne 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" Po 1771 2165 $EndPAD $PAD Sh "U17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_GPIOS/FPGA_BANK0_IO_8" +Ne 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8" Po 2165 2165 $EndPAD $PAD @@ -4644,7 +4804,7 @@ $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 3739 2165 $EndPAD $PAD @@ -4679,7 +4839,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2952 2558 $EndPAD $PAD @@ -4707,35 +4867,35 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -1377 2558 $EndPAD $PAD Sh "V9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA_GPIOS/FPGA_BANK0_IO_52" +Ne 134 "/FPGA_GPIOS/FPGA_BANK0_IO_52" Po -983 2558 $EndPAD $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -590 2558 $EndPAD $PAD Sh "V11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" +Ne 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" Po -196 2558 $EndPAD $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po 196 2558 $EndPAD $PAD @@ -4749,42 +4909,42 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 983 2558 $EndPAD $PAD Sh "V15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" +Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" Po 1377 2558 $EndPAD $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po 1771 2558 $EndPAD $PAD Sh "V17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" +Ne 77 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" Po 2165 2558 $EndPAD $PAD Sh "V18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_GPIOS/FPGA_BANK0_IO_11" +Ne 76 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" Po 2558 2558 $EndPAD $PAD Sh "V19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_10" +Ne 122 "/FPGA_GPIOS/FPGA_BANK0_IO_10" Po 2952 2558 $EndPAD $PAD @@ -4840,7 +5000,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -2558 2952 $EndPAD $PAD @@ -4854,77 +5014,77 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -1771 2952 $EndPAD $PAD Sh "W8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" +Ne 131 "/FPGA_GPIOS/FPGA_BANK0_IO_48" Po -1377 2952 $EndPAD $PAD Sh "W9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50" +Ne 133 "/FPGA_GPIOS/FPGA_BANK0_IO_50" Po -983 2952 $EndPAD $PAD Sh "W10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46" +Ne 130 "/FPGA_GPIOS/FPGA_BANK0_IO_46" Po -590 2952 $EndPAD $PAD Sh "W11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" +Ne 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" Po -196 2952 $EndPAD $PAD Sh "W12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK" +Ne 103 "/FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK" Po 196 2952 $EndPAD $PAD Sh "W13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_27" +Ne 86 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_27" Po 590 2952 $EndPAD $PAD Sh "W14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/FPGA_GPIOS/FPGA_BANK0_IO_30" +Ne 128 "/FPGA_GPIOS/FPGA_BANK0_IO_30" Po 983 2952 $EndPAD $PAD Sh "W15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA_GPIOS/FPGA_BANK0_IO_25" +Ne 85 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_25" Po 1377 2952 $EndPAD $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1771 2952 $EndPAD $PAD Sh "W17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_GPIOS/FPGA_BANK0_IO_15" +Ne 124 "/FPGA_GPIOS/FPGA_BANK0_IO_15" Po 2165 2952 $EndPAD $PAD @@ -4938,7 +5098,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 2952 2952 $EndPAD $PAD @@ -4980,7 +5140,7 @@ $PAD Sh "Y3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA,_Port0,_Port2,_PROG_IF/IS_TRIGGER" +Ne 107 "/FPGA,_Port0,_Port2,_PROG_IF/IS_TRIGGER" Po -3346 3346 $EndPAD $PAD @@ -4994,7 +5154,7 @@ $PAD Sh "Y5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY" +Ne 296 "/Image_Sensor/IS_STANDBY" Po -2558 3346 $EndPAD $PAD @@ -5008,42 +5168,42 @@ $PAD Sh "Y7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 291 "/Image_Sensor/IS_DOUT9" +Ne 102 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" Po -1771 3346 $EndPAD $PAD Sh "Y8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 289 "/Image_Sensor/IS_DOUT6" +Ne 287 "/Image_Sensor/IS_DOUT6" Po -1377 3346 $EndPAD $PAD Sh "Y9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/FPGA_GPIOS/FPGA_BANK0_IO_45" +Ne 129 "/FPGA_GPIOS/FPGA_BANK0_IO_45" Po -983 3346 $EndPAD $PAD Sh "Y10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" +Ne 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" Po -590 3346 $EndPAD $PAD Sh "Y11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" +Ne 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" Po -196 3346 $EndPAD $PAD Sh "Y12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" +Ne 106 "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" Po 196 3346 $EndPAD $PAD @@ -5064,35 +5224,35 @@ $PAD Sh "Y15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/FPGA_GPIOS/FPGA_BANK0_IO_32" +Ne 88 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32" Po 1377 3346 $EndPAD $PAD Sh "Y16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24" +Ne 84 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24" Po 1771 3346 $EndPAD $PAD Sh "Y17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_GPIOS/FPGA_BANK0_IO_20" +Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20" Po 2165 3346 $EndPAD $PAD Sh "Y18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA_GPIOS/FPGA_BANK0_IO_5" +Ne 132 "/FPGA_GPIOS/FPGA_BANK0_IO_5" Po 2558 3346 $EndPAD $PAD Sh "Y19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/FPGA_GPIOS/FPGA_BANK0_IO_3" +Ne 127 "/FPGA_GPIOS/FPGA_BANK0_IO_3" Po 2952 3346 $EndPAD $PAD @@ -5113,203 +5273,203 @@ $PAD Sh "Y22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 358 "N-000376" +Ne 390 "N-000399" Po 4133 3346 $EndPAD $PAD Sh "AA1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 359 "N-000379" +Ne 391 "N-000402" Po -4133 3739 $EndPAD $PAD Sh "AA2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA,_Port0,_Port2,_PROG_IF/IS_LINE" +Ne 292 "/Image_Sensor/IS_LINE" Po -3739 3739 $EndPAD $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -3346 3739 $EndPAD $PAD Sh "AA4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA,_Port0,_Port2,_PROG_IF/IS_TEST" +Ne 297 "/Image_Sensor/IS_TEST" Po -2952 3739 $EndPAD $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2558 3739 $EndPAD $PAD Sh "AA6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 296 "/Image_Sensor/IS_SDA" +Ne 295 "/Image_Sensor/IS_SDA" Po -2165 3739 $EndPAD $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -1771 3739 $EndPAD $PAD Sh "AA8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 290 "/Image_Sensor/IS_DOUT7" +Ne 288 "/Image_Sensor/IS_DOUT7" Po -1377 3739 $EndPAD $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -983 3739 $EndPAD $PAD Sh "AA10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 288 "/Image_Sensor/IS_DOUT4" +Ne 101 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT4" Po -590 3739 $EndPAD $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -196 3739 $EndPAD $PAD Sh "AA12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 286 "/Image_Sensor/IS_DOUT1" +Ne 283 "/Image_Sensor/IS_DOUT1" Po 196 3739 $EndPAD $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 590 3739 $EndPAD $PAD Sh "AA14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" +Ne 83 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" Po 983 3739 $EndPAD $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po 1377 3739 $EndPAD $PAD Sh "AA16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/FPGA_GPIOS/FPGA_BANK0_IO_28" +Ne 126 "/FPGA_GPIOS/FPGA_BANK0_IO_28" Po 1771 3739 $EndPAD $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 2165 3739 $EndPAD $PAD Sh "AA18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_GPIOS/FPGA_BANK0_IO_18" +Ne 79 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_18" Po 2558 3739 $EndPAD $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po 2952 3739 $EndPAD $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1" +Ne 311 "/Non_volatile_memories/SPI_DQ1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" +Ne 115 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" Po 3739 3739 $EndPAD $PAD Sh "AA22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_GPIOS/FPGA_BANK0_IO_0" +Ne 74 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_0" Po 4133 3739 $EndPAD $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -4133 4133 $EndPAD $PAD Sh "AB2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" +Ne 290 "/Image_Sensor/IS_FRAME" Po -3739 4133 $EndPAD $PAD Sh "AB3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" +Ne 104 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" Po -3346 4133 $EndPAD $PAD Sh "AB4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 292 "/Image_Sensor/IS_I2C_ADDR" +Ne 291 "/Image_Sensor/IS_I2C_ADDR" Po -2952 4133 $EndPAD $PAD Sh "AB5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 295 "/Image_Sensor/IS_RESET_N" +Ne 294 "/Image_Sensor/IS_RESET_N" Po -2558 4133 $EndPAD $PAD Sh "AB6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 294 "/Image_Sensor/IS_PIXEL" +Ne 105 "/FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL" Po -2165 4133 $EndPAD $PAD @@ -5323,42 +5483,42 @@ $PAD Sh "AB8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8" +Ne 289 "/Image_Sensor/IS_DOUT8" Po -1377 4133 $EndPAD $PAD Sh "AB9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5" +Ne 286 "/Image_Sensor/IS_DOUT5" Po -983 4133 $EndPAD $PAD Sh "AB10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" +Ne 285 "/Image_Sensor/IS_DOUT3" Po -590 4133 $EndPAD $PAD Sh "AB11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 287 "/Image_Sensor/IS_DOUT2" +Ne 284 "/Image_Sensor/IS_DOUT2" Po -196 4133 $EndPAD $PAD Sh "AB12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 285 "/Image_Sensor/IS_DOUT0" +Ne 98 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0" Po 196 4133 $EndPAD $PAD Sh "AB13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/FPGA_GPIOS/FPGA_BANK0_IO_39" +Ne 91 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39" Po 590 4133 $EndPAD $PAD @@ -5372,21 +5532,21 @@ $PAD Sh "AB15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" +Ne 89 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" Po 1377 4133 $EndPAD $PAD Sh "AB16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/FPGA_GPIOS/FPGA_BANK0_IO_29" +Ne 87 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29" Po 1771 4133 $EndPAD $PAD Sh "AB17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" +Ne 82 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" Po 2165 4133 $EndPAD $PAD @@ -5407,7 +5567,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 305 "/Non_volatile_memories/SPI_DQ0" +Ne 310 "/Non_volatile_memories/SPI_DQ0" Po 3346 4133 $EndPAD $PAD @@ -5421,7 +5581,7 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 @@ -5443,77 +5603,77 @@ $PAD Sh "PAD" R 904 628 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 0 0 $EndPAD $PAD Sh "1" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 308 "/PSU/2.5V_EN" +Ne 313 "/PSU/2.5V_EN" Po -393 491 $EndPAD $PAD Sh "10" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 357 "N-000199" +Ne 363 "N-000180" Po -393 -491 $EndPAD $PAD Sh "2" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -196 491 $EndPAD $PAD Sh "9" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 320 "/PSU/VFB2.5" +Ne 324 "/PSU/VFB2.5" Po -196 -491 $EndPAD $PAD Sh "3" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 317 "/PSU/SW_2.5" +Ne 321 "/PSU/SW_2.5" Po 0 491 $EndPAD $PAD Sh "8" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 324 "/PSU/VIN_DC-DC-2.5" +Ne 328 "/PSU/VIN_DC-DC-2.5" Po 0 -491 $EndPAD $PAD Sh "4" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 317 "/PSU/SW_2.5" +Ne 321 "/PSU/SW_2.5" Po 196 491 $EndPAD $PAD Sh "7" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 324 "/PSU/VIN_DC-DC-2.5" +Ne 328 "/PSU/VIN_DC-DC-2.5" Po 196 -491 $EndPAD $PAD Sh "5" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 393 491 $EndPAD $PAD Sh "6" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 324 "/PSU/VIN_DC-DC-2.5" +Ne 328 "/PSU/VIN_DC-DC-2.5" Po 393 -491 $EndPAD $EndMODULE DFN10 @@ -5541,7 +5701,7 @@ $PAD Sh "2" R 157 236 0 0 1350 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5569,7 +5729,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5597,7 +5757,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Banks/M0_UDM" +Ne 164 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5625,7 +5785,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Banks/M0_UDQS" +Ne 165 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5653,7 +5813,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 17 "/DDR_Banks/M0_CKE" +Ne 147 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5674,14 +5834,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" +Ne 148 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK#" +Ne 149 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5728,28 +5888,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 152 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" +Ne 142 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 151 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A2" +Ne 141 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 9 "/DDR_Banks/M0_A1" +Ne 139 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 8 "/DDR_Banks/M0_A0" +Ne 138 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5796,28 +5956,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A10" +Ne 15 "/DDR_Banks/M0_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" +Ne 21 "/DDR_Banks/M0_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 15 "/DDR_Banks/M0_BA0" +Ne 20 "/DDR_Banks/M0_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M0_RAS#" +Ne 163 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5864,28 +6024,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 16 "/DDR_Banks/M0_CAS#" +Ne 146 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" +Ne 28 "/DDR_Banks/M0_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_LDM" +Ne 25 "/DDR_Banks/M0_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS" +Ne 26 "/DDR_Banks/M0_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5932,28 +6092,28 @@ $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A4" +Ne 17 "/DDR_Banks/M0_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 154 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A5" +Ne 18 "/DDR_Banks/M0_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 12 "/DDR_Banks/M0_A6" +Ne 143 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 13 "/DDR_Banks/M0_A7" +Ne 144 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6000,28 +6160,28 @@ $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 14 "/DDR_Banks/M0_A8" +Ne 19 "/DDR_Banks/M0_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" +Ne 145 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 10 "/DDR_Banks/M0_A11" +Ne 16 "/DDR_Banks/M0_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 11 "/DDR_Banks/M0_A12" +Ne 140 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6068,28 +6228,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7" +Ne 160 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" +Ne 159 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 22 "/DDR_Banks/M0_DQ5" +Ne 158 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" +Ne 24 "/DDR_Banks/M0_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6136,28 +6296,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" +Ne 157 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" +Ne 156 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" +Ne 151 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Banks/M0_DQ0" +Ne 150 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6204,28 +6364,28 @@ $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 19 "/DDR_Banks/M0_DQ11" +Ne 23 "/DDR_Banks/M0_DQ11" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10" +Ne 22 "/DDR_Banks/M0_DQ10" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Banks/M0_DQ9" +Ne 162 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/DDR_Banks/M0_DQ8" +Ne 161 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6272,28 +6432,28 @@ $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 21 "/DDR_Banks/M0_DQ15" +Ne 155 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" +Ne 154 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" +Ne 153 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/DDR_Banks/M0_DQ12" +Ne 152 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6315,105 +6475,105 @@ $PAD Sh "PAD" R 433 433 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -235 -235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 235 235 $EndPAD $PAD Sh "PAD" R 433 433 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 235 -235 $EndPAD $PAD Sh "15" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 310 "/PSU/5V_EN" +Ne 315 "/PSU/5V_EN" Po -393 688 $EndPAD $PAD Sh "1" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 314 "/PSU/AVR_SCK" +Ne 8 "/DBG_PRG/AVR_SCK" Po -393 -688 $EndPAD $PAD Sh "14" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 329 "/PSU/lout_5.0" +Ne 333 "/PSU/lout_5.0" Po -196 688 $EndPAD $PAD Sh "2" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 315 "/PSU/Iout_1.2" +Ne 319 "/PSU/Iout_1.2" Po -196 -688 $EndPAD $PAD Sh "13" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 313 "/PSU/AVR_RST" +Ne 318 "/PSU/AVR_RST" Po 0 688 $EndPAD $PAD Sh "3" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 307 "/PSU/1.2V_EN" +Ne 312 "/PSU/1.2V_EN" Po 0 -688 $EndPAD $PAD Sh "12" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 308 "/PSU/2.5V_EN" +Ne 313 "/PSU/2.5V_EN" Po 196 688 $EndPAD $PAD Sh "4" R 99 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 328 "/PSU/lout_3.3" +Ne 332 "/PSU/lout_3.3" Po 196 -688 $EndPAD $PAD Sh "11" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 327 "/PSU/lout_2.5" +Ne 331 "/PSU/lout_2.5" Po 393 688 $EndPAD $PAD Sh "5" R 98 157 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 309 "/PSU/3.3V_EN" +Ne 314 "/PSU/3.3V_EN" Po 393 -688 $EndPAD $PAD Sh "20" R 157 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 311 "/PSU/AVR_MISO" +Ne 316 "/PSU/AVR_MISO" Po -688 -393 $EndPAD $PAD @@ -6448,7 +6608,7 @@ $PAD Sh "8" R 157 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 688 0 $EndPAD $PAD @@ -6469,7 +6629,7 @@ $PAD Sh "16" R 157 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 312 "/PSU/AVR_MOSI" +Ne 317 "/PSU/AVR_MOSI" Po -688 393 $EndPAD $PAD @@ -6504,7 +6664,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 45 "/DDR_Banks/M1_UDQS" +Ne 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6532,7 +6692,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CS#" +Ne 33 "/DDR_Banks/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6560,7 +6720,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" +Ne 31 "/DDR_Banks/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6588,7 +6748,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDM" +Ne 40 "/DDR_Banks/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6607,28 +6767,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15" +Ne 35 "/DDR_Banks/M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_DQ14" +Ne 34 "/DDR_Banks/M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" +Ne 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 37 "/DDR_Banks/M1_DQ12" +Ne 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12" Po 295 -177 $EndPAD $PAD @@ -6675,28 +6835,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" +Ne 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" +Ne 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/DDR_Banks/M1_DQ9" +Ne 38 "/DDR_Banks/M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/DDR_Banks/M1_DQ8" +Ne 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" Po 295 -177 $EndPAD $PAD @@ -6745,7 +6905,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK#" +Ne 32 "/DDR_Banks/M1_CLK#" Po -176 0 $EndPAD $PAD @@ -6771,28 +6931,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 172 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A12" +Ne 169 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/DDR_Banks/M1_A11" +Ne 29 "/DDR_Banks/M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" +Ne 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_A8" +Ne 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" Po 295 -177 $EndPAD $PAD @@ -6839,28 +6999,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A7" +Ne 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" +Ne 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" +Ne 172 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" +Ne 171 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" Po 295 -177 $EndPAD $PAD @@ -6935,28 +7095,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" +Ne 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" +Ne 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" +Ne 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0" +Ne 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -7003,7 +7163,7 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 36 "/DDR_Banks/M1_CAS#" +Ne 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" Po 295 177 $EndPAD $PAD @@ -7017,14 +7177,14 @@ $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/DDR_Banks/M1_LDM" +Ne 39 "/DDR_Banks/M1_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/DDR_Banks/M1_LDQS" +Ne 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -7071,28 +7231,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7" +Ne 37 "/DDR_Banks/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" +Ne 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M1_DQ5" +Ne 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4" +Ne 36 "/DDR_Banks/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -7139,28 +7299,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Banks/M1_A10" +Ne 168 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/DDR_Banks/M1_BA1" +Ne 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/DDR_Banks/M1_BA0" +Ne 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 44 "/DDR_Banks/M1_RAS#" +Ne 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -7207,28 +7367,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Banks/M1_A3" +Ne 170 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A2" +Ne 30 "/DDR_Banks/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" +Ne 167 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/DDR_Banks/M1_A0" +Ne 166 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -7249,7 +7409,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -176 0 $EndPAD $PAD @@ -7277,14 +7437,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 48 "/Ethernet_Phy/ETH_A1.8V" +Ne 43 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 56 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 51 "/Ethernet_Phy/ETH_PLL1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7305,14 +7465,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/ETH_1.8V" +Ne 42 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 48 "/Ethernet_Phy/ETH_A1.8V" +Ne 43 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7340,7 +7500,7 @@ $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7368,7 +7528,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7396,7 +7556,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7424,7 +7584,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7452,7 +7612,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7479,56 +7639,56 @@ $PAD Sh "8" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -750 -1050 $EndPAD $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 306 "/Non_volatile_memories/SPI_FLASH_CS#" +Ne 116 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" +Ne 118 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" +Ne 115 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 305 "/Non_volatile_memories/SPI_DQ0" +Ne 310 "/Non_volatile_memories/SPI_DQ0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1" +Ne 311 "/Non_volatile_memories/SPI_DQ1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" +Ne 117 "/FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2" Po 250 1050 $EndPAD $PAD Sh "4" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 750 1050 $EndPAD $SHAPE3D @@ -7562,7 +7722,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -7590,7 +7750,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7618,7 +7778,7 @@ $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7646,7 +7806,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7674,7 +7834,7 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7702,7 +7862,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7723,14 +7883,14 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7758,7 +7918,7 @@ $PAD Sh "2" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1210 @@ -7786,7 +7946,7 @@ $PAD Sh "2" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7814,7 +7974,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7842,7 +8002,7 @@ $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7870,7 +8030,7 @@ $PAD Sh "2" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7898,7 +8058,7 @@ $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7919,14 +8079,14 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7954,7 +8114,7 @@ $PAD Sh "2" R 275 510 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -7982,7 +8142,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8010,7 +8170,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8038,7 +8198,7 @@ $PAD Sh "2" R 157 236 0 0 2250 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8066,7 +8226,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8094,7 +8254,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8122,7 +8282,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8150,7 +8310,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8178,7 +8338,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8199,14 +8359,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8234,7 +8394,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8262,7 +8422,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8283,14 +8443,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8318,7 +8478,7 @@ $PAD Sh "2" R 157 236 0 0 450 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8346,7 +8506,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8367,14 +8527,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8402,7 +8562,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8423,14 +8583,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 342 "N-000115" +Ne 348 "N-000099" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8451,14 +8611,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 334 "/USB/USBD_D+" +Ne 342 "/USB/USBD_D+" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8479,14 +8639,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 335 "/USB/USBD_D-" +Ne 343 "/USB/USBD_D-" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8514,7 +8674,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8535,14 +8695,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 347 "N-000169" +Ne 360 "N-000162" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8563,14 +8723,14 @@ $PAD Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 354 "N-000178" +Ne 359 "N-000160" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 353 "N-000177" +Ne 358 "N-000159" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8591,14 +8751,14 @@ $PAD Sh "1" R 197 354 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 352 "N-000176" +Ne 357 "N-000158" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8619,14 +8779,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/DDR_Banks/M1_VREF" +Ne 41 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8654,7 +8814,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8682,7 +8842,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8710,7 +8870,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8738,7 +8898,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8766,7 +8926,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8794,7 +8954,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8822,7 +8982,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8850,7 +9010,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8878,7 +9038,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8906,7 +9066,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8934,7 +9094,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8962,7 +9122,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8990,7 +9150,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/DDR_Banks/M1_VREF" +Ne 41 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9011,14 +9171,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M0_VREF" +Ne 27 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9046,7 +9206,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M0_VREF" +Ne 27 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9074,7 +9234,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/DDR_Banks/M1_VREF" +Ne 41 "/DDR_Banks/M1_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9095,14 +9255,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/DDR_Banks/M1_VREF" +Ne 41 "/DDR_Banks/M1_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9123,14 +9283,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M0_VREF" +Ne 27 "/DDR_Banks/M0_VREF" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9158,7 +9318,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M0_VREF" +Ne 27 "/DDR_Banks/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9184,56 +9344,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 353 "N-000177" +Ne 358 "N-000159" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 331 "/USB/USBA_D-" +Ne 339 "/USB/USBA_D-" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 330 "/USB/USBA_D+" +Ne 338 "/USB/USBA_D+" Po 0 -787 $EndPAD $PAD Sh "4" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 352 "N-000176" +Ne 357 "N-000158" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 340 "/USB/USB_CASE_HOST" +Ne 346 "/USB/USB_CASE_HOST" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 340 "/USB/USB_CASE_HOST" +Ne 346 "/USB/USB_CASE_HOST" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 340 "/USB/USB_CASE_HOST" +Ne 346 "/USB/USB_CASE_HOST" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 340 "/USB/USB_CASE_HOST" +Ne 346 "/USB/USB_CASE_HOST" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -9254,7 +9414,7 @@ $PAD Sh "1" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 354 "N-000178" +Ne 359 "N-000160" Po -570 0 $EndPAD $PAD @@ -9289,7 +9449,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9310,14 +9470,14 @@ $PAD Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_A3.3V" +Ne 44 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9345,7 +9505,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9366,14 +9526,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 330 "/USB/USBA_D+" +Ne 338 "/USB/USBA_D+" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9394,14 +9554,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 331 "/USB/USBA_D-" +Ne 339 "/USB/USBA_D-" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -9422,14 +9582,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/ETH_1.8V" +Ne 42 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9457,7 +9617,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9478,14 +9638,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/ETH_1.8V" +Ne 42 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9513,7 +9673,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9534,14 +9694,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 48 "/Ethernet_Phy/ETH_A1.8V" +Ne 43 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9562,14 +9722,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 49 "/Ethernet_Phy/ETH_A3.3V" +Ne 44 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9590,14 +9750,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 56 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 51 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9625,7 +9785,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9653,7 +9813,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9674,7 +9834,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 55 "/Ethernet_Phy/ETH_MDIO" +Ne 62 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -9702,14 +9862,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 343 "N-000148" +Ne 349 "N-000132" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9737,7 +9897,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 69 "/Ethernet_Phy/MAG_TX+" +Ne 59 "/Ethernet_Phy/MAG_TX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9765,7 +9925,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 70 "/Ethernet_Phy/MAG_TX-" +Ne 60 "/Ethernet_Phy/MAG_TX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9793,7 +9953,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 66 "/Ethernet_Phy/MAG_RX+" +Ne 56 "/Ethernet_Phy/MAG_RX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9821,7 +9981,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 67 "/Ethernet_Phy/MAG_RX-" +Ne 57 "/Ethernet_Phy/MAG_RX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9842,14 +10002,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 345 "N-000164" +Ne 351 "N-000148" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 52 "/Ethernet_Phy/ETH_LED0" +Ne 49 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9870,14 +10030,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 344 "N-000163" +Ne 350 "N-000147" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 53 "/Ethernet_Phy/ETH_LED1" +Ne 50 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9906,7 +10066,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_DQ0" +Ne 150 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -9920,35 +10080,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" +Ne 151 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" +Ne 156 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" +Ne 157 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4" +Ne 24 "/DDR_Banks/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -9962,28 +10122,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_DQ5" +Ne 158 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" +Ne 159 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7" +Ne 160 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -10004,7 +10164,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS" +Ne 26 "/DDR_Banks/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -10032,35 +10192,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_LDM" +Ne 25 "/DDR_Banks/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_WE#" +Ne 28 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_CAS#" +Ne 146 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M0_RAS#" +Ne 163 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1791 2176 $EndPAD $PAD @@ -10074,49 +10234,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_BA0" +Ne 20 "/DDR_Banks/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1" +Ne 21 "/DDR_Banks/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A10" +Ne 15 "/DDR_Banks/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A0" +Ne 138 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A1" +Ne 139 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A2" +Ne 141 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" +Ne 142 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -10130,63 +10290,63 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A4" +Ne 17 "/DDR_Banks/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A5" +Ne 18 "/DDR_Banks/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_A6" +Ne 143 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_A7" +Ne 144 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_A8" +Ne 19 "/DDR_Banks/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" +Ne 145 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_A11" +Ne 16 "/DDR_Banks/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_A12" +Ne 140 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -10200,42 +10360,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK#" +Ne 149 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_CKE" +Ne 147 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" +Ne 148 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M0_UDM" +Ne 164 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M0_VREF" +Ne 27 "/DDR_Banks/M0_VREF" Po 255 -2176 $EndPAD $PAD @@ -10249,14 +10409,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M0_UDQS" +Ne 165 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -511 -2176 $EndPAD $PAD @@ -10270,7 +10430,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M0_DQ8" +Ne 161 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10284,35 +10444,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M0_DQ9" +Ne 162 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10" +Ne 22 "/DDR_Banks/M0_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_DQ11" +Ne 23 "/DDR_Banks/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_DQ12" +Ne 152 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10326,35 +10486,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" +Ne 153 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" +Ne 154 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_DQ15" +Ne 155 "/FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -10383,7 +10543,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0" +Ne 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -10397,35 +10557,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" +Ne 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" +Ne 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" +Ne 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4" +Ne 36 "/DDR_Banks/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -10439,28 +10599,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M1_DQ5" +Ne 189 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" +Ne 190 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7" +Ne 37 "/DDR_Banks/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -10481,7 +10641,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/DDR_Banks/M1_LDQS" +Ne 192 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -10509,7 +10669,7 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/DDR_Banks/M1_LDM" +Ne 39 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD @@ -10523,21 +10683,21 @@ $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_CAS#" +Ne 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/DDR_Banks/M1_RAS#" +Ne 193 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CS#" +Ne 33 "/DDR_Banks/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -10551,49 +10711,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_BA0" +Ne 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_BA1" +Ne 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_A10" +Ne 168 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_A0" +Ne 166 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" +Ne 167 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A2" +Ne 30 "/DDR_Banks/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_A3" +Ne 170 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -10607,63 +10767,63 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" +Ne 171 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" +Ne 172 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" +Ne 173 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A7" +Ne 174 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_A8" +Ne 175 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" +Ne 176 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_A11" +Ne 29 "/DDR_Banks/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A12" +Ne 169 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -10677,14 +10837,14 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK#" +Ne 32 "/DDR_Banks/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE" +Ne 31 "/DDR_Banks/M1_CKE" Po 1279 -2176 $EndPAD $PAD @@ -10698,21 +10858,21 @@ $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDM" +Ne 40 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/DDR_Banks/M1_VREF" +Ne 41 "/DDR_Banks/M1_VREF" Po 255 -2176 $EndPAD $PAD @@ -10726,14 +10886,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/DDR_Banks/M1_UDQS" +Ne 194 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -511 -2176 $EndPAD $PAD @@ -10747,7 +10907,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/DDR_Banks/M1_DQ8" +Ne 191 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10761,35 +10921,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/DDR_Banks/M1_DQ9" +Ne 38 "/DDR_Banks/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" +Ne 183 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" +Ne 184 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/DDR_Banks/M1_DQ12" +Ne 185 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10803,35 +10963,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" +Ne 186 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_DQ14" +Ne 34 "/DDR_Banks/M1_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15" +Ne 35 "/DDR_Banks/M1_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -10851,35 +11011,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 68 "/Ethernet_Phy/MAG_SHIELD" +Ne 58 "/Ethernet_Phy/MAG_SHIELD" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 68 "/Ethernet_Phy/MAG_SHIELD" +Ne 58 "/Ethernet_Phy/MAG_SHIELD" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 68 "/Ethernet_Phy/MAG_SHIELD" +Ne 58 "/Ethernet_Phy/MAG_SHIELD" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 68 "/Ethernet_Phy/MAG_SHIELD" +Ne 58 "/Ethernet_Phy/MAG_SHIELD" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 69 "/Ethernet_Phy/MAG_TX+" +Ne 59 "/Ethernet_Phy/MAG_TX+" Po -1750 -2500 $EndPAD $PAD @@ -10893,28 +11053,28 @@ $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 341 "GND" +Ne 347 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 66 "/Ethernet_Phy/MAG_RX+" +Ne 56 "/Ethernet_Phy/MAG_RX+" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 70 "/Ethernet_Phy/MAG_TX-" +Ne 60 "/Ethernet_Phy/MAG_TX-" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 341 "GND" +Ne 347 "GND" Po -250 -3500 $EndPAD $PAD @@ -10928,7 +11088,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 67 "/Ethernet_Phy/MAG_RX-" +Ne 57 "/Ethernet_Phy/MAG_RX-" Po 1750 -3500 $EndPAD $PAD @@ -10942,7 +11102,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 345 "N-000164" +Ne 351 "N-000148" Po -1150 -5400 $EndPAD $PAD @@ -10956,7 +11116,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 344 "N-000163" +Ne 350 "N-000147" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -10981,21 +11141,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 129 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" +Ne 121 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 304 "/Non_volatile_memories/SD_DAT3" +Ne 309 "/Non_volatile_memories/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 302 "/Non_volatile_memories/SD_CMD" +Ne 306 "/Non_volatile_memories/SD_CMD" Po -433 0 $EndPAD $PAD @@ -11009,56 +11169,56 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 301 "/Non_volatile_memories/SD_CLK" +Ne 305 "/Non_volatile_memories/SD_CLK" Po 433 0 $EndPAD $PAD Sh "6" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 866 0 $EndPAD $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 128 "/FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0" +Ne 307 "/Non_volatile_memories/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 303 "/Non_volatile_memories/SD_DAT1" +Ne 308 "/Non_volatile_memories/SD_DAT1" Po 1732 0 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po -2707 1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po -2707 -2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 2707 -2244 $EndPAD $EndMODULE MICROSD-500901 @@ -11322,28 +11482,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" +Ne 114 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" +Ne 114 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N" +Ne 303 "/Non_volatile_memories/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N" +Ne 300 "/Non_volatile_memories/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -11371,7 +11531,7 @@ $PAD Sh "13" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 100 3850 $EndPAD $PAD @@ -11392,21 +11552,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA,_Port0,_Port2,_PROG_IF/NF_CLE" +Ne 299 "/Non_volatile_memories/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 297 "/Non_volatile_memories/NF_ALE" +Ne 298 "/Non_volatile_memories/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N" +Ne 304 "/Non_volatile_memories/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -11483,28 +11643,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 298 "/Non_volatile_memories/NF_D0" +Ne 108 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D1" +Ne 109 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D2" +Ne 301 "/Non_volatile_memories/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 299 "/Non_volatile_memories/NF_D3" +Ne 110 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -11532,7 +11692,7 @@ $PAD Sh "36" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 100 -3850 $EndPAD $PAD @@ -11567,28 +11727,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" +Ne 111 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 300 "/Non_volatile_memories/NF_D5" +Ne 112 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" +Ne 113 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA,_Port0,_Port2,_PROG_IF/NF_D7" +Ne 302 "/Non_volatile_memories/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -11638,35 +11798,35 @@ $PAD Sh "12" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -1613 1082 $EndPAD $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/Ethernet_Phy/ETH_RXER" +Ne 68 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/Ethernet_Phy/ETH_RXC" +Ne 64 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/Ethernet_Phy/ETH_RXDV" +Ne 53 "/Ethernet_Phy/ETH_RXDV" Po -1613 491 $EndPAD $PAD Sh "8" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -1613 295 $EndPAD $PAD @@ -11680,63 +11840,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" +Ne 65 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/Ethernet_Phy/ETH_RXD1" +Ne 66 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/Ethernet_Phy/ETH_RXD2" +Ne 52 "/Ethernet_Phy/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/Ethernet_Phy/ETH_RXD3" +Ne 67 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_MDC" +Ne 61 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/ETH_MDIO" +Ne 62 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" +Ne 63 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 51 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_CLK" +Ne 45 "/Ethernet_Phy/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -11750,7 +11910,7 @@ $PAD Sh "44" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -295 -1613 $EndPAD $PAD @@ -11771,56 +11931,56 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/Ethernet_Phy/MAG_TX+" +Ne 59 "/Ethernet_Phy/MAG_TX+" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/Ethernet_Phy/MAG_TX-" +Ne 60 "/Ethernet_Phy/MAG_TX-" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_A3.3V" +Ne 44 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 343 "N-000148" +Ne 349 "N-000132" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_INT" +Ne 48 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_LED0" +Ne 49 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_LED1" +Ne 50 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -11848,21 +12008,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_A1.8V" +Ne 43 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/Ethernet_Phy/MAG_RX-" +Ne 57 "/Ethernet_Phy/MAG_RX-" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/Ethernet_Phy/MAG_RX+" +Ne 56 "/Ethernet_Phy/MAG_RX+" Po 1613 -491 $EndPAD $PAD @@ -11876,91 +12036,91 @@ $PAD Sh "35" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1613 -1082 $EndPAD $PAD Sh "13" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_1.8V" +Ne 42 "/Ethernet_Phy/ETH_1.8V" Po -1082 1613 $EndPAD $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER" +Ne 55 "/Ethernet_Phy/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/Ethernet_Phy/ETH_TXC" +Ne 69 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN" +Ne 54 "/Ethernet_Phy/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" +Ne 70 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" +Ne 71 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/Ethernet_Phy/ETH_TXD2" +Ne 72 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/Ethernet_Phy/ETH_TXD3" +Ne 73 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA,_Port0,_Port2,_PROG_IF/ETH_COL" +Ne 46 "/Ethernet_Phy/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_CRS" +Ne 47 "/Ethernet_Phy/ETH_CRS" Po 688 1613 $EndPAD $PAD Sh "23" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 885 1613 $EndPAD $PAD @@ -11995,7 +12155,7 @@ $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -12017,35 +12177,35 @@ $PAD Sh "1" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 309 "/PSU/3.3V_EN" +Ne 314 "/PSU/3.3V_EN" Po -375 500 $EndPAD $PAD Sh "3" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 318 "/PSU/SW_3.3" +Ne 322 "/PSU/SW_3.3" Po 375 500 $EndPAD $PAD Sh "5" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 321 "/PSU/VFB3.3" +Ne 325 "/PSU/VFB3.3" Po -375 -500 $EndPAD $PAD Sh "2" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 0 500 $EndPAD $PAD Sh "4" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 325 "/PSU/VIN_DC-DC-3.3" +Ne 329 "/PSU/VIN_DC-DC-3.3" Po 375 -500 $EndPAD $SHAPE3D @@ -12073,35 +12233,35 @@ $PAD Sh "1" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 307 "/PSU/1.2V_EN" +Ne 312 "/PSU/1.2V_EN" Po -375 500 $EndPAD $PAD Sh "3" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 316 "/PSU/SW_1.2" +Ne 320 "/PSU/SW_1.2" Po 375 500 $EndPAD $PAD Sh "5" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 319 "/PSU/VFB1.2" +Ne 323 "/PSU/VFB1.2" Po -375 -500 $EndPAD $PAD Sh "2" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 0 500 $EndPAD $PAD Sh "4" R 200 300 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 323 "/PSU/VIN_DC-DC-1.2" +Ne 327 "/PSU/VIN_DC-DC-1.2" Po 375 -500 $EndPAD $SHAPE3D @@ -12135,7 +12295,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 321 "/PSU/VFB3.3" +Ne 325 "/PSU/VFB3.3" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12156,14 +12316,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 321 "/PSU/VFB3.3" +Ne 325 "/PSU/VFB3.3" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12191,7 +12351,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 321 "/PSU/VFB3.3" +Ne 325 "/PSU/VFB3.3" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12219,7 +12379,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12247,7 +12407,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12275,7 +12435,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 319 "/PSU/VFB1.2" +Ne 323 "/PSU/VFB1.2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12296,14 +12456,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 319 "/PSU/VFB1.2" +Ne 323 "/PSU/VFB1.2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12331,7 +12491,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 319 "/PSU/VFB1.2" +Ne 323 "/PSU/VFB1.2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12352,14 +12512,14 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 325 "/PSU/VIN_DC-DC-3.3" +Ne 329 "/PSU/VIN_DC-DC-3.3" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -12380,14 +12540,14 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 323 "/PSU/VIN_DC-DC-1.2" +Ne 327 "/PSU/VIN_DC-DC-1.2" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -12415,7 +12575,7 @@ $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -12443,7 +12603,7 @@ $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -12471,7 +12631,7 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 318 "/PSU/SW_3.3" +Ne 322 "/PSU/SW_3.3" Po 570 0 $EndPAD $EndMODULE 1210 @@ -12499,7 +12659,7 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 316 "/PSU/SW_1.2" +Ne 320 "/PSU/SW_1.2" Po 570 0 $EndPAD $EndMODULE 1210 @@ -12527,7 +12687,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 49 "/Ethernet_Phy/ETH_A3.3V" +Ne 44 "/Ethernet_Phy/ETH_A3.3V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -12555,7 +12715,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 358 "N-000376" +Ne 390 "N-000399" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12583,143 +12743,10 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 359 "N-000379" +Ne 391 "N-000402" Po 176 0 $EndPAD $EndMODULE 0402 -$MODULE pin_array_8x2 -Po 68988 14154 900 15 3FB38B89 4C716CF9 ~~ -Li pin_array_8x2 -Cd Double rangee de contacts 2 x 8 pins -Kw CONN -Sc 4C716CF9 -AR /4C716A4D/4C716CAB -Op 0 0 0 -T0 0 -1300 400 400 900 80 N V 21 N"J6" -T1 0 1300 400 400 900 80 N V 21 N"CONN_8X2" -DS -3900 900 -3900 -900 120 21 -DS -3900 -900 3900 -900 120 21 -DS 3900 -900 3900 900 120 21 -DS 3900 900 -3900 900 120 21 -$PAD -Sh "1" R 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 6 "/DBG_PRG/FPGA_TCK" -Po -3500 500 -$EndPAD -$PAD -Sh "2" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po -3500 -500 -$EndPAD -$PAD -Sh "3" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 127 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TMS" -Po -2500 500 -$EndPAD -$PAD -Sh "4" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po -2500 -500 -$EndPAD -$PAD -Sh "5" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 126 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TDO" -Po -1500 500 -$EndPAD -$PAD -Sh "6" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po -1500 -500 -$EndPAD -$PAD -Sh "7" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 7 "/DBG_PRG/FPGA_TDI" -Po -500 500 -$EndPAD -$PAD -Sh "8" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po -500 -500 -$EndPAD -$PAD -Sh "9" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po 500 500 -$EndPAD -$PAD -Sh "10" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po 500 -500 -$EndPAD -$PAD -Sh "11" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po 1500 500 -$EndPAD -$PAD -Sh "12" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po 1500 -500 -$EndPAD -$PAD -Sh "13" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po 2500 500 -$EndPAD -$PAD -Sh "14" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po 2500 -500 -$EndPAD -$PAD -Sh "15" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po 3500 500 -$EndPAD -$PAD -Sh "16" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po 3500 -500 -$EndPAD -$SHAPE3D -Na "pin_array/pins_array_8x2.wrl" -Sc 1.000000 1.000000 1.000000 -Of 0.000000 0.000000 0.000000 -Ro 0.000000 0.000000 0.000000 -$EndSHAPE3D -$EndMODULE pin_array_8x2 $MODULE MLF16 Po 57429 27272 0 0 4C71B372 4C71BB0D ~~ Li MLF16 @@ -12752,49 +12779,49 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 338 "/USB/USBD_SPD" +Ne 279 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD" Po -295 491 $EndPAD $PAD Sh "11" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 346 "N-000168" +Ne 355 "N-000155" Po -98 -491 $EndPAD $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 337 "/USB/USBD_RCV" +Ne 278 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV" Po -98 491 $EndPAD $PAD Sh "10" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 350 "N-000172" +Ne 352 "N-000152" Po 98 -491 $EndPAD $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 279 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VP" +Ne 281 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VP" Po 98 491 $EndPAD $PAD Sh "9" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 336 "/USB/USBD_OE_N" +Ne 344 "/USB/USBD_OE_N" Po 295 -491 $EndPAD $PAD Sh "4" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 278 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" +Ne 280 "/FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM" Po 295 491 $EndPAD $PAD @@ -12822,7 +12849,7 @@ $PAD Sh "6" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 491 98 $EndPAD $PAD @@ -12836,7 +12863,7 @@ $PAD Sh "7" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 491 -98 $EndPAD $PAD @@ -12886,35 +12913,35 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 332 "/USB/USBA_SPD" +Ne 276 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD" Po -295 491 $EndPAD $PAD Sh "11" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 348 "N-000170" +Ne 353 "N-000153" Po -98 -491 $EndPAD $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 276 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV" +Ne 340 "/USB/USBA_RCV" Po -98 491 $EndPAD $PAD Sh "10" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 349 "N-000171" +Ne 354 "N-000154" Po 98 -491 $EndPAD $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 333 "/USB/USBA_VP" +Ne 277 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP" Po 98 491 $EndPAD $PAD @@ -12928,7 +12955,7 @@ $PAD Sh "4" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 277 "/FPGA_Port_1,_Port_3_DDR,_USB/USBA_VM" +Ne 341 "/USB/USBA_VM" Po 295 491 $EndPAD $PAD @@ -12956,7 +12983,7 @@ $PAD Sh "6" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 491 98 $EndPAD $PAD @@ -12970,7 +12997,7 @@ $PAD Sh "7" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 491 -98 $EndPAD $PAD @@ -13012,7 +13039,7 @@ $PAD Sh "2" R 157 236 0 0 1350 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13040,7 +13067,7 @@ $PAD Sh "2" R 157 236 0 0 1350 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13068,7 +13095,7 @@ $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -13096,7 +13123,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13124,7 +13151,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13152,7 +13179,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13180,7 +13207,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13208,7 +13235,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13236,14 +13263,14 @@ $PAD Sh "2" R 157 236 0 0 3150 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE ZX62D-B-5P8 -Po 62598 16157 1800 15 4BAADC40 4C75F662 ~~ +Po 62598 16157 1800 15 4BAADC40 4CB9D6F7 ~~ Li ZX62D-B-5P8 -Sc 4C75F662 +Sc 4CB9D6F7 AR /4C5F1EDC/4C75F027 Op 0 0 0 T0 446 -852 157 157 1800 20 N V 21 N"J7" @@ -13262,35 +13289,35 @@ $PAD Sh "1" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 347 "N-000169" +Ne 360 "N-000162" Po 0 0 $EndPAD $PAD Sh "2" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 335 "/USB/USBD_D-" +Ne 343 "/USB/USBD_D-" Po 310 0 $EndPAD $PAD Sh "3" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 334 "/USB/USBD_D+" +Ne 342 "/USB/USBD_D+" Po 630 0 $EndPAD $PAD Sh "4" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 351 "N-000174" +Ne 356 "N-000156" Po 940 0 $EndPAD $PAD Sh "5" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 351 "N-000174" +Ne 356 "N-000156" Po 1260 0 $EndPAD $PAD @@ -13311,28 +13338,28 @@ $PAD Sh "8" R 860 900 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 339 "/USB/USB_CASE_DEV" +Ne 345 "/USB/USB_CASE_DEV" Po -1070 140 $EndPAD $PAD Sh "6" R 860 900 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 339 "/USB/USB_CASE_DEV" +Ne 345 "/USB/USB_CASE_DEV" Po 2320 2310 $EndPAD $PAD Sh "7" R 860 900 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 339 "/USB/USB_CASE_DEV" +Ne 345 "/USB/USB_CASE_DEV" Po -1070 2310 $EndPAD $PAD Sh "9" R 860 900 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 339 "/USB/USB_CASE_DEV" +Ne 345 "/USB/USB_CASE_DEV" Po 2320 140 $EndPAD $EndMODULE ZX62D-B-5P8 @@ -13353,14 +13380,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 315 "/PSU/Iout_1.2" +Ne 319 "/PSU/Iout_1.2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13381,14 +13408,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 328 "/PSU/lout_3.3" +Ne 332 "/PSU/lout_3.3" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13409,7 +13436,7 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 323 "/PSU/VIN_DC-DC-1.2" +Ne 327 "/PSU/VIN_DC-DC-1.2" Po -570 0 $EndPAD $PAD @@ -13437,7 +13464,7 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 325 "/PSU/VIN_DC-DC-3.3" +Ne 329 "/PSU/VIN_DC-DC-3.3" Po -570 0 $EndPAD $PAD @@ -13473,7 +13500,7 @@ $PAD Sh "6" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 323 "/PSU/VIN_DC-DC-1.2" +Ne 327 "/PSU/VIN_DC-DC-1.2" Po -196 153 $EndPAD $PAD @@ -13487,14 +13514,14 @@ $PAD Sh "5" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 0 153 $EndPAD $PAD Sh "3" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 315 "/PSU/Iout_1.2" +Ne 319 "/PSU/Iout_1.2" Po 196 -153 $EndPAD $PAD @@ -13530,7 +13557,7 @@ $PAD Sh "6" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 325 "/PSU/VIN_DC-DC-3.3" +Ne 329 "/PSU/VIN_DC-DC-3.3" Po -196 153 $EndPAD $PAD @@ -13544,14 +13571,14 @@ $PAD Sh "5" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 0 153 $EndPAD $PAD Sh "3" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 328 "/PSU/lout_3.3" +Ne 332 "/PSU/lout_3.3" Po 196 -153 $EndPAD $PAD @@ -13580,7 +13607,7 @@ $PAD Sh "6" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 326 "/PSU/VIN_DC-DC-5.0" +Ne 330 "/PSU/VIN_DC-DC-5.0" Po -375 -500 $EndPAD $PAD @@ -13594,28 +13621,28 @@ $PAD Sh "4" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 310 "/PSU/5V_EN" +Ne 315 "/PSU/5V_EN" Po 375 -500 $EndPAD $PAD Sh "3" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 322 "/PSU/VFB5.0" +Ne 326 "/PSU/VFB5.0" Po 375 500 $EndPAD $PAD Sh "2" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 0 500 $EndPAD $PAD Sh "1" R 276 394 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 355 "N-000184" +Ne 361 "N-000168" Po -375 500 $EndPAD $SHAPE3D @@ -13642,14 +13669,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 310 "/PSU/5V_EN" +Ne 315 "/PSU/5V_EN" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 326 "/PSU/VIN_DC-DC-5.0" +Ne 330 "/PSU/VIN_DC-DC-5.0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13677,7 +13704,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 322 "/PSU/VFB5.0" +Ne 326 "/PSU/VFB5.0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13698,14 +13725,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 322 "/PSU/VFB5.0" +Ne 326 "/PSU/VFB5.0" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13733,7 +13760,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 322 "/PSU/VFB5.0" +Ne 326 "/PSU/VFB5.0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13761,7 +13788,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13782,14 +13809,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 329 "/PSU/lout_5.0" +Ne 333 "/PSU/lout_5.0" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13810,14 +13837,14 @@ $PAD Sh "1" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 326 "/PSU/VIN_DC-DC-5.0" +Ne 330 "/PSU/VIN_DC-DC-5.0" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 373 0 $EndPAD $EndMODULE 0805 @@ -13845,7 +13872,7 @@ $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -13866,7 +13893,7 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 326 "/PSU/VIN_DC-DC-5.0" +Ne 330 "/PSU/VIN_DC-DC-5.0" Po -570 0 $EndPAD $PAD @@ -13894,14 +13921,14 @@ $PAD Sh "1" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 355 "N-000184" +Ne 361 "N-000168" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 326 "/PSU/VIN_DC-DC-5.0" +Ne 330 "/PSU/VIN_DC-DC-5.0" Po 570 0 $EndPAD $EndMODULE 1210 @@ -13930,7 +13957,7 @@ $PAD Sh "6" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 326 "/PSU/VIN_DC-DC-5.0" +Ne 330 "/PSU/VIN_DC-DC-5.0" Po -196 153 $EndPAD $PAD @@ -13944,14 +13971,14 @@ $PAD Sh "5" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 0 153 $EndPAD $PAD Sh "3" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 329 "/PSU/lout_5.0" +Ne 333 "/PSU/lout_5.0" Po 196 -153 $EndPAD $PAD @@ -13986,7 +14013,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 320 "/PSU/VFB2.5" +Ne 324 "/PSU/VFB2.5" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14007,14 +14034,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 320 "/PSU/VFB2.5" +Ne 324 "/PSU/VFB2.5" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14035,14 +14062,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 308 "/PSU/2.5V_EN" +Ne 313 "/PSU/2.5V_EN" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14063,14 +14090,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 357 "N-000199" +Ne 363 "N-000180" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 356 "N-000194" +Ne 362 "N-000175" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14098,7 +14125,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14126,7 +14153,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 320 "/PSU/VFB2.5" +Ne 324 "/PSU/VFB2.5" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14147,14 +14174,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 356 "N-000194" +Ne 362 "N-000175" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14182,7 +14209,7 @@ $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -14203,14 +14230,14 @@ $PAD Sh "1" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 324 "/PSU/VIN_DC-DC-2.5" +Ne 328 "/PSU/VIN_DC-DC-2.5" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -14238,7 +14265,7 @@ $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 317 "/PSU/SW_2.5" +Ne 321 "/PSU/SW_2.5" Po 570 0 $EndPAD $EndMODULE 1210 @@ -14259,14 +14286,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 327 "/PSU/lout_2.5" +Ne 331 "/PSU/lout_2.5" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14287,7 +14314,7 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 324 "/PSU/VIN_DC-DC-2.5" +Ne 328 "/PSU/VIN_DC-DC-2.5" Po -570 0 $EndPAD $PAD @@ -14323,7 +14350,7 @@ $PAD Sh "6" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 324 "/PSU/VIN_DC-DC-2.5" +Ne 328 "/PSU/VIN_DC-DC-2.5" Po -196 153 $EndPAD $PAD @@ -14337,14 +14364,14 @@ $PAD Sh "5" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 0 153 $EndPAD $PAD Sh "3" R 118 204 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 327 "/PSU/lout_2.5" +Ne 331 "/PSU/lout_2.5" Po 196 -153 $EndPAD $PAD @@ -14379,7 +14406,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 334 "/USB/USBD_D+" +Ne 342 "/USB/USBD_D+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14400,14 +14427,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 335 "/USB/USBD_D-" +Ne 343 "/USB/USBD_D-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14428,14 +14455,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 334 "/USB/USBD_D+" +Ne 342 "/USB/USBD_D+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14456,14 +14483,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 331 "/USB/USBA_D-" +Ne 339 "/USB/USBA_D-" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 349 "N-000171" +Ne 354 "N-000154" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14484,14 +14511,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 330 "/USB/USBA_D+" +Ne 338 "/USB/USBA_D+" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 348 "N-000170" +Ne 353 "N-000153" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14512,14 +14539,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 335 "/USB/USBD_D-" +Ne 343 "/USB/USBD_D-" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 350 "N-000172" +Ne 352 "N-000152" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14540,14 +14567,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 334 "/USB/USBD_D+" +Ne 342 "/USB/USBD_D+" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 346 "N-000168" +Ne 355 "N-000155" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14575,7 +14602,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 330 "/USB/USBA_D+" +Ne 338 "/USB/USBA_D+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14596,14 +14623,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 330 "/USB/USBA_D+" +Ne 338 "/USB/USBA_D+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14624,14 +14651,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 331 "/USB/USBA_D-" +Ne 339 "/USB/USBA_D-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14652,14 +14679,14 @@ $PAD Sh "1" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 339 "/USB/USB_CASE_DEV" +Ne 345 "/USB/USB_CASE_DEV" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -14680,14 +14707,14 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 340 "/USB/USB_CASE_HOST" +Ne 346 "/USB/USB_CASE_HOST" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -14708,14 +14735,14 @@ $PAD Sh "1" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 339 "/USB/USB_CASE_DEV" +Ne 345 "/USB/USB_CASE_DEV" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -14736,14 +14763,14 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 340 "/USB/USB_CASE_HOST" +Ne 346 "/USB/USB_CASE_HOST" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -14764,14 +14791,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 307 "/PSU/1.2V_EN" +Ne 312 "/PSU/1.2V_EN" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 323 "/PSU/VIN_DC-DC-1.2" +Ne 327 "/PSU/VIN_DC-DC-1.2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14792,7 +14819,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 313 "/PSU/AVR_RST" +Ne 318 "/PSU/AVR_RST" Po -176 0 $EndPAD $PAD @@ -14820,14 +14847,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 309 "/PSU/3.3V_EN" +Ne 314 "/PSU/3.3V_EN" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 325 "/PSU/VIN_DC-DC-3.3" +Ne 329 "/PSU/VIN_DC-DC-3.3" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14855,66 +14882,10 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 -$MODULE PIN_ARRAY_5x1 -Po 71236 15654 900 15 45976D86 4C811FE5 ~~ -Li PIN_ARRAY_5x1 -Cd Double rangee de contacts 2 x 5 pins -Kw CONN -Sc 4C811FE5 -AR /4C69ED5F/4C7FD562 -Op 0 0 0 -T0 0 -1000 400 400 900 80 N V 21 N"P1" -T1 0 1000 400 400 900 80 N I 21 N"AVR/PROG" -DS -2500 -500 -2500 500 120 21 -DS 2500 500 2500 -500 120 21 -DS -2500 -500 2500 -500 120 21 -DS 2500 500 -2500 500 120 21 -$PAD -Sh "1" R 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 341 "GND" -Po -2000 0 -$EndPAD -$PAD -Sh "2" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 314 "/PSU/AVR_SCK" -Po -1000 0 -$EndPAD -$PAD -Sh "3" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 311 "/PSU/AVR_MISO" -Po 0 0 -$EndPAD -$PAD -Sh "4" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 312 "/PSU/AVR_MOSI" -Po 1000 0 -$EndPAD -$PAD -Sh "5" C 600 600 0 0 900 -Dr 400 0 0 -At STD N 00E0FFFF -Ne 0 "" -Po 2000 0 -$EndPAD -$SHAPE3D -Na "pin_array/pins_array_5x1.wrl" -Sc 1.000000 1.000000 1.000000 -Of 0.000000 0.000000 0.000000 -Ro 0.000000 0.000000 0.000000 -$EndSHAPE3D -$EndMODULE PIN_ARRAY_5x1 $MODULE 1206 Po 45803 19031 2700 15 4C5FF890 4C8934E6 ~~ Li 1206 @@ -14932,14 +14903,14 @@ $PAD Sh "1" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/Ethernet_Phy/MAG_SHIELD" +Ne 58 "/Ethernet_Phy/MAG_SHIELD" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -14960,14 +14931,14 @@ $PAD Sh "1" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/Ethernet_Phy/MAG_SHIELD" +Ne 58 "/Ethernet_Phy/MAG_SHIELD" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -14988,14 +14959,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 284 "/Image_Sensor/+2.8_VDDPLL" +Ne 337 "/Snesor_PSU/+2.8_VDDPLL" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 362 "N-000424" +Ne 394 "N-000447" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15016,14 +14987,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 365 "N-000427" +Ne 397 "N-000450" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15044,14 +15015,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 367 "N-000429" +Ne 399 "N-000452" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15072,14 +15043,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 364 "N-000426" +Ne 396 "N-000449" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15100,14 +15071,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 280 "/Image_Sensor/+1.8_VDD" +Ne 282 "/Image_Sensor/+1.8_VDD" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 369 "N-000431" +Ne 401 "N-000454" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15128,14 +15099,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 282 "/Image_Sensor/+2.8_VAAPIX" +Ne 335 "/Snesor_PSU/+2.8_VAAPIX" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 373 "N-000435" +Ne 405 "N-000458" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15156,14 +15127,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 281 "/Image_Sensor/+2.8_VAA" +Ne 334 "/Snesor_PSU/+2.8_VAA" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 374 "N-000436" +Ne 406 "N-000459" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15184,14 +15155,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 368 "N-000430" +Ne 400 "N-000453" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15212,14 +15183,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 363 "N-000425" +Ne 395 "N-000448" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15240,14 +15211,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 371 "N-000433" +Ne 403 "N-000456" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15268,14 +15239,14 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 284 "/Image_Sensor/+2.8_VDDPLL" +Ne 337 "/Snesor_PSU/+2.8_VDDPLL" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -15296,14 +15267,14 @@ $PAD Sh "1" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -15324,14 +15295,14 @@ $PAD Sh "1" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 361 "N-000423" +Ne 393 "N-000446" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -15352,14 +15323,14 @@ $PAD Sh "1" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 360 "N-000422" +Ne 392 "N-000445" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -15380,14 +15351,14 @@ $PAD Sh "1" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 280 "/Image_Sensor/+1.8_VDD" +Ne 282 "/Image_Sensor/+1.8_VDD" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -15408,14 +15379,14 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 282 "/Image_Sensor/+2.8_VAAPIX" +Ne 335 "/Snesor_PSU/+2.8_VAAPIX" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -15436,14 +15407,14 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 281 "/Image_Sensor/+2.8_VAA" +Ne 334 "/Snesor_PSU/+2.8_VAA" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -15464,14 +15435,14 @@ $PAD Sh "1" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 366 "N-000428" +Ne 398 "N-000451" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -15492,14 +15463,14 @@ $PAD Sh "1" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 372 "N-000434" +Ne 404 "N-000457" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -15520,14 +15491,14 @@ $PAD Sh "1" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 370 "N-000432" +Ne 402 "N-000455" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -15549,42 +15520,42 @@ $PAD Sh "6" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 284 "/Image_Sensor/+2.8_VDDPLL" +Ne 337 "/Snesor_PSU/+2.8_VDDPLL" Po -375 -500 $EndPAD $PAD Sh "5" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 362 "N-000424" +Ne 394 "N-000447" Po 0 -500 $EndPAD $PAD Sh "4" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 367 "N-000429" +Ne 399 "N-000452" Po 375 -500 $EndPAD $PAD Sh "3" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 361 "N-000423" +Ne 393 "N-000446" Po 375 500 $EndPAD $PAD Sh "2" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 0 500 $EndPAD $PAD Sh "1" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 361 "N-000423" +Ne 393 "N-000446" Po -375 500 $EndPAD $SHAPE3D @@ -15612,42 +15583,42 @@ $PAD Sh "6" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -375 -500 $EndPAD $PAD Sh "5" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 365 "N-000427" +Ne 397 "N-000450" Po 0 -500 $EndPAD $PAD Sh "4" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 364 "N-000426" +Ne 396 "N-000449" Po 375 -500 $EndPAD $PAD Sh "3" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 360 "N-000422" +Ne 392 "N-000445" Po 375 500 $EndPAD $PAD Sh "2" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 0 500 $EndPAD $PAD Sh "1" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 360 "N-000422" +Ne 392 "N-000445" Po -375 500 $EndPAD $SHAPE3D @@ -15675,42 +15646,42 @@ $PAD Sh "6" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 280 "/Image_Sensor/+1.8_VDD" +Ne 282 "/Image_Sensor/+1.8_VDD" Po -375 -500 $EndPAD $PAD Sh "5" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 369 "N-000431" +Ne 401 "N-000454" Po 0 -500 $EndPAD $PAD Sh "4" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 368 "N-000430" +Ne 400 "N-000453" Po 375 -500 $EndPAD $PAD Sh "3" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 366 "N-000428" +Ne 398 "N-000451" Po 375 500 $EndPAD $PAD Sh "2" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 0 500 $EndPAD $PAD Sh "1" R 276 394 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 366 "N-000428" +Ne 398 "N-000451" Po -375 500 $EndPAD $SHAPE3D @@ -15738,42 +15709,42 @@ $PAD Sh "6" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 282 "/Image_Sensor/+2.8_VAAPIX" +Ne 335 "/Snesor_PSU/+2.8_VAAPIX" Po -375 -500 $EndPAD $PAD Sh "5" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 373 "N-000435" +Ne 405 "N-000458" Po 0 -500 $EndPAD $PAD Sh "4" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 363 "N-000425" +Ne 395 "N-000448" Po 375 -500 $EndPAD $PAD Sh "3" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 372 "N-000434" +Ne 404 "N-000457" Po 375 500 $EndPAD $PAD Sh "2" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 0 500 $EndPAD $PAD Sh "1" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 372 "N-000434" +Ne 404 "N-000457" Po -375 500 $EndPAD $SHAPE3D @@ -15801,42 +15772,42 @@ $PAD Sh "6" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 281 "/Image_Sensor/+2.8_VAA" +Ne 334 "/Snesor_PSU/+2.8_VAA" Po -375 -500 $EndPAD $PAD Sh "5" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 374 "N-000436" +Ne 406 "N-000459" Po 0 -500 $EndPAD $PAD Sh "4" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 371 "N-000433" +Ne 403 "N-000456" Po 375 -500 $EndPAD $PAD Sh "3" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 370 "N-000432" +Ne 402 "N-000455" Po 375 500 $EndPAD $PAD Sh "2" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 0 500 $EndPAD $PAD Sh "1" R 276 394 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 370 "N-000432" +Ne 402 "N-000455" Po -375 500 $EndPAD $SHAPE3D @@ -15863,14 +15834,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 362 "N-000424" +Ne 394 "N-000447" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15891,14 +15862,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 284 "/Image_Sensor/+2.8_VDDPLL" +Ne 337 "/Snesor_PSU/+2.8_VDDPLL" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 362 "N-000424" +Ne 394 "N-000447" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15919,14 +15890,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 365 "N-000427" +Ne 397 "N-000450" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15947,14 +15918,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 365 "N-000427" +Ne 397 "N-000450" Po 176 0 $EndPAD $EndMODULE 0402 @@ -15975,14 +15946,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 369 "N-000431" +Ne 401 "N-000454" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16003,14 +15974,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 280 "/Image_Sensor/+1.8_VDD" +Ne 282 "/Image_Sensor/+1.8_VDD" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 369 "N-000431" +Ne 401 "N-000454" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16031,14 +16002,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 373 "N-000435" +Ne 405 "N-000458" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16059,14 +16030,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 282 "/Image_Sensor/+2.8_VAAPIX" +Ne 335 "/Snesor_PSU/+2.8_VAAPIX" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 373 "N-000435" +Ne 405 "N-000458" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16087,14 +16058,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 374 "N-000436" +Ne 406 "N-000459" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16115,14 +16086,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 281 "/Image_Sensor/+2.8_VAA" +Ne 334 "/Snesor_PSU/+2.8_VAA" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 374 "N-000436" +Ne 406 "N-000459" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16143,14 +16114,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16171,14 +16142,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16199,14 +16170,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16227,14 +16198,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16255,14 +16226,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 280 "/Image_Sensor/+1.8_VDD" +Ne 282 "/Image_Sensor/+1.8_VDD" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16283,14 +16254,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 280 "/Image_Sensor/+1.8_VDD" +Ne 282 "/Image_Sensor/+1.8_VDD" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16311,14 +16282,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 280 "/Image_Sensor/+1.8_VDD" +Ne 282 "/Image_Sensor/+1.8_VDD" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16339,14 +16310,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 281 "/Image_Sensor/+2.8_VAA" +Ne 334 "/Snesor_PSU/+2.8_VAA" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16367,14 +16338,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 281 "/Image_Sensor/+2.8_VAA" +Ne 334 "/Snesor_PSU/+2.8_VAA" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16395,14 +16366,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 282 "/Image_Sensor/+2.8_VAAPIX" +Ne 335 "/Snesor_PSU/+2.8_VAAPIX" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16423,14 +16394,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 284 "/Image_Sensor/+2.8_VDDPLL" +Ne 337 "/Snesor_PSU/+2.8_VDDPLL" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 341 "GND" +Ne 347 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -16451,14 +16422,14 @@ $PAD Sh "1" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -16479,14 +16450,14 @@ $PAD Sh "1" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 280 "/Image_Sensor/+1.8_VDD" +Ne 282 "/Image_Sensor/+1.8_VDD" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -16507,14 +16478,14 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 281 "/Image_Sensor/+2.8_VAA" +Ne 334 "/Snesor_PSU/+2.8_VAA" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -16535,14 +16506,14 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 282 "/Image_Sensor/+2.8_VAAPIX" +Ne 335 "/Snesor_PSU/+2.8_VAAPIX" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -16563,14 +16534,14 @@ $PAD Sh "1" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 284 "/Image_Sensor/+2.8_VDDPLL" +Ne 337 "/Snesor_PSU/+2.8_VDDPLL" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -16593,7 +16564,7 @@ $PAD Sh "19" R 196 303 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 280 "/Image_Sensor/+1.8_VDD" +Ne 282 "/Image_Sensor/+1.8_VDD" Po -1515 1816 $EndPAD $PAD @@ -16614,7 +16585,7 @@ $PAD Sh "22" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY" +Ne 296 "/Image_Sensor/IS_STANDBY" Po -688 1771 $EndPAD $PAD @@ -16628,49 +16599,49 @@ $PAD Sh "24" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 292 "/Image_Sensor/IS_I2C_ADDR" +Ne 291 "/Image_Sensor/IS_I2C_ADDR" Po -137 1771 $EndPAD $PAD Sh "25" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA,_Port0,_Port2,_PROG_IF/IS_TEST" +Ne 297 "/Image_Sensor/IS_TEST" Po 137 1771 $EndPAD $PAD Sh "26" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" +Ne 104 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH" Po 413 1771 $EndPAD $PAD Sh "27" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA,_Port0,_Port2,_PROG_IF/IS_TRIGGER" +Ne 107 "/FPGA,_Port0,_Port2,_PROG_IF/IS_TRIGGER" Po 688 1771 $EndPAD $PAD Sh "28" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME" +Ne 290 "/Image_Sensor/IS_FRAME" Po 964 1771 $EndPAD $PAD Sh "29" R 196 393 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA,_Port0,_Port2,_PROG_IF/IS_LINE" +Ne 292 "/Image_Sensor/IS_LINE" Po 1240 1771 $EndPAD $PAD Sh "30" R 196 270 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1515 1831 $EndPAD $PAD @@ -16698,49 +16669,49 @@ $PAD Sh "34" R 196 393 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 281 "/Image_Sensor/+2.8_VAA" +Ne 334 "/Snesor_PSU/+2.8_VAA" Po 1771 688 $EndPAD $PAD Sh "35" R 196 393 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1771 413 $EndPAD $PAD Sh "36" R 196 393 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 281 "/Image_Sensor/+2.8_VAA" +Ne 334 "/Snesor_PSU/+2.8_VAA" Po 1771 137 $EndPAD $PAD Sh "37" R 196 393 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 282 "/Image_Sensor/+2.8_VAAPIX" +Ne 335 "/Snesor_PSU/+2.8_VAAPIX" Po 1771 -137 $EndPAD $PAD Sh "38" R 196 393 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 282 "/Image_Sensor/+2.8_VAAPIX" +Ne 335 "/Snesor_PSU/+2.8_VAAPIX" Po 1771 -413 $EndPAD $PAD Sh "39" R 196 393 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1771 -688 $EndPAD $PAD Sh "40" R 196 393 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 281 "/Image_Sensor/+2.8_VAA" +Ne 334 "/Snesor_PSU/+2.8_VAA" Po 1771 -964 $EndPAD $PAD @@ -16768,98 +16739,98 @@ $PAD Sh "44" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po 1240 -1771 $EndPAD $PAD Sh "45" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 285 "/Image_Sensor/IS_DOUT0" +Ne 98 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0" Po 964 -1771 $EndPAD $PAD Sh "46" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 286 "/Image_Sensor/IS_DOUT1" +Ne 283 "/Image_Sensor/IS_DOUT1" Po 688 -1771 $EndPAD $PAD Sh "47" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 287 "/Image_Sensor/IS_DOUT2" +Ne 284 "/Image_Sensor/IS_DOUT2" Po 413 -1771 $EndPAD $PAD Sh "48" R 196 592 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3" +Ne 285 "/Image_Sensor/IS_DOUT3" Po 137 -1673 $EndPAD $PAD Sh "1" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 288 "/Image_Sensor/IS_DOUT4" +Ne 101 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT4" Po -137 -1771 $EndPAD $PAD Sh "2" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5" +Ne 286 "/Image_Sensor/IS_DOUT5" Po -413 -1771 $EndPAD $PAD Sh "3" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 289 "/Image_Sensor/IS_DOUT6" +Ne 287 "/Image_Sensor/IS_DOUT6" Po -688 -1771 $EndPAD $PAD Sh "4" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 284 "/Image_Sensor/+2.8_VDDPLL" +Ne 337 "/Snesor_PSU/+2.8_VDDPLL" Po -964 -1771 $EndPAD $PAD Sh "5" R 196 393 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK" +Ne 103 "/FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK" Po -1240 -1771 $EndPAD $PAD Sh "6" R 196 270 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 341 "GND" +Ne 347 "GND" Po -1515 -1831 $EndPAD $PAD Sh "7" R 196 303 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 290 "/Image_Sensor/IS_DOUT7" +Ne 288 "/Image_Sensor/IS_DOUT7" Po -1816 -1515 $EndPAD $PAD Sh "8" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8" +Ne 289 "/Image_Sensor/IS_DOUT8" Po -1771 -1240 $EndPAD $PAD Sh "9" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 291 "/Image_Sensor/IS_DOUT9" +Ne 102 "/FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9" Po -1771 -964 $EndPAD $PAD @@ -16880,49 +16851,49 @@ $PAD Sh "12" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -1771 -137 $EndPAD $PAD Sh "13" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 294 "/Image_Sensor/IS_PIXEL" +Ne 105 "/FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL" Po -1771 137 $EndPAD $PAD Sh "14" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 280 "/Image_Sensor/+1.8_VDD" +Ne 282 "/Image_Sensor/+1.8_VDD" Po -1771 413 $EndPAD $PAD Sh "15" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" +Ne 106 "/FPGA,_Port0,_Port2,_PROG_IF/IS_SCL" Po -1771 688 $EndPAD $PAD Sh "16" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 296 "/Image_Sensor/IS_SDA" +Ne 295 "/Image_Sensor/IS_SDA" Po -1771 964 $EndPAD $PAD Sh "17" R 196 393 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 295 "/Image_Sensor/IS_RESET_N" +Ne 294 "/Image_Sensor/IS_RESET_N" Po -1771 1240 $EndPAD $PAD Sh "18" R 196 303 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 283 "/Image_Sensor/+2.8_VDDIO" +Ne 336 "/Snesor_PSU/+2.8_VDDIO" Po -1816 1515 $EndPAD $EndMODULE iLCC-48 @@ -16982,283 +16953,1248 @@ $PAD Sh "1" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/FPGA_GPIOS/FPGA_BANK0_IO_8" +Ne 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8" Po 9499 -1141 $EndPAD $PAD Sh "3" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 133 "/FPGA_GPIOS/FPGA_BANK0_IO_16" +Ne 125 "/FPGA_GPIOS/FPGA_BANK0_IO_16" Po 8499 -1141 $EndPAD $PAD Sh "5" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 130 "/FPGA_GPIOS/FPGA_BANK0_IO_0" +Ne 74 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_0" Po 7499 -1141 $EndPAD $PAD Sh "7" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 80 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_10" +Ne 122 "/FPGA_GPIOS/FPGA_BANK0_IO_10" Po 6499 -1141 $EndPAD $PAD Sh "9" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 131 "/FPGA_GPIOS/FPGA_BANK0_IO_11" +Ne 76 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11" Po 5499 -1141 $EndPAD $PAD Sh "11" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 145 "/FPGA_GPIOS/FPGA_BANK0_IO_5" +Ne 132 "/FPGA_GPIOS/FPGA_BANK0_IO_5" Po 4499 -1141 $EndPAD $PAD Sh "13" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 83 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" +Ne 78 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17" Po 3499 -1141 $EndPAD $PAD Sh "15" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 136 "/FPGA_GPIOS/FPGA_BANK0_IO_20" +Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20" Po 2499 -1141 $EndPAD $PAD Sh "17" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 138 "/FPGA_GPIOS/FPGA_BANK0_IO_28" +Ne 126 "/FPGA_GPIOS/FPGA_BANK0_IO_28" Po 1499 -1141 $EndPAD $PAD Sh "19" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 85 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" +Ne 83 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22" Po 499 -1141 $EndPAD $PAD Sh "21" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 87 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_27" +Ne 86 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_27" Po -499 -1141 $EndPAD $PAD Sh "23" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/FPGA_GPIOS/FPGA_BANK0_IO_39" +Ne 91 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39" Po -1499 -1141 $EndPAD $PAD Sh "25" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 135 "/FPGA_GPIOS/FPGA_BANK0_IO_2" +Ne 80 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_2" Po -2499 -1141 $EndPAD $PAD Sh "27" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 148 "/FPGA_GPIOS/FPGA_BANK0_IO_7" +Ne 137 "/FPGA_GPIOS/FPGA_BANK0_IO_7" Po -3499 -1141 $EndPAD $PAD Sh "29" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 81 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12" +Ne 123 "/FPGA_GPIOS/FPGA_BANK0_IO_12" Po -4499 -1141 $EndPAD $PAD Sh "31" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" +Ne 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44" Po -5499 -1141 $EndPAD $PAD Sh "33" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" +Ne 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47" Po -6499 -1141 $EndPAD $PAD Sh "35" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/FPGA_GPIOS/FPGA_BANK0_IO_45" +Ne 129 "/FPGA_GPIOS/FPGA_BANK0_IO_45" Po -7499 -1141 $EndPAD $PAD Sh "37" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 146 "/FPGA_GPIOS/FPGA_BANK0_IO_52" +Ne 134 "/FPGA_GPIOS/FPGA_BANK0_IO_52" Po -8499 -1141 $EndPAD $PAD Sh "39" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56" +Ne 135 "/FPGA_GPIOS/FPGA_BANK0_IO_56" Po -9499 -1141 $EndPAD $PAD Sh "2" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 79 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" +Ne 75 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1" Po 9499 1141 $EndPAD $PAD Sh "4" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 98 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" +Ne 97 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9" Po 8499 1141 $EndPAD $PAD Sh "6" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 82 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" +Ne 77 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14" Po 7499 1141 $EndPAD $PAD Sh "8" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 132 "/FPGA_GPIOS/FPGA_BANK0_IO_15" +Ne 124 "/FPGA_GPIOS/FPGA_BANK0_IO_15" Po 6499 1141 $EndPAD $PAD Sh "10" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 140 "/FPGA_GPIOS/FPGA_BANK0_IO_3" +Ne 127 "/FPGA_GPIOS/FPGA_BANK0_IO_3" Po 5499 1141 $EndPAD $PAD Sh "12" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 134 "/FPGA_GPIOS/FPGA_BANK0_IO_18" +Ne 79 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_18" Po 4499 1141 $EndPAD $PAD Sh "14" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" +Ne 82 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21" Po 3499 1141 $EndPAD $PAD Sh "16" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 86 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24" +Ne 84 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24" Po 2499 1141 $EndPAD $PAD Sh "18" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 139 "/FPGA_GPIOS/FPGA_BANK0_IO_29" +Ne 87 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29" Po 1499 1141 $EndPAD $PAD Sh "20" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 141 "/FPGA_GPIOS/FPGA_BANK0_IO_30" +Ne 128 "/FPGA_GPIOS/FPGA_BANK0_IO_30" Po 499 1141 $EndPAD $PAD Sh "22" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 137 "/FPGA_GPIOS/FPGA_BANK0_IO_25" +Ne 85 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_25" Po -499 1141 $EndPAD $PAD Sh "24" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 88 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" +Ne 89 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33" Po -1499 1141 $EndPAD $PAD Sh "26" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/FPGA_GPIOS/FPGA_BANK0_IO_32" +Ne 88 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32" Po -2499 1141 $EndPAD $PAD Sh "28" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 147 "/FPGA_GPIOS/FPGA_BANK0_IO_6" +Ne 136 "/FPGA_GPIOS/FPGA_BANK0_IO_6" Po -3499 1141 $EndPAD $PAD Sh "30" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 89 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" +Ne 90 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36" Po -4499 1141 $EndPAD $PAD Sh "32" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 90 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" +Ne 92 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40" Po -5499 1141 $EndPAD $PAD Sh "34" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 91 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" +Ne 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43" Po -6499 1141 $EndPAD $PAD Sh "36" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 93 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46" +Ne 130 "/FPGA_GPIOS/FPGA_BANK0_IO_46" Po -7499 1141 $EndPAD $PAD Sh "38" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 96 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50" +Ne 133 "/FPGA_GPIOS/FPGA_BANK0_IO_50" Po -8499 1141 $EndPAD $PAD Sh "40" R 511 1260 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48" +Ne 131 "/FPGA_GPIOS/FPGA_BANK0_IO_48" Po -9499 1141 $EndPAD $EndMODULE header20x2_smd_100mil +$MODULE 0402 +Po 40008 47594 0 15 4C5FF890 4CB9E51A ~~ +Li 0402 +Sc 4CB9E51A +AR /4C716A4D/4CB9C8AC +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R76" +T1 0 150 200 200 0 40 N I 25 N"10K" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 389 "N-000237" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 36728 47461 0 15 4C5FF890 4CB9E51C ~~ +Li 0402 +Sc 4CB9E51C +AR /4C716A4D/4CB9C8A1 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R75" +T1 0 150 200 200 0 40 N I 25 N"10K" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 384 "N-000232" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 38760 44669 1800 15 4C5FF890 4CB9E51E ~~ +Li 0402 +Sc 4CB9E51E +AR /4C716A4D/4CB9C9A3 +Op 0 0 0 +At SMD +T0 0 -150 200 200 1800 40 N V 25 N"R74" +T1 0 150 200 200 1800 40 N I 25 N"470" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/DBG_PRG/VCC_USB" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 383 "N-000231" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 36799 45744 1800 15 4C5FF890 4CB9E520 ~~ +Li 0402 +Sc 4CB9E520 +AR /4C716A4D/4CB9C8E1 +Op 0 0 0 +At SMD +T0 0 -150 200 200 1800 40 N V 25 N"R73" +T1 0 150 200 200 1800 40 N I 25 N"10K" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 385 "N-000233" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/DBG_PRG/VCC_USB" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 38083 45776 0 15 4C5FF890 4CB9E522 ~~ +Li 0402 +Sc 4CB9E522 +AR /4C716A4D/4CB9C8D7 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R72" +T1 0 150 200 200 0 40 N I 25 N"1.5K" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 386 "N-000234" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 388 "N-000236" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 38193 46366 0 15 4C5FF890 4CB9E524 ~~ +Li 0402 +Sc 4CB9E524 +AR /4C716A4D/4CB9C8F8 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R71" +T1 0 150 200 200 0 40 N I 25 N"27" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 388 "N-000236" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 12 "/DBG_PRG/FTDI_USB_DP" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 38173 46945 0 15 4C5FF890 4CB9E526 ~~ +Li 0402 +Sc 4CB9E526 +AR /4C716A4D/4CB9C8F1 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R70" +T1 0 150 200 200 0 40 N I 25 N"27" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 387 "N-000235" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 11 "/DBG_PRG/FTDI_USB_DM" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 36567 46413 900 15 4C5FF890 4CB9E528 ~~ +Li 0402 +Sc 4CB9E528 +AR /4C716A4D/4CB9E17F +Op 0 0 0 +At SMD +T0 0 -150 200 200 900 40 N V 25 N"FB2" +T1 0 150 200 200 900 40 N I 25 N"FILTER" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "/DBG_PRG/5V_USB" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/DBG_PRG/VCC_USB" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 49724 55067 0 15 4C5FF890 4CB9E52A ~~ +Li 0402 +Sc 4CB9E52A +AR /4C716A4D/4CB9CA50 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"FB1" +T1 0 150 200 200 0 40 N I 25 N"FILTER" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 382 "N-000229" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 36067 44866 1800 15 4C5FF890 4CB9E52C ~~ +Li 0402 +Sc 4CB9E52C +AR /4C716A4D/4CB9C996 +Op 0 0 0 +At SMD +T0 0 -150 200 200 1800 40 N V 25 N"C151" +T1 0 150 200 200 1800 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 383 "N-000231" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 35965 47315 0 15 4C5FF890 4CB9E52E ~~ +Li 0402 +Sc 4CB9E52E +AR /4C716A4D/4CB9C965 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C149" +T1 0 150 200 200 0 40 N I 25 N"33nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "/DBG_PRG/3.3V_USB" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 35925 46815 1800 15 4C5FF890 4CB9E530 ~~ +Li 0402 +Sc 4CB9E530 +AR /4C716A4D/4CB9C9AD +Op 0 0 0 +At SMD +T0 0 -150 200 200 1800 40 N V 25 N"C148" +T1 0 150 200 200 1800 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "/DBG_PRG/5V_USB" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 35106 47358 2700 15 4C5FF890 4CB9E532 ~~ +Li 0402 +Sc 4CB9E532 +AR /4C716A4D/4CB9DE25 +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 25 N"C147" +T1 0 150 200 200 2700 40 N I 25 N"47pF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 364 "N-000208" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 32870 47358 900 15 4C5FF890 4CB9E534 ~~ +Li 0402 +Sc 4CB9E534 +AR /4C716A4D/4CB9DE29 +Op 0 0 0 +At SMD +T0 0 -150 200 200 900 40 N V 25 N"C146" +T1 0 150 200 200 900 40 N I 25 N"47pF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 381 "N-000226" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 35846 46094 1800 15 4C5FF890 4CB9E535 ~~ +Li 0603 +Sc 4CB9E535 +AR /4C716A4D/4CB9D9A7 +Op 0 0 0 +At SMD +T0 0 -150 200 200 1800 40 N V 25 N"C150" +T1 0 150 200 200 1800 40 N I 25 N"10uF" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/DBG_PRG/VCC_USB" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 1206 +Po 52976 57697 0 15 4C5FF890 4CB9E536 ~~ +Li 1206 +Sc 4CB9E536 +AR /4C716A4D/4CB9D313 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R69" +T1 0 150 200 200 0 40 N I 25 N"1M" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/DBG_PRG/USB_CASE_FTDI" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 +$MODULE 1206 +Po 45382 57732 0 15 4C5FF890 4CB9E538 ~~ +Li 1206 +Sc 4CB9E538 +AR /4C716A4D/4CB9D312 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C145" +T1 0 150 200 200 0 40 N I 25 N"4.7nF" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/DBG_PRG/USB_CASE_FTDI" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 +$MODULE CRYSTAL +Po 33587 47370 0 15 4CB9DFD5 4CB9E539 ~~ +Li CRYSTAL +Sc 4CB9E539 +AR /4C716A4D/4CB9DDF8 +Op 0 0 0 +T0 417 -1173 280 180 0 45 N V 21 N"X1" +T1 394 961 600 600 0 120 N I 21 N"6MHz" +DC 0 433 -59 423 30 21 +DS -374 -955 -374 325 30 21 +DS -374 325 1240 325 30 21 +DS 1240 325 1240 -955 30 21 +DS 1240 -955 -374 -955 30 21 +$PAD +Sh "1" R 551 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 381 "N-000226" +Po 0 0 +$EndPAD +$PAD +Sh "3" R 551 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 866 0 +$EndPAD +$PAD +Sh "2" R 551 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 364 "N-000208" +Po 866 -630 +$EndPAD +$PAD +Sh "4" R 551 453 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 -630 +$EndPAD +$EndMODULE CRYSTAL +$MODULE LQFP48 +Po 39039 46728 0 15 4C433D64 4CB9E53A ~~ +Li LQFP48 +Sc 4CB9E53A +AR /4C716A4D/4CB9C4D7 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"IC1" +T1 0 150 200 200 0 40 N I 25 N"FT2232D" +DC -1574 -1574 -1574 -1653 39 21 +DS -1377 -1377 -1377 1377 39 21 +DS -1377 1377 1377 1377 39 21 +DS 1377 1377 1377 -1377 39 21 +DS 1377 -1377 -1377 -1377 39 21 +$PAD +Sh "12" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 376 "N-000220" +Po -1613 1082 +$EndPAD +$PAD +Sh "11" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 375 "N-000219" +Po -1613 885 +$EndPAD +$PAD +Sh "10" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 384 "N-000232" +Po -1613 688 +$EndPAD +$PAD +Sh "9" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po -1613 491 +$EndPAD +$PAD +Sh "8" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 387 "N-000235" +Po -1613 295 +$EndPAD +$PAD +Sh "7" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 388 "N-000236" +Po -1613 98 +$EndPAD +$PAD +Sh "6" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "/DBG_PRG/3.3V_USB" +Po -1613 -98 +$EndPAD +$PAD +Sh "5" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 386 "N-000234" +Po -1613 -295 +$EndPAD +$PAD +Sh "4" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/DBG_PRG/VCC_USB" +Po -1613 -491 +$EndPAD +$PAD +Sh "3" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/DBG_PRG/VCC_USB" +Po -1613 -688 +$EndPAD +$PAD +Sh "2" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 385 "N-000233" +Po -1613 -885 +$EndPAD +$PAD +Sh "1" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1613 -1082 +$EndPAD +$PAD +Sh "48" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1082 -1613 +$EndPAD +$PAD +Sh "47" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po -885 -1613 +$EndPAD +$PAD +Sh "46" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 383 "N-000231" +Po -688 -1613 +$EndPAD +$PAD +Sh "45" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po -491 -1613 +$EndPAD +$PAD +Sh "44" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 364 "N-000208" +Po -295 -1613 +$EndPAD +$PAD +Sh "43" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 381 "N-000226" +Po -98 -1613 +$EndPAD +$PAD +Sh "42" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/DBG_PRG/VCC_USB" +Po 98 -1613 +$EndPAD +$PAD +Sh "41" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 295 -1613 +$EndPAD +$PAD +Sh "40" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 8 "/DBG_PRG/AVR_SCK" +Po 491 -1613 +$EndPAD +$PAD +Sh "39" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 317 "/PSU/AVR_MOSI" +Po 688 -1613 +$EndPAD +$PAD +Sh "38" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 316 "/PSU/AVR_MISO" +Po 885 -1613 +$EndPAD +$PAD +Sh "37" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 318 "/PSU/AVR_RST" +Po 1082 -1613 +$EndPAD +$PAD +Sh "25" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po 1613 1082 +$EndPAD +$PAD +Sh "26" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 389 "N-000237" +Po 1613 885 +$EndPAD +$PAD +Sh "27" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 378 "N-000222" +Po 1613 688 +$EndPAD +$PAD +Sh "28" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 377 "N-000221" +Po 1613 491 +$EndPAD +$PAD +Sh "29" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 379 "N-000223" +Po 1613 295 +$EndPAD +$PAD +Sh "30" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 380 "N-000224" +Po 1613 98 +$EndPAD +$PAD +Sh "31" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "/DBG_PRG/3.3V_USB" +Po 1613 -98 +$EndPAD +$PAD +Sh "32" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 367 "N-000211" +Po 1613 -295 +$EndPAD +$PAD +Sh "33" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 368 "N-000212" +Po 1613 -491 +$EndPAD +$PAD +Sh "34" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po 1613 -688 +$EndPAD +$PAD +Sh "35" R 315 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 366 "N-000210" +Po 1613 -885 +$EndPAD +$PAD +Sh "36" R 315 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 365 "N-000209" +Po 1613 -1082 +$EndPAD +$PAD +Sh "13" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 374 "N-000218" +Po -1082 1613 +$EndPAD +$PAD +Sh "14" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "/DBG_PRG/3.3V_USB" +Po -885 1613 +$EndPAD +$PAD +Sh "15" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 373 "N-000217" +Po -688 1613 +$EndPAD +$PAD +Sh "16" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 370 "N-000214" +Po -491 1613 +$EndPAD +$PAD +Sh "17" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 369 "N-000213" +Po -295 1613 +$EndPAD +$PAD +Sh "18" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 347 "GND" +Po -98 1613 +$EndPAD +$PAD +Sh "19" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 371 "N-000215" +Po 98 1613 +$EndPAD +$PAD +Sh "20" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 372 "N-000216" +Po 295 1613 +$EndPAD +$PAD +Sh "21" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "/DBG_PRG/FPGA_TMS" +Po 491 1613 +$EndPAD +$PAD +Sh "22" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 120 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TDO" +Po 688 1613 +$EndPAD +$PAD +Sh "23" R 99 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 9 "/DBG_PRG/FPGA_TDI" +Po 885 1613 +$EndPAD +$PAD +Sh "24" R 98 315 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 119 "/FPGA,_Port0,_Port2,_PROG_IF/S6_TCK" +Po 1082 1613 +$EndPAD +$EndMODULE LQFP48 +$MODULE ZX62D-B-5P8 +Po 48724 56555 0 15 4BAADC40 4CB9E55A ~~ +Li ZX62D-B-5P8 +Sc 4CB9E55A +AR /4C716A4D/4CB9D311 +Op 0 0 0 +T0 446 -852 157 157 0 20 N V 21 N"J8" +T1 550 -500 118 118 0 20 N I 21 N"ZX62D-B-5P8" +DS -1690 2970 -1760 2970 100 21 +DS -1760 2970 -1760 -630 100 21 +DS -1760 -630 2960 -630 100 21 +DS 2960 -630 2960 -630 100 21 +DS 2960 -630 2960 2970 100 21 +DS 2960 2970 -1690 2970 100 21 +DS -1910 3120 -1910 -780 10 24 +DS -1910 -780 3110 -780 10 24 +DS 3110 -780 3110 3120 10 24 +DS 3110 3120 -1910 3120 10 24 +$PAD +Sh "1" R 200 620 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "/DBG_PRG/5V_USB" +Po 0 0 +$EndPAD +$PAD +Sh "2" R 200 620 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 11 "/DBG_PRG/FTDI_USB_DM" +Po 310 0 +$EndPAD +$PAD +Sh "3" R 200 620 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 12 "/DBG_PRG/FTDI_USB_DP" +Po 630 0 +$EndPAD +$PAD +Sh "4" R 200 620 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 382 "N-000229" +Po 940 0 +$EndPAD +$PAD +Sh "5" R 200 620 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 382 "N-000229" +Po 1260 0 +$EndPAD +$PAD +Sh "H1" C 380 380 0 0 0 +Dr 420 0 0 +At STD N 00C08001 +Ne 0 "" +Po -240 1170 +$EndPAD +$PAD +Sh "H2" C 380 380 0 0 0 +Dr 420 0 0 +At STD N 00C08001 +Ne 0 "" +Po 1490 1170 +$EndPAD +$PAD +Sh "8" R 860 900 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/DBG_PRG/USB_CASE_FTDI" +Po -1070 140 +$EndPAD +$PAD +Sh "6" R 860 900 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/DBG_PRG/USB_CASE_FTDI" +Po 2320 2310 +$EndPAD +$PAD +Sh "7" R 860 900 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/DBG_PRG/USB_CASE_FTDI" +Po -1070 2310 +$EndPAD +$PAD +Sh "9" R 860 900 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/DBG_PRG/USB_CASE_FTDI" +Po 2320 140 +$EndPAD +$EndMODULE ZX62D-B-5P8 $COTATION Ge 0 25 0 Va 39410 @@ -17301,11 +18237,6 @@ $DRAWSEGMENT Po 0 45709 13386 45709 52756 150 De 28 0 900 0 0 $EndDRAWSEGMENT -$TEXTPCB -Te "PROGRAMMING" -Po 72512 20543 394 591 99 0 -De 25 1 0 Normal -$EndTEXTPCB $TRACK Po 0 60626 35110 60822 35110 39 -1 De 15 0 0 0 0 @@ -18957,2138 +19888,2290 @@ Po 0 62145 21869 61987 21711 79 -1 De 15 0 5 0 0 Po 0 61987 21711 61987 21657 79 -1 De 15 0 5 0 400 -Po 0 58835 31205 58835 31803 59 -1 -De 3 0 6 0 0 -Po 0 59583 30209 59583 30409 59 -1 -De 3 0 6 0 0 -Po 0 59583 30409 58835 31205 59 -1 -De 3 0 6 0 0 -Po 0 59634 30158 60040 29752 59 -1 -De 3 0 6 0 0 -Po 0 60040 29752 60047 29752 59 -1 -De 3 0 6 0 0 -Po 3 60047 29752 60047 29752 157 -1 -De 15 1 6 0 0 -Po 0 60047 29752 60862 28937 59 -1 -De 0 0 6 0 0 -Po 0 60862 28933 60862 28937 59 -1 -De 0 0 6 0 0 -Po 0 59634 30158 59583 30209 59 -1 -De 3 0 6 0 0 -Po 0 58835 31803 58823 31815 59 -1 -De 3 0 6 0 0 -Po 0 57646 32607 57646 32598 59 -1 -De 15 0 6 0 800 -Po 0 58402 32236 58823 31815 59 -1 -De 3 0 6 0 0 -Po 0 58823 31815 58811 31827 59 -1 -De 3 0 6 0 0 -Po 0 58008 32236 58402 32236 59 -1 -De 3 0 6 0 0 -Po 0 57799 32445 58008 32236 59 -1 -De 3 0 6 0 0 -Po 3 57799 32445 57799 32445 157 -1 -De 15 1 6 0 0 -Po 0 57646 32598 57799 32445 59 -1 -De 15 0 6 0 0 Po 0 59614 31098 59614 30563 59 -1 -De 3 0 7 0 0 +De 3 0 9 0 0 Po 0 59732 30315 61031 29016 59 -1 -De 3 0 7 0 0 +De 3 0 9 0 0 Po 0 59732 30445 59732 30315 59 -1 -De 3 0 7 0 0 +De 3 0 9 0 0 Po 0 59614 30563 59732 30445 59 -1 -De 3 0 7 0 0 +De 3 0 9 0 0 Po 0 59024 32004 59425 32004 59 -1 -De 3 0 7 0 0 +De 3 0 9 0 0 Po 0 58840 31820 59024 32004 59 -1 -De 15 0 7 0 0 -Po 3 59024 32004 59024 32004 157 -1 -De 15 1 7 0 0 -Po 0 58827 31820 58840 31820 59 -1 -De 15 0 7 0 800 -Po 0 59614 31815 59614 31098 59 -1 -De 3 0 7 0 0 -Po 0 59614 31098 59614 31114 59 -1 -De 3 0 7 0 0 -Po 0 59425 32004 59614 31815 59 -1 -De 3 0 7 0 0 -Po 0 50995 31576 50694 31576 39 -1 -De 15 0 8 0 800 -Po 0 49921 31535 49768 31535 39 -1 -De 0 0 8 0 400 -Po 0 49961 31575 49921 31535 39 -1 -De 0 0 8 0 0 -Po 0 50693 31575 49961 31575 39 -1 -De 0 0 8 0 0 -Po 3 50693 31575 50693 31575 157 -1 -De 15 1 8 0 0 -Po 0 50694 31576 50693 31575 39 -1 -De 15 0 8 0 0 -Po 0 50995 31320 50040 31320 39 -1 -De 15 0 9 0 800 -Po 0 50020 31338 49768 31338 39 -1 -De 0 0 9 0 400 -Po 0 50039 31319 50020 31338 39 -1 -De 0 0 9 0 0 -Po 3 50039 31319 50039 31319 157 -1 -De 15 1 9 0 0 -Po 0 50040 31320 50039 31319 39 -1 De 15 0 9 0 0 -Po 0 47941 32134 47425 32134 39 -1 -De 0 0 10 0 800 -Po 0 47216 32343 46643 32343 39 -1 +Po 3 59024 32004 59024 32004 157 -1 +De 15 1 9 0 0 +Po 0 58827 31820 58840 31820 59 -1 +De 15 0 9 0 800 +Po 0 59614 31815 59614 31098 59 -1 +De 3 0 9 0 0 +Po 0 59614 31098 59614 31114 59 -1 +De 3 0 9 0 0 +Po 0 59425 32004 59614 31815 59 -1 +De 3 0 9 0 0 +Po 0 59134 29925 59134 30638 59 -1 +De 3 0 10 0 0 +Po 0 58827 31027 58827 31032 59 -1 De 15 0 10 0 400 -Po 0 47425 32134 47216 32343 39 -1 -De 15 0 10 0 0 -Po 3 47425 32134 47425 32134 157 -1 +Po 3 58965 30807 58965 30807 157 -1 De 15 1 10 0 0 -Po 0 47941 31937 47657 31937 39 -1 -De 0 0 11 0 800 -Po 0 47460 32599 46643 32599 39 -1 -De 15 0 11 0 400 -Po 0 47583 32476 47460 32599 39 -1 -De 15 0 11 0 0 -Po 0 47583 32011 47583 32476 39 -1 -De 15 0 11 0 0 -Po 0 47657 31937 47583 32011 39 -1 -De 15 0 11 0 0 -Po 3 47657 31937 47657 31937 157 -1 -De 15 1 11 0 0 -Po 0 47937 31142 47417 31142 39 -1 -De 0 0 12 0 800 -Po 0 47239 31320 46643 31320 39 -1 -De 15 0 12 0 400 -Po 0 47417 31142 47239 31320 39 -1 -De 15 0 12 0 0 -Po 3 47417 31142 47417 31142 157 -1 -De 15 1 12 0 0 -Po 0 47937 30945 47646 30945 39 -1 -De 0 0 13 0 800 -Po 0 47417 31576 46643 31576 39 -1 -De 15 0 13 0 400 -Po 0 47575 31418 47417 31576 39 -1 -De 15 0 13 0 0 -Po 0 47575 31016 47575 31418 39 -1 -De 15 0 13 0 0 -Po 0 47646 30945 47575 31016 39 -1 -De 15 0 13 0 0 -Po 3 47646 30945 47646 30945 157 -1 -De 15 1 13 0 0 -Po 0 47941 32527 47256 32527 39 -1 -De 0 0 14 0 800 -Po 0 46883 31832 46643 31832 39 -1 -De 15 0 14 0 400 -Po 0 46980 31929 46883 31832 39 -1 -De 15 0 14 0 0 -Po 3 46980 31929 46980 31929 157 -1 -De 15 1 14 0 0 -Po 0 46980 32251 46980 31929 39 -1 -De 0 0 14 0 0 -Po 0 47256 32527 46980 32251 39 -1 -De 0 0 14 0 0 -Po 0 50995 32344 50017 32344 39 -1 -De 15 0 15 0 800 -Po 0 49988 32315 49775 32315 39 -1 -De 0 0 15 0 400 -Po 0 50016 32343 49988 32315 39 -1 -De 0 0 15 0 0 -Po 3 50016 32343 50016 32343 157 -1 -De 15 1 15 0 0 -Po 0 50017 32344 50016 32343 39 -1 +Po 0 58827 31027 58965 30807 59 -1 +De 15 0 10 0 0 +Po 0 59134 30638 58965 30807 59 -1 +De 3 0 10 0 0 +Po 0 59209 29846 59209 29850 59 -1 +De 3 0 10 0 0 +Po 0 59209 29850 59134 29925 59 -1 +De 3 0 10 0 0 +Po 0 59134 29925 59138 29921 59 -1 +De 3 0 10 0 0 +Po 0 60464 28591 60465 28591 59 -1 +De 3 0 10 0 0 +Po 0 59213 29842 59209 29846 59 -1 +De 3 0 10 0 0 +Po 0 59209 29846 60464 28591 59 -1 +De 3 0 10 0 0 +Po 0 49775 31922 50027 31922 39 -1 +De 0 0 15 0 800 +Po 0 50117 31832 50995 31832 39 -1 +De 15 0 15 0 400 +Po 0 50051 31898 50117 31832 39 -1 De 15 0 15 0 0 -Po 0 50995 33367 50677 33367 39 -1 -De 15 0 16 0 800 -Po 3 50055 33610 50055 33610 157 -1 +Po 3 50051 31898 50051 31898 157 -1 +De 15 1 15 0 0 +Po 0 50027 31922 50051 31898 39 -1 +De 0 0 15 0 0 +Po 0 47941 32134 47425 32134 39 -1 +De 0 0 16 0 800 +Po 0 47216 32343 46643 32343 39 -1 +De 15 0 16 0 400 +Po 0 47425 32134 47216 32343 39 -1 +De 15 0 16 0 0 +Po 3 47425 32134 47425 32134 157 -1 De 15 1 16 0 0 -Po 0 50055 33610 50039 33626 39 -1 -De 0 0 16 0 0 -Po 0 50039 33626 49795 33626 39 -1 -De 0 0 16 0 400 -Po 0 50224 33441 50055 33610 39 -1 -De 15 0 16 0 0 -Po 0 50603 33441 50224 33441 39 -1 -De 15 0 16 0 0 -Po 0 50677 33367 50603 33441 39 -1 -De 15 0 16 0 0 -Po 0 46643 33367 47765 33367 39 -1 -De 15 0 17 0 800 -Po 0 48072 33189 48151 33268 39 -1 -De 0 0 17 0 400 -Po 0 47933 33189 48072 33189 39 -1 -De 0 0 17 0 0 -Po 0 47923 33199 47933 33189 39 -1 -De 0 0 17 0 0 -Po 3 47923 33199 47923 33199 157 -1 +Po 0 47937 31535 47145 31535 39 -1 +De 0 0 17 0 800 +Po 0 46843 30808 46643 30808 39 -1 +De 15 0 17 0 400 +Po 0 46941 30906 46843 30808 39 -1 +De 15 0 17 0 0 +Po 3 46941 30906 46941 30906 157 -1 De 15 1 17 0 0 -Po 0 47923 33209 47923 33199 39 -1 -De 15 0 17 0 0 -Po 0 47765 33367 47923 33209 39 -1 -De 15 0 17 0 0 -Po 0 49838 38086 49937 38086 39 -1 +Po 0 46941 31331 46941 30906 39 -1 +De 0 0 17 0 0 +Po 0 47145 31535 46941 31331 39 -1 +De 0 0 17 0 0 +Po 0 47937 31338 47294 31338 39 -1 De 0 0 18 0 800 -Po 0 50736 38484 50995 38484 39 -1 +Po 0 47020 31064 46643 31064 39 -1 De 15 0 18 0 400 -Po 0 50673 38421 50736 38484 39 -1 +Po 0 47110 31154 47020 31064 39 -1 De 15 0 18 0 0 -Po 3 50673 38421 50673 38421 157 -1 +Po 3 47110 31154 47110 31154 157 -1 De 15 1 18 0 0 -Po 0 50272 38421 50673 38421 39 -1 +Po 0 47294 31338 47110 31154 39 -1 De 0 0 18 0 0 -Po 0 49937 38086 50272 38421 39 -1 -De 0 0 18 0 0 -Po 0 47351 36590 47209 36590 39 -1 +Po 0 47941 32527 47256 32527 39 -1 De 0 0 19 0 800 -Po 0 46850 36949 46643 36949 39 -1 +Po 0 46883 31832 46643 31832 39 -1 De 15 0 19 0 400 -Po 0 47000 36799 46850 36949 39 -1 +Po 0 46980 31929 46883 31832 39 -1 De 15 0 19 0 0 -Po 3 47000 36799 47000 36799 157 -1 +Po 3 46980 31929 46980 31929 157 -1 De 15 1 19 0 0 -Po 0 47209 36590 47000 36799 39 -1 +Po 0 46980 32251 46980 31929 39 -1 De 0 0 19 0 0 -Po 0 46643 37204 46900 37204 39 -1 +Po 0 47256 32527 46980 32251 39 -1 +De 0 0 19 0 0 +Po 0 50995 32344 50017 32344 39 -1 De 15 0 20 0 800 -Po 0 47188 37492 47362 37492 39 -1 +Po 0 49988 32315 49775 32315 39 -1 De 0 0 20 0 400 -Po 0 47035 37339 47188 37492 39 -1 +Po 0 50016 32343 49988 32315 39 -1 De 0 0 20 0 0 -Po 3 47035 37339 47035 37339 157 -1 +Po 3 50016 32343 50016 32343 157 -1 De 15 1 20 0 0 -Po 0 46900 37204 47035 37339 39 -1 +Po 0 50017 32344 50016 32343 39 -1 De 15 0 20 0 0 -Po 0 47362 38082 47260 38082 39 -1 -De 0 0 21 0 800 -Po 0 46858 38484 46643 38484 39 -1 -De 15 0 21 0 400 -Po 0 46972 38370 46858 38484 39 -1 -De 15 0 21 0 0 -Po 3 46972 38370 46972 38370 157 -1 -De 15 1 21 0 0 -Po 0 47260 38082 46972 38370 39 -1 +Po 0 50995 32088 50706 32088 39 -1 +De 15 0 21 0 800 +Po 0 50657 32119 49775 32119 39 -1 +De 0 0 21 0 400 +Po 0 50697 32079 50657 32119 39 -1 De 0 0 21 0 0 -Po 0 49846 36338 50056 36338 39 -1 -De 0 0 22 0 800 -Po 0 50161 36437 50995 36437 39 -1 -De 15 0 22 0 400 -Po 0 50059 36335 50161 36437 39 -1 -De 15 0 22 0 0 -Po 3 50059 36335 50059 36335 157 -1 -De 15 1 22 0 0 -Po 0 50056 36338 50059 36335 39 -1 +Po 3 50697 32079 50697 32079 157 -1 +De 15 1 21 0 0 +Po 0 50706 32088 50697 32079 39 -1 +De 15 0 21 0 0 +Po 0 46643 36437 47000 36437 39 -1 +De 15 0 22 0 800 +Po 0 47044 36393 47351 36393 39 -1 +De 0 0 22 0 400 +Po 0 47004 36433 47044 36393 39 -1 De 0 0 22 0 0 -Po 0 46643 35669 46826 35669 39 -1 -De 15 0 23 0 800 -Po 0 47157 36000 47351 36000 39 -1 -De 0 0 23 0 400 -Po 0 47035 35878 47157 36000 39 -1 -De 0 0 23 0 0 -Po 3 47035 35878 47035 35878 157 -1 -De 15 1 23 0 0 -Po 0 46826 35669 47035 35878 39 -1 +Po 3 47004 36433 47004 36433 157 -1 +De 15 1 22 0 0 +Po 0 47000 36437 47004 36433 39 -1 +De 15 0 22 0 0 +Po 0 47351 36590 47209 36590 39 -1 +De 0 0 23 0 800 +Po 0 46850 36949 46643 36949 39 -1 +De 15 0 23 0 400 +Po 0 47000 36799 46850 36949 39 -1 De 15 0 23 0 0 -Po 0 47351 36197 47031 36197 39 -1 +Po 3 47000 36799 47000 36799 157 -1 +De 15 1 23 0 0 +Po 0 47209 36590 47000 36799 39 -1 +De 0 0 23 0 0 +Po 0 49846 36535 49925 36535 39 -1 De 0 0 24 0 800 -Po 0 47015 36181 46643 36181 39 -1 +Po 0 50339 36949 50995 36949 39 -1 De 15 0 24 0 400 -Po 0 47031 36197 47015 36181 39 -1 +Po 0 50126 36736 50339 36949 39 -1 De 15 0 24 0 0 -Po 3 47031 36197 47031 36197 157 -1 +Po 3 50126 36736 50126 36736 157 -1 De 15 1 24 0 0 -Po 0 50995 33111 50716 33111 39 -1 +Po 0 49925 36535 50126 36736 39 -1 +De 0 0 24 0 0 +Po 0 50709 36949 50995 36949 39 -1 +De 15 0 24 0 400 +Po 0 50995 33879 50598 33879 39 -1 De 15 0 25 0 800 -Po 0 49858 32512 50039 32693 39 -1 -De 0 0 25 0 0 -Po 3 50039 32693 50039 32693 157 -1 -De 15 1 25 0 0 -Po 0 49858 32512 49775 32512 39 -1 +Po 0 50458 34019 49795 34019 39 -1 De 0 0 25 0 400 -Po 0 50039 33102 50039 32693 39 -1 +Po 0 50520 33957 50458 34019 39 -1 +De 0 0 25 0 0 +Po 3 50520 33957 50520 33957 157 -1 +De 15 1 25 0 0 +Po 0 50598 33879 50520 33957 39 -1 De 15 0 25 0 0 -Po 0 50224 33287 50039 33102 39 -1 -De 15 0 25 0 0 -Po 0 50540 33287 50224 33287 39 -1 -De 15 0 25 0 0 -Po 0 50716 33111 50540 33287 39 -1 -De 15 0 25 0 0 -Po 0 46643 33879 47916 33879 39 -1 +Po 0 50995 34901 50688 34901 39 -1 De 15 0 26 0 800 -Po 0 48102 34055 48151 34055 39 -1 +Po 0 50003 34216 49795 34216 39 -1 De 0 0 26 0 400 -Po 0 47921 33874 48102 34055 39 -1 +Po 0 50681 34894 50003 34216 39 -1 De 0 0 26 0 0 -Po 3 47921 33874 47921 33874 157 -1 +Po 3 50681 34894 50681 34894 157 -1 De 15 1 26 0 0 -Po 0 47916 33879 47921 33874 39 -1 +Po 0 50688 34901 50681 34894 39 -1 De 15 0 26 0 0 -Po 0 47751 34901 47846 34996 39 -1 -De 15 0 27 0 0 -Po 0 46643 34901 47751 34901 39 -1 -De 15 0 27 0 800 -Po 0 47889 35039 48151 35039 39 -1 -De 0 0 27 0 400 -Po 0 47846 34996 47889 35039 39 -1 -De 0 0 27 0 0 -Po 3 47846 34996 47846 34996 157 -1 -De 15 1 27 0 0 Po 0 46643 34391 47017 34391 79 -1 -De 15 0 28 0 800 +De 15 0 27 0 800 Po 0 47265 34290 47265 34154 79 -1 -De 0 0 28 0 400 +De 0 0 27 0 400 Po 0 47165 34390 47265 34290 79 -1 -De 0 0 28 0 0 +De 0 0 27 0 0 Po 0 47018 34390 47165 34390 79 -1 -De 0 0 28 0 0 +De 0 0 27 0 0 Po 3 47018 34390 47018 34390 157 -1 -De 15 1 28 0 0 +De 15 1 27 0 0 Po 0 47017 34391 47018 34390 79 -1 -De 15 0 28 0 0 +De 15 0 27 0 0 Po 0 47265 34646 47265 34154 79 -1 -De 0 0 28 0 C00 +De 0 0 27 0 C00 Po 0 47265 33661 47265 34154 79 -1 -De 0 0 28 0 C00 +De 0 0 27 0 C00 Po 0 47265 33169 47265 33661 79 -1 -De 0 0 28 0 C00 -Po 0 65956 31576 65360 31576 39 -1 -De 15 0 29 0 800 -Po 0 65331 31547 65130 31547 39 -1 -De 0 0 29 0 400 -Po 0 65335 31551 65331 31547 39 -1 -De 0 0 29 0 0 -Po 3 65335 31551 65335 31551 157 -1 -De 15 1 29 0 0 -Po 0 65360 31576 65335 31551 39 -1 -De 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-De 15 0 325 0 0 -Po 0 62756 25035 62655 25136 79 -1 -De 15 0 325 0 0 -Po 3 62756 25035 62756 25035 157 -1 -De 15 1 325 0 0 -Po 0 63065 25124 63069 25124 79 -1 -De 15 0 325 0 0 -Po 0 62965 25024 63065 25124 79 -1 -De 15 0 325 0 0 -Po 3 62965 25024 62965 25024 157 -1 -De 15 1 325 0 0 -Po 0 62866 24925 62965 25024 79 -1 -De 0 0 325 0 0 -Po 0 62717 25265 62928 25265 236 -1 -De 15 0 325 0 800 -Po 0 62928 25265 63069 25124 236 -1 -De 15 0 325 0 0 -Po 0 63069 25124 63165 25028 236 -1 -De 15 0 325 0 0 -Po 0 63165 25028 63165 24864 236 -1 -De 15 0 325 0 400 -Po 0 61968 25136 62535 25136 315 -1 -De 15 0 325 0 800 -Po 0 62535 25136 62588 25136 315 -1 -De 15 0 325 0 0 -Po 0 62588 25136 62717 25265 315 -1 -De 15 0 325 0 400 -Po 0 61968 25136 61968 24683 79 -1 -De 15 0 325 0 800 -Po 0 61618 24327 61811 24327 79 -1 +Po 0 63485 25357 63489 25353 39 -1 De 0 0 325 0 400 -Po 0 61615 24330 61618 24327 79 -1 +Po 0 63489 25353 63489 24822 39 -1 +De 0 0 325 0 C00 +Po 0 63489 25865 63489 25353 39 -1 +De 0 0 325 0 400 +Po 0 63165 25614 63165 25793 39 -1 +De 15 0 325 0 800 +Po 0 63267 25865 63489 25865 39 -1 De 0 0 325 0 0 -Po 3 61615 24330 61615 24330 157 -1 +Po 0 63252 25880 63267 25865 39 -1 +De 0 0 325 0 0 +Po 3 63252 25880 63252 25880 157 -1 De 15 1 325 0 0 -Po 0 61968 24683 61615 24330 79 -1 +Po 0 63165 25793 63252 25880 39 -1 De 15 0 325 0 0 -Po 0 62928 25265 63165 25028 59 -1 -De 15 0 325 0 0 -Po 0 63165 25028 63165 24864 59 -1 -De 15 0 325 0 400 -Po 0 62791 22819 62791 22992 236 -1 -De 15 0 326 0 0 -Po 0 62851 23052 63185 23052 236 -1 +Po 0 63865 22220 63865 22079 39 -1 +De 0 0 326 0 800 +Po 0 64256 22231 64185 22302 39 -1 De 15 0 326 0 400 -Po 0 62791 22992 62851 23052 236 -1 +Po 0 64256 22114 64256 22231 39 -1 De 15 0 326 0 0 -Po 0 62644 22797 62769 22797 236 -1 +Po 0 64173 22031 64256 22114 39 -1 De 15 0 326 0 0 -Po 0 62769 22797 62791 22819 236 -1 -De 15 0 326 0 0 -Po 0 61987 22797 62644 22797 315 -1 -De 15 0 326 0 800 -Po 0 62644 22797 62646 22795 315 -1 -De 15 0 326 0 0 -Po 0 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42406 46612 42150 157 -1 -De 15 0 366 0 400 +De 15 0 398 0 400 Po 0 46868 42803 46868 42406 157 -1 -De 15 0 366 0 0 +De 15 0 398 0 0 Po 0 47140 43075 46868 42803 157 -1 -De 15 0 366 0 0 +De 15 0 398 0 0 Po 0 60352 42997 60352 42672 79 -1 -De 15 0 367 0 800 +De 15 0 399 0 800 Po 0 60395 42629 60395 42430 79 -1 -De 0 0 367 0 400 +De 0 0 399 0 400 Po 0 60381 42643 60395 42629 79 -1 -De 0 0 367 0 0 +De 0 0 399 0 0 Po 3 60381 42643 60381 42643 157 -1 -De 15 1 367 0 0 +De 15 1 399 0 0 Po 0 60352 42672 60381 42643 79 -1 -De 15 0 367 0 0 +De 15 0 399 0 0 Po 0 47761 43056 47991 43056 79 -1 -De 0 0 368 0 800 +De 0 0 400 0 800 Po 0 48016 43075 48313 43075 79 -1 -De 15 0 368 0 400 +De 15 0 400 0 400 Po 0 48013 43078 48016 43075 79 -1 -De 15 0 368 0 0 +De 15 0 400 0 0 Po 3 48013 43078 48013 43078 157 -1 -De 15 1 368 0 0 +De 15 1 400 0 0 Po 0 47991 43056 48013 43078 79 -1 -De 0 0 368 0 0 +De 0 0 400 0 0 Po 0 47761 42687 47340 42687 79 -1 -De 0 0 369 0 800 +De 0 0 401 0 800 Po 0 47340 42687 47328 42675 79 -1 -De 0 0 369 0 400 +De 0 0 401 0 400 Po 0 47313 43075 47313 42690 79 -1 -De 0 0 369 0 800 +De 0 0 401 0 800 Po 0 47313 42690 47328 42675 79 -1 -De 0 0 369 0 400 +De 0 0 401 0 400 Po 0 48313 42700 47998 42700 79 -1 -De 15 0 369 0 800 +De 15 0 401 0 800 Po 0 47985 42687 47761 42687 79 -1 -De 0 0 369 0 400 +De 0 0 401 0 400 Po 0 47994 42696 47985 42687 79 -1 -De 0 0 369 0 0 +De 0 0 401 0 0 Po 3 47994 42696 47994 42696 157 -1 -De 15 1 369 0 0 +De 15 1 401 0 0 Po 0 47998 42700 47994 42696 79 -1 -De 15 0 369 0 0 +De 15 0 401 0 0 Po 0 63755 41951 63755 41779 157 -1 -De 15 0 370 0 800 +De 15 0 402 0 800 Po 0 64089 41445 64505 41445 157 -1 -De 15 0 370 0 0 +De 15 0 402 0 0 Po 0 63755 41779 64089 41445 157 -1 -De 15 0 370 0 0 +De 15 0 402 0 0 Po 0 64505 41951 64505 41445 157 -1 -De 15 0 370 0 800 +De 15 0 402 0 800 Po 0 64505 41445 64704 41246 157 -1 -De 15 0 370 0 400 +De 15 0 402 0 400 Po 0 63770 42415 63770 42610 79 -1 -De 0 0 371 0 800 +De 0 0 403 0 800 Po 0 63755 42625 63755 42951 79 -1 -De 15 0 371 0 400 +De 15 0 403 0 400 Po 0 63768 42612 63755 42625 79 -1 -De 15 0 371 0 0 +De 15 0 403 0 0 Po 3 63768 42612 63768 42612 157 -1 -De 15 1 371 0 0 +De 15 1 403 0 0 Po 0 63770 42610 63768 42612 79 -1 -De 0 0 371 0 0 +De 0 0 403 0 0 Po 0 63835 45085 63835 44873 157 -1 -De 15 0 372 0 800 +De 15 0 404 0 800 Po 0 64168 44540 64585 44540 157 -1 -De 15 0 372 0 0 +De 15 0 404 0 0 Po 0 63835 44873 64168 44540 157 -1 -De 15 0 372 0 0 +De 15 0 404 0 0 Po 0 64585 44540 64741 44384 157 -1 -De 15 0 372 0 400 +De 15 0 404 0 400 Po 0 64585 45085 64585 44540 157 -1 -De 15 0 372 0 800 +De 15 0 404 0 800 Po 0 64585 44540 64741 44384 157 -1 -De 15 0 372 0 400 +De 15 0 404 0 400 Po 0 63855 45129 64181 45129 79 -1 -De 0 0 373 0 800 +De 0 0 405 0 800 Po 0 64181 45129 64192 45140 79 -1 -De 0 0 373 0 400 +De 0 0 405 0 400 Po 0 64192 45546 64192 45140 79 -1 -De 0 0 373 0 C00 +De 0 0 405 0 C00 Po 0 64192 45546 64192 45760 79 -1 -De 0 0 373 0 800 +De 0 0 405 0 800 Po 0 64210 45778 64210 46085 79 -1 -De 15 0 373 0 400 +De 15 0 405 0 400 Po 0 64206 45774 64210 45778 79 -1 -De 15 0 373 0 0 +De 15 0 405 0 0 Po 3 64206 45774 64206 45774 157 -1 -De 15 1 373 0 0 +De 15 1 405 0 0 Po 0 64192 45760 64206 45774 79 -1 -De 0 0 373 0 0 +De 0 0 405 0 0 Po 0 64130 42951 64130 42608 79 -1 -De 15 0 374 0 800 +De 15 0 406 0 800 Po 0 64147 42591 64147 42407 79 -1 -De 0 0 374 0 400 +De 0 0 406 0 400 Po 0 64134 42604 64147 42591 79 -1 -De 0 0 374 0 0 +De 0 0 406 0 0 Po 3 64134 42604 64134 42604 157 -1 -De 15 1 374 0 0 +De 15 1 406 0 0 Po 0 64130 42608 64134 42604 79 -1 -De 15 0 374 0 0 +De 15 0 406 0 0 Po 0 63755 41931 64159 41931 79 -1 -De 0 0 374 0 C00 +De 0 0 406 0 C00 Po 0 64147 42407 64147 41943 79 -1 -De 0 0 374 0 800 +De 0 0 406 0 800 Po 0 64147 41943 64159 41931 79 -1 -De 0 0 374 0 400 +De 0 0 406 0 400 Po 0 64147 41943 64159 41931 39 -1 -De 0 0 374 0 400 +De 0 0 406 0 400 $EndTRACK $ZONE $EndZONE @@ -29816,7 +30747,7 @@ ZLayer 4 ZAux 47 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 S 79 79 +ZOptions 0 16 F 79 79 ZCorner 57465 32756 0 ZCorner 57465 32441 0 ZCorner 57807 32441 0 @@ -32519,7 +33450,7 @@ ZLayer 4 ZAux 51 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 S 79 79 +ZOptions 0 16 F 79 79 ZCorner 50610 40110 0 ZCorner 51756 37996 0 ZCorner 51843 37949 0 @@ -38176,12 +39107,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C74868B 341 "GND" +ZInfo 4C74868B 347 "GND" ZLayer 1 ZAux 16 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 S 79 79 +ZOptions 0 16 F 79 79 ZCorner 66094 41240 0 ZCorner 66339 30043 0 ZCorner 66339 29488 0 @@ -46117,7 +47048,7 @@ ZLayer 2 ZAux 9 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 S 79 79 +ZOptions 0 16 F 79 79 ZCorner 58146 36236 0 ZCorner 58146 33566 0 ZCorner 63350 28362 0 @@ -47326,12 +48257,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75CC96 318 "/PSU/SW_3.3" +ZInfo 4C75CC96 322 "/PSU/SW_3.3" ZLayer 15 ZAux 4 F ZClearance 157 T ZMinThickness 39 -ZOptions 0 16 S 39 197 +ZOptions 0 16 F 39 197 ZCorner 65823 25014 0 ZCorner 65823 24285 0 ZCorner 63953 24285 0 @@ -47414,12 +48345,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75CDA9 323 "/PSU/VIN_DC-DC-1.2" +ZInfo 4C75CDA9 327 "/PSU/VIN_DC-DC-1.2" ZLayer 15 ZAux 14 F ZClearance 39 T ZMinThickness 39 -ZOptions 0 16 S 39 79 +ZOptions 0 16 F 39 79 ZCorner 64362 27985 0 ZCorner 64362 27828 0 ZCorner 64370 27828 0 @@ -47521,12 +48452,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75CF67 325 "/PSU/VIN_DC-DC-3.3" +ZInfo 4C75CF67 329 "/PSU/VIN_DC-DC-3.3" ZLayer 15 ZAux 9 F ZClearance 157 T ZMinThickness 100 -ZOptions 1 16 S 39 197 +ZOptions 1 16 F 39 197 ZCorner 64366 25986 0 ZCorner 64366 25470 0 ZCorner 63949 25470 0 @@ -47660,7 +48591,7 @@ ZLayer 15 ZAux 5 E ZClearance 59 T ZMinThickness 59 -ZOptions 1 16 S 79 79 +ZOptions 1 16 F 79 79 ZCorner 65685 26091 0 ZCorner 65685 25552 0 ZCorner 65673 25540 0 @@ -47712,12 +48643,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75DFA9 316 "/PSU/SW_1.2" +ZInfo 4C75DFA9 320 "/PSU/SW_1.2" ZLayer 15 ZAux 4 F ZClearance 157 T ZMinThickness 39 -ZOptions 0 16 S 39 197 +ZOptions 0 16 F 39 197 ZCorner 65720 27016 0 ZCorner 65720 26362 0 ZCorner 63894 26362 0 @@ -47808,12 +48739,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75E13A 341 "GND" +ZInfo 4C75E13A 347 "GND" ZLayer 0 ZAux 35 F ZClearance 98 T ZMinThickness 100 -ZOptions 1 16 S 39 197 +ZOptions 1 16 F 39 197 ZCorner 66213 28496 0 ZCorner 66213 18843 0 ZCorner 66213 18815 0 @@ -49702,7 +50633,7 @@ ZLayer 4 ZAux 22 F ZClearance 59 T ZMinThickness 59 -ZOptions 1 16 S 79 79 +ZOptions 1 16 F 79 79 ZCorner 60594 38772 0 ZCorner 60594 38020 0 ZCorner 59642 38020 0 @@ -50041,12 +50972,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C7D3DA6 339 "/USB/USB_CASE_DEV" +ZInfo 4C7D3DA6 345 "/USB/USB_CASE_DEV" ZLayer 15 ZAux 6 E ZClearance 98 T ZMinThickness 100 -ZOptions 1 32 S 39 197 +ZOptions 1 32 F 39 197 ZCorner 65205 16941 0 ZCorner 65205 13362 0 ZCorner 58594 13362 0 @@ -50724,12 +51655,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C7D4490 340 "/USB/USB_CASE_HOST" +ZInfo 4C7D4490 346 "/USB/USB_CASE_HOST" ZLayer 15 ZAux 12 E ZClearance 98 T ZMinThickness 100 -ZOptions 1 32 S 39 197 +ZOptions 1 32 F 39 197 ZCorner 58630 21457 0 ZCorner 58630 18008 0 ZCorner 59331 17307 0 @@ -51555,12 +52486,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C7D44D4 340 "/USB/USB_CASE_HOST" +ZInfo 4C7D44D4 346 "/USB/USB_CASE_HOST" ZLayer 0 ZAux 12 E ZClearance 98 T ZMinThickness 100 -ZOptions 1 32 S 39 197 +ZOptions 1 32 F 39 197 ZCorner 58634 21461 0 ZCorner 58634 18012 0 ZCorner 59331 17315 0 @@ -52201,12 +53132,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C7FE465 317 "/PSU/SW_2.5" +ZInfo 4C7FE465 321 "/PSU/SW_2.5" ZLayer 15 ZAux 6 F ZClearance 157 T ZMinThickness 39 -ZOptions 0 32 S 39 197 +ZOptions 0 32 F 39 197 ZCorner 65732 19945 0 ZCorner 65732 19213 0 ZCorner 64583 19213 0 @@ -52295,12 +53226,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C893672 68 "/Ethernet_Phy/MAG_SHIELD" +ZInfo 4C893672 58 "/Ethernet_Phy/MAG_SHIELD" ZLayer 0 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 S 39 197 +ZOptions 1 32 F 39 197 ZCorner 54925 19335 0 ZCorner 54925 18299 0 ZCorner 53984 17358 0 @@ -52765,12 +53696,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C8936BC 68 "/Ethernet_Phy/MAG_SHIELD" +ZInfo 4C8936BC 58 "/Ethernet_Phy/MAG_SHIELD" ZLayer 15 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 S 39 197 +ZOptions 1 32 F 39 197 ZCorner 54929 19335 0 ZCorner 54929 18299 0 ZCorner 53988 17358 0 @@ -53327,12 +54258,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C893C7F 68 "/Ethernet_Phy/MAG_SHIELD" +ZInfo 4C893C7F 58 "/Ethernet_Phy/MAG_SHIELD" ZLayer 1 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 S 39 197 +ZOptions 1 32 F 39 197 ZCorner 54929 19335 0 ZCorner 54929 18303 0 ZCorner 53984 17358 0 @@ -53797,12 +54728,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C893CAD 68 "/Ethernet_Phy/MAG_SHIELD" +ZInfo 4C893CAD 58 "/Ethernet_Phy/MAG_SHIELD" ZLayer 4 ZAux 9 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 S 39 197 +ZOptions 1 32 F 39 197 ZCorner 54925 19339 0 ZCorner 54925 18299 0 ZCorner 53984 17358 0 @@ -54268,12 +55199,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C893D07 68 "/Ethernet_Phy/MAG_SHIELD" +ZInfo 4C893D07 58 "/Ethernet_Phy/MAG_SHIELD" ZLayer 2 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 S 39 197 +ZOptions 1 32 F 39 197 ZCorner 54929 19335 0 ZCorner 54929 18295 0 ZCorner 53988 17354 0 @@ -54738,12 +55669,12 @@ $FILLSEGMENTS $endFILLSEGMENTS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C893D38 68 "/Ethernet_Phy/MAG_SHIELD" +ZInfo 4C893D38 58 "/Ethernet_Phy/MAG_SHIELD" ZLayer 3 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 S 39 197 +ZOptions 1 32 F 39 197 ZCorner 54929 19335 0 ZCorner 54929 18291 0 ZCorner 53988 17350 0 diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp index 6b53414..ce89567 100644 --- a/kicad/xue-rnc/xue-rnc.cmp +++ b/kicad/xue-rnc/xue-rnc.cmp @@ -1,4 +1,4 @@ -Cmp-Mod V01 Created by CvPCB (2010-06-08 BZR 2367)-stable date = Fri 08 Oct 2010 09:27:08 AM COT +Cmp-Mod V01 Created by CvPCB (2010-06-08 BZR 2367)-stable date = Sat 16 Oct 2010 12:46:17 PM COT BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; @@ -798,13 +798,6 @@ ValeurCmp = 10uF; IdModule = 1206; EndCmp -BeginCmp -TimeStamp = /4C9E2B0F/4C9E2DF7; -Reference = C119; -ValeurCmp = 100nF; -IdModule = 0402; -EndCmp - BeginCmp TimeStamp = /4C9E2B0F/4C9E2B85; Reference = C120; @@ -819,20 +812,6 @@ ValeurCmp = 10nF; IdModule = 0402; EndCmp -BeginCmp -TimeStamp = /4C9E2B0F/4C9E2DF3; -Reference = C122; -ValeurCmp = 10nF; -IdModule = 0402; -EndCmp - -BeginCmp -TimeStamp = /4C9E2B0F/4C9E2DDB; -Reference = C123; -ValeurCmp = 100nF; -IdModule = 0402; -EndCmp - BeginCmp TimeStamp = /4C9E2B0F/4C9E2B81; Reference = C124; @@ -847,13 +826,6 @@ ValeurCmp = 22pF; IdModule = 0402; EndCmp -BeginCmp -TimeStamp = /4C9E2B0F/4C9E2DE4; -Reference = C126; -ValeurCmp = 10uF; -IdModule = 1206; -EndCmp - BeginCmp TimeStamp = /4C9E2B0F/4C9E2B82; Reference = C127; @@ -980,6 +952,55 @@ ValeurCmp = 10uF; IdModule = 1206; EndCmp +BeginCmp +TimeStamp = /4C716A4D/4CB9D312; +Reference = C145; +ValeurCmp = 4.7nF; +IdModule = 1206; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DE29; +Reference = C146; +ValeurCmp = 47pF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DE25; +Reference = C147; +ValeurCmp = 47pF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C9AD; +Reference = C148; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C965; +Reference = C149; +ValeurCmp = 33nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9D9A7; +Reference = C150; +ValeurCmp = 10uF; +IdModule = 0603; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C996; +Reference = C151; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + BeginCmp TimeStamp = /4C5F1EDC/4C5F2B55; Reference = F1; @@ -987,6 +1008,27 @@ ValeurCmp = MICROSMD075F; IdModule = 1210; EndCmp +BeginCmp +TimeStamp = /4C716A4D/4CB9CA50; +Reference = FB1; +ValeurCmp = FILTER; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9E17F; +Reference = FB2; +ValeurCmp = FILTER; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C4D7; +Reference = IC1; +ValeurCmp = FT2232D; +IdModule = LQFP48; +EndCmp + BeginCmp TimeStamp = /4C4227FE/4B76F5E2; Reference = J1; @@ -1009,15 +1051,15 @@ IdModule = USB-48204; EndCmp BeginCmp -TimeStamp = /4C716A4D/4C716CAB; -Reference = J6; -ValeurCmp = CONN_8X2; -IdModule = pin_array_8x2; +TimeStamp = /4C5F1EDC/4C75F027; +Reference = J7; +ValeurCmp = ZX62D-B-5P8; +IdModule = ZX62D-B-5P8; EndCmp BeginCmp -TimeStamp = /4C5F1EDC/4C75F027; -Reference = J7; +TimeStamp = /4C716A4D/4CB9D311; +Reference = J8; ValeurCmp = ZX62D-B-5P8; IdModule = ZX62D-B-5P8; EndCmp @@ -1100,10 +1142,10 @@ IdModule = M12-TU400A; EndCmp BeginCmp -TimeStamp = /4C69ED5F/4C7FD562; -Reference = P1; -ValeurCmp = AVR/PROG; -IdModule = PIN_ARRAY_5x1; +TimeStamp = /4CB0D95D/4CB0D9BF; +Reference = P2; +ValeurCmp = CONN_20X2; +IdModule = header20x2_smd_100mil; EndCmp BeginCmp @@ -1582,6 +1624,62 @@ ValeurCmp = R; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C716A4D/4CB9D313; +Reference = R69; +ValeurCmp = 1M; +IdModule = 1206; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C8F1; +Reference = R70; +ValeurCmp = 27; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C8F8; +Reference = R71; +ValeurCmp = 27; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C8D7; +Reference = R72; +ValeurCmp = 1.5K; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C8E1; +Reference = R73; +ValeurCmp = 10K; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C9A3; +Reference = R74; +ValeurCmp = 470; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C8A1; +Reference = R75; +ValeurCmp = 10K; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9C8AC; +Reference = R76; +ValeurCmp = 10K; +IdModule = 0402; +EndCmp + BeginCmp TimeStamp = /4C7BC2A2/4C69C6B2; Reference = RP1; @@ -1708,6 +1806,118 @@ ValeurCmp = R_PACK4; IdModule = R_PACK4-0402; EndCmp +BeginCmp +TimeStamp = /4C716A4D/4CB9DD95; +Reference = TP1; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD94; +Reference = TP2; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD92; +Reference = TP3; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD93; +Reference = TP4; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD99; +Reference = TP5; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD9A; +Reference = TP6; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD9C; +Reference = TP7; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD9B; +Reference = TP8; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD5B; +Reference = TP9; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD67; +Reference = TP10; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD7D; +Reference = TP11; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DD7C; +Reference = TP12; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DDA3; +Reference = TP13; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DDA2; +Reference = TP14; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DDA0; +Reference = TP15; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + +BeginCmp +TimeStamp = /4C716A4D/4CB9DDA1; +Reference = TP16; +ValeurCmp = CONN_1; +IdModule = TP40R; +EndCmp + BeginCmp TimeStamp = /4C7BC2B2/4C431E53; Reference = U1; @@ -1848,13 +2058,6 @@ ValeurCmp = TPS793XX; IdModule = SOT23_6; EndCmp -BeginCmp -TimeStamp = /4C9E2B0F/4C9E2DCC; -Reference = U21; -ValeurCmp = REG102; -IdModule = SOT23-5; -EndCmp - BeginCmp TimeStamp = /4C9E2B0F/4C9E2B80; Reference = U22; @@ -1904,4 +2107,11 @@ ValeurCmp = V0402MHS03; IdModule = 0603; EndCmp +BeginCmp +TimeStamp = /4C716A4D/4CB9DDF8; +Reference = X1; +ValeurCmp = 6MHz; +IdModule = CRYSTAL; +EndCmp + EndListe diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 14a9448..75e5e34 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,69 +1,69 @@ -# EESchema Netlist Version 1.1 created Tue 12 Oct 2010 10:03:14 PM COT +# EESchema Netlist Version 1.1 created Sat 16 Oct 2010 12:53:00 PM COT ( ( /4CB0D95D/4CB0D9BF header20x2_smd_100mil P2 CONN_20X2 {Lib=CONN_20X2} - ( 1 /FPGA_GPIOS/FPGA_BANK0_IO_8 ) + ( 1 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8 ) ( 2 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1 ) ( 3 /FPGA_GPIOS/FPGA_BANK0_IO_16 ) ( 4 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9 ) - ( 5 /FPGA_GPIOS/FPGA_BANK0_IO_0 ) + ( 5 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_0 ) ( 6 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14 ) - ( 7 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_10 ) + ( 7 /FPGA_GPIOS/FPGA_BANK0_IO_10 ) ( 8 /FPGA_GPIOS/FPGA_BANK0_IO_15 ) - ( 9 /FPGA_GPIOS/FPGA_BANK0_IO_11 ) + ( 9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11 ) ( 10 /FPGA_GPIOS/FPGA_BANK0_IO_3 ) ( 11 /FPGA_GPIOS/FPGA_BANK0_IO_5 ) - ( 12 /FPGA_GPIOS/FPGA_BANK0_IO_18 ) + ( 12 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_18 ) ( 13 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17 ) ( 14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21 ) - ( 15 /FPGA_GPIOS/FPGA_BANK0_IO_20 ) + ( 15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20 ) ( 16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24 ) ( 17 /FPGA_GPIOS/FPGA_BANK0_IO_28 ) - ( 18 /FPGA_GPIOS/FPGA_BANK0_IO_29 ) + ( 18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29 ) ( 19 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22 ) ( 20 /FPGA_GPIOS/FPGA_BANK0_IO_30 ) ( 21 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_27 ) - ( 22 /FPGA_GPIOS/FPGA_BANK0_IO_25 ) - ( 23 /FPGA_GPIOS/FPGA_BANK0_IO_39 ) + ( 22 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_25 ) + ( 23 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39 ) ( 24 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33 ) - ( 25 /FPGA_GPIOS/FPGA_BANK0_IO_2 ) - ( 26 /FPGA_GPIOS/FPGA_BANK0_IO_32 ) + ( 25 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_2 ) + ( 26 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32 ) ( 27 /FPGA_GPIOS/FPGA_BANK0_IO_7 ) ( 28 /FPGA_GPIOS/FPGA_BANK0_IO_6 ) - ( 29 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12 ) + ( 29 /FPGA_GPIOS/FPGA_BANK0_IO_12 ) ( 30 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36 ) ( 31 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_44 ) ( 32 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_40 ) ( 33 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47 ) ( 34 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_43 ) ( 35 /FPGA_GPIOS/FPGA_BANK0_IO_45 ) - ( 36 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46 ) + ( 36 /FPGA_GPIOS/FPGA_BANK0_IO_46 ) ( 37 /FPGA_GPIOS/FPGA_BANK0_IO_52 ) - ( 38 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50 ) - ( 39 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56 ) - ( 40 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48 ) + ( 38 /FPGA_GPIOS/FPGA_BANK0_IO_50 ) + ( 39 /FPGA_GPIOS/FPGA_BANK0_IO_56 ) + ( 40 /FPGA_GPIOS/FPGA_BANK0_IO_48 ) ) ( /4C9E2AF4/4CAF29D5 $noname MP1 M12-TU400A {Lib=M12-TU400A} ( 1 ? ) ( 2 ? ) ) ( /4C9E2AF4/4C9E3C76 $noname C140 100nF {Lib=C} - ( 1 /Image_Sensor/+2.8_VDDIO ) + ( 1 /Snesor_PSU/+2.8_VDDIO ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C71 $noname C142 100nF {Lib=C} - ( 1 /Image_Sensor/+2.8_VDDIO ) + ( 1 /Snesor_PSU/+2.8_VDDIO ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C70 $noname C144 10uF {Lib=CAPAPOL} - ( 1 /Image_Sensor/+2.8_VDDIO ) + ( 1 /Snesor_PSU/+2.8_VDDIO ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C6F $noname C143 100nF {Lib=C} - ( 1 /Image_Sensor/+2.8_VDDIO ) + ( 1 /Snesor_PSU/+2.8_VDDIO ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C6E $noname C141 100nF {Lib=C} - ( 1 /Image_Sensor/+2.8_VDDIO ) + ( 1 /Snesor_PSU/+2.8_VDDIO ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C65 $noname C136 100nF {Lib=C} @@ -83,98 +83,98 @@ ( 2 GND ) ) ( /4C9E2AF4/4C9E3C32 $noname C133 100nF {Lib=C} - ( 1 /Image_Sensor/+2.8_VAA ) + ( 1 /Snesor_PSU/+2.8_VAA ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C2E $noname C135 10uF {Lib=CAPAPOL} - ( 1 /Image_Sensor/+2.8_VAA ) + ( 1 /Snesor_PSU/+2.8_VAA ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C2D $noname C134 100nF {Lib=C} - ( 1 /Image_Sensor/+2.8_VAA ) + ( 1 /Snesor_PSU/+2.8_VAA ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C27 $noname C131 100nF {Lib=C} - ( 1 /Image_Sensor/+2.8_VAAPIX ) + ( 1 /Snesor_PSU/+2.8_VAAPIX ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C26 $noname C132 10uF {Lib=CAPAPOL} - ( 1 /Image_Sensor/+2.8_VAAPIX ) + ( 1 /Snesor_PSU/+2.8_VAAPIX ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C04 $noname C130 10uF {Lib=CAPAPOL} - ( 1 /Image_Sensor/+2.8_VDDPLL ) + ( 1 /Snesor_PSU/+2.8_VDDPLL ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3C00 $noname C129 100nF {Lib=C} - ( 1 /Image_Sensor/+2.8_VDDPLL ) + ( 1 /Snesor_PSU/+2.8_VDDPLL ) ( 2 GND ) ) ( /4C9E2AF4/4C9E3B7C $noname U24 MT9M033 {Lib=MT9M033} - ( 1 /Image_Sensor/IS_DOUT4 ) - ( 2 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5 ) + ( 1 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT4 ) + ( 2 /Image_Sensor/IS_DOUT5 ) ( 3 /Image_Sensor/IS_DOUT6 ) - ( 4 /Image_Sensor/+2.8_VDDPLL ) + ( 4 /Snesor_PSU/+2.8_VDDPLL ) ( 5 /FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK ) ( 6 GND ) ( 7 /Image_Sensor/IS_DOUT7 ) - ( 8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8 ) - ( 9 /Image_Sensor/IS_DOUT9 ) + ( 8 /Image_Sensor/IS_DOUT8 ) + ( 9 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9 ) ( 10 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT10 ) ( 11 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11 ) - ( 12 /Image_Sensor/+2.8_VDDIO ) - ( 13 /Image_Sensor/IS_PIXEL ) + ( 12 /Snesor_PSU/+2.8_VDDIO ) + ( 13 /FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL ) ( 14 /Image_Sensor/+1.8_VDD ) ( 15 /FPGA,_Port0,_Port2,_PROG_IF/IS_SCL ) ( 16 /Image_Sensor/IS_SDA ) ( 17 /Image_Sensor/IS_RESET_N ) - ( 18 /Image_Sensor/+2.8_VDDIO ) + ( 18 /Snesor_PSU/+2.8_VDDIO ) ( 19 /Image_Sensor/+1.8_VDD ) ( 20 ? ) ( 21 ? ) - ( 22 /FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY ) + ( 22 /Image_Sensor/IS_STANDBY ) ( 23 /Image_Sensor/IS_OE_N ) ( 24 /Image_Sensor/IS_I2C_ADDR ) - ( 25 /FPGA,_Port0,_Port2,_PROG_IF/IS_TEST ) + ( 25 /Image_Sensor/IS_TEST ) ( 26 /FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH ) ( 27 /FPGA,_Port0,_Port2,_PROG_IF/IS_TRIGGER ) - ( 28 /FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME ) - ( 29 /FPGA,_Port0,_Port2,_PROG_IF/IS_LINE ) + ( 28 /Image_Sensor/IS_FRAME ) + ( 29 /Image_Sensor/IS_LINE ) ( 30 GND ) ( 31 ? ) ( 32 ? ) ( 33 ? ) - ( 34 /Image_Sensor/+2.8_VAA ) + ( 34 /Snesor_PSU/+2.8_VAA ) ( 35 GND ) - ( 36 /Image_Sensor/+2.8_VAA ) - ( 37 /Image_Sensor/+2.8_VAAPIX ) - ( 38 /Image_Sensor/+2.8_VAAPIX ) + ( 36 /Snesor_PSU/+2.8_VAA ) + ( 37 /Snesor_PSU/+2.8_VAAPIX ) + ( 38 /Snesor_PSU/+2.8_VAAPIX ) ( 39 GND ) - ( 40 /Image_Sensor/+2.8_VAA ) + ( 40 /Snesor_PSU/+2.8_VAA ) ( 41 ? ) ( 42 ? ) ( 43 ? ) ( 44 GND ) - ( 45 /Image_Sensor/IS_DOUT0 ) + ( 45 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0 ) ( 46 /Image_Sensor/IS_DOUT1 ) ( 47 /Image_Sensor/IS_DOUT2 ) - ( 48 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3 ) + ( 48 /Image_Sensor/IS_DOUT3 ) ) ( /4C9E2B0F/4C9E2BAA $noname C107 10uF {Lib=CAPAPOL} - ( 1 N-000428 ) + ( 1 N-000467 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2BA9 $noname C110 10nF {Lib=C} - ( 1 N-000430 ) + ( 1 N-000469 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2BA8 $noname R64 R {Lib=R} - ( 1 N-000431 ) + ( 1 N-000470 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2BA7 $noname R63 R {Lib=R} ( 1 /Image_Sensor/+1.8_VDD ) - ( 2 N-000431 ) + ( 2 N-000470 ) ) ( /4C9E2B0F/4C9E2BA6 $noname C116 10uF {Lib=CAPAPOL} ( 1 /Image_Sensor/+1.8_VDD ) @@ -182,143 +182,143 @@ ) ( /4C9E2B0F/4C9E2BA5 $noname C113 22pF {Lib=C} ( 1 /Image_Sensor/+1.8_VDD ) - ( 2 N-000431 ) + ( 2 N-000470 ) ) ( /4C9E2B0F/4C9E2BA4 $noname U20 TPS793XX {Lib=TPS793XX} - ( 1 N-000428 ) + ( 1 N-000467 ) ( 2 GND ) - ( 3 N-000428 ) - ( 4 N-000430 ) - ( 5 N-000431 ) + ( 3 N-000467 ) + ( 4 N-000469 ) + ( 5 N-000470 ) ( 6 /Image_Sensor/+1.8_VDD ) ) ( /4C9E2B0F/4C9E2B96 $noname U23 TPS793XX {Lib=TPS793XX} - ( 1 N-000423 ) + ( 1 N-000462 ) ( 2 GND ) - ( 3 N-000423 ) - ( 4 N-000429 ) - ( 5 N-000424 ) - ( 6 /Image_Sensor/+2.8_VDDPLL ) + ( 3 N-000462 ) + ( 4 N-000468 ) + ( 5 N-000463 ) + ( 6 /Snesor_PSU/+2.8_VDDPLL ) ) ( /4C9E2B0F/4C9E2B95 $noname C125 22pF {Lib=C} - ( 1 /Image_Sensor/+2.8_VDDPLL ) - ( 2 N-000424 ) + ( 1 /Snesor_PSU/+2.8_VDDPLL ) + ( 2 N-000463 ) ) ( /4C9E2B0F/4C9E2B94 $noname C128 10uF {Lib=CAPAPOL} - ( 1 /Image_Sensor/+2.8_VDDPLL ) + ( 1 /Snesor_PSU/+2.8_VDDPLL ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B93 $noname R67 R {Lib=R} - ( 1 /Image_Sensor/+2.8_VDDPLL ) - ( 2 N-000424 ) + ( 1 /Snesor_PSU/+2.8_VDDPLL ) + ( 2 N-000463 ) ) ( /4C9E2B0F/4C9E2B92 $noname R68 R {Lib=R} - ( 1 N-000424 ) + ( 1 N-000463 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B91 $noname C121 10nF {Lib=C} - ( 1 N-000429 ) + ( 1 N-000468 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B90 $noname C118 10uF {Lib=CAPAPOL} - ( 1 N-000423 ) + ( 1 N-000462 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B86 $noname C117 10uF {Lib=CAPAPOL} - ( 1 N-000422 ) + ( 1 N-000461 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B85 $noname C120 10nF {Lib=C} - ( 1 N-000426 ) + ( 1 N-000465 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B84 $noname R66 R {Lib=R} - ( 1 N-000427 ) + ( 1 N-000466 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B83 $noname R65 R {Lib=R} - ( 1 /Image_Sensor/+2.8_VDDIO ) - ( 2 N-000427 ) + ( 1 /Snesor_PSU/+2.8_VDDIO ) + ( 2 N-000466 ) ) ( /4C9E2B0F/4C9E2B82 $noname C127 10uF {Lib=CAPAPOL} - ( 1 /Image_Sensor/+2.8_VDDIO ) + ( 1 /Snesor_PSU/+2.8_VDDIO ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B81 $noname C124 22pF {Lib=C} - ( 1 /Image_Sensor/+2.8_VDDIO ) - ( 2 N-000427 ) + ( 1 /Snesor_PSU/+2.8_VDDIO ) + ( 2 N-000466 ) ) ( /4C9E2B0F/4C9E2B80 $noname U22 TPS793XX {Lib=TPS793XX} - ( 1 N-000422 ) + ( 1 N-000461 ) ( 2 GND ) - ( 3 N-000422 ) - ( 4 N-000426 ) - ( 5 N-000427 ) - ( 6 /Image_Sensor/+2.8_VDDIO ) + ( 3 N-000461 ) + ( 4 N-000465 ) + ( 5 N-000466 ) + ( 6 /Snesor_PSU/+2.8_VDDIO ) ) ( /4C9E2B0F/4C9E2B72 $noname U19 TPS793XX {Lib=TPS793XX} - ( 1 N-000434 ) + ( 1 N-000473 ) ( 2 GND ) - ( 3 N-000434 ) - ( 4 N-000425 ) - ( 5 N-000435 ) - ( 6 /Image_Sensor/+2.8_VAAPIX ) + ( 3 N-000473 ) + ( 4 N-000464 ) + ( 5 N-000474 ) + ( 6 /Snesor_PSU/+2.8_VAAPIX ) ) ( /4C9E2B0F/4C9E2B71 $noname C112 22pF {Lib=C} - ( 1 /Image_Sensor/+2.8_VAAPIX ) - ( 2 N-000435 ) + ( 1 /Snesor_PSU/+2.8_VAAPIX ) + ( 2 N-000474 ) ) ( /4C9E2B0F/4C9E2B70 $noname C115 10uF {Lib=CAPAPOL} - ( 1 /Image_Sensor/+2.8_VAAPIX ) + ( 1 /Snesor_PSU/+2.8_VAAPIX ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B6F $noname R61 R {Lib=R} - ( 1 /Image_Sensor/+2.8_VAAPIX ) - ( 2 N-000435 ) + ( 1 /Snesor_PSU/+2.8_VAAPIX ) + ( 2 N-000474 ) ) ( /4C9E2B0F/4C9E2B6E $noname R62 R {Lib=R} - ( 1 N-000435 ) + ( 1 N-000474 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B6D $noname C109 10nF {Lib=C} - ( 1 N-000425 ) + ( 1 N-000464 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2B6C $noname C106 10uF {Lib=CAPAPOL} - ( 1 N-000434 ) + ( 1 N-000473 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E28CB $noname C105 10uF {Lib=CAPAPOL} - ( 1 N-000432 ) + ( 1 N-000471 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E28C1 $noname C108 10nF {Lib=C} - ( 1 N-000433 ) + ( 1 N-000472 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E289D $noname R60 R {Lib=R} - ( 1 N-000436 ) + ( 1 N-000475 ) ( 2 GND ) ) ( /4C9E2B0F/4C9E287F $noname R59 R {Lib=R} - ( 1 /Image_Sensor/+2.8_VAA ) - ( 2 N-000436 ) + ( 1 /Snesor_PSU/+2.8_VAA ) + ( 2 N-000475 ) ) ( /4C9E2B0F/4C9E286D $noname C114 10uF {Lib=CAPAPOL} - ( 1 /Image_Sensor/+2.8_VAA ) + ( 1 /Snesor_PSU/+2.8_VAA ) ( 2 GND ) ) ( /4C9E2B0F/4C9E2857 $noname C111 22pF {Lib=C} - ( 1 /Image_Sensor/+2.8_VAA ) - ( 2 N-000436 ) + ( 1 /Snesor_PSU/+2.8_VAA ) + ( 2 N-000475 ) ) ( /4C9E2B0F/4C9E2848 $noname U18 TPS793XX {Lib=TPS793XX} - ( 1 N-000432 ) + ( 1 N-000471 ) ( 2 GND ) - ( 3 N-000432 ) - ( 4 N-000433 ) - ( 5 N-000436 ) - ( 6 /Image_Sensor/+2.8_VAA ) + ( 3 N-000471 ) + ( 4 N-000472 ) + ( 5 N-000475 ) + ( 6 /Snesor_PSU/+2.8_VAA ) ) ( /4C7BC2B2/4C749A0C 0402 C94 470nF {Lib=C} ( 1 +2.5V ) @@ -342,11 +342,11 @@ ) ( /4C7BC2B2/4C7168DD 0402 R30 330 {Lib=R} ( 1 +3.3V ) - ( 2 N-000376 ) + ( 2 N-000415 ) ) ( /4C7BC2B2/4C716877 0402 R29 4.7k {Lib=R} ( 1 +3.3V ) - ( 2 N-000379 ) + ( 2 N-000418 ) ) ( /4C7BC2B2/4C6B29DA 0402 C77 470nF {Lib=C} ( 1 +2.5V ) @@ -377,27 +377,27 @@ ( 2 GND ) ) ( /4C7BC2B2/4C656D53 $noname C69 470nF {Lib=C} - ( 1 N-000115 ) + ( 1 N-000099 ) ( 2 GND ) ) ( /4C7BC2B2/4C656D49 $noname C67 470nF {Lib=C} - ( 1 N-000115 ) + ( 1 N-000099 ) ( 2 GND ) ) ( /4C7BC2B2/4C656D46 $noname C64 470nF {Lib=C} - ( 1 N-000115 ) + ( 1 N-000099 ) ( 2 GND ) ) ( /4C7BC2B2/4C656D45 $noname C61 470nF {Lib=C} - ( 1 N-000115 ) + ( 1 N-000099 ) ( 2 GND ) ) ( /4C7BC2B2/4C656D44 $noname C58 4.7uF {Lib=C} - ( 1 N-000115 ) + ( 1 N-000099 ) ( 2 GND ) ) ( /4C7BC2B2/4C656D43 $noname C55 100uF {Lib=C} - ( 1 N-000115 ) + ( 1 N-000099 ) ( 2 GND ) ) ( /4C7BC2B2/4C656D08 $noname C68 470nF {Lib=C} @@ -542,32 +542,32 @@ ( H3 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK# ) ( G3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0 ) ( C13 ? ) - ( A13 /FPGA,_Port0,_Port2,_PROG_IF/NF_D2 ) - ( C12 /Non_volatile_memories/NF_D0 ) - ( B12 /Non_volatile_memories/NF_D3 ) + ( A13 /Non_volatile_memories/NF_D2 ) + ( C12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D0 ) + ( B12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D3 ) ( A12 /FPGA,_Port0,_Port2,_PROG_IF/NF_D4 ) - ( D11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D7 ) - ( C11 /Non_volatile_memories/NF_D5 ) + ( D11 /Non_volatile_memories/NF_D7 ) + ( C11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 ) ( B11 +3.3V ) ( A11 /FPGA,_Port0,_Port2,_PROG_IF/NF_D6 ) ( G10 +3.3V ) ( D10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 ) - ( C10 /Ethernet_Phy/ETH_TXD2 ) + ( C10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2 ) ( B10 /Ethernet_Phy/ETH_CRS ) - ( A10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_INT ) + ( A10 /Ethernet_Phy/ETH_INT ) ( E9 +3.3V ) - ( D9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN ) + ( D9 /Ethernet_Phy/ETH_TXEN ) ( C9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1 ) - ( A9 /FPGA,_Port0,_Port2,_PROG_IF/ETH_COL ) - ( D8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER ) - ( C8 /Ethernet_Phy/ETH_TXC ) - ( B8 /Ethernet_Phy/ETH_RXER ) - ( A8 /Ethernet_Phy/ETH_TXD3 ) - ( D7 /Ethernet_Phy/ETH_MDC ) + ( A9 /Ethernet_Phy/ETH_COL ) + ( D8 /Ethernet_Phy/ETH_TXER ) + ( C8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC ) + ( B8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER ) + ( A8 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3 ) + ( D7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC ) ( C7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RESET_N ) ( B7 +3.3V ) - ( A7 /Ethernet_Phy/ETH_RXC ) - ( D6 /Ethernet_Phy/ETH_MDIO ) + ( A7 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC ) + ( D6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO ) ( C6 /Ethernet_Phy/ETH_RXD2 ) ( B6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 ) ( A6 /Ethernet_Phy/ETH_RXDV ) @@ -583,7 +583,7 @@ ( B1 ? ) ( B19 +3.3V ) ( B18 /Non_volatile_memories/SD_DAT1 ) - ( A18 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0 ) + ( A18 /Non_volatile_memories/SD_DAT0 ) ( E17 +3.3V ) ( D17 ? ) ( C17 ? ) @@ -592,17 +592,17 @@ ( C16 /Non_volatile_memories/SD_CMD ) ( B16 /Non_volatile_memories/SD_DAT3 ) ( A16 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT2 ) - ( D15 /FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N ) - ( C15 /FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N ) + ( D15 /Non_volatile_memories/NF_CS1_N ) + ( C15 /Non_volatile_memories/NF_RE_N ) ( B15 +3.3V ) ( A15 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB ) ( G14 +3.3V ) ( D14 /FPGA,_Port0,_Port2,_PROG_IF/NF_D1 ) - ( C14 /FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N ) - ( B14 /FPGA,_Port0,_Port2,_PROG_IF/NF_CLE ) + ( C14 /Non_volatile_memories/NF_WE_N ) + ( B14 /Non_volatile_memories/NF_CLE ) ( A14 /Non_volatile_memories/NF_ALE ) ( E13 +3.3V ) - ( F17 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV ) + ( F17 /USB/USBA_RCV ) ( N16 ? ) ( M16 ? ) ( L16 +2.5V ) @@ -610,7 +610,7 @@ ( J16 ? ) ( H16 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS# ) ( G16 ? ) - ( F16 /USB/USBA_SPD ) + ( F16 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD ) ( L15 ? ) ( W22 ? ) ( V22 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15 ) @@ -640,12 +640,12 @@ ( M19 ? ) ( L19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM ) ( K19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A6 ) - ( J19 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK# ) + ( J19 /DDR_Banks/M1_CLK# ) ( H19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE# ) ( G19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10 ) ( F19 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11 ) ( E19 +2.5V ) - ( D19 /USB/USBA_VP ) + ( D19 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP ) ( C19 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N ) ( U18 +2.5V ) ( P18 ? ) @@ -662,7 +662,7 @@ ( J17 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0 ) ( H17 ? ) ( G17 ? ) - ( A20 /USB/USBD_RCV ) + ( A20 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV ) ( P8 ? ) ( M8 ? ) ( K8 ? ) @@ -720,9 +720,9 @@ ( G20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3 ) ( F20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A4 ) ( E20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A7 ) - ( D20 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VM ) + ( D20 /USB/USBA_VM ) ( C20 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8 ) - ( B20 /USB/USBD_SPD ) + ( B20 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD ) ( J14 +1.2V ) ( H14 ? ) ( F14 ? ) @@ -738,7 +738,7 @@ ( F13 ? ) ( D13 ? ) ( B13 GND ) - ( Y22 N-000376 ) + ( Y22 N-000415 ) ( A22 GND ) ( R12 +2.5V ) ( P12 GND ) @@ -759,7 +759,7 @@ ( G18 GND ) ( E18 /DBG_PRG/FPGA_TDI ) ( D18 GND ) - ( C18 /FPGA,_Port0,_Port2,_PROG_IF/S6_TMS ) + ( C18 /DBG_PRG/FPGA_TMS ) ( R17 ? ) ( N17 GND ) ( B17 GND ) @@ -773,7 +773,7 @@ ( K15 +2.5V ) ( J15 GND ) ( H15 +2.5V ) - ( G15 /DBG_PRG/FPGA_TCK ) + ( G15 /FPGA,_Port0,_Port2,_PROG_IF/S6_TCK ) ( F15 ? ) ( E15 GND ) ( V14 GND ) @@ -813,7 +813,7 @@ ( J2 GND ) ( E2 GND ) ( A1 GND ) - ( AA1 N-000379 ) + ( AA1 N-000418 ) ( U21 GND ) ( N21 GND ) ( J21 GND ) @@ -844,77 +844,77 @@ ( P9 +1.2V ) ( N9 GND ) ( M9 +1.2V ) - ( V19 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_10 ) - ( AB8 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT8 ) + ( V19 /FPGA_GPIOS/FPGA_BANK0_IO_10 ) + ( AB8 /Image_Sensor/IS_DOUT8 ) ( AA8 /Image_Sensor/IS_DOUT7 ) ( Y18 /FPGA_GPIOS/FPGA_BANK0_IO_5 ) ( W18 ? ) - ( V18 /FPGA_GPIOS/FPGA_BANK0_IO_11 ) + ( V18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_11 ) ( T18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_1 ) ( AB7 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT11 ) - ( AA7 N-000115 ) - ( Y17 /FPGA_GPIOS/FPGA_BANK0_IO_20 ) + ( AA7 N-000099 ) + ( Y17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_20 ) ( W17 /FPGA_GPIOS/FPGA_BANK0_IO_15 ) ( V17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_14 ) - ( U17 /FPGA_GPIOS/FPGA_BANK0_IO_8 ) - ( T17 /FPGA_GPIOS/FPGA_BANK0_IO_2 ) - ( AB6 /Image_Sensor/IS_PIXEL ) + ( U17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_8 ) + ( T17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_2 ) + ( AB6 /FPGA,_Port0,_Port2,_PROG_IF/IS_PIXEL ) ( AA6 /Image_Sensor/IS_SDA ) ( Y16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_24 ) - ( V16 N-000115 ) + ( V16 N-000099 ) ( U16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_9 ) ( T16 /FPGA_GPIOS/FPGA_BANK0_IO_6 ) - ( R16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_12 ) + ( R16 /FPGA_GPIOS/FPGA_BANK0_IO_12 ) ( AB5 /Image_Sensor/IS_RESET_N ) - ( Y15 /FPGA_GPIOS/FPGA_BANK0_IO_32 ) - ( W15 /FPGA_GPIOS/FPGA_BANK0_IO_25 ) + ( Y15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_32 ) + ( W15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_25 ) ( V15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_17 ) ( U15 /FPGA_GPIOS/FPGA_BANK0_IO_16 ) ( T15 /FPGA_GPIOS/FPGA_BANK0_IO_7 ) ( R15 ? ) ( AB4 /Image_Sensor/IS_I2C_ADDR ) - ( AA4 /FPGA,_Port0,_Port2,_PROG_IF/IS_TEST ) - ( C5 /Ethernet_Phy/ETH_RXD3 ) - ( A5 /Ethernet_Phy/ETH_RXD1 ) + ( AA4 /Image_Sensor/IS_TEST ) + ( C5 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3 ) + ( A5 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1 ) ( B4 +3.3V ) ( A4 /Ethernet_Phy/ETH_CLK ) ( A3 ? ) ( AB19 ? ) - ( AA19 N-000115 ) + ( AA19 N-000099 ) ( AB18 ? ) - ( AA18 /FPGA_GPIOS/FPGA_BANK0_IO_18 ) + ( AA18 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_18 ) ( AB17 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_21 ) - ( AB16 /FPGA_GPIOS/FPGA_BANK0_IO_29 ) + ( AB16 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_29 ) ( AA16 /FPGA_GPIOS/FPGA_BANK0_IO_28 ) ( AB15 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_33 ) - ( AA15 N-000115 ) + ( AA15 N-000099 ) ( AB14 ? ) ( AA14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_22 ) - ( AB13 /FPGA_GPIOS/FPGA_BANK0_IO_39 ) - ( AA22 /FPGA_GPIOS/FPGA_BANK0_IO_0 ) - ( AB12 /Image_Sensor/IS_DOUT0 ) + ( AB13 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_39 ) + ( AA22 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_0 ) + ( AB12 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT0 ) ( AA12 /Image_Sensor/IS_DOUT1 ) ( AB21 ? ) ( AA21 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK ) ( AB11 /Image_Sensor/IS_DOUT2 ) - ( AA11 N-000115 ) + ( AA11 N-000099 ) ( AB20 /Non_volatile_memories/SPI_DQ0 ) - ( AA20 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1 ) - ( AB10 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT3 ) - ( AA10 /Image_Sensor/IS_DOUT4 ) - ( AB9 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT5 ) + ( AA20 /Non_volatile_memories/SPI_DQ1 ) + ( AB10 /Image_Sensor/IS_DOUT3 ) + ( AA10 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT4 ) + ( AB9 /Image_Sensor/IS_DOUT5 ) ( Y19 /FPGA_GPIOS/FPGA_BANK0_IO_3 ) ( V9 /FPGA_GPIOS/FPGA_BANK0_IO_52 ) ( U9 ? ) - ( T9 N-000115 ) + ( T9 N-000099 ) ( R9 ? ) ( Y8 /Image_Sensor/IS_DOUT6 ) - ( W8 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_48 ) - ( V8 N-000115 ) + ( W8 /FPGA_GPIOS/FPGA_BANK0_IO_48 ) + ( V8 N-000099 ) ( U8 ? ) ( T8 ? ) ( R8 ? ) - ( Y7 /Image_Sensor/IS_DOUT9 ) + ( Y7 /FPGA,_Port0,_Port2,_PROG_IF/IS_DOUT9 ) ( V7 ? ) ( T7 ? ) ( R7 ? ) @@ -922,10 +922,10 @@ ( W6 ? ) ( U6 ? ) ( T6 ? ) - ( Y5 /FPGA,_Port0,_Port2,_PROG_IF/IS_STANDBY ) - ( W5 N-000115 ) + ( Y5 /Image_Sensor/IS_STANDBY ) + ( W5 N-000099 ) ( V5 ? ) - ( T5 /Non_volatile_memories/SPI_FLASH_CS# ) + ( T5 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO ) ( Y4 /Image_Sensor/IS_OE_N ) ( W4 ? ) ( Y3 /FPGA,_Port0,_Port2,_PROG_IF/IS_TRIGGER ) @@ -939,18 +939,18 @@ ( U14 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 ) ( T14 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_36 ) ( AB3 /FPGA,_Port0,_Port2,_PROG_IF/IS_FLASH ) - ( AA3 N-000115 ) + ( AA3 N-000099 ) ( Y13 ? ) ( W13 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_27 ) ( V13 ? ) ( U13 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3 ) - ( T13 N-000115 ) + ( T13 N-000099 ) ( R13 ? ) - ( AB2 /FPGA,_Port0,_Port2,_PROG_IF/IS_FRAME ) - ( AA2 /FPGA,_Port0,_Port2,_PROG_IF/IS_LINE ) + ( AB2 /Image_Sensor/IS_FRAME ) + ( AA2 /Image_Sensor/IS_LINE ) ( Y12 /FPGA,_Port0,_Port2,_PROG_IF/IS_SCL ) ( W12 /FPGA,_Port0,_Port2,_PROG_IF/IS_EXTCLK ) - ( V12 N-000115 ) + ( V12 N-000099 ) ( U12 ? ) ( T12 ? ) ( Y21 ? ) @@ -960,23 +960,23 @@ ( T11 ? ) ( R11 ? ) ( Y10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_47 ) - ( W10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_46 ) - ( U10 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_56 ) + ( W10 /FPGA_GPIOS/FPGA_BANK0_IO_46 ) + ( U10 /FPGA_GPIOS/FPGA_BANK0_IO_56 ) ( T10 ? ) ( Y9 /FPGA_GPIOS/FPGA_BANK0_IO_45 ) - ( W9 /FPGA,_Port0,_Port2,_PROG_IF/FPGA_BANK0_IO_50 ) + ( W9 /FPGA_GPIOS/FPGA_BANK0_IO_50 ) ) ( /4C7BC2A2/4C6B216E 0402 R23 33 {Lib=R} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDM ) - ( 2 /DDR_Banks/M0_UDM ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM ) ) ( /4C7BC2A2/4C6B216D 0402 R22 33 {Lib=R} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_UDQS ) - ( 2 /DDR_Banks/M0_UDQS ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS ) ) ( /4C7BC2A2/4C6B216B 0402 R24 33 {Lib=R} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CKE ) - ( 2 /DDR_Banks/M0_CKE ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE ) ) ( /4C7BC2A2/4C6B1B90 0402 R21 120 {Lib=R} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK ) @@ -989,38 +989,38 @@ ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A3 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A3 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A2 ) - ( 7 /DDR_Banks/M0_A1 ) - ( 8 /DDR_Banks/M0_A0 ) + ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A1 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A0 ) ) ( /4C7BC2A2/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_RAS# ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA0 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_BA1 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A10 ) - ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A10 ) - ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1 ) + ( 5 /DDR_Banks/M0_A10 ) + ( 6 /DDR_Banks/M0_BA1 ) ( 7 /DDR_Banks/M0_BA0 ) - ( 8 /DDR_Banks/M0_RAS# ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS# ) ) ( /4C7BC2A2/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDQS ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_LDM ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_WE# ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_CAS# ) - ( 5 /DDR_Banks/M0_CAS# ) - ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_WE# ) - ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_LDM ) - ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS ) + ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS# ) + ( 6 /DDR_Banks/M0_WE# ) + ( 7 /DDR_Banks/M0_LDM ) + ( 8 /DDR_Banks/M0_LDQS ) ) ( /4C7BC2A2/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A7 ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A6 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A5 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A4 ) - ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A4 ) - ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A5 ) - ( 7 /DDR_Banks/M0_A6 ) - ( 8 /DDR_Banks/M0_A7 ) + ( 5 /DDR_Banks/M0_A4 ) + ( 6 /DDR_Banks/M0_A5 ) + ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A6 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A7 ) ) ( /4C7BC2A2/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_A12 ) @@ -1030,7 +1030,7 @@ ( 5 /DDR_Banks/M0_A8 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A9 ) ( 7 /DDR_Banks/M0_A11 ) - ( 8 /DDR_Banks/M0_A12 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A12 ) ) ( /4C7BC2A2/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ4 ) @@ -1039,8 +1039,8 @@ ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ7 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6 ) - ( 7 /DDR_Banks/M0_DQ5 ) - ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4 ) + ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5 ) + ( 8 /DDR_Banks/M0_DQ4 ) ) ( /4C7BC2A2/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ0 ) @@ -1050,7 +1050,7 @@ ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2 ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1 ) - ( 8 /DDR_Banks/M0_DQ0 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0 ) ) ( /4C7BC2A2/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ8 ) @@ -1058,65 +1058,65 @@ ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ10 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ11 ) ( 5 /DDR_Banks/M0_DQ11 ) - ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10 ) - ( 7 /DDR_Banks/M0_DQ9 ) - ( 8 /DDR_Banks/M0_DQ8 ) + ( 6 /DDR_Banks/M0_DQ10 ) + ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8 ) ) ( /4C7BC2A2/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ12 ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ13 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ14 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M0_DQ15 ) - ( 5 /DDR_Banks/M0_DQ15 ) + ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14 ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13 ) - ( 8 /DDR_Banks/M0_DQ12 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12 ) ) ( /4C7BC2A2/4C69E7DD 0402 R19 33 {Lib=R} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDQS ) - ( 2 /DDR_Banks/M1_UDQS ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS ) ) ( /4C7BC2A2/4C69E92D 0402 R20 33 {Lib=R} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CS# ) - ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CS# ) + ( 2 /DDR_Banks/M1_CS# ) ) ( /4C7BC2A2/4C69E7F8 0402 R17 33 {Lib=R} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CKE ) - ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE ) + ( 2 /DDR_Banks/M1_CKE ) ) ( /4C7BC2A2/4C69E7C2 0402 R18 33 {Lib=R} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_UDM ) - ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDM ) + ( 2 /DDR_Banks/M1_UDM ) ) ( /4C7BC2A2/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11 ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10 ) ( 3 /DDR_Banks/M1_DQ9 ) - ( 4 /DDR_Banks/M1_DQ8 ) + ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ8 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ9 ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ10 ) ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ11 ) ) ( /4C7BC2A2/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} - ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15 ) + ( 1 /DDR_Banks/M1_DQ15 ) ( 2 /DDR_Banks/M1_DQ14 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13 ) - ( 4 /DDR_Banks/M1_DQ12 ) + ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ12 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ13 ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ14 ) ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ15 ) ) ( /4C7BC2A2/4C69DF7A 0402 R16 120 {Lib=R} - ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK# ) + ( 1 /DDR_Banks/M1_CLK# ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK ) ) ( /4C7BC2A2/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A12 ) ( 2 /DDR_Banks/M1_A11 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A9 ) - ( 4 /DDR_Banks/M1_A8 ) + ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A8 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A8 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A9 ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A11 ) @@ -1147,64 +1147,221 @@ ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_LDM ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_WE# ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_CAS# ) - ( 5 /DDR_Banks/M1_CAS# ) + ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS# ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_WE# ) ( 7 /DDR_Banks/M1_LDM ) - ( 8 /DDR_Banks/M1_LDQS ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDQS ) ) ( /4C7BC2A2/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ4 ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ5 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ6 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_DQ7 ) - ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7 ) + ( 5 /DDR_Banks/M1_DQ7 ) ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6 ) - ( 7 /DDR_Banks/M1_DQ5 ) - ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4 ) + ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5 ) + ( 8 /DDR_Banks/M1_DQ4 ) ) ( /4C7BC2A2/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_RAS# ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA0 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_BA1 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A10 ) - ( 5 /DDR_Banks/M1_A10 ) - ( 6 /DDR_Banks/M1_BA1 ) - ( 7 /DDR_Banks/M1_BA0 ) - ( 8 /DDR_Banks/M1_RAS# ) + ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A10 ) + ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1 ) + ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS# ) ) ( /4C7BC2A2/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A0 ) ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A1 ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A2 ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/R_M1_A3 ) - ( 5 /DDR_Banks/M1_A3 ) - ( 6 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A2 ) + ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A3 ) + ( 6 /DDR_Banks/M1_A2 ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A1 ) - ( 8 /DDR_Banks/M1_A0 ) + ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A0 ) ) - ( /4C716A4D/4C716CAB $noname J6 CONN_8X2 {Lib=CONN_8X2} - ( 1 /DBG_PRG/FPGA_TCK ) - ( 2 ? ) - ( 3 /FPGA,_Port0,_Port2,_PROG_IF/S6_TMS ) - ( 4 ? ) - ( 5 /FPGA,_Port0,_Port2,_PROG_IF/S6_TDO ) - ( 6 ? ) - ( 7 /DBG_PRG/FPGA_TDI ) - ( 8 ? ) - ( 9 ? ) - ( 10 ? ) + ( /4C716A4D/4CB9E17F $noname FB2 FILTER {Lib=FILTER} + ( 1 /DBG_PRG/5V_USB ) + ( 2 /DBG_PRG/VCC_USB ) + ) + ( /4C716A4D/4CB9DE29 $noname C146 47pF {Lib=C} + ( 1 N-000226 ) + ( 2 GND ) + ) + ( /4C716A4D/4CB9DE25 $noname C147 47pF {Lib=C} + ( 1 N-000208 ) + ( 2 GND ) + ) + ( /4C716A4D/4CB9DDF8 $noname X1 6MHz {Lib=CRYSTAL} + ( 1 N-000226 ) + ( 2 N-000208 ) + ) + ( /4C716A4D/4CB9DDA3 $noname TP13 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DDA2 $noname TP14 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DDA1 $noname TP16 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DDA0 $noname TP15 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD9C $noname TP7 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD9B $noname TP8 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD9A $noname TP6 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD99 $noname TP5 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD95 $noname TP1 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD94 $noname TP2 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD93 $noname TP4 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD92 $noname TP3 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD7D $noname TP11 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD7C $noname TP12 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD67 $noname TP10 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9DD5B $noname TP9 CONN_1 {Lib=CONN_1} + ( 1 ? ) + ) + ( /4C716A4D/4CB9D9A7 $noname C150 10uF {Lib=CAPAPOL} + ( 1 /DBG_PRG/VCC_USB ) + ( 2 GND ) + ) + ( /4C716A4D/4CB9D313 $noname R69 1M {Lib=R} + ( 1 /DBG_PRG/USB_CASE_FTDI ) + ( 2 GND ) + ) + ( /4C716A4D/4CB9D312 $noname C145 4.7nF {Lib=C} + ( 1 /DBG_PRG/USB_CASE_FTDI ) + ( 2 GND ) + ) + ( /4C716A4D/4CB9D311 ZX62D-B-5P8 J8 ZX62D-B-5P8 {Lib=ZX62D-B-5P8} + ( 1 /DBG_PRG/5V_USB ) + ( 2 /DBG_PRG/FTDI_USB_DM ) + ( 3 /DBG_PRG/FTDI_USB_DP ) + ( 4 N-000229 ) + ( 5 N-000229 ) + ( 6 /DBG_PRG/USB_CASE_FTDI ) + ( 7 /DBG_PRG/USB_CASE_FTDI ) + ( 8 /DBG_PRG/USB_CASE_FTDI ) + ( 9 /DBG_PRG/USB_CASE_FTDI ) + ) + ( /4C716A4D/4CB9CA50 $noname FB1 FILTER {Lib=FILTER} + ( 1 N-000229 ) + ( 2 GND ) + ) + ( /4C716A4D/4CB9C9AD $noname C148 100nF {Lib=C} + ( 1 /DBG_PRG/5V_USB ) + ( 2 GND ) + ) + ( /4C716A4D/4CB9C9A3 $noname R74 470 {Lib=R} + ( 1 /DBG_PRG/VCC_USB ) + ( 2 N-000231 ) + ) + ( /4C716A4D/4CB9C996 $noname C151 100nF {Lib=C} + ( 1 N-000231 ) + ( 2 GND ) + ) + ( /4C716A4D/4CB9C965 $noname C149 33nF {Lib=C} + ( 1 GND ) + ( 2 /DBG_PRG/3.3V_USB ) + ) + ( /4C716A4D/4CB9C8F8 $noname R71 27 {Lib=R} + ( 1 N-000236 ) + ( 2 /DBG_PRG/FTDI_USB_DP ) + ) + ( /4C716A4D/4CB9C8F1 $noname R70 27 {Lib=R} + ( 1 N-000235 ) + ( 2 /DBG_PRG/FTDI_USB_DM ) + ) + ( /4C716A4D/4CB9C8E1 $noname R73 10K {Lib=R} + ( 1 N-000233 ) + ( 2 /DBG_PRG/VCC_USB ) + ) + ( /4C716A4D/4CB9C8D7 $noname R72 1.5K {Lib=R} + ( 1 N-000234 ) + ( 2 N-000236 ) + ) + ( /4C716A4D/4CB9C8AC $noname R76 10K {Lib=R} + ( 1 +3.3V ) + ( 2 N-000237 ) + ) + ( /4C716A4D/4CB9C8A1 $noname R75 10K {Lib=R} + ( 1 +3.3V ) + ( 2 N-000232 ) + ) + ( /4C716A4D/4CB9C4D7 ft2232c-LQFP IC1 FT2232D {Lib=FT2232C} + ( 1 ? ) + ( 2 N-000233 ) + ( 3 /DBG_PRG/VCC_USB ) + ( 4 /DBG_PRG/VCC_USB ) + ( 5 N-000234 ) + ( 6 /DBG_PRG/3.3V_USB ) + ( 7 N-000236 ) + ( 8 N-000235 ) + ( 9 GND ) + ( 10 N-000232 ) ( 11 ? ) ( 12 ? ) ( 13 ? ) - ( 14 ? ) + ( 14 /DBG_PRG/3.3V_USB ) ( 15 ? ) ( 16 ? ) - ) - ( /4C69ED5F/4C7FD562 $noname P1 AVR/PROG {Lib=CONN_4} - ( 1 GND ) - ( 2 /PSU/AVR_SCK ) - ( 3 /PSU/AVR_MISO ) - ( 4 /PSU/AVR_MOSI ) + ( 17 ? ) + ( 18 GND ) + ( 19 ? ) + ( 20 ? ) + ( 21 /DBG_PRG/FPGA_TMS ) + ( 22 /FPGA,_Port0,_Port2,_PROG_IF/S6_TDO ) + ( 23 /DBG_PRG/FPGA_TDI ) + ( 24 /FPGA,_Port0,_Port2,_PROG_IF/S6_TCK ) + ( 25 GND ) + ( 26 N-000237 ) + ( 27 ? ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 /DBG_PRG/3.3V_USB ) + ( 32 ? ) + ( 33 ? ) + ( 34 GND ) + ( 35 ? ) + ( 36 ? ) + ( 37 /PSU/AVR_RST ) + ( 38 /PSU/AVR_MISO ) + ( 39 /PSU/AVR_MOSI ) + ( 40 /DBG_PRG/AVR_SCK ) + ( 41 ? ) + ( 42 /DBG_PRG/VCC_USB ) + ( 43 N-000226 ) + ( 44 N-000208 ) + ( 45 GND ) + ( 46 N-000231 ) + ( 47 GND ) + ( 48 ? ) ) ( /4C69ED5F/4C7FD266 0402 C104 100nF {Lib=CAP} ( 1 +3.3V ) @@ -1242,11 +1399,11 @@ ( 2 GND ) ) ( /4C69ED5F/4C7C4D9E $noname R40 47K {Lib=R} - ( 1 N-000199 ) - ( 2 N-000194 ) + ( 1 N-000180 ) + ( 2 N-000175 ) ) ( /4C69ED5F/4C7C4D94 $noname C100 220pF {Lib=C} - ( 1 N-000194 ) + ( 1 N-000175 ) ( 2 GND ) ) ( /4C69ED5F/4C7C4D8E $noname C99 22uF {Lib=C} @@ -1317,7 +1474,7 @@ ( 2 /PSU/VFB5.0 ) ) ( /4C69ED5F/4C79C828 1210 L10 4.7uH {Lib=INDUCTOR} - ( 1 N-000184 ) + ( 1 N-000168 ) ( 2 /PSU/VIN_DC-DC-5.0 ) ) ( /4C69ED5F/4C79C7C0 0402 R37 1M {Lib=R} @@ -1325,7 +1482,7 @@ ( 2 /PSU/VIN_DC-DC-5.0 ) ) ( /4C69ED5F/4C79C65B SOT23_6 U15 A7117 {Lib=A7117} - ( 1 N-000184 ) + ( 1 N-000168 ) ( 2 GND ) ( 3 /PSU/VFB5.0 ) ( 4 /PSU/5V_EN ) @@ -1443,11 +1600,11 @@ ( 7 /PSU/VIN_DC-DC-2.5 ) ( 8 /PSU/VIN_DC-DC-2.5 ) ( 9 /PSU/VFB2.5 ) - ( 10 N-000199 ) + ( 10 N-000180 ) ) ( /4C69ED5F/4C69EE11 MLF20m1 U9 ATTINY24A-MLF {Lib=ATTINY24A-MLF} ( PAD GND ) - ( 1 /PSU/AVR_SCK ) + ( 1 /DBG_PRG/AVR_SCK ) ( 2 /PSU/Iout_1.2 ) ( 3 /PSU/1.2V_EN ) ( 4 /PSU/lout_3.3 ) @@ -1485,14 +1642,14 @@ ( 2 GND ) ) ( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB} - ( 1 /Non_volatile_memories/SPI_FLASH_CS# ) - ( 2 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO1 ) + ( 1 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CSO ) + ( 2 /Non_volatile_memories/SPI_DQ1 ) ( 3 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO2 ) ( 4 GND ) ( 5 /Non_volatile_memories/SPI_DQ0 ) ( 6 /FPGA,_Port0,_Port2,_PROG_IF/PROG_CCLK ) ( 7 /FPGA,_Port0,_Port2,_PROG_IF/PROG_MISO3 ) - ( 8 N-000115 ) + ( 8 N-000099 ) ) ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} ( CASE GND ) @@ -1504,7 +1661,7 @@ ( 4 +3.3V ) ( 5 /Non_volatile_memories/SD_CLK ) ( 6 GND ) - ( 7 /FPGA,_Port0,_Port2,_PROG_IF/SD_DAT0 ) + ( 7 /Non_volatile_memories/SD_DAT0 ) ( 8 /Non_volatile_memories/SD_DAT1 ) ) ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} @@ -1515,17 +1672,17 @@ ( 5 ? ) ( 6 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB ) ( 7 /FPGA,_Port0,_Port2,_PROG_IF/NF_RNB ) - ( 8 /FPGA,_Port0,_Port2,_PROG_IF/NF_RE_N ) - ( 9 /FPGA,_Port0,_Port2,_PROG_IF/NF_CS1_N ) + ( 8 /Non_volatile_memories/NF_RE_N ) + ( 9 /Non_volatile_memories/NF_CS1_N ) ( 10 ? ) ( 11 ? ) ( 12 +3.3V ) ( 13 GND ) ( 14 ? ) ( 15 ? ) - ( 16 /FPGA,_Port0,_Port2,_PROG_IF/NF_CLE ) + ( 16 /Non_volatile_memories/NF_CLE ) ( 17 /Non_volatile_memories/NF_ALE ) - ( 18 /FPGA,_Port0,_Port2,_PROG_IF/NF_WE_N ) + ( 18 /Non_volatile_memories/NF_WE_N ) ( 19 +3.3V ) ( 20 ? ) ( 21 ? ) @@ -1536,10 +1693,10 @@ ( 26 ? ) ( 27 ? ) ( 28 ? ) - ( 29 /Non_volatile_memories/NF_D0 ) + ( 29 /FPGA,_Port0,_Port2,_PROG_IF/NF_D0 ) ( 30 /FPGA,_Port0,_Port2,_PROG_IF/NF_D1 ) - ( 31 /FPGA,_Port0,_Port2,_PROG_IF/NF_D2 ) - ( 32 /Non_volatile_memories/NF_D3 ) + ( 31 /Non_volatile_memories/NF_D2 ) + ( 32 /FPGA,_Port0,_Port2,_PROG_IF/NF_D3 ) ( 33 ? ) ( 34 ? ) ( 35 ? ) @@ -1549,9 +1706,9 @@ ( 39 ? ) ( 40 ? ) ( 41 /FPGA,_Port0,_Port2,_PROG_IF/NF_D4 ) - ( 42 /Non_volatile_memories/NF_D5 ) + ( 42 /FPGA,_Port0,_Port2,_PROG_IF/NF_D5 ) ( 43 /FPGA,_Port0,_Port2,_PROG_IF/NF_D6 ) - ( 44 /FPGA,_Port0,_Port2,_PROG_IF/NF_D7 ) + ( 44 /Non_volatile_memories/NF_D7 ) ( 45 ? ) ( 46 ? ) ( 47 ? ) @@ -1571,19 +1728,19 @@ ) ( /4C5F1EDC/4C7D354D $noname R49 24 {Lib=R} ( 1 /USB/USBD_D+ ) - ( 2 N-000168 ) + ( 2 N-000155 ) ) ( /4C5F1EDC/4C7D354C $noname R50 24 {Lib=R} ( 1 /USB/USBD_D- ) - ( 2 N-000172 ) + ( 2 N-000152 ) ) ( /4C5F1EDC/4C7D350E $noname R52 24 {Lib=R} ( 1 /USB/USBA_D- ) - ( 2 N-000171 ) + ( 2 N-000154 ) ) ( /4C5F1EDC/4C7D3508 $noname R51 24 {Lib=R} ( 1 /USB/USBA_D+ ) - ( 2 N-000170 ) + ( 2 N-000153 ) ) ( /4C5F1EDC/4C7D32A3 $noname R48 15k {Lib=R} ( 1 +3.3V ) @@ -1598,40 +1755,40 @@ ( 2 /USB/USBA_D- ) ) ( /4C5F1EDC/4C75F027 ZX62D-B-5P8 J7 ZX62D-B-5P8 {Lib=ZX62D-B-5P8} - ( 1 N-000169 ) + ( 1 N-000162 ) ( 2 /USB/USBD_D- ) ( 3 /USB/USBD_D+ ) - ( 4 N-000174 ) - ( 5 N-000174 ) + ( 4 N-000156 ) + ( 5 N-000156 ) ( 6 /USB/USB_CASE_DEV ) ( 7 /USB/USB_CASE_DEV ) ( 8 /USB/USB_CASE_DEV ) ( 9 /USB/USB_CASE_DEV ) ) ( /4C5F1EDC/4C71BA25 MLF16 U7 MIC2550-MLF {Lib=MIC2550-MLF} - ( 1 /USB/USBD_SPD ) - ( 2 /USB/USBD_RCV ) + ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_SPD ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_RCV ) ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_VP ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/USBD_VM ) ( 6 GND ) ( 7 GND ) ( 9 /USB/USBD_OE_N ) - ( 10 N-000172 ) - ( 11 N-000168 ) + ( 10 N-000152 ) + ( 11 N-000155 ) ( 12 +3.3V ) ( 14 +3.3V ) ( 15 +2.5V ) ) ( /4C5F1EDC/4C71BA1D MLF16 U6 MIC2550-MLF {Lib=MIC2550-MLF} - ( 1 /USB/USBA_SPD ) - ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_RCV ) - ( 3 /USB/USBA_VP ) - ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VM ) + ( 1 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_SPD ) + ( 2 /USB/USBA_RCV ) + ( 3 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_VP ) + ( 4 /USB/USBA_VM ) ( 6 GND ) ( 7 GND ) ( 9 /FPGA_Port_1,_Port_3_DDR,_USB/USBA_OE_N ) - ( 10 N-000171 ) - ( 11 N-000170 ) + ( 10 N-000154 ) + ( 11 N-000153 ) ( 12 +3.3V ) ( 14 +3.3V ) ( 15 +2.5V ) @@ -1665,15 +1822,15 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} - ( 1 N-000169 ) + ( 1 N-000162 ) ( 2 GND ) ) ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000178 ) - ( 2 N-000177 ) + ( 1 N-000160 ) + ( 2 N-000159 ) ) ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000176 ) + ( 1 N-000158 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} @@ -1693,7 +1850,7 @@ ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000178 ) + ( 1 N-000160 ) ( 2 +5V ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} @@ -1701,10 +1858,10 @@ ( S2 /USB/USB_CASE_HOST ) ( S3 /USB/USB_CASE_HOST ) ( S4 /USB/USB_CASE_HOST ) - ( 1 N-000177 ) + ( 1 N-000159 ) ( 2 /USB/USBA_D- ) ( 3 /USB/USBA_D+ ) - ( 4 N-000176 ) + ( 4 N-000158 ) ) ( /4C5F1EDC/4C5F2039 $noname C15 100nF {Lib=C} ( 1 +2.5V ) @@ -1767,11 +1924,11 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} - ( 1 /Ethernet_Phy/ETH_MDIO ) + ( 1 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO ) ( 2 +3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000148 ) + ( 1 N-000132 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} @@ -1791,31 +1948,31 @@ ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /Ethernet_Phy/ETH_MDIO ) - ( 2 /Ethernet_Phy/ETH_MDC ) - ( 3 /Ethernet_Phy/ETH_RXD3 ) + ( 1 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDIO ) + ( 2 /FPGA,_Port0,_Port2,_PROG_IF/ETH_MDC ) + ( 3 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD3 ) ( 4 /Ethernet_Phy/ETH_RXD2 ) - ( 5 /Ethernet_Phy/ETH_RXD1 ) + ( 5 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD1 ) ( 6 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXD0 ) ( 7 +3.3V ) ( 8 GND ) ( 9 /Ethernet_Phy/ETH_RXDV ) - ( 10 /Ethernet_Phy/ETH_RXC ) - ( 11 /Ethernet_Phy/ETH_RXER ) + ( 10 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXC ) + ( 11 /FPGA,_Port0,_Port2,_PROG_IF/ETH_RXER ) ( 12 GND ) ( 13 /Ethernet_Phy/ETH_1.8V ) - ( 14 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXER ) - ( 15 /Ethernet_Phy/ETH_TXC ) - ( 16 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXEN ) + ( 14 /Ethernet_Phy/ETH_TXER ) + ( 15 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXC ) + ( 16 /Ethernet_Phy/ETH_TXEN ) ( 17 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD0 ) ( 18 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD1 ) - ( 19 /Ethernet_Phy/ETH_TXD2 ) - ( 20 /Ethernet_Phy/ETH_TXD3 ) - ( 21 /FPGA,_Port0,_Port2,_PROG_IF/ETH_COL ) + ( 19 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD2 ) + ( 20 /FPGA,_Port0,_Port2,_PROG_IF/ETH_TXD3 ) + ( 21 /Ethernet_Phy/ETH_COL ) ( 22 /Ethernet_Phy/ETH_CRS ) ( 23 GND ) ( 24 +3.3V ) - ( 25 /FPGA,_Port0,_Port2,_PROG_IF/ETH_INT ) + ( 25 /Ethernet_Phy/ETH_INT ) ( 26 /Ethernet_Phy/ETH_LED0 ) ( 27 /Ethernet_Phy/ETH_LED1 ) ( 28 ? ) @@ -1827,7 +1984,7 @@ ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000148 ) + ( 37 N-000132 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) ( 40 /Ethernet_Phy/MAG_TX- ) @@ -1857,11 +2014,11 @@ ( 2 /Ethernet_Phy/MAG_RX+ ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000163 ) + ( 1 N-000147 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000164 ) + ( 1 N-000148 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} @@ -1874,9 +2031,9 @@ ( 7 /Ethernet_Phy/MAG_RX+ ) ( 8 /Ethernet_Phy/MAG_RX- ) ( 9 +3.3V ) - ( 10 N-000164 ) + ( 10 N-000148 ) ( 11 +3.3V ) - ( 12 N-000163 ) + ( 12 N-000147 ) ( 13 /Ethernet_Phy/MAG_SHIELD ) ( 14 /Ethernet_Phy/MAG_SHIELD ) ) @@ -1888,64 +2045,64 @@ ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ2 ) ( 6 GND ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ3 ) - ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ4 ) + ( 8 /DDR_Banks/M1_DQ4 ) ( 9 +2.5V ) - ( 10 /DDR_Banks/M1_DQ5 ) + ( 10 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ5 ) ( 11 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ7 ) + ( 13 /DDR_Banks/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /DDR_Banks/M1_LDQS ) + ( 16 /FPGA_Port_1,_Port_3_DDR,_USB/M1_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) ( 20 /DDR_Banks/M1_LDM ) ( 21 /FPGA_Port_1,_Port_3_DDR,_USB/M1_WE# ) - ( 22 /DDR_Banks/M1_CAS# ) - ( 23 /DDR_Banks/M1_RAS# ) - ( 24 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CS# ) + ( 22 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CAS# ) + ( 23 /FPGA_Port_1,_Port_3_DDR,_USB/M1_RAS# ) + ( 24 /DDR_Banks/M1_CS# ) ( 25 ? ) - ( 26 /DDR_Banks/M1_BA0 ) - ( 27 /DDR_Banks/M1_BA1 ) - ( 28 /DDR_Banks/M1_A10 ) - ( 29 /DDR_Banks/M1_A0 ) + ( 26 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA0 ) + ( 27 /FPGA_Port_1,_Port_3_DDR,_USB/M1_BA1 ) + ( 28 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A10 ) + ( 29 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A0 ) ( 30 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A1 ) - ( 31 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A2 ) - ( 32 /DDR_Banks/M1_A3 ) + ( 31 /DDR_Banks/M1_A2 ) + ( 32 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A4 ) ( 36 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A5 ) ( 37 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A6 ) ( 38 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A7 ) - ( 39 /DDR_Banks/M1_A8 ) + ( 39 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A8 ) ( 40 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A9 ) ( 41 /DDR_Banks/M1_A11 ) ( 42 /FPGA_Port_1,_Port_3_DDR,_USB/M1_A12 ) ( 43 ? ) - ( 44 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK# ) - ( 45 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CKE ) + ( 44 /DDR_Banks/M1_CLK# ) + ( 45 /DDR_Banks/M1_CKE ) ( 46 /FPGA_Port_1,_Port_3_DDR,_USB/M1_CLK ) - ( 47 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDM ) + ( 47 /DDR_Banks/M1_UDM ) ( 48 GND ) ( 49 /DDR_Banks/M1_VREF ) ( 50 ? ) - ( 51 /DDR_Banks/M1_UDQS ) + ( 51 /FPGA_Port_1,_Port_3_DDR,_USB/M1_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M1_DQ8 ) + ( 54 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ8 ) ( 55 +2.5V ) ( 56 /DDR_Banks/M1_DQ9 ) ( 57 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ10 ) ( 58 GND ) ( 59 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ11 ) - ( 60 /DDR_Banks/M1_DQ12 ) + ( 60 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ12 ) ( 61 +2.5V ) ( 62 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ13 ) ( 63 /DDR_Banks/M1_DQ14 ) ( 64 GND ) - ( 65 /FPGA_Port_1,_Port_3_DDR,_USB/M1_DQ15 ) + ( 65 /DDR_Banks/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} @@ -2046,70 +2203,70 @@ ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /DDR_Banks/M0_DQ0 ) + ( 2 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ0 ) ( 3 +2.5V ) ( 4 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ1 ) ( 5 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ2 ) ( 6 GND ) ( 7 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ3 ) - ( 8 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ4 ) + ( 8 /DDR_Banks/M0_DQ4 ) ( 9 +2.5V ) - ( 10 /DDR_Banks/M0_DQ5 ) + ( 10 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ5 ) ( 11 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ6 ) ( 12 GND ) ( 13 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /FPGA_Port_1,_Port_3_DDR,_USB/M0_LDQS ) + ( 16 /DDR_Banks/M0_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Port_1,_Port_3_DDR,_USB/M0_LDM ) - ( 21 /FPGA_Port_1,_Port_3_DDR,_USB/M0_WE# ) - ( 22 /DDR_Banks/M0_CAS# ) - ( 23 /DDR_Banks/M0_RAS# ) + ( 20 /DDR_Banks/M0_LDM ) + ( 21 /DDR_Banks/M0_WE# ) + ( 22 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CAS# ) + ( 23 /FPGA_Port_1,_Port_3_DDR,_USB/M0_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /DDR_Banks/M0_BA0 ) - ( 27 /FPGA_Port_1,_Port_3_DDR,_USB/M0_BA1 ) - ( 28 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A10 ) - ( 29 /DDR_Banks/M0_A0 ) - ( 30 /DDR_Banks/M0_A1 ) + ( 27 /DDR_Banks/M0_BA1 ) + ( 28 /DDR_Banks/M0_A10 ) + ( 29 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A0 ) + ( 30 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A1 ) ( 31 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A2 ) ( 32 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A4 ) - ( 36 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A5 ) - ( 37 /DDR_Banks/M0_A6 ) - ( 38 /DDR_Banks/M0_A7 ) + ( 35 /DDR_Banks/M0_A4 ) + ( 36 /DDR_Banks/M0_A5 ) + ( 37 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A6 ) + ( 38 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A7 ) ( 39 /DDR_Banks/M0_A8 ) ( 40 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A9 ) ( 41 /DDR_Banks/M0_A11 ) - ( 42 /DDR_Banks/M0_A12 ) + ( 42 /FPGA_Port_1,_Port_3_DDR,_USB/M0_A12 ) ( 43 ? ) ( 44 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK# ) - ( 45 /DDR_Banks/M0_CKE ) + ( 45 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CKE ) ( 46 /FPGA_Port_1,_Port_3_DDR,_USB/M0_CLK ) - ( 47 /DDR_Banks/M0_UDM ) + ( 47 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDM ) ( 48 GND ) ( 49 /DDR_Banks/M0_VREF ) ( 50 ? ) - ( 51 /DDR_Banks/M0_UDQS ) + ( 51 /FPGA_Port_1,_Port_3_DDR,_USB/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M0_DQ8 ) + ( 54 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /DDR_Banks/M0_DQ9 ) - ( 57 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ10 ) + ( 56 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ9 ) + ( 57 /DDR_Banks/M0_DQ10 ) ( 58 GND ) ( 59 /DDR_Banks/M0_DQ11 ) - ( 60 /DDR_Banks/M0_DQ12 ) + ( 60 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ12 ) ( 61 +2.5V ) ( 62 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ13 ) ( 63 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M0_DQ15 ) + ( 65 /FPGA_Port_1,_Port_3_DDR,_USB/M0_DQ15 ) ( 66 GND ) ) ) @@ -2575,6 +2732,80 @@ $component R16 SM0603 SM0805 $endlist +$component C146 + SM* + C? + C1-1 +$endlist +$component C147 + SM* + C? + C1-1 +$endlist +$component C150 + CP* + SM* +$endlist +$component R69 + R? + SM0603 + SM0805 +$endlist +$component C145 + SM* + C? + C1-1 +$endlist +$component C148 + SM* + C? + C1-1 +$endlist +$component R74 + R? + SM0603 + SM0805 +$endlist +$component C151 + SM* + C? + C1-1 +$endlist +$component C149 + SM* + C? + C1-1 +$endlist +$component R71 + R? + SM0603 + SM0805 +$endlist +$component R70 + R? + SM0603 + SM0805 +$endlist +$component R73 + R? + SM0603 + SM0805 +$endlist +$component R72 + R? + SM0603 + SM0805 +$endlist +$component R76 + R? + SM0603 + SM0805 +$endlist +$component R75 + R? + SM0603 + SM0805 +$endlist $component C104 SM* C? @@ -3123,65 +3354,74 @@ $endlist $endfootprintlist } { Pin List by Nets -Net 18 "/DDR Banks/M0_UDM" "M0_UDM" - U2 47 +Net 1 "/FPGA, Port0, Port2, PROG IF/S6_TDO" "S6_TDO" + IC1 22 + U1 A19 +Net 2 "/DBG_PRG/FPGA_TDI" "FPGA_TDI" + IC1 23 + U1 E18 +Net 3 "/DBG_PRG/FPGA_TMS" "FPGA_TMS" + IC1 21 + U1 C18 +Net 4 "/FPGA, Port0, Port2, PROG IF/S6_TCK" "S6_TCK" + IC1 24 + U1 G15 +Net 5 "/DBG_PRG/AVR_SCK" "AVR_SCK" + U9 1 + IC1 40 +Net 6 "/FPGA Port 1, Port 3 DDR, USB/M0_UDM" "M0_UDM" R23 2 -Net 19 "/FPGA Port 1, Port 3 DDR, USB/M0_LDQS" "M0_LDQS" - RP16 8 + U2 47 +Net 7 "/DDR Banks/M0_LDQS" "M0_LDQS" U2 16 -Net 20 "/FPGA Port 1, Port 3 DDR, USB/M0_CLK" "M0_CLK" - U1 H4 + RP16 8 +Net 8 "/FPGA Port 1, Port 3 DDR, USB/M0_CLK" "M0_CLK" R21 1 U2 46 -Net 21 "/FPGA Port 1, Port 3 DDR, USB/M0_CLK#" "M0_CLK#" + U1 H4 +Net 9 "/FPGA Port 1, Port 3 DDR, USB/M0_CLK#" "M0_CLK#" + U2 44 R21 2 U1 H3 - U2 44 -Net 22 "GND" "GND" - C12 2 - J1 CASE - J1 CASE - J1 COM - J1 6 - U4 23 - R9 2 - U5 36 - C68 2 - C10 2 - C55 2 - C58 2 - U5 13 - C11 2 - R2 2 - C61 2 - U4 39 - U4 36 - U4 35 - U4 44 - C8 2 - C7 2 - J1 CASE - C5 2 - C3 2 - C1 2 - C9 2 - C6 2 - C4 2 - C2 2 - C27 2 - C21 2 - C26 2 - C24 2 - C25 2 - C23 2 - C33 2 - C28 2 - C29 2 - C31 2 - C30 2 - C32 2 - C93 2 - C91 2 +Net 10 "GND" "GND" + R47 1 + R46 1 + C35 2 + U6 6 + U1 G18 + U6 7 + J4 5 + J4 4 + R53 1 + R54 1 + C37 2 + V4 2 + V3 2 + C38 2 + R15 2 + V2 2 + C15 2 + C14 2 + C13 2 + R10 2 + C16 2 + V1 2 + U7 6 + U7 7 + L7 2 + L5 2 + C36 2 + C45 2 + U2 6 + C42 2 + C39 2 + C47 2 + C44 2 + C22 2 + R14 2 + R12 2 + C20 2 + C18 2 U2 64 C41 2 C53 2 @@ -3195,37 +3435,8 @@ Net 22 "GND" "GND" U2 24 U2 34 C70 2 - C71 2 - C34 2 - U3 58 - C43 2 - C40 2 - C92 2 - U2 48 - U2 58 - C90 2 - C94 2 - C76 2 - C77 2 - C50 2 C66 2 C63 2 - C65 2 - C62 2 - C59 2 - C56 2 - C75 1 - C45 2 - U2 6 - C42 2 - C39 2 - C47 2 - C44 2 - C22 2 - R14 2 - R12 2 - C20 2 - C18 2 C72 2 C73 2 C74 2 @@ -3237,79 +3448,40 @@ Net 22 "GND" "GND" C67 2 C64 2 C48 2 - U1 J9 - U1 B9 - U1 W7 - U1 U7 - U1 H7 - U1 E7 - U1 R5 - U1 L5 - U1 G5 - U1 B5 - U1 V4 - R35 2 - C95 2 - U1 D4 - U1 U2 - U1 N2 - U1 J2 - U1 E2 - U1 A1 - P1 1 - R53 1 - U1 D18 - R54 1 - U1 N17 - U1 B17 - U1 W16 - U1 AA5 - U1 N15 - U1 M14 - U1 K14 - U1 N13 - U1 L13 - U1 J13 - U1 B13 - U1 A22 - U1 P12 - U9 8 - U9 PAD - C81 2 - R25 2 - C80 2 - C78 2 - U10 2 - U11 2 - U12 2 - C85 2 - U14 5 - R27 2 - R33 2 - C84 2 - U13 5 - R31 2 - C82 2 - U10 5 - U10 PAD - C98 2 - R38 2 - C97 2 - U15 2 - C103 2 - R42 2 - C102 2 - U16 5 - U17 5 - R44 2 - R41 2 - C100 2 - C99 2 - C104 2 - C35 2 - U6 6 - U6 7 - U1 G18 + C75 1 + C30 2 + C32 2 + C93 2 + C91 2 + C90 2 + C94 2 + C76 2 + C77 2 + C71 2 + C34 2 + U3 58 + C43 2 + C40 2 + C92 2 + C27 2 + C21 2 + C26 2 + C24 2 + C25 2 + C23 2 + C33 2 + C28 2 + C29 2 + C31 2 + C8 2 + C7 2 + C5 2 + C3 2 + C1 2 + C9 2 + C6 2 + C4 2 + C2 2 U1 L18 U1 R18 U1 W19 @@ -3319,1547 +3491,1688 @@ Net 22 "GND" "GND" U4 8 U1 AA17 U4 12 - J4 4 - J4 5 - L7 2 - L5 2 - C36 2 - C37 2 - V4 2 - U1 P10 - V3 2 - U1 M10 - C38 2 - U1 K10 - U1 J15 - U1 E15 - U1 V14 - U1 P14 - U1 J11 - U1 E11 - U1 V10 - V1 2 - U7 6 - U7 7 - R47 1 - R46 1 - R15 2 - U1 N9 - V2 2 - U1 L9 - U1 M12 - U1 K12 - U1 AB1 - U1 U21 - U1 N21 - U1 J21 - U1 E21 - C15 2 - C14 2 - U1 N11 - C13 2 + U4 23 + R2 2 + C11 2 + C10 2 + C12 2 + R9 2 + U4 39 + U4 44 + U4 35 + U4 36 + C56 2 + C50 2 + J1 CASE + J1 CASE + J1 CASE + J1 COM + J1 6 + C61 2 + U5 13 + C58 2 + C55 2 + U5 36 + C68 2 + C65 2 + C62 2 + C59 2 U1 L11 - R10 2 - C16 2 - C144 2 + U1 N11 + U1 E21 + U1 J21 + U1 N21 + U1 U21 + U1 AB1 + U1 K12 + U1 M12 + U1 L9 + U1 N9 + U1 K10 + U1 M10 + U1 P10 + U1 V10 + R41 2 + R44 2 + U17 5 + U12 2 + U11 2 + U10 2 + C78 2 + C80 2 + R25 2 + C81 2 + R35 2 + U16 5 + C102 2 + R42 2 + C103 2 + U15 2 + C97 2 + R38 2 + C98 2 + C104 2 + C99 2 + C100 2 + C84 2 + C82 2 + U9 PAD + U9 8 + U10 PAD + U10 5 + R31 2 + U13 5 + R33 2 + U14 5 + C85 2 + R27 2 + U1 H7 + U1 U7 + U1 W7 + U1 B9 + U1 J9 + U1 A1 + U1 E2 + U1 J2 + U1 N2 + U1 U2 + U1 D4 + C148 2 + FB1 2 + C151 2 + U1 E11 + U1 J11 + U1 P14 + U1 V14 + U1 E15 + U1 J15 + U1 N15 + U1 AA5 + U1 W16 + U1 B17 + U1 N17 + U1 D18 + U1 P12 + U1 A22 + U1 B13 + U1 J13 + U1 L13 + U1 N13 + U1 K14 + U1 M14 + U1 V4 + U1 B5 + U1 G5 + U1 L5 + U1 R5 + U1 E7 + C146 2 + C147 2 + C95 2 + C149 1 + C150 2 + R69 2 + C145 2 + IC1 34 + IC1 25 + IC1 45 + IC1 47 + IC1 18 + IC1 9 + C138 2 + U24 44 + U24 35 + U24 39 + U24 30 C143 2 C141 2 C136 2 - C138 2 - C140 2 - U24 44 - U24 35 - C142 2 - U24 39 - U24 30 - U3 52 - C133 2 - U3 34 - C137 2 - U3 64 + C118 2 C129 2 C130 2 U3 66 C132 2 - U24 6 C131 2 C134 2 U3 48 U3 12 - U3 6 C135 2 + U3 52 + C133 2 + U3 6 + U24 6 C139 2 - R62 2 - C109 2 + C140 2 + C142 2 + C144 2 + U3 34 + C137 2 + U3 64 R68 2 - C121 2 - C106 2 - C105 2 - C108 2 - R60 2 - C114 2 - U18 2 - U19 2 - C115 2 C107 2 C110 2 R64 2 C116 2 U20 2 - C118 2 - C117 2 - C120 2 - R66 2 - C127 2 - U22 2 - U23 2 C128 2 -Net 23 "/FPGA Port 1, Port 3 DDR, USB/M1_CLK#" "M1_CLK#" + U23 2 + U22 2 + C115 2 + U19 2 + U18 2 + C114 2 + R62 2 + C109 2 + R60 2 + C108 2 + C105 2 + C106 2 + C121 2 + C127 2 + R66 2 + C120 2 + C117 2 + U2 58 + U2 48 +Net 11 "/DDR Banks/M1_CLK#" "M1_CLK#" U3 44 U1 J19 R16 1 -Net 24 "/FPGA Port 1, Port 3 DDR, USB/M1_CLK" "M1_CLK" - U1 H20 +Net 12 "/FPGA Port 1, Port 3 DDR, USB/M1_CLK" "M1_CLK" U3 46 + U1 H20 R16 2 -Net 25 "/FPGA Port 1, Port 3 DDR, USB/M1_CKE" "M1_CKE" - R17 2 +Net 13 "/DDR Banks/M1_CKE" "M1_CKE" U3 45 -Net 26 "/DDR Banks/M1_CAS#" "M1_CAS#" + R17 2 +Net 14 "/FPGA Port 1, Port 3 DDR, USB/M1_CAS#" "M1_CAS#" U3 22 RP3 5 -Net 27 "/FPGA Port 1, Port 3 DDR, USB/M0_LDM" "M0_LDM" +Net 15 "/DDR Banks/M0_LDM" "M0_LDM" RP16 7 U2 20 -Net 28 "/DDR Banks/M0_UDQS" "M0_UDQS" - U2 51 +Net 16 "/FPGA Port 1, Port 3 DDR, USB/M0_UDQS" "M0_UDQS" R22 2 -Net 29 "/DDR Banks/M1_UDQS" "M1_UDQS" + U2 51 +Net 17 "/FPGA Port 1, Port 3 DDR, USB/M1_UDQS" "M1_UDQS" U3 51 R19 2 -Net 30 "/DDR Banks/M1_LDM" "M1_LDM" +Net 18 "/DDR Banks/M1_LDM" "M1_LDM" U3 20 RP3 7 -Net 31 "/DDR Banks/M1_LDQS" "M1_LDQS" +Net 19 "/FPGA Port 1, Port 3 DDR, USB/M1_LDQS" "M1_LDQS" RP3 8 U3 16 -Net 32 "/FPGA Port 1, Port 3 DDR, USB/M1_UDM" "M1_UDM" +Net 20 "/DDR Banks/M1_UDM" "M1_UDM" U3 47 R18 2 -Net 33 "/FPGA Port 1, Port 3 DDR, USB/M1_CS#" "M1_CS#" - U3 24 +Net 21 "/DDR Banks/M1_CS#" "M1_CS#" R20 2 -Net 34 "/Non volatile memories/NF_ALE" "NF_ALE" + U3 24 +Net 22 "/Non volatile memories/NF_ALE" "NF_ALE" U1 A14 U5 17 -Net 35 "/FPGA, Port0, Port2, PROG IF/NF_CLE" "NF_CLE" +Net 23 "/Non volatile memories/NF_CLE" "NF_CLE" U1 B14 U5 16 -Net 36 "/FPGA, Port0, Port2, PROG IF/NF_WE_N" "NF_WE_N" - U1 C14 +Net 24 "/Non volatile memories/NF_WE_N" "NF_WE_N" U5 18 -Net 37 "/FPGA, Port0, Port2, PROG IF/NF_CS1_N" "NF_CS1_N" - U5 9 + U1 C14 +Net 25 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" U1 D15 -Net 38 "/FPGA, Port0, Port2, PROG IF/NF_RE_N" "NF_RE_N" - U1 C15 + U5 9 +Net 26 "/Non volatile memories/NF_RE_N" "NF_RE_N" U5 8 -Net 39 "/FPGA, Port0, Port2, PROG IF/NF_RNB" "NF_RNB" - U5 7 + U1 C15 +Net 27 "/FPGA, Port0, Port2, PROG IF/NF_RNB" "NF_RNB" U5 6 + U5 7 U1 A15 -Net 40 "/FPGA, Port0, Port2, PROG IF/PROG_CCLK" "PROG_CCLK" +Net 28 "/FPGA, Port0, Port2, PROG IF/PROG_CCLK" "PROG_CCLK" U1 AA21 U8 6 -Net 41 "/Non volatile memories/SPI_FLASH_CS#" "SPI_FLASH_CS#" +Net 29 "/FPGA, Port0, Port2, PROG IF/PROG_CSO" "PROG_CSO" U8 1 U1 T5 -Net 42 "/USB/USBA_SPD" "USBA_SPD" - U1 F16 +Net 30 "/FPGA Port 1, Port 3 DDR, USB/USBA_SPD" "USBA_SPD" U6 1 -Net 43 "/FPGA Port 1, Port 3 DDR, USB/USBA_OE_N" "USBA_OE_N" + U1 F16 +Net 31 "/FPGA Port 1, Port 3 DDR, USB/USBA_OE_N" "USBA_OE_N" U6 9 U1 C19 -Net 44 "/FPGA Port 1, Port 3 DDR, USB/USBA_RCV" "USBA_RCV" - U1 F17 +Net 32 "/USB/USBA_RCV" "USBA_RCV" U6 2 -Net 45 "/USB/USBA_VP" "USBA_VP" - U6 3 + U1 F17 +Net 33 "/FPGA Port 1, Port 3 DDR, USB/USBA_VP" "USBA_VP" U1 D19 -Net 49 "/FPGA, Port0, Port2, PROG IF/S6_TDO" "S6_TDO" - U1 A19 - J6 5 -Net 50 "/DBG_PRG/FPGA_TDI" "FPGA_TDI" - J6 7 - U1 E18 -Net 51 "/FPGA, Port0, Port2, PROG IF/S6_TMS" "S6_TMS" - J6 3 - U1 C18 -Net 52 "/DBG_PRG/FPGA_TCK" "FPGA_TCK" - J6 1 - U1 G15 -Net 53 "/Non volatile memories/SD_CMD" "SD_CMD" + U6 3 +Net 34 "/PSU/AVR_MISO" "AVR_MISO" + IC1 38 + U9 20 +Net 35 "/PSU/AVR_MOSI" "AVR_MOSI" + U9 16 + IC1 39 +Net 36 "/PSU/AVR_RST" "AVR_RST" + R57 1 + IC1 37 + U9 13 +Net 37 "/Non volatile memories/SD_CMD" "SD_CMD" J1 3 U1 C16 -Net 54 "/Non volatile memories/SD_CLK" "SD_CLK" - U1 A17 +Net 38 "/Non volatile memories/SD_CLK" "SD_CLK" J1 5 -Net 55 "/FPGA, Port0, Port2, PROG IF/ETH_TXEN" "ETH_TXEN" - U4 16 + U1 A17 +Net 39 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" U1 D9 -Net 56 "/FPGA, Port0, Port2, PROG IF/ETH_TXER" "ETH_TXER" - U4 14 + U4 16 +Net 40 "/Ethernet Phy/ETH_TXER" "ETH_TXER" U1 D8 -Net 57 "/Ethernet Phy/ETH_CLK" "ETH_CLK" - U1 A4 + U4 14 +Net 41 "/Ethernet Phy/ETH_CLK" "ETH_CLK" U4 46 -Net 58 "/FPGA, Port0, Port2, PROG IF/ETH_INT" "ETH_INT" - U4 25 + U1 A4 +Net 42 "/Ethernet Phy/ETH_INT" "ETH_INT" U1 A10 -Net 59 "/FPGA Port 1, Port 3 DDR, USB/M0_WE#" "M0_WE#" - RP16 6 + U4 25 +Net 43 "/DDR Banks/M0_WE#" "M0_WE#" U2 21 -Net 60 "/DDR Banks/M0_RAS#" "M0_RAS#" + RP16 6 +Net 44 "/FPGA Port 1, Port 3 DDR, USB/M0_RAS#" "M0_RAS#" U2 23 RP15 8 -Net 61 "/DDR Banks/M1_RAS#" "M1_RAS#" +Net 45 "/FPGA Port 1, Port 3 DDR, USB/M1_RAS#" "M1_RAS#" U3 23 RP2 8 -Net 62 "/FPGA Port 1, Port 3 DDR, USB/M1_WE#" "M1_WE#" +Net 46 "/FPGA Port 1, Port 3 DDR, USB/M1_WE#" "M1_WE#" RP3 6 U3 21 -Net 63 "/DDR Banks/M0_CAS#" "M0_CAS#" +Net 47 "/FPGA Port 1, Port 3 DDR, USB/M0_CAS#" "M0_CAS#" U2 22 RP16 5 -Net 64 "/DDR Banks/M0_CKE" "M0_CKE" +Net 48 "/FPGA Port 1, Port 3 DDR, USB/M0_CKE" "M0_CKE" R24 2 U2 45 -Net 65 "/FPGA Port 1, Port 3 DDR, USB/USBA_VM" "USBA_VM" - U6 4 +Net 49 "/USB/USBA_VM" "USBA_VM" U1 D20 -Net 66 "/USB/USBD_SPD" "USBD_SPD" + U6 4 +Net 50 "/FPGA Port 1, Port 3 DDR, USB/USBD_SPD" "USBD_SPD" U7 1 U1 B20 -Net 67 "/USB/USBD_OE_N" "USBD_OE_N" - U1 A21 +Net 51 "/USB/USBD_OE_N" "USBD_OE_N" U7 9 -Net 68 "/USB/USBD_RCV" "USBD_RCV" + U1 A21 +Net 52 "/FPGA Port 1, Port 3 DDR, USB/USBD_RCV" "USBD_RCV" U7 2 U1 A20 -Net 69 "/FPGA Port 1, Port 3 DDR, USB/USBD_VP" "USBD_VP" +Net 53 "/FPGA Port 1, Port 3 DDR, USB/USBD_VP" "USBD_VP" U7 3 U1 B21 -Net 70 "/FPGA Port 1, Port 3 DDR, USB/USBD_VM" "USBD_VM" - U1 B22 +Net 54 "/FPGA Port 1, Port 3 DDR, USB/USBD_VM" "USBD_VM" U7 4 -Net 71 "/Ethernet Phy/ETH_RXC" "ETH_RXC" - U1 A7 + U1 B22 +Net 55 "/FPGA, Port0, Port2, PROG IF/ETH_RXC" "ETH_RXC" U4 10 -Net 72 "/FPGA, Port0, Port2, PROG IF/ETH_RESET_N" "ETH_RESET_N" - U1 C7 + U1 A7 +Net 56 "/FPGA, Port0, Port2, PROG IF/ETH_RESET_N" "ETH_RESET_N" U4 48 -Net 73 "/Ethernet Phy/ETH_CRS" "ETH_CRS" - U1 B10 + U1 C7 +Net 57 "/Ethernet Phy/ETH_CRS" "ETH_CRS" U4 22 -Net 74 "/FPGA, Port0, Port2, PROG IF/ETH_COL" "ETH_COL" - U4 21 + U1 B10 +Net 58 "/Ethernet Phy/ETH_COL" "ETH_COL" U1 A9 -Net 75 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" + U4 21 +Net 59 "/FPGA, Port0, Port2, PROG IF/ETH_MDIO" "ETH_MDIO" + U4 1 U1 D6 R1 1 - U4 1 -Net 76 "/Ethernet Phy/ETH_MDC" "ETH_MDC" - U4 2 +Net 60 "/FPGA, Port0, Port2, PROG IF/ETH_MDC" "ETH_MDC" U1 D7 -Net 77 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" - U1 A6 + U4 2 +Net 61 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" U4 9 -Net 78 "/Ethernet Phy/ETH_RXER" "ETH_RXER" + U1 A6 +Net 62 "/FPGA, Port0, Port2, PROG IF/ETH_RXER" "ETH_RXER" U1 B8 U4 11 -Net 79 "/Ethernet Phy/ETH_TXC" "ETH_TXC" +Net 63 "/FPGA, Port0, Port2, PROG IF/ETH_TXC" "ETH_TXC" U1 C8 U4 15 -Net 80 "/Image Sensor/+2.8_VDDIO" "+2.8_VDDIO" - C124 1 - C143 1 - U24 18 - C141 1 - C144 1 - C127 1 - C140 1 - U24 12 - U22 6 - R65 1 - C142 1 -Net 81 "/Image Sensor/+2.8_VAAPIX" "+2.8_VAAPIX" - R61 1 - C112 1 - U19 6 - U24 37 - U24 38 - C132 1 - C115 1 - C131 1 -Net 82 "/Image Sensor/IS_SDA" "IS_SDA" - U1 AA6 - U24 16 -Net 83 "/Image Sensor/IS_I2C_ADDR" "IS_I2C_ADDR" - U1 AB4 - U24 24 -Net 84 "/Image Sensor/IS_RESET_N" "IS_RESET_N" - U1 AB5 - U24 17 -Net 85 "/FPGA, Port0, Port2, PROG IF/IS_STANDBY" "IS_STANDBY" - U24 22 +Net 64 "/Image Sensor/IS_STANDBY" "IS_STANDBY" U1 Y5 -Net 86 "/FPGA, Port0, Port2, PROG IF/IS_TRIGGER" "IS_TRIGGER" + U24 22 +Net 65 "/FPGA, Port0, Port2, PROG IF/IS_TRIGGER" "IS_TRIGGER" U1 Y3 U24 27 -Net 87 "/Image Sensor/IS_PIXEL" "IS_PIXEL" +Net 66 "/FPGA, Port0, Port2, PROG IF/IS_PIXEL" "IS_PIXEL" U24 13 U1 AB6 -Net 88 "/FPGA, Port0, Port2, PROG IF/IS_FRAME" "IS_FRAME" +Net 67 "/Image Sensor/IS_FRAME" "IS_FRAME" U1 AB2 U24 28 -Net 89 "/FPGA, Port0, Port2, PROG IF/IS_LINE" "IS_LINE" +Net 68 "/Snesor PSU/+2.8_VDDIO" "+2.8_VDDIO" + R65 1 + C127 1 + C141 1 + C142 1 + C140 1 + U24 12 + U24 18 + U22 6 + C124 1 + C143 1 + C144 1 +Net 69 "/Snesor PSU/+2.8_VAAPIX" "+2.8_VAAPIX" + C132 1 + C131 1 + C112 1 + C115 1 + R61 1 + U24 38 + U24 37 + U19 6 +Net 70 "/Image Sensor/IS_SDA" "IS_SDA" + U1 AA6 + U24 16 +Net 71 "/Image Sensor/IS_I2C_ADDR" "IS_I2C_ADDR" + U1 AB4 + U24 24 +Net 72 "/Image Sensor/IS_RESET_N" "IS_RESET_N" + U1 AB5 + U24 17 +Net 73 "/Image Sensor/IS_LINE" "IS_LINE" U1 AA2 U24 29 -Net 90 "/FPGA, Port0, Port2, PROG IF/IS_FLASH" "IS_FLASH" +Net 74 "/FPGA, Port0, Port2, PROG IF/IS_FLASH" "IS_FLASH" U24 26 U1 AB3 -Net 91 "/FPGA, Port0, Port2, PROG IF/IS_TEST" "IS_TEST" - U1 AA4 +Net 75 "/Image Sensor/IS_TEST" "IS_TEST" U24 25 -Net 92 "/Image Sensor/IS_OE_N" "IS_OE_N" + U1 AA4 +Net 76 "/Image Sensor/IS_OE_N" "IS_OE_N" U1 Y4 U24 23 -Net 93 "/FPGA, Port0, Port2, PROG IF/IS_EXTCLK" "IS_EXTCLK" +Net 77 "/FPGA, Port0, Port2, PROG IF/IS_EXTCLK" "IS_EXTCLK" U1 W12 U24 5 -Net 94 "/FPGA, Port0, Port2, PROG IF/IS_SCL" "IS_SCL" +Net 78 "/FPGA, Port0, Port2, PROG IF/IS_SCL" "IS_SCL" U24 15 U1 Y12 -Net 95 "/Image Sensor/+2.8_VAA" "+2.8_VAA" - U18 6 - C133 1 +Net 79 "/Snesor PSU/+2.8_VAA" "+2.8_VAA" C111 1 C114 1 - R59 1 - C134 1 C135 1 - U24 36 + C134 1 U24 40 + C133 1 U24 34 -Net 96 "/Image Sensor/+1.8_VDD" "+1.8_VDD" + U18 6 + U24 36 + R59 1 +Net 80 "/Image Sensor/+1.8_VDD" "+1.8_VDD" C139 1 - U20 6 - R63 1 U24 14 - C116 1 + C137 1 + U20 6 C113 1 C136 1 - U24 19 C138 1 - C137 1 -Net 97 "/Image Sensor/+2.8_VDDPLL" "+2.8_VDDPLL" - C128 1 + R63 1 + C116 1 + U24 19 +Net 81 "/Snesor PSU/+2.8_VDDPLL" "+2.8_VDDPLL" R67 1 - C125 1 - U24 4 - U23 6 C130 1 C129 1 -Net 102 "+2.5V" "+2.5V" - C59 1 - C62 1 - C53 1 - C65 1 - U3 15 - C17 1 - C70 1 - C94 1 - U2 55 - C71 1 - C77 1 - U2 1 - U2 3 - U2 9 - U1 R12 - U3 55 - U2 61 - U2 18 - U3 9 - U3 18 - C49 1 - C43 1 - C54 1 - U3 61 - C57 1 - C103 1 - C52 1 - L11 1 - R43 1 - C102 1 - C101 1 - C46 1 - U2 33 - C60 1 - C63 1 - C66 1 - U3 1 - U1 V6 - U1 R6 - U3 33 - C51 1 - C56 1 - U1 H9 - U1 N8 - U1 L8 - U3 3 - U1 G12 - C15 1 - U1 U11 - C31 1 - C29 1 - C28 1 - C37 1 - U1 W21 - U1 R21 - U1 R10 + C128 1 + C125 1 + U23 6 + U24 4 +Net 86 "+2.5V" "+2.5V" + C68 1 C21 1 + U2 1 + C26 1 + C33 1 + C24 1 + C25 1 C22 1 C23 1 - C25 1 - C24 1 - C26 1 - U7 15 - U2 15 - U6 15 - C33 1 + C17 1 + U2 3 C19 1 - C27 1 - U1 L7 - U1 W2 + U1 R10 U1 R2 - C32 1 - C30 1 - R13 1 U1 L2 U1 G2 - C68 1 U1 C2 - U1 K15 - U1 H15 - R11 1 + U1 W2 U1 F11 - U1 M15 + U2 15 + U2 55 + C53 1 + R13 1 + U3 3 + U1 F4 U1 F6 U1 U5 U1 N5 U1 J5 + U1 J18 U1 L16 - C40 1 U1 E19 U1 U18 + U1 L7 U1 N18 - U1 J18 + U1 W21 + U1 R21 U1 L21 U1 G21 U1 C21 - C34 1 - U1 F4 + U3 9 + U1 G12 + R11 1 + U1 U11 + C52 1 + U2 33 + U1 K15 + U1 M15 + U3 61 + C43 1 U1 D16 -Net 105 "/DDR Banks/M0_VREF" "M0_VREF" + U1 R12 + C70 1 + C71 1 + C34 1 + U2 9 + C40 1 + C51 1 + C49 1 + U2 18 + U2 61 + U1 H15 + C46 1 + C15 1 + C31 1 + C30 1 + C56 1 + U3 1 + U3 55 + C32 1 + C27 1 + C94 1 + C37 1 + U3 18 + U1 V6 + C66 1 + U3 15 + U3 33 + U1 L8 + U6 15 + U1 N8 + U7 15 + C60 1 + C63 1 + C65 1 + C62 1 + C59 1 + U1 R6 + C77 1 + C102 1 + C101 1 + C57 1 + C54 1 + U1 H9 + C28 1 + C29 1 + C103 1 + L11 1 + R43 1 +Net 89 "/DDR Banks/M0_VREF" "M0_VREF" U2 49 - R11 2 C17 2 R12 1 + R11 2 C18 1 -Net 106 "/DDR Banks/M1_VREF" "M1_VREF" +Net 90 "/DDR Banks/M1_VREF" "M1_VREF" + U3 49 R14 1 + R13 2 C19 2 C20 1 - R13 2 - U3 49 -Net 115 "" "" - C55 1 - C58 1 - U1 AA3 - U1 T13 - U1 V12 - U1 AA7 - U1 V16 - U1 W5 +Net 99 "" "" U1 T9 U1 V8 - C69 1 - U8 8 + U1 AA19 + U1 AA3 + U1 T13 C67 1 + U1 AA15 + C55 1 + U1 W5 + U8 8 + U1 V16 + C69 1 C64 1 C61 1 + C58 1 U1 AA11 - U1 AA19 - U1 AA15 -Net 116 "+3.3V" "+3.3V" - U1 Y20 + U1 V12 + U1 AA7 +Net 100 "+3.3V" "+3.3V" + R26 1 + C50 1 + R6 1 + C47 1 + C75 2 + R75 1 + C74 1 + R76 1 + R5 1 + L8 1 + L2 1 + U4 24 + C44 1 U1 B4 + C5 1 U1 B7 - C81 1 U1 E13 + C3 1 U1 G14 U1 B15 - C79 1 - C80 1 - R26 1 - L8 1 - U9 9 - R57 2 - J4 3 - J4 6 - J4 9 - J4 11 - R55 1 - U5 37 - U5 19 - U1 E17 - U1 B19 - R1 2 - C11 1 - C10 1 C1 1 - C3 1 - C5 1 + C72 1 + C73 1 + C80 1 + C79 1 + U1 Y20 + R57 2 C104 1 - R3 1 - L2 1 - R4 1 - R6 1 - R5 1 - U4 24 - U5 12 - J1 4 - U1 E9 - U1 G10 - U1 B11 - U4 7 + U1 B19 + U1 E17 C91 1 C90 1 - C13 1 R30 1 - C14 1 + J4 11 + J4 9 + J4 6 + J4 3 + U5 12 + R55 1 + R29 1 + U7 12 + U7 14 + R48 1 + J1 4 C35 1 C36 1 - U7 14 - U7 12 - C74 1 - C75 2 - R48 1 - C44 1 - C41 1 - C47 1 - C50 1 - R29 1 - C73 1 U6 12 - C72 1 U6 14 -Net 147 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - C7 1 + C14 1 + C13 1 + C10 1 + U5 37 + C81 1 + U1 E9 + C11 1 + R1 2 + U1 G10 + U1 B11 + C41 1 + U4 7 + R3 1 + U9 9 + R4 1 + U5 19 +Net 131 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" U4 38 - C8 1 L2 2 -Net 148 "" "" - U4 37 + C8 1 + C7 1 +Net 132 "" "" R2 1 -Net 149 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - U4 47 + U4 37 +Net 133 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" C9 1 L3 2 -Net 155 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + U4 47 +Net 139 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" L3 1 U4 31 C6 1 L1 2 -Net 156 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" - L1 1 - C4 1 +Net 140 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" C2 1 U4 13 -Net 159 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD" - R9 1 + L1 1 + C4 1 +Net 143 "/Ethernet Phy/MAG_SHIELD" "MAG_SHIELD" C12 1 + R9 1 J4 14 J4 13 -Net 160 "/Ethernet Phy/ETH_LED1" "ETH_LED1" +Net 144 "/Ethernet Phy/ETH_LED1" "ETH_LED1" U4 27 R8 2 -Net 161 "/Ethernet Phy/ETH_LED0" "ETH_LED0" +Net 145 "/Ethernet Phy/ETH_LED0" "ETH_LED0" U4 26 R7 2 -Net 162 "/Ethernet Phy/MAG_RX-" "MAG_RX-" +Net 146 "/Ethernet Phy/MAG_RX-" "MAG_RX-" R6 2 - U4 32 J4 8 -Net 163 "" "" - J4 12 + U4 32 +Net 147 "" "" R8 1 -Net 164 "" "" + J4 12 +Net 148 "" "" J4 10 R7 1 -Net 165 "/Ethernet Phy/MAG_TX-" "MAG_TX-" +Net 149 "/Ethernet Phy/MAG_TX-" "MAG_TX-" + J4 2 R4 2 U4 40 - J4 2 -Net 166 "/Ethernet Phy/MAG_RX+" "MAG_RX+" +Net 150 "/Ethernet Phy/MAG_RX+" "MAG_RX+" R5 2 - J4 7 U4 33 -Net 167 "/Ethernet Phy/MAG_TX+" "MAG_TX+" + J4 7 +Net 151 "/Ethernet Phy/MAG_TX+" "MAG_TX+" J4 1 - R3 2 U4 41 -Net 168 "" "" - U7 11 - R49 2 -Net 169 "" "" - L7 1 - J7 1 -Net 170 "" "" - U6 11 - R51 2 -Net 171 "" "" - U6 10 - R52 2 -Net 172 "" "" + R3 2 +Net 152 "" "" R50 2 U7 10 -Net 173 "/USB/USB_CASE_DEV" "USB_CASE_DEV" - R15 1 - C38 1 - J7 7 - J7 6 - J7 8 - J7 9 -Net 174 "" "" - J7 4 +Net 153 "" "" + U6 11 + R51 2 +Net 154 "" "" + U6 10 + R52 2 +Net 155 "" "" + U7 11 + R49 2 +Net 156 "" "" J7 5 -Net 175 "/USB/USB_CASE_HOST" "USB_CASE_HOST" - C16 1 - R10 1 - J5 S4 - J5 S3 - J5 S2 - J5 S1 -Net 176 "" "" - L5 1 + J7 4 +Net 157 "/USB/USBD_D+" "USBD_D+" + V3 1 + V3 1 + J7 3 + R53 2 + R55 2 + R49 1 +Net 158 "" "" J5 4 -Net 177 "" "" + L5 1 +Net 159 "" "" J5 1 L4 2 -Net 178 "" "" +Net 160 "" "" L4 1 F1 1 -Net 179 "+5V" "+5V" +Net 161 "+5V" "+5V" + U15 5 C96 1 C97 1 R39 1 - U15 5 - F1 2 C98 1 -Net 180 "/USB/USBD_D+" "USBD_D+" - R49 1 - R55 2 - V3 1 - V3 1 - R53 2 - J7 3 -Net 181 "/USB/USBD_D-" "USBD_D-" - R50 1 - R54 2 + F1 2 +Net 162 "" "" + J7 1 + L7 1 +Net 163 "/USB/USBD_D-" "USBD_D-" V4 1 V4 1 J7 2 -Net 182 "/USB/USBA_D-" "USBA_D-" - R52 1 - J5 2 - V2 1 + R50 1 + R54 2 +Net 164 "/USB/USBA_D-" "USBA_D-" R46 2 V2 1 -Net 183 "/USB/USBA_D+" "USBA_D+" - V1 1 - V1 1 + V2 1 + J5 2 + R52 1 +Net 165 "/USB/USBA_D+" "USBA_D+" J5 3 R51 1 R48 2 R47 2 -Net 184 "" "" - U15 1 + V1 1 + V1 1 +Net 166 "/USB/USB_CASE_HOST" "USB_CASE_HOST" + J5 S2 + J5 S3 + J5 S4 + R10 1 + J5 S1 + C16 1 +Net 167 "/USB/USB_CASE_DEV" "USB_CASE_DEV" + J7 6 + J7 7 + J7 8 + J7 9 + R15 1 + C38 1 +Net 168 "" "" L10 1 -Net 185 "/PSU/VFB2.5" "VFB2.5" - R43 2 - R42 1 - C101 2 - U10 9 -Net 186 "/PSU/1.2V_EN" "1.2V_EN" + U15 1 +Net 169 "/PSU/1.2V_EN" "1.2V_EN" + U9 3 U12 1 R58 1 - U9 3 -Net 187 "/PSU/VFB3.3" "VFB3.3" - R25 1 +Net 170 "/PSU/VFB2.5" "VFB2.5" + U10 9 + R42 1 + C101 2 + R43 2 +Net 171 "/PSU/VFB3.3" "VFB3.3" R26 2 - U11 5 + R25 1 C79 2 -Net 188 "/PSU/3.3V_EN" "3.3V_EN" - U11 1 + U11 5 +Net 172 "/PSU/3.3V_EN" "3.3V_EN" U9 5 + U11 1 R56 1 -Net 189 "/PSU/lout_5.0" "lout_5.0" +Net 173 "/PSU/lout_5.0" "lout_5.0" + U9 14 R35 1 U16 3 - U9 14 -Net 190 "/PSU/lout_2.5" "lout_2.5" +Net 174 "/PSU/lout_2.5" "lout_2.5" U17 3 R44 1 U9 11 -Net 191 "/PSU/AVR_SCK" "AVR_SCK" - U9 1 - P1 2 -Net 192 "/PSU/AVR_MISO" "AVR_MISO" - P1 3 - U9 20 -Net 193 "/PSU/AVR_MOSI" "AVR_MOSI" - P1 4 - U9 16 -Net 194 "" "" - R40 2 +Net 175 "" "" C100 1 -Net 195 "/PSU/Iout_1.2" "Iout_1.2" - R33 1 + R40 2 +Net 176 "/PSU/Iout_1.2" "Iout_1.2" U9 2 + R33 1 U14 3 -Net 196 "/PSU/5V_EN" "5V_EN" +Net 177 "/PSU/5V_EN" "5V_EN" U9 15 - R37 1 U15 4 -Net 197 "/PSU/2.5V_EN" "2.5V_EN" + R37 1 +Net 178 "/PSU/2.5V_EN" "2.5V_EN" U10 1 R41 1 U9 12 -Net 198 "+BATT" "+BATT" - U14 1 - R34 2 - U13 1 +Net 179 "+BATT" "+BATT" R32 2 + U13 1 U17 1 + R34 2 + U14 1 R45 2 U16 1 R36 2 -Net 199 "" "" +Net 180 "" "" R40 1 U10 10 -Net 200 "/PSU/SW_2.5" "SW_2.5" +Net 181 "/PSU/SW_2.5" "SW_2.5" U10 3 - L11 2 U10 4 -Net 201 "/PSU/lout_3.3" "lout_3.3" + L11 2 +Net 182 "/PSU/lout_3.3" "lout_3.3" U9 4 - U13 3 R31 1 -Net 202 "/PSU/SW_3.3" "SW_3.3" - L8 2 + U13 3 +Net 183 "/PSU/SW_3.3" "SW_3.3" U11 3 -Net 203 "/PSU/VFB1.2" "VFB1.2" + L8 2 +Net 184 "/PSU/VFB1.2" "VFB1.2" R27 1 + R28 2 U12 5 C83 2 - R28 2 -Net 204 "+1.2V" "+1.2V" - U1 K9 - U1 N12 - U1 M9 - U1 P9 - U1 J10 - U1 L10 - U1 N10 - C39 1 - C92 1 - U1 K11 - C93 1 - U1 M11 - U1 P11 - C76 1 - C42 1 +Net 185 "+1.2V" "+1.2V" U1 J12 - U1 L12 - C45 1 - C48 1 - U1 J8 - U1 N14 + C84 1 + C83 1 R28 1 + U1 K11 + U1 P11 + U1 M11 + C85 1 + C92 1 + U1 J10 + U1 P9 + U1 M9 + U1 K9 + L9 1 + U1 N12 + U1 L12 + U1 K13 + C42 1 + C48 1 + C76 1 + C39 1 U1 R14 + U1 N14 + U1 J8 + C45 1 U1 L14 U1 J14 - C83 1 - C84 1 - C85 1 - L9 1 - U1 K13 U1 P13 U1 M13 -Net 205 "/PSU/VFB5.0" "VFB5.0" + C93 1 + U1 N10 + U1 L10 +Net 186 "/PSU/VFB5.0" "VFB5.0" R39 2 R38 1 C96 2 U15 3 -Net 206 "/PSU/VIN_DC-DC-1.2" "VIN_DC-DC-1.2" - R34 1 - C82 1 +Net 187 "/PSU/VIN_DC-DC-1.2" "VIN_DC-DC-1.2" U12 4 - U14 6 R58 2 -Net 207 "/PSU/SW_1.2" "SW_1.2" - L9 2 + R34 1 + U14 6 + C82 1 +Net 188 "/PSU/SW_1.2" "SW_1.2" U12 3 -Net 210 "/PSU/VIN_DC-DC-3.3" "VIN_DC-DC-3.3" - C78 1 - U13 6 - R32 1 + L9 2 +Net 191 "/PSU/VIN_DC-DC-3.3" "VIN_DC-DC-3.3" U11 4 + U13 6 R56 2 -Net 221 "/PSU/VIN_DC-DC-2.5" "VIN_DC-DC-2.5" - U10 6 + R32 1 + C78 1 +Net 202 "/PSU/VIN_DC-DC-2.5" "VIN_DC-DC-2.5" U17 6 - U10 7 R45 1 - U10 8 C99 1 -Net 222 "/PSU/AVR_RST" "AVR_RST" - U9 13 - R57 1 -Net 225 "/PSU/VIN_DC-DC-5.0" "VIN_DC-DC-5.0" + U10 6 + U10 7 + U10 8 +Net 205 "/PSU/VIN_DC-DC-5.0" "VIN_DC-DC-5.0" + U15 6 U16 6 C95 1 - U15 6 + R36 1 L10 2 R37 2 - R36 1 -Net 238 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ7" "R_M1_DQ7" - RP4 4 - U1 K22 -Net 239 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ6" "R_M1_DQ6" - U1 K21 - RP4 3 -Net 240 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ5" "R_M1_DQ5" - RP4 2 - U1 J22 -Net 241 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ4" "R_M1_DQ4" - RP4 1 - U1 J20 -Net 242 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CAS#" "R_M1_CAS#" - U1 H22 - RP3 4 -Net 243 "/FPGA Port 1, Port 3 DDR, USB/R_M1_WE#" "R_M1_WE#" - RP3 3 - U1 H19 -Net 244 "/FPGA Port 1, Port 3 DDR, USB/R_M1_LDM" "R_M1_LDM" - U1 L19 - RP3 2 -Net 245 "/FPGA Port 1, Port 3 DDR, USB/R_M1_LDQS" "R_M1_LDQS" - RP3 1 - U1 L20 -Net 246 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ3" "R_M1_DQ3" - U1 M22 - RP5 4 -Net 247 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ2" "R_M1_DQ2" - RP5 3 - U1 M21 -Net 248 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ1" "R_M1_DQ1" - U1 N22 - RP5 2 -Net 249 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ0" "R_M1_DQ0" - U1 N20 - RP5 1 -Net 250 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A11" "R_M1_A11" - U1 F19 - RP7 7 -Net 251 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A9" "R_M1_A9" - RP7 6 - U1 C22 -Net 252 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A8" "R_M1_A8" - U1 C20 - RP7 5 -Net 253 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A7" "R_M1_A7" - U1 E20 - RP6 8 -Net 254 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A6" "R_M1_A6" - RP6 7 - U1 K19 -Net 255 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A5" "R_M1_A5" - U1 K20 - RP6 6 -Net 256 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A4" "R_M1_A4" - U1 F20 - RP6 5 -Net 257 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A12" "R_M1_A12" - U1 D22 - RP7 8 -Net 258 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A10" "R_M1_A10" +Net 206 "/DBG_PRG/5V_USB" "5V_USB" + FB2 1 + J8 1 + C148 1 +Net 207 "/DBG_PRG/FTDI_USB_DP" "FTDI_USB_DP" + R71 2 + J8 3 +Net 208 "" "" + X1 2 + IC1 44 + C147 1 +Net 226 "" "" + X1 1 + IC1 43 + C146 1 +Net 227 "/DBG_PRG/VCC_USB" "VCC_USB" + R74 1 + IC1 4 + IC1 3 + R73 2 + IC1 42 + C150 1 + FB2 2 +Net 228 "/DBG_PRG/USB_CASE_FTDI" "USB_CASE_FTDI" + J8 7 + J8 8 + J8 6 + R69 1 + J8 9 + C145 1 +Net 229 "" "" + J8 5 + FB1 1 + J8 4 +Net 230 "/DBG_PRG/FTDI_USB_DM" "FTDI_USB_DM" + R70 2 + J8 2 +Net 231 "" "" + IC1 46 + R74 2 + C151 1 +Net 232 "" "" + R75 2 + IC1 10 +Net 233 "" "" + R73 1 + IC1 2 +Net 234 "" "" + IC1 5 + R72 1 +Net 235 "" "" + IC1 8 + R70 1 +Net 236 "" "" + R71 1 + R72 2 + IC1 7 +Net 237 "" "" + R76 2 + IC1 26 +Net 238 "/DBG_PRG/3.3V_USB" "3.3V_USB" + IC1 6 + C149 2 + IC1 14 + IC1 31 +Net 257 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A10" "R_M1_A10" RP2 4 U1 G19 -Net 259 "/FPGA Port 1, Port 3 DDR, USB/R_M1_BA1" "R_M1_BA1" - RP2 3 +Net 258 "/FPGA Port 1, Port 3 DDR, USB/R_M1_BA1" "R_M1_BA1" U1 K17 + RP2 3 +Net 259 "/FPGA Port 1, Port 3 DDR, USB/R_M1_BA0" "R_M1_BA0" + RP2 2 + U1 J17 Net 260 "/FPGA Port 1, Port 3 DDR, USB/R_M1_RAS#" "R_M1_RAS#" RP2 1 U1 H21 Net 261 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A2" "R_M1_A2" - U1 E22 RP1 3 + U1 E22 Net 262 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A3" "R_M1_A3" - U1 G20 RP1 4 + U1 G20 Net 263 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A1" "R_M1_A1" RP1 2 U1 F22 Net 264 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A0" "R_M1_A0" RP1 1 U1 F21 -Net 265 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ7" "R_M0_DQ7" - U1 K1 - RP12 4 -Net 266 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ6" "R_M0_DQ6" - RP12 3 - U1 K2 -Net 267 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ5" "R_M0_DQ5" - U1 J1 - RP12 2 -Net 268 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ4" "R_M0_DQ4" - U1 J3 - RP12 1 -Net 269 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A8" "R_M0_A8" - RP18 4 - U1 E3 -Net 270 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A9" "R_M0_A9" - U1 E1 - RP18 3 -Net 271 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ3" "R_M0_DQ3" - RP13 4 - U1 M1 -Net 272 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ2" "R_M0_DQ2" - U1 M2 - RP13 3 -Net 273 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ1" "R_M0_DQ1" - U1 N1 - RP13 2 -Net 274 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ0" "R_M0_DQ0" - RP13 1 - U1 N3 -Net 275 "/FPGA Port 1, Port 3 DDR, USB/R_M0_CAS#" "R_M0_CAS#" - RP16 4 - U1 K4 -Net 276 "/FPGA Port 1, Port 3 DDR, USB/R_M0_WE#" "R_M0_WE#" - RP16 3 - U1 F2 -Net 277 "/FPGA Port 1, Port 3 DDR, USB/R_M0_LDM" "R_M0_LDM" - U1 L4 - RP16 2 -Net 278 "/FPGA Port 1, Port 3 DDR, USB/R_M0_LDQS" "R_M0_LDQS" - U1 L3 - RP16 1 -Net 279 "/FPGA Port 1, Port 3 DDR, USB/R_M0_RAS#" "R_M0_RAS#" - RP15 1 - U1 K5 -Net 280 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A10" "R_M0_A10" - U1 G4 - RP15 4 -Net 281 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A11" "R_M0_A11" - U1 C1 - RP18 2 -Net 282 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A12" "R_M0_A12" - RP18 1 - U1 D1 -Net 283 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A4" "R_M0_A4" - RP17 4 - U1 F3 -Net 284 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A5" "R_M0_A5" - RP17 3 - U1 K3 -Net 285 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A6" "R_M0_A6" - RP17 2 - U1 J4 -Net 286 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A7" "R_M0_A7" - U1 H6 - RP17 1 -Net 287 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ13" "R_M1_DQ13" - U1 U22 - RP8 6 -Net 288 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ12" "R_M1_DQ12" - U1 U20 - RP8 5 -Net 289 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ11" "R_M0_DQ11" - RP11 4 - U1 R1 -Net 290 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ10" "R_M0_DQ10" - RP11 3 - U1 R3 -Net 291 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ9" "R_M0_DQ9" - RP11 2 - U1 P1 -Net 292 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ8" "R_M0_DQ8" - U1 P2 - RP11 1 -Net 293 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CS#" "R_M1_CS#" +Net 265 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CS#" "R_M1_CS#" R20 1 U1 H16 -Net 294 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ15" "R_M0_DQ15" - RP10 4 - U1 V1 -Net 295 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ14" "R_M0_DQ14" - RP10 3 - U1 V2 -Net 296 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ13" "R_M0_DQ13" - RP10 2 - U1 U1 -Net 297 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ12" "R_M0_DQ12" - RP10 1 - U1 U3 -Net 323 "/FPGA Port 1, Port 3 DDR, USB/R_M0_UDQS" "R_M0_UDQS" - U1 T2 - R22 1 -Net 333 "/FPGA Port 1, Port 3 DDR, USB/R_M1_BA0" "R_M1_BA0" - RP2 2 - U1 J17 -Net 341 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ15" "R_M1_DQ15" - RP8 8 - U1 V22 -Net 348 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CKE" "R_M1_CKE" - R17 1 +Net 266 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CKE" "R_M1_CKE" U1 D21 -Net 349 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ10" "R_M1_DQ10" + R17 1 +Net 267 "/FPGA Port 1, Port 3 DDR, USB/R_M1_CAS#" "R_M1_CAS#" + U1 H22 + RP3 4 +Net 268 "/FPGA Port 1, Port 3 DDR, USB/R_M1_WE#" "R_M1_WE#" + RP3 3 + U1 H19 +Net 269 "/FPGA Port 1, Port 3 DDR, USB/R_M1_LDM" "R_M1_LDM" + RP3 2 + U1 L19 +Net 270 "/FPGA Port 1, Port 3 DDR, USB/R_M1_LDQS" "R_M1_LDQS" + U1 L20 + RP3 1 +Net 271 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A7" "R_M1_A7" + RP6 8 + U1 E20 +Net 272 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A6" "R_M1_A6" + RP6 7 + U1 K19 +Net 273 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A5" "R_M1_A5" + U1 K20 + RP6 6 +Net 274 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A4" "R_M1_A4" + RP6 5 + U1 F20 +Net 275 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A12" "R_M1_A12" + U1 D22 + RP7 8 +Net 276 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A11" "R_M1_A11" + RP7 7 + U1 F19 +Net 277 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A9" "R_M1_A9" + RP7 6 + U1 C22 +Net 278 "/FPGA Port 1, Port 3 DDR, USB/R_M1_A8" "R_M1_A8" + RP7 5 + U1 C20 +Net 294 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ12" "R_M1_DQ12" + U1 U20 + RP8 5 +Net 296 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ10" "R_M1_DQ10" RP9 7 U1 R20 -Net 351 "/FPGA Port 1, Port 3 DDR, USB/R_M1_UDM" "R_M1_UDM" - U1 M20 +Net 298 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ0" "R_M1_DQ0" + U1 N20 + RP5 1 +Net 299 "/FPGA Port 1, Port 3 DDR, USB/R_M1_UDM" "R_M1_UDM" R18 1 -Net 353 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ11" "R_M1_DQ11" - RP9 8 - U1 R22 -Net 354 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ9" "R_M1_DQ9" - RP9 6 - U1 P22 -Net 357 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ14" "R_M1_DQ14" + U1 M20 +Net 300 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ4" "R_M1_DQ4" + RP4 1 + U1 J20 +Net 341 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ14" "R_M1_DQ14" U1 V21 RP8 7 -Net 358 "/FPGA Port 1, Port 3 DDR, USB/R_M1_UDQS" "R_M1_UDQS" - R19 1 +Net 342 "/FPGA Port 1, Port 3 DDR, USB/R_M1_UDQS" "R_M1_UDQS" U1 T21 -Net 359 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ8" "R_M1_DQ8" + R19 1 +Net 343 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ8" "R_M1_DQ8" RP9 5 U1 P21 -Net 360 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A3" "R_M0_A3" - U1 K6 - RP14 4 -Net 361 "/FPGA Port 1, Port 3 DDR, USB/R_M0_BA0" "R_M0_BA0" - RP15 2 - U1 G3 +Net 344 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ2" "R_M1_DQ2" + RP5 3 + U1 M21 +Net 345 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ6" "R_M1_DQ6" + RP4 3 + U1 K21 +Net 350 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ15" "R_M1_DQ15" + U1 V22 + RP8 8 +Net 351 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ13" "R_M1_DQ13" + RP8 6 + U1 U22 +Net 353 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ11" "R_M1_DQ11" + U1 R22 + RP9 8 +Net 354 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ9" "R_M1_DQ9" + U1 P22 + RP9 6 +Net 355 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ1" "R_M1_DQ1" + U1 N22 + RP5 2 +Net 356 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ3" "R_M1_DQ3" + RP5 4 + U1 M22 +Net 358 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ7" "R_M1_DQ7" + U1 K22 + RP4 4 +Net 359 "/FPGA Port 1, Port 3 DDR, USB/R_M1_DQ5" "R_M1_DQ5" + U1 J22 + RP4 2 +Net 361 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A7" "R_M0_A7" + U1 H6 + RP17 1 Net 362 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A2" "R_M0_A2" - U1 H5 RP14 3 -Net 363 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A0" "R_M0_A0" + U1 H5 +Net 363 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A6" "R_M0_A6" + RP17 2 + U1 J4 +Net 364 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ12" "R_M0_DQ12" + U1 U3 + RP10 1 +Net 365 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A3" "R_M0_A3" + RP14 4 + U1 K6 +Net 366 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A10" "R_M0_A10" + RP15 4 + U1 G4 +Net 367 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ8" "R_M0_DQ8" + U1 P2 + RP11 1 +Net 368 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ2" "R_M0_DQ2" + U1 M2 + RP13 3 +Net 369 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ6" "R_M0_DQ6" + U1 K2 + RP12 3 +Net 370 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A0" "R_M0_A0" U1 H2 RP14 1 -Net 368 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A1" "R_M0_A1" +Net 375 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ15" "R_M0_DQ15" + U1 V1 + RP10 4 +Net 376 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ13" "R_M0_DQ13" + RP10 2 + U1 U1 +Net 378 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ11" "R_M0_DQ11" + U1 R1 + RP11 4 +Net 379 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ10" "R_M0_DQ10" + U1 R3 + RP11 3 +Net 381 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ0" "R_M0_DQ0" + U1 N3 + RP13 1 +Net 382 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A5" "R_M0_A5" + RP17 3 + U1 K3 +Net 383 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ4" "R_M0_DQ4" + RP12 1 + U1 J3 +Net 384 "/FPGA Port 1, Port 3 DDR, USB/R_M0_BA0" "R_M0_BA0" + U1 G3 + RP15 2 +Net 385 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A4" "R_M0_A4" + RP17 4 + U1 F3 +Net 386 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A8" "R_M0_A8" + RP18 4 + U1 E3 +Net 391 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ14" "R_M0_DQ14" + U1 V2 + RP10 3 +Net 392 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ9" "R_M0_DQ9" + RP11 2 + U1 P1 +Net 393 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ1" "R_M0_DQ1" + RP13 2 + U1 N1 +Net 394 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ3" "R_M0_DQ3" + U1 M1 + RP13 4 +Net 396 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ7" "R_M0_DQ7" + U1 K1 + RP12 4 +Net 397 "/FPGA Port 1, Port 3 DDR, USB/R_M0_DQ5" "R_M0_DQ5" + RP12 2 + U1 J1 +Net 398 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A1" "R_M0_A1" RP14 2 U1 H1 -Net 369 "/FPGA Port 1, Port 3 DDR, USB/R_M0_BA1" "R_M0_BA1" +Net 399 "/FPGA Port 1, Port 3 DDR, USB/R_M0_BA1" "R_M0_BA1" U1 G1 RP15 3 -Net 372 "/FPGA Port 1, Port 3 DDR, USB/R_M0_CKE" "R_M0_CKE" +Net 401 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A9" "R_M0_A9" + RP18 3 + U1 E1 +Net 402 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A12" "R_M0_A12" + U1 D1 + RP18 1 +Net 403 "/FPGA Port 1, Port 3 DDR, USB/R_M0_A11" "R_M0_A11" + U1 C1 + RP18 2 +Net 405 "/FPGA Port 1, Port 3 DDR, USB/R_M0_CAS#" "R_M0_CAS#" + U1 K4 + RP16 4 +Net 406 "/FPGA Port 1, Port 3 DDR, USB/R_M0_WE#" "R_M0_WE#" + RP16 3 + U1 F2 +Net 407 "/FPGA Port 1, Port 3 DDR, USB/R_M0_LDM" "R_M0_LDM" + U1 L4 + RP16 2 +Net 408 "/FPGA Port 1, Port 3 DDR, USB/R_M0_LDQS" "R_M0_LDQS" + U1 L3 + RP16 1 +Net 409 "/FPGA Port 1, Port 3 DDR, USB/R_M0_RAS#" "R_M0_RAS#" + RP15 1 + U1 K5 +Net 410 "/FPGA Port 1, Port 3 DDR, USB/R_M0_UDQS" "R_M0_UDQS" + R22 1 + U1 T2 +Net 411 "/FPGA Port 1, Port 3 DDR, USB/R_M0_CKE" "R_M0_CKE" R24 1 U1 D2 -Net 373 "/FPGA Port 1, Port 3 DDR, USB/R_M0_UDM" "R_M0_UDM" +Net 412 "/FPGA Port 1, Port 3 DDR, USB/R_M0_UDM" "R_M0_UDM" R23 1 U1 M3 -Net 376 "" "" +Net 415 "" "" R30 2 U1 Y22 -Net 379 "" "" +Net 418 "" "" R29 2 U1 AA1 -Net 422 "" "" +Net 461 "" "" U22 3 U22 1 C117 1 -Net 423 "" "" - U23 3 +Net 462 "" "" C118 1 U23 1 -Net 424 "" "" + U23 3 +Net 463 "" "" + U23 5 R68 1 R67 2 C125 2 - U23 5 -Net 425 "" "" - U19 4 +Net 464 "" "" C109 1 -Net 426 "" "" - U22 4 + U19 4 +Net 465 "" "" C120 1 -Net 427 "" "" + U22 4 +Net 466 "" "" + C124 2 + R65 2 U22 5 R66 1 - R65 2 - C124 2 -Net 428 "" "" - C107 1 +Net 467 "" "" U20 3 U20 1 -Net 429 "" "" + C107 1 +Net 468 "" "" U23 4 C121 1 -Net 430 "" "" - U20 4 +Net 469 "" "" C110 1 -Net 431 "" "" - R64 1 + U20 4 +Net 470 "" "" R63 2 + R64 1 C113 2 U20 5 -Net 432 "" "" +Net 471 "" "" + C105 1 U18 1 U18 3 - C105 1 -Net 433 "" "" +Net 472 "" "" C108 1 U18 4 -Net 434 "" "" +Net 473 "" "" C106 1 - U19 3 U19 1 -Net 435 "" "" + U19 3 +Net 474 "" "" U19 5 - C112 2 - R61 2 R62 1 -Net 436 "" "" + R61 2 + C112 2 +Net 475 "" "" U18 5 - C111 2 - R59 2 R60 1 -Net 455 "/DDR Banks/M0_DQ8" "M0_DQ8" - U2 54 - RP11 8 -Net 456 "/DDR Banks/M0_DQ9" "M0_DQ9" - RP11 7 - U2 56 -Net 457 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ10" "M0_DQ10" - RP11 6 - U2 57 -Net 458 "/DDR Banks/M0_DQ11" "M0_DQ11" - U2 59 - RP11 5 -Net 459 "/DDR Banks/M0_DQ12" "M0_DQ12" - RP10 8 - U2 60 -Net 460 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ13" "M0_DQ13" - U2 62 - RP10 7 -Net 461 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ14" "M0_DQ14" - RP10 6 - U2 63 -Net 462 "/DDR Banks/M0_DQ15" "M0_DQ15" - U2 65 - RP10 5 -Net 463 "/DDR Banks/M0_A0" "M0_A0" - RP14 8 - U2 29 -Net 464 "/DDR Banks/M0_A1" "M0_A1" - U2 30 - RP14 7 -Net 465 "/FPGA Port 1, Port 3 DDR, USB/M0_A2" "M0_A2" - U2 31 - RP14 6 -Net 466 "/FPGA Port 1, Port 3 DDR, USB/M0_A3" "M0_A3" - U2 32 - RP14 5 -Net 467 "/FPGA Port 1, Port 3 DDR, USB/M0_A4" "M0_A4" - RP17 5 - U2 35 -Net 468 "/FPGA Port 1, Port 3 DDR, USB/M0_A5" "M0_A5" - U2 36 - RP17 6 -Net 469 "/DDR Banks/M0_A6" "M0_A6" - RP17 7 - U2 37 -Net 470 "/DDR Banks/M0_A7" "M0_A7" - U2 38 - RP17 8 -Net 471 "/DDR Banks/M0_A8" "M0_A8" - U2 39 - RP18 5 -Net 472 "/FPGA Port 1, Port 3 DDR, USB/M0_A9" "M0_A9" - RP18 6 - U2 40 -Net 473 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ7" "M1_DQ7" - RP4 5 - U3 13 -Net 474 "/DDR Banks/M1_DQ8" "M1_DQ8" - RP9 4 - U3 54 -Net 475 "/DDR Banks/M1_DQ9" "M1_DQ9" - RP9 3 - U3 56 -Net 476 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ10" "M1_DQ10" - RP9 2 - U3 57 -Net 477 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ11" "M1_DQ11" - RP9 1 - U3 59 -Net 478 "/DDR Banks/M1_DQ12" "M1_DQ12" - RP8 4 - U3 60 -Net 479 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ13" "M1_DQ13" - RP8 3 + R59 2 + C111 2 +Net 494 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ13" "M1_DQ13" U3 62 -Net 480 "/DDR Banks/M1_DQ14" "M1_DQ14" + RP8 3 +Net 495 "/DDR Banks/M1_DQ14" "M1_DQ14" U3 63 RP8 2 -Net 481 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ15" "M1_DQ15" - U3 65 +Net 496 "/DDR Banks/M1_DQ15" "M1_DQ15" RP8 1 -Net 482 "/DDR Banks/M0_DQ0" "M0_DQ0" - RP13 8 + U3 65 +Net 497 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ0" "M0_DQ0" U2 2 -Net 483 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ1" "M0_DQ1" - RP13 7 + RP13 8 +Net 498 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ1" "M0_DQ1" U2 4 -Net 484 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ2" "M0_DQ2" + RP13 7 +Net 499 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ2" "M0_DQ2" U2 5 RP13 6 -Net 485 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ3" "M0_DQ3" +Net 500 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ3" "M0_DQ3" RP13 5 U2 7 -Net 486 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ4" "M0_DQ4" - U2 8 +Net 501 "/DDR Banks/M0_DQ4" "M0_DQ4" RP12 8 -Net 487 "/DDR Banks/M0_DQ5" "M0_DQ5" - U2 10 + U2 8 +Net 502 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ5" "M0_DQ5" RP12 7 -Net 488 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ6" "M0_DQ6" - RP12 6 + U2 10 +Net 503 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ6" "M0_DQ6" U2 11 -Net 489 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ7" "M0_DQ7" - RP12 5 + RP12 6 +Net 504 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ7" "M0_DQ7" U2 13 -Net 490 "/FPGA Port 1, Port 3 DDR, USB/M0_A10" "M0_A10" - RP15 5 - U2 28 -Net 491 "/DDR Banks/M0_A11" "M0_A11" - RP18 7 - U2 41 -Net 492 "/DDR Banks/M0_A12" "M0_A12" - RP18 8 - U2 42 -Net 493 "/DDR Banks/M1_A0" "M1_A0" - RP1 8 - U3 29 -Net 494 "/FPGA Port 1, Port 3 DDR, USB/M1_A1" "M1_A1" - U3 30 - RP1 7 -Net 495 "/FPGA Port 1, Port 3 DDR, USB/M1_A2" "M1_A2" - RP1 6 - U3 31 -Net 496 "/DDR Banks/M1_A3" "M1_A3" - RP1 5 - U3 32 -Net 497 "/FPGA Port 1, Port 3 DDR, USB/M1_A4" "M1_A4" - RP6 4 - U3 35 -Net 498 "/FPGA Port 1, Port 3 DDR, USB/M1_A5" "M1_A5" - U3 36 - RP6 3 -Net 499 "/FPGA Port 1, Port 3 DDR, USB/M1_A6" "M1_A6" - RP6 2 - U3 37 -Net 500 "/FPGA Port 1, Port 3 DDR, USB/M1_A7" "M1_A7" - U3 38 - RP6 1 -Net 501 "/DDR Banks/M1_A8" "M1_A8" - U3 39 - RP7 4 -Net 502 "/FPGA Port 1, Port 3 DDR, USB/M1_A9" "M1_A9" - U3 40 - RP7 3 -Net 503 "/DDR Banks/M1_A10" "M1_A10" - RP2 5 - U3 28 -Net 504 "/DDR Banks/M1_A11" "M1_A11" - RP7 2 - U3 41 -Net 505 "/FPGA Port 1, Port 3 DDR, USB/M1_A12" "M1_A12" - RP7 1 - U3 42 -Net 506 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_48" "FPGA_BANK0_IO_48" - P2 40 - U1 W8 -Net 508 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_50" "FPGA_BANK0_IO_50" - U1 W9 - P2 38 -Net 510 "/FPGA GPIOS/FPGA_BANK0_IO_52" "FPGA_BANK0_IO_52" - U1 V9 - P2 37 -Net 514 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_56" "FPGA_BANK0_IO_56" - U1 U10 - P2 39 -Net 523 "/FPGA GPIOS/FPGA_BANK0_IO_29" "FPGA_BANK0_IO_29" - U1 AB16 - P2 18 -Net 524 "/FPGA GPIOS/FPGA_BANK0_IO_30" "FPGA_BANK0_IO_30" - P2 20 - U1 W14 -Net 526 "/FPGA GPIOS/FPGA_BANK0_IO_32" "FPGA_BANK0_IO_32" - U1 Y15 - P2 26 -Net 527 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_33" "FPGA_BANK0_IO_33" - P2 24 - U1 AB15 -Net 530 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_36" "FPGA_BANK0_IO_36" - U1 T14 - P2 30 -Net 533 "/FPGA GPIOS/FPGA_BANK0_IO_39" "FPGA_BANK0_IO_39" - U1 AB13 - P2 23 -Net 534 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_40" "FPGA_BANK0_IO_40" - P2 32 - U1 Y11 -Net 537 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_43" "FPGA_BANK0_IO_43" - U1 V11 - P2 34 -Net 538 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_44" "FPGA_BANK0_IO_44" - P2 31 - U1 W11 -Net 539 "/FPGA GPIOS/FPGA_BANK0_IO_45" "FPGA_BANK0_IO_45" - P2 35 - U1 Y9 -Net 540 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_46" "FPGA_BANK0_IO_46" - U1 W10 - P2 36 -Net 541 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_47" "FPGA_BANK0_IO_47" - U1 Y10 - P2 33 -Net 542 "/DDR Banks/M1_BA0" "M1_BA0" - RP2 7 - U3 26 -Net 543 "/DDR Banks/M1_BA1" "M1_BA1" - RP2 6 - U3 27 -Net 544 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ0" "M1_DQ0" + RP12 5 +Net 505 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ8" "M0_DQ8" + U2 54 + RP11 8 +Net 506 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ9" "M0_DQ9" + RP11 7 + U2 56 +Net 507 "/DDR Banks/M0_DQ10" "M0_DQ10" + U2 57 + RP11 6 +Net 508 "/DDR Banks/M0_DQ11" "M0_DQ11" + RP11 5 + U2 59 +Net 509 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ12" "M0_DQ12" + U2 60 + RP10 8 +Net 510 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ13" "M0_DQ13" + RP10 7 + U2 62 +Net 511 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ0" "M1_DQ0" U3 2 RP5 8 -Net 545 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ1" "M1_DQ1" +Net 512 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ1" "M1_DQ1" RP5 7 U3 4 -Net 546 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ2" "M1_DQ2" - U3 5 +Net 513 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ2" "M1_DQ2" RP5 6 -Net 547 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ3" "M1_DQ3" + U3 5 +Net 514 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ3" "M1_DQ3" U3 7 RP5 5 -Net 548 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ4" "M1_DQ4" - U3 8 +Net 515 "/DDR Banks/M1_DQ4" "M1_DQ4" RP4 8 -Net 549 "/DDR Banks/M1_DQ5" "M1_DQ5" - U3 10 + U3 8 +Net 516 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ5" "M1_DQ5" RP4 7 -Net 550 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ6" "M1_DQ6" - U3 11 + U3 10 +Net 517 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ6" "M1_DQ6" RP4 6 -Net 551 "/DDR Banks/M0_BA0" "M0_BA0" - RP15 7 - U2 26 -Net 552 "/FPGA Port 1, Port 3 DDR, USB/M0_BA1" "M0_BA1" - RP15 6 - U2 27 -Net 553 "/FPGA, Port0, Port2, PROG IF/NF_D6" "NF_D6" - U1 A11 - U5 43 -Net 554 "/FPGA, Port0, Port2, PROG IF/NF_D7" "NF_D7" - U1 D11 - U5 44 -Net 555 "/Non volatile memories/SPI_DQ0" "SPI_DQ0" - U1 AB20 - U8 5 -Net 556 "/FPGA, Port0, Port2, PROG IF/PROG_MISO1" "PROG_MISO1" - U1 AA20 - U8 2 -Net 557 "/FPGA, Port0, Port2, PROG IF/PROG_MISO2" "PROG_MISO2" - U8 3 - U1 U14 -Net 558 "/FPGA, Port0, Port2, PROG IF/PROG_MISO3" "PROG_MISO3" - U8 7 - U1 U13 -Net 559 "/FPGA, Port0, Port2, PROG IF/SD_DAT0" "SD_DAT0" - J1 7 - U1 A18 -Net 560 "/Non volatile memories/SD_DAT1" "SD_DAT1" - J1 8 - U1 B18 -Net 561 "/FPGA, Port0, Port2, PROG IF/SD_DAT2" "SD_DAT2" - J1 1 - U1 A16 -Net 562 "/Non volatile memories/SD_DAT3" "SD_DAT3" - U1 B16 - J1 2 -Net 563 "/Non volatile memories/NF_D0" "NF_D0" - U5 29 - U1 C12 -Net 564 "/FPGA, Port0, Port2, PROG IF/NF_D1" "NF_D1" - U5 30 - U1 D14 -Net 565 "/FPGA, Port0, Port2, PROG IF/NF_D2" "NF_D2" - U1 A13 - U5 31 -Net 566 "/Non volatile memories/NF_D3" "NF_D3" - U1 B12 - U5 32 -Net 567 "/FPGA, Port0, Port2, PROG IF/NF_D4" "NF_D4" - U1 A12 - U5 41 -Net 568 "/Non volatile memories/NF_D5" "NF_D5" - U1 C11 - U5 42 -Net 569 "/FPGA, Port0, Port2, PROG IF/ETH_TXD0" "ETH_TXD0" - U4 17 - U1 D10 -Net 570 "/FPGA, Port0, Port2, PROG IF/ETH_TXD1" "ETH_TXD1" - U1 C9 - U4 18 -Net 571 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" - U4 19 - U1 C10 -Net 572 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" - U4 20 - U1 A8 -Net 573 "/FPGA, Port0, Port2, PROG IF/ETH_RXD0" "ETH_RXD0" - U1 B6 - U4 6 -Net 574 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" - U4 5 - U1 A5 -Net 575 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" - U1 C6 - U4 4 -Net 576 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" - U4 3 - U1 C5 -Net 577 "/FPGA GPIOS/FPGA_BANK0_IO_2" "FPGA_BANK0_IO_2" - P2 25 - U1 T17 -Net 578 "/FPGA GPIOS/FPGA_BANK0_IO_3" "FPGA_BANK0_IO_3" - U1 Y19 - P2 10 -Net 580 "/FPGA GPIOS/FPGA_BANK0_IO_5" "FPGA_BANK0_IO_5" - U1 Y18 - P2 11 -Net 581 "/FPGA GPIOS/FPGA_BANK0_IO_6" "FPGA_BANK0_IO_6" - U1 T16 - P2 28 -Net 582 "/FPGA GPIOS/FPGA_BANK0_IO_7" "FPGA_BANK0_IO_7" - U1 T15 - P2 27 -Net 583 "/FPGA GPIOS/FPGA_BANK0_IO_8" "FPGA_BANK0_IO_8" - P2 1 - U1 U17 -Net 584 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_9" "FPGA_BANK0_IO_9" - U1 U16 - P2 4 -Net 585 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_10" "FPGA_BANK0_IO_10" - U1 V19 - P2 7 -Net 586 "/FPGA GPIOS/FPGA_BANK0_IO_11" "FPGA_BANK0_IO_11" - U1 V18 - P2 9 -Net 587 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_12" "FPGA_BANK0_IO_12" - P2 29 - U1 R16 -Net 589 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_14" "FPGA_BANK0_IO_14" - U1 V17 - P2 6 -Net 590 "/FPGA GPIOS/FPGA_BANK0_IO_15" "FPGA_BANK0_IO_15" - P2 8 - U1 W17 -Net 591 "/FPGA GPIOS/FPGA_BANK0_IO_16" "FPGA_BANK0_IO_16" - U1 U15 - P2 3 -Net 592 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_17" "FPGA_BANK0_IO_17" + U3 11 +Net 518 "/DDR Banks/M1_DQ7" "M1_DQ7" + RP4 5 + U3 13 +Net 519 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ8" "M1_DQ8" + RP9 4 + U3 54 +Net 520 "/DDR Banks/M1_DQ9" "M1_DQ9" + RP9 3 + U3 56 +Net 521 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ10" "M1_DQ10" + RP9 2 + U3 57 +Net 522 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ11" "M1_DQ11" + U3 59 + RP9 1 +Net 523 "/FPGA Port 1, Port 3 DDR, USB/M1_DQ12" "M1_DQ12" + RP8 4 + U3 60 +Net 524 "/FPGA Port 1, Port 3 DDR, USB/M1_A4" "M1_A4" + U3 35 + RP6 4 +Net 525 "/FPGA Port 1, Port 3 DDR, USB/M1_A5" "M1_A5" + U3 36 + RP6 3 +Net 526 "/FPGA Port 1, Port 3 DDR, USB/M1_A6" "M1_A6" + RP6 2 + U3 37 +Net 527 "/FPGA Port 1, Port 3 DDR, USB/M1_A7" "M1_A7" + RP6 1 + U3 38 +Net 528 "/FPGA Port 1, Port 3 DDR, USB/M1_A8" "M1_A8" + RP7 4 + U3 39 +Net 529 "/FPGA Port 1, Port 3 DDR, USB/M1_A9" "M1_A9" + U3 40 + RP7 3 +Net 530 "/FPGA Port 1, Port 3 DDR, USB/M1_A10" "M1_A10" + U3 28 + RP2 5 +Net 531 "/DDR Banks/M1_A11" "M1_A11" + U3 41 + RP7 2 +Net 532 "/FPGA Port 1, Port 3 DDR, USB/M1_A12" "M1_A12" + RP7 1 + U3 42 +Net 533 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ14" "M0_DQ14" + RP10 6 + U2 63 +Net 534 "/FPGA Port 1, Port 3 DDR, USB/M0_DQ15" "M0_DQ15" + RP10 5 + U2 65 +Net 535 "/FPGA Port 1, Port 3 DDR, USB/M0_A0" "M0_A0" + U2 29 + RP14 8 +Net 536 "/FPGA Port 1, Port 3 DDR, USB/M0_A1" "M0_A1" + RP14 7 + U2 30 +Net 537 "/FPGA Port 1, Port 3 DDR, USB/M0_A2" "M0_A2" + RP14 6 + U2 31 +Net 538 "/FPGA Port 1, Port 3 DDR, USB/M0_A3" "M0_A3" + U2 32 + RP14 5 +Net 539 "/DDR Banks/M0_A4" "M0_A4" + U2 35 + RP17 5 +Net 540 "/DDR Banks/M0_A5" "M0_A5" + U2 36 + RP17 6 +Net 541 "/FPGA Port 1, Port 3 DDR, USB/M0_A6" "M0_A6" + RP17 7 + U2 37 +Net 542 "/FPGA Port 1, Port 3 DDR, USB/M0_A7" "M0_A7" + RP17 8 + U2 38 +Net 543 "/DDR Banks/M0_A8" "M0_A8" + RP18 5 + U2 39 +Net 544 "/FPGA Port 1, Port 3 DDR, USB/M0_A9" "M0_A9" + U2 40 + RP18 6 +Net 545 "/DDR Banks/M0_A10" "M0_A10" + U2 28 + RP15 5 +Net 546 "/DDR Banks/M0_A11" "M0_A11" + U2 41 + RP18 7 +Net 547 "/FPGA Port 1, Port 3 DDR, USB/M0_A12" "M0_A12" + U2 42 + RP18 8 +Net 548 "/FPGA Port 1, Port 3 DDR, USB/M1_A0" "M1_A0" + U3 29 + RP1 8 +Net 549 "/FPGA Port 1, Port 3 DDR, USB/M1_A1" "M1_A1" + RP1 7 + U3 30 +Net 550 "/DDR Banks/M1_A2" "M1_A2" + U3 31 + RP1 6 +Net 551 "/FPGA Port 1, Port 3 DDR, USB/M1_A3" "M1_A3" + RP1 5 + U3 32 +Net 552 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_36" "FPGA_BANK0_IO_36" + U1 T14 + P2 30 +Net 555 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_39" "FPGA_BANK0_IO_39" + P2 23 + U1 AB13 +Net 556 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_40" "FPGA_BANK0_IO_40" + U1 Y11 + P2 32 +Net 559 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_43" "FPGA_BANK0_IO_43" + P2 34 + U1 V11 +Net 560 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_44" "FPGA_BANK0_IO_44" + U1 W11 + P2 31 +Net 561 "/FPGA GPIOS/FPGA_BANK0_IO_45" "FPGA_BANK0_IO_45" + P2 35 + U1 Y9 +Net 562 "/FPGA GPIOS/FPGA_BANK0_IO_46" "FPGA_BANK0_IO_46" + P2 36 + U1 W10 +Net 563 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_47" "FPGA_BANK0_IO_47" + U1 Y10 + P2 33 +Net 564 "/FPGA GPIOS/FPGA_BANK0_IO_48" "FPGA_BANK0_IO_48" + P2 40 + U1 W8 +Net 566 "/FPGA GPIOS/FPGA_BANK0_IO_50" "FPGA_BANK0_IO_50" + U1 W9 + P2 38 +Net 568 "/FPGA GPIOS/FPGA_BANK0_IO_52" "FPGA_BANK0_IO_52" + U1 V9 + P2 37 +Net 570 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_17" "FPGA_BANK0_IO_17" U1 V15 P2 13 -Net 593 "/FPGA GPIOS/FPGA_BANK0_IO_18" "FPGA_BANK0_IO_18" - P2 12 +Net 571 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_18" "FPGA_BANK0_IO_18" U1 AA18 -Net 595 "/FPGA GPIOS/FPGA_BANK0_IO_0" "FPGA_BANK0_IO_0" - P2 5 - U1 AA22 -Net 596 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_1" "FPGA_BANK0_IO_1" - P2 2 - U1 T18 -Net 597 "/FPGA GPIOS/FPGA_BANK0_IO_20" "FPGA_BANK0_IO_20" + P2 12 +Net 573 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_20" "FPGA_BANK0_IO_20" U1 Y17 P2 15 -Net 598 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_21" "FPGA_BANK0_IO_21" +Net 574 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_21" "FPGA_BANK0_IO_21" U1 AB17 P2 14 -Net 599 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_22" "FPGA_BANK0_IO_22" +Net 575 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_22" "FPGA_BANK0_IO_22" U1 AA14 P2 19 -Net 601 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_24" "FPGA_BANK0_IO_24" - U1 Y16 +Net 577 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_24" "FPGA_BANK0_IO_24" P2 16 -Net 602 "/FPGA GPIOS/FPGA_BANK0_IO_25" "FPGA_BANK0_IO_25" + U1 Y16 +Net 578 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_25" "FPGA_BANK0_IO_25" U1 W15 P2 22 -Net 604 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_27" "FPGA_BANK0_IO_27" +Net 580 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_27" "FPGA_BANK0_IO_27" U1 W13 P2 21 -Net 605 "/FPGA GPIOS/FPGA_BANK0_IO_28" "FPGA_BANK0_IO_28" +Net 581 "/FPGA GPIOS/FPGA_BANK0_IO_28" "FPGA_BANK0_IO_28" P2 17 U1 AA16 -Net 606 "/Image Sensor/IS_DOUT0" "IS_DOUT0" +Net 582 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_29" "FPGA_BANK0_IO_29" + U1 AB16 + P2 18 +Net 583 "/FPGA GPIOS/FPGA_BANK0_IO_30" "FPGA_BANK0_IO_30" + U1 W14 + P2 20 +Net 585 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_32" "FPGA_BANK0_IO_32" + U1 Y15 + P2 26 +Net 586 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_33" "FPGA_BANK0_IO_33" + P2 24 + U1 AB15 +Net 589 "/DDR Banks/M0_BA0" "M0_BA0" + U2 26 + RP15 7 +Net 590 "/DDR Banks/M0_BA1" "M0_BA1" + U2 27 + RP15 6 +Net 591 "/FPGA Port 1, Port 3 DDR, USB/M1_BA0" "M1_BA0" + U3 26 + RP2 7 +Net 592 "/FPGA Port 1, Port 3 DDR, USB/M1_BA1" "M1_BA1" + RP2 6 + U3 27 +Net 595 "/FPGA GPIOS/FPGA_BANK0_IO_56" "FPGA_BANK0_IO_56" + U1 U10 + P2 39 +Net 604 "/FPGA, Port0, Port2, PROG IF/NF_D6" "NF_D6" + U1 A11 + U5 43 +Net 605 "/Non volatile memories/NF_D7" "NF_D7" + U5 44 + U1 D11 +Net 606 "/Non volatile memories/SPI_DQ0" "SPI_DQ0" + U1 AB20 + U8 5 +Net 607 "/Non volatile memories/SPI_DQ1" "SPI_DQ1" + U8 2 + U1 AA20 +Net 608 "/FPGA, Port0, Port2, PROG IF/PROG_MISO2" "PROG_MISO2" + U1 U14 + U8 3 +Net 609 "/FPGA, Port0, Port2, PROG IF/PROG_MISO3" "PROG_MISO3" + U8 7 + U1 U13 +Net 610 "/Non volatile memories/SD_DAT0" "SD_DAT0" + U1 A18 + J1 7 +Net 611 "/Non volatile memories/SD_DAT1" "SD_DAT1" + U1 B18 + J1 8 +Net 612 "/FPGA, Port0, Port2, PROG IF/SD_DAT2" "SD_DAT2" + U1 A16 + J1 1 +Net 613 "/Non volatile memories/SD_DAT3" "SD_DAT3" + U1 B16 + J1 2 +Net 614 "/FPGA, Port0, Port2, PROG IF/NF_D0" "NF_D0" + U5 29 + U1 C12 +Net 615 "/FPGA, Port0, Port2, PROG IF/NF_D1" "NF_D1" + U1 D14 + U5 30 +Net 616 "/Non volatile memories/NF_D2" "NF_D2" + U1 A13 + U5 31 +Net 617 "/FPGA, Port0, Port2, PROG IF/NF_D3" "NF_D3" + U5 32 + U1 B12 +Net 618 "/FPGA, Port0, Port2, PROG IF/NF_D4" "NF_D4" + U5 41 + U1 A12 +Net 619 "/FPGA, Port0, Port2, PROG IF/NF_D5" "NF_D5" + U1 C11 + U5 42 +Net 620 "/FPGA, Port0, Port2, PROG IF/ETH_TXD0" "ETH_TXD0" + U4 17 + U1 D10 +Net 621 "/FPGA, Port0, Port2, PROG IF/ETH_TXD1" "ETH_TXD1" + U1 C9 + U4 18 +Net 622 "/FPGA, Port0, Port2, PROG IF/ETH_TXD2" "ETH_TXD2" + U4 19 + U1 C10 +Net 623 "/FPGA, Port0, Port2, PROG IF/ETH_TXD3" "ETH_TXD3" + U1 A8 + U4 20 +Net 624 "/FPGA, Port0, Port2, PROG IF/ETH_RXD0" "ETH_RXD0" + U4 6 + U1 B6 +Net 625 "/FPGA, Port0, Port2, PROG IF/ETH_RXD1" "ETH_RXD1" + U1 A5 + U4 5 +Net 626 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" + U1 C6 + U4 4 +Net 627 "/FPGA, Port0, Port2, PROG IF/ETH_RXD3" "ETH_RXD3" + U4 3 + U1 C5 +Net 628 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_0" "FPGA_BANK0_IO_0" + U1 AA22 + P2 5 +Net 629 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_1" "FPGA_BANK0_IO_1" + P2 2 + U1 T18 +Net 630 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_2" "FPGA_BANK0_IO_2" + U1 T17 + P2 25 +Net 631 "/FPGA GPIOS/FPGA_BANK0_IO_3" "FPGA_BANK0_IO_3" + P2 10 + U1 Y19 +Net 633 "/FPGA GPIOS/FPGA_BANK0_IO_5" "FPGA_BANK0_IO_5" + U1 Y18 + P2 11 +Net 634 "/FPGA GPIOS/FPGA_BANK0_IO_6" "FPGA_BANK0_IO_6" + P2 28 + U1 T16 +Net 635 "/FPGA GPIOS/FPGA_BANK0_IO_7" "FPGA_BANK0_IO_7" + P2 27 + U1 T15 +Net 636 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_8" "FPGA_BANK0_IO_8" + U1 U17 + P2 1 +Net 637 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_9" "FPGA_BANK0_IO_9" + U1 U16 + P2 4 +Net 638 "/FPGA GPIOS/FPGA_BANK0_IO_10" "FPGA_BANK0_IO_10" + P2 7 + U1 V19 +Net 639 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_11" "FPGA_BANK0_IO_11" + P2 9 + U1 V18 +Net 640 "/FPGA GPIOS/FPGA_BANK0_IO_12" "FPGA_BANK0_IO_12" + P2 29 + U1 R16 +Net 642 "/FPGA, Port0, Port2, PROG IF/FPGA_BANK0_IO_14" "FPGA_BANK0_IO_14" + U1 V17 + P2 6 +Net 643 "/FPGA GPIOS/FPGA_BANK0_IO_15" "FPGA_BANK0_IO_15" + P2 8 + U1 W17 +Net 644 "/FPGA GPIOS/FPGA_BANK0_IO_16" "FPGA_BANK0_IO_16" + P2 3 + U1 U15 +Net 645 "/FPGA, Port0, Port2, PROG IF/IS_DOUT0" "IS_DOUT0" U24 45 U1 AB12 -Net 607 "/Image Sensor/IS_DOUT1" "IS_DOUT1" +Net 646 "/Image Sensor/IS_DOUT1" "IS_DOUT1" U24 46 U1 AA12 -Net 608 "/Image Sensor/IS_DOUT2" "IS_DOUT2" - U24 47 +Net 647 "/Image Sensor/IS_DOUT2" "IS_DOUT2" U1 AB11 -Net 609 "/FPGA, Port0, Port2, PROG IF/IS_DOUT3" "IS_DOUT3" - U1 AB10 + U24 47 +Net 648 "/Image Sensor/IS_DOUT3" "IS_DOUT3" U24 48 -Net 610 "/Image Sensor/IS_DOUT4" "IS_DOUT4" - U24 1 + U1 AB10 +Net 649 "/FPGA, Port0, Port2, PROG IF/IS_DOUT4" "IS_DOUT4" U1 AA10 -Net 611 "/FPGA, Port0, Port2, PROG IF/IS_DOUT5" "IS_DOUT5" - U1 AB9 + U24 1 +Net 650 "/Image Sensor/IS_DOUT5" "IS_DOUT5" U24 2 -Net 612 "/Image Sensor/IS_DOUT6" "IS_DOUT6" - U1 Y8 + U1 AB9 +Net 651 "/Image Sensor/IS_DOUT6" "IS_DOUT6" U24 3 -Net 613 "/Image Sensor/IS_DOUT7" "IS_DOUT7" - U24 7 + U1 Y8 +Net 652 "/Image Sensor/IS_DOUT7" "IS_DOUT7" U1 AA8 -Net 614 "/FPGA, Port0, Port2, PROG IF/IS_DOUT8" "IS_DOUT8" + U24 7 +Net 653 "/Image Sensor/IS_DOUT8" "IS_DOUT8" U1 AB8 U24 8 -Net 615 "/Image Sensor/IS_DOUT9" "IS_DOUT9" - U24 9 +Net 654 "/FPGA, Port0, Port2, PROG IF/IS_DOUT9" "IS_DOUT9" U1 Y7 -Net 616 "/FPGA, Port0, Port2, PROG IF/IS_DOUT10" "IS_DOUT10" + U24 9 +Net 655 "/FPGA, Port0, Port2, PROG IF/IS_DOUT10" "IS_DOUT10" U1 Y6 U24 10 -Net 617 "/FPGA, Port0, Port2, PROG IF/IS_DOUT11" "IS_DOUT11" - U1 AB7 +Net 656 "/FPGA, Port0, Port2, PROG IF/IS_DOUT11" "IS_DOUT11" U24 11 + U1 AB7 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 289c89b..eea3da6 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,8 +1,10 @@ -update=Tue 12 Oct 2010 10:05:41 PM COT +update=Sat 16 Oct 2010 12:53:56 PM COT version=1 last_client=pcbnew [common] NetDir= +[general] +version=1 [eeschema] version=1 LibDir= @@ -89,13 +91,12 @@ LibName47=../library/tps793xx LibName48=../library/reg102 LibName49=../library/mt9m033 LibName50=../library/m12-tu400a +LibName51=/home/juan64bits/emQbit/xue/kicad/library/ft2232c [cvpcb] version=1 NetIExt=net [cvpcb/libraries] EquName1=devcms -[general] -version=1 [pcbnew] version=1 PadDrlX=0 @@ -151,3 +152,6 @@ LibName32=../modules/MLP6 LibName33=../modules/iLCC-48 LibName34=../modules/M12-TU400A LibName35=../modules/header20x2_smd_100mil +LibName36=/home/juan64bits/emQbit/xue/kicad/modules/CRYSTAL +LibName37=/home/juan64bits/emQbit/xue/kicad/modules/TP40R +LibName38=/home/juan64bits/emQbit/xue/kicad/modules/TP66R diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 18144e9..76b4ba4 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Tue 12 Oct 2010 10:05:38 PM COT +EESchema Schematic File Version 2 date Sat 16 Oct 2010 12:53:51 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -49,13 +49,14 @@ LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a +LIBS:ft2232c LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 1 12 Title "" -Date "13 oct 2010" +Date "16 oct 2010" Rev "" Comp "" Comment1 "" @@ -63,6 +64,18 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Wire Wire Line + 4000 1250 3550 1250 +Wire Wire Line + 3550 1250 3550 2400 +Wire Wire Line + 3550 2400 4000 2400 +Wire Wire Line + 4000 1450 3750 1450 +Wire Wire Line + 3750 1450 3750 2200 +Wire Wire Line + 3750 2200 4000 2200 Wire Bus Line 9550 5600 10900 5600 Wire Wire Line @@ -90,9 +103,9 @@ Wire Wire Line Wire Wire Line 10850 9900 9500 9900 Wire Wire Line - 6200 5750 5200 5750 + 6200 2400 5200 2400 Wire Wire Line - 6200 5550 5200 5550 + 6200 2200 5200 2200 Wire Wire Line 10900 4600 9550 4600 Wire Wire Line @@ -218,9 +231,9 @@ Wire Wire Line Wire Bus Line 10900 4700 9550 4700 Wire Wire Line - 6200 5450 5200 5450 + 6200 2100 5200 2100 Wire Wire Line - 5200 5650 6200 5650 + 5200 2300 6200 2300 Wire Wire Line 10850 9800 9500 9800 Wire Wire Line @@ -245,6 +258,18 @@ Wire Wire Line 5200 3950 6200 3950 Wire Wire Line 5200 4150 6200 4150 +Wire Wire Line + 4000 2100 3850 2100 +Wire Wire Line + 3850 2100 3850 1550 +Wire Wire Line + 3850 1550 4000 1550 +Wire Wire Line + 4000 2300 3650 2300 +Wire Wire Line + 3650 2300 3650 1350 +Wire Wire Line + 3650 1350 4000 1350 $Sheet S 10900 5250 1320 700 U 4CB0D95D @@ -293,10 +318,10 @@ S 6200 700 3350 5450 U 4C7BC2B2 F0 "FPGA, Port0, Port2, PROG IF" 60 F1 "FPGA_0_2_PROG.sch" 60 -F2 "S6_TCK" I L 6200 5450 60 -F3 "S6_TDI" I L 6200 5550 60 -F4 "S6_TDO" O L 6200 5650 60 -F5 "S6_TMS" I L 6200 5750 60 +F2 "S6_TCK" I L 6200 2100 60 +F3 "S6_TDI" I L 6200 2200 60 +F4 "S6_TDO" O L 6200 2300 60 +F5 "S6_TMS" I L 6200 2400 60 F6 "PROG_MISO[0..3]" B R 9550 4700 60 F7 "PROG_CCLK" O R 9550 4600 60 F8 "PROG_CSO" O R 9550 4500 60 @@ -384,42 +409,30 @@ F36 "M1_CLK" O L 6200 7850 60 F37 "M1_CLK#" O L 6200 7950 60 F38 "M0_CLK" O L 6200 9900 60 F39 "M0_CLK#" O L 6200 10000 60 -F40 "FPGA_2.5V_IO_M17" B R 9500 7050 60 -F41 "FPGA_2.5V_IO_N16" B R 9500 7150 60 -F42 "FPGA_2.5V_IO_P19" B R 9500 7250 60 -F43 "FPGA_2.5V_IO_P17" B R 9500 7350 60 -F44 "FPGA_2.5V_IO_P18" B R 9500 7450 60 -F45 "FPGA_2.5V_IO_U19" B R 9500 7550 60 -F46 "FPGA_2.5V_IO_T20" B R 9500 7650 60 -F47 "FPGA_2.5V_IO_V20" B R 9500 7750 60 -F48 "FPGA_2.5V_IO_W20" B R 9500 7850 60 -F49 "FPGA_2.5V_IO_W22" B R 9500 7950 60 -F50 "FPGA_2.5V_IO_V3" B R 9500 8050 60 -F51 "FPGA_2.5V_IO_U4" B R 9500 8150 60 -F52 "FPGA_2.5V_IO_T3" B R 9500 8250 60 -F53 "FPGA_2.5V_IO_T4" B R 9500 8350 60 -F54 "FPGA_2.5V_IO_P7" B R 9500 8450 60 -F55 "FPGA_2.5V_IO_P8" B R 9500 8550 60 -F56 "FPGA_2.5V_IO_W1" B R 9500 8650 60 -F57 "FPGA_2.5V_IO_W3" B R 9500 8750 60 -F58 "FPGA_2.5V_IO_Y1" B R 9500 8850 60 -F59 "FPGA_2.5V_IO_Y2" B R 9500 8950 60 $EndSheet $Sheet -S 4000 5400 1200 700 +S 4000 1900 1200 700 U 4C716A4D F0 "DBG_PRG" 60 F1 "DBG_PRG.sch" 60 -F2 "FPGA_TDO" B R 5200 5650 60 -F3 "FPGA_TDI" B R 5200 5550 60 -F4 "FPGA_TMS" B R 5200 5750 60 -F5 "FPGA_TCK" B R 5200 5450 60 +F2 "FPGA_TDO" B R 5200 2300 60 +F3 "FPGA_TDI" B R 5200 2200 60 +F4 "FPGA_TMS" B R 5200 2400 60 +F5 "FPGA_TCK" B R 5200 2100 60 +F6 "AVR_SCK" B L 4000 2100 60 +F7 "AVR_RST" B L 4000 2400 60 +F8 "AVR_MOSI" B L 4000 2200 60 +F9 "AVR_MISO" B L 4000 2300 60 $EndSheet $Sheet S 4000 950 1200 750 U 4C69ED5F F0 "PSU" 60 F1 "PSU.sch" 60 +F2 "AVR_SCK" B L 4000 1550 60 +F3 "AVR_MISO" B L 4000 1350 60 +F4 "AVR_MOSI" B L 4000 1450 60 +F5 "AVR_RST" B L 4000 1250 60 $EndSheet $Sheet S 10900 2900 1050 1950