diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index f2c6482..9b1c0ea 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -47,7 +47,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 6 6 Title "" -Date "12 aug 2010" +Date "13 aug 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index efaf2b3..cf803a6 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -47,7 +47,7 @@ EELAYER END $Descr A2 23400 16535 Sheet 3 6 Title "" -Date "12 aug 2010" +Date "13 aug 2010" Rev "" Comp "" Comment1 "" @@ -56,7 +56,7 @@ Comment3 "" Comment4 "" $EndDescr Text HLabel 18600 10150 2 60 BiDi ~ 0 -ND_D[0..7] +NF_D[0..7] Wire Bus Line 18600 10150 18300 10150 Wire Wire Line diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index 86598a6..a063a29 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -47,7 +47,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 5 6 Title "" -Date "12 aug 2010" +Date "13 aug 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 572976f..7bdff2c 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -47,7 +47,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 2 6 Title "" -Date "12 aug 2010" +Date "13 aug 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 895ea77..9238c18 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -47,7 +47,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 4 6 Title "" -Date "12 aug 2010" +Date "13 aug 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 8ae8b00..753507a 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Thu 12 Aug 2010 05:12:17 PM COT +EESchema-LIBRARY Version 2.3 Date: Thu 12 Aug 2010 09:08:15 PM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index a16d853..7636e98 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Thu 12 Aug 2010 12:06:58 PM COT +PCBNEW-BOARD Version 1 date Thu 12 Aug 2010 09:10:48 PM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -6,21 +6,21 @@ $GENERAL LayerCount 4 Ly 1FFF8007 EnabledLayers 1FFF8007 -Links 423 -NoConn 423 +Links 431 +NoConn 431 Di 44325 10878 68579 39600 Ndraw 2 Ntrack 0 Nzone 0 BoardThickness 630 Nmodule 65 -Nnets 150 +Nnets 158 $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "12 aug 2010" +Date "13 aug 2010" Rev "" Comp "" Comment1 "" @@ -84,11 +84,11 @@ Na 4 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/DDR_Banks/M0_A10" +Na 5 "/DDR_Banks/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A5" +Na 6 "/DDR_Banks/M0_A3" St ~ $EndEQUIPOT $EQUIPOT @@ -96,59 +96,59 @@ Na 7 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_BA0" +Na 8 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_CLK" +Na 9 "/DDR_Banks/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_DQ10" +Na 10 "/DDR_Banks/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_DQ13" +Na 11 "/DDR_Banks/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_DQ5" +Na 12 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_DQ6" +Na 13 "/DDR_Banks/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_DQ9" +Na 14 "/DDR_Banks/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_LDM" +Na 15 "/DDR_Banks/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_LDQS" +Na 16 "/DDR_Banks/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_UDM" +Na 17 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_UDQS" +Na 18 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M1_A10" +Na 19 "/DDR_Banks/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M1_A11" +Na 20 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M1_A4" +Na 21 "/DDR_Banks/M1_A10" St ~ $EndEQUIPOT $EQUIPOT @@ -156,71 +156,71 @@ Na 22 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_A6" +Na 23 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_A9" +Na 24 "/DDR_Banks/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_BA0" +Na 25 "/DDR_Banks/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_CAS#" +Na 26 "/DDR_Banks/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_CKE" +Na 27 "/DDR_Banks/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_DQ0" +Na 28 "/DDR_Banks/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_DQ13" +Na 29 "/DDR_Banks/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_DQ3" +Na 30 "/DDR_Banks/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_DQ5" +Na 31 "/DDR_Banks/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_DQ6" +Na 32 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_LDM" +Na 33 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_RAS#" +Na 34 "/DDR_Banks/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/Ethernet_Phy/ETH_1.8V" +Na 35 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/Ethernet_Phy/ETH_A1.8V" +Na 36 "/Ethernet_Phy/ETH_1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/Ethernet_Phy/ETH_A3.3V" +Na 37 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/Ethernet_Phy/ETH_COL" +Na 38 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/Ethernet_Phy/ETH_CRS" +Na 39 "/Ethernet_Phy/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT @@ -240,11 +240,11 @@ Na 43 "/Ethernet_Phy/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_PLL1.8V" +Na 44 "/Ethernet_Phy/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_RXC" +Na 45 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT @@ -256,51 +256,51 @@ Na 47 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_RXDV" +Na 48 "/Ethernet_Phy/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_RXER" +Na 49 "/Ethernet_Phy/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/ETH_TXC" +Na 50 "/Ethernet_Phy/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Ethernet_Phy/ETH_TXD1" +Na 51 "/FPGA_Spartan6/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/Ethernet_Phy/ETH_TXD2" +Na 52 "/FPGA_Spartan6/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/Ethernet_Phy/ETH_TXEN" +Na 53 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/Ethernet_Phy/ETH_TXER" +Na 54 "/FPGA_Spartan6/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Spartan6/ETH_CLK" +Na 55 "/FPGA_Spartan6/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/ETH_MDIO" +Na 56 "/FPGA_Spartan6/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/ETH_RESET_N" +Na 57 "/FPGA_Spartan6/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/ETH_RXD2" +Na 58 "/FPGA_Spartan6/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/ETH_RXD3" +Na 59 "/FPGA_Spartan6/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT @@ -312,27 +312,27 @@ Na 61 "/FPGA_Spartan6/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/M0_A0" +Na 62 "/FPGA_Spartan6/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/M0_A1" +Na 63 "/FPGA_Spartan6/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/M0_A11" +Na 64 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/M0_A12" +Na 65 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/M0_A2" +Na 66 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/M0_A3" +Na 67 "/FPGA_Spartan6/M0_A2" St ~ $EndEQUIPOT $EQUIPOT @@ -340,11 +340,11 @@ Na 68 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_A6" +Na 69 "/FPGA_Spartan6/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_A8" +Na 70 "/FPGA_Spartan6/M0_A6" St ~ $EndEQUIPOT $EQUIPOT @@ -352,79 +352,79 @@ Na 71 "/FPGA_Spartan6/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_BA1" +Na 72 "/FPGA_Spartan6/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_CAS#" +Na 73 "/FPGA_Spartan6/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_CKE" +Na 74 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_CLK#" +Na 75 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_DQ0" +Na 76 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_DQ1" +Na 77 "/FPGA_Spartan6/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_DQ11" +Na 78 "/FPGA_Spartan6/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_DQ12" +Na 79 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_DQ14" +Na 80 "/FPGA_Spartan6/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_DQ15" +Na 81 "/FPGA_Spartan6/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_DQ2" +Na 82 "/FPGA_Spartan6/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_DQ3" +Na 83 "/FPGA_Spartan6/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_DQ4" +Na 84 "/FPGA_Spartan6/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M0_DQ7" +Na 85 "/FPGA_Spartan6/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M0_DQ8" +Na 86 "/FPGA_Spartan6/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M0_RAS#" +Na 87 "/FPGA_Spartan6/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M0_WE#" +Na 88 "/FPGA_Spartan6/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M1_A0" +Na 89 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M1_A1" +Na 90 "/FPGA_Spartan6/M1_A11" St ~ $EndEQUIPOT $EQUIPOT @@ -440,227 +440,259 @@ Na 93 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_A7" +Na 94 "/FPGA_Spartan6/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_A8" +Na 95 "/FPGA_Spartan6/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_BA1" +Na 96 "/FPGA_Spartan6/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_CLK" +Na 97 "/FPGA_Spartan6/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_CLK#" +Na 98 "/FPGA_Spartan6/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_DQ1" +Na 99 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_DQ10" +Na 100 "/FPGA_Spartan6/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_DQ11" +Na 101 "/FPGA_Spartan6/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_DQ12" +Na 102 "/FPGA_Spartan6/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_DQ14" +Na 103 "/FPGA_Spartan6/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_DQ15" +Na 104 "/FPGA_Spartan6/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ2" +Na 105 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_DQ4" +Na 106 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_DQ7" +Na 107 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_DQ8" +Na 108 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ9" +Na 109 "/FPGA_Spartan6/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_LDQS" +Na 110 "/FPGA_Spartan6/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_UDM" +Na 111 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Spartan6/M1_UDQS" +Na 112 "/FPGA_Spartan6/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_WE#" +Na 113 "/FPGA_Spartan6/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Spartan6/SD_DAT3" +Na 114 "/FPGA_Spartan6/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/USBA_OE_N" +Na 115 "/FPGA_Spartan6/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/USBA_VM" +Na 116 "/FPGA_Spartan6/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Spartan6/USBA_VP" +Na 117 "/FPGA_Spartan6/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/Non_volatile_memories/FRB_N" +Na 118 "/FPGA_Spartan6/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/Non_volatile_memories/SD_CLK" +Na 119 "/FPGA_Spartan6/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/Non_volatile_memories/SD_CMD" +Na 120 "/FPGA_Spartan6/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/Non_volatile_memories/SD_DAT0" +Na 121 "/FPGA_Spartan6/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/Non_volatile_memories/SD_DAT1" +Na 122 "/FPGA_Spartan6/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/Non_volatile_memories/SD_DAT2" +Na 123 "/Non_volatile_memories/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/USB/USBA_RCV" +Na 124 "/Non_volatile_memories/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/USB/USBA_SPD" +Na 125 "/Non_volatile_memories/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "3.3V" +Na 126 "/Non_volatile_memories/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "GND" +Na 127 "/Non_volatile_memories/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "N-000043" +Na 128 "/Non_volatile_memories/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "N-000044" +Na 129 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "N-000045" +Na 130 "/Non_volatile_memories/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "N-000047" +Na 131 "/USB/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "N-000101" +Na 132 "/USB/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "N-000334" +Na 133 "/USB/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "N-000335" +Na 134 "3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "N-000336" +Na 135 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "N-000337" +Na 136 "N-000049" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "N-000338" +Na 137 "N-000050" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "N-000344" +Na 138 "N-000051" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "N-000345" +Na 139 "N-000053" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "N-000346" +Na 140 "N-000110" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "N-000347" +Na 141 "N-000327" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "N-000350" +Na 142 "N-000328" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "N-000356" +Na 143 "N-000329" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "N-000357" +Na 144 "N-000330" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "N-000358" +Na 145 "N-000331" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "N-000360" +Na 146 "N-000337" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "N-000361" +Na 147 "N-000338" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "N-000362" +Na 148 "N-000339" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "N-000363" +Na 149 "N-000340" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 150 "N-000343" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 151 "N-000349" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 152 "N-000350" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 153 "N-000351" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 154 "N-000353" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 155 "N-000354" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 156 "N-000355" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 157 "N-000356" St ~ $EndEQUIPOT $NCLASS @@ -677,151 +709,159 @@ AddNet "+1.2V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" -AddNet "/DDR_Banks/M0_A10" -AddNet "/DDR_Banks/M0_A5" +AddNet "/DDR_Banks/M0_A11" +AddNet "/DDR_Banks/M0_A3" AddNet "/DDR_Banks/M0_A7" -AddNet "/DDR_Banks/M0_BA0" +AddNet "/DDR_Banks/M0_A8" +AddNet "/DDR_Banks/M0_CAS#" +AddNet "/DDR_Banks/M0_CKE" AddNet "/DDR_Banks/M0_CLK" +AddNet "/DDR_Banks/M0_CLK#" AddNet "/DDR_Banks/M0_DQ10" -AddNet "/DDR_Banks/M0_DQ13" -AddNet "/DDR_Banks/M0_DQ5" -AddNet "/DDR_Banks/M0_DQ6" -AddNet "/DDR_Banks/M0_DQ9" +AddNet "/DDR_Banks/M0_DQ14" +AddNet "/DDR_Banks/M0_DQ2" +AddNet "/DDR_Banks/M0_DQ3" +AddNet "/DDR_Banks/M0_DQ4" AddNet "/DDR_Banks/M0_LDM" -AddNet "/DDR_Banks/M0_LDQS" -AddNet "/DDR_Banks/M0_UDM" -AddNet "/DDR_Banks/M0_UDQS" +AddNet "/DDR_Banks/M0_RAS#" +AddNet "/DDR_Banks/M0_WE#" AddNet "/DDR_Banks/M1_A10" -AddNet "/DDR_Banks/M1_A11" -AddNet "/DDR_Banks/M1_A4" AddNet "/DDR_Banks/M1_A5" -AddNet "/DDR_Banks/M1_A6" -AddNet "/DDR_Banks/M1_A9" -AddNet "/DDR_Banks/M1_BA0" -AddNet "/DDR_Banks/M1_CAS#" +AddNet "/DDR_Banks/M1_A8" +AddNet "/DDR_Banks/M1_BA1" AddNet "/DDR_Banks/M1_CKE" -AddNet "/DDR_Banks/M1_DQ0" -AddNet "/DDR_Banks/M1_DQ13" +AddNet "/DDR_Banks/M1_CLK" +AddNet "/DDR_Banks/M1_DQ12" AddNet "/DDR_Banks/M1_DQ3" -AddNet "/DDR_Banks/M1_DQ5" +AddNet "/DDR_Banks/M1_DQ4" AddNet "/DDR_Banks/M1_DQ6" -AddNet "/DDR_Banks/M1_LDM" +AddNet "/DDR_Banks/M1_DQ7" +AddNet "/DDR_Banks/M1_LDQS" AddNet "/DDR_Banks/M1_RAS#" +AddNet "/DDR_Banks/M1_UDM" +AddNet "/DDR_Banks/M1_WE#" AddNet "/Ethernet_Phy/ETH_1.8V" AddNet "/Ethernet_Phy/ETH_A1.8V" AddNet "/Ethernet_Phy/ETH_A3.3V" AddNet "/Ethernet_Phy/ETH_COL" -AddNet "/Ethernet_Phy/ETH_CRS" AddNet "/Ethernet_Phy/ETH_INT" AddNet "/Ethernet_Phy/ETH_LED0" AddNet "/Ethernet_Phy/ETH_LED1" AddNet "/Ethernet_Phy/ETH_MDC" +AddNet "/Ethernet_Phy/ETH_MDIO" AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/ETH_RXC" AddNet "/Ethernet_Phy/ETH_RXD0" AddNet "/Ethernet_Phy/ETH_RXD1" -AddNet "/Ethernet_Phy/ETH_RXDV" -AddNet "/Ethernet_Phy/ETH_RXER" -AddNet "/Ethernet_Phy/ETH_TXC" AddNet "/Ethernet_Phy/ETH_TXD1" AddNet "/Ethernet_Phy/ETH_TXD2" AddNet "/Ethernet_Phy/ETH_TXEN" -AddNet "/Ethernet_Phy/ETH_TXER" AddNet "/FPGA_Spartan6/ETH_CLK" -AddNet "/FPGA_Spartan6/ETH_MDIO" +AddNet "/FPGA_Spartan6/ETH_CRS" AddNet "/FPGA_Spartan6/ETH_RESET_N" +AddNet "/FPGA_Spartan6/ETH_RXC" AddNet "/FPGA_Spartan6/ETH_RXD2" AddNet "/FPGA_Spartan6/ETH_RXD3" +AddNet "/FPGA_Spartan6/ETH_RXDV" +AddNet "/FPGA_Spartan6/ETH_RXER" +AddNet "/FPGA_Spartan6/ETH_TXC" AddNet "/FPGA_Spartan6/ETH_TXD0" AddNet "/FPGA_Spartan6/ETH_TXD3" +AddNet "/FPGA_Spartan6/ETH_TXER" AddNet "/FPGA_Spartan6/M0_A0" AddNet "/FPGA_Spartan6/M0_A1" -AddNet "/FPGA_Spartan6/M0_A11" +AddNet "/FPGA_Spartan6/M0_A10" AddNet "/FPGA_Spartan6/M0_A12" AddNet "/FPGA_Spartan6/M0_A2" -AddNet "/FPGA_Spartan6/M0_A3" AddNet "/FPGA_Spartan6/M0_A4" +AddNet "/FPGA_Spartan6/M0_A5" AddNet "/FPGA_Spartan6/M0_A6" -AddNet "/FPGA_Spartan6/M0_A8" AddNet "/FPGA_Spartan6/M0_A9" +AddNet "/FPGA_Spartan6/M0_BA0" AddNet "/FPGA_Spartan6/M0_BA1" -AddNet "/FPGA_Spartan6/M0_CAS#" -AddNet "/FPGA_Spartan6/M0_CKE" -AddNet "/FPGA_Spartan6/M0_CLK#" AddNet "/FPGA_Spartan6/M0_DQ0" AddNet "/FPGA_Spartan6/M0_DQ1" AddNet "/FPGA_Spartan6/M0_DQ11" AddNet "/FPGA_Spartan6/M0_DQ12" -AddNet "/FPGA_Spartan6/M0_DQ14" +AddNet "/FPGA_Spartan6/M0_DQ13" AddNet "/FPGA_Spartan6/M0_DQ15" -AddNet "/FPGA_Spartan6/M0_DQ2" -AddNet "/FPGA_Spartan6/M0_DQ3" -AddNet "/FPGA_Spartan6/M0_DQ4" +AddNet "/FPGA_Spartan6/M0_DQ5" +AddNet "/FPGA_Spartan6/M0_DQ6" AddNet "/FPGA_Spartan6/M0_DQ7" AddNet "/FPGA_Spartan6/M0_DQ8" -AddNet "/FPGA_Spartan6/M0_RAS#" -AddNet "/FPGA_Spartan6/M0_WE#" +AddNet "/FPGA_Spartan6/M0_DQ9" +AddNet "/FPGA_Spartan6/M0_LDQS" +AddNet "/FPGA_Spartan6/M0_UDM" +AddNet "/FPGA_Spartan6/M0_UDQS" AddNet "/FPGA_Spartan6/M1_A0" AddNet "/FPGA_Spartan6/M1_A1" +AddNet "/FPGA_Spartan6/M1_A11" AddNet "/FPGA_Spartan6/M1_A12" AddNet "/FPGA_Spartan6/M1_A2" AddNet "/FPGA_Spartan6/M1_A3" +AddNet "/FPGA_Spartan6/M1_A4" +AddNet "/FPGA_Spartan6/M1_A6" AddNet "/FPGA_Spartan6/M1_A7" -AddNet "/FPGA_Spartan6/M1_A8" -AddNet "/FPGA_Spartan6/M1_BA1" -AddNet "/FPGA_Spartan6/M1_CLK" +AddNet "/FPGA_Spartan6/M1_A9" +AddNet "/FPGA_Spartan6/M1_BA0" +AddNet "/FPGA_Spartan6/M1_CAS#" AddNet "/FPGA_Spartan6/M1_CLK#" +AddNet "/FPGA_Spartan6/M1_DQ0" AddNet "/FPGA_Spartan6/M1_DQ1" AddNet "/FPGA_Spartan6/M1_DQ10" AddNet "/FPGA_Spartan6/M1_DQ11" -AddNet "/FPGA_Spartan6/M1_DQ12" +AddNet "/FPGA_Spartan6/M1_DQ13" AddNet "/FPGA_Spartan6/M1_DQ14" AddNet "/FPGA_Spartan6/M1_DQ15" AddNet "/FPGA_Spartan6/M1_DQ2" -AddNet "/FPGA_Spartan6/M1_DQ4" -AddNet "/FPGA_Spartan6/M1_DQ7" +AddNet "/FPGA_Spartan6/M1_DQ5" AddNet "/FPGA_Spartan6/M1_DQ8" AddNet "/FPGA_Spartan6/M1_DQ9" -AddNet "/FPGA_Spartan6/M1_LDQS" -AddNet "/FPGA_Spartan6/M1_UDM" +AddNet "/FPGA_Spartan6/M1_LDM" AddNet "/FPGA_Spartan6/M1_UDQS" -AddNet "/FPGA_Spartan6/M1_WE#" -AddNet "/FPGA_Spartan6/SD_DAT3" -AddNet "/FPGA_Spartan6/USBA_OE_N" -AddNet "/FPGA_Spartan6/USBA_VM" +AddNet "/FPGA_Spartan6/NF_D1" +AddNet "/FPGA_Spartan6/NF_D2" +AddNet "/FPGA_Spartan6/NF_D3" +AddNet "/FPGA_Spartan6/NF_D4" +AddNet "/FPGA_Spartan6/NF_D6" +AddNet "/FPGA_Spartan6/SD_CLK" +AddNet "/FPGA_Spartan6/SD_DAT1" +AddNet "/FPGA_Spartan6/USBA_RCV" AddNet "/FPGA_Spartan6/USBA_VP" -AddNet "/Non_volatile_memories/FRB_N" -AddNet "/Non_volatile_memories/SD_CLK" +AddNet "/Non_volatile_memories/NF_D0" +AddNet "/Non_volatile_memories/NF_D5" +AddNet "/Non_volatile_memories/NF_D7" +AddNet "/Non_volatile_memories/NF_RNB" AddNet "/Non_volatile_memories/SD_CMD" AddNet "/Non_volatile_memories/SD_DAT0" -AddNet "/Non_volatile_memories/SD_DAT1" AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "/USB/USBA_RCV" +AddNet "/Non_volatile_memories/SD_DAT3" +AddNet "/USB/USBA_OE_N" AddNet "/USB/USBA_SPD" +AddNet "/USB/USBA_VM" AddNet "3.3V" AddNet "GND" -AddNet "N-000043" -AddNet "N-000044" -AddNet "N-000045" -AddNet "N-000047" -AddNet "N-000101" -AddNet "N-000334" -AddNet "N-000335" -AddNet "N-000336" +AddNet "N-000049" +AddNet "N-000050" +AddNet "N-000051" +AddNet "N-000053" +AddNet "N-000110" +AddNet "N-000327" +AddNet "N-000328" +AddNet "N-000329" +AddNet "N-000330" +AddNet "N-000331" AddNet "N-000337" AddNet "N-000338" -AddNet "N-000344" -AddNet "N-000345" -AddNet "N-000346" -AddNet "N-000347" +AddNet "N-000339" +AddNet "N-000340" +AddNet "N-000343" +AddNet "N-000349" AddNet "N-000350" +AddNet "N-000351" +AddNet "N-000353" +AddNet "N-000354" +AddNet "N-000355" AddNet "N-000356" -AddNet "N-000357" -AddNet "N-000358" -AddNet "N-000360" -AddNet "N-000361" -AddNet "N-000362" -AddNet "N-000363" $EndNCLASS $MODULE FGG484bga-p10 Po 56450 33930 0 15 4C4325AE 4C431E53 ~~ @@ -844,7 +884,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -4133 -4133 $EndPAD $PAD @@ -872,7 +912,7 @@ $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_MDIO" +Ne 44 "/Ethernet_Phy/ETH_MDIO" Po -2558 -4133 $EndPAD $PAD @@ -886,49 +926,49 @@ $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_RXDV" +Ne 57 "/FPGA_Spartan6/ETH_RXDV" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXER" +Ne 62 "/FPGA_Spartan6/ETH_TXER" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_TXD2" +Ne 49 "/Ethernet_Phy/ETH_TXD2" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_COL" +Ne 39 "/Ethernet_Phy/ETH_COL" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 125 "/Non_volatile_memories/NF_D7" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 116 "/FPGA_Spartan6/NF_D3" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 114 "/FPGA_Spartan6/NF_D1" Po 590 -4133 $EndPAD $PAD @@ -942,28 +982,28 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/SD_DAT3" +Ne 0 "" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/Non_volatile_memories/SD_CLK" +Ne 0 "" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/USBA_VM" +Ne 129 "/Non_volatile_memories/SD_DAT2" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/USB/USBA_RCV" +Ne 128 "/Non_volatile_memories/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -991,7 +1031,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 4133 -4133 $EndPAD $PAD @@ -1026,14 +1066,14 @@ $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2558 -3739 $EndPAD $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RXD2" +Ne 55 "/FPGA_Spartan6/ETH_RXD2" Po -2165 -3739 $EndPAD $PAD @@ -1047,21 +1087,21 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_RXER" +Ne 58 "/FPGA_Spartan6/ETH_RXER" Po -1377 -3739 $EndPAD $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -983 -3739 $EndPAD $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_CRS" +Ne 52 "/FPGA_Spartan6/ETH_CRS" Po -590 -3739 $EndPAD $PAD @@ -1075,14 +1115,14 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 117 "/FPGA_Spartan6/NF_D4" Po 196 -3739 $EndPAD $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 590 -3739 $EndPAD $PAD @@ -1103,21 +1143,21 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/Non_volatile_memories/SD_DAT0" +Ne 0 "" Po 1771 -3739 $EndPAD $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 2165 -3739 $EndPAD $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/USBA_VP" +Ne 120 "/FPGA_Spartan6/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1152,7 +1192,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A11" +Ne 5 "/DDR_Banks/M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1187,7 +1227,7 @@ $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_RXD3" +Ne 56 "/FPGA_Spartan6/ETH_RXD3" Po -2165 -3346 $EndPAD $PAD @@ -1208,14 +1248,14 @@ $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_TXD1" +Ne 48 "/Ethernet_Phy/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_CLK" +Ne 51 "/FPGA_Spartan6/ETH_CLK" Po -590 -3346 $EndPAD $PAD @@ -1229,14 +1269,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 124 "/Non_volatile_memories/NF_D5" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 115 "/FPGA_Spartan6/NF_D2" Po 590 -3346 $EndPAD $PAD @@ -1257,14 +1297,14 @@ $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/Non_volatile_memories/SD_DAT1" +Ne 0 "" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/Non_volatile_memories/SD_CMD" +Ne 130 "/Non_volatile_memories/SD_DAT3" Po 2165 -3346 $EndPAD $PAD @@ -1285,7 +1325,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A8" +Ne 23 "/DDR_Banks/M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1299,21 +1339,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A9" +Ne 97 "/FPGA_Spartan6/M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A12" +Ne 66 "/FPGA_Spartan6/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_CKE" +Ne 10 "/DDR_Banks/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1327,7 +1367,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1341,7 +1381,7 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RESET_N" +Ne 53 "/FPGA_Spartan6/ETH_RESET_N" Po -2165 -2952 $EndPAD $PAD @@ -1355,28 +1395,28 @@ $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_TXC" +Ne 59 "/FPGA_Spartan6/ETH_TXC" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_TXEN" +Ne 50 "/Ethernet_Phy/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_RXC" +Ne 54 "/FPGA_Spartan6/ETH_RXC" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 118 "/FPGA_Spartan6/NF_D6" Po -196 -2952 $EndPAD $PAD @@ -1397,14 +1437,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 123 "/Non_volatile_memories/NF_D0" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/Non_volatile_memories/SD_DAT2" +Ne 0 "" Po 1377 -2952 $EndPAD $PAD @@ -1418,14 +1458,14 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/USB/USBA_SPD" +Ne 127 "/Non_volatile_memories/SD_CMD" Po 2165 -2952 $EndPAD $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 2558 -2952 $EndPAD $PAD @@ -1446,7 +1486,7 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_CKE" +Ne 25 "/DDR_Banks/M1_CKE" Po 3739 -2952 $EndPAD $PAD @@ -1467,14 +1507,14 @@ $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A8" +Ne 8 "/DDR_Banks/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1502,7 +1542,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -1771 -2558 $EndPAD $PAD @@ -1558,14 +1598,14 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 1377 -2558 $EndPAD $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/USBA_OE_N" +Ne 119 "/FPGA_Spartan6/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -1593,14 +1633,14 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A7" +Ne 96 "/FPGA_Spartan6/M1_A7" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 3739 -2558 $EndPAD $PAD @@ -1621,7 +1661,7 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_WE#" +Ne 20 "/DDR_Banks/M0_WE#" Po -3739 -2165 $EndPAD $PAD @@ -1740,35 +1780,35 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_A11" +Ne 90 "/FPGA_Spartan6/M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_A4" +Ne 94 "/FPGA_Spartan6/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A0" +Ne 88 "/FPGA_Spartan6/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A1" +Ne 89 "/FPGA_Spartan6/M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_BA1" +Ne 73 "/FPGA_Spartan6/M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -1782,21 +1822,21 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_BA0" +Ne 72 "/FPGA_Spartan6/M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_A10" +Ne 65 "/FPGA_Spartan6/M0_A10" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2558 -1771 $EndPAD $PAD @@ -1887,14 +1927,14 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M1_A10" +Ne 21 "/DDR_Banks/M1_A10" Po 2952 -1771 $EndPAD $PAD @@ -1922,35 +1962,35 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M0_A1" +Ne 64 "/FPGA_Spartan6/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/M0_A0" +Ne 63 "/FPGA_Spartan6/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_CLK#" +Ne 12 "/DDR_Banks/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_CLK" +Ne 11 "/DDR_Banks/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A2" +Ne 67 "/FPGA_Spartan6/M0_A2" Po -2558 -1377 $EndPAD $PAD @@ -1964,7 +2004,7 @@ $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -1771 -1377 $EndPAD $PAD @@ -2048,56 +2088,56 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_WE#" +Ne 35 "/DDR_Banks/M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_CLK" +Ne 26 "/DDR_Banks/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_RAS#" +Ne 33 "/DDR_Banks/M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_CAS#" +Ne 99 "/FPGA_Spartan6/M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_DQ5" +Ne 80 "/FPGA_Spartan6/M0_DQ5" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ4" +Ne 17 "/DDR_Banks/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A6" +Ne 70 "/FPGA_Spartan6/M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2132,7 +2172,7 @@ $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -983 -983 $EndPAD $PAD @@ -2146,7 +2186,7 @@ $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -196 -983 $EndPAD $PAD @@ -2160,7 +2200,7 @@ $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 590 -983 $EndPAD $PAD @@ -2174,7 +2214,7 @@ $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 1377 -983 $EndPAD $PAD @@ -2188,7 +2228,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_BA0" +Ne 98 "/FPGA_Spartan6/M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2202,70 +2242,70 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_CLK#" +Ne 100 "/FPGA_Spartan6/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ4" +Ne 29 "/DDR_Banks/M1_DQ4" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ5" +Ne 109 "/FPGA_Spartan6/M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ7" +Ne 82 "/FPGA_Spartan6/M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ6" +Ne 81 "/FPGA_Spartan6/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A5" +Ne 69 "/FPGA_Spartan6/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_CAS#" +Ne 9 "/DDR_Banks/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_RAS#" +Ne 19 "/DDR_Banks/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A3" +Ne 6 "/DDR_Banks/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2293,7 +2333,7 @@ $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -590 -590 $EndPAD $PAD @@ -2321,7 +2361,7 @@ $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 983 -590 $EndPAD $PAD @@ -2342,7 +2382,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_BA1" +Ne 24 "/DDR_Banks/M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2356,7 +2396,7 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A6" +Ne 95 "/FPGA_Spartan6/M1_A6" Po 2952 -590 $EndPAD $PAD @@ -2370,14 +2410,14 @@ $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_DQ6" +Ne 30 "/DDR_Banks/M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ7" +Ne 31 "/DDR_Banks/M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2398,21 +2438,21 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_LDQS" +Ne 85 "/FPGA_Spartan6/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_LDM" +Ne 18 "/DDR_Banks/M0_LDM" Po -2952 -196 $EndPAD $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2558 -196 $EndPAD $PAD @@ -2440,7 +2480,7 @@ $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -983 -196 $EndPAD $PAD @@ -2454,7 +2494,7 @@ $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -196 -196 $EndPAD $PAD @@ -2468,7 +2508,7 @@ $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 590 -196 $EndPAD $PAD @@ -2503,21 +2543,21 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_LDM" +Ne 112 "/FPGA_Spartan6/M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_LDQS" +Ne 32 "/DDR_Banks/M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -2538,21 +2578,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ3" +Ne 16 "/DDR_Banks/M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ2" +Ne 15 "/DDR_Banks/M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_UDM" +Ne 86 "/FPGA_Spartan6/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2601,7 +2641,7 @@ $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -590 196 $EndPAD $PAD @@ -2615,7 +2655,7 @@ $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 196 196 $EndPAD $PAD @@ -2629,7 +2669,7 @@ $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 983 196 $EndPAD $PAD @@ -2657,7 +2697,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 133 "/USB/USBA_VM" Po 2558 196 $EndPAD $PAD @@ -2671,42 +2711,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_UDM" +Ne 34 "/DDR_Banks/M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ2" +Ne 108 "/FPGA_Spartan6/M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ3" +Ne 28 "/DDR_Banks/M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ1" +Ne 75 "/FPGA_Spartan6/M0_DQ1" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ0" +Ne 74 "/FPGA_Spartan6/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -2748,7 +2788,7 @@ $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -983 590 $EndPAD $PAD @@ -2762,7 +2802,7 @@ $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -196 590 $EndPAD $PAD @@ -2776,7 +2816,7 @@ $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 590 590 $EndPAD $PAD @@ -2797,14 +2837,14 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 121 "/FPGA_Spartan6/USBA_RCV" Po 1771 590 $EndPAD $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 2165 590 $EndPAD $PAD @@ -2825,35 +2865,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_DQ0" +Ne 101 "/FPGA_Spartan6/M1_DQ0" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_DQ1" +Ne 102 "/FPGA_Spartan6/M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ9" +Ne 84 "/FPGA_Spartan6/M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ8" +Ne 83 "/FPGA_Spartan6/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -2909,7 +2949,7 @@ $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -590 983 $EndPAD $PAD @@ -2923,7 +2963,7 @@ $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 196 983 $EndPAD $PAD @@ -2937,7 +2977,7 @@ $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 983 983 $EndPAD $PAD @@ -2958,14 +2998,14 @@ $PAD Sh "P17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 122 "/FPGA_Spartan6/USBA_VP" Po 2165 983 $EndPAD $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 131 "/USB/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -2986,21 +3026,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ8" +Ne 110 "/FPGA_Spartan6/M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ9" +Ne 111 "/FPGA_Spartan6/M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ11" +Ne 76 "/FPGA_Spartan6/M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3014,7 +3054,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_DQ10" +Ne 13 "/DDR_Banks/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3028,7 +3068,7 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2558 1377 $EndPAD $PAD @@ -3119,21 +3159,21 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 2558 1377 $EndPAD $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 132 "/USB/USBA_SPD" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_DQ10" +Ne 103 "/FPGA_Spartan6/M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3147,7 +3187,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ11" +Ne 104 "/FPGA_Spartan6/M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3161,7 +3201,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_UDQS" +Ne 87 "/FPGA_Spartan6/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3210,7 +3250,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po -983 1771 $EndPAD $PAD @@ -3238,7 +3278,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po 590 1771 $EndPAD $PAD @@ -3294,7 +3334,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_UDQS" +Ne 113 "/FPGA_Spartan6/M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3308,21 +3348,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_DQ13" +Ne 78 "/FPGA_Spartan6/M0_DQ13" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ12" +Ne 77 "/FPGA_Spartan6/M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3350,7 +3390,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -1771 2165 $EndPAD $PAD @@ -3441,35 +3481,35 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ12" +Ne 27 "/DDR_Banks/M1_DQ12" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_DQ13" +Ne 105 "/FPGA_Spartan6/M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ15" +Ne 79 "/FPGA_Spartan6/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ14" +Ne 14 "/DDR_Banks/M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3483,7 +3523,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2952 2558 $EndPAD $PAD @@ -3511,7 +3551,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po -1377 2558 $EndPAD $PAD @@ -3525,7 +3565,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -590 2558 $EndPAD $PAD @@ -3539,7 +3579,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po 196 2558 $EndPAD $PAD @@ -3553,7 +3593,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 983 2558 $EndPAD $PAD @@ -3567,7 +3607,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po 1771 2558 $EndPAD $PAD @@ -3602,14 +3642,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ14" +Ne 106 "/FPGA_Spartan6/M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ15" +Ne 107 "/FPGA_Spartan6/M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -3644,7 +3684,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po -2558 2952 $EndPAD $PAD @@ -3658,7 +3698,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -1771 2952 $EndPAD $PAD @@ -3721,7 +3761,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 1771 2952 $EndPAD $PAD @@ -3742,7 +3782,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 2952 2952 $EndPAD $PAD @@ -3938,7 +3978,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po -3346 3739 $EndPAD $PAD @@ -3952,7 +3992,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2558 3739 $EndPAD $PAD @@ -3966,7 +4006,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po -1771 3739 $EndPAD $PAD @@ -3980,7 +4020,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -983 3739 $EndPAD $PAD @@ -3994,7 +4034,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po -196 3739 $EndPAD $PAD @@ -4008,7 +4048,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 590 3739 $EndPAD $PAD @@ -4022,7 +4062,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po 1377 3739 $EndPAD $PAD @@ -4036,7 +4076,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 2165 3739 $EndPAD $PAD @@ -4050,7 +4090,7 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000101" +Ne 140 "N-000110" Po 2952 3739 $EndPAD $PAD @@ -4078,7 +4118,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -4133 4133 $EndPAD $PAD @@ -4225,7 +4265,7 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 @@ -4247,42 +4287,42 @@ $PAD Sh "12" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -1613 1082 $EndPAD $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_RXER" +Ne 58 "/FPGA_Spartan6/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_RXC" +Ne 54 "/FPGA_Spartan6/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_RXDV" +Ne 57 "/FPGA_Spartan6/ETH_RXDV" Po -1613 491 $EndPAD $PAD Sh "8" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -1613 295 $EndPAD $PAD Sh "7" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -1613 98 $EndPAD $PAD @@ -4303,14 +4343,14 @@ $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RXD2" +Ne 55 "/FPGA_Spartan6/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_RXD3" +Ne 56 "/FPGA_Spartan6/ETH_RXD3" Po -1613 -688 $EndPAD $PAD @@ -4324,28 +4364,28 @@ $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_MDIO" +Ne 44 "/Ethernet_Phy/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RESET_N" +Ne 53 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 45 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_CLK" +Ne 51 "/FPGA_Spartan6/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -4359,7 +4399,7 @@ $PAD Sh "44" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -295 -1613 $EndPAD $PAD @@ -4380,35 +4420,35 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 133 "N-000334" +Ne 141 "N-000327" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000346" +Ne 148 "N-000339" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_A3.3V" +Ne 38 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 138 "N-000344" +Ne 146 "N-000337" Po 1082 -1613 $EndPAD $PAD @@ -4457,21 +4497,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_A1.8V" +Ne 37 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 139 "N-000345" +Ne 147 "N-000338" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 134 "N-000335" +Ne 142 "N-000328" Po 1613 -491 $EndPAD $PAD @@ -4485,42 +4525,42 @@ $PAD Sh "35" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 1613 -1082 $EndPAD $PAD Sh "13" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_1.8V" +Ne 36 "/Ethernet_Phy/ETH_1.8V" Po -1082 1613 $EndPAD $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXER" +Ne 62 "/FPGA_Spartan6/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_TXC" +Ne 59 "/FPGA_Spartan6/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_TXEN" +Ne 50 "/Ethernet_Phy/ETH_TXEN" Po -491 1613 $EndPAD $PAD @@ -4534,14 +4574,14 @@ $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_TXD1" +Ne 48 "/Ethernet_Phy/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_TXD2" +Ne 49 "/Ethernet_Phy/ETH_TXD2" Po 98 1613 $EndPAD $PAD @@ -4555,28 +4595,28 @@ $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_COL" +Ne 39 "/Ethernet_Phy/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_CRS" +Ne 52 "/FPGA_Spartan6/ETH_CRS" Po 688 1613 $EndPAD $PAD Sh "23" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 885 1613 $EndPAD $PAD Sh "24" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po 1082 1613 $EndPAD $EndMODULE LQFP48 @@ -4840,14 +4880,14 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/Non_volatile_memories/FRB_N" +Ne 126 "/Non_volatile_memories/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/Non_volatile_memories/FRB_N" +Ne 126 "/Non_volatile_memories/NF_RNB" Po -1090 3850 $EndPAD $PAD @@ -4882,14 +4922,14 @@ $PAD Sh "12" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -100 3850 $EndPAD $PAD Sh "13" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 100 3850 $EndPAD $PAD @@ -4931,7 +4971,7 @@ $PAD Sh "19" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po 1280 3850 $EndPAD $PAD @@ -5001,28 +5041,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 123 "/Non_volatile_memories/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 114 "/FPGA_Spartan6/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 115 "/FPGA_Spartan6/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 116 "/FPGA_Spartan6/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -5050,14 +5090,14 @@ $PAD Sh "36" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 100 -3850 $EndPAD $PAD Sh "37" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 3 "+3.3V" Po -100 -3850 $EndPAD $PAD @@ -5085,28 +5125,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 117 "/FPGA_Spartan6/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 124 "/Non_volatile_memories/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 118 "/FPGA_Spartan6/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 125 "/Non_volatile_memories/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -5159,21 +5199,21 @@ $PAD Sh "1" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 123 "/Non_volatile_memories/SD_DAT2" +Ne 129 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 114 "/FPGA_Spartan6/SD_DAT3" +Ne 130 "/Non_volatile_memories/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 120 "/Non_volatile_memories/SD_CMD" +Ne 127 "/Non_volatile_memories/SD_CMD" Po -433 0 $EndPAD $PAD @@ -5187,56 +5227,56 @@ $PAD Sh "5" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 119 "/Non_volatile_memories/SD_CLK" +Ne 119 "/FPGA_Spartan6/SD_CLK" Po 433 0 $EndPAD $PAD Sh "6" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 866 0 $EndPAD $PAD Sh "7" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 121 "/Non_volatile_memories/SD_DAT0" +Ne 128 "/Non_volatile_memories/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 122 "/Non_volatile_memories/SD_DAT1" +Ne 120 "/FPGA_Spartan6/SD_DAT1" Po 1732 0 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 2707 -1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2707 -1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2707 2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 2707 2244 $EndPAD $EndMODULE MICROSD-500901 @@ -5256,112 +5296,112 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 135 "N-000336" +Ne 143 "N-000329" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 135 "N-000336" +Ne 143 "N-000329" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 135 "N-000336" +Ne 143 "N-000329" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 135 "N-000336" +Ne 143 "N-000329" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 133 "N-000334" +Ne 141 "N-000327" Po -1750 -2500 $EndPAD $PAD Sh "3" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 126 "3.3V" +Ne 134 "3.3V" Po -750 -2500 $EndPAD $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 127 "GND" +Ne 135 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 134 "N-000335" +Ne 142 "N-000328" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 140 "N-000346" +Ne 148 "N-000339" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 127 "GND" +Ne 135 "GND" Po -250 -3500 $EndPAD $PAD Sh "6" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 126 "3.3V" +Ne 134 "3.3V" Po 750 -3500 $EndPAD $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 139 "N-000345" +Ne 147 "N-000338" Po 1750 -3500 $EndPAD $PAD Sh "9" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 126 "3.3V" +Ne 134 "3.3V" Po -2150 -5400 $EndPAD $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 136 "N-000337" +Ne 144 "N-000330" Po -1150 -5400 $EndPAD $PAD Sh "11" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 126 "3.3V" +Ne 134 "3.3V" Po 1150 -5400 $EndPAD $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 142 "N-000350" +Ne 150 "N-000343" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -5397,28 +5437,28 @@ $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/USB/USBA_SPD" +Ne 132 "/USB/USBA_SPD" Po -511 1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/USB/USBA_RCV" +Ne 121 "/FPGA_Spartan6/USBA_RCV" Po -255 1112 $EndPAD $PAD Sh "4" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/USBA_VP" +Ne 122 "/FPGA_Spartan6/USBA_VP" Po 0 1112 $EndPAD $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/USBA_VM" +Ne 133 "/USB/USBA_VM" Po 255 1112 $EndPAD $PAD @@ -5432,42 +5472,42 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 767 1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 767 -1112 $EndPAD $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/USBA_OE_N" +Ne 131 "/USB/USBA_OE_N" Po 511 -1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 143 "N-000356" +Ne 151 "N-000349" Po 255 -1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 146 "N-000360" +Ne 154 "N-000353" Po 0 -1112 $EndPAD $PAD Sh "12" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -255 -1112 $EndPAD $PAD @@ -5481,7 +5521,7 @@ $PAD Sh "14" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -767 -1112 $EndPAD $EndMODULE TSSOP-14 @@ -5510,7 +5550,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_DQ0" +Ne 101 "/FPGA_Spartan6/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -5524,35 +5564,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_DQ1" +Ne 102 "/FPGA_Spartan6/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ2" +Ne 108 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ3" +Ne 28 "/DDR_Banks/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ4" +Ne 29 "/DDR_Banks/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -5566,28 +5606,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ5" +Ne 109 "/FPGA_Spartan6/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_DQ6" +Ne 30 "/DDR_Banks/M1_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ7" +Ne 31 "/DDR_Banks/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5608,7 +5648,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_LDQS" +Ne 32 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -5636,35 +5676,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_LDM" +Ne 112 "/FPGA_Spartan6/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_WE#" +Ne 35 "/DDR_Banks/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_CAS#" +Ne 99 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_RAS#" +Ne 33 "/DDR_Banks/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 1791 2176 $EndPAD $PAD @@ -5678,35 +5718,35 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_BA0" +Ne 98 "/FPGA_Spartan6/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_BA1" +Ne 24 "/DDR_Banks/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M1_A10" +Ne 21 "/DDR_Banks/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A0" +Ne 88 "/FPGA_Spartan6/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A1" +Ne 89 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD @@ -5734,14 +5774,14 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_A4" +Ne 94 "/FPGA_Spartan6/M1_A4" Po 3838 -2176 $EndPAD $PAD @@ -5755,35 +5795,35 @@ $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A6" +Ne 95 "/FPGA_Spartan6/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A7" +Ne 96 "/FPGA_Spartan6/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A8" +Ne 23 "/DDR_Banks/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A9" +Ne 97 "/FPGA_Spartan6/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_A11" +Ne 90 "/FPGA_Spartan6/M1_A11" Po 2303 -2176 $EndPAD $PAD @@ -5804,42 +5844,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_CLK#" +Ne 100 "/FPGA_Spartan6/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_CKE" +Ne 25 "/DDR_Banks/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_CLK" +Ne 26 "/DDR_Banks/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_UDM" +Ne 34 "/DDR_Banks/M1_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "N-000044" +Ne 137 "N-000050" Po 255 -2176 $EndPAD $PAD @@ -5853,14 +5893,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_UDQS" +Ne 113 "/FPGA_Spartan6/M1_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -511 -2176 $EndPAD $PAD @@ -5874,7 +5914,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ8" +Ne 110 "/FPGA_Spartan6/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -5888,35 +5928,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ9" +Ne 111 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_DQ10" +Ne 103 "/FPGA_Spartan6/M1_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ11" +Ne 104 "/FPGA_Spartan6/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ12" +Ne 27 "/DDR_Banks/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -5930,35 +5970,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_DQ13" +Ne 105 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ14" +Ne 106 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ15" +Ne 107 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -5987,7 +6027,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ0" +Ne 74 "/FPGA_Spartan6/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -6001,35 +6041,35 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ1" +Ne 75 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ2" +Ne 15 "/DDR_Banks/M0_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ3" +Ne 16 "/DDR_Banks/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ4" +Ne 17 "/DDR_Banks/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -6043,28 +6083,28 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_DQ5" +Ne 80 "/FPGA_Spartan6/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ6" +Ne 81 "/FPGA_Spartan6/M0_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ7" +Ne 82 "/FPGA_Spartan6/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -6085,7 +6125,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_LDQS" +Ne 85 "/FPGA_Spartan6/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -6113,35 +6153,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_LDM" +Ne 18 "/DDR_Banks/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_WE#" +Ne 20 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_CAS#" +Ne 9 "/DDR_Banks/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_RAS#" +Ne 19 "/DDR_Banks/M0_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 1791 2176 $EndPAD $PAD @@ -6155,49 +6195,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_BA0" +Ne 72 "/FPGA_Spartan6/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_BA1" +Ne 73 "/FPGA_Spartan6/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_A10" +Ne 65 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/M0_A0" +Ne 63 "/FPGA_Spartan6/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M0_A1" +Ne 64 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A2" +Ne 67 "/FPGA_Spartan6/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A3" +Ne 6 "/DDR_Banks/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -6211,7 +6251,7 @@ $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 4094 -2176 $EndPAD $PAD @@ -6225,14 +6265,14 @@ $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A5" +Ne 69 "/FPGA_Spartan6/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A6" +Ne 70 "/FPGA_Spartan6/M0_A6" Po 3326 -2176 $EndPAD $PAD @@ -6246,7 +6286,7 @@ $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A8" +Ne 8 "/DDR_Banks/M0_A8" Po 2814 -2176 $EndPAD $PAD @@ -6260,14 +6300,14 @@ $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A11" +Ne 5 "/DDR_Banks/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A12" +Ne 66 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6281,42 +6321,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_CLK#" +Ne 12 "/DDR_Banks/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_CKE" +Ne 10 "/DDR_Banks/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_CLK" +Ne 11 "/DDR_Banks/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_UDM" +Ne 86 "/FPGA_Spartan6/M0_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 130 "N-000045" +Ne 138 "N-000051" Po 255 -2176 $EndPAD $PAD @@ -6330,14 +6370,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_UDQS" +Ne 87 "/FPGA_Spartan6/M0_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -511 -2176 $EndPAD $PAD @@ -6351,7 +6391,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ8" +Ne 83 "/FPGA_Spartan6/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6365,35 +6405,35 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ9" +Ne 84 "/FPGA_Spartan6/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_DQ10" +Ne 13 "/DDR_Banks/M0_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ11" +Ne 76 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ12" +Ne 77 "/FPGA_Spartan6/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6407,35 +6447,35 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_DQ13" +Ne 78 "/FPGA_Spartan6/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ14" +Ne 14 "/DDR_Banks/M0_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ15" +Ne 79 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -6456,14 +6496,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 147 "N-000361" +Ne 155 "N-000354" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6484,14 +6524,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "N-000336" +Ne 143 "N-000329" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6512,7 +6552,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "N-000350" +Ne 150 "N-000343" Po -176 0 $EndPAD $PAD @@ -6540,7 +6580,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "N-000337" +Ne 144 "N-000330" Po -176 0 $EndPAD $PAD @@ -6568,14 +6608,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "N-000345" +Ne 147 "N-000338" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6596,14 +6636,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "N-000335" +Ne 142 "N-000328" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6624,14 +6664,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000346" +Ne 148 "N-000339" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6652,14 +6692,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "N-000334" +Ne 141 "N-000327" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6680,14 +6720,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "N-000344" +Ne 146 "N-000337" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6708,14 +6748,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_MDIO" +Ne 44 "/Ethernet_Phy/ETH_MDIO" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6736,14 +6776,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 147 "N-000361" +Ne 155 "N-000354" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6764,14 +6804,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "N-000336" +Ne 143 "N-000329" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6792,14 +6832,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6820,14 +6860,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6848,14 +6888,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 45 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "N-000347" +Ne 149 "N-000340" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6876,14 +6916,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_A3.3V" +Ne 38 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6904,14 +6944,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_A1.8V" +Ne 37 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "N-000347" +Ne 149 "N-000340" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6932,14 +6972,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6960,14 +7000,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000338" +Ne 145 "N-000331" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 141 "N-000347" +Ne 149 "N-000340" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6988,14 +7028,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7016,14 +7056,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_1.8V" +Ne 36 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7044,14 +7084,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 143 "N-000356" +Ne 151 "N-000349" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7072,14 +7112,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 146 "N-000360" +Ne 154 "N-000353" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7100,14 +7140,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_A1.8V" +Ne 37 "/Ethernet_Phy/ETH_A1.8V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 45 "/Ethernet_Phy/ETH_PLL1.8V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7128,14 +7168,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_A3.3V" +Ne 38 "/Ethernet_Phy/ETH_A3.3V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7156,14 +7196,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000338" +Ne 145 "N-000331" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_A1.8V" +Ne 37 "/Ethernet_Phy/ETH_A1.8V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7184,14 +7224,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 149 "N-000363" +Ne 157 "N-000356" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7212,14 +7252,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 149 "N-000363" +Ne 157 "N-000356" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7240,14 +7280,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 149 "N-000363" +Ne 157 "N-000356" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7268,14 +7308,14 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_A3.3V" +Ne 38 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7296,14 +7336,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "3.3V" +Ne 134 "3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7324,7 +7364,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 144 "N-000357" +Ne 152 "N-000350" Po -570 0 $EndPAD $PAD @@ -7357,56 +7397,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 148 "N-000362" +Ne 156 "N-000355" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 143 "N-000356" +Ne 151 "N-000349" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 146 "N-000360" +Ne 154 "N-000353" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 146 "N-000360" +Ne 154 "N-000353" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 147 "N-000361" +Ne 155 "N-000354" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 147 "N-000361" +Ne 155 "N-000354" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 147 "N-000361" +Ne 155 "N-000354" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 147 "N-000361" +Ne 155 "N-000354" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -7434,7 +7474,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "N-000045" +Ne 138 "N-000051" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7455,14 +7495,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "N-000045" +Ne 138 "N-000051" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "N-000047" +Ne 139 "N-000053" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7483,14 +7523,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "N-000044" +Ne 137 "N-000050" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "N-000043" +Ne 136 "N-000049" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7518,7 +7558,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "N-000044" +Ne 137 "N-000050" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7546,7 +7586,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "N-000045" +Ne 138 "N-000051" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7567,14 +7607,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "N-000045" +Ne 138 "N-000051" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "N-000047" +Ne 139 "N-000053" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7602,7 +7642,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "N-000044" +Ne 137 "N-000050" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7630,7 +7670,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7658,7 +7698,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7686,7 +7726,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7714,7 +7754,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7742,7 +7782,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7770,7 +7810,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7798,7 +7838,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7826,7 +7866,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7854,7 +7894,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7882,7 +7922,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7910,7 +7950,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7938,7 +7978,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7959,14 +7999,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "N-000044" +Ne 137 "N-000050" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "N-000043" +Ne 136 "N-000049" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7994,7 +8034,7 @@ $PAD Sh "2" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -8022,7 +8062,7 @@ $PAD Sh "2" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -8043,14 +8083,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "N-000358" +Ne 153 "N-000351" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "GND" +Ne 135 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8071,14 +8111,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "N-000357" +Ne 152 "N-000350" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "N-000362" +Ne 156 "N-000355" Po 294 0 $EndPAD $EndMODULE 0603 diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index f322bc5..fb7936d 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,66 +1,66 @@ -# EESchema Netlist Version 1.1 created Thu 12 Aug 2010 05:12:23 PM COT +# EESchema Netlist Version 1.1 created Thu 12 Aug 2010 09:08:23 PM COT ( ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000358 ) - ( 2 N-000363 ) + ( 1 N-000350 ) + ( 2 N-000355 ) ) ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000359 ) + ( 1 N-000351 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000362 ) + ( 1 N-000354 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000362 ) + ( 1 N-000354 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000361 ) + ( 1 N-000353 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000357 ) + ( 1 N-000349 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000358 ) + ( 1 N-000350 ) ( 2 +5V ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000362 ) - ( S2 N-000362 ) - ( S3 N-000362 ) - ( S4 N-000362 ) - ( 1 N-000363 ) - ( 2 N-000357 ) - ( 3 N-000361 ) - ( 4 N-000359 ) + ( S1 N-000354 ) + ( S2 N-000354 ) + ( S3 N-000354 ) + ( S4 N-000354 ) + ( 1 N-000355 ) + ( 2 N-000349 ) + ( 3 N-000353 ) + ( 4 N-000351 ) ) ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} - ( 1 N-000364 ) + ( 1 N-000356 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} - ( 1 N-000364 ) + ( 1 N-000356 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} - ( 1 N-000364 ) + ( 1 N-000356 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) - ( 2 /FPGA_Spartan6/USBA_SPD ) + ( 2 /USB/USBA_SPD ) ( 3 /FPGA_Spartan6/USBA_RCV ) ( 4 /FPGA_Spartan6/USBA_VP ) - ( 5 /FPGA_Spartan6/USBA_VM ) + ( 5 /USB/USBA_VM ) ( 7 GND ) ( 8 GND ) - ( 9 /FPGA_Spartan6/USBA_OE_N ) - ( 10 N-000357 ) - ( 11 N-000361 ) + ( 9 /USB/USBA_OE_N ) + ( 10 N-000349 ) + ( 11 N-000353 ) ( 12 3.3V ) ( 14 3.3V ) ) @@ -79,7 +79,7 @@ ( L6 ? ) ( K6 /DDR_Banks/M0_A3 ) ( J6 ? ) - ( H6 /FPGA_Spartan6/M0_A7 ) + ( H6 /DDR_Banks/M0_A7 ) ( G6 ? ) ( F6 +2.5V ) ( E6 ? ) @@ -97,7 +97,7 @@ ( H21 /DDR_Banks/M1_RAS# ) ( G21 +2.5V ) ( F21 /FPGA_Spartan6/M1_A0 ) - ( D21 /FPGA_Spartan6/M1_CKE ) + ( D21 /DDR_Banks/M1_CKE ) ( C21 +2.5V ) ( B21 ? ) ( A21 ? ) @@ -108,12 +108,12 @@ ( R20 /FPGA_Spartan6/M1_DQ10 ) ( P20 ? ) ( N20 /FPGA_Spartan6/M1_DQ0 ) - ( M20 /FPGA_Spartan6/M1_UDM ) + ( M20 /DDR_Banks/M1_UDM ) ( L20 /DDR_Banks/M1_LDQS ) - ( K20 /FPGA_Spartan6/M1_A5 ) + ( K20 /DDR_Banks/M1_A5 ) ( J20 /DDR_Banks/M1_DQ4 ) ( H20 /DDR_Banks/M1_CLK ) - ( G20 /DDR_Banks/M1_A3 ) + ( G20 /FPGA_Spartan6/M1_A3 ) ( F20 /FPGA_Spartan6/M1_A4 ) ( E20 /FPGA_Spartan6/M1_A7 ) ( D20 ? ) @@ -126,34 +126,34 @@ ( H8 ? ) ( B3 ? ) ( W2 +2.5V ) - ( V2 /FPGA_Spartan6/M0_DQ14 ) - ( T2 /DDR_Banks/M0_UDQS ) + ( V2 /DDR_Banks/M0_DQ14 ) + ( T2 /FPGA_Spartan6/M0_UDQS ) ( R2 +2.5V ) - ( P2 /DDR_Banks/M0_DQ8 ) - ( M2 /FPGA_Spartan6/M0_DQ2 ) + ( P2 /FPGA_Spartan6/M0_DQ8 ) + ( M2 /DDR_Banks/M0_DQ2 ) ( L2 +2.5V ) ( K2 /FPGA_Spartan6/M0_DQ6 ) ( H2 /FPGA_Spartan6/M0_A0 ) ( G2 +2.5V ) ( F2 /DDR_Banks/M0_WE# ) - ( D2 /FPGA_Spartan6/M0_CKE ) + ( D2 /DDR_Banks/M0_CKE ) ( C2 +2.5V ) ( B2 ? ) ( A2 ? ) ( Y1 ? ) ( W1 ? ) ( V1 /FPGA_Spartan6/M0_DQ15 ) - ( U1 /DDR_Banks/M0_DQ13 ) + ( U1 /FPGA_Spartan6/M0_DQ13 ) ( T1 ? ) - ( R1 /DDR_Banks/M0_DQ11 ) + ( R1 /FPGA_Spartan6/M0_DQ11 ) ( P1 /FPGA_Spartan6/M0_DQ9 ) - ( N1 /DDR_Banks/M0_DQ1 ) - ( M1 /FPGA_Spartan6/M0_DQ3 ) + ( N1 /FPGA_Spartan6/M0_DQ1 ) + ( M1 /DDR_Banks/M0_DQ3 ) ( L1 ? ) - ( K1 /DDR_Banks/M0_DQ7 ) + ( K1 /FPGA_Spartan6/M0_DQ7 ) ( J1 /FPGA_Spartan6/M0_DQ5 ) ( H1 /FPGA_Spartan6/M0_A1 ) - ( G1 /DDR_Banks/M0_BA1 ) + ( G1 /FPGA_Spartan6/M0_BA1 ) ( T4 ? ) ( R4 ? ) ( P4 ? ) @@ -161,57 +161,57 @@ ( M4 ? ) ( L4 /DDR_Banks/M0_LDM ) ( K4 /DDR_Banks/M0_CAS# ) - ( J4 /DDR_Banks/M0_A6 ) - ( H4 /FPGA_Spartan6/M0_CLK ) - ( G4 /DDR_Banks/M0_A10 ) + ( J4 /FPGA_Spartan6/M0_A6 ) + ( H4 /DDR_Banks/M0_CLK ) + ( G4 /FPGA_Spartan6/M0_A10 ) ( F4 +2.5V ) ( E4 ? ) ( C4 ? ) ( W3 ? ) ( V3 ? ) - ( U3 /DDR_Banks/M0_DQ12 ) + ( U3 /FPGA_Spartan6/M0_DQ12 ) ( T3 ? ) ( R3 /DDR_Banks/M0_DQ10 ) ( P3 ? ) ( N3 /FPGA_Spartan6/M0_DQ0 ) ( M3 /FPGA_Spartan6/M0_UDM ) - ( L3 /DDR_Banks/M0_LDQS ) + ( L3 /FPGA_Spartan6/M0_LDQS ) ( K3 /FPGA_Spartan6/M0_A5 ) ( J3 /DDR_Banks/M0_DQ4 ) - ( H3 /FPGA_Spartan6/M0_CLK# ) + ( H3 /DDR_Banks/M0_CLK# ) ( G3 /FPGA_Spartan6/M0_BA0 ) ( F3 /FPGA_Spartan6/M0_A4 ) - ( E3 /FPGA_Spartan6/M0_A8 ) + ( E3 /DDR_Banks/M0_A8 ) ( D3 ? ) ( C3 ? ) ( G10 +3.3V ) - ( D10 /Ethernet_Phy/ETH_RXC ) + ( D10 /FPGA_Spartan6/ETH_RXC ) ( C10 /FPGA_Spartan6/ETH_CLK ) - ( B10 /Ethernet_Phy/ETH_CRS ) + ( B10 /FPGA_Spartan6/ETH_CRS ) ( A10 /Ethernet_Phy/ETH_COL ) ( E9 +3.3V ) - ( D9 /FPGA_Spartan6/ETH_TXEN ) - ( C9 /FPGA_Spartan6/ETH_TXD1 ) + ( D9 /Ethernet_Phy/ETH_TXEN ) + ( C9 /Ethernet_Phy/ETH_TXD1 ) ( A9 /Ethernet_Phy/ETH_TXD2 ) ( D8 /FPGA_Spartan6/ETH_TXC ) - ( C8 /Ethernet_Phy/ETH_TXD0 ) + ( C8 /FPGA_Spartan6/ETH_TXD0 ) ( B8 /FPGA_Spartan6/ETH_RXER ) ( A8 /FPGA_Spartan6/ETH_TXER ) ( D7 /FPGA_Spartan6/ETH_TXD3 ) ( C7 /Ethernet_Phy/ETH_RXD0 ) ( B7 +3.3V ) - ( A7 /Ethernet_Phy/ETH_RXDV ) + ( A7 /FPGA_Spartan6/ETH_RXDV ) ( D6 /FPGA_Spartan6/ETH_RESET_N ) - ( C6 /Ethernet_Phy/ETH_RXD3 ) - ( B6 /Ethernet_Phy/ETH_RXD2 ) + ( C6 /FPGA_Spartan6/ETH_RXD3 ) + ( B6 /FPGA_Spartan6/ETH_RXD2 ) ( A6 /Ethernet_Phy/ETH_RXD1 ) ( C5 /Ethernet_Phy/ETH_MDC ) - ( A5 /FPGA_Spartan6/ETH_MDIO ) + ( A5 /Ethernet_Phy/ETH_MDIO ) ( B4 +3.3V ) - ( A4 /FPGA_Spartan6/ETH_INT ) + ( A4 /Ethernet_Phy/ETH_INT ) ( U19 ? ) ( T19 ? ) - ( R19 /FPGA_Spartan6/USBA_SPD ) + ( R19 /USB/USBA_SPD ) ( P19 ? ) ( N19 ? ) ( B19 +3.3V ) @@ -230,45 +230,45 @@ ( B15 +3.3V ) ( A15 ? ) ( G14 +3.3V ) - ( D14 ? ) + ( D14 /Non_volatile_memories/NF_D0 ) ( C14 ? ) ( B14 ? ) ( A14 ? ) ( E13 +3.3V ) - ( C13 ? ) - ( A13 ? ) - ( C12 ? ) - ( B12 ? ) - ( A12 ? ) - ( D11 ? ) + ( C13 /FPGA_Spartan6/NF_D2 ) + ( A13 /FPGA_Spartan6/NF_D1 ) + ( C12 /Non_volatile_memories/NF_D5 ) + ( B12 /FPGA_Spartan6/NF_D4 ) + ( A12 /FPGA_Spartan6/NF_D3 ) + ( D11 /FPGA_Spartan6/NF_D6 ) ( C11 ? ) ( B11 +3.3V ) - ( A11 ? ) + ( A11 /Non_volatile_memories/NF_D7 ) ( H16 ? ) ( G16 ? ) ( F16 ? ) ( L15 ? ) ( W22 ? ) - ( V22 /DDR_Banks/M1_DQ15 ) + ( V22 /FPGA_Spartan6/M1_DQ15 ) ( U22 /FPGA_Spartan6/M1_DQ13 ) ( T22 ? ) ( R22 /FPGA_Spartan6/M1_DQ11 ) - ( P22 /DDR_Banks/M1_DQ9 ) + ( P22 /FPGA_Spartan6/M1_DQ9 ) ( N22 /FPGA_Spartan6/M1_DQ1 ) - ( M22 /FPGA_Spartan6/M1_DQ3 ) + ( M22 /DDR_Banks/M1_DQ3 ) ( L22 ? ) - ( K22 /FPGA_Spartan6/M1_DQ7 ) - ( J22 /DDR_Banks/M1_DQ5 ) - ( H22 /DDR_Banks/M1_CAS# ) + ( K22 /DDR_Banks/M1_DQ7 ) + ( J22 /FPGA_Spartan6/M1_DQ5 ) + ( H22 /FPGA_Spartan6/M1_CAS# ) ( G22 ? ) ( F22 /FPGA_Spartan6/M1_A1 ) ( E22 /FPGA_Spartan6/M1_A2 ) ( D22 /FPGA_Spartan6/M1_A12 ) - ( C22 /DDR_Banks/M1_A9 ) + ( C22 /FPGA_Spartan6/M1_A9 ) ( B22 ? ) ( W21 +2.5V ) ( V21 /FPGA_Spartan6/M1_DQ14 ) - ( T21 /DDR_Banks/M1_UDQS ) + ( T21 /FPGA_Spartan6/M1_UDQS ) ( R21 +2.5V ) ( P21 /FPGA_Spartan6/M1_DQ8 ) ( M21 /FPGA_Spartan6/M1_DQ2 ) @@ -278,15 +278,15 @@ ( L19 /FPGA_Spartan6/M1_LDM ) ( K19 /FPGA_Spartan6/M1_A6 ) ( J19 /FPGA_Spartan6/M1_CLK# ) - ( H19 /FPGA_Spartan6/M1_WE# ) - ( G19 /FPGA_Spartan6/M1_A10 ) + ( H19 /DDR_Banks/M1_WE# ) + ( G19 /DDR_Banks/M1_A10 ) ( F19 /FPGA_Spartan6/M1_A11 ) ( E19 +2.5V ) ( D19 ? ) ( U18 +2.5V ) - ( P18 /FPGA_Spartan6/USBA_OE_N ) + ( P18 /USB/USBA_OE_N ) ( N18 +2.5V ) - ( M18 /FPGA_Spartan6/USBA_VM ) + ( M18 /USB/USBA_VM ) ( K18 ? ) ( J18 +2.5V ) ( H18 ? ) @@ -294,7 +294,7 @@ ( P17 /FPGA_Spartan6/USBA_VP ) ( M17 ? ) ( L17 ? ) - ( K17 /FPGA_Spartan6/M1_BA1 ) + ( K17 /DDR_Banks/M1_BA1 ) ( J17 /FPGA_Spartan6/M1_BA0 ) ( H17 ? ) ( G17 ? ) @@ -432,7 +432,7 @@ ( V18 ? ) ( T18 ? ) ( AB7 ? ) - ( AA7 N-000118 ) + ( AA7 N-000110 ) ( Y17 ? ) ( W17 ? ) ( V17 ? ) @@ -441,7 +441,7 @@ ( AB6 ? ) ( AA6 ? ) ( Y16 ? ) - ( V16 N-000118 ) + ( V16 N-000110 ) ( U16 ? ) ( T16 ? ) ( R16 ? ) @@ -456,18 +456,18 @@ ( AA4 ? ) ( F1 ? ) ( E1 /FPGA_Spartan6/M0_A9 ) - ( D1 /DDR_Banks/M0_A12 ) - ( C1 /FPGA_Spartan6/M0_A11 ) + ( D1 /FPGA_Spartan6/M0_A12 ) + ( C1 /DDR_Banks/M0_A11 ) ( B1 ? ) ( AB19 ? ) - ( AA19 N-000118 ) + ( AA19 N-000110 ) ( AB18 ? ) ( AA18 ? ) ( AB17 ? ) ( AB16 ? ) ( AA16 ? ) ( AB15 ? ) - ( AA15 N-000118 ) + ( AA15 N-000110 ) ( AB14 ? ) ( AA14 ? ) ( AB13 ? ) @@ -477,7 +477,7 @@ ( AB21 ? ) ( AA21 ? ) ( AB11 ? ) - ( AA11 N-000118 ) + ( AA11 N-000110 ) ( AB20 ? ) ( AA20 ? ) ( AB10 ? ) @@ -486,11 +486,11 @@ ( Y19 ? ) ( V9 ? ) ( U9 ? ) - ( T9 N-000118 ) + ( T9 N-000110 ) ( R9 ? ) ( Y8 ? ) ( W8 ? ) - ( V8 N-000118 ) + ( V8 N-000110 ) ( U8 ? ) ( T8 ? ) ( R8 ? ) @@ -503,7 +503,7 @@ ( U6 ? ) ( T6 ? ) ( Y5 ? ) - ( W5 N-000118 ) + ( W5 N-000110 ) ( V5 ? ) ( T5 ? ) ( Y4 ? ) @@ -519,18 +519,18 @@ ( U14 ? ) ( T14 ? ) ( AB3 ? ) - ( AA3 N-000118 ) + ( AA3 N-000110 ) ( Y13 ? ) ( W13 ? ) ( V13 ? ) ( U13 ? ) - ( T13 N-000118 ) + ( T13 N-000110 ) ( R13 ? ) ( AB2 ? ) ( AA2 ? ) ( Y12 ? ) ( W12 ? ) - ( V12 N-000118 ) + ( V12 N-000110 ) ( U12 ? ) ( T12 ? ) ( Y11 ? ) @@ -547,7 +547,7 @@ ) ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} ( 1 /Ethernet_Phy/ETH_PLL1.8V ) - ( 2 N-000348 ) + ( 2 N-000340 ) ) ( /4C4320F3/4C5D810A $noname L3 INDUCTOR {Lib=INDUCTOR} ( 1 /Ethernet_Phy/ETH_A1.8V ) @@ -555,15 +555,15 @@ ) ( /4C4320F3/4C5D8104 $noname C6 C {Lib=C} ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 N-000348 ) + ( 2 N-000340 ) ) ( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR} - ( 1 N-000339 ) + ( 1 N-000331 ) ( 2 /Ethernet_Phy/ETH_A1.8V ) ) ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} - ( 1 N-000339 ) - ( 2 N-000348 ) + ( 1 N-000331 ) + ( 2 N-000340 ) ) ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} ( 1 /Ethernet_Phy/ETH_1.8V ) @@ -594,11 +594,11 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} - ( 1 /FPGA_Spartan6/ETH_MDIO ) + ( 1 /Ethernet_Phy/ETH_MDIO ) ( 2 3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000345 ) + ( 1 N-000337 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} @@ -610,55 +610,55 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000337 ) + ( 1 N-000329 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000337 ) + ( 1 N-000329 ) ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /FPGA_Spartan6/ETH_MDIO ) + ( 1 /Ethernet_Phy/ETH_MDIO ) ( 2 /Ethernet_Phy/ETH_MDC ) - ( 3 /Ethernet_Phy/ETH_RXD3 ) - ( 4 /Ethernet_Phy/ETH_RXD2 ) + ( 3 /FPGA_Spartan6/ETH_RXD3 ) + ( 4 /FPGA_Spartan6/ETH_RXD2 ) ( 5 /Ethernet_Phy/ETH_RXD1 ) ( 6 /Ethernet_Phy/ETH_RXD0 ) ( 7 3.3V ) ( 8 GND ) - ( 9 /Ethernet_Phy/ETH_RXDV ) - ( 10 /Ethernet_Phy/ETH_RXC ) + ( 9 /FPGA_Spartan6/ETH_RXDV ) + ( 10 /FPGA_Spartan6/ETH_RXC ) ( 11 /FPGA_Spartan6/ETH_RXER ) ( 12 GND ) ( 13 /Ethernet_Phy/ETH_1.8V ) ( 14 /FPGA_Spartan6/ETH_TXER ) ( 15 /FPGA_Spartan6/ETH_TXC ) - ( 16 /FPGA_Spartan6/ETH_TXEN ) - ( 17 /Ethernet_Phy/ETH_TXD0 ) - ( 18 /FPGA_Spartan6/ETH_TXD1 ) + ( 16 /Ethernet_Phy/ETH_TXEN ) + ( 17 /FPGA_Spartan6/ETH_TXD0 ) + ( 18 /Ethernet_Phy/ETH_TXD1 ) ( 19 /Ethernet_Phy/ETH_TXD2 ) ( 20 /FPGA_Spartan6/ETH_TXD3 ) ( 21 /Ethernet_Phy/ETH_COL ) - ( 22 /Ethernet_Phy/ETH_CRS ) + ( 22 /FPGA_Spartan6/ETH_CRS ) ( 23 GND ) ( 24 3.3V ) - ( 25 /FPGA_Spartan6/ETH_INT ) + ( 25 /Ethernet_Phy/ETH_INT ) ( 26 /Ethernet_Phy/ETH_LED0 ) ( 27 /Ethernet_Phy/ETH_LED1 ) ( 28 ? ) ( 29 ? ) ( 30 ? ) ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000346 ) - ( 33 N-000336 ) + ( 32 N-000338 ) + ( 33 N-000328 ) ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000345 ) + ( 37 N-000337 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) - ( 40 N-000347 ) - ( 41 N-000335 ) + ( 40 N-000339 ) + ( 41 N-000327 ) ( 42 ? ) ( 43 ? ) ( 44 GND ) @@ -669,43 +669,43 @@ ) ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000335 ) + ( 2 N-000327 ) ) ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000347 ) + ( 2 N-000339 ) ) ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000346 ) + ( 2 N-000338 ) ) ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000336 ) + ( 2 N-000328 ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000351 ) + ( 1 N-000343 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000338 ) + ( 1 N-000330 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000335 ) - ( 2 N-000347 ) + ( 1 N-000327 ) + ( 2 N-000339 ) ( 3 3.3V ) ( 4 GND ) ( 5 GND ) ( 6 3.3V ) - ( 7 N-000336 ) - ( 8 N-000346 ) + ( 7 N-000328 ) + ( 8 N-000338 ) ( 9 3.3V ) - ( 10 N-000338 ) + ( 10 N-000330 ) ( 11 3.3V ) - ( 12 N-000351 ) - ( 13 N-000337 ) - ( 14 N-000337 ) + ( 12 N-000343 ) + ( 13 N-000329 ) + ( 14 N-000329 ) ) ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} ( CASE GND ) @@ -749,10 +749,10 @@ ( 26 ? ) ( 27 ? ) ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 ? ) - ( 32 ? ) + ( 29 /Non_volatile_memories/NF_D0 ) + ( 30 /FPGA_Spartan6/NF_D1 ) + ( 31 /FPGA_Spartan6/NF_D2 ) + ( 32 /FPGA_Spartan6/NF_D3 ) ( 33 ? ) ( 34 ? ) ( 35 ? ) @@ -761,10 +761,10 @@ ( 38 ? ) ( 39 ? ) ( 40 ? ) - ( 41 ? ) - ( 42 ? ) - ( 43 ? ) - ( 44 ? ) + ( 41 /FPGA_Spartan6/NF_D4 ) + ( 42 /Non_volatile_memories/NF_D5 ) + ( 43 /FPGA_Spartan6/NF_D6 ) + ( 44 /Non_volatile_memories/NF_D7 ) ( 45 ? ) ( 46 ? ) ( 47 ? ) @@ -865,13 +865,13 @@ ( 4 /FPGA_Spartan6/M1_DQ1 ) ( 5 /FPGA_Spartan6/M1_DQ2 ) ( 6 GND ) - ( 7 /FPGA_Spartan6/M1_DQ3 ) + ( 7 /DDR_Banks/M1_DQ3 ) ( 8 /DDR_Banks/M1_DQ4 ) ( 9 +2.5V ) - ( 10 /DDR_Banks/M1_DQ5 ) + ( 10 /FPGA_Spartan6/M1_DQ5 ) ( 11 /DDR_Banks/M1_DQ6 ) ( 12 GND ) - ( 13 /FPGA_Spartan6/M1_DQ7 ) + ( 13 /DDR_Banks/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /DDR_Banks/M1_LDQS ) @@ -879,42 +879,42 @@ ( 18 +2.5V ) ( 19 ? ) ( 20 /FPGA_Spartan6/M1_LDM ) - ( 21 /FPGA_Spartan6/M1_WE# ) - ( 22 /DDR_Banks/M1_CAS# ) + ( 21 /DDR_Banks/M1_WE# ) + ( 22 /FPGA_Spartan6/M1_CAS# ) ( 23 /DDR_Banks/M1_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /FPGA_Spartan6/M1_BA0 ) - ( 27 /FPGA_Spartan6/M1_BA1 ) - ( 28 /FPGA_Spartan6/M1_A10 ) + ( 27 /DDR_Banks/M1_BA1 ) + ( 28 /DDR_Banks/M1_A10 ) ( 29 /FPGA_Spartan6/M1_A0 ) ( 30 /FPGA_Spartan6/M1_A1 ) ( 31 /FPGA_Spartan6/M1_A2 ) - ( 32 /DDR_Banks/M1_A3 ) + ( 32 /FPGA_Spartan6/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M1_A4 ) - ( 36 /FPGA_Spartan6/M1_A5 ) + ( 36 /DDR_Banks/M1_A5 ) ( 37 /FPGA_Spartan6/M1_A6 ) ( 38 /FPGA_Spartan6/M1_A7 ) ( 39 /DDR_Banks/M1_A8 ) - ( 40 /DDR_Banks/M1_A9 ) + ( 40 /FPGA_Spartan6/M1_A9 ) ( 41 /FPGA_Spartan6/M1_A11 ) ( 42 /FPGA_Spartan6/M1_A12 ) ( 43 ? ) ( 44 /FPGA_Spartan6/M1_CLK# ) - ( 45 /FPGA_Spartan6/M1_CKE ) + ( 45 /DDR_Banks/M1_CKE ) ( 46 /DDR_Banks/M1_CLK ) - ( 47 /FPGA_Spartan6/M1_UDM ) + ( 47 /DDR_Banks/M1_UDM ) ( 48 GND ) ( 49 N-000050 ) ( 50 ? ) - ( 51 /DDR_Banks/M1_UDQS ) + ( 51 /FPGA_Spartan6/M1_UDQS ) ( 52 GND ) ( 53 ? ) ( 54 /FPGA_Spartan6/M1_DQ8 ) ( 55 +2.5V ) - ( 56 /DDR_Banks/M1_DQ9 ) + ( 56 /FPGA_Spartan6/M1_DQ9 ) ( 57 /FPGA_Spartan6/M1_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M1_DQ11 ) @@ -923,26 +923,26 @@ ( 62 /FPGA_Spartan6/M1_DQ13 ) ( 63 /FPGA_Spartan6/M1_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M1_DQ15 ) + ( 65 /FPGA_Spartan6/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) ( 2 /FPGA_Spartan6/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /DDR_Banks/M0_DQ1 ) - ( 5 /FPGA_Spartan6/M0_DQ2 ) + ( 4 /FPGA_Spartan6/M0_DQ1 ) + ( 5 /DDR_Banks/M0_DQ2 ) ( 6 GND ) - ( 7 /FPGA_Spartan6/M0_DQ3 ) + ( 7 /DDR_Banks/M0_DQ3 ) ( 8 /DDR_Banks/M0_DQ4 ) ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M0_DQ5 ) ( 11 /FPGA_Spartan6/M0_DQ6 ) ( 12 GND ) - ( 13 /DDR_Banks/M0_DQ7 ) + ( 13 /FPGA_Spartan6/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /DDR_Banks/M0_LDQS ) + ( 16 /FPGA_Spartan6/M0_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) @@ -953,8 +953,8 @@ ( 24 GND ) ( 25 ? ) ( 26 /FPGA_Spartan6/M0_BA0 ) - ( 27 /DDR_Banks/M0_BA1 ) - ( 28 /DDR_Banks/M0_A10 ) + ( 27 /FPGA_Spartan6/M0_BA1 ) + ( 28 /FPGA_Spartan6/M0_A10 ) ( 29 /FPGA_Spartan6/M0_A0 ) ( 30 /FPGA_Spartan6/M0_A1 ) ( 31 /FPGA_Spartan6/M0_A2 ) @@ -963,33 +963,33 @@ ( 34 GND ) ( 35 /FPGA_Spartan6/M0_A4 ) ( 36 /FPGA_Spartan6/M0_A5 ) - ( 37 /DDR_Banks/M0_A6 ) - ( 38 /FPGA_Spartan6/M0_A7 ) - ( 39 /FPGA_Spartan6/M0_A8 ) + ( 37 /FPGA_Spartan6/M0_A6 ) + ( 38 /DDR_Banks/M0_A7 ) + ( 39 /DDR_Banks/M0_A8 ) ( 40 /FPGA_Spartan6/M0_A9 ) - ( 41 /FPGA_Spartan6/M0_A11 ) - ( 42 /DDR_Banks/M0_A12 ) + ( 41 /DDR_Banks/M0_A11 ) + ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) - ( 44 /FPGA_Spartan6/M0_CLK# ) - ( 45 /FPGA_Spartan6/M0_CKE ) - ( 46 /FPGA_Spartan6/M0_CLK ) + ( 44 /DDR_Banks/M0_CLK# ) + ( 45 /DDR_Banks/M0_CKE ) + ( 46 /DDR_Banks/M0_CLK ) ( 47 /FPGA_Spartan6/M0_UDM ) ( 48 GND ) ( 49 N-000051 ) ( 50 ? ) - ( 51 /DDR_Banks/M0_UDQS ) + ( 51 /FPGA_Spartan6/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M0_DQ8 ) + ( 54 /FPGA_Spartan6/M0_DQ8 ) ( 55 +2.5V ) ( 56 /FPGA_Spartan6/M0_DQ9 ) ( 57 /DDR_Banks/M0_DQ10 ) ( 58 GND ) - ( 59 /DDR_Banks/M0_DQ11 ) - ( 60 /DDR_Banks/M0_DQ12 ) + ( 59 /FPGA_Spartan6/M0_DQ11 ) + ( 60 /FPGA_Spartan6/M0_DQ12 ) ( 61 +2.5V ) - ( 62 /DDR_Banks/M0_DQ13 ) - ( 63 /FPGA_Spartan6/M0_DQ14 ) + ( 62 /FPGA_Spartan6/M0_DQ13 ) + ( 63 /DDR_Banks/M0_DQ14 ) ( 64 GND ) ( 65 /FPGA_Spartan6/M0_DQ15 ) ( 66 GND ) @@ -1261,8 +1261,8 @@ Net 2 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" U1 D8 U4 15 Net 3 "/DDR Banks/M0_WE#" "M0_WE#" - U2 21 U1 F2 + U2 21 Net 4 "/Non volatile memories/NF_RNB" "NF_RNB" U5 7 U5 6 @@ -1270,12 +1270,12 @@ Net 11 "/Non volatile memories/SD_CMD" "SD_CMD" J1 3 U1 D17 Net 12 "/FPGA Spartan6/SD_CLK" "SD_CLK" - U1 E16 J1 5 -Net 13 "/FPGA Spartan6/ETH_INT" "ETH_INT" + U1 E16 +Net 13 "/Ethernet Phy/ETH_INT" "ETH_INT" U1 A4 U4 25 -Net 14 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" +Net 14 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" U1 A7 U4 9 Net 15 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" @@ -1284,694 +1284,718 @@ Net 15 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" Net 16 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" U1 A8 U4 14 -Net 17 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" +Net 17 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" U1 D9 U4 16 Net 18 "/Ethernet Phy/ETH_MDC" "ETH_MDC" - U1 C5 U4 2 -Net 19 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" + U1 C5 +Net 19 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" + R1 1 U1 A5 U4 1 - R1 1 Net 20 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" U1 D6 U4 48 -Net 21 "/Ethernet Phy/ETH_RXC" "ETH_RXC" - U1 D10 +Net 21 "/FPGA Spartan6/ETH_RXC" "ETH_RXC" U4 10 + U1 D10 Net 22 "/Ethernet Phy/ETH_COL" "ETH_COL" - U4 21 U1 A10 -Net 23 "/Ethernet Phy/ETH_CRS" "ETH_CRS" + U4 21 +Net 23 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" U1 B10 U4 22 -Net 24 "/FPGA Spartan6/M1_UDM" "M1_UDM" +Net 24 "/DDR Banks/M1_UDM" "M1_UDM" U1 M20 U3 47 Net 25 "/DDR Banks/M1_LDQS" "M1_LDQS" - U1 L20 U3 16 + U1 L20 Net 26 "/FPGA Spartan6/M1_LDM" "M1_LDM" U3 20 U1 L19 -Net 27 "/DDR Banks/M1_UDQS" "M1_UDQS" - U1 T21 +Net 27 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" U3 51 -Net 28 "/DDR Banks/M0_UDQS" "M0_UDQS" - U1 T2 + U1 T21 +Net 28 "/FPGA Spartan6/M0_UDQS" "M0_UDQS" U2 51 + U1 T2 Net 29 "/DDR Banks/M0_LDM" "M0_LDM" U1 L4 U2 20 -Net 30 "/DDR Banks/M1_CAS#" "M1_CAS#" - U3 22 +Net 30 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" U1 H22 -Net 31 "/FPGA Spartan6/M1_CKE" "M1_CKE" + U3 22 +Net 31 "/DDR Banks/M1_CKE" "M1_CKE" U1 D21 U3 45 Net 32 "GND" "GND" - U1 W16 - U1 D4 - U1 V4 - U5 13 - U1 AA5 - U1 B5 - U5 36 - U1 E21 - U4 8 - C12 2 - U1 J2 - U1 E2 - U1 A1 - U1 B17 - U1 U2 - U1 N2 - U3 64 - U1 N11 - U1 L11 - J1 6 - U1 J11 - U1 V10 - U1 P10 - V1 2 - U1 M10 - U3 12 - U2 64 - U2 34 - U2 24 - U2 58 - U2 48 - U3 6 - U2 66 - U2 6 + U4 44 + U1 G5 + V2 2 + U1 AA9 + U1 AB22 + U1 AA13 + U4 23 + U1 AA17 + C15 2 + U1 N13 + C10 2 + U1 K14 U3 66 - R9 2 + U1 M14 + C11 2 + R2 2 + U1 P14 + U1 V14 U3 48 U3 58 U3 52 - U2 52 - U2 12 + U1 E15 U3 24 U3 34 - U1 N9 - U1 B13 - U4 12 - U1 A22 - U1 P12 - R10 2 - U1 M12 - U1 J15 - U1 AB1 - U1 U21 - U1 N21 - U1 J21 + U3 64 + L5 2 + U1 V10 U1 K10 + U1 M10 + U1 P10 + U4 12 + U1 B9 + C13 2 + C14 2 + U1 J11 + U1 L11 + U1 N11 + U1 J9 + U6 8 + U6 7 + U1 B17 + U1 W16 + U5 13 + U1 AA5 + U1 W7 + U1 U7 + U1 H7 J1 COM J1 CASE J1 CASE J1 CASE - C16 2 - C11 2 - R2 2 - U1 B9 - J4 4 - J4 5 - U4 44 - L5 2 - C24 2 - C25 2 - C23 2 - C22 2 - U1 AA9 - U1 AB22 - C31 2 - C30 2 - C32 2 - U1 AA13 - C27 2 - U1 AA17 - U6 7 - U6 8 - C21 2 - U1 H7 - U4 23 - U1 E7 - C8 2 + R9 2 + U1 J15 U1 R5 - C7 2 - C5 2 - C3 2 - C1 2 + U5 36 U1 L5 - U1 G5 - U1 W7 - U1 U7 - U1 W19 - U1 J13 - U4 35 - U1 L13 - U1 N13 - U4 36 - U1 L9 - U1 J9 - U1 K14 - U4 39 - V2 2 - U1 N17 - U1 D18 - U1 G18 - U1 L18 + U1 E7 + U2 34 + U2 24 U1 R18 - U1 P14 - C33 2 - U1 V14 - U1 E15 - C15 2 - C28 2 - C29 2 - C14 2 - C13 2 - C2 2 + U1 L18 + U1 G18 + U2 58 + U2 48 + U1 D18 + U1 N17 + U2 66 + U3 6 + U1 L13 + U1 J13 + U1 W19 + U3 12 + U2 64 + C12 2 + J1 6 + U4 8 + U2 6 + U2 52 + U2 12 + C30 2 + C31 2 + C22 2 + C23 2 + C25 2 + C24 2 C26 2 - C10 2 + C29 2 + C21 2 + C27 2 + C32 2 + C2 2 + U1 L9 + C28 2 + C33 2 C34 2 - U1 M14 -Net 33 "/FPGA Spartan6/M0_CKE" "M0_CKE" - U1 D2 + U4 39 + U1 E21 + U1 A1 + U1 E2 + U1 J2 + U1 N2 + U1 U2 + U1 D4 + C1 2 + C3 2 + C5 2 + C7 2 + U1 V4 + C8 2 + U1 B5 + U1 U21 + J4 5 + J4 4 + U1 AB1 + U1 J21 + U1 N21 + V1 2 + U1 P12 + U1 A22 + U1 B13 + U1 N9 + C16 2 + R10 2 + U4 36 + U4 35 + U1 M12 +Net 33 "/DDR Banks/M0_CKE" "M0_CKE" U2 45 + U1 D2 Net 34 "/DDR Banks/M0_CAS#" "M0_CAS#" U1 K4 U2 22 -Net 35 "/FPGA Spartan6/M1_WE#" "M1_WE#" +Net 35 "/DDR Banks/M1_WE#" "M1_WE#" U1 H19 U3 21 Net 36 "/DDR Banks/M1_RAS#" "M1_RAS#" - U3 23 U1 H21 + U3 23 Net 37 "/DDR Banks/M0_RAS#" "M0_RAS#" - U2 23 U1 K5 -Net 38 "/DDR Banks/M0_LDQS" "M0_LDQS" + U2 23 +Net 38 "/FPGA Spartan6/M0_LDQS" "M0_LDQS" U1 L3 U2 16 Net 39 "/FPGA Spartan6/M0_UDM" "M0_UDM" - U2 47 U1 M3 -Net 40 "/FPGA Spartan6/USBA_VM" "USBA_VM" - U1 M18 + U2 47 +Net 40 "/USB/USBA_VM" "USBA_VM" U6 5 + U1 M18 Net 41 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" - U6 3 U1 N16 -Net 42 "/FPGA Spartan6/USBA_SPD" "USBA_SPD" + U6 3 +Net 42 "/USB/USBA_SPD" "USBA_SPD" U6 2 U1 R19 -Net 43 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" +Net 43 "/DDR Banks/M0_CLK#" "M0_CLK#" U1 H3 U2 44 -Net 44 "/FPGA Spartan6/M0_CLK" "M0_CLK" +Net 44 "/DDR Banks/M0_CLK" "M0_CLK" U1 H4 U2 46 Net 45 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" - U1 J19 U3 44 + U1 J19 Net 46 "/DDR Banks/M1_CLK" "M1_CLK" - U1 H20 U3 46 + U1 H20 Net 47 "/FPGA Spartan6/USBA_VP" "USBA_VP" U1 P17 U6 4 -Net 48 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" - U1 P18 +Net 48 "/USB/USBA_OE_N" "USBA_OE_N" U6 9 + U1 P18 Net 49 "" "" R14 2 C20 2 Net 50 "" "" R14 1 R13 2 - U3 49 - C20 1 C19 2 + C20 1 + U3 49 Net 51 "" "" R12 1 - C18 1 - C17 2 - U2 49 R11 2 + U2 49 + C17 2 + C18 1 Net 52 "+2.5V" "+2.5V" - C33 1 - U1 H9 - U1 V6 - U1 U18 - U1 N18 - U1 J18 + U1 M15 + U1 D16 + U1 L7 U1 L16 - U1 F4 - U1 R6 - R13 1 U6 1 - C22 1 - C23 1 - C25 1 - C24 1 - C26 1 - C34 1 + U1 W2 + U1 H15 + U1 K15 + U1 R2 + U1 L2 + U1 C2 + U1 G2 + U1 E19 + U1 J18 + U1 R21 + U1 N18 + U1 L21 + U1 U18 + U1 G21 + U1 F4 + U1 W21 + U1 C21 + U2 61 + U2 33 + U2 1 + U2 3 + U2 9 C29 1 C28 1 - U1 E19 + C33 1 + U1 G12 + U1 J5 + U1 N5 + U2 15 + U3 55 + U2 55 + U1 U5 + U1 F6 + U1 R10 + U3 9 + U1 F11 + U3 61 + R11 1 + C19 1 + C17 1 + U1 H9 + U3 3 + U3 1 + U1 R12 U1 L8 + U2 18 U1 N8 - U1 R21 - U1 L21 - U1 G21 - U1 C21 + U1 R6 + C24 1 + C25 1 + C23 1 + U1 V6 + C22 1 + R13 1 C21 1 - U1 W21 C27 1 C32 1 C30 1 C31 1 - U1 J5 - U2 33 - U3 18 - U3 33 - U2 61 - U3 15 - U1 L7 - U1 F11 - U1 R10 - U1 W2 - U1 R2 - U1 L2 - U1 G2 - U1 R12 - U1 C2 - U1 G12 - U1 H15 U1 U11 - U1 K15 - U3 61 - U3 9 - R11 1 - U2 55 - C19 1 - U2 15 - C17 1 - U3 1 - U3 3 - U2 18 - U3 55 - U1 F6 - U2 9 - U1 U5 - U1 N5 - U2 3 - U2 1 - U1 D16 - U1 M15 + U3 18 + U3 15 + C26 1 + C34 1 + U3 33 Net 53 "" "" R12 2 C18 2 Net 98 "3.3V" "3.3V" - J4 11 + U4 24 + R4 1 + R6 1 + R5 1 + J4 3 + J4 6 J4 9 - U6 14 + J4 11 + L2 1 C5 1 C3 1 C1 1 - R6 1 - L2 1 - R5 1 - U4 24 - C11 1 - J4 3 - J4 6 - C10 1 - U6 12 - U5 12 R1 2 - U4 7 - R4 1 - U5 19 + U6 12 + U6 14 R3 1 + U5 19 + U5 12 + C11 1 + U4 7 + C10 1 Net 99 "+3.3V" "+3.3V" - U1 B15 - U1 G14 - U1 E13 - U1 B4 - U5 37 U1 B19 U1 E17 - U1 E9 U1 B7 - U1 G10 + U1 B4 + U1 E13 + U1 G14 + U1 B15 U1 B11 -Net 118 "" "" - U1 AA19 - U1 T9 - U1 AA7 - U1 AA11 - U1 V8 - U1 AA3 - U1 AA15 + U5 37 + U1 G10 + U1 E9 +Net 110 "" "" U1 V16 - U1 V12 + U1 AA15 + U1 AA11 + U1 AA7 U1 T13 + U1 AA3 + U1 AA19 + U1 V8 + U1 T9 + U1 V12 U1 W5 -Net 119 "+1.2V" "+1.2V" - U1 M11 - U1 K11 +Net 111 "+1.2V" "+1.2V" + U1 J8 + U1 P13 + U1 N12 + U1 M13 + U1 K13 + U1 N14 + U1 L14 + U1 M9 U1 J12 U1 L12 - U1 N12 - U1 K13 - U1 M13 - U1 P13 - U1 M9 - U1 P11 - U1 K9 U1 J14 - U1 N10 U1 L10 - U1 L14 - U1 N14 U1 R14 - U1 P9 U1 J10 - U1 J8 -Net 334 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + U1 K11 + U1 M11 + U1 K9 + U1 P9 + U1 P11 + U1 N10 +Net 326 "/Ethernet Phy/ETH_LED0" "ETH_LED0" U4 26 R7 2 -Net 335 "" "" +Net 327 "" "" R3 2 - J4 1 U4 41 -Net 336 "" "" + J4 1 +Net 328 "" "" J4 7 - U4 33 R5 2 -Net 337 "" "" + U4 33 +Net 329 "" "" C12 1 + R9 1 J4 13 J4 14 - R9 1 -Net 338 "" "" +Net 330 "" "" J4 10 R7 1 -Net 339 "" "" - C4 1 +Net 331 "" "" L1 1 -Net 340 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" - C2 1 + C4 1 +Net 332 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" U4 13 -Net 341 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + C2 1 +Net 333 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + L3 2 C9 1 U4 47 - L3 2 -Net 344 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" +Net 336 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + L3 1 L1 2 U4 31 C6 1 - L3 1 -Net 345 "" "" - R2 1 +Net 337 "" "" U4 37 -Net 346 "" "" + R2 1 +Net 338 "" "" U4 32 - R6 2 J4 8 -Net 347 "" "" - U4 40 + R6 2 +Net 339 "" "" R4 2 J4 2 -Net 348 "" "" + U4 40 +Net 340 "" "" C9 2 C6 2 C4 2 -Net 349 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - L2 2 - C8 1 +Net 341 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" C7 1 + C8 1 + L2 2 U4 38 -Net 350 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - U4 27 +Net 342 "/Ethernet Phy/ETH_LED1" "ETH_LED1" R8 2 -Net 351 "" "" - R8 1 + U4 27 +Net 343 "" "" J4 12 -Net 357 "" "" - V2 1 + R8 1 +Net 349 "" "" V2 1 J5 2 U6 10 -Net 358 "" "" - L4 1 + V2 1 +Net 350 "" "" F1 1 -Net 359 "" "" - L5 1 + L4 1 +Net 351 "" "" J5 4 -Net 361 "" "" - J5 3 + L5 1 +Net 353 "" "" + V1 1 + V1 1 U6 11 - V1 1 - V1 1 -Net 362 "" "" + J5 3 +Net 354 "" "" J5 S1 - R10 1 J5 S2 - J5 S4 - C16 1 J5 S3 -Net 363 "" "" + J5 S4 + R10 1 + C16 1 +Net 355 "" "" J5 1 L4 2 -Net 364 "" "" - C15 1 - C14 1 +Net 356 "" "" C13 1 -Net 365 "/Non volatile memories/SD_DAT3" "SD_DAT3" - J1 2 + C14 1 + C15 1 +Net 357 "/Non volatile memories/SD_DAT3" "SD_DAT3" U1 C17 -Net 366 "/Non volatile memories/SD_DAT2" "SD_DAT2" + J1 2 +Net 358 "/Non volatile memories/SD_DAT2" "SD_DAT2" J1 1 U1 A17 -Net 367 "/FPGA Spartan6/SD_DAT1" "SD_DAT1" +Net 359 "/FPGA Spartan6/SD_DAT1" "SD_DAT1" U1 B18 J1 8 -Net 368 "/Non volatile memories/SD_DAT0" "SD_DAT0" - U1 A18 +Net 360 "/Non volatile memories/SD_DAT0" "SD_DAT0" J1 7 -Net 369 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" - U1 D7 + U1 A18 +Net 361 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" U4 20 -Net 370 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" - U1 A9 + U1 D7 +Net 362 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" U4 19 -Net 371 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" + U1 A9 +Net 363 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" U4 18 U1 C9 -Net 372 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" - U4 17 +Net 364 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" U1 C8 -Net 373 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" + U4 17 +Net 365 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" U4 3 U1 C6 -Net 374 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" +Net 366 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" U4 4 U1 B6 -Net 375 "/FPGA Spartan6/M1_BA1" "M1_BA1" +Net 367 "/DDR Banks/M1_BA1" "M1_BA1" U1 K17 U3 27 -Net 376 "/FPGA Spartan6/M1_BA0" "M1_BA0" - U3 26 +Net 368 "/FPGA Spartan6/M1_BA0" "M1_BA0" U1 J17 -Net 377 "/DDR Banks/M0_BA1" "M0_BA1" - U2 27 + U3 26 +Net 369 "/FPGA Spartan6/M0_BA1" "M0_BA1" U1 G1 -Net 378 "/FPGA Spartan6/M0_BA0" "M0_BA0" + U2 27 +Net 370 "/FPGA Spartan6/M0_BA0" "M0_BA0" U1 G3 U2 26 -Net 387 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" +Net 371 "/Non volatile memories/NF_D7" "NF_D7" + U5 44 + U1 A11 +Net 372 "/FPGA Spartan6/NF_D6" "NF_D6" + U1 D11 + U5 43 +Net 373 "/Non volatile memories/NF_D5" "NF_D5" + U1 C12 + U5 42 +Net 374 "/FPGA Spartan6/NF_D4" "NF_D4" + U5 41 + U1 B12 +Net 375 "/FPGA Spartan6/NF_D3" "NF_D3" + U1 A12 + U5 32 +Net 376 "/FPGA Spartan6/NF_D2" "NF_D2" + U1 C13 + U5 31 +Net 377 "/FPGA Spartan6/NF_D1" "NF_D1" + U1 A13 + U5 30 +Net 378 "/Non volatile memories/NF_D0" "NF_D0" + U5 29 + U1 D14 +Net 379 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" U1 A6 U4 5 -Net 388 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" - U4 6 +Net 380 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" U1 C7 -Net 389 "/DDR Banks/M1_A8" "M1_A8" + U4 6 +Net 381 "/DDR Banks/M1_A8" "M1_A8" U3 39 U1 C20 -Net 390 "/FPGA Spartan6/M1_A7" "M1_A7" +Net 382 "/FPGA Spartan6/M1_A7" "M1_A7" U1 E20 U3 38 -Net 391 "/FPGA Spartan6/M1_A6" "M1_A6" - U1 K19 +Net 383 "/FPGA Spartan6/M1_A6" "M1_A6" U3 37 -Net 392 "/FPGA Spartan6/M1_A5" "M1_A5" + U1 K19 +Net 384 "/DDR Banks/M1_A5" "M1_A5" U3 36 U1 K20 -Net 393 "/FPGA Spartan6/M1_A4" "M1_A4" - U3 35 +Net 385 "/FPGA Spartan6/M1_A4" "M1_A4" U1 F20 -Net 394 "/DDR Banks/M1_A3" "M1_A3" - U1 G20 + U3 35 +Net 386 "/FPGA Spartan6/M1_A3" "M1_A3" U3 32 -Net 395 "/FPGA Spartan6/M1_A2" "M1_A2" - U1 E22 + U1 G20 +Net 387 "/FPGA Spartan6/M1_A2" "M1_A2" U3 31 -Net 396 "/FPGA Spartan6/M1_A1" "M1_A1" + U1 E22 +Net 388 "/FPGA Spartan6/M1_A1" "M1_A1" U1 F22 U3 30 -Net 397 "/FPGA Spartan6/M1_A0" "M1_A0" - U3 29 +Net 389 "/FPGA Spartan6/M1_A0" "M1_A0" U1 F21 -Net 398 "/DDR Banks/M0_A12" "M0_A12" + U3 29 +Net 390 "/FPGA Spartan6/M0_A12" "M0_A12" U2 42 U1 D1 -Net 399 "/FPGA Spartan6/M0_A11" "M0_A11" +Net 391 "/DDR Banks/M0_A11" "M0_A11" U1 C1 U2 41 -Net 400 "/DDR Banks/M0_A10" "M0_A10" - U2 28 +Net 392 "/FPGA Spartan6/M0_A10" "M0_A10" U1 G4 -Net 401 "/DDR Banks/M1_DQ15" "M1_DQ15" + U2 28 +Net 393 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" U1 V22 U3 65 -Net 402 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" - U3 63 +Net 394 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" U1 V21 -Net 403 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" - U1 U22 + U3 63 +Net 395 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" U3 62 -Net 404 "/DDR Banks/M1_DQ12" "M1_DQ12" - U3 60 + U1 U22 +Net 396 "/DDR Banks/M1_DQ12" "M1_DQ12" U1 U20 -Net 405 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" - U1 R22 + U3 60 +Net 397 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" U3 59 -Net 406 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" - U1 R20 + U1 R22 +Net 398 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" U3 57 -Net 407 "/DDR Banks/M1_DQ9" "M1_DQ9" - U3 56 + U1 R20 +Net 399 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" U1 P22 -Net 408 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" - U3 54 + U3 56 +Net 400 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" U1 P21 -Net 409 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" + U3 54 +Net 401 "/DDR Banks/M1_DQ7" "M1_DQ7" U3 13 U1 K22 -Net 410 "/DDR Banks/M1_DQ6" "M1_DQ6" +Net 402 "/DDR Banks/M1_DQ6" "M1_DQ6" U1 K21 U3 11 -Net 411 "/DDR Banks/M1_DQ5" "M1_DQ5" - U3 10 +Net 403 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" U1 J22 -Net 412 "/DDR Banks/M1_DQ4" "M1_DQ4" + U3 10 +Net 404 "/DDR Banks/M1_DQ4" "M1_DQ4" U1 J20 U3 8 -Net 413 "/FPGA Spartan6/M1_DQ3" "M1_DQ3" - U3 7 +Net 405 "/DDR Banks/M1_DQ3" "M1_DQ3" U1 M22 -Net 414 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" - U3 5 + U3 7 +Net 406 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" U1 M21 -Net 415 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" + U3 5 +Net 407 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" U3 4 U1 N22 -Net 416 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" +Net 408 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" U3 2 U1 N20 -Net 417 "/FPGA Spartan6/M1_A12" "M1_A12" - U3 42 +Net 409 "/FPGA Spartan6/M1_A12" "M1_A12" U1 D22 -Net 418 "/FPGA Spartan6/M1_A11" "M1_A11" + U3 42 +Net 410 "/FPGA Spartan6/M1_A11" "M1_A11" U3 41 U1 F19 -Net 419 "/FPGA Spartan6/M1_A10" "M1_A10" - U3 28 +Net 411 "/DDR Banks/M1_A10" "M1_A10" U1 G19 -Net 420 "/DDR Banks/M1_A9" "M1_A9" - U3 40 + U3 28 +Net 412 "/FPGA Spartan6/M1_A9" "M1_A9" U1 C22 -Net 421 "/DDR Banks/M0_DQ7" "M0_DQ7" - U2 13 + U3 40 +Net 413 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" U1 K1 -Net 422 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" + U2 13 +Net 414 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" U1 K2 U2 11 -Net 423 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" - U2 10 +Net 415 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" U1 J1 -Net 424 "/DDR Banks/M0_DQ4" "M0_DQ4" + U2 10 +Net 416 "/DDR Banks/M0_DQ4" "M0_DQ4" U2 8 U1 J3 -Net 425 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" - U1 M1 +Net 417 "/DDR Banks/M0_DQ3" "M0_DQ3" U2 7 -Net 426 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" + U1 M1 +Net 418 "/DDR Banks/M0_DQ2" "M0_DQ2" U2 5 U1 M2 -Net 427 "/DDR Banks/M0_DQ1" "M0_DQ1" +Net 419 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" U1 N1 U2 4 -Net 428 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" +Net 420 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" U1 N3 U2 2 -Net 429 "/FPGA Spartan6/M0_A9" "M0_A9" +Net 421 "/FPGA Spartan6/M0_A9" "M0_A9" U1 E1 U2 40 -Net 430 "/FPGA Spartan6/M0_A8" "M0_A8" - U2 39 +Net 422 "/DDR Banks/M0_A8" "M0_A8" U1 E3 -Net 431 "/FPGA Spartan6/M0_A7" "M0_A7" - U1 H6 + U2 39 +Net 423 "/DDR Banks/M0_A7" "M0_A7" U2 38 -Net 432 "/DDR Banks/M0_A6" "M0_A6" - U2 37 + U1 H6 +Net 424 "/FPGA Spartan6/M0_A6" "M0_A6" U1 J4 -Net 433 "/FPGA Spartan6/M0_A5" "M0_A5" - U2 36 + U2 37 +Net 425 "/FPGA Spartan6/M0_A5" "M0_A5" U1 K3 -Net 434 "/FPGA Spartan6/M0_A4" "M0_A4" + U2 36 +Net 426 "/FPGA Spartan6/M0_A4" "M0_A4" U2 35 U1 F3 -Net 435 "/DDR Banks/M0_A3" "M0_A3" - U2 32 +Net 427 "/DDR Banks/M0_A3" "M0_A3" U1 K6 -Net 436 "/FPGA Spartan6/M0_A2" "M0_A2" + U2 32 +Net 428 "/FPGA Spartan6/M0_A2" "M0_A2" U2 31 U1 H5 -Net 437 "/FPGA Spartan6/M0_A1" "M0_A1" - U2 30 +Net 429 "/FPGA Spartan6/M0_A1" "M0_A1" U1 H1 -Net 438 "/FPGA Spartan6/M0_A0" "M0_A0" + U2 30 +Net 430 "/FPGA Spartan6/M0_A0" "M0_A0" U2 29 U1 H2 -Net 439 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" - U1 V1 +Net 431 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" U2 65 -Net 440 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" - U2 63 + U1 V1 +Net 432 "/DDR Banks/M0_DQ14" "M0_DQ14" U1 V2 -Net 441 "/DDR Banks/M0_DQ13" "M0_DQ13" + U2 63 +Net 433 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" U1 U1 U2 62 -Net 442 "/DDR Banks/M0_DQ12" "M0_DQ12" - U1 U3 +Net 434 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" U2 60 -Net 443 "/DDR Banks/M0_DQ11" "M0_DQ11" - U1 R1 + U1 U3 +Net 435 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" U2 59 -Net 444 "/DDR Banks/M0_DQ10" "M0_DQ10" + U1 R1 +Net 436 "/DDR Banks/M0_DQ10" "M0_DQ10" U2 57 U1 R3 -Net 445 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" - U2 56 +Net 437 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" U1 P1 -Net 446 "/DDR Banks/M0_DQ8" "M0_DQ8" - U1 P2 + U2 56 +Net 438 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" U2 54 + U1 P2 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index e1fcc2c..df247cb 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Thu 12 Aug 2010 12:07:08 PM COT +update=Thu 12 Aug 2010 09:10:48 PM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 221abff..e9a9bdc 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 05:12:17 PM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 09:08:15 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -47,7 +47,7 @@ EELAYER END $Descr A3 16535 11700 Sheet 1 6 Title "" -Date "12 aug 2010" +Date "13 aug 2010" Rev "" Comp "" Comment1 "" @@ -244,7 +244,7 @@ F49 "SD_CMD" B R 9300 3000 60 F50 "SD_DAT[0..3]" B R 9300 3100 60 F51 "ETH_CRS" I R 9300 6700 60 F52 "ETH_COL" I R 9300 6800 60 -F53 "ND_D[0..7]" B R 9300 4050 60 +F53 "NF_D[0..7]" B R 9300 4050 60 $EndSheet $Sheet S 10600 6250 1300 1800