From e1d2dfa457a3fac108b2c10a37dd59035d36bf9d Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Sun, 26 Dec 2010 19:16:00 -0500 Subject: [PATCH] new psu components in the pcb... placement pendent --- modules/Makefile | 1 + xue-rnc/ether.sch | 4 +- xue-rnc/expansion.sch | 4 +- xue-rnc/flash.sch | 36 +- xue-rnc/fpga1.sch | 96 +- xue-rnc/fpga2.sch | 16 +- xue-rnc/psu.sch | 261 +- xue-rnc/sdram.sch | 68 +- xue-rnc/usb.sch | 96 +- xue-rnc/xue-rnc.000 | 48788 ++++++++++++++++++++++++++++++++++++++++ xue-rnc/xue-rnc.brd | 15110 +++++++------ xue-rnc/xue-rnc.cmp | 240 +- xue-rnc/xue-rnc.net | 2497 +- xue-rnc/xue-rnc.pro | 8 +- xue-rnc/xue-rnc.pro~ | 155 + xue-rnc/xue-rnc.sch | 4 +- 16 files changed, 58982 insertions(+), 8402 deletions(-) create mode 100644 xue-rnc/xue-rnc.000 create mode 100644 xue-rnc/xue-rnc.pro~ diff --git a/modules/Makefile b/modules/Makefile index 05ec9ee..6bde4e7 100644 --- a/modules/Makefile +++ b/modules/Makefile @@ -10,6 +10,7 @@ MODULES= \ MLF16 \ MLF20m1 \ MLP6 \ + MINI-SO-8 \ SON008V5060 \ UDFN6 \ stdpass diff --git a/xue-rnc/ether.sch b/xue-rnc/ether.sch index cf6203e..82e7d5f 100644 --- a/xue-rnc/ether.sch +++ b/xue-rnc/ether.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 26 Dec 2010 05:23:16 PM COT +EESchema Schematic File Version 2 date Sun 26 Dec 2010 07:06:53 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,7 +58,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 11 9 Title "" -Date "26 dec 2010" +Date "27 dec 2010" Rev "" Comp "" Comment1 "" diff --git a/xue-rnc/expansion.sch b/xue-rnc/expansion.sch index 2cc1d0e..a0f3411 100644 --- a/xue-rnc/expansion.sch +++ b/xue-rnc/expansion.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 26 Dec 2010 05:23:16 PM COT +EESchema Schematic File Version 2 date Sun 26 Dec 2010 07:06:53 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,7 +58,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 2 9 Title "" -Date "26 dec 2010" +Date "27 dec 2010" Rev "" Comp "" Comment1 "" diff --git a/xue-rnc/flash.sch b/xue-rnc/flash.sch index 12344d0..1fa2fc3 100644 --- a/xue-rnc/flash.sch +++ b/xue-rnc/flash.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 26 Dec 2010 05:23:16 PM COT +EESchema Schematic File Version 2 date Sun 26 Dec 2010 07:06:53 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,7 +58,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 9 9 Title "" -Date "26 dec 2010" +Date "27 dec 2010" Rev "" Comp "" Comment1 "" @@ -251,19 +251,19 @@ F 1 "100nF" H 4000 5400 50 0000 L CNN -1 0 0 1 $EndComp $Comp -L GND #PWR027 +L GND #PWR045 U 1 1 4C65D6AB P 9350 3150 -F 0 "#PWR027" H 9350 3150 30 0001 C CNN +F 0 "#PWR045" H 9350 3150 30 0001 C CNN F 1 "GND" H 9350 3080 30 0001 C CNN 1 9350 3150 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR028 +L +3.3V #PWR046 U 1 1 4C65D69B P 9350 2650 -F 0 "#PWR028" H 9350 2610 30 0001 C CNN +F 0 "#PWR046" H 9350 2610 30 0001 C CNN F 1 "+3.3V" H 9350 2760 30 0000 C CNN 1 9350 2650 1 0 0 -1 @@ -327,10 +327,10 @@ SPI_DQ[0..3] Text HLabel 2450 1700 0 60 Input ~ 0 SPI_FLASH_CS# $Comp -L GND #PWR029 +L GND #PWR047 U 1 1 4C65ABE9 P 2650 2450 -F 0 "#PWR029" H 2650 2450 30 0001 C CNN +F 0 "#PWR047" H 2650 2450 30 0001 C CNN F 1 "GND" H 2650 2380 30 0001 C CNN 1 2650 2450 1 0 0 -1 @@ -363,19 +363,19 @@ Entry Wire Line Entry Wire Line 8150 3150 8250 3050 $Comp -L +3.3V #PWR030 +L +3.3V #PWR048 U 1 1 4C646C14 P 7950 2900 -F 0 "#PWR030" H 7950 2860 30 0001 C CNN +F 0 "#PWR048" H 7950 2860 30 0001 C CNN F 1 "+3.3V" H 7950 3010 30 0000 C CNN 1 7950 2900 1 0 0 -1 $EndComp $Comp -L GND #PWR031 +L GND #PWR049 U 1 1 4C646BEA P 7950 3000 -F 0 "#PWR031" H 7950 3000 30 0001 C CNN +F 0 "#PWR049" H 7950 3000 30 0001 C CNN F 1 "GND" H 7950 2930 30 0001 C CNN 1 7950 3000 1 0 0 -1 @@ -425,10 +425,10 @@ SD_DAT3 Text Label 4200 6100 0 30 ~ 0 SD_CMD $Comp -L GND #PWR032 +L GND #PWR050 U 1 1 4C61D875 P 3950 5800 -F 0 "#PWR032" H 3950 5800 30 0001 C CNN +F 0 "#PWR050" H 3950 5800 30 0001 C CNN F 1 "GND" H 3950 5730 30 0001 C CNN 1 3950 5800 1 0 0 -1 @@ -440,19 +440,19 @@ SD_DAT0 Text Label 4200 5850 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR033 +L GND #PWR051 U 1 1 4C438ADC P 5800 6200 -F 0 "#PWR033" H 5800 6200 30 0001 C CNN +F 0 "#PWR051" H 5800 6200 30 0001 C CNN F 1 "GND" H 5800 6130 30 0001 C CNN 1 5800 6200 1 0 0 -1 $EndComp $Comp -L GND #PWR034 +L GND #PWR052 U 1 1 4C438AD5 P 5350 6550 -F 0 "#PWR034" H 5350 6550 30 0001 C CNN +F 0 "#PWR052" H 5350 6550 30 0001 C CNN F 1 "GND" H 5350 6480 30 0001 C CNN 1 5350 6550 1 0 0 -1 diff --git a/xue-rnc/fpga1.sch b/xue-rnc/fpga1.sch index 7117dff..80b651a 100644 --- a/xue-rnc/fpga1.sch +++ b/xue-rnc/fpga1.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 26 Dec 2010 05:23:16 PM COT +EESchema Schematic File Version 2 date Sun 26 Dec 2010 07:06:53 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,7 +58,7 @@ EELAYER END $Descr A3 16535 11700 Sheet 3 9 Title "" -Date "26 dec 2010" +Date "27 dec 2010" Rev "" Comp "" Comment1 "" @@ -1266,10 +1266,10 @@ FPGA_BANK0_IO_38 Text Notes 7900 3650 0 40 ~ 0 M[1]=Low (master), High (slave) $Comp -L GND #PWR01 +L GND #PWR019 U 1 1 4CD361EC P 7900 3900 -F 0 "#PWR01" H 7900 3900 30 0001 C CNN +F 0 "#PWR019" H 7900 3900 30 0001 C CNN F 1 "GND" H 7900 3830 30 0001 C CNN 1 7900 3900 1 0 0 -1 @@ -1279,10 +1279,10 @@ M[0]=Low (parallel), High (serial) Text GLabel 8000 1200 1 30 BiDi ~ 0 VCCO2 $Comp -L GND #PWR02 +L GND #PWR020 U 1 1 4CD35A7F P 1450 2350 -F 0 "#PWR02" H 1450 2350 30 0001 C CNN +F 0 "#PWR020" H 1450 2350 30 0001 C CNN F 1 "GND" H 1450 2280 30 0001 C CNN 1 1450 2350 0 1 1 0 @@ -1291,19 +1291,19 @@ Text Notes 15200 7550 0 40 ~ 0 FPGA CLOCK NoConn ~ 13800 7200 $Comp -L GND #PWR03 +L GND #PWR021 U 1 1 4CD34DDD P 13750 7450 -F 0 "#PWR03" H 13750 7450 30 0001 C CNN +F 0 "#PWR021" H 13750 7450 30 0001 C CNN F 1 "GND" H 13750 7380 30 0001 C CNN 1 13750 7450 1 0 0 -1 $EndComp $Comp -L GND #PWR04 +L GND #PWR022 U 1 1 4CD34DC9 P 15050 6700 -F 0 "#PWR04" H 15050 6700 30 0001 C CNN +F 0 "#PWR022" H 15050 6700 30 0001 C CNN F 1 "GND" H 15050 6630 30 0001 C CNN 1 15050 6700 -1 0 0 1 @@ -1602,10 +1602,10 @@ FPGA_BANK0_IO_1 Text Label 9250 7050 0 60 ~ 0 FPGA_BANK0_IO_0 $Comp -L GND #PWR05 +L GND #PWR023 U 1 1 4CB241C7 P 4750 8950 -F 0 "#PWR05" H 4750 8950 30 0001 C CNN +F 0 "#PWR023" H 4750 8950 30 0001 C CNN F 1 "GND" H 4750 8880 30 0001 C CNN 1 4750 8950 1 0 0 -1 @@ -1947,19 +1947,19 @@ F 2 "0402" H 650 6550 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR06 +L +3.3V #PWR024 U 1 1 4C7168D5 P 650 6250 -F 0 "#PWR06" H 650 6210 30 0001 C CNN +F 0 "#PWR024" H 650 6210 30 0001 C CNN F 1 "+3.3V" H 650 6360 30 0000 C CNN 1 650 6250 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR07 +L +3.3V #PWR025 U 1 1 4C716889 P 8450 6600 -F 0 "#PWR07" H 8450 6560 30 0001 C CNN +F 0 "#PWR025" H 8450 6560 30 0001 C CNN F 1 "+3.3V" H 8450 6710 30 0000 C CNN 1 8450 6600 1 0 0 -1 @@ -1975,10 +1975,10 @@ F 2 "0402" H 8450 6900 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR08 +L GND #PWR026 U 1 1 4C716816 P 8050 7350 -F 0 "#PWR08" H 8050 7350 30 0001 C CNN +F 0 "#PWR026" H 8050 7350 30 0001 C CNN F 1 "GND" H 8050 7280 30 0001 C CNN 1 8050 7350 1 0 0 -1 @@ -2038,28 +2038,28 @@ $EndComp Text GLabel 12100 650 0 30 BiDi ~ 0 VCCO2 $Comp -L +3.3V #PWR09 +L +3.3V #PWR027 U 1 1 4C65CF66 P 1100 9500 -F 0 "#PWR09" H 1100 9460 30 0001 C CNN +F 0 "#PWR027" H 1100 9460 30 0001 C CNN F 1 "+3.3V" H 1100 9610 30 0000 C CNN 1 1100 9500 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR010 +L +2.5V #PWR028 U 1 1 4C65C84B P 3550 10450 -F 0 "#PWR010" H 3550 10400 20 0001 C CNN +F 0 "#PWR028" H 3550 10400 20 0001 C CNN F 1 "+2.5V" H 3550 10550 30 0000 C CNN 1 3550 10450 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR011 +L +2.5V #PWR029 U 1 1 4C65C837 P 1100 10400 -F 0 "#PWR011" H 1100 10350 20 0001 C CNN +F 0 "#PWR029" H 1100 10350 20 0001 C CNN F 1 "+2.5V" H 1100 10500 30 0000 C CNN 1 1100 10400 1 0 0 -1 @@ -2107,10 +2107,10 @@ F 2 "0402" H 2500 10700 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR012 +L GND #PWR030 U 1 1 4C656D9B P 1100 11000 -F 0 "#PWR012" H 1100 11000 30 0001 C CNN +F 0 "#PWR030" H 1100 11000 30 0001 C CNN F 1 "GND" H 1100 10930 30 0001 C CNN 1 1100 11000 1 0 0 -1 @@ -2178,10 +2178,10 @@ F 2 "0602" H 4950 9800 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR013 +L GND #PWR031 U 1 1 4C656D47 P 3550 10100 -F 0 "#PWR013" H 3550 10100 30 0001 C CNN +F 0 "#PWR031" H 3550 10100 30 0001 C CNN F 1 "GND" H 3550 10030 30 0001 C CNN 1 3550 10100 1 0 0 -1 @@ -2239,10 +2239,10 @@ F 2 "0402" H 4950 10750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR014 +L GND #PWR032 U 1 1 4C656CFD P 3550 11050 -F 0 "#PWR014" H 3550 11050 30 0001 C CNN +F 0 "#PWR032" H 3550 11050 30 0001 C CNN F 1 "GND" H 3550 10980 30 0001 C CNN 1 3550 11050 1 0 0 -1 @@ -2290,10 +2290,10 @@ F 2 "1210" H 3550 10750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR015 +L GND #PWR033 U 1 1 4C656CBC P 1100 10100 -F 0 "#PWR015" H 1100 10100 30 0001 C CNN +F 0 "#PWR033" H 1100 10100 30 0001 C CNN F 1 "GND" H 1100 10030 30 0001 C CNN 1 1100 10100 1 0 0 -1 @@ -2343,10 +2343,10 @@ $EndComp Text Notes 6050 10450 0 30 ~ 0 VCC_AUX Decoupling Capacitors (7) $Comp -L GND #PWR016 +L GND #PWR034 U 1 1 4C656C68 P 5950 11050 -F 0 "#PWR016" H 5950 11050 30 0001 C CNN +F 0 "#PWR034" H 5950 11050 30 0001 C CNN F 1 "GND" H 5950 10980 30 0001 C CNN 1 5950 11050 1 0 0 -1 @@ -2422,19 +2422,19 @@ F 2 "1210" H 5950 10750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR017 +L +2.5V #PWR035 U 1 1 4C656BBA P 5950 10450 -F 0 "#PWR017" H 5950 10400 20 0001 C CNN +F 0 "#PWR035" H 5950 10400 20 0001 C CNN F 1 "+2.5V" H 5950 10550 30 0000 C CNN 1 5950 10450 1 0 0 -1 $EndComp $Comp -L GND #PWR018 +L GND #PWR036 U 1 1 4C656BA8 P 5950 10050 -F 0 "#PWR018" H 5950 10050 30 0001 C CNN +F 0 "#PWR036" H 5950 10050 30 0001 C CNN F 1 "GND" H 5950 9980 30 0001 C CNN 1 5950 10050 1 0 0 -1 @@ -2472,10 +2472,10 @@ F 2 "0603" H 6300 9750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR019 +L +1.2V #PWR037 U 1 1 4C656AA1 P 5950 9450 -F 0 "#PWR019" H 5950 9590 20 0001 C CNN +F 0 "#PWR037" H 5950 9590 20 0001 C CNN F 1 "+1.2V" H 5950 9560 30 0000 C CNN 1 5950 9450 1 0 0 -1 @@ -2525,28 +2525,28 @@ NF_RE_N Text HLabel 5950 3350 2 60 BiDi ~ 0 NF_RNB $Comp -L +3.3V #PWR020 +L +3.3V #PWR038 U 1 1 4C61E5B3 P 3850 1800 -F 0 "#PWR020" H 3850 1760 30 0001 C CNN +F 0 "#PWR038" H 3850 1760 30 0001 C CNN F 1 "+3.3V" H 3850 1910 30 0000 C CNN 1 3850 1800 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR021 +L +1.2V #PWR039 U 1 1 4C61E58C P 4850 6150 -F 0 "#PWR021" H 4850 6290 20 0001 C CNN +F 0 "#PWR039" H 4850 6290 20 0001 C CNN F 1 "+1.2V" H 4850 6260 30 0000 C CNN 1 4850 6150 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR022 +L +2.5V #PWR040 U 1 1 4C61E577 P 3350 6150 -F 0 "#PWR022" H 3350 6100 20 0001 C CNN +F 0 "#PWR040" H 3350 6100 20 0001 C CNN F 1 "+2.5V" H 3350 6250 30 0000 C CNN 1 3350 6150 1 0 0 -1 @@ -2624,10 +2624,10 @@ ETH_MDC Text HLabel 2150 4450 0 60 BiDi ~ 0 ETH_INT $Comp -L GND #PWR023 +L GND #PWR041 U 1 1 4C439B7E P 4000 8000 -F 0 "#PWR023" H 4000 8000 30 0001 C CNN +F 0 "#PWR041" H 4000 8000 30 0001 C CNN F 1 "GND" H 4000 7930 30 0001 C CNN 1 4000 8000 -1 0 0 -1 diff --git a/xue-rnc/fpga2.sch b/xue-rnc/fpga2.sch index f339264..614e9e3 100644 --- a/xue-rnc/fpga2.sch +++ b/xue-rnc/fpga2.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 26 Dec 2010 05:23:16 PM COT +EESchema Schematic File Version 2 date Sun 26 Dec 2010 07:06:53 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,7 +58,7 @@ EELAYER END $Descr A3 16535 11700 Sheet 6 9 Title "" -Date "26 dec 2010" +Date "27 dec 2010" Rev "" Comp "" Comment1 "" @@ -1562,19 +1562,19 @@ F 1 "R_PACK4" H 3400 6600 40 0000 C CNN -1 0 0 1 $EndComp $Comp -L +2.5V #PWR024 +L +2.5V #PWR042 U 1 1 4C61E523 P 9200 6250 -F 0 "#PWR024" H 9200 6200 20 0001 C CNN +F 0 "#PWR042" H 9200 6200 20 0001 C CNN F 1 "+2.5V" H 9200 6350 30 0000 C CNN 1 9200 6250 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR025 +L +2.5V #PWR043 U 1 1 4C61E51F P 9800 850 -F 0 "#PWR025" H 9800 800 20 0001 C CNN +F 0 "#PWR043" H 9800 800 20 0001 C CNN F 1 "+2.5V" H 9800 950 30 0000 C CNN 1 9800 850 1 0 0 -1 @@ -1592,10 +1592,10 @@ M1_BA[0..1] Text HLabel 4700 9500 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR026 +L GND #PWR044 U 1 1 4C60C21D P 6250 5650 -F 0 "#PWR026" H 6250 5650 30 0001 C CNN +F 0 "#PWR044" H 6250 5650 30 0001 C CNN F 1 "GND" H 6250 5580 30 0001 C CNN 1 6250 5650 -1 0 0 -1 diff --git a/xue-rnc/psu.sch b/xue-rnc/psu.sch index f012686..cde1bbb 100644 --- a/xue-rnc/psu.sch +++ b/xue-rnc/psu.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 26 Dec 2010 05:23:16 PM COT +EESchema Schematic File Version 2 date Sun 26 Dec 2010 07:06:53 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,7 +58,7 @@ EELAYER END $Descr A3 16535 11700 Sheet 2 9 Title "" -Date "26 dec 2010" +Date "27 dec 2010" Rev "" Comp "" Comment1 "" @@ -68,16 +68,12 @@ Comment4 "" $EndDescr Connection ~ 4450 7150 Wire Wire Line - 4300 7150 4450 7150 -Wire Wire Line - 4450 7150 4800 7150 -Wire Wire Line - 4800 7150 5450 7150 + 4300 7150 5450 7150 Wire Wire Line 3600 7300 4300 7300 Connection ~ 3150 10150 Wire Wire Line - 3150 10150 3150 10300 + 3150 10300 3150 10150 Connection ~ 3450 9100 Wire Wire Line 3450 9100 3450 8700 @@ -98,47 +94,37 @@ Wire Wire Line 2750 10750 2750 10850 Connection ~ 3850 10150 Wire Wire Line - 4850 9100 4850 10150 + 4850 10150 4850 9100 Connection ~ 2750 10150 Wire Wire Line - 2750 10250 2750 10150 + 2750 10250 2750 10100 Wire Wire Line - 2750 10150 2750 10100 + 2500 10150 2500 10100 Wire Wire Line - 2500 10100 2500 10150 -Wire Wire Line - 2500 10150 2450 10150 -Wire Wire Line - 2450 10150 2400 10150 + 2500 10150 2400 10150 Wire Wire Line 2400 10150 2400 10100 Wire Wire Line - 850 9100 1050 9100 -Wire Wire Line - 1050 9100 1300 9100 + 850 9100 1300 9100 Connection ~ 3450 9400 Wire Wire Line - 3450 9400 3450 9300 + 3450 9300 3450 9400 Wire Wire Line 3450 9300 3350 9300 Wire Wire Line - 3950 9700 3950 9400 + 3950 9400 3950 9700 Wire Wire Line 5300 9650 5300 9500 Wire Wire Line - 5500 9450 5500 9500 + 5500 9500 5500 9450 Wire Wire Line - 5500 9500 5300 9500 -Wire Wire Line - 5300 9500 5100 9500 + 5500 9500 5100 9500 Wire Wire Line 5100 9500 5100 9450 Wire Wire Line - 5500 9250 5500 9200 + 5500 9200 5500 9250 Wire Wire Line - 5500 9200 5300 9200 -Wire Wire Line - 5300 9200 5100 9200 + 5500 9200 5100 9200 Wire Wire Line 5100 9200 5100 9250 Wire Wire Line @@ -148,13 +134,9 @@ Connection ~ 5300 9500 Wire Wire Line 5450 7150 5450 7100 Wire Wire Line - 5950 4300 5950 4350 + 5950 4350 5950 4300 Wire Wire Line - 5950 4350 5450 4350 -Wire Wire Line - 5450 4350 5000 4350 -Wire Wire Line - 5000 4350 4900 4350 + 4900 4350 5950 4350 Wire Wire Line 2100 6750 2100 7050 Wire Wire Line @@ -173,19 +155,15 @@ Connection ~ 4800 7150 Wire Wire Line 4800 7150 4800 7250 Wire Wire Line - 4600 7300 4600 7250 + 4600 7250 4600 7300 Wire Wire Line - 4600 7250 4800 7250 -Wire Wire Line - 4800 7250 5000 7250 + 4600 7250 5000 7250 Wire Wire Line 5000 7250 5000 7300 Wire Wire Line - 4600 7500 4600 7550 + 4600 7550 4600 7500 Wire Wire Line - 4600 7550 4800 7550 -Wire Wire Line - 4800 7550 5000 7550 + 4600 7550 5000 7550 Wire Wire Line 5000 7550 5000 7500 Wire Wire Line @@ -193,26 +171,20 @@ Wire Wire Line Wire Wire Line 5450 4900 5450 4750 Wire Wire Line - 4850 1950 5050 1950 -Wire Wire Line - 5050 1950 5250 1950 + 4850 1950 5250 1950 Connection ~ 5050 1550 Wire Wire Line 5050 1550 5050 1650 Wire Wire Line - 5650 4700 5650 4750 + 5650 4750 5650 4700 Wire Wire Line - 5650 4750 5450 4750 -Wire Wire Line - 5450 4750 5250 4750 + 5650 4750 5250 4750 Wire Wire Line 5250 4750 5250 4700 Wire Wire Line - 5650 4500 5650 4450 + 5650 4450 5650 4500 Wire Wire Line - 5650 4450 5450 4450 -Wire Wire Line - 5450 4450 5250 4450 + 5650 4450 5250 4450 Wire Wire Line 5250 4450 5250 4500 Wire Wire Line @@ -235,21 +207,13 @@ Connection ~ 2350 5050 Wire Wire Line 2350 5050 2350 4950 Wire Wire Line - 2550 4950 2550 5050 + 2550 5050 2550 4950 Wire Wire Line - 2550 5050 2450 5050 -Wire Wire Line - 2450 5050 2350 5050 -Wire Wire Line - 2350 5050 2250 5050 + 2550 5050 2250 5050 Wire Wire Line 2250 5050 2250 4950 Wire Wire Line - 3300 4350 3400 4350 -Wire Wire Line - 3400 4350 4200 4350 -Wire Wire Line - 4200 4350 4300 4350 + 3300 4350 4300 4350 Wire Wire Line 3300 3750 4200 3750 Connection ~ 3900 3650 @@ -258,29 +222,19 @@ Wire Wire Line Wire Wire Line 3350 3650 3300 3650 Wire Wire Line - 3900 3300 3900 3650 + 3900 3950 3900 3300 Wire Wire Line - 3900 3650 3900 3950 -Wire Wire Line - 3900 3950 3400 3950 -Wire Wire Line - 3400 3950 3300 3950 + 3300 3950 3900 3950 Wire Wire Line 4200 3750 4200 4050 Connection ~ 3400 3850 Wire Wire Line - 3300 3850 3400 3850 + 3400 3850 3300 3850 Connection ~ 3400 4350 Wire Wire Line - 3300 4550 3400 4550 + 3400 4550 3300 4550 Wire Wire Line - 3400 4550 3400 4450 -Wire Wire Line - 3400 4450 3400 4350 -Wire Wire Line - 3400 4350 3400 4250 -Wire Wire Line - 3400 4250 3400 4150 + 3400 4550 3400 4150 Wire Wire Line 3400 4150 3300 4150 Wire Wire Line @@ -336,11 +290,9 @@ Wire Notes Line Wire Notes Line 550 8250 550 6150 Wire Wire Line - 3550 1450 3650 1450 + 3650 1450 3550 1450 Wire Wire Line - 3650 1450 3650 1350 -Wire Wire Line - 3650 1350 3650 1100 + 3650 1100 3650 1450 Wire Wire Line 4050 1800 3700 1800 Connection ~ 3700 1800 @@ -357,11 +309,9 @@ Wire Wire Line Wire Wire Line 1700 1450 1700 1750 Wire Wire Line - 2050 1550 1950 1550 + 1950 1550 2050 1550 Wire Wire Line - 1950 1550 1950 1650 -Wire Wire Line - 1950 1650 1950 2000 + 1950 2000 1950 1550 Wire Wire Line 1050 1400 1050 1200 Wire Wire Line @@ -371,12 +321,10 @@ Wire Wire Line 3400 4450 3300 4450 Connection ~ 3400 4450 Wire Wire Line - 3300 4050 3400 4050 + 3400 4050 3300 4050 Connection ~ 3400 3950 Wire Wire Line - 3400 4050 3400 3950 -Wire Wire Line - 3400 3950 3400 3850 + 3400 3850 3400 4050 Wire Wire Line 4200 4250 4200 4350 Connection ~ 4200 4350 @@ -392,11 +340,9 @@ Wire Wire Line 2450 5050 2450 4950 Connection ~ 2450 5050 Wire Wire Line - 2800 4950 2800 5050 + 2800 5050 2800 4950 Wire Wire Line - 2800 5050 2850 5050 -Wire Wire Line - 2850 5050 3100 5050 + 3100 5050 2800 5050 Connection ~ 2850 5050 Wire Wire Line 2650 5650 2650 5600 @@ -417,43 +363,33 @@ Wire Wire Line 5050 2100 5050 1950 Connection ~ 5050 1650 Wire Wire Line - 4850 1700 4850 1650 + 4850 1650 4850 1700 Wire Wire Line - 5250 1700 5250 1650 + 5250 1650 5250 1700 Wire Wire Line 4850 1950 4850 1900 Wire Wire Line 5250 1950 5250 1900 Wire Wire Line - 5250 1650 5050 1650 -Wire Wire Line - 5050 1650 4850 1650 + 4850 1650 5250 1650 Wire Wire Line 3600 7150 3700 7150 Wire Wire Line - 2150 7200 2100 7200 + 2100 7200 2150 7200 Wire Wire Line - 2100 7200 2100 7300 -Wire Wire Line - 2100 7300 2100 7600 + 2100 7600 2100 7200 Wire Wire Line 2150 7300 2100 7300 Connection ~ 2100 7300 Wire Wire Line - 4650 1550 4750 1550 -Wire Wire Line - 4750 1550 5050 1550 -Wire Wire Line - 5050 1550 5750 1550 + 4650 1550 5750 1550 Wire Wire Line 5750 1550 5750 1450 Wire Wire Line 1050 9200 1050 9100 Connection ~ 1050 9100 Wire Wire Line - 2000 9100 1950 9100 -Wire Wire Line - 1950 9100 1900 9100 + 2000 9100 1900 9100 Wire Wire Line 2450 10150 2450 10250 Connection ~ 2450 10150 @@ -466,26 +402,12 @@ Wire Wire Line Wire Wire Line 3350 9700 3400 9700 Wire Wire Line - 3350 9400 3450 9400 -Wire Wire Line - 3450 9400 3950 9400 -Wire Wire Line - 3950 9400 4100 9400 -Wire Wire Line - 4100 9400 4150 9400 + 3350 9400 4150 9400 Connection ~ 3950 9400 Wire Wire Line 4100 9650 4100 9850 Wire Wire Line - 3350 9100 3450 9100 -Wire Wire Line - 3450 9100 4700 9100 -Wire Wire Line - 4700 9100 4850 9100 -Wire Wire Line - 4850 9100 5300 9100 -Wire Wire Line - 5300 9100 5850 9100 + 3350 9100 5850 9100 Wire Wire Line 5850 9100 5850 9050 Connection ~ 5300 9100 @@ -497,13 +419,9 @@ Connection ~ 1950 9100 Wire Wire Line 3450 8700 2850 8700 Wire Wire Line - 4850 10150 3850 10150 + 3750 10150 4850 10150 Wire Wire Line - 3850 10150 3750 10150 -Wire Wire Line - 3250 10150 3150 10150 -Wire Wire Line - 3150 10150 2750 10150 + 3250 10150 2750 10150 Wire Wire Line 4300 7300 4450 7150 Text Notes 4350 7150 0 40 Italic 0 @@ -516,25 +434,26 @@ U 1 1 4D160B09 P 2650 8700 F 0 "D1" H 2650 8800 40 0000 C CNN F 1 "MBRS140T3" H 2650 8600 40 0000 C CNN +F 2 "0805" H 2650 8700 60 0001 C CNN 1 2650 8700 1 0 0 -1 $EndComp Text Notes 5100 11100 0 40 Italic 0 http://www.national.com/ds/LM/LM2621.pdf $Comp -L GND #PWR64 +L GND #PWR01 U 1 1 4D1409D1 P 5300 9650 -F 0 "#PWR64" H 5300 9650 30 0001 C CNN +F 0 "#PWR01" H 5300 9650 30 0001 C CNN F 1 "GND" H 5300 9580 30 0001 C CNN 1 5300 9650 1 0 0 -1 $EndComp $Comp -L GND #PWR61 +L GND #PWR02 U 1 1 4D14097D P 4100 9850 -F 0 "#PWR61" H 4100 9850 30 0001 C CNN +F 0 "#PWR02" H 4100 9850 30 0001 C CNN F 1 "GND" H 4100 9780 30 0001 C CNN 1 4100 9850 1 0 0 -1 @@ -550,28 +469,28 @@ F 2 "0402" H 4100 9550 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR57 +L GND #PWR03 U 1 1 4D14083D P 2750 10850 -F 0 "#PWR57" H 2750 10850 30 0001 C CNN +F 0 "#PWR03" H 2750 10850 30 0001 C CNN F 1 "GND" H 2750 10780 30 0001 C CNN 1 2750 10850 1 0 0 -1 $EndComp $Comp -L GND #PWR55 +L GND #PWR04 U 1 1 4D140715 P 2450 10250 -F 0 "#PWR55" H 2450 10250 30 0001 C CNN +F 0 "#PWR04" H 2450 10250 30 0001 C CNN F 1 "GND" H 2450 10180 30 0001 C CNN 1 2450 10250 1 0 0 -1 $EndComp $Comp -L GND #PWR49 +L GND #PWR05 U 1 1 4D140708 P 1050 9650 -F 0 "#PWR49" H 1050 9650 30 0001 C CNN +F 0 "#PWR05" H 1050 9650 30 0001 C CNN F 1 "GND" H 1050 9580 30 0001 C CNN 1 1050 9650 1 0 0 -1 @@ -667,10 +586,10 @@ F 2 "1210" H 1600 9100 60 0001 C CNN 0 1 1 0 $EndComp $Comp -L GND #PWR54 +L GND #PWR06 U 1 1 4D140270 P 2100 7600 -F 0 "#PWR54" H 2100 7600 30 0001 C CNN +F 0 "#PWR06" H 2100 7600 30 0001 C CNN F 1 "GND" H 2100 7530 30 0001 C CNN 1 2100 7600 1 0 0 -1 @@ -686,10 +605,10 @@ F 2 "0805" H 4000 7150 60 0001 C CNN 0 1 1 0 $EndComp $Comp -L GND #PWR51 +L GND #PWR07 U 1 1 4D14016E P 1300 7550 -F 0 "#PWR51" H 1300 7550 30 0001 C CNN +F 0 "#PWR07" H 1300 7550 30 0001 C CNN F 1 "GND" H 1300 7480 30 0001 C CNN 1 1300 7550 1 0 0 -1 @@ -725,10 +644,10 @@ F 2 "0402" H 5000 7400 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR62 +L GND #PWR08 U 1 1 4D140161 P 4800 7700 -F 0 "#PWR62" H 4800 7700 30 0001 C CNN +F 0 "#PWR08" H 4800 7700 30 0001 C CNN F 1 "GND" H 4800 7630 30 0001 C CNN 1 4800 7700 1 0 0 -1 @@ -736,10 +655,10 @@ $EndComp Text Notes 4550 8200 0 40 ~ 0 http://www.onsemi.com/pub_link/Collateral/NCP1529-D.PDF $Comp -L GND #PWR65 +L GND #PWR09 U 1 1 4D13FF19 P 5450 4900 -F 0 "#PWR65" H 5450 4900 30 0001 C CNN +F 0 "#PWR09" H 5450 4900 30 0001 C CNN F 1 "GND" H 5450 4830 30 0001 C CNN 1 5450 4900 1 0 0 -1 @@ -765,10 +684,10 @@ F 2 "0402" H 5250 1800 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR63 +L GND #PWR010 U 1 1 4D13FF2E P 5050 2100 -F 0 "#PWR63" H 5050 2100 30 0001 C CNN +F 0 "#PWR010" H 5050 2100 30 0001 C CNN F 1 "GND" H 5050 2030 30 0001 C CNN 1 5050 2100 1 0 0 -1 @@ -784,28 +703,28 @@ F 2 "0402" H 5650 4600 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR59 +L GND #PWR011 U 1 1 4D13FEDF P 3050 3400 -F 0 "#PWR59" H 3050 3400 30 0001 C CNN +F 0 "#PWR011" H 3050 3400 30 0001 C CNN F 1 "GND" H 3050 3330 30 0001 C CNN 1 3050 3400 1 0 0 -1 $EndComp $Comp -L GND #PWR56 +L GND #PWR012 U 1 1 4D13FECF P 2650 5900 -F 0 "#PWR56" H 2650 5900 30 0001 C CNN +F 0 "#PWR012" H 2650 5900 30 0001 C CNN F 1 "GND" H 2650 5830 30 0001 C CNN 1 2650 5900 1 0 0 -1 $EndComp $Comp -L GND #PWR58 +L GND #PWR013 U 1 1 4D13FEC8 P 2850 5650 -F 0 "#PWR58" H 2850 5650 30 0001 C CNN +F 0 "#PWR013" H 2850 5650 30 0001 C CNN F 1 "GND" H 2850 5580 30 0001 C CNN 1 2850 5650 1 0 0 -1 @@ -821,10 +740,10 @@ F 2 "1210" H 1100 4200 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR50 +L GND #PWR014 U 1 1 4D13FEB5 P 1100 4600 -F 0 "#PWR50" H 1100 4600 30 0001 C CNN +F 0 "#PWR014" H 1100 4600 30 0001 C CNN F 1 "GND" H 1100 4530 30 0001 C CNN 1 1100 4600 1 0 0 -1 @@ -941,37 +860,37 @@ Design in progress!!! Text Notes 1900 1100 0 40 ~ 0 ???\n $Comp -L GND #PWR53 +L GND #PWR015 U 1 1 4D13F926 P 1950 2000 -F 0 "#PWR53" H 1950 2000 30 0001 C CNN +F 0 "#PWR015" H 1950 2000 30 0001 C CNN F 1 "GND" H 1950 1930 30 0001 C CNN 1 1950 2000 1 0 0 -1 $EndComp $Comp -L GND #PWR52 +L GND #PWR016 U 1 1 4D13F8E2 P 1700 2550 -F 0 "#PWR52" H 1700 2550 30 0001 C CNN +F 0 "#PWR016" H 1700 2550 30 0001 C CNN F 1 "GND" H 1700 2480 30 0001 C CNN 1 1700 2550 1 0 0 -1 $EndComp $Comp -L GND #PWR48 +L GND #PWR017 U 1 1 4D13F81E P 1050 1900 -F 0 "#PWR48" H 1050 1900 30 0001 C CNN +F 0 "#PWR017" H 1050 1900 30 0001 C CNN F 1 "GND" H 1050 1830 30 0001 C CNN 1 1050 1900 1 0 0 -1 $EndComp $Comp -L GND #PWR60 +L GND #PWR018 U 1 1 4D13F818 P 3700 2400 -F 0 "#PWR60" H 3700 2400 30 0001 C CNN +F 0 "#PWR018" H 3700 2400 30 0001 C CNN F 1 "GND" H 3700 2330 30 0001 C CNN 1 3700 2400 1 0 0 -1 diff --git a/xue-rnc/sdram.sch b/xue-rnc/sdram.sch index e9c5b20..51793e4 100644 --- a/xue-rnc/sdram.sch +++ b/xue-rnc/sdram.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 26 Dec 2010 05:23:16 PM COT +EESchema Schematic File Version 2 date Sun 26 Dec 2010 07:06:53 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,7 +58,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 9 9 Title "" -Date "26 dec 2010" +Date "27 dec 2010" Rev "" Comp "" Comment1 "" @@ -542,19 +542,19 @@ Entry Wire Line Entry Wire Line 10100 4400 10200 4500 $Comp -L GND #PWR035 +L GND #PWR053 U 1 1 4C699C4D P 9950 2100 -F 0 "#PWR035" H 9950 2100 30 0001 C CNN +F 0 "#PWR053" H 9950 2100 30 0001 C CNN F 1 "GND" H 9950 2030 30 0001 C CNN 1 9950 2100 1 0 0 -1 $EndComp $Comp -L GND #PWR036 +L GND #PWR054 U 1 1 4C699C48 P 4550 2150 -F 0 "#PWR036" H 4550 2150 30 0001 C CNN +F 0 "#PWR054" H 4550 2150 30 0001 C CNN F 1 "GND" H 4550 2080 30 0001 C CNN 1 4550 2150 1 0 0 -1 @@ -612,37 +612,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR037 +L GND #PWR055 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR037" H 6900 6200 30 0001 C CNN +F 0 "#PWR055" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR038 +L +2.5V #PWR056 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR038" H 6900 5750 20 0001 C CNN +F 0 "#PWR056" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR039 +L +2.5V #PWR057 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR039" H 1700 5750 20 0001 C CNN +F 0 "#PWR057" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR040 +L GND #PWR058 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR040" H 1700 6200 30 0001 C CNN +F 0 "#PWR058" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -658,19 +658,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR041 +L +2.5V #PWR059 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR041" H 3050 1700 20 0001 C CNN +F 0 "#PWR059" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR042 +L +2.5V #PWR060 U 1 1 4C61CFC6 P 8400 1700 -F 0 "#PWR042" H 8400 1650 20 0001 C CNN +F 0 "#PWR060" H 8400 1650 20 0001 C CNN F 1 "+2.5V" H 8400 1800 30 0000 C CNN 1 8400 1700 1 0 0 -1 @@ -736,37 +736,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR043 +L +2.5V #PWR061 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR043" H 8300 5700 20 0001 C CNN +F 0 "#PWR061" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR044 +L GND #PWR062 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR044" H 8300 6350 30 0001 C CNN +F 0 "#PWR062" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR045 +L GND #PWR063 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR045" H 3050 6350 30 0001 C CNN +F 0 "#PWR063" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR046 +L +2.5V #PWR064 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR046" H 3050 5700 20 0001 C CNN +F 0 "#PWR064" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -852,19 +852,19 @@ F 2 "0402" H 9950 1750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR047 +L +2.5V #PWR065 U 1 1 4C61CE2F P 9950 800 -F 0 "#PWR047" H 9950 750 20 0001 C CNN +F 0 "#PWR065" H 9950 750 20 0001 C CNN F 1 "+2.5V" H 9950 900 30 0000 C CNN 1 9950 800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR048 +L +2.5V #PWR066 U 1 1 4C61CDF1 P 4550 850 -F 0 "#PWR048" H 4550 800 20 0001 C CNN +F 0 "#PWR066" H 4550 800 20 0001 C CNN F 1 "+2.5V" H 4550 950 30 0000 C CNN 1 4550 850 1 0 0 -1 @@ -947,10 +947,10 @@ $EndComp Text HLabel 5000 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR049 +L GND #PWR067 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR049" H 3000 5200 30 0001 C CNN +F 0 "#PWR067" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1226,10 +1226,10 @@ Entry Wire Line Entry Wire Line 10100 3600 10200 3700 $Comp -L GND #PWR050 +L GND #PWR068 U 1 1 4C437C3F P 8350 5150 -F 0 "#PWR050" H 8350 5150 30 0001 C CNN +F 0 "#PWR068" H 8350 5150 30 0001 C CNN F 1 "GND" H 8350 5080 30 0001 C CNN 1 8350 5150 1 0 0 -1 diff --git a/xue-rnc/usb.sch b/xue-rnc/usb.sch index 35c5f89..068219e 100644 --- a/xue-rnc/usb.sch +++ b/xue-rnc/usb.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 26 Dec 2010 05:23:16 PM COT +EESchema Schematic File Version 2 date Sun 26 Dec 2010 07:06:53 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,7 +58,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 8 9 Title "" -Date "26 dec 2010" +Date "27 dec 2010" Rev "" Comp "" Comment1 "" @@ -378,10 +378,10 @@ F 1 "15k" V 3975 6100 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR051 +L +3.3V #PWR069 U 1 1 4C7D365E P 3975 5750 -F 0 "#PWR051" H 3975 5710 30 0001 C CNN +F 0 "#PWR069" H 3975 5710 30 0001 C CNN F 1 "+3.3V" H 3975 5860 30 0000 C CNN 1 3975 5750 1 0 0 -1 @@ -393,10 +393,10 @@ USBA_D- Text Label 4125 6550 0 40 ~ 0 USBD_D- $Comp -L GND #PWR052 +L GND #PWR070 U 1 1 4C7D3584 P 1750 7150 -F 0 "#PWR052" H 1750 7150 30 0001 C CNN +F 0 "#PWR070" H 1750 7150 30 0001 C CNN F 1 "GND" H 1750 7080 30 0001 C CNN 1 1750 7150 1 0 0 -1 @@ -421,10 +421,10 @@ F 1 "24" V 2400 6550 50 0000 C CNN 0 1 1 0 $EndComp $Comp -L GND #PWR053 +L GND #PWR071 U 1 1 4C7D353A P 1850 3450 -F 0 "#PWR053" H 1850 3450 30 0001 C CNN +F 0 "#PWR071" H 1850 3450 30 0001 C CNN F 1 "GND" H 1850 3380 30 0001 C CNN 1 1850 3450 1 0 0 -1 @@ -454,10 +454,10 @@ USB_CASE_DEV Text Label 5850 2950 0 40 ~ 0 USB_CASE_HOST $Comp -L +3.3V #PWR054 +L +3.3V #PWR072 U 1 1 4C7D32BA P 4350 2050 -F 0 "#PWR054" H 4350 2010 30 0001 C CNN +F 0 "#PWR072" H 4350 2010 30 0001 C CNN F 1 "+3.3V" H 4350 2160 30 0000 C CNN 1 4350 2050 1 0 0 -1 @@ -525,91 +525,91 @@ F 2 "MLF16" H 1700 2750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR055 +L +3.3V #PWR073 U 1 1 4C695F50 P 2700 4600 -F 0 "#PWR055" H 2700 4560 30 0001 C CNN +F 0 "#PWR073" H 2700 4560 30 0001 C CNN F 1 "+3.3V" H 2700 4710 30 0000 C CNN 1 2700 4600 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR056 +L +3.3V #PWR074 U 1 1 4C695F4B P 2100 6100 -F 0 "#PWR056" H 2100 6060 30 0001 C CNN +F 0 "#PWR074" H 2100 6060 30 0001 C CNN F 1 "+3.3V" H 2100 6210 30 0000 C CNN 1 2100 6100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR057 +L +3.3V #PWR075 U 1 1 4C695F43 P 2650 1100 -F 0 "#PWR057" H 2650 1060 30 0001 C CNN +F 0 "#PWR075" H 2650 1060 30 0001 C CNN F 1 "+3.3V" H 2650 1210 30 0000 C CNN 1 2650 1100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR058 +L +3.3V #PWR076 U 1 1 4C695F3B P 2200 2400 -F 0 "#PWR058" H 2200 2360 30 0001 C CNN +F 0 "#PWR076" H 2200 2360 30 0001 C CNN F 1 "+3.3V" H 2200 2510 30 0000 C CNN 1 2200 2400 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR059 +L +2.5V #PWR077 U 1 1 4C695DCD P 3200 4550 -F 0 "#PWR059" H 3200 4500 20 0001 C CNN +F 0 "#PWR077" H 3200 4500 20 0001 C CNN F 1 "+2.5V" H 3200 4650 30 0000 C CNN 1 3200 4550 1 0 0 -1 $EndComp $Comp -L GND #PWR060 +L GND #PWR078 U 1 1 4C695F0A P 3200 5550 -F 0 "#PWR060" H 3200 5550 30 0001 C CNN +F 0 "#PWR078" H 3200 5550 30 0001 C CNN F 1 "GND" H 3200 5480 30 0001 C CNN 1 3200 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR061 +L GND #PWR079 U 1 1 4C695F09 P 2650 5550 -F 0 "#PWR061" H 2650 5550 30 0001 C CNN +F 0 "#PWR079" H 2650 5550 30 0001 C CNN F 1 "GND" H 2650 5480 30 0001 C CNN 1 2650 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR062 +L GND #PWR080 U 1 1 4C695DFE P 3150 1850 -F 0 "#PWR062" H 3150 1850 30 0001 C CNN +F 0 "#PWR080" H 3150 1850 30 0001 C CNN F 1 "GND" H 3150 1780 30 0001 C CNN 1 3150 1850 1 0 0 -1 $EndComp $Comp -L GND #PWR063 +L GND #PWR081 U 1 1 4C695DF8 P 2600 1850 -F 0 "#PWR063" H 2600 1850 30 0001 C CNN +F 0 "#PWR081" H 2600 1850 30 0001 C CNN F 1 "GND" H 2600 1780 30 0001 C CNN 1 2600 1850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR064 +L +2.5V #PWR082 U 1 1 4C695DA7 P 3150 1100 -F 0 "#PWR064" H 3150 1050 20 0001 C CNN +F 0 "#PWR082" H 3150 1050 20 0001 C CNN F 1 "+2.5V" H 3150 1200 30 0000 C CNN 1 3150 1100 1 0 0 -1 @@ -694,28 +694,28 @@ USBD_VP Text HLabel 1200 6750 0 40 BiDi ~ 0 USBD_VM $Comp -L GND #PWR065 +L GND #PWR083 U 1 1 4C6552B5 P 5500 7400 -F 0 "#PWR065" H 5500 7400 30 0001 C CNN +F 0 "#PWR083" H 5500 7400 30 0001 C CNN F 1 "GND" H 5500 7330 30 0001 C CNN 1 5500 7400 1 0 0 -1 $EndComp $Comp -L GND #PWR066 +L GND #PWR084 U 1 1 4C6552B4 P 3150 7500 -F 0 "#PWR066" H 3150 7500 30 0001 C CNN +F 0 "#PWR084" H 3150 7500 30 0001 C CNN F 1 "GND" H 3150 7430 30 0001 C CNN 1 3150 7500 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR067 +L +2.5V #PWR085 U 1 1 4C6552B2 P 1150 6150 -F 0 "#PWR067" H 1150 6100 20 0001 C CNN +F 0 "#PWR085" H 1150 6100 20 0001 C CNN F 1 "+2.5V" H 1150 6250 30 0000 C CNN 1 1150 6150 1 0 0 -1 @@ -731,28 +731,28 @@ F 2 "0603" H 4650 7000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR068 +L GND #PWR086 U 1 1 4C6552AE P 4650 7350 -F 0 "#PWR068" H 4650 7350 30 0001 C CNN +F 0 "#PWR086" H 4650 7350 30 0001 C CNN F 1 "GND" H 4650 7280 30 0001 C CNN 1 4650 7350 1 0 0 -1 $EndComp $Comp -L GND #PWR069 +L GND #PWR087 U 1 1 4C63F2B5 P 4900 3700 -F 0 "#PWR069" H 4900 3700 30 0001 C CNN +F 0 "#PWR087" H 4900 3700 30 0001 C CNN F 1 "GND" H 4900 3630 30 0001 C CNN 1 4900 3700 1 0 0 -1 $EndComp $Comp -L +5V #PWR070 +L +5V #PWR088 U 1 1 4C63F295 P 4700 1350 -F 0 "#PWR070" H 4700 1440 20 0001 C CNN +F 0 "#PWR088" H 4700 1440 20 0001 C CNN F 1 "+5V" H 4700 1440 30 0000 C CNN 1 4700 1350 1 0 0 -1 @@ -778,28 +778,28 @@ F 2 "0603" H 4900 3350 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR071 +L +2.5V #PWR089 U 1 1 4C63EC16 P 1250 2450 -F 0 "#PWR071" H 1250 2400 20 0001 C CNN +F 0 "#PWR089" H 1250 2400 20 0001 C CNN F 1 "+2.5V" H 1250 2550 30 0000 C CNN 1 1250 2450 1 0 0 -1 $EndComp $Comp -L GND #PWR072 +L GND #PWR090 U 1 1 4C63EA1B P 3100 3800 -F 0 "#PWR072" H 3100 3800 30 0001 C CNN +F 0 "#PWR090" H 3100 3800 30 0001 C CNN F 1 "GND" H 3100 3730 30 0001 C CNN 1 3100 3800 1 0 0 -1 $EndComp $Comp -L GND #PWR073 +L GND #PWR091 U 1 1 4C63E9FA P 5950 3750 -F 0 "#PWR073" H 5950 3750 30 0001 C CNN +F 0 "#PWR091" H 5950 3750 30 0001 C CNN F 1 "GND" H 5950 3680 30 0001 C CNN 1 5950 3750 1 0 0 -1 diff --git a/xue-rnc/xue-rnc.000 b/xue-rnc/xue-rnc.000 new file mode 100644 index 0000000..5de0e8e --- /dev/null +++ b/xue-rnc/xue-rnc.000 @@ -0,0 +1,48788 @@ +PCBNEW-BOARD Version 1 date Thu 23 Dec 2010 05:39:51 PM COT + +# Created by Pcbnew(2010-10-01 BZR 2513)-testing + +$GENERAL +LayerCount 6 +Ly 1FFF801F +EnabledLayers 13FF801F +Links 737 +NoConn 57 +Di 45633 12844 74358 60460 +Ndraw 6 +Ntrack 4940 +Nzone 0 +BoardThickness 630 +Nmodule 172 +Nnets 308 +$EndGENERAL + +$SHEETDESCR +Sheet A4 11700 8267 +Title "" +Date "23 dec 2010" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndSHEETDESCR + +$SETUP +InternalUnit 0.000100 INCH +ZoneGridSize 250 +Layers 6 +Layer[0] Back signal +Layer[1] GND power +Layer[2] Inner3 signal +Layer[3] Inner4 signal +Layer[4] VDD power +Layer[15] Front signal +TrackWidth 39 +TrackWidthList 59 +TrackWidthList 79 +TrackWidthList 118 +TrackWidthList 157 +TrackWidthList 236 +TrackWidthList 315 +TrackWidthList 394 +TrackClearence 39 +ZoneClearence 59 +TrackMinWidth 39 +DrawSegmWidth 150 +EdgeSegmWidth 150 +ViaSize 157 +ViaDrill 79 +ViaMinSize 157 +ViaMinDrill 79 +ViaSizeList 157 79 +ViaSizeList 236 157 +MicroViaSize 197 +MicroViaDrill 79 +MicroViasAllowed 0 +MicroViaMinSize 157 +MicroViaMinDrill 59 +TextPcbWidth 120 +TextPcbSize 394 591 +EdgeModWidth 59 +TextModSize 600 600 +TextModWidth 120 +PadSize 196 393 +PadDrill 0 +Pad2MaskClearance 100 +AuxiliaryAxisOrg 0 0 +$EndSETUP + +$EQUIPOT +Na 0 "" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 1 "+1.2V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 2 "+1.8V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 3 "+2.5V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 4 "+3.3V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 5 "+5V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 6 "/ether/ETH_A1.8V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 7 "/ether/ETH_A3.3V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 8 "/ether/ETH_CRS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 9 "/ether/ETH_INT" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 10 "/ether/ETH_LED0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 11 "/ether/ETH_LED1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 12 "/ether/ETH_MDIO" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 13 "/ether/ETH_PLL1.8V" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 14 "/ether/ETH_RXD0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 15 "/ether/ETH_RXDV" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 16 "/ether/ETH_RXER" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 17 "/ether/ETH_TXER" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 18 "/ether/MAG_RX+" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 19 "/ether/MAG_RX-" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 20 "/ether/MAG_SHIELD" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 21 "/ether/MAG_TX+" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 22 "/ether/MAG_TX-" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 23 "/expansion/FPGA_BANK0_IO_1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 24 "/expansion/FPGA_BANK0_IO_10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 25 "/expansion/FPGA_BANK0_IO_12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 26 "/expansion/FPGA_BANK0_IO_14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 27 "/expansion/FPGA_BANK0_IO_15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 28 "/expansion/FPGA_BANK0_IO_17" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 29 "/expansion/FPGA_BANK0_IO_21" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 30 "/expansion/FPGA_BANK0_IO_24" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 31 "/expansion/FPGA_BANK0_IO_27" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 32 "/expansion/FPGA_BANK0_IO_29" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 33 "/expansion/FPGA_BANK0_IO_3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 34 "/expansion/FPGA_BANK0_IO_30" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 35 "/expansion/FPGA_BANK0_IO_32" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 36 "/expansion/FPGA_BANK0_IO_34" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 37 "/expansion/FPGA_BANK0_IO_36" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 38 "/expansion/FPGA_BANK0_IO_38" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 39 "/expansion/FPGA_BANK0_IO_39" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 40 "/expansion/FPGA_BANK0_IO_43" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 41 "/expansion/FPGA_BANK0_IO_45" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 42 "/expansion/FPGA_BANK0_IO_46" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 43 "/expansion/FPGA_BANK0_IO_47" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 44 "/expansion/FPGA_BANK0_IO_49" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 45 "/expansion/FPGA_BANK0_IO_5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 46 "/expansion/FPGA_BANK0_IO_53" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 47 "/expansion/FPGA_BANK0_IO_54" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 48 "/expansion/FPGA_BANK0_IO_57" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 49 "/expansion/FPGA_BANK0_IO_60" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 50 "/expansion/FPGA_BANK0_IO_63" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 51 "/expansion/FPGA_BANK0_IO_8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 52 "/expansion/FPGA_BANK0_IO_9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 53 "/flash/NF_CLE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 54 "/flash/NF_D2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 55 "/flash/NF_D4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 56 "/flash/NF_D5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 57 "/flash/NF_RE_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 58 "/flash/NF_WE_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 59 "/flash/SD_CMD" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 60 "/flash/SD_DAT1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 61 "/flash/SD_DAT2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 62 "/flash/SD_DAT3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 63 "/fpga1/ETH_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 64 "/fpga1/ETH_COL" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 65 "/fpga1/ETH_MDC" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 66 "/fpga1/ETH_RESET_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 67 "/fpga1/ETH_RXC" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 68 "/fpga1/ETH_RXD1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 69 "/fpga1/ETH_RXD2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 70 "/fpga1/ETH_RXD3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 71 "/fpga1/ETH_TXC" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 72 "/fpga1/ETH_TXD0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 73 "/fpga1/ETH_TXD1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 74 "/fpga1/ETH_TXD2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 75 "/fpga1/ETH_TXD3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 76 "/fpga1/ETH_TXEN" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 77 "/fpga1/FPGA_BANK0_IO_11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 78 "/fpga1/FPGA_BANK0_IO_18" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 79 "/fpga1/FPGA_BANK0_IO_2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 80 "/fpga1/FPGA_BANK0_IO_20" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 81 "/fpga1/FPGA_BANK0_IO_22" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 82 "/fpga1/FPGA_BANK0_IO_25" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 83 "/fpga1/FPGA_BANK0_IO_28" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 84 "/fpga1/FPGA_BANK0_IO_33" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 85 "/fpga1/FPGA_BANK0_IO_40" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 86 "/fpga1/FPGA_BANK0_IO_44" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 87 "/fpga1/FPGA_BANK0_IO_48" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 88 "/fpga1/FPGA_BANK0_IO_50" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 89 "/fpga1/FPGA_BANK0_IO_51" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 90 "/fpga1/FPGA_BANK0_IO_52" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 91 "/fpga1/FPGA_BANK0_IO_56" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 92 "/fpga1/FPGA_BANK0_IO_58" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 93 "/fpga1/FPGA_BANK0_IO_6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 94 "/fpga1/FPGA_BANK0_IO_62" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 95 "/fpga1/FPGA_BANK0_IO_7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 96 "/fpga1/NF_ALE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 97 "/fpga1/NF_CS1_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 98 "/fpga1/NF_D0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 99 "/fpga1/NF_D1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 100 "/fpga1/NF_D3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 101 "/fpga1/NF_D6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 102 "/fpga1/NF_D7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 103 "/fpga1/NF_RNB" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 104 "/fpga1/PROG_CCLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 105 "/fpga1/PROG_CSO" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 106 "/fpga1/PROG_MISO0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 107 "/fpga1/PROG_MISO1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 108 "/fpga1/PROG_MISO2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 109 "/fpga1/PROG_MISO3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 110 "/fpga1/SD_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 111 "/fpga1/SD_DAT0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 112 "/fpga2/M0_A1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 113 "/fpga2/M0_A10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 114 "/fpga2/M0_A11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 115 "/fpga2/M0_A12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 116 "/fpga2/M0_A2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 117 "/fpga2/M0_A3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 118 "/fpga2/M0_A5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 119 "/fpga2/M0_A6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 120 "/fpga2/M0_A7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 121 "/fpga2/M0_A8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 122 "/fpga2/M0_A9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 123 "/fpga2/M0_BA1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 124 "/fpga2/M0_CKE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 125 "/fpga2/M0_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 126 "/fpga2/M0_DQ0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 127 "/fpga2/M0_DQ10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 128 "/fpga2/M0_DQ11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 129 "/fpga2/M0_DQ12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 130 "/fpga2/M0_DQ14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 131 "/fpga2/M0_DQ2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 132 "/fpga2/M0_DQ3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 133 "/fpga2/M0_DQ9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 134 "/fpga2/M0_LDQS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 135 "/fpga2/M0_RAS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 136 "/fpga2/M0_UDM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 137 "/fpga2/M0_UDQS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 138 "/fpga2/M1_A0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 139 "/fpga2/M1_A1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 140 "/fpga2/M1_A2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 141 "/fpga2/M1_A3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 142 "/fpga2/M1_A4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 143 "/fpga2/M1_A5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 144 "/fpga2/M1_BA0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 145 "/fpga2/M1_BA1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 146 "/fpga2/M1_CAS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 147 "/fpga2/M1_CKE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 148 "/fpga2/M1_DQ10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 149 "/fpga2/M1_DQ12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 150 "/fpga2/M1_DQ13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 151 "/fpga2/M1_DQ3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 152 "/fpga2/M1_DQ4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 153 "/fpga2/M1_DQ5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 154 "/fpga2/M1_DQ6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 155 "/fpga2/M1_DQ7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 156 "/fpga2/M1_DQ8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 157 "/fpga2/M1_LDQS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 158 "/fpga2/M1_RAS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 159 "/fpga2/M1_UDM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 160 "/fpga2/M1_UDQS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 161 "/fpga2/M1_WE#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 162 "/fpga2/R_M0_A0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 163 "/fpga2/R_M0_A1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 164 "/fpga2/R_M0_A10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 165 "/fpga2/R_M0_A11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 166 "/fpga2/R_M0_A12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 167 "/fpga2/R_M0_A2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 168 "/fpga2/R_M0_A3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 169 "/fpga2/R_M0_A4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 170 "/fpga2/R_M0_A5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 171 "/fpga2/R_M0_A6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 172 "/fpga2/R_M0_A7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 173 "/fpga2/R_M0_A8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 174 "/fpga2/R_M0_A9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 175 "/fpga2/R_M0_BA0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 176 "/fpga2/R_M0_BA1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 177 "/fpga2/R_M0_CAS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 178 "/fpga2/R_M0_CKE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 179 "/fpga2/R_M0_DQ0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 180 "/fpga2/R_M0_DQ1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 181 "/fpga2/R_M0_DQ10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 182 "/fpga2/R_M0_DQ11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 183 "/fpga2/R_M0_DQ12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 184 "/fpga2/R_M0_DQ13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 185 "/fpga2/R_M0_DQ14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 186 "/fpga2/R_M0_DQ15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 187 "/fpga2/R_M0_DQ2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 188 "/fpga2/R_M0_DQ3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 189 "/fpga2/R_M0_DQ4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 190 "/fpga2/R_M0_DQ5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 191 "/fpga2/R_M0_DQ6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 192 "/fpga2/R_M0_DQ7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 193 "/fpga2/R_M0_DQ8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 194 "/fpga2/R_M0_DQ9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 195 "/fpga2/R_M0_LDM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 196 "/fpga2/R_M0_LDQS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 197 "/fpga2/R_M0_RAS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 198 "/fpga2/R_M0_UDM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 199 "/fpga2/R_M0_UDQS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 200 "/fpga2/R_M0_WE#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 201 "/fpga2/R_M1_A0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 202 "/fpga2/R_M1_A1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 203 "/fpga2/R_M1_A10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 204 "/fpga2/R_M1_A11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 205 "/fpga2/R_M1_A12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 206 "/fpga2/R_M1_A2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 207 "/fpga2/R_M1_A3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 208 "/fpga2/R_M1_A4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 209 "/fpga2/R_M1_A5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 210 "/fpga2/R_M1_A6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 211 "/fpga2/R_M1_A7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 212 "/fpga2/R_M1_A8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 213 "/fpga2/R_M1_A9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 214 "/fpga2/R_M1_BA0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 215 "/fpga2/R_M1_BA1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 216 "/fpga2/R_M1_CAS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 217 "/fpga2/R_M1_CKE" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 218 "/fpga2/R_M1_CS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 219 "/fpga2/R_M1_DQ0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 220 "/fpga2/R_M1_DQ1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 221 "/fpga2/R_M1_DQ10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 222 "/fpga2/R_M1_DQ11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 223 "/fpga2/R_M1_DQ12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 224 "/fpga2/R_M1_DQ13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 225 "/fpga2/R_M1_DQ14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 226 "/fpga2/R_M1_DQ15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 227 "/fpga2/R_M1_DQ2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 228 "/fpga2/R_M1_DQ3" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 229 "/fpga2/R_M1_DQ4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 230 "/fpga2/R_M1_DQ5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 231 "/fpga2/R_M1_DQ6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 232 "/fpga2/R_M1_DQ7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 233 "/fpga2/R_M1_DQ8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 234 "/fpga2/R_M1_DQ9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 235 "/fpga2/R_M1_LDM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 236 "/fpga2/R_M1_LDQS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 237 "/fpga2/R_M1_RAS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 238 "/fpga2/R_M1_UDM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 239 "/fpga2/R_M1_UDQS" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 240 "/fpga2/R_M1_WE#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 241 "/fpga2/USBA_RCV" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 242 "/fpga2/USBA_VM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 243 "/fpga2/USBA_VP" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 244 "/fpga2/USBD_RCV" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 245 "/sdram/M0_A0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 246 "/sdram/M0_A4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 247 "/sdram/M0_BA0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 248 "/sdram/M0_CAS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 249 "/sdram/M0_CLK#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 250 "/sdram/M0_DQ1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 251 "/sdram/M0_DQ13" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 252 "/sdram/M0_DQ15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 253 "/sdram/M0_DQ4" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 254 "/sdram/M0_DQ5" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 255 "/sdram/M0_DQ6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 256 "/sdram/M0_DQ7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 257 "/sdram/M0_DQ8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 258 "/sdram/M0_LDM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 259 "/sdram/M0_VREF" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 260 "/sdram/M0_WE#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 261 "/sdram/M1_A10" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 262 "/sdram/M1_A11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 263 "/sdram/M1_A12" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 264 "/sdram/M1_A6" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 265 "/sdram/M1_A7" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 266 "/sdram/M1_A8" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 267 "/sdram/M1_A9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 268 "/sdram/M1_CLK" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 269 "/sdram/M1_CLK#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 270 "/sdram/M1_CS#" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 271 "/sdram/M1_DQ0" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 272 "/sdram/M1_DQ1" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 273 "/sdram/M1_DQ11" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 274 "/sdram/M1_DQ14" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 275 "/sdram/M1_DQ15" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 276 "/sdram/M1_DQ2" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 277 "/sdram/M1_DQ9" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 278 "/sdram/M1_LDM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 279 "/sdram/M1_VREF" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 280 "/usb/USBA_D+" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 281 "/usb/USBA_D-" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 282 "/usb/USBA_OE_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 283 "/usb/USBA_SPD" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 284 "/usb/USBD_D+" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 285 "/usb/USBD_D-" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 286 "/usb/USBD_OE_N" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 287 "/usb/USBD_SPD" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 288 "/usb/USBD_VM" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 289 "/usb/USBD_VP" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 290 "/usb/USB_CASE_DEV" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 291 "/usb/USB_CASE_HOST" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 292 "GND" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 293 "N-000120" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 294 "N-000121" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 295 "N-000133" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 296 "N-000142" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 297 "N-000143" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 298 "N-000144" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 299 "N-000145" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 300 "N-000146" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 301 "N-000147" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 302 "N-000149" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 303 "N-000150" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 304 "N-000178" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 305 "N-000356" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 306 "N-000359" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 307 "VCCO2" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 39 +TrackWidth 39 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +AddNet "" +AddNet "+1.8V" +AddNet "/ether/ETH_A1.8V" +AddNet "/ether/ETH_A3.3V" +AddNet "/ether/ETH_CRS" +AddNet "/ether/ETH_INT" +AddNet "/ether/ETH_LED0" +AddNet "/ether/ETH_LED1" +AddNet "/ether/ETH_MDIO" +AddNet "/ether/ETH_PLL1.8V" +AddNet "/ether/ETH_RXD0" +AddNet "/ether/ETH_RXDV" +AddNet "/ether/ETH_RXER" +AddNet "/ether/ETH_TXER" +AddNet "/ether/MAG_RX+" +AddNet "/ether/MAG_RX-" +AddNet "/ether/MAG_SHIELD" +AddNet "/ether/MAG_TX+" +AddNet "/ether/MAG_TX-" +AddNet "/expansion/FPGA_BANK0_IO_1" +AddNet "/expansion/FPGA_BANK0_IO_10" +AddNet "/expansion/FPGA_BANK0_IO_12" +AddNet "/expansion/FPGA_BANK0_IO_14" +AddNet "/expansion/FPGA_BANK0_IO_15" +AddNet "/expansion/FPGA_BANK0_IO_17" +AddNet "/expansion/FPGA_BANK0_IO_21" +AddNet "/expansion/FPGA_BANK0_IO_24" +AddNet "/expansion/FPGA_BANK0_IO_27" +AddNet "/expansion/FPGA_BANK0_IO_29" +AddNet "/expansion/FPGA_BANK0_IO_3" +AddNet "/expansion/FPGA_BANK0_IO_30" +AddNet "/expansion/FPGA_BANK0_IO_32" +AddNet "/expansion/FPGA_BANK0_IO_34" +AddNet "/expansion/FPGA_BANK0_IO_36" +AddNet "/expansion/FPGA_BANK0_IO_38" +AddNet "/expansion/FPGA_BANK0_IO_39" +AddNet "/expansion/FPGA_BANK0_IO_43" +AddNet "/expansion/FPGA_BANK0_IO_45" +AddNet "/expansion/FPGA_BANK0_IO_46" +AddNet "/expansion/FPGA_BANK0_IO_47" +AddNet "/expansion/FPGA_BANK0_IO_49" +AddNet "/expansion/FPGA_BANK0_IO_5" +AddNet "/expansion/FPGA_BANK0_IO_53" +AddNet "/expansion/FPGA_BANK0_IO_54" +AddNet "/expansion/FPGA_BANK0_IO_57" +AddNet "/expansion/FPGA_BANK0_IO_60" +AddNet "/expansion/FPGA_BANK0_IO_63" +AddNet "/expansion/FPGA_BANK0_IO_8" +AddNet "/expansion/FPGA_BANK0_IO_9" +AddNet "/flash/NF_CLE" +AddNet "/flash/NF_D2" +AddNet "/flash/NF_D4" +AddNet "/flash/NF_D5" +AddNet "/flash/NF_RE_N" +AddNet "/flash/NF_WE_N" +AddNet "/flash/SD_CMD" +AddNet "/flash/SD_DAT1" +AddNet "/flash/SD_DAT2" +AddNet "/flash/SD_DAT3" +AddNet "/fpga1/ETH_CLK" +AddNet "/fpga1/ETH_COL" +AddNet "/fpga1/ETH_MDC" +AddNet "/fpga1/ETH_RESET_N" +AddNet "/fpga1/ETH_RXC" +AddNet "/fpga1/ETH_RXD1" +AddNet "/fpga1/ETH_RXD2" +AddNet "/fpga1/ETH_RXD3" +AddNet "/fpga1/ETH_TXC" +AddNet "/fpga1/ETH_TXD0" +AddNet "/fpga1/ETH_TXD1" +AddNet "/fpga1/ETH_TXD2" +AddNet "/fpga1/ETH_TXD3" +AddNet "/fpga1/ETH_TXEN" +AddNet "/fpga1/FPGA_BANK0_IO_11" +AddNet "/fpga1/FPGA_BANK0_IO_18" +AddNet "/fpga1/FPGA_BANK0_IO_2" +AddNet "/fpga1/FPGA_BANK0_IO_20" +AddNet "/fpga1/FPGA_BANK0_IO_22" +AddNet "/fpga1/FPGA_BANK0_IO_25" +AddNet "/fpga1/FPGA_BANK0_IO_28" +AddNet "/fpga1/FPGA_BANK0_IO_33" +AddNet "/fpga1/FPGA_BANK0_IO_40" +AddNet "/fpga1/FPGA_BANK0_IO_44" +AddNet "/fpga1/FPGA_BANK0_IO_48" +AddNet "/fpga1/FPGA_BANK0_IO_50" +AddNet "/fpga1/FPGA_BANK0_IO_51" +AddNet "/fpga1/FPGA_BANK0_IO_52" +AddNet "/fpga1/FPGA_BANK0_IO_56" +AddNet "/fpga1/FPGA_BANK0_IO_58" +AddNet "/fpga1/FPGA_BANK0_IO_6" +AddNet "/fpga1/FPGA_BANK0_IO_62" +AddNet "/fpga1/FPGA_BANK0_IO_7" +AddNet "/fpga1/NF_ALE" +AddNet "/fpga1/NF_CS1_N" +AddNet "/fpga1/NF_D0" +AddNet "/fpga1/NF_D1" +AddNet "/fpga1/NF_D3" +AddNet "/fpga1/NF_D6" +AddNet "/fpga1/NF_D7" +AddNet "/fpga1/NF_RNB" +AddNet "/fpga1/PROG_CCLK" +AddNet "/fpga1/PROG_CSO" +AddNet "/fpga1/PROG_MISO0" +AddNet "/fpga1/PROG_MISO1" +AddNet "/fpga1/PROG_MISO2" +AddNet "/fpga1/PROG_MISO3" +AddNet "/fpga1/SD_CLK" +AddNet "/fpga1/SD_DAT0" +AddNet "/fpga2/M0_A1" +AddNet "/fpga2/M0_A10" +AddNet "/fpga2/M0_A11" +AddNet "/fpga2/M0_A12" +AddNet "/fpga2/M0_A2" +AddNet "/fpga2/M0_A3" +AddNet "/fpga2/M0_A5" +AddNet "/fpga2/M0_A6" +AddNet "/fpga2/M0_A7" +AddNet "/fpga2/M0_A8" +AddNet "/fpga2/M0_A9" +AddNet "/fpga2/M0_BA1" +AddNet "/fpga2/M0_CKE" +AddNet "/fpga2/M0_CLK" +AddNet "/fpga2/M0_DQ0" +AddNet "/fpga2/M0_DQ10" +AddNet "/fpga2/M0_DQ11" +AddNet "/fpga2/M0_DQ12" +AddNet "/fpga2/M0_DQ14" +AddNet "/fpga2/M0_DQ2" +AddNet "/fpga2/M0_DQ3" +AddNet "/fpga2/M0_DQ9" +AddNet "/fpga2/M0_LDQS" +AddNet "/fpga2/M0_RAS#" +AddNet "/fpga2/M0_UDM" +AddNet "/fpga2/M0_UDQS" +AddNet "/fpga2/M1_A0" +AddNet "/fpga2/M1_A1" +AddNet "/fpga2/M1_A2" +AddNet "/fpga2/M1_A3" +AddNet "/fpga2/M1_A4" +AddNet "/fpga2/M1_A5" +AddNet "/fpga2/M1_BA0" +AddNet "/fpga2/M1_BA1" +AddNet "/fpga2/M1_CAS#" +AddNet "/fpga2/M1_CKE" +AddNet "/fpga2/M1_DQ10" +AddNet "/fpga2/M1_DQ12" +AddNet "/fpga2/M1_DQ13" +AddNet "/fpga2/M1_DQ3" +AddNet "/fpga2/M1_DQ4" +AddNet "/fpga2/M1_DQ5" +AddNet "/fpga2/M1_DQ6" +AddNet "/fpga2/M1_DQ7" +AddNet "/fpga2/M1_DQ8" +AddNet "/fpga2/M1_LDQS" +AddNet "/fpga2/M1_RAS#" +AddNet "/fpga2/M1_UDM" +AddNet "/fpga2/M1_UDQS" +AddNet "/fpga2/M1_WE#" +AddNet "/fpga2/R_M0_A0" +AddNet "/fpga2/R_M0_A1" +AddNet "/fpga2/R_M0_A10" +AddNet "/fpga2/R_M0_A11" +AddNet "/fpga2/R_M0_A12" +AddNet "/fpga2/R_M0_A2" +AddNet "/fpga2/R_M0_A3" +AddNet "/fpga2/R_M0_A4" +AddNet "/fpga2/R_M0_A5" +AddNet "/fpga2/R_M0_A6" +AddNet "/fpga2/R_M0_A7" +AddNet "/fpga2/R_M0_A8" +AddNet "/fpga2/R_M0_A9" +AddNet "/fpga2/R_M0_BA0" +AddNet "/fpga2/R_M0_BA1" +AddNet "/fpga2/R_M0_CAS#" +AddNet "/fpga2/R_M0_CKE" +AddNet "/fpga2/R_M0_DQ0" +AddNet "/fpga2/R_M0_DQ1" +AddNet "/fpga2/R_M0_DQ10" +AddNet "/fpga2/R_M0_DQ11" +AddNet "/fpga2/R_M0_DQ12" +AddNet "/fpga2/R_M0_DQ13" +AddNet "/fpga2/R_M0_DQ14" +AddNet "/fpga2/R_M0_DQ15" +AddNet "/fpga2/R_M0_DQ2" +AddNet "/fpga2/R_M0_DQ3" +AddNet "/fpga2/R_M0_DQ4" +AddNet "/fpga2/R_M0_DQ5" +AddNet "/fpga2/R_M0_DQ6" +AddNet "/fpga2/R_M0_DQ7" +AddNet "/fpga2/R_M0_DQ8" +AddNet "/fpga2/R_M0_DQ9" +AddNet "/fpga2/R_M0_LDM" +AddNet "/fpga2/R_M0_LDQS" +AddNet "/fpga2/R_M0_RAS#" +AddNet "/fpga2/R_M0_UDM" +AddNet "/fpga2/R_M0_UDQS" +AddNet "/fpga2/R_M0_WE#" +AddNet "/fpga2/R_M1_A0" +AddNet "/fpga2/R_M1_A1" +AddNet "/fpga2/R_M1_A10" +AddNet "/fpga2/R_M1_A11" +AddNet "/fpga2/R_M1_A12" +AddNet "/fpga2/R_M1_A2" +AddNet "/fpga2/R_M1_A3" +AddNet "/fpga2/R_M1_A4" +AddNet "/fpga2/R_M1_A5" +AddNet "/fpga2/R_M1_A6" +AddNet "/fpga2/R_M1_A7" +AddNet "/fpga2/R_M1_A8" +AddNet "/fpga2/R_M1_A9" +AddNet "/fpga2/R_M1_BA0" +AddNet "/fpga2/R_M1_BA1" +AddNet "/fpga2/R_M1_CAS#" +AddNet "/fpga2/R_M1_CKE" +AddNet "/fpga2/R_M1_CS#" +AddNet "/fpga2/R_M1_DQ0" +AddNet "/fpga2/R_M1_DQ1" +AddNet "/fpga2/R_M1_DQ10" +AddNet "/fpga2/R_M1_DQ11" +AddNet "/fpga2/R_M1_DQ12" +AddNet "/fpga2/R_M1_DQ13" +AddNet "/fpga2/R_M1_DQ14" +AddNet "/fpga2/R_M1_DQ15" +AddNet "/fpga2/R_M1_DQ2" +AddNet "/fpga2/R_M1_DQ3" +AddNet "/fpga2/R_M1_DQ4" +AddNet "/fpga2/R_M1_DQ5" +AddNet "/fpga2/R_M1_DQ6" +AddNet "/fpga2/R_M1_DQ7" +AddNet "/fpga2/R_M1_DQ8" +AddNet "/fpga2/R_M1_DQ9" +AddNet "/fpga2/R_M1_LDM" +AddNet "/fpga2/R_M1_LDQS" +AddNet "/fpga2/R_M1_RAS#" +AddNet "/fpga2/R_M1_UDM" +AddNet "/fpga2/R_M1_UDQS" +AddNet "/fpga2/R_M1_WE#" +AddNet "/fpga2/USBA_RCV" +AddNet "/fpga2/USBA_VM" +AddNet "/fpga2/USBA_VP" +AddNet "/fpga2/USBD_RCV" +AddNet "/sdram/M0_A0" +AddNet "/sdram/M0_A4" +AddNet "/sdram/M0_BA0" +AddNet "/sdram/M0_CAS#" +AddNet "/sdram/M0_CLK#" +AddNet "/sdram/M0_DQ1" +AddNet "/sdram/M0_DQ13" +AddNet "/sdram/M0_DQ15" +AddNet "/sdram/M0_DQ4" +AddNet "/sdram/M0_DQ5" +AddNet "/sdram/M0_DQ6" +AddNet "/sdram/M0_DQ7" +AddNet "/sdram/M0_DQ8" +AddNet "/sdram/M0_LDM" +AddNet "/sdram/M0_VREF" +AddNet "/sdram/M0_WE#" +AddNet "/sdram/M1_A10" +AddNet "/sdram/M1_A11" +AddNet "/sdram/M1_A12" +AddNet "/sdram/M1_A6" +AddNet "/sdram/M1_A7" +AddNet "/sdram/M1_A8" +AddNet "/sdram/M1_A9" +AddNet "/sdram/M1_CLK" +AddNet "/sdram/M1_CLK#" +AddNet "/sdram/M1_CS#" +AddNet "/sdram/M1_DQ0" +AddNet "/sdram/M1_DQ1" +AddNet "/sdram/M1_DQ11" +AddNet "/sdram/M1_DQ14" +AddNet "/sdram/M1_DQ15" +AddNet "/sdram/M1_DQ2" +AddNet "/sdram/M1_DQ9" +AddNet "/sdram/M1_LDM" +AddNet "/sdram/M1_VREF" +AddNet "/usb/USBA_D+" +AddNet "/usb/USBA_D-" +AddNet "/usb/USBA_OE_N" +AddNet "/usb/USBA_SPD" +AddNet "/usb/USBD_D+" +AddNet "/usb/USBD_D-" +AddNet "/usb/USBD_OE_N" +AddNet "/usb/USBD_SPD" +AddNet "/usb/USBD_VM" +AddNet "/usb/USBD_VP" +AddNet "/usb/USB_CASE_DEV" +AddNet "/usb/USB_CASE_HOST" +AddNet "N-000120" +AddNet "N-000121" +AddNet "N-000133" +AddNet "N-000142" +AddNet "N-000143" +AddNet "N-000144" +AddNet "N-000145" +AddNet "N-000146" +AddNet "N-000147" +AddNet "N-000149" +AddNet "N-000150" +AddNet "N-000178" +AddNet "N-000356" +AddNet "N-000359" +AddNet "VCCO2" +$EndNCLASS +$NCLASS +Name "ADDRESS/DDR" +Desc "" +Clearance 59 +TrackWidth 39 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +$EndNCLASS +$NCLASS +Name "CLK#CLK/DDR" +Desc "" +Clearance 39 +TrackWidth 39 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +$EndNCLASS +$NCLASS +Name "DATA/DDR" +Desc "" +Clearance 79 +TrackWidth 39 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +$EndNCLASS +$NCLASS +Name "ETH" +Desc "" +Clearance 98 +TrackWidth 79 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +$EndNCLASS +$NCLASS +Name "POWER" +Desc "" +Clearance 59 +TrackWidth 118 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +AddNet "+1.2V" +AddNet "+2.5V" +AddNet "+3.3V" +AddNet "+5V" +AddNet "GND" +$EndNCLASS +$NCLASS +Name "SDIO" +Desc "" +Clearance 59 +TrackWidth 59 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +$EndNCLASS +$NCLASS +Name "USB" +Desc "" +Clearance 59 +TrackWidth 59 +ViaDia 157 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 +$EndNCLASS +$MODULE FGG484bga-p10 +Po 56269 34378 0 15 4CF99E1A 4C6A0A06 ~~ +Li FGG484bga-p10 +Sc 4C6A0A06 +AR /4C7BC2B2/4C431E53 +Op 0 0 0 +At SMD +T0 -4100 -4732 200 200 0 40 N V 25 N"U1" +T1 0 150 200 200 0 40 N I 25 N"XC6SLX45FGG484" +DS -4527 4527 -4527 -4527 39 21 +DS -4527 -4527 4527 -4527 39 21 +DS 4527 -4527 4527 4527 39 21 +DS 4527 4527 -4527 4527 39 21 +DS -4527 -4527 -4527 -4842 39 21 +DS -4527 -4842 -4842 -4842 39 21 +DS -4842 -4842 -4842 -4527 39 21 +DS -4842 -4527 -4527 -4527 39 21 +$PAD +Sh "A1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -4133 -4133 +$EndPAD +$PAD +Sh "A2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3739 -4133 +$EndPAD +$PAD +Sh "A3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -3346 -4133 +$EndPAD +$PAD +Sh "A4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 63 "/fpga1/ETH_CLK" +Po -2952 -4133 +$EndPAD +$PAD +Sh "A5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 68 "/fpga1/ETH_RXD1" +Po -2558 -4133 +$EndPAD +$PAD +Sh "A6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 15 "/ether/ETH_RXDV" +Po -2165 -4133 +$EndPAD +$PAD +Sh "A7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 67 "/fpga1/ETH_RXC" +Po -1771 -4133 +$EndPAD +$PAD +Sh "A8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 75 "/fpga1/ETH_TXD3" +Po -1377 -4133 +$EndPAD +$PAD +Sh "A9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 64 "/fpga1/ETH_COL" +Po -983 -4133 +$EndPAD +$PAD +Sh "A10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 9 "/ether/ETH_INT" +Po -590 -4133 +$EndPAD +$PAD +Sh "A11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 101 "/fpga1/NF_D6" +Po -196 -4133 +$EndPAD +$PAD +Sh "A12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 55 "/flash/NF_D4" +Po 196 -4133 +$EndPAD +$PAD +Sh "A13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 54 "/flash/NF_D2" +Po 590 -4133 +$EndPAD +$PAD +Sh "A14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 96 "/fpga1/NF_ALE" +Po 983 -4133 +$EndPAD +$PAD +Sh "A15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 103 "/fpga1/NF_RNB" +Po 1377 -4133 +$EndPAD +$PAD +Sh "A16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 61 "/flash/SD_DAT2" +Po 1771 -4133 +$EndPAD +$PAD +Sh "A17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 110 "/fpga1/SD_CLK" +Po 2165 -4133 +$EndPAD +$PAD +Sh "A18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 111 "/fpga1/SD_DAT0" +Po 2558 -4133 +$EndPAD +$PAD +Sh "A19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2952 -4133 +$EndPAD +$PAD +Sh "A20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 244 "/fpga2/USBD_RCV" +Po 3346 -4133 +$EndPAD +$PAD +Sh "A21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 286 "/usb/USBD_OE_N" +Po 3739 -4133 +$EndPAD +$PAD +Sh "A22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 4133 -4133 +$EndPAD +$PAD +Sh "B1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -4133 -3739 +$EndPAD +$PAD +Sh "B2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3739 -3739 +$EndPAD +$PAD +Sh "B3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3346 -3739 +$EndPAD +$PAD +Sh "B4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -2952 -3739 +$EndPAD +$PAD +Sh "B5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2558 -3739 +$EndPAD +$PAD +Sh "B6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/ether/ETH_RXD0" +Po -2165 -3739 +$EndPAD +$PAD +Sh "B7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -1771 -3739 +$EndPAD +$PAD +Sh "B8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 16 "/ether/ETH_RXER" +Po -1377 -3739 +$EndPAD +$PAD +Sh "B9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -983 -3739 +$EndPAD +$PAD +Sh "B10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 8 "/ether/ETH_CRS" +Po -590 -3739 +$EndPAD +$PAD +Sh "B11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -196 -3739 +$EndPAD +$PAD +Sh "B12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 100 "/fpga1/NF_D3" +Po 196 -3739 +$EndPAD +$PAD +Sh "B13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 590 -3739 +$EndPAD +$PAD +Sh "B14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 53 "/flash/NF_CLE" +Po 983 -3739 +$EndPAD +$PAD +Sh "B15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 1377 -3739 +$EndPAD +$PAD +Sh "B16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 62 "/flash/SD_DAT3" +Po 1771 -3739 +$EndPAD +$PAD +Sh "B17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 2165 -3739 +$EndPAD +$PAD +Sh "B18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 60 "/flash/SD_DAT1" +Po 2558 -3739 +$EndPAD +$PAD +Sh "B19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 2952 -3739 +$EndPAD +$PAD +Sh "B20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 287 "/usb/USBD_SPD" +Po 3346 -3739 +$EndPAD +$PAD +Sh "B21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 289 "/usb/USBD_VP" +Po 3739 -3739 +$EndPAD +$PAD +Sh "B22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 288 "/usb/USBD_VM" +Po 4133 -3739 +$EndPAD +$PAD +Sh "C1" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 165 "/fpga2/R_M0_A11" +Po -4133 -3346 +$EndPAD +$PAD +Sh "C2" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -3739 -3346 +$EndPAD +$PAD +Sh "C3" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3346 -3346 +$EndPAD +$PAD +Sh "C4" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 -3346 +$EndPAD +$PAD +Sh "C5" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 70 "/fpga1/ETH_RXD3" +Po -2558 -3346 +$EndPAD +$PAD +Sh "C6" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 69 "/fpga1/ETH_RXD2" +Po -2165 -3346 +$EndPAD +$PAD +Sh "C7" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 66 "/fpga1/ETH_RESET_N" +Po -1771 -3346 +$EndPAD +$PAD +Sh "C8" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 71 "/fpga1/ETH_TXC" +Po -1377 -3346 +$EndPAD +$PAD +Sh "C9" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 73 "/fpga1/ETH_TXD1" +Po -983 -3346 +$EndPAD +$PAD +Sh "C10" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 74 "/fpga1/ETH_TXD2" +Po -590 -3346 +$EndPAD +$PAD +Sh "C11" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 56 "/flash/NF_D5" +Po -196 -3346 +$EndPAD +$PAD +Sh "C12" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 98 "/fpga1/NF_D0" +Po 196 -3346 +$EndPAD +$PAD +Sh "C13" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 590 -3346 +$EndPAD +$PAD +Sh "C14" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 58 "/flash/NF_WE_N" +Po 983 -3346 +$EndPAD +$PAD +Sh "C15" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 57 "/flash/NF_RE_N" +Po 1377 -3346 +$EndPAD +$PAD +Sh "C16" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 59 "/flash/SD_CMD" +Po 1771 -3346 +$EndPAD +$PAD +Sh "C17" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2165 -3346 +$EndPAD +$PAD +Sh "C18" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 -3346 +$EndPAD +$PAD +Sh "C19" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 282 "/usb/USBA_OE_N" +Po 2952 -3346 +$EndPAD +$PAD +Sh "C20" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 212 "/fpga2/R_M1_A8" +Po 3346 -3346 +$EndPAD +$PAD +Sh "C21" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 3739 -3346 +$EndPAD +$PAD +Sh "C22" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 213 "/fpga2/R_M1_A9" +Po 4133 -3346 +$EndPAD +$PAD +Sh "D1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 166 "/fpga2/R_M0_A12" +Po -4133 -2952 +$EndPAD +$PAD +Sh "D2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 178 "/fpga2/R_M0_CKE" +Po -3739 -2952 +$EndPAD +$PAD +Sh "D3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3346 -2952 +$EndPAD +$PAD +Sh "D4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2952 -2952 +$EndPAD +$PAD +Sh "D5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2558 -2952 +$EndPAD +$PAD +Sh "D6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 12 "/ether/ETH_MDIO" +Po -2165 -2952 +$EndPAD +$PAD +Sh "D7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "/fpga1/ETH_MDC" +Po -1771 -2952 +$EndPAD +$PAD +Sh "D8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 17 "/ether/ETH_TXER" +Po -1377 -2952 +$EndPAD +$PAD +Sh "D9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 76 "/fpga1/ETH_TXEN" +Po -983 -2952 +$EndPAD +$PAD +Sh "D10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 72 "/fpga1/ETH_TXD0" +Po -590 -2952 +$EndPAD +$PAD +Sh "D11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 102 "/fpga1/NF_D7" +Po -196 -2952 +$EndPAD +$PAD +Sh "D12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 -2952 +$EndPAD +$PAD +Sh "D13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 590 -2952 +$EndPAD +$PAD +Sh "D14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 99 "/fpga1/NF_D1" +Po 983 -2952 +$EndPAD +$PAD +Sh "D15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 97 "/fpga1/NF_CS1_N" +Po 1377 -2952 +$EndPAD +$PAD +Sh "D16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 1771 -2952 +$EndPAD +$PAD +Sh "D17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2165 -2952 +$EndPAD +$PAD +Sh "D18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 2558 -2952 +$EndPAD +$PAD +Sh "D19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 243 "/fpga2/USBA_VP" +Po 2952 -2952 +$EndPAD +$PAD +Sh "D20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 242 "/fpga2/USBA_VM" +Po 3346 -2952 +$EndPAD +$PAD +Sh "D21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 217 "/fpga2/R_M1_CKE" +Po 3739 -2952 +$EndPAD +$PAD +Sh "D22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 205 "/fpga2/R_M1_A12" +Po 4133 -2952 +$EndPAD +$PAD +Sh "E1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 174 "/fpga2/R_M0_A9" +Po -4133 -2558 +$EndPAD +$PAD +Sh "E2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -3739 -2558 +$EndPAD +$PAD +Sh "E3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 173 "/fpga2/R_M0_A8" +Po -3346 -2558 +$EndPAD +$PAD +Sh "E4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 -2558 +$EndPAD +$PAD +Sh "E5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2558 -2558 +$EndPAD +$PAD +Sh "E6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 -2558 +$EndPAD +$PAD +Sh "E7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -1771 -2558 +$EndPAD +$PAD +Sh "E8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 -2558 +$EndPAD +$PAD +Sh "E9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -983 -2558 +$EndPAD +$PAD +Sh "E10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -590 -2558 +$EndPAD +$PAD +Sh "E11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -196 -2558 +$EndPAD +$PAD +Sh "E12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 -2558 +$EndPAD +$PAD +Sh "E13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 590 -2558 +$EndPAD +$PAD +Sh "E14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 983 -2558 +$EndPAD +$PAD +Sh "E15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 1377 -2558 +$EndPAD +$PAD +Sh "E16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1771 -2558 +$EndPAD +$PAD +Sh "E17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 2165 -2558 +$EndPAD +$PAD +Sh "E18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 -2558 +$EndPAD +$PAD +Sh "E19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 2952 -2558 +$EndPAD +$PAD +Sh "E20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 211 "/fpga2/R_M1_A7" +Po 3346 -2558 +$EndPAD +$PAD +Sh "E21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 3739 -2558 +$EndPAD +$PAD +Sh "E22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 206 "/fpga2/R_M1_A2" +Po 4133 -2558 +$EndPAD +$PAD +Sh "F1" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -4133 -2165 +$EndPAD +$PAD +Sh "F2" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 200 "/fpga2/R_M0_WE#" +Po -3739 -2165 +$EndPAD +$PAD +Sh "F3" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 169 "/fpga2/R_M0_A4" +Po -3346 -2165 +$EndPAD +$PAD +Sh "F4" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2952 -2165 +$EndPAD +$PAD +Sh "F5" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2558 -2165 +$EndPAD +$PAD +Sh "F6" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2165 -2165 +$EndPAD +$PAD +Sh "F7" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1771 -2165 +$EndPAD +$PAD +Sh "F8" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 -2165 +$EndPAD +$PAD +Sh "F9" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -983 -2165 +$EndPAD +$PAD +Sh "F10" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -590 -2165 +$EndPAD +$PAD +Sh "F11" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -196 -2165 +$EndPAD +$PAD +Sh "F12" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 -2165 +$EndPAD +$PAD +Sh "F13" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 590 -2165 +$EndPAD +$PAD +Sh "F14" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 983 -2165 +$EndPAD +$PAD +Sh "F15" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1377 -2165 +$EndPAD +$PAD +Sh "F16" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 283 "/usb/USBA_SPD" +Po 1771 -2165 +$EndPAD +$PAD +Sh "F17" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 241 "/fpga2/USBA_RCV" +Po 2165 -2165 +$EndPAD +$PAD +Sh "F18" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 -2165 +$EndPAD +$PAD +Sh "F19" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 204 "/fpga2/R_M1_A11" +Po 2952 -2165 +$EndPAD +$PAD +Sh "F20" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 208 "/fpga2/R_M1_A4" +Po 3346 -2165 +$EndPAD +$PAD +Sh "F21" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 201 "/fpga2/R_M1_A0" +Po 3739 -2165 +$EndPAD +$PAD +Sh "F22" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 202 "/fpga2/R_M1_A1" +Po 4133 -2165 +$EndPAD +$PAD +Sh "G1" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 176 "/fpga2/R_M0_BA1" +Po -4133 -1771 +$EndPAD +$PAD +Sh "G2" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -3739 -1771 +$EndPAD +$PAD +Sh "G3" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 175 "/fpga2/R_M0_BA0" +Po -3346 -1771 +$EndPAD +$PAD +Sh "G4" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 164 "/fpga2/R_M0_A10" +Po -2952 -1771 +$EndPAD +$PAD +Sh "G5" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2558 -1771 +$EndPAD +$PAD +Sh "G6" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 -1771 +$EndPAD +$PAD +Sh "G7" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1771 -1771 +$EndPAD +$PAD +Sh "G8" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 -1771 +$EndPAD +$PAD +Sh "G9" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -983 -1771 +$EndPAD +$PAD +Sh "G10" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -590 -1771 +$EndPAD +$PAD +Sh "G11" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 -1771 +$EndPAD +$PAD +Sh "G12" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 196 -1771 +$EndPAD +$PAD +Sh "G13" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 590 -1771 +$EndPAD +$PAD +Sh "G14" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 983 -1771 +$EndPAD +$PAD +Sh "G15" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1377 -1771 +$EndPAD +$PAD +Sh "G16" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1771 -1771 +$EndPAD +$PAD +Sh "G17" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2165 -1771 +$EndPAD +$PAD +Sh "G18" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 2558 -1771 +$EndPAD +$PAD +Sh "G19" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 203 "/fpga2/R_M1_A10" +Po 2952 -1771 +$EndPAD +$PAD +Sh "G20" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 207 "/fpga2/R_M1_A3" +Po 3346 -1771 +$EndPAD +$PAD +Sh "G21" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 3739 -1771 +$EndPAD +$PAD +Sh "G22" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 4133 -1771 +$EndPAD +$PAD +Sh "H1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 163 "/fpga2/R_M0_A1" +Po -4133 -1377 +$EndPAD +$PAD +Sh "H2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 162 "/fpga2/R_M0_A0" +Po -3739 -1377 +$EndPAD +$PAD +Sh "H3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 249 "/sdram/M0_CLK#" +Po -3346 -1377 +$EndPAD +$PAD +Sh "H4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 125 "/fpga2/M0_CLK" +Po -2952 -1377 +$EndPAD +$PAD +Sh "H5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 167 "/fpga2/R_M0_A2" +Po -2558 -1377 +$EndPAD +$PAD +Sh "H6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 172 "/fpga2/R_M0_A7" +Po -2165 -1377 +$EndPAD +$PAD +Sh "H7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -1771 -1377 +$EndPAD +$PAD +Sh "H8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 -1377 +$EndPAD +$PAD +Sh "H9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -983 -1377 +$EndPAD +$PAD +Sh "H10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -590 -1377 +$EndPAD +$PAD +Sh "H11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 -1377 +$EndPAD +$PAD +Sh "H12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 -1377 +$EndPAD +$PAD +Sh "H13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 590 -1377 +$EndPAD +$PAD +Sh "H14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 983 -1377 +$EndPAD +$PAD +Sh "H15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 1377 -1377 +$EndPAD +$PAD +Sh "H16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 218 "/fpga2/R_M1_CS#" +Po 1771 -1377 +$EndPAD +$PAD +Sh "H17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2165 -1377 +$EndPAD +$PAD +Sh "H18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 -1377 +$EndPAD +$PAD +Sh "H19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 240 "/fpga2/R_M1_WE#" +Po 2952 -1377 +$EndPAD +$PAD +Sh "H20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 268 "/sdram/M1_CLK" +Po 3346 -1377 +$EndPAD +$PAD +Sh "H21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 237 "/fpga2/R_M1_RAS#" +Po 3739 -1377 +$EndPAD +$PAD +Sh "H22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 216 "/fpga2/R_M1_CAS#" +Po 4133 -1377 +$EndPAD +$PAD +Sh "J1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 190 "/fpga2/R_M0_DQ5" +Po -4133 -983 +$EndPAD +$PAD +Sh "J2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -3739 -983 +$EndPAD +$PAD +Sh "J3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 189 "/fpga2/R_M0_DQ4" +Po -3346 -983 +$EndPAD +$PAD +Sh "J4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 171 "/fpga2/R_M0_A6" +Po -2952 -983 +$EndPAD +$PAD +Sh "J5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2558 -983 +$EndPAD +$PAD +Sh "J6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 -983 +$EndPAD +$PAD +Sh "J7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1771 -983 +$EndPAD +$PAD +Sh "J8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -1377 -983 +$EndPAD +$PAD +Sh "J9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -983 -983 +$EndPAD +$PAD +Sh "J10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -590 -983 +$EndPAD +$PAD +Sh "J11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -196 -983 +$EndPAD +$PAD +Sh "J12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 196 -983 +$EndPAD +$PAD +Sh "J13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 590 -983 +$EndPAD +$PAD +Sh "J14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 983 -983 +$EndPAD +$PAD +Sh "J15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 1377 -983 +$EndPAD +$PAD +Sh "J16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1771 -983 +$EndPAD +$PAD +Sh "J17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 214 "/fpga2/R_M1_BA0" +Po 2165 -983 +$EndPAD +$PAD +Sh "J18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 2558 -983 +$EndPAD +$PAD +Sh "J19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 269 "/sdram/M1_CLK#" +Po 2952 -983 +$EndPAD +$PAD +Sh "J20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 229 "/fpga2/R_M1_DQ4" +Po 3346 -983 +$EndPAD +$PAD +Sh "J21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 3739 -983 +$EndPAD +$PAD +Sh "J22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 230 "/fpga2/R_M1_DQ5" +Po 4133 -983 +$EndPAD +$PAD +Sh "K1" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 192 "/fpga2/R_M0_DQ7" +Po -4133 -590 +$EndPAD +$PAD +Sh "K2" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 191 "/fpga2/R_M0_DQ6" +Po -3739 -590 +$EndPAD +$PAD +Sh "K3" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 170 "/fpga2/R_M0_A5" +Po -3346 -590 +$EndPAD +$PAD +Sh "K4" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 177 "/fpga2/R_M0_CAS#" +Po -2952 -590 +$EndPAD +$PAD +Sh "K5" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 197 "/fpga2/R_M0_RAS#" +Po -2558 -590 +$EndPAD +$PAD +Sh "K6" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 168 "/fpga2/R_M0_A3" +Po -2165 -590 +$EndPAD +$PAD +Sh "K7" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1771 -590 +$EndPAD +$PAD +Sh "K8" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 -590 +$EndPAD +$PAD +Sh "K9" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -983 -590 +$EndPAD +$PAD +Sh "K10" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -590 -590 +$EndPAD +$PAD +Sh "K11" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -196 -590 +$EndPAD +$PAD +Sh "K12" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 196 -590 +$EndPAD +$PAD +Sh "K13" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 590 -590 +$EndPAD +$PAD +Sh "K14" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 983 -590 +$EndPAD +$PAD +Sh "K15" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 1377 -590 +$EndPAD +$PAD +Sh "K16" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1771 -590 +$EndPAD +$PAD +Sh "K17" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 215 "/fpga2/R_M1_BA1" +Po 2165 -590 +$EndPAD +$PAD +Sh "K18" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 -590 +$EndPAD +$PAD +Sh "K19" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 210 "/fpga2/R_M1_A6" +Po 2952 -590 +$EndPAD +$PAD +Sh "K20" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 209 "/fpga2/R_M1_A5" +Po 3346 -590 +$EndPAD +$PAD +Sh "K21" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 231 "/fpga2/R_M1_DQ6" +Po 3739 -590 +$EndPAD +$PAD +Sh "K22" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 232 "/fpga2/R_M1_DQ7" +Po 4133 -590 +$EndPAD +$PAD +Sh "L1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -4133 -196 +$EndPAD +$PAD +Sh "L2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -3739 -196 +$EndPAD +$PAD +Sh "L3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 196 "/fpga2/R_M0_LDQS" +Po -3346 -196 +$EndPAD +$PAD +Sh "L4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 195 "/fpga2/R_M0_LDM" +Po -2952 -196 +$EndPAD +$PAD +Sh "L5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2558 -196 +$EndPAD +$PAD +Sh "L6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 -196 +$EndPAD +$PAD +Sh "L7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -1771 -196 +$EndPAD +$PAD +Sh "L8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -1377 -196 +$EndPAD +$PAD +Sh "L9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -983 -196 +$EndPAD +$PAD +Sh "L10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -590 -196 +$EndPAD +$PAD +Sh "L11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -196 -196 +$EndPAD +$PAD +Sh "L12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 196 -196 +$EndPAD +$PAD +Sh "L13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 590 -196 +$EndPAD +$PAD +Sh "L14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 983 -196 +$EndPAD +$PAD +Sh "L15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1377 -196 +$EndPAD +$PAD +Sh "L16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 1771 -196 +$EndPAD +$PAD +Sh "L17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2165 -196 +$EndPAD +$PAD +Sh "L18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 2558 -196 +$EndPAD +$PAD +Sh "L19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 235 "/fpga2/R_M1_LDM" +Po 2952 -196 +$EndPAD +$PAD +Sh "L20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 236 "/fpga2/R_M1_LDQS" +Po 3346 -196 +$EndPAD +$PAD +Sh "L21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 3739 -196 +$EndPAD +$PAD +Sh "L22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 4133 -196 +$EndPAD +$PAD +Sh "M1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 188 "/fpga2/R_M0_DQ3" +Po -4133 196 +$EndPAD +$PAD +Sh "M2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 187 "/fpga2/R_M0_DQ2" +Po -3739 196 +$EndPAD +$PAD +Sh "M3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 198 "/fpga2/R_M0_UDM" +Po -3346 196 +$EndPAD +$PAD +Sh "M4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 196 +$EndPAD +$PAD +Sh "M5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2558 196 +$EndPAD +$PAD +Sh "M6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 196 +$EndPAD +$PAD +Sh "M7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1771 196 +$EndPAD +$PAD +Sh "M8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 196 +$EndPAD +$PAD +Sh "M9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -983 196 +$EndPAD +$PAD +Sh "M10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -590 196 +$EndPAD +$PAD +Sh "M11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -196 196 +$EndPAD +$PAD +Sh "M12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 196 196 +$EndPAD +$PAD +Sh "M13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 590 196 +$EndPAD +$PAD +Sh "M14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 983 196 +$EndPAD +$PAD +Sh "M15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 1377 196 +$EndPAD +$PAD +Sh "M16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1771 196 +$EndPAD +$PAD +Sh "M17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2165 196 +$EndPAD +$PAD +Sh "M18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 196 +$EndPAD +$PAD +Sh "M19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2952 196 +$EndPAD +$PAD +Sh "M20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 238 "/fpga2/R_M1_UDM" +Po 3346 196 +$EndPAD +$PAD +Sh "M21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 227 "/fpga2/R_M1_DQ2" +Po 3739 196 +$EndPAD +$PAD +Sh "M22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 228 "/fpga2/R_M1_DQ3" +Po 4133 196 +$EndPAD +$PAD +Sh "N1" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 180 "/fpga2/R_M0_DQ1" +Po -4133 590 +$EndPAD +$PAD +Sh "N2" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -3739 590 +$EndPAD +$PAD +Sh "N3" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 179 "/fpga2/R_M0_DQ0" +Po -3346 590 +$EndPAD +$PAD +Sh "N4" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 590 +$EndPAD +$PAD +Sh "N5" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2558 590 +$EndPAD +$PAD +Sh "N6" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 590 +$EndPAD +$PAD +Sh "N7" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1771 590 +$EndPAD +$PAD +Sh "N8" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -1377 590 +$EndPAD +$PAD +Sh "N9" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -983 590 +$EndPAD +$PAD +Sh "N10" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -590 590 +$EndPAD +$PAD +Sh "N11" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -196 590 +$EndPAD +$PAD +Sh "N12" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 196 590 +$EndPAD +$PAD +Sh "N13" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 590 590 +$EndPAD +$PAD +Sh "N14" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 983 590 +$EndPAD +$PAD +Sh "N15" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 1377 590 +$EndPAD +$PAD +Sh "N16" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1771 590 +$EndPAD +$PAD +Sh "N17" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 2165 590 +$EndPAD +$PAD +Sh "N18" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 2558 590 +$EndPAD +$PAD +Sh "N19" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2952 590 +$EndPAD +$PAD +Sh "N20" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 219 "/fpga2/R_M1_DQ0" +Po 3346 590 +$EndPAD +$PAD +Sh "N21" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 3739 590 +$EndPAD +$PAD +Sh "N22" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 220 "/fpga2/R_M1_DQ1" +Po 4133 590 +$EndPAD +$PAD +Sh "P1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 194 "/fpga2/R_M0_DQ9" +Po -4133 983 +$EndPAD +$PAD +Sh "P2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 193 "/fpga2/R_M0_DQ8" +Po -3739 983 +$EndPAD +$PAD +Sh "P3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3346 983 +$EndPAD +$PAD +Sh "P4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 983 +$EndPAD +$PAD +Sh "P5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2558 983 +$EndPAD +$PAD +Sh "P6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 983 +$EndPAD +$PAD +Sh "P7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1771 983 +$EndPAD +$PAD +Sh "P8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 983 +$EndPAD +$PAD +Sh "P9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -983 983 +$EndPAD +$PAD +Sh "P10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -590 983 +$EndPAD +$PAD +Sh "P11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -196 983 +$EndPAD +$PAD +Sh "P12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 196 983 +$EndPAD +$PAD +Sh "P13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 590 983 +$EndPAD +$PAD +Sh "P14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 983 983 +$EndPAD +$PAD +Sh "P15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1377 983 +$EndPAD +$PAD +Sh "P16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1771 983 +$EndPAD +$PAD +Sh "P17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2165 983 +$EndPAD +$PAD +Sh "P18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 983 +$EndPAD +$PAD +Sh "P19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2952 983 +$EndPAD +$PAD +Sh "P20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 3346 983 +$EndPAD +$PAD +Sh "P21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 233 "/fpga2/R_M1_DQ8" +Po 3739 983 +$EndPAD +$PAD +Sh "P22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 234 "/fpga2/R_M1_DQ9" +Po 4133 983 +$EndPAD +$PAD +Sh "R1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 182 "/fpga2/R_M0_DQ11" +Po -4133 1377 +$EndPAD +$PAD +Sh "R2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -3739 1377 +$EndPAD +$PAD +Sh "R3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 181 "/fpga2/R_M0_DQ10" +Po -3346 1377 +$EndPAD +$PAD +Sh "R4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 1377 +$EndPAD +$PAD +Sh "R5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2558 1377 +$EndPAD +$PAD +Sh "R6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2165 1377 +$EndPAD +$PAD +Sh "R7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1771 1377 +$EndPAD +$PAD +Sh "R8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 1377 +$EndPAD +$PAD +Sh "R9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 92 "/fpga1/FPGA_BANK0_IO_58" +Po -983 1377 +$EndPAD +$PAD +Sh "R10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -590 1377 +$EndPAD +$PAD +Sh "R11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 1377 +$EndPAD +$PAD +Sh "R12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 196 1377 +$EndPAD +$PAD +Sh "R13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 590 1377 +$EndPAD +$PAD +Sh "R14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po 983 1377 +$EndPAD +$PAD +Sh "R15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1377 1377 +$EndPAD +$PAD +Sh "R16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 25 "/expansion/FPGA_BANK0_IO_12" +Po 1771 1377 +$EndPAD +$PAD +Sh "R17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2165 1377 +$EndPAD +$PAD +Sh "R18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 2558 1377 +$EndPAD +$PAD +Sh "R19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2952 1377 +$EndPAD +$PAD +Sh "R20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 221 "/fpga2/R_M1_DQ10" +Po 3346 1377 +$EndPAD +$PAD +Sh "R21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 3739 1377 +$EndPAD +$PAD +Sh "R22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 222 "/fpga2/R_M1_DQ11" +Po 4133 1377 +$EndPAD +$PAD +Sh "T1" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -4133 1771 +$EndPAD +$PAD +Sh "T2" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 199 "/fpga2/R_M0_UDQS" +Po -3739 1771 +$EndPAD +$PAD +Sh "T3" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3346 1771 +$EndPAD +$PAD +Sh "T4" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 1771 +$EndPAD +$PAD +Sh "T5" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 105 "/fpga1/PROG_CSO" +Po -2558 1771 +$EndPAD +$PAD +Sh "T6" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 1771 +$EndPAD +$PAD +Sh "T7" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 49 "/expansion/FPGA_BANK0_IO_60" +Po -1771 1771 +$EndPAD +$PAD +Sh "T8" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 46 "/expansion/FPGA_BANK0_IO_53" +Po -1377 1771 +$EndPAD +$PAD +Sh "T9" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po -983 1771 +$EndPAD +$PAD +Sh "T10" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -590 1771 +$EndPAD +$PAD +Sh "T11" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 1771 +$EndPAD +$PAD +Sh "T12" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 36 "/expansion/FPGA_BANK0_IO_34" +Po 196 1771 +$EndPAD +$PAD +Sh "T13" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po 590 1771 +$EndPAD +$PAD +Sh "T14" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 37 "/expansion/FPGA_BANK0_IO_36" +Po 983 1771 +$EndPAD +$PAD +Sh "T15" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 95 "/fpga1/FPGA_BANK0_IO_7" +Po 1377 1771 +$EndPAD +$PAD +Sh "T16" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 93 "/fpga1/FPGA_BANK0_IO_6" +Po 1771 1771 +$EndPAD +$PAD +Sh "T17" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 79 "/fpga1/FPGA_BANK0_IO_2" +Po 2165 1771 +$EndPAD +$PAD +Sh "T18" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 23 "/expansion/FPGA_BANK0_IO_1" +Po 2558 1771 +$EndPAD +$PAD +Sh "T19" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2952 1771 +$EndPAD +$PAD +Sh "T20" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 3346 1771 +$EndPAD +$PAD +Sh "T21" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 239 "/fpga2/R_M1_UDQS" +Po 3739 1771 +$EndPAD +$PAD +Sh "T22" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 4133 1771 +$EndPAD +$PAD +Sh "U1" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 184 "/fpga2/R_M0_DQ13" +Po -4133 2165 +$EndPAD +$PAD +Sh "U2" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -3739 2165 +$EndPAD +$PAD +Sh "U3" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 183 "/fpga2/R_M0_DQ12" +Po -3346 2165 +$EndPAD +$PAD +Sh "U4" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 2165 +$EndPAD +$PAD +Sh "U5" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2558 2165 +$EndPAD +$PAD +Sh "U6" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 94 "/fpga1/FPGA_BANK0_IO_62" +Po -2165 2165 +$EndPAD +$PAD +Sh "U7" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -1771 2165 +$EndPAD +$PAD +Sh "U8" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 47 "/expansion/FPGA_BANK0_IO_54" +Po -1377 2165 +$EndPAD +$PAD +Sh "U9" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 89 "/fpga1/FPGA_BANK0_IO_51" +Po -983 2165 +$EndPAD +$PAD +Sh "U10" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 91 "/fpga1/FPGA_BANK0_IO_56" +Po -590 2165 +$EndPAD +$PAD +Sh "U11" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -196 2165 +$EndPAD +$PAD +Sh "U12" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 2165 +$EndPAD +$PAD +Sh "U13" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 109 "/fpga1/PROG_MISO3" +Po 590 2165 +$EndPAD +$PAD +Sh "U14" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 108 "/fpga1/PROG_MISO2" +Po 983 2165 +$EndPAD +$PAD +Sh "U15" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 1377 2165 +$EndPAD +$PAD +Sh "U16" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 52 "/expansion/FPGA_BANK0_IO_9" +Po 1771 2165 +$EndPAD +$PAD +Sh "U17" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 51 "/expansion/FPGA_BANK0_IO_8" +Po 2165 2165 +$EndPAD +$PAD +Sh "U18" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 2558 2165 +$EndPAD +$PAD +Sh "U19" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2952 2165 +$EndPAD +$PAD +Sh "U20" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 223 "/fpga2/R_M1_DQ12" +Po 3346 2165 +$EndPAD +$PAD +Sh "U21" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 3739 2165 +$EndPAD +$PAD +Sh "U22" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "/fpga2/R_M1_DQ13" +Po 4133 2165 +$EndPAD +$PAD +Sh "V1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 186 "/fpga2/R_M0_DQ15" +Po -4133 2558 +$EndPAD +$PAD +Sh "V2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 185 "/fpga2/R_M0_DQ14" +Po -3739 2558 +$EndPAD +$PAD +Sh "V3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3346 2558 +$EndPAD +$PAD +Sh "V4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2952 2558 +$EndPAD +$PAD +Sh "V5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 50 "/expansion/FPGA_BANK0_IO_63" +Po -2558 2558 +$EndPAD +$PAD +Sh "V6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2165 2558 +$EndPAD +$PAD +Sh "V7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 44 "/expansion/FPGA_BANK0_IO_49" +Po -1771 2558 +$EndPAD +$PAD +Sh "V8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po -1377 2558 +$EndPAD +$PAD +Sh "V9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 90 "/fpga1/FPGA_BANK0_IO_52" +Po -983 2558 +$EndPAD +$PAD +Sh "V10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -590 2558 +$EndPAD +$PAD +Sh "V11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 40 "/expansion/FPGA_BANK0_IO_43" +Po -196 2558 +$EndPAD +$PAD +Sh "V12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po 196 2558 +$EndPAD +$PAD +Sh "V13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 590 2558 +$EndPAD +$PAD +Sh "V14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 983 2558 +$EndPAD +$PAD +Sh "V15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 28 "/expansion/FPGA_BANK0_IO_17" +Po 1377 2558 +$EndPAD +$PAD +Sh "V16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po 1771 2558 +$EndPAD +$PAD +Sh "V17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 26 "/expansion/FPGA_BANK0_IO_14" +Po 2165 2558 +$EndPAD +$PAD +Sh "V18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 77 "/fpga1/FPGA_BANK0_IO_11" +Po 2558 2558 +$EndPAD +$PAD +Sh "V19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 24 "/expansion/FPGA_BANK0_IO_10" +Po 2952 2558 +$EndPAD +$PAD +Sh "V20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 3346 2558 +$EndPAD +$PAD +Sh "V21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 225 "/fpga2/R_M1_DQ14" +Po 3739 2558 +$EndPAD +$PAD +Sh "V22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 226 "/fpga2/R_M1_DQ15" +Po 4133 2558 +$EndPAD +$PAD +Sh "W1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -4133 2952 +$EndPAD +$PAD +Sh "W2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -3739 2952 +$EndPAD +$PAD +Sh "W3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3346 2952 +$EndPAD +$PAD +Sh "W4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 2952 +$EndPAD +$PAD +Sh "W5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po -2558 2952 +$EndPAD +$PAD +Sh "W6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 48 "/expansion/FPGA_BANK0_IO_57" +Po -2165 2952 +$EndPAD +$PAD +Sh "W7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -1771 2952 +$EndPAD +$PAD +Sh "W8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 87 "/fpga1/FPGA_BANK0_IO_48" +Po -1377 2952 +$EndPAD +$PAD +Sh "W9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 88 "/fpga1/FPGA_BANK0_IO_50" +Po -983 2952 +$EndPAD +$PAD +Sh "W10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 42 "/expansion/FPGA_BANK0_IO_46" +Po -590 2952 +$EndPAD +$PAD +Sh "W11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 86 "/fpga1/FPGA_BANK0_IO_44" +Po -196 2952 +$EndPAD +$PAD +Sh "W12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 2952 +$EndPAD +$PAD +Sh "W13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 31 "/expansion/FPGA_BANK0_IO_27" +Po 590 2952 +$EndPAD +$PAD +Sh "W14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 34 "/expansion/FPGA_BANK0_IO_30" +Po 983 2952 +$EndPAD +$PAD +Sh "W15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 82 "/fpga1/FPGA_BANK0_IO_25" +Po 1377 2952 +$EndPAD +$PAD +Sh "W16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 1771 2952 +$EndPAD +$PAD +Sh "W17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 27 "/expansion/FPGA_BANK0_IO_15" +Po 2165 2952 +$EndPAD +$PAD +Sh "W18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 2952 +$EndPAD +$PAD +Sh "W19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 2952 2952 +$EndPAD +$PAD +Sh "W20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 3346 2952 +$EndPAD +$PAD +Sh "W21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 3739 2952 +$EndPAD +$PAD +Sh "W22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 4133 2952 +$EndPAD +$PAD +Sh "Y1" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -4133 3346 +$EndPAD +$PAD +Sh "Y2" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3739 3346 +$EndPAD +$PAD +Sh "Y3" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3346 3346 +$EndPAD +$PAD +Sh "Y4" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 3346 +$EndPAD +$PAD +Sh "Y5" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2558 3346 +$EndPAD +$PAD +Sh "Y6" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 3346 +$EndPAD +$PAD +Sh "Y7" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1771 3346 +$EndPAD +$PAD +Sh "Y8" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 3346 +$EndPAD +$PAD +Sh "Y9" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 41 "/expansion/FPGA_BANK0_IO_45" +Po -983 3346 +$EndPAD +$PAD +Sh "Y10" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 43 "/expansion/FPGA_BANK0_IO_47" +Po -590 3346 +$EndPAD +$PAD +Sh "Y11" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 85 "/fpga1/FPGA_BANK0_IO_40" +Po -196 3346 +$EndPAD +$PAD +Sh "Y12" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 3346 +$EndPAD +$PAD +Sh "Y13" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 38 "/expansion/FPGA_BANK0_IO_38" +Po 590 3346 +$EndPAD +$PAD +Sh "Y14" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 983 3346 +$EndPAD +$PAD +Sh "Y15" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 35 "/expansion/FPGA_BANK0_IO_32" +Po 1377 3346 +$EndPAD +$PAD +Sh "Y16" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 30 "/expansion/FPGA_BANK0_IO_24" +Po 1771 3346 +$EndPAD +$PAD +Sh "Y17" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 80 "/fpga1/FPGA_BANK0_IO_20" +Po 2165 3346 +$EndPAD +$PAD +Sh "Y18" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 45 "/expansion/FPGA_BANK0_IO_5" +Po 2558 3346 +$EndPAD +$PAD +Sh "Y19" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 33 "/expansion/FPGA_BANK0_IO_3" +Po 2952 3346 +$EndPAD +$PAD +Sh "Y20" O 158 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 3346 3346 +$EndPAD +$PAD +Sh "Y21" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 3739 3346 +$EndPAD +$PAD +Sh "Y22" O 157 158 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 306 "N-000359" +Po 4133 3346 +$EndPAD +$PAD +Sh "AA1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 305 "N-000356" +Po -4133 3739 +$EndPAD +$PAD +Sh "AA2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3739 3739 +$EndPAD +$PAD +Sh "AA3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po -3346 3739 +$EndPAD +$PAD +Sh "AA4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 3739 +$EndPAD +$PAD +Sh "AA5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2558 3739 +$EndPAD +$PAD +Sh "AA6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 3739 +$EndPAD +$PAD +Sh "AA7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po -1771 3739 +$EndPAD +$PAD +Sh "AA8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 3739 +$EndPAD +$PAD +Sh "AA9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -983 3739 +$EndPAD +$PAD +Sh "AA10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -590 3739 +$EndPAD +$PAD +Sh "AA11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po -196 3739 +$EndPAD +$PAD +Sh "AA12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 3739 +$EndPAD +$PAD +Sh "AA13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 590 3739 +$EndPAD +$PAD +Sh "AA14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 81 "/fpga1/FPGA_BANK0_IO_22" +Po 983 3739 +$EndPAD +$PAD +Sh "AA15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po 1377 3739 +$EndPAD +$PAD +Sh "AA16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 83 "/fpga1/FPGA_BANK0_IO_28" +Po 1771 3739 +$EndPAD +$PAD +Sh "AA17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 2165 3739 +$EndPAD +$PAD +Sh "AA18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 78 "/fpga1/FPGA_BANK0_IO_18" +Po 2558 3739 +$EndPAD +$PAD +Sh "AA19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po 2952 3739 +$EndPAD +$PAD +Sh "AA20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 107 "/fpga1/PROG_MISO1" +Po 3346 3739 +$EndPAD +$PAD +Sh "AA21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 104 "/fpga1/PROG_CCLK" +Po 3739 3739 +$EndPAD +$PAD +Sh "AA22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po 4133 3739 +$EndPAD +$PAD +Sh "AB1" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -4133 4133 +$EndPAD +$PAD +Sh "AB2" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3739 4133 +$EndPAD +$PAD +Sh "AB3" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -3346 4133 +$EndPAD +$PAD +Sh "AB4" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2952 4133 +$EndPAD +$PAD +Sh "AB5" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2558 4133 +$EndPAD +$PAD +Sh "AB6" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2165 4133 +$EndPAD +$PAD +Sh "AB7" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1771 4133 +$EndPAD +$PAD +Sh "AB8" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1377 4133 +$EndPAD +$PAD +Sh "AB9" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -983 4133 +$EndPAD +$PAD +Sh "AB10" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -590 4133 +$EndPAD +$PAD +Sh "AB11" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 4133 +$EndPAD +$PAD +Sh "AB12" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 4133 +$EndPAD +$PAD +Sh "AB13" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 39 "/expansion/FPGA_BANK0_IO_39" +Po 590 4133 +$EndPAD +$PAD +Sh "AB14" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 983 4133 +$EndPAD +$PAD +Sh "AB15" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 84 "/fpga1/FPGA_BANK0_IO_33" +Po 1377 4133 +$EndPAD +$PAD +Sh "AB16" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 32 "/expansion/FPGA_BANK0_IO_29" +Po 1771 4133 +$EndPAD +$PAD +Sh "AB17" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 29 "/expansion/FPGA_BANK0_IO_21" +Po 2165 4133 +$EndPAD +$PAD +Sh "AB18" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2558 4133 +$EndPAD +$PAD +Sh "AB19" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2952 4133 +$EndPAD +$PAD +Sh "AB20" O 158 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 106 "/fpga1/PROG_MISO0" +Po 3346 4133 +$EndPAD +$PAD +Sh "AB21" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 3739 4133 +$EndPAD +$PAD +Sh "AB22" O 157 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 4133 4133 +$EndPAD +$EndMODULE FGG484bga-p10 +$MODULE 0402 +Po 54811 32925 1350 0 4CDB6F04 4C6B2A04 ~~ +Li 0402 +Sc 4C6B2A04 +AR /4C7BC2B2/4C6B29DA +Op 0 0 0 +At SMD +T0 587 -20 200 200 1350 40 M V 20 N"C77" +T1 0 -150 200 200 1350 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1350 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1350 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 55685 34382 0 0 4CDB6F1E 4C6B2A02 ~~ +Li 0402 +Sc 4C6B2A02 +AR /4C7BC2B2/4C6B29A3 +Op 0 0 0 +At SMD +T0 4 342 200 200 0 40 M V 20 N"C76" +T1 0 -150 200 200 0 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 1 "+1.2V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 48327 34055 1800 0 4CCF2DAB 4C6B21D8 ~~ +Li 0402 +Sc 4C6B21D8 +AR /4C7BC2A2/4C6B216E +Op 0 0 0 +At SMD +T0 -8 335 200 200 1800 40 M V 20 N"R23" +T1 0 -150 200 200 1800 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 198 "/fpga2/R_M0_UDM" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 136 "/fpga2/M0_UDM" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 48043 35280 1800 0 4CCF2E5F 4C6B21D6 ~~ +Li 0402 +Sc 4C6B21D6 +AR /4C7BC2A2/4C6B216D +Op 0 0 0 +At SMD +T0 -59 323 200 200 1800 40 M V 20 N"R22" +T1 0 -150 200 200 1800 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 199 "/fpga2/R_M0_UDQS" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 137 "/fpga2/M0_UDQS" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 48327 33268 1800 0 4CDB6E2B 4C6B21D2 ~~ +Li 0402 +Sc 4C6B21D2 +AR /4C7BC2A2/4C6B216B +Op 0 0 0 +At SMD +T0 20 347 200 200 1800 40 M V 20 N"R24" +T1 0 -150 200 200 1800 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 178 "/fpga2/R_M0_CKE" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 124 "/fpga2/M0_CKE" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 51370 33417 900 0 4CDB6ED4 4C6B1F81 ~~ +Li 0402 +Sc 4C6B1F81 +AR /4C7BC2A2/4C6B1B90 +Op 0 0 0 +At SMD +T0 -16 -354 200 200 900 40 M V 20 N"R21" +T1 0 -150 200 200 900 40 M I 20 N"120" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 125 "/fpga2/M0_CLK" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 249 "/sdram/M0_CLK#" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE R_PACK4-0402 +Po 49591 31240 900 0 4C69A686 4C6A0EC8 ~~ +Li R_PACK4-0402 +Sc 4C6A0EC8 +AR /4C7BC2A2/4C6A0D58 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP14" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 162 "/fpga2/R_M0_A0" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 163 "/fpga2/R_M0_A1" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 167 "/fpga2/R_M0_A2" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 168 "/fpga2/R_M0_A3" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 117 "/fpga2/M0_A3" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 116 "/fpga2/M0_A2" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 112 "/fpga2/M0_A1" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 245 "/sdram/M0_A0" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 49598 32217 900 0 4C69A686 4C6A0EC6 ~~ +Li R_PACK4-0402 +Sc 4C6A0EC6 +AR /4C7BC2A2/4C6A0D57 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP15" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 197 "/fpga2/R_M0_RAS#" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 175 "/fpga2/R_M0_BA0" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 176 "/fpga2/R_M0_BA1" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 164 "/fpga2/R_M0_A10" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 113 "/fpga2/M0_A10" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 123 "/fpga2/M0_BA1" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 247 "/sdram/M0_BA0" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 135 "/fpga2/M0_RAS#" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 48114 31240 2700 0 4C69A686 4C6A0EC2 ~~ +Li R_PACK4-0402 +Sc 4C6A0EC2 +AR /4C7BC2A2/4C6A0D55 +Op 0 0 0 +T0 117 451 197 197 2700 49 M V 20 N"RP17" +T1 68 -436 157 157 2700 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 172 "/fpga2/R_M0_A7" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 171 "/fpga2/R_M0_A6" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 170 "/fpga2/R_M0_A5" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 169 "/fpga2/R_M0_A4" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 246 "/sdram/M0_A4" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 118 "/fpga2/M0_A5" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 119 "/fpga2/M0_A6" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 120 "/fpga2/M0_A7" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 48118 32232 2700 0 4C69A686 4C6A0EC0 ~~ +Li R_PACK4-0402 +Sc 4C6A0EC0 +AR /4C7BC2A2/4C6A0D54 +Op 0 0 0 +T0 117 451 197 197 2700 49 M V 20 N"RP18" +T1 68 -436 157 157 2700 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 166 "/fpga2/R_M0_A12" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 165 "/fpga2/R_M0_A11" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 174 "/fpga2/R_M0_A9" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 173 "/fpga2/R_M0_A8" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 121 "/fpga2/M0_A8" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 122 "/fpga2/M0_A9" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 114 "/fpga2/M0_A11" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 115 "/fpga2/M0_A12" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 49669 36240 900 0 4CF99F84 4C6A039A ~~ +Li R_PACK4-0402 +Sc 4C6A039A +AR /4C7BC2A2/4C69FCE8 +Op 0 0 0 +T0 20 -437 197 197 900 49 M V 20 N"RP12" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 189 "/fpga2/R_M0_DQ4" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 190 "/fpga2/R_M0_DQ5" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 191 "/fpga2/R_M0_DQ6" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 192 "/fpga2/R_M0_DQ7" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 256 "/sdram/M0_DQ7" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 255 "/sdram/M0_DQ6" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 254 "/sdram/M0_DQ5" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 253 "/sdram/M0_DQ4" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 49661 37791 900 0 4CF99F8F 4C6A0398 ~~ +Li R_PACK4-0402 +Sc 4C6A0398 +AR /4C7BC2A2/4C69FCE7 +Op 0 0 0 +T0 181 -456 197 197 900 49 M V 20 N"RP13" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 179 "/fpga2/R_M0_DQ0" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 180 "/fpga2/R_M0_DQ1" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 187 "/fpga2/R_M0_DQ2" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 188 "/fpga2/R_M0_DQ3" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 132 "/fpga2/M0_DQ3" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 131 "/fpga2/M0_DQ2" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 250 "/sdram/M0_DQ1" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 126 "/fpga2/M0_DQ0" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 47528 36295 2700 0 4C69A686 4C6A0396 ~~ +Li R_PACK4-0402 +Sc 4C6A0396 +AR /4C7BC2A2/4C69FCE6 +Op 0 0 0 +T0 117 451 197 197 2700 49 M V 20 N"RP11" +T1 68 -436 157 157 2700 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 193 "/fpga2/R_M0_DQ8" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 194 "/fpga2/R_M0_DQ9" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 181 "/fpga2/R_M0_DQ10" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 182 "/fpga2/R_M0_DQ11" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 128 "/fpga2/M0_DQ11" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 127 "/fpga2/M0_DQ10" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 133 "/fpga2/M0_DQ9" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 257 "/sdram/M0_DQ8" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 47539 37787 2700 0 4C69A686 4C6A0394 ~~ +Li R_PACK4-0402 +Sc 4C6A0394 +AR /4C7BC2A2/4C69FC19 +Op 0 0 0 +T0 117 451 197 197 2700 49 M V 20 N"RP10" +T1 68 -436 157 157 2700 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 183 "/fpga2/R_M0_DQ12" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 184 "/fpga2/R_M0_DQ13" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 185 "/fpga2/R_M0_DQ14" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 186 "/fpga2/R_M0_DQ15" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 252 "/sdram/M0_DQ15" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 130 "/fpga2/M0_DQ14" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 251 "/sdram/M0_DQ13" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 129 "/fpga2/M0_DQ12" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE 0402 +Po 61079 35965 900 0 4C755A3C 4C69EB29 ~~ +Li 0402 +Sc 4C69EB29 +AR /4C7BC2A2/4C69E7DD +Op 0 0 0 +At SMD +T0 -20 -307 200 200 900 40 M V 20 N"R19" +T1 0 -150 200 200 900 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 239 "/fpga2/R_M1_UDQS" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 160 "/fpga2/M1_UDQS" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 62429 33098 0 0 4C7558DD 4C69EB27 ~~ +Li 0402 +Sc 4C69EB27 +AR /4C7BC2A2/4C69E92D +Op 0 0 0 +At SMD +T0 -8 326 200 200 0 40 M V 20 N"R20" +T1 0 -150 200 200 0 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 218 "/fpga2/R_M1_CS#" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 270 "/sdram/M1_CS#" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 61024 32283 2700 0 4CDB6EBC 4C69EB25 ~~ +Li 0402 +Sc 4C69EB25 +AR /4C7BC2A2/4C69E7F8 +Op 0 0 0 +At SMD +T0 -645 -11 200 200 2700 40 M V 20 N"R17" +T1 0 -150 200 200 2700 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 217 "/fpga2/R_M1_CKE" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 147 "/fpga2/M1_CKE" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 60701 34567 0 0 4C755A3F 4C69EB23 ~~ +Li 0402 +Sc 4C69EB23 +AR /4C7BC2A2/4C69E7C2 +Op 0 0 0 +At SMD +T0 -8 -351 200 200 0 40 M V 20 N"R18" +T1 0 -150 200 200 0 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 238 "/fpga2/R_M1_UDM" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 159 "/fpga2/M1_UDM" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE R_PACK4-0402 +Po 63063 38004 900 0 4CF99EEE 4C69E3ED ~~ +Li R_PACK4-0402 +Sc 4C69E3ED +AR /4C7BC2A2/4C69E299 +Op 0 0 0 +T0 -748 87 197 197 900 49 M V 20 N"RP8" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 275 "/sdram/M1_DQ15" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 274 "/sdram/M1_DQ14" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 150 "/fpga2/M1_DQ13" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 149 "/fpga2/M1_DQ12" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 223 "/fpga2/R_M1_DQ12" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 224 "/fpga2/R_M1_DQ13" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 225 "/fpga2/R_M1_DQ14" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 226 "/fpga2/R_M1_DQ15" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 62713 36508 900 0 4C69A686 4C69E3EE ~~ +Li R_PACK4-0402 +Sc 4C69E3EE +AR /4C7BC2A2/4C69E3A6 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP9" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 273 "/sdram/M1_DQ11" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 148 "/fpga2/M1_DQ10" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 277 "/sdram/M1_DQ9" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 156 "/fpga2/M1_DQ8" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 233 "/fpga2/R_M1_DQ8" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 234 "/fpga2/R_M1_DQ9" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 221 "/fpga2/R_M1_DQ10" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 222 "/fpga2/R_M1_DQ11" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE 0402 +Po 61020 33370 900 0 4C755B41 4C69E066 ~~ +Li 0402 +Sc 4C69E066 +AR /4C7BC2A2/4C69DF7A +Op 0 0 0 +At SMD +T0 16 342 200 200 900 40 M V 20 N"R16" +T1 0 -150 200 200 900 40 M I 20 N"120" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 269 "/sdram/M1_CLK#" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 268 "/sdram/M1_CLK" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE R_PACK4-0402 +Po 62925 32201 900 0 4C69A686 4C69DCB4 ~~ +Li R_PACK4-0402 +Sc 4C69DCB4 +AR /4C7BC2A2/4C69DC05 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP7" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 263 "/sdram/M1_A12" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 262 "/sdram/M1_A11" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 267 "/sdram/M1_A9" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 266 "/sdram/M1_A8" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 212 "/fpga2/R_M1_A8" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 213 "/fpga2/R_M1_A9" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 204 "/fpga2/R_M1_A11" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 205 "/fpga2/R_M1_A12" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 62929 31173 900 0 4C69A686 4C69DB1A ~~ +Li R_PACK4-0402 +Sc 4C69DB1A +AR /4C7BC2A2/4C69DA8A +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP6" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 265 "/sdram/M1_A7" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 264 "/sdram/M1_A6" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 143 "/fpga2/M1_A5" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 142 "/fpga2/M1_A4" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 208 "/fpga2/R_M1_A4" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 209 "/fpga2/R_M1_A5" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 210 "/fpga2/R_M1_A6" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 211 "/fpga2/R_M1_A7" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 64941 37598 900 0 4CF99EFC 4C69D4B9 ~~ +Li R_PACK4-0402 +Sc 4C69D4B9 +AR /4C7BC2A2/4C69D3A9 +Op 0 0 0 +T0 114 -496 197 197 900 49 M V 20 N"RP5" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 219 "/fpga2/R_M1_DQ0" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 220 "/fpga2/R_M1_DQ1" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 227 "/fpga2/R_M1_DQ2" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 228 "/fpga2/R_M1_DQ3" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 151 "/fpga2/M1_DQ3" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 276 "/sdram/M1_DQ2" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 272 "/sdram/M1_DQ1" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 271 "/sdram/M1_DQ0" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 64949 36327 900 0 4CF99F08 4C69D4B5 ~~ +Li R_PACK4-0402 +Sc 4C69D4B5 +AR /4C7BC2A2/4C69D3A3 +Op 0 0 0 +T0 8 -504 197 197 900 49 M V 20 N"RP4" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 229 "/fpga2/R_M1_DQ4" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 230 "/fpga2/R_M1_DQ5" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 231 "/fpga2/R_M1_DQ6" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 232 "/fpga2/R_M1_DQ7" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 155 "/fpga2/M1_DQ7" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 154 "/fpga2/M1_DQ6" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 153 "/fpga2/M1_DQ5" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 152 "/fpga2/M1_DQ4" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 64969 32563 900 0 4C69A686 4C69D012 ~~ +Li R_PACK4-0402 +Sc 4C69D012 +AR /4C7BC2A2/4C69CEE8 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP2" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 237 "/fpga2/R_M1_RAS#" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 214 "/fpga2/R_M1_BA0" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 215 "/fpga2/R_M1_BA1" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 203 "/fpga2/R_M1_A10" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 261 "/sdram/M1_A10" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 145 "/fpga2/M1_BA1" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 144 "/fpga2/M1_BA0" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 158 "/fpga2/M1_RAS#" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE R_PACK4-0402 +Po 64953 31252 900 0 4C69A686 4C69CDBA ~~ +Li R_PACK4-0402 +Sc 4C69CDBA +AR /4C7BC2A2/4C69C6B2 +Op 0 0 0 +T0 117 451 197 197 900 49 M V 20 N"RP1" +T1 68 -436 157 157 900 39 M I 20 N"R_PACK4" +DS -394 -276 -394 275 59 20 +DS 394 -277 394 276 59 20 +DS -354 0 354 0 59 20 +$PAD +Sh "1" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 201 "/fpga2/R_M1_A0" +Po -295 -177 +$EndPAD +$PAD +Sh "2" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 202 "/fpga2/R_M1_A1" +Po -98 -177 +$EndPAD +$PAD +Sh "3" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 206 "/fpga2/R_M1_A2" +Po 98 -177 +$EndPAD +$PAD +Sh "4" R 118 157 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 207 "/fpga2/R_M1_A3" +Po 295 -177 +$EndPAD +$PAD +Sh "5" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 141 "/fpga2/M1_A3" +Po 295 177 +$EndPAD +$PAD +Sh "6" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 140 "/fpga2/M1_A2" +Po 98 177 +$EndPAD +$PAD +Sh "7" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 139 "/fpga2/M1_A1" +Po -98 177 +$EndPAD +$PAD +Sh "8" R 118 157 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 138 "/fpga2/M1_A0" +Po -295 177 +$EndPAD +$EndMODULE R_PACK4-0402 +$MODULE 0402 +Po 61051 17331 0 15 4CF99D57 4C6969AB ~~ +Li 0402 +Sc 4C6969AB +AR /4C4227FE/4C6969AB +Op 0 0 0 +At SMD +T0 -189 480 200 200 900 40 N V 21 N"C75" +T1 0 150 200 200 0 40 N I 21 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47691 26665 1800 0 4CDB6CD2 4C5D810A ~~ +Li 0402 +Sc 4C5D810A +AR /4C4320F3/4C5D810A +Op 0 0 0 +At SMD +T0 156 299 200 200 1800 40 M V 20 N"L3" +T1 0 -150 200 200 1800 40 M I 20 N"FB" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "/ether/ETH_A1.8V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 13 "/ether/ETH_PLL1.8V" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 48675 25878 1800 0 4CDB6CC1 4C5D80F3 ~~ +Li 0402 +Sc 4C5D80F3 +AR /4C4320F3/4C5D80F3 +Op 0 0 0 +At SMD +T0 533 4 200 200 1800 40 M V 20 N"L1" +T1 0 -150 200 200 1800 40 M I 20 N"FB" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 2 "+1.8V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "/ether/ETH_A1.8V" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 59941 26213 900 0 4CDB6D6F 4C65D681 ~~ +Li 0603 +Sc 4C65D681 +AR /4C4227FE/4C65D681 +Op 0 0 0 +At SMD +T0 16 -354 200 200 900 40 M V 20 N"C74" +T1 0 -150 200 200 900 40 M I 20 N"1uF" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0402 +Po 59965 24547 900 0 4CDB6D66 4C65D67C ~~ +Li 0402 +Sc 4C65D67C +AR /4C4227FE/4C65D67C +Op 0 0 0 +At SMD +T0 19 -315 200 200 900 40 M V 20 N"C73" +T1 0 -150 200 200 900 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 53445 26173 900 0 4CDB6D1D 4C65D661 ~~ +Li 0402 +Sc 4C65D661 +AR /4C4227FE/4C65D661 +Op 0 0 0 +At SMD +T0 19 342 200 200 900 40 M V 20 N"C72" +T1 0 -150 200 200 900 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 50014 35166 1800 0 4CDB6E6A 4C65D2A9 ~~ +Li 0402 +Sc 4C65D2A9 +AR /4C421DD3/4C65D2A9 +Op 0 0 0 +At SMD +T0 18 320 200 200 1800 40 M V 20 N"C70" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 65354 30512 1800 0 4CDB6EAB 4C65D28E ~~ +Li 0402 +Sc 4C65D28E +AR /4C421DD3/4C65D28E +Op 0 0 0 +At SMD +T0 610 -16 200 200 1800 40 M V 20 N"C71" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE SO8E +Po 58516 40232 2700 15 4CDDC03D 4C65A75D ~~ +Li SO8E +Cd module CMS SOJ 8 pins etroit +Kw CMS SOJ +Sc 4C65A75D +AR /4C4227FE/4C65A75D +Op 0 0 0 +At SMD +T0 1181 24 315 315 3600 60 N V 21 N"U8" +T1 0 400 350 350 2700 60 N I 21 N"X25X64MB" +DS -1050 700 -1050 750 50 21 +DS -1050 750 1050 750 50 21 +DS 1050 -750 -1050 -750 50 21 +DS -1050 -750 -1050 700 50 21 +DS -1050 -200 -850 -200 50 21 +DS -850 -200 -850 200 50 21 +DS -850 200 -1050 200 50 21 +DS 1050 -750 1050 750 50 21 +$PAD +Sh "8" R 200 450 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po -750 -1050 +$EndPAD +$PAD +Sh "1" R 200 450 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 105 "/fpga1/PROG_CSO" +Po -750 1050 +$EndPAD +$PAD +Sh "7" R 200 450 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 109 "/fpga1/PROG_MISO3" +Po -250 -1050 +$EndPAD +$PAD +Sh "6" R 200 450 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 104 "/fpga1/PROG_CCLK" +Po 250 -1050 +$EndPAD +$PAD +Sh "5" R 200 450 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 106 "/fpga1/PROG_MISO0" +Po 750 -1050 +$EndPAD +$PAD +Sh "2" R 200 450 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 107 "/fpga1/PROG_MISO1" +Po -250 1050 +$EndPAD +$PAD +Sh "3" R 200 450 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 108 "/fpga1/PROG_MISO2" +Po 250 1050 +$EndPAD +$PAD +Sh "4" R 200 450 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 750 1050 +$EndPAD +$SHAPE3D +Na "smd/cms_so8.wrl" +Sc 0.500000 0.320000 0.500000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SO8E +$MODULE 1206 +Po 48520 39457 1800 15 4CF99E56 4C61D151 ~~ +Li 1206 +Sc 4C61D151 +AR /4C421DD3/4C61D151 +Op 0 0 0 +At SMD +T0 1166 -315 200 200 1800 40 N V 25 N"C33" +T1 0 150 200 200 1800 40 N I 25 N"10uF" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 +$MODULE 0402 +Po 56272 35700 2700 0 4CDB6F4C 4C656AC0 ~~ +Li 0402 +Sc 4C656AC0 +AR /4C7BC2B2/4C656AC0 +Op 0 0 0 +At SMD +T0 485 -19 200 200 3600 40 M V 20 N"C45" +T1 0 -150 200 200 2700 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 1 "+1.2V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 1210 +Po 55165 39594 1800 15 4CDDC037 4C656A80 ~~ +Li 1210 +Sc 4C656A80 +AR /4C7BC2B2/4C656A80 +Op 0 0 0 +At SMD +T0 4 -756 200 200 1800 40 N V 25 N"C39" +T1 0 150 200 200 1800 40 N I 25 N"100uF" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 64610 29496 0 15 4CDB6EAF 4C656BF8 ~~ +Li 1210 +Sc 4C656BF8 +AR /4C7BC2B2/4C656BF8 +Op 0 0 0 +At SMD +T0 563 -669 200 200 0 40 N V 25 N"C40" +T1 0 150 200 200 0 40 N I 25 N"100uF" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 51807 24819 900 15 4CDDC1A3 4C656CB7 ~~ +Li 1210 +Sc 4C656CB7 +AR /4C7BC2B2/4C656CB7 +Op 0 0 0 +At SMD +T0 36 -701 200 200 900 40 N V 25 N"C41" +T1 0 150 200 200 900 40 N I 25 N"100uF" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 61654 39882 0 15 4CDDBFCB 4C656D97 ~~ +Li 1210 +Sc 4C656D97 +AR /4C7BC2B2/4C656D97 +Op 0 0 0 +At SMD +T0 -20 -662 200 200 0 40 N V 25 N"C54" +T1 0 150 200 200 0 40 N I 25 N"100uF" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 52700 39580 1800 15 4CDDC030 4CD36481 ~~ +Li 1210 +Sc 4CD36481 +AR /4C7BC2B2/4C656D43 +Op 0 0 0 +At SMD +T0 19 -747 200 200 1800 40 N V 25 N"C55" +T1 0 150 200 200 1800 40 N I 25 N"100uF" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "VCCO2" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 47000 29400 0 15 4CDDC2D7 4C656CF9 ~~ +Li 1210 +Sc 4C656CF9 +AR /4C7BC2B2/4C656CF9 +Op 0 0 0 +At SMD +T0 -12 -750 200 200 0 40 N V 25 N"C56" +T1 0 150 200 200 0 40 N I 25 N"100uF" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 0805 +Po 54917 39386 1800 0 4CDB6E7C 4C656ABD ~~ +Li 0805 +Sc 4C656ABD +AR /4C7BC2B2/4C656ABD +Op 0 0 0 +At SMD +T0 -284 453 200 200 1800 40 M V 20 N"C42" +T1 0 -150 200 200 1800 40 M I 20 N"4.7uF" +DS -561 -305 -561 305 50 20 +DS -561 305 561 305 50 20 +DS 561 305 561 -305 50 20 +DS 561 -305 -561 -305 50 20 +$PAD +Sh "1" R 275 510 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 1 "+1.2V" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0805 +Po 61043 30421 2700 0 4C756D6C 4C656BF9 ~~ +Li 0805 +Sc 4C656BF9 +AR /4C7BC2B2/4C656BF9 +Op 0 0 0 +At SMD +T0 -328 -484 200 200 2700 40 M V 20 N"C43" +T1 0 -150 200 200 2700 40 M I 20 N"4.7uF" +DS -561 -305 -561 305 50 20 +DS -561 305 561 305 50 20 +DS 561 305 561 -305 50 20 +DS 561 -305 -561 -305 50 20 +$PAD +Sh "1" R 275 510 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0805 +Po 60402 29224 0 15 4CDDC1D9 4C656CB9 ~~ +Li 0805 +Sc 4C656CB9 +AR /4C7BC2B2/4C656CB9 +Op 0 0 0 +At SMD +T0 909 158 200 200 0 40 N V 21 N"C44" +T1 0 150 200 200 0 40 N I 21 N"4.7uF" +DS -561 305 -561 -305 50 21 +DS -561 -305 561 -305 50 21 +DS 561 -305 561 305 50 21 +DS 561 305 -561 305 50 21 +$PAD +Sh "1" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0805 +Po 51358 30382 900 0 4CDB6E17 4C656C16 ~~ +Li 0805 +Sc 4C656C16 +AR /4C7BC2B2/4C656C16 +Op 0 0 0 +At SMD +T0 323 -433 200 200 900 40 M V 20 N"C46" +T1 0 -150 200 200 900 40 M I 20 N"4.7uF" +DS -561 -305 -561 305 50 20 +DS -561 305 561 305 50 20 +DS 561 305 561 -305 50 20 +DS 561 -305 -561 -305 50 20 +$PAD +Sh "1" R 275 510 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0805 +Po 61000 38900 2700 0 4C756BD3 4C656D98 ~~ +Li 0805 +Sc 4C656D98 +AR /4C7BC2B2/4C656D98 +Op 0 0 0 +At SMD +T0 309 480 200 200 2700 40 M V 20 N"C57" +T1 0 -150 200 200 2700 40 M I 20 N"4.7uF" +DS -561 -305 -561 305 50 20 +DS -561 305 561 305 50 20 +DS 561 305 561 -305 50 20 +DS 561 -305 -561 -305 50 20 +$PAD +Sh "1" R 275 510 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0805 +Po 51600 38500 2700 0 4CDB6E70 4C656D44 ~~ +Li 0805 +Sc 4C656D44 +AR /4C7BC2B2/4C656D44 +Op 0 0 0 +At SMD +T0 -323 454 200 200 2700 40 M V 20 N"C58" +T1 0 -150 200 200 2700 40 M I 20 N"4.7uF" +DS -561 -305 -561 305 50 20 +DS -561 305 561 305 50 20 +DS 561 305 561 -305 50 20 +DS 561 -305 -561 -305 50 20 +$PAD +Sh "1" R 275 510 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 307 "VCCO2" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0805 +Po 48945 29921 1800 0 4CDB6E0E 4C656CFA ~~ +Li 0805 +Sc 4C656CFA +AR /4C7BC2B2/4C656CFA +Op 0 0 0 +At SMD +T0 -287 429 200 200 1800 40 M V 20 N"C59" +T1 0 -150 200 200 1800 40 M I 20 N"4.7uF" +DS -561 -305 -561 305 50 20 +DS -561 305 561 305 50 20 +DS 561 305 561 -305 50 20 +DS 561 -305 -561 -305 50 20 +$PAD +Sh "1" R 275 510 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0402 +Po 53732 30142 0 0 4CDB6EDC 4C656CBA ~~ +Li 0402 +Sc 4C656CBA +AR /4C7BC2B2/4C656CBA +Op 0 0 0 +At SMD +T0 24 334 200 200 0 40 M V 20 N"C47" +T1 0 -150 200 200 0 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 56272 33776 2700 0 4CDB6EFC 4C733849 ~~ +Li 0402 +Sc 4C733849 +AR /4C7BC2B2/4C656AC2 +Op 0 0 0 +At SMD +T0 -12 327 200 200 2700 40 M V 20 N"C48" +T1 0 -150 200 200 2700 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 1 "+1.2V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 57610 33035 2250 0 4CDB6EEE 4C656C24 ~~ +Li 0402 +Sc 4C656C24 +AR /4C7BC2B2/4C656C24 +Op 0 0 0 +At SMD +T0 -8 314 200 200 2250 40 M V 20 N"C49" +T1 0 -150 200 200 2250 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2250 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2250 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 56315 30173 0 0 4CDB6EE2 4C656CBB ~~ +Li 0402 +Sc 4C656CBB +AR /4C7BC2B2/4C656CBB +Op 0 0 0 +At SMD +T0 20 343 200 200 0 40 M V 20 N"C50" +T1 0 -150 200 200 0 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 57700 34382 1800 0 4CDB6F2D 4C656C27 ~~ +Li 0402 +Sc 4C656C27 +AR /4C7BC2B2/4C656C27 +Op 0 0 0 +At SMD +T0 -24 311 200 200 1800 40 M V 20 N"C51" +T1 0 -150 200 200 1800 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 56272 32331 2700 0 4CDB6EF3 4C656BFA ~~ +Li 0402 +Sc 4C656BFA +AR /4C7BC2B2/4C656BFA +Op 0 0 0 +At SMD +T0 4 323 200 200 2700 40 M V 20 N"C52" +T1 0 -150 200 200 2700 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 54600 34400 1800 0 4CDB6F16 4C656C49 ~~ +Li 0402 +Sc 4C656C49 +AR /4C7BC2B2/4C656C49 +Op 0 0 0 +At SMD +T0 -18 -328 200 200 1800 40 M V 20 N"C53" +T1 0 -150 200 200 1800 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 60921 37283 0 0 4C756B35 4C656D99 ~~ +Li 0402 +Sc 4C656D99 +AR /4C7BC2B2/4C656D99 +Op 0 0 0 +At SMD +T0 -35 -311 200 200 0 40 M V 20 N"C60" +T1 0 -150 200 200 0 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 56300 38500 2700 0 4CDB6E82 4C656D45 ~~ +Li 0402 +Sc 4C656D45 +AR /4C7BC2B2/4C656D45 +Op 0 0 0 +At SMD +T0 16 320 200 200 2700 40 M V 20 N"C61" +T1 0 -150 200 200 2700 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 307 "VCCO2" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 51800 31200 1800 0 4CDB6E1B 4C656CFB ~~ +Li 0402 +Sc 4C656CFB +AR /4C7BC2B2/4C656CFB +Op 0 0 0 +At SMD +T0 17 -331 200 200 1800 40 M V 20 N"C62" +T1 0 -150 200 200 1800 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 56272 33039 2700 0 4CDB6EF7 4C656D9A ~~ +Li 0402 +Sc 4C656D9A +AR /4C7BC2B2/4C656D9A +Op 0 0 0 +At SMD +T0 -27 339 200 200 2700 40 M V 20 N"C63" +T1 0 -150 200 200 2700 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 53300 38800 0 0 4CDB6E76 4C656D46 ~~ +Li 0402 +Sc 4C656D46 +AR /4C7BC2B2/4C656D46 +Op 0 0 0 +At SMD +T0 598 23 200 200 0 40 M V 20 N"C64" +T1 0 -150 200 200 0 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 307 "VCCO2" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 55146 35110 450 0 4CDB6F3C 4C656CFC ~~ +Li 0402 +Sc 4C656CFC +AR /4C7BC2B2/4C656CFC +Op 0 0 0 +At SMD +T0 -635 17 200 200 450 40 M V 20 N"C65" +T1 0 -150 200 200 450 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 450 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 450 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 58831 34382 1800 0 4C755B47 4C656D9D ~~ +Li 0402 +Sc 4C656D9D +AR /4C7BC2B2/4C656D9D +Op 0 0 0 +At SMD +T0 21 -324 200 200 1800 40 M V 20 N"C66" +T1 0 -150 200 200 1800 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 58900 38900 1800 0 4CDB6E9C 4C656D49 ~~ +Li 0402 +Sc 4C656D49 +AR /4C7BC2B2/4C656D49 +Op 0 0 0 +At SMD +T0 14 294 200 200 1800 40 M V 20 N"C67" +T1 0 -150 200 200 1800 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 307 "VCCO2" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 53169 34358 0 0 4CDB6F11 4C656D08 ~~ +Li 0402 +Sc 4C656D08 +AR /4C7BC2B2/4C656D08 +Op 0 0 0 +At SMD +T0 28 347 200 200 0 40 M V 20 N"C68" +T1 0 -150 200 200 0 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 56300 37402 2700 0 4CDB6E87 4C656D53 ~~ +Li 0402 +Sc 4C656D53 +AR /4C7BC2B2/4C656D53 +Op 0 0 0 +At SMD +T0 -4 312 200 200 2700 40 M V 20 N"C69" +T1 0 -150 200 200 2700 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 307 "VCCO2" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 61571 17795 1800 15 4CF99D6A 4C6552B8 ~~ +Li 0603 +Sc 4C6552B8 +AR /4C5F1EDC/4C6552B8 +Op 0 0 0 +At SMD +T0 -130 370 200 200 1800 40 N V 21 N"V3" +T1 0 150 200 200 1800 40 N I 21 N"V0402MHS03" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 284 "/usb/USBD_D+" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 62528 17791 0 15 4CF99D64 4C6552B9 ~~ +Li 0603 +Sc 4C6552B9 +AR /4C5F1EDC/4C6552B9 +Op 0 0 0 +At SMD +T0 -83 -385 200 200 0 40 N V 21 N"V4" +T1 0 150 200 200 0 40 N I 21 N"V0402MHS03" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 285 "/usb/USBD_D-" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0402 +Po 56854 28346 2700 0 4CDB6D31 4C6552BC ~~ +Li 0402 +Sc 4C6552BC +AR /4C5F1EDC/4C6552BC +Op 0 0 0 +At SMD +T0 -23 330 200 200 2700 40 M V 20 N"C37" +T1 0 -150 200 200 2700 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 60185 17402 2700 15 4CDDC188 4C6552B1 ~~ +Li 0603 +Sc 4C6552B1 +AR /4C5F1EDC/4C6552B1 +Op 0 0 0 +At SMD +T0 232 382 200 200 2700 40 N V 25 N"L7" +T1 0 150 200 200 2700 40 N I 25 N"FB" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 297 "N-000143" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 56803 21843 900 15 4C892DF6 4C63F252 ~~ +Li 0603 +Sc 4C63F252 +AR /4C5F1EDC/4C63F252 +Op 0 0 0 +At SMD +T0 -129 -366 200 200 900 40 N V 21 N"L4" +T1 0 150 200 200 900 40 N I 21 N"FB" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 303 "N-000150" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 302 "N-000149" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 54921 20791 2700 15 4C7D4200 4C63F248 ~~ +Li 0603 +Sc 4C63F248 +AR /4C5F1EDC/4C63F248 +Op 0 0 0 +At SMD +T0 256 406 200 200 2700 40 N V 21 N"L5" +T1 0 150 200 200 2700 40 N I 21 N"FB" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 296 "N-000142" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0402 +Po 62228 34689 0 0 4C755799 4C61CE30 ~~ +Li 0402 +Sc 4C61CE30 +AR /4C421DD3/4C61CE30 +Op 0 0 0 +At SMD +T0 0 338 200 200 0 40 M V 20 N"R14" +T1 0 -150 200 200 0 40 M I 20 N"1K_1%" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 279 "/sdram/M1_VREF" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 63197 29799 1800 15 4CDB6EB3 4C61CFA0 ~~ +Li 0603 +Sc 4C61CFA0 +AR /4C421DD3/4C61CFA0 +Op 0 0 0 +At SMD +T0 209 370 200 200 1800 40 N V 25 N"C27" +T1 0 150 200 200 1800 40 N I 25 N"1uF" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 47299 30531 0 0 4CDB6E21 4C61CF2F ~~ +Li 0603 +Sc 4C61CF2F +AR /4C421DD3/4C61CF2F +Op 0 0 0 +At SMD +T0 -23 402 200 200 0 40 M V 20 N"C21" +T1 0 -150 200 200 0 40 M I 20 N"1uF" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0402 +Po 62193 35850 0 0 4C7559C6 4C61CFA5 ~~ +Li 0402 +Sc 4C61CFA5 +AR /4C421DD3/4C61CFA5 +Op 0 0 0 +At SMD +T0 626 36 200 200 0 40 M V 20 N"C28" +T1 0 -150 200 200 0 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 62193 37374 0 0 4C7559CC 4C61CFA4 ~~ +Li 0402 +Sc 4C61CFA4 +AR /4C421DD3/4C61CFA4 +Op 0 0 0 +At SMD +T0 622 16 200 200 0 40 M V 20 N"C29" +T1 0 -150 200 200 0 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 65331 38602 1800 0 4C755996 4C61CFA3 ~~ +Li 0402 +Sc 4C61CFA3 +AR /4C421DD3/4C61CFA3 +Op 0 0 0 +At SMD +T0 611 -16 200 200 1800 40 M V 20 N"C31" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 66016 34874 2700 0 4CF99F15 4C61CFA2 ~~ +Li 0402 +Sc 4C61CFA2 +AR /4C421DD3/4C61CFA2 +Op 0 0 0 +At SMD +T0 -20 -386 200 200 2700 40 M V 20 N"C30" +T1 0 -150 200 200 2700 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 65327 38988 1800 0 4C75599C 4C61CFA1 ~~ +Li 0402 +Sc 4C61CFA1 +AR /4C421DD3/4C61CFA1 +Op 0 0 0 +At SMD +T0 603 -36 200 200 1800 40 M V 20 N"C32" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 46854 35535 0 0 4CDB6E60 4C61CF27 ~~ +Li 0402 +Sc 4C61CF27 +AR /4C421DD3/4C61CF27 +Op 0 0 0 +At SMD +T0 -622 12 200 200 0 40 M V 20 N"C26" +T1 0 -150 200 200 0 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47008 37071 0 0 4CDB6E65 4C61CF17 ~~ +Li 0402 +Sc 4C61CF17 +AR /4C421DD3/4C61CF17 +Op 0 0 0 +At SMD +T0 -673 23 200 200 0 40 M V 20 N"C24" +T1 0 -150 200 200 0 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 50217 30413 1800 0 4CDB6E11 4C61CF16 ~~ +Li 0402 +Sc 4C61CF16 +AR /4C421DD3/4C61CF16 +Op 0 0 0 +At SMD +T0 -3 322 200 200 1800 40 M V 20 N"C25" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 50276 39079 1800 0 4C6EF558 4C61CEF7 ~~ +Li 0402 +Sc 4C61CEF7 +AR /4C421DD3/4C61CEF7 +Op 0 0 0 +At SMD +T0 612 -27 200 200 1800 40 M V 20 N"C23" +T1 0 -150 200 200 1800 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 50283 38701 1800 0 4C6EF554 4C61CEB9 ~~ +Li 0402 +Sc 4C61CEB9 +AR /4C421DD3/4C61CEB9 +Op 0 0 0 +At SMD +T0 602 -11 200 200 1800 40 M V 20 N"C22" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 62220 34110 1800 0 4C7557C2 4C61CE31 ~~ +Li 0402 +Sc 4C61CE31 +AR /4C421DD3/4C61CE31 +Op 0 0 0 +At SMD +T0 4 303 200 200 1800 40 M V 20 N"R13" +T1 0 -150 200 200 1800 40 M I 20 N"1K_1%" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 279 "/sdram/M1_VREF" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47441 34646 0 0 4CDB6E56 4C61CDB5 ~~ +Li 0402 +Sc 4C61CDB5 +AR /4C421DD3/4C61CDB5 +Op 0 0 0 +At SMD +T0 -646 35 200 200 0 40 M V 20 N"R12" +T1 0 -150 200 200 0 40 M I 20 N"1K_1%" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 259 "/sdram/M0_VREF" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47441 33169 1800 0 4CDB6E46 4C61CD4A ~~ +Li 0402 +Sc 4C61CD4A +AR /4C421DD3/4C61CD4A +Op 0 0 0 +At SMD +T0 654 -20 200 200 1800 40 M V 20 N"R11" +T1 0 -150 200 200 1800 40 M I 20 N"1K_1%" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 259 "/sdram/M0_VREF" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 62902 34110 0 0 4C7557A3 4C61CCE3 ~~ +Li 0402 +Sc 4C61CCE3 +AR /4C421DD3/4C61CCE3 +Op 0 0 0 +At SMD +T0 630 3 200 200 0 40 M V 20 N"C19" +T1 0 -150 200 200 0 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 279 "/sdram/M1_VREF" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 62898 34689 1800 0 4C75579D 4C61CCE2 ~~ +Li 0402 +Sc 4C61CCE2 +AR /4C421DD3/4C61CCE2 +Op 0 0 0 +At SMD +T0 -611 -47 200 200 1800 40 M V 20 N"C20" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 279 "/sdram/M1_VREF" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47441 34154 0 0 4CDB6E4D 4C61CC96 ~~ +Li 0402 +Sc 4C61CC96 +AR /4C421DD3/4C61CC96 +Op 0 0 0 +At SMD +T0 -658 39 200 200 0 40 M V 20 N"C18" +T1 0 -150 200 200 0 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 259 "/sdram/M0_VREF" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47441 33661 1800 0 4CDB6E41 4C61CC73 ~~ +Li 0402 +Sc 4C61CC73 +AR /4C421DD3/4C61CC73 +Op 0 0 0 +At SMD +T0 642 -32 200 200 1800 40 M V 20 N"C17" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 259 "/sdram/M0_VREF" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE USB-48204 +Po 56799 18303 1800 15 4C7D3F62 4C71CC3A ~~ +Li USB-48204 +Sc 4C71CC3A +AR /4C5F1EDC/4C5F23DD +Op 0 0 0 +T0 1393 -3162 157 157 1800 20 N V 21 N"J5" +T1 0 118 118 118 3600 20 N I 21 N"USB-48204-0001" +DS -1499 5299 -1704 5299 60 21 +DS -1704 5299 -1704 5178 60 21 +DS -1704 5178 -1502 5178 60 21 +DS 1500 5298 1708 5298 60 21 +DS 1708 5298 1707 5180 60 21 +DS 1707 5180 1499 5181 60 21 +DS -1500 -3000 -1500 5300 60 21 +DS -1500 -3000 1500 -3000 60 21 +DS 1500 -3000 1500 5300 60 21 +DS -1500 5300 1500 5300 60 21 +$PAD +Sh "1" R 470 470 0 0 1800 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 302 "N-000149" +Po 0 -2362 +$EndPAD +$PAD +Sh "2" C 470 470 0 0 1800 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 281 "/usb/USBA_D-" +Po 0 -1575 +$EndPAD +$PAD +Sh "3" C 470 470 0 0 1800 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 280 "/usb/USBA_D+" +Po 0 -787 +$EndPAD +$PAD +Sh "4" C 470 470 0 0 1800 +Dr 360 0 0 +At STD N 0CC0FFFF +Ne 296 "N-000142" +Po 0 0 +$EndPAD +$PAD +Sh "S1" C 670 670 0 0 1800 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 291 "/usb/USB_CASE_HOST" +Po 1077 287 +$EndPAD +$PAD +Sh "S2" C 670 670 0 0 1800 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 291 "/usb/USB_CASE_HOST" +Po -1077 287 +$EndPAD +$PAD +Sh "S3" C 670 670 0 0 1800 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 291 "/usb/USB_CASE_HOST" +Po 1077 -2468 +$EndPAD +$PAD +Sh "S4" C 670 670 0 0 1800 +Dr 532 0 0 +At STD N 0CC0FFFF +Ne 291 "/usb/USB_CASE_HOST" +Po -1077 -2468 +$EndPAD +$EndMODULE USB-48204 +$MODULE 1210 +Po 57378 22894 0 15 4C7D3F78 4C5F2B55 ~~ +Li 1210 +Sc 4C5F2B55 +AR /4C5F1EDC/4C5F2B55 +Op 0 0 0 +At SMD +T0 -972 -394 200 200 900 40 N V 25 N"F1" +T1 0 150 200 200 0 40 N I 25 N"MICROSMD075F" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 303 "N-000150" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 5 "+5V" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 0603 +Po 47209 23642 0 15 4CDDC207 4CDDBD18 ~~ +Li 0603 +Sc 4CDDBD18 +AR /4C4320F3/4C5D7F9F +Op 0 0 0 +At SMD +T0 665 31 200 200 0 40 N V 25 N"C1" +T1 0 150 200 200 0 40 N I 25 N"1uF" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 46350 24551 900 15 4CDDC203 4C5D7FA5 ~~ +Li 0603 +Sc 4C5D7FA5 +AR /4C4320F3/4C5D7FA5 +Op 0 0 0 +At SMD +T0 -689 -23 200 200 900 40 N V 25 N"C7" +T1 0 150 200 200 900 40 N I 25 N"1uF" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "/ether/ETH_A3.3V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 54980 25870 1800 0 4CDB6D4A 4C5F2033 ~~ +Li 0603 +Sc 4C5F2033 +AR /4C5F1EDC/4C5F2033 +Op 0 0 0 +At SMD +T0 771 -126 200 200 1800 40 M V 20 N"C13" +T1 0 -150 200 200 1800 40 M I 20 N"1uF" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 55280 22240 1800 0 4C7D4082 4C5F2CA7 ~~ +Li 0603 +Sc 4C5F2CA7 +AR /4C5F1EDC/4C5F2CA7 +Op 0 0 0 +At SMD +T0 666 -51 200 200 1800 40 M V 20 N"V1" +T1 0 -150 200 200 1800 40 M I 20 N"V0402MHS03" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 280 "/usb/USBA_D+" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 56236 22240 0 0 4C7D4088 4C5F2CA3 ~~ +Li 0603 +Sc 4C5F2CA3 +AR /4C5F1EDC/4C5F2CA3 +Op 0 0 0 +At SMD +T0 658 20 200 200 0 40 M V 20 N"V2" +T1 0 -150 200 200 0 40 M I 20 N"V0402MHS03" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 281 "/usb/USBA_D-" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0402 +Po 49754 27461 1800 0 4CDB6D06 4C5D80ED ~~ +Li 0402 +Sc 4C5D80ED +AR /4C4320F3/4C5D80ED +Op 0 0 0 +At SMD +T0 41 319 200 200 1800 40 M V 20 N"C2" +T1 0 -150 200 200 1800 40 M I 20 N"1uF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 2 "+1.8V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 46965 23445 0 0 4CDB6C94 4C5D7FA1 ~~ +Li 0402 +Sc 4C5D7FA1 +AR /4C4320F3/4C5D7FA1 +Op 0 0 0 +At SMD +T0 523 4 200 200 0 40 M V 20 N"C3" +T1 0 -150 200 200 0 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 48675 26272 1800 0 4CDB6CC5 4C5D80F0 ~~ +Li 0402 +Sc 4C5D80F0 +AR /4C4320F3/4C5D80F0 +Op 0 0 0 +At SMD +T0 533 -11 200 200 1800 40 M V 20 N"C4" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 2 "+1.8V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 46953 23858 0 0 4CDB6C98 4C5D7FA3 ~~ +Li 0402 +Sc 4C5D7FA3 +AR /4C4320F3/4C5D7FA3 +Op 0 0 0 +At SMD +T0 523 28 200 200 0 40 M V 20 N"C5" +T1 0 -150 200 200 0 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 48675 25484 0 0 4CDB6CBD 4C5D8104 ~~ +Li 0402 +Sc 4C5D8104 +AR /4C4320F3/4C5D8104 +Op 0 0 0 +At SMD +T0 -545 12 200 200 0 40 M V 20 N"C6" +T1 0 -150 200 200 0 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 6 "/ether/ETH_A1.8V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47490 25089 900 0 4CDDC3B4 4C5D7FA7 ~~ +Li 0402 +Sc 4C5D7FA7 +AR /4C4320F3/4C5D7FA7 +Op 0 0 0 +At SMD +T0 140 392 200 200 1800 40 M V 20 N"C8" +T1 0 -150 200 200 900 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 7 "/ether/ETH_A3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47691 27059 0 0 4CDB6CCF 4C5D8114 ~~ +Li 0402 +Sc 4C5D8114 +AR /4C4320F3/4C5D8114 +Op 0 0 0 +At SMD +T0 -140 339 200 200 0 40 M V 20 N"C9" +T1 0 -150 200 200 0 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 13 "/ether/ETH_PLL1.8V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 49659 25484 1800 0 4CDDC39B 4C5D7E41 ~~ +Li 0402 +Sc 4C5D7E41 +AR /4C4320F3/4C5D7E41 +Op 0 0 0 +At SMD +T0 -187 -319 200 200 1800 40 M V 20 N"C10" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 48675 27453 1800 0 4CDB6CFF 4C5D7E43 ~~ +Li 0402 +Sc 4C5D7E43 +AR /4C4320F3/4C5D7E43 +Op 0 0 0 +At SMD +T0 -34 343 200 200 1800 40 M V 20 N"C11" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47185 27878 1800 0 4CDB6D0C 4C5D7F39 ~~ +Li 0402 +Sc 4C5D7F39 +AR /4C4320F3/4C5D7F39 +Op 0 0 0 +At SMD +T0 16 -342 200 200 1800 40 M V 20 N"R1" +T1 0 -150 200 200 1800 40 M I 20 N"4.7K" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 12 "/ether/ETH_MDIO" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47043 25087 900 0 4CDDC3AB 4C5D7ECF ~~ +Li 0402 +Sc 4C5D7ECF +AR /4C4320F3/4C5D7ECF +Op 0 0 0 +At SMD +T0 130 -393 200 200 1800 40 M V 20 N"R2" +T1 0 -150 200 200 900 40 M I 20 N"6.65K" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 295 "N-000133" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 52988 20272 1800 0 4CDB6C77 4C5D7AFE ~~ +Li 0402 +Sc 4C5D7AFE +AR /4C4320F3/4C5D7AFE +Op 0 0 0 +At SMD +T0 -516 0 200 200 1800 40 M V 20 N"R3" +T1 0 -150 200 200 1800 40 M I 20 N"49.9" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 21 "/ether/MAG_TX+" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 52988 20863 1800 0 4CDB6C7B 4C5D7AFC ~~ +Li 0402 +Sc 4C5D7AFC +AR /4C4320F3/4C5D7AFC +Op 0 0 0 +At SMD +T0 -532 -3 200 200 1800 40 M V 20 N"R4" +T1 0 -150 200 200 1800 40 M I 20 N"49.9" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 22 "/ether/MAG_TX-" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47957 19858 0 0 4CF99F5E 4C5D7AF7 ~~ +Li 0402 +Sc 4C5D7AF7 +AR /4C4320F3/4C5D7AF7 +Op 0 0 0 +At SMD +T0 -4 -342 200 200 0 40 M V 20 N"R5" +T1 0 -150 200 200 0 40 M I 20 N"49.9" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 18 "/ether/MAG_RX+" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 47279 20863 0 0 4CDB6C85 4C5D7AF9 ~~ +Li 0402 +Sc 4C5D7AF9 +AR /4C4320F3/4C5D7AF9 +Op 0 0 0 +At SMD +T0 -523 35 200 200 0 40 M V 20 N"R6" +T1 0 -150 200 200 0 40 M I 20 N"49.9" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 19 "/ether/MAG_RX-" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 50031 24130 1800 0 4CDB6C8B 4C5D719D ~~ +Li 0402 +Sc 4C5D719D +AR /4C4320F3/4C5D719D +Op 0 0 0 +At SMD +T0 0 315 200 200 1800 40 M V 20 N"R7" +T1 0 -150 200 200 1800 40 M I 20 N"220" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 294 "N-000121" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 10 "/ether/ETH_LED0" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 49065 24124 0 0 4CDB6C8F 4C6D06C7 ~~ +Li 0402 +Sc 4C6D06C7 +AR /4C4320F3/4C5D71DB +Op 0 0 0 +At SMD +T0 14 -325 200 200 0 40 M V 20 N"R8" +T1 0 -150 200 200 0 40 M I 20 N"220" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 293 "N-000120" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 11 "/ether/ETH_LED1" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE TSOP-66 +Po 48819 34646 900 15 4CF99E4F 4C609B99 ~~ +Li TSOP-66 +Sc 4C609B99 +AR /4C421DD3/4C609B99 +Op 0 0 0 +At SMD +T0 -4508 2197 200 200 900 40 N V 25 N"U2" +T1 0 150 200 200 900 40 N I 25 N"MT46V32M16TG" +DC -4094 1881 -4094 1822 39 21 +DS 4350 -1968 4350 1968 39 21 +DS 4350 1968 -4350 1968 39 21 +DS -4350 1968 -4350 -1968 39 21 +DS -4350 -1968 4350 -1968 39 21 +$PAD +Sh "1" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -4094 2176 +$EndPAD +$PAD +Sh "2" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 126 "/fpga2/M0_DQ0" +Po -3838 2176 +$EndPAD +$PAD +Sh "3" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -3582 2176 +$EndPAD +$PAD +Sh "4" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 250 "/sdram/M0_DQ1" +Po -3326 2176 +$EndPAD +$PAD +Sh "5" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 131 "/fpga2/M0_DQ2" +Po -3070 2176 +$EndPAD +$PAD +Sh "6" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2814 2176 +$EndPAD +$PAD +Sh "7" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 132 "/fpga2/M0_DQ3" +Po -2558 2176 +$EndPAD +$PAD +Sh "8" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 253 "/sdram/M0_DQ4" +Po -2303 2176 +$EndPAD +$PAD +Sh "9" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2047 2176 +$EndPAD +$PAD +Sh "10" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 254 "/sdram/M0_DQ5" +Po -1791 2176 +$EndPAD +$PAD +Sh "11" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 255 "/sdram/M0_DQ6" +Po -1535 2176 +$EndPAD +$PAD +Sh "12" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -1279 2176 +$EndPAD +$PAD +Sh "13" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 256 "/sdram/M0_DQ7" +Po -1023 2176 +$EndPAD +$PAD +Sh "14" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -767 2176 +$EndPAD +$PAD +Sh "15" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -511 2176 +$EndPAD +$PAD +Sh "16" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 134 "/fpga2/M0_LDQS" +Po -255 2176 +$EndPAD +$PAD +Sh "17" R 136 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 2176 +$EndPAD +$PAD +Sh "18" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 255 2176 +$EndPAD +$PAD +Sh "19" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 511 2176 +$EndPAD +$PAD +Sh "20" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 258 "/sdram/M0_LDM" +Po 767 2176 +$EndPAD +$PAD +Sh "21" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 260 "/sdram/M0_WE#" +Po 1023 2176 +$EndPAD +$PAD +Sh "22" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 248 "/sdram/M0_CAS#" +Po 1279 2176 +$EndPAD +$PAD +Sh "23" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 135 "/fpga2/M0_RAS#" +Po 1535 2176 +$EndPAD +$PAD +Sh "24" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 1791 2176 +$EndPAD +$PAD +Sh "25" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2047 2176 +$EndPAD +$PAD +Sh "26" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 247 "/sdram/M0_BA0" +Po 2302 2176 +$EndPAD +$PAD +Sh "27" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 123 "/fpga2/M0_BA1" +Po 2558 2176 +$EndPAD +$PAD +Sh "28" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 113 "/fpga2/M0_A10" +Po 2814 2176 +$EndPAD +$PAD +Sh "29" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 245 "/sdram/M0_A0" +Po 3070 2176 +$EndPAD +$PAD +Sh "30" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 112 "/fpga2/M0_A1" +Po 3326 2176 +$EndPAD +$PAD +Sh "31" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 116 "/fpga2/M0_A2" +Po 3582 2176 +$EndPAD +$PAD +Sh "32" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 117 "/fpga2/M0_A3" +Po 3838 2176 +$EndPAD +$PAD +Sh "33" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 4094 2176 +$EndPAD +$PAD +Sh "34" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 4094 -2176 +$EndPAD +$PAD +Sh "35" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 246 "/sdram/M0_A4" +Po 3838 -2176 +$EndPAD +$PAD +Sh "36" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 118 "/fpga2/M0_A5" +Po 3582 -2176 +$EndPAD +$PAD +Sh "37" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 119 "/fpga2/M0_A6" +Po 3326 -2176 +$EndPAD +$PAD +Sh "38" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 120 "/fpga2/M0_A7" +Po 3070 -2176 +$EndPAD +$PAD +Sh "39" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 121 "/fpga2/M0_A8" +Po 2814 -2176 +$EndPAD +$PAD +Sh "40" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 122 "/fpga2/M0_A9" +Po 2558 -2176 +$EndPAD +$PAD +Sh "41" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 114 "/fpga2/M0_A11" +Po 2303 -2176 +$EndPAD +$PAD +Sh "42" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 115 "/fpga2/M0_A12" +Po 2047 -2176 +$EndPAD +$PAD +Sh "43" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1791 -2176 +$EndPAD +$PAD +Sh "44" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 249 "/sdram/M0_CLK#" +Po 1535 -2176 +$EndPAD +$PAD +Sh "45" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 124 "/fpga2/M0_CKE" +Po 1279 -2176 +$EndPAD +$PAD +Sh "46" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 125 "/fpga2/M0_CLK" +Po 1023 -2176 +$EndPAD +$PAD +Sh "47" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 136 "/fpga2/M0_UDM" +Po 767 -2176 +$EndPAD +$PAD +Sh "48" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 511 -2176 +$EndPAD +$PAD +Sh "49" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 259 "/sdram/M0_VREF" +Po 255 -2176 +$EndPAD +$PAD +Sh "50" R 136 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 -2176 +$EndPAD +$PAD +Sh "51" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 137 "/fpga2/M0_UDQS" +Po -255 -2176 +$EndPAD +$PAD +Sh "52" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -511 -2176 +$EndPAD +$PAD +Sh "53" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -767 -2176 +$EndPAD +$PAD +Sh "54" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 257 "/sdram/M0_DQ8" +Po -1023 -2176 +$EndPAD +$PAD +Sh "55" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -1279 -2176 +$EndPAD +$PAD +Sh "56" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 133 "/fpga2/M0_DQ9" +Po -1535 -2176 +$EndPAD +$PAD +Sh "57" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 127 "/fpga2/M0_DQ10" +Po -1791 -2176 +$EndPAD +$PAD +Sh "58" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2047 -2176 +$EndPAD +$PAD +Sh "59" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 128 "/fpga2/M0_DQ11" +Po -2303 -2176 +$EndPAD +$PAD +Sh "60" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 129 "/fpga2/M0_DQ12" +Po -2558 -2176 +$EndPAD +$PAD +Sh "61" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2814 -2176 +$EndPAD +$PAD +Sh "62" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 251 "/sdram/M0_DQ13" +Po -3070 -2176 +$EndPAD +$PAD +Sh "63" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 130 "/fpga2/M0_DQ14" +Po -3326 -2176 +$EndPAD +$PAD +Sh "64" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -3582 -2176 +$EndPAD +$PAD +Sh "65" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 252 "/sdram/M0_DQ15" +Po -3838 -2176 +$EndPAD +$PAD +Sh "66" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -4094 -2176 +$EndPAD +$EndMODULE TSOP-66 +$MODULE TSOP-66 +Po 63780 34646 900 15 4CF99E35 4C609C8E ~~ +Li TSOP-66 +Sc 4C609C8E +AR /4C421DD3/4C609C8E +Op 0 0 0 +At SMD +T0 -4504 2255 200 200 900 40 N V 25 N"U3" +T1 0 150 200 200 900 40 N I 25 N"MT46V32M16TG" +DC -4094 1881 -4094 1822 39 21 +DS 4350 -1968 4350 1968 39 21 +DS 4350 1968 -4350 1968 39 21 +DS -4350 1968 -4350 -1968 39 21 +DS -4350 -1968 4350 -1968 39 21 +$PAD +Sh "1" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -4094 2176 +$EndPAD +$PAD +Sh "2" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 271 "/sdram/M1_DQ0" +Po -3838 2176 +$EndPAD +$PAD +Sh "3" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -3582 2176 +$EndPAD +$PAD +Sh "4" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 272 "/sdram/M1_DQ1" +Po -3326 2176 +$EndPAD +$PAD +Sh "5" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 276 "/sdram/M1_DQ2" +Po -3070 2176 +$EndPAD +$PAD +Sh "6" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2814 2176 +$EndPAD +$PAD +Sh "7" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 151 "/fpga2/M1_DQ3" +Po -2558 2176 +$EndPAD +$PAD +Sh "8" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 152 "/fpga2/M1_DQ4" +Po -2303 2176 +$EndPAD +$PAD +Sh "9" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2047 2176 +$EndPAD +$PAD +Sh "10" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 153 "/fpga2/M1_DQ5" +Po -1791 2176 +$EndPAD +$PAD +Sh "11" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 154 "/fpga2/M1_DQ6" +Po -1535 2176 +$EndPAD +$PAD +Sh "12" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -1279 2176 +$EndPAD +$PAD +Sh "13" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 155 "/fpga2/M1_DQ7" +Po -1023 2176 +$EndPAD +$PAD +Sh "14" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -767 2176 +$EndPAD +$PAD +Sh "15" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -511 2176 +$EndPAD +$PAD +Sh "16" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 157 "/fpga2/M1_LDQS" +Po -255 2176 +$EndPAD +$PAD +Sh "17" R 136 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 2176 +$EndPAD +$PAD +Sh "18" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 255 2176 +$EndPAD +$PAD +Sh "19" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 511 2176 +$EndPAD +$PAD +Sh "20" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 278 "/sdram/M1_LDM" +Po 767 2176 +$EndPAD +$PAD +Sh "21" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 161 "/fpga2/M1_WE#" +Po 1023 2176 +$EndPAD +$PAD +Sh "22" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 146 "/fpga2/M1_CAS#" +Po 1279 2176 +$EndPAD +$PAD +Sh "23" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 158 "/fpga2/M1_RAS#" +Po 1535 2176 +$EndPAD +$PAD +Sh "24" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 270 "/sdram/M1_CS#" +Po 1791 2176 +$EndPAD +$PAD +Sh "25" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2047 2176 +$EndPAD +$PAD +Sh "26" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 144 "/fpga2/M1_BA0" +Po 2302 2176 +$EndPAD +$PAD +Sh "27" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 145 "/fpga2/M1_BA1" +Po 2558 2176 +$EndPAD +$PAD +Sh "28" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 261 "/sdram/M1_A10" +Po 2814 2176 +$EndPAD +$PAD +Sh "29" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 138 "/fpga2/M1_A0" +Po 3070 2176 +$EndPAD +$PAD +Sh "30" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 139 "/fpga2/M1_A1" +Po 3326 2176 +$EndPAD +$PAD +Sh "31" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 140 "/fpga2/M1_A2" +Po 3582 2176 +$EndPAD +$PAD +Sh "32" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 141 "/fpga2/M1_A3" +Po 3838 2176 +$EndPAD +$PAD +Sh "33" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po 4094 2176 +$EndPAD +$PAD +Sh "34" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 4094 -2176 +$EndPAD +$PAD +Sh "35" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 142 "/fpga2/M1_A4" +Po 3838 -2176 +$EndPAD +$PAD +Sh "36" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 143 "/fpga2/M1_A5" +Po 3582 -2176 +$EndPAD +$PAD +Sh "37" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 264 "/sdram/M1_A6" +Po 3326 -2176 +$EndPAD +$PAD +Sh "38" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 265 "/sdram/M1_A7" +Po 3070 -2176 +$EndPAD +$PAD +Sh "39" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 266 "/sdram/M1_A8" +Po 2814 -2176 +$EndPAD +$PAD +Sh "40" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 267 "/sdram/M1_A9" +Po 2558 -2176 +$EndPAD +$PAD +Sh "41" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 262 "/sdram/M1_A11" +Po 2303 -2176 +$EndPAD +$PAD +Sh "42" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 263 "/sdram/M1_A12" +Po 2047 -2176 +$EndPAD +$PAD +Sh "43" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1791 -2176 +$EndPAD +$PAD +Sh "44" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 269 "/sdram/M1_CLK#" +Po 1535 -2176 +$EndPAD +$PAD +Sh "45" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 147 "/fpga2/M1_CKE" +Po 1279 -2176 +$EndPAD +$PAD +Sh "46" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 268 "/sdram/M1_CLK" +Po 1023 -2176 +$EndPAD +$PAD +Sh "47" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 159 "/fpga2/M1_UDM" +Po 767 -2176 +$EndPAD +$PAD +Sh "48" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 511 -2176 +$EndPAD +$PAD +Sh "49" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 279 "/sdram/M1_VREF" +Po 255 -2176 +$EndPAD +$PAD +Sh "50" R 136 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 -2176 +$EndPAD +$PAD +Sh "51" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 160 "/fpga2/M1_UDQS" +Po -255 -2176 +$EndPAD +$PAD +Sh "52" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -511 -2176 +$EndPAD +$PAD +Sh "53" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -767 -2176 +$EndPAD +$PAD +Sh "54" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 156 "/fpga2/M1_DQ8" +Po -1023 -2176 +$EndPAD +$PAD +Sh "55" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -1279 -2176 +$EndPAD +$PAD +Sh "56" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 277 "/sdram/M1_DQ9" +Po -1535 -2176 +$EndPAD +$PAD +Sh "57" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 148 "/fpga2/M1_DQ10" +Po -1791 -2176 +$EndPAD +$PAD +Sh "58" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -2047 -2176 +$EndPAD +$PAD +Sh "59" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 273 "/sdram/M1_DQ11" +Po -2303 -2176 +$EndPAD +$PAD +Sh "60" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 149 "/fpga2/M1_DQ12" +Po -2558 -2176 +$EndPAD +$PAD +Sh "61" R 137 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -2814 -2176 +$EndPAD +$PAD +Sh "62" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 150 "/fpga2/M1_DQ13" +Po -3070 -2176 +$EndPAD +$PAD +Sh "63" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 274 "/sdram/M1_DQ14" +Po -3326 -2176 +$EndPAD +$PAD +Sh "64" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -3582 -2176 +$EndPAD +$PAD +Sh "65" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 275 "/sdram/M1_DQ15" +Po -3838 -2176 +$EndPAD +$PAD +Sh "66" R 138 275 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -4094 -2176 +$EndPAD +$EndMODULE TSOP-66 +$MODULE SD-48025 +Po 50224 17323 1800 15 00000000 4C704BE8 ~~ +Li SD-48025 +Sc 4C704BE8 +AR /4C4320F3/4C5D6F5A +Op 0 0 0 +T0 527 -694 157 157 1800 20 N V 21 N"J4" +T1 0 118 118 118 0 20 N I 21 N"RJ45-48025" +DS -3700 -5800 -3700 4300 60 21 +DS -3700 -5800 3700 -5800 60 21 +DS 3700 -5800 3700 4300 60 21 +DS -3700 4300 3700 4300 60 21 +$PAD +Sh "13" C 1646 1646 0 0 1800 +Dr 1252 0 0 +At STD N 0CC0FFFF +Ne 20 "/ether/MAG_SHIELD" +Po 2250 0 +$EndPAD +$PAD +Sh "13" C 984 984 0 0 1800 +Dr 640 0 0 +At STD N 0CC0FFFF +Ne 20 "/ether/MAG_SHIELD" +Po 3100 -1200 +$EndPAD +$PAD +Sh "14" C 1646 1646 0 0 1800 +Dr 1252 0 0 +At STD N 0CC0FFFF +Ne 20 "/ether/MAG_SHIELD" +Po -2250 0 +$EndPAD +$PAD +Sh "14" C 984 984 0 0 1800 +Dr 640 0 0 +At STD N 0CC0FFFF +Ne 20 "/ether/MAG_SHIELD" +Po -3100 -1200 +$EndPAD +$PAD +Sh "1" R 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 21 "/ether/MAG_TX+" +Po -1750 -2500 +$EndPAD +$PAD +Sh "3" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 4 "+3.3V" +Po -750 -2500 +$EndPAD +$PAD +Sh "5" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 292 "GND" +Po 250 -2500 +$EndPAD +$PAD +Sh "7" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 18 "/ether/MAG_RX+" +Po 1250 -2500 +$EndPAD +$PAD +Sh "2" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 22 "/ether/MAG_TX-" +Po -1250 -3500 +$EndPAD +$PAD +Sh "4" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 292 "GND" +Po -250 -3500 +$EndPAD +$PAD +Sh "6" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 4 "+3.3V" +Po 750 -3500 +$EndPAD +$PAD +Sh "8" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 19 "/ether/MAG_RX-" +Po 1750 -3500 +$EndPAD +$PAD +Sh "9" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 4 "+3.3V" +Po -2150 -5400 +$EndPAD +$PAD +Sh "10" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 294 "N-000121" +Po -1150 -5400 +$EndPAD +$PAD +Sh "11" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 4 "+3.3V" +Po 1150 -5400 +$EndPAD +$PAD +Sh "12" C 540 540 0 0 1800 +Dr 350 0 0 +At STD N 0CC0FFFF +Ne 293 "N-000120" +Po 2150 -5400 +$EndPAD +$EndMODULE SD-48025 +$MODULE MICROSD-500901 +Po 62024 16291 0 0 4CDDC503 4B76F5E2 ~~ +Li MICROSD-500901 +Sc 4B76F5E2 +AR /4C4227FE/4B76F5E2 +Op 0 0 0 +T0 3409 1099 394 394 0 39 M V 20 N"J1" +T1 0 -118 118 118 1800 20 M I 20 N"MICROSD" +DS -2709 -1675 -2709 507 60 20 +DS -2707 -3095 -2707 -2747 60 20 +DS 2709 -1699 2709 500 60 20 +DS 2706 -3088 2706 -2767 60 20 +DS -1989 1553 -1989 1013 60 20 +DS -1989 1013 1573 1016 60 20 +DS 1573 1016 1573 1548 60 20 +DS -2707 1555 2707 1555 60 20 +DS -2707 -3091 2707 -3091 60 20 +$PAD +Sh "1" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 61 "/flash/SD_DAT2" +Po -1299 0 +$EndPAD +$PAD +Sh "2" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 62 "/flash/SD_DAT3" +Po -866 0 +$EndPAD +$PAD +Sh "3" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 59 "/flash/SD_CMD" +Po -433 0 +$EndPAD +$PAD +Sh "4" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 4 "+3.3V" +Po 0 0 +$EndPAD +$PAD +Sh "5" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 110 "/fpga1/SD_CLK" +Po 433 0 +$EndPAD +$PAD +Sh "6" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 292 "GND" +Po 866 0 +$EndPAD +$PAD +Sh "7" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 111 "/fpga1/SD_DAT0" +Po 1299 0 +$EndPAD +$PAD +Sh "8" R 315 590 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 60 "/flash/SD_DAT1" +Po 1732 0 +$EndPAD +$PAD +Sh "CASE" R 571 787 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 292 "GND" +Po 2707 1024 +$EndPAD +$PAD +Sh "CASE" R 571 787 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 292 "GND" +Po -2707 1024 +$EndPAD +$PAD +Sh "CASE" R 571 787 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 292 "GND" +Po -2707 -2244 +$EndPAD +$PAD +Sh "CASE" R 571 787 0 0 0 +Dr 0 0 0 +At STD N 00440001 +Ne 292 "GND" +Po 2707 -2244 +$EndPAD +$EndMODULE MICROSD-500901 +$MODULE NAND-48TSOP +Po 56780 26154 900 15 4CDDC1BA 4B76F108 ~~ +Li NAND-48TSOP +Sc 4B76F108 +AR /4C4227FE/4B76F108 +Op 0 0 0 +T0 2607 -2485 394 394 1800 39 N V 21 N"U5" +T1 0 118 118 118 -900 20 N I 21 N"NAND" +DS -2470 3900 -2470 -3900 60 24 +DS -2470 -3900 2430 -3900 60 24 +DS 2430 -3900 2430 3900 60 24 +DS 2430 3900 -2470 3900 60 24 +DS -2270 4320 -2470 4520 60 26 +DS -2470 4520 -2070 4520 60 26 +DS -2070 4520 -2270 4320 60 26 +DS -2360 3500 2360 3500 60 26 +DS 2360 3500 2360 -3500 60 26 +DS 2360 -3500 -2360 -3500 60 26 +DS -2360 -3500 -2360 3500 60 26 +DS -2270 4320 -2470 4520 60 21 +DS -2470 4520 -2070 4520 60 21 +DS -2070 4520 -2270 4320 60 21 +DS -2420 3400 2380 3400 60 21 +DS 2380 3400 2380 -3450 60 21 +DS 2380 -3450 -2420 -3450 60 21 +DS -2420 -3450 -2420 3400 60 21 +DS -2400 3500 -2290 3500 30 26 +DS -2290 3500 -2290 3900 30 26 +DS -2290 3900 -2240 3900 30 26 +DS -2240 3900 -2240 3500 30 26 +DS -2240 3500 -2090 3500 30 26 +DS -2090 3500 -2090 3900 30 26 +DS -2090 3900 -2040 3900 30 26 +DS -2040 3900 -2040 3500 30 26 +DS -2040 3500 -1900 3500 30 26 +DS -1900 3500 -1900 3900 30 26 +DS -1900 3900 -1850 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+$EndPAD +$PAD +Sh "4" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1680 3850 +$EndPAD +$PAD +Sh "5" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1480 3850 +$EndPAD +$PAD +Sh "6" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 103 "/fpga1/NF_RNB" +Po -1280 3850 +$EndPAD +$PAD +Sh "7" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 103 "/fpga1/NF_RNB" +Po -1090 3850 +$EndPAD +$PAD +Sh "8" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 57 "/flash/NF_RE_N" +Po -890 3850 +$EndPAD +$PAD +Sh "9" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 97 "/fpga1/NF_CS1_N" +Po -690 3850 +$EndPAD +$PAD +Sh "10" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -500 3850 +$EndPAD +$PAD +Sh "11" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -300 3850 +$EndPAD +$PAD +Sh "12" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -100 3850 +$EndPAD +$PAD +Sh "13" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 100 3850 +$EndPAD +$PAD +Sh "14" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 290 3850 +$EndPAD +$PAD +Sh "15" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 490 3850 +$EndPAD +$PAD +Sh "16" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 53 "/flash/NF_CLE" +Po 690 3850 +$EndPAD +$PAD +Sh "17" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 96 "/fpga1/NF_ALE" +Po 880 3850 +$EndPAD +$PAD +Sh "18" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 58 "/flash/NF_WE_N" +Po 1080 3850 +$EndPAD +$PAD +Sh "19" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 1280 3850 +$EndPAD +$PAD +Sh "20" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1470 3850 +$EndPAD +$PAD +Sh "21" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1670 3850 +$EndPAD +$PAD +Sh "22" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1870 3850 +$EndPAD +$PAD +Sh "23" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2060 3850 +$EndPAD +$PAD +Sh "24" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2260 3850 +$EndPAD +$PAD +Sh "25" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2260 -3850 +$EndPAD +$PAD +Sh "26" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 2060 -3850 +$EndPAD +$PAD +Sh "27" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1870 -3850 +$EndPAD +$PAD +Sh "28" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1670 -3850 +$EndPAD +$PAD +Sh "29" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 98 "/fpga1/NF_D0" +Po 1470 -3850 +$EndPAD +$PAD +Sh "30" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 99 "/fpga1/NF_D1" +Po 1280 -3850 +$EndPAD +$PAD +Sh "31" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 54 "/flash/NF_D2" +Po 1080 -3850 +$EndPAD +$PAD +Sh "32" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 100 "/fpga1/NF_D3" +Po 880 -3850 +$EndPAD +$PAD +Sh "33" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 690 -3850 +$EndPAD +$PAD +Sh "34" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 490 -3850 +$EndPAD +$PAD +Sh "35" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 290 -3850 +$EndPAD +$PAD +Sh "36" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 100 -3850 +$EndPAD +$PAD +Sh "37" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -100 -3850 +$EndPAD +$PAD +Sh "38" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -300 -3850 +$EndPAD +$PAD +Sh "39" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -500 -3850 +$EndPAD +$PAD +Sh "40" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -690 -3850 +$EndPAD +$PAD +Sh "41" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 55 "/flash/NF_D4" +Po -890 -3850 +$EndPAD +$PAD +Sh "42" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 56 "/flash/NF_D5" +Po -1090 -3850 +$EndPAD +$PAD +Sh "43" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 101 "/fpga1/NF_D6" +Po -1280 -3850 +$EndPAD +$PAD +Sh "44" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 102 "/fpga1/NF_D7" +Po -1480 -3850 +$EndPAD +$PAD +Sh "45" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1680 -3850 +$EndPAD +$PAD +Sh "46" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -1870 -3850 +$EndPAD +$PAD +Sh "47" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2070 -3850 +$EndPAD +$PAD +Sh "48" R 100 600 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -2270 -3850 +$EndPAD +$EndMODULE NAND-48TSOP +$MODULE LQFP48 +Po 48675 26272 900 15 4CF99DA8 4C432132 ~~ +Li LQFP48 +Sc 4C432132 +AR /4C4320F3/4C432132 +Op 0 0 0 +At SMD +T0 1811 1581 394 394 900 40 N V 25 N"U4" +T1 0 150 200 200 900 40 N I 25 N"K8001" +DC -1574 -1574 -1574 -1653 39 21 +DS -1377 -1377 -1377 1377 39 21 +DS -1377 1377 1377 1377 39 21 +DS 1377 1377 1377 -1377 39 21 +DS 1377 -1377 -1377 -1377 39 21 +$PAD +Sh "12" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -1613 1082 +$EndPAD +$PAD +Sh "11" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 16 "/ether/ETH_RXER" +Po -1613 885 +$EndPAD +$PAD +Sh "10" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 67 "/fpga1/ETH_RXC" +Po -1613 688 +$EndPAD +$PAD +Sh "9" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 15 "/ether/ETH_RXDV" +Po -1613 491 +$EndPAD +$PAD +Sh "8" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -1613 295 +$EndPAD +$PAD +Sh "7" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -1613 98 +$EndPAD +$PAD +Sh "6" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 14 "/ether/ETH_RXD0" +Po -1613 -98 +$EndPAD +$PAD +Sh "5" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 68 "/fpga1/ETH_RXD1" +Po -1613 -295 +$EndPAD +$PAD +Sh "4" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 69 "/fpga1/ETH_RXD2" +Po -1613 -491 +$EndPAD +$PAD +Sh "3" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 70 "/fpga1/ETH_RXD3" +Po -1613 -688 +$EndPAD +$PAD +Sh "2" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 65 "/fpga1/ETH_MDC" +Po -1613 -885 +$EndPAD +$PAD +Sh "1" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 12 "/ether/ETH_MDIO" +Po -1613 -1082 +$EndPAD +$PAD +Sh "48" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 66 "/fpga1/ETH_RESET_N" +Po -1082 -1613 +$EndPAD +$PAD +Sh "47" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 13 "/ether/ETH_PLL1.8V" +Po -885 -1613 +$EndPAD +$PAD +Sh "46" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 63 "/fpga1/ETH_CLK" +Po -688 -1613 +$EndPAD +$PAD +Sh "45" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -491 -1613 +$EndPAD +$PAD +Sh "44" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -295 -1613 +$EndPAD +$PAD +Sh "43" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -98 -1613 +$EndPAD +$PAD +Sh "42" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 98 -1613 +$EndPAD +$PAD +Sh "41" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 21 "/ether/MAG_TX+" +Po 295 -1613 +$EndPAD +$PAD +Sh "40" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 22 "/ether/MAG_TX-" +Po 491 -1613 +$EndPAD +$PAD +Sh "39" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 688 -1613 +$EndPAD +$PAD +Sh "38" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 7 "/ether/ETH_A3.3V" +Po 885 -1613 +$EndPAD +$PAD +Sh "37" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 295 "N-000133" +Po 1082 -1613 +$EndPAD +$PAD +Sh "25" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 9 "/ether/ETH_INT" +Po 1613 1082 +$EndPAD +$PAD +Sh "26" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 10 "/ether/ETH_LED0" +Po 1613 885 +$EndPAD +$PAD +Sh "27" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 11 "/ether/ETH_LED1" +Po 1613 688 +$EndPAD +$PAD +Sh "28" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1613 491 +$EndPAD +$PAD +Sh "29" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1613 295 +$EndPAD +$PAD +Sh "30" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1613 98 +$EndPAD +$PAD +Sh "31" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 6 "/ether/ETH_A1.8V" +Po 1613 -98 +$EndPAD +$PAD +Sh "32" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 19 "/ether/MAG_RX-" +Po 1613 -295 +$EndPAD +$PAD +Sh "33" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 18 "/ether/MAG_RX+" +Po 1613 -491 +$EndPAD +$PAD +Sh "34" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 1613 -688 +$EndPAD +$PAD +Sh "35" R 315 99 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 1613 -885 +$EndPAD +$PAD +Sh "36" R 315 98 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 1613 -1082 +$EndPAD +$PAD +Sh "13" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 2 "+1.8V" +Po -1082 1613 +$EndPAD +$PAD +Sh "14" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 17 "/ether/ETH_TXER" +Po -885 1613 +$EndPAD +$PAD +Sh "15" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 71 "/fpga1/ETH_TXC" +Po -688 1613 +$EndPAD +$PAD +Sh "16" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 76 "/fpga1/ETH_TXEN" +Po -491 1613 +$EndPAD +$PAD +Sh "17" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 72 "/fpga1/ETH_TXD0" +Po -295 1613 +$EndPAD +$PAD +Sh "18" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 73 "/fpga1/ETH_TXD1" +Po -98 1613 +$EndPAD +$PAD +Sh "19" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 74 "/fpga1/ETH_TXD2" +Po 98 1613 +$EndPAD +$PAD +Sh "20" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 75 "/fpga1/ETH_TXD3" +Po 295 1613 +$EndPAD +$PAD +Sh "21" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 64 "/fpga1/ETH_COL" +Po 491 1613 +$EndPAD +$PAD +Sh "22" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 8 "/ether/ETH_CRS" +Po 688 1613 +$EndPAD +$PAD +Sh "23" R 99 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 885 1613 +$EndPAD +$PAD +Sh "24" R 98 315 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po 1082 1613 +$EndPAD +$EndMODULE LQFP48 +$MODULE 1206 +Po 63750 39693 1800 15 4CDDBFD3 4C61D1D4 ~~ +Li 1206 +Sc 4C61D1D4 +AR /4C421DD3/4C61D1D4 +Op 0 0 0 +At SMD +T0 96 -590 200 200 1800 40 N V 25 N"C34" +T1 0 150 200 200 1800 40 N I 25 N"10uF" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 3 "+2.5V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 +$MODULE 0603 +Po 46992 24362 1800 0 4CDB6C9C 4C5D7FB7 ~~ +Li 0603 +Sc 4C5D7FB7 +AR /4C4320F3/4C5D7FB7 +Op 0 0 0 +At SMD +T0 649 -126 200 200 1800 40 M V 20 N"L2" +T1 0 -150 200 200 1800 40 M I 20 N"FB" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 7 "/ether/ETH_A3.3V" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0402 +Po 60921 37756 1800 0 4C756B39 4C716CF6 ~~ +Li 0402 +Sc 4C716CF6 +AR /4C7BC2B2/4C7168DD +Op 0 0 0 +At SMD +T0 15 -350 200 200 1800 40 M V 20 N"R30" +T1 0 -150 200 200 1800 40 M I 20 N"330" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 306 "N-000359" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 51134 39547 900 0 4CD365DA 4C716CF8 ~~ +Li 0402 +Sc 4C716CF8 +AR /4C7BC2B2/4C716877 +Op 0 0 0 +At SMD +T0 -4 347 200 200 900 40 M V 20 N"R29" +T1 0 -150 200 200 900 40 M I 20 N"4.7k" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 305 "N-000356" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE MLF16 +Po 57429 27272 0 0 4CDB6D2D 4C71BB0D ~~ +Li MLF16 +Sc 4C71BB0D +AR /4C5F1EDC/4C71BA25 +Op 0 0 0 +At SMD +T0 221 775 200 200 0 40 M V 20 N"U7" +T1 0 -150 200 200 0 40 M I 20 N"MIC2550-MLF" +DC -669 669 -669 747 39 20 +DS -590 -590 -590 590 39 20 +DS -590 590 590 590 39 20 +DS 590 590 590 -590 39 20 +DS 590 -590 -590 -590 39 20 +$PAD +Sh "PAD" R 590 590 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 0 0 +$EndPAD +$PAD +Sh "12" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -295 -491 +$EndPAD +$PAD +Sh "1" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 287 "/usb/USBD_SPD" +Po -295 491 +$EndPAD +$PAD +Sh "11" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 300 "N-000146" +Po -98 -491 +$EndPAD +$PAD +Sh "2" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 244 "/fpga2/USBD_RCV" +Po -98 491 +$EndPAD +$PAD +Sh "10" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 299 "N-000145" +Po 98 -491 +$EndPAD +$PAD +Sh "3" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 289 "/usb/USBD_VP" +Po 98 491 +$EndPAD +$PAD +Sh "9" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 286 "/usb/USBD_OE_N" +Po 295 -491 +$EndPAD +$PAD +Sh "4" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 288 "/usb/USBD_VM" +Po 295 491 +$EndPAD +$PAD +Sh "16" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -491 295 +$EndPAD +$PAD +Sh "5" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 491 295 +$EndPAD +$PAD +Sh "15" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -491 98 +$EndPAD +$PAD +Sh "6" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 491 98 +$EndPAD +$PAD +Sh "14" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -491 -98 +$EndPAD +$PAD +Sh "7" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 491 -98 +$EndPAD +$PAD +Sh "13" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -491 -295 +$EndPAD +$PAD +Sh "8" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 491 -295 +$EndPAD +$EndMODULE MLF16 +$MODULE MLF16 +Po 55717 27272 0 0 4CDB6D28 4C71BB0F ~~ +Li MLF16 +Sc 4C71BB0F +AR /4C5F1EDC/4C71BA1D +Op 0 0 0 +At SMD +T0 401 795 200 200 0 40 M V 20 N"U6" +T1 0 -150 200 200 0 40 M I 20 N"MIC2550-MLF" +DC -669 669 -669 747 39 20 +DS -590 -590 -590 590 39 20 +DS -590 590 590 590 39 20 +DS 590 590 590 -590 39 20 +DS 590 -590 -590 -590 39 20 +$PAD +Sh "PAD" R 590 590 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 0 0 +$EndPAD +$PAD +Sh "12" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -295 -491 +$EndPAD +$PAD +Sh "1" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 283 "/usb/USBA_SPD" +Po -295 491 +$EndPAD +$PAD +Sh "11" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 298 "N-000144" +Po -98 -491 +$EndPAD +$PAD +Sh "2" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 241 "/fpga2/USBA_RCV" +Po -98 491 +$EndPAD +$PAD +Sh "10" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 301 "N-000147" +Po 98 -491 +$EndPAD +$PAD +Sh "3" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 243 "/fpga2/USBA_VP" +Po 98 491 +$EndPAD +$PAD +Sh "9" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 282 "/usb/USBA_OE_N" +Po 295 -491 +$EndPAD +$PAD +Sh "4" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 242 "/fpga2/USBA_VM" +Po 295 491 +$EndPAD +$PAD +Sh "16" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -491 295 +$EndPAD +$PAD +Sh "5" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 491 295 +$EndPAD +$PAD +Sh "15" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -491 98 +$EndPAD +$PAD +Sh "6" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 491 98 +$EndPAD +$PAD +Sh "14" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -491 -98 +$EndPAD +$PAD +Sh "7" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 491 -98 +$EndPAD +$PAD +Sh "13" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po -491 -295 +$EndPAD +$PAD +Sh "8" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 491 -295 +$EndPAD +$EndMODULE MLF16 +$MODULE 0402 +Po 50744 28492 1350 0 4CDB6D15 4C744B72 ~~ +Li 0402 +Sc 4C744B72 +AR /4C7BC2B2/4C73D074 +Op 0 0 0 +At SMD +T0 6 -345 200 200 1350 40 M V 20 N"C90" +T1 0 -150 200 200 1350 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1350 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1350 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 57280 30457 1350 0 4CDB6EE8 4C744B74 ~~ +Li 0402 +Sc 4C744B74 +AR /4C7BC2B2/4C73D252 +Op 0 0 0 +At SMD +T0 -19 309 200 200 1350 40 M V 20 N"C91" +T1 0 -150 200 200 1350 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1350 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1350 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 56835 25886 1800 0 4CDB6D3F 4C6552BE ~~ +Li 0603 +Sc 4C6552BE +AR /4C5F1EDC/4C6552BE +Op 0 0 0 +At SMD +T0 760 -20 200 200 1800 40 M V 20 N"C35" +T1 0 -150 200 200 1800 40 M I 20 N"1uF" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0402 +Po 56858 26402 1800 0 4CDB6D43 4C6552BD ~~ +Li 0402 +Sc 4C6552BD +AR /4C5F1EDC/4C6552BD +Op 0 0 0 +At SMD +T0 594 -27 200 200 1800 40 M V 20 N"C36" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 54768 27201 900 0 4CDB6D55 4C5F2039 ~~ +Li 0402 +Sc 4C5F2039 +AR /4C5F1EDC/4C5F2039 +Op 0 0 0 +At SMD +T0 20 -351 200 200 900 40 M V 20 N"C15" +T1 0 -150 200 200 900 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 55071 26398 1800 0 4CDB6D50 4C5F2037 ~~ +Li 0402 +Sc 4C5F2037 +AR /4C5F1EDC/4C5F2037 +Op 0 0 0 +At SMD +T0 799 -4 200 200 1800 40 M V 20 N"C14" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 56854 34382 1800 0 4CDB6F28 4C748F82 ~~ +Li 0402 +Sc 4C748F82 +AR /4C7BC2B2/4C748EDA +Op 0 0 0 +At SMD +T0 8 284 200 200 1800 40 M V 20 N"C93" +T1 0 -150 200 200 1800 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 1 "+1.2V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 56272 34972 900 0 4CDB6F43 4C748F7F ~~ +Li 0402 +Sc 4C748F7F +AR /4C7BC2B2/4C748EDB +Op 0 0 0 +At SMD +T0 19 330 200 200 900 40 M V 20 N"C92" +T1 0 -150 200 200 900 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 1 "+1.2V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 53413 32346 3150 0 4CDB6F0A 4C749A4B ~~ +Li 0402 +Sc 4C749A4B +AR /4C7BC2B2/4C749A0C +Op 0 0 0 +At SMD +T0 -3 359 200 200 3150 40 M V 20 N"C94" +T1 0 -150 200 200 3150 40 M I 20 N"470nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 3150 +Dr 0 0 0 +At SMD N 00440001 +Ne 3 "+2.5V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 3150 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE ZX62D-B-5P8 +Po 62598 16157 1800 15 4CF99D75 4CB9D6F7 ~~ +Li ZX62D-B-5P8 +Sc 4CB9D6F7 +AR /4C5F1EDC/4C75F027 +Op 0 0 0 +T0 -1638 -1115 394 394 1800 39 N V 21 N"J7" +T1 550 -500 118 118 1800 20 N I 21 N"ZX62D-B-5P8" +DS -1690 2970 -1760 2970 100 21 +DS -1760 2970 -1760 -630 100 21 +DS -1760 -630 2960 -630 100 21 +DS 2960 -630 2960 -630 100 21 +DS 2960 -630 2960 2970 100 21 +DS 2960 2970 -1690 2970 100 21 +DS -1910 3120 -1910 -780 10 24 +DS -1910 -780 3110 -780 10 24 +DS 3110 -780 3110 3120 10 24 +DS 3110 3120 -1910 3120 10 24 +$PAD +Sh "1" R 200 620 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 0 +$EndPAD +$PAD +Sh "2" R 200 620 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 285 "/usb/USBD_D-" +Po 310 0 +$EndPAD +$PAD +Sh "3" R 200 620 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 284 "/usb/USBD_D+" +Po 630 0 +$EndPAD +$PAD +Sh "4" R 200 620 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 297 "N-000143" +Po 940 0 +$EndPAD +$PAD +Sh "5" R 200 620 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 297 "N-000143" +Po 1260 0 +$EndPAD +$PAD +Sh "H1" C 380 380 0 0 1800 +Dr 420 0 0 +At STD N 00C08001 +Ne 0 "" +Po -240 1170 +$EndPAD +$PAD +Sh "H2" C 380 380 0 0 1800 +Dr 420 0 0 +At STD N 00C08001 +Ne 0 "" +Po 1490 1170 +$EndPAD +$PAD +Sh "8" R 860 900 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 290 "/usb/USB_CASE_DEV" +Po -1070 140 +$EndPAD +$PAD +Sh "6" R 860 900 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 290 "/usb/USB_CASE_DEV" +Po 2320 2310 +$EndPAD +$PAD +Sh "7" R 860 900 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 290 "/usb/USB_CASE_DEV" +Po -1070 2310 +$EndPAD +$PAD +Sh "9" R 860 900 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 290 "/usb/USB_CASE_DEV" +Po 2320 140 +$EndPAD +$EndMODULE ZX62D-B-5P8 +$MODULE 0402 +Po 61469 18024 0 0 4C7D3C9F 4C7D37B8 ~~ +Li 0402 +Sc 4C7D37B8 +AR /4C5F1EDC/4C7D365F +Op 0 0 0 +At SMD +T0 -626 -31 200 200 0 40 M V 20 N"R55" +T1 0 -150 200 200 0 40 M I 20 N"15k" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 284 "/usb/USBD_D+" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 62654 18248 1800 15 4CF99D6E 4C7D37BA ~~ +Li 0402 +Sc 4C7D37BA +AR /4C5F1EDC/4C7D3660 +Op 0 0 0 +At SMD +T0 40 -370 200 200 1800 40 N V 25 N"R54" +T1 0 150 200 200 1800 40 N I 25 N"15k" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 285 "/usb/USBD_D-" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 61445 18252 0 15 4CF99D5A 4C7D37BC ~~ +Li 0402 +Sc 4C7D37BC +AR /4C5F1EDC/4C7D3661 +Op 0 0 0 +At SMD +T0 4 358 200 200 0 40 N V 25 N"R53" +T1 0 150 200 200 0 40 N I 25 N"15k" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 284 "/usb/USBD_D+" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 55984 24957 2700 0 4C7D3E96 4C7D37BE ~~ +Li 0402 +Sc 4C7D37BE +AR /4C5F1EDC/4C7D350E +Op 0 0 0 +At SMD +T0 -28 -347 200 200 2700 40 M V 20 N"R52" +T1 0 -150 200 200 2700 40 M I 20 N"24" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 281 "/usb/USBA_D-" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 301 "N-000147" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 55531 24957 2700 0 4C7D3E79 4C7D37C0 ~~ +Li 0402 +Sc 4C7D37C0 +AR /4C5F1EDC/4C7D3508 +Op 0 0 0 +At SMD +T0 -8 318 200 200 2700 40 M V 20 N"R51" +T1 0 -150 200 200 2700 40 M I 20 N"24" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 280 "/usb/USBA_D+" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 298 "N-000144" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 57677 24945 2700 0 4C7D38BF 4C7D37C2 ~~ +Li 0402 +Sc 4C7D37C2 +AR /4C5F1EDC/4C7D354C +Op 0 0 0 +At SMD +T0 -20 -323 200 200 2700 40 M V 20 N"R50" +T1 0 -150 200 200 2700 40 M I 20 N"24" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 285 "/usb/USBD_D-" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 299 "N-000145" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 57252 24945 2700 0 4C7D38C5 4C7D37C4 ~~ +Li 0402 +Sc 4C7D37C4 +AR /4C5F1EDC/4C7D354D +Op 0 0 0 +At SMD +T0 8 303 200 200 2700 40 M V 20 N"R49" +T1 0 -150 200 200 2700 40 M I 20 N"24" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 284 "/usb/USBD_D+" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 300 "N-000146" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 55378 23390 0 0 4C7D40EE 4C7D37C6 ~~ +Li 0402 +Sc 4C7D37C6 +AR /4C5F1EDC/4C7D32A3 +Op 0 0 0 +At SMD +T0 -654 8 200 200 0 40 M V 20 N"R48" +T1 0 -150 200 200 0 40 M I 20 N"15k" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 280 "/usb/USBA_D+" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 55421 21780 0 0 4C7D407E 4C7D37C8 ~~ +Li 0402 +Sc 4C7D37C8 +AR /4C5F1EDC/4C7D3098 +Op 0 0 0 +At SMD +T0 -638 4 200 200 0 40 M V 20 N"R47" +T1 0 -150 200 200 0 40 M I 20 N"15k" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 280 "/usb/USBA_D+" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 56543 21787 1800 0 4C7D405F 4C7D37CA ~~ +Li 0402 +Sc 4C7D37CA +AR /4C5F1EDC/4C7D3075 +Op 0 0 0 +At SMD +T0 -599 11 200 200 1800 40 M V 20 N"R46" +T1 0 -150 200 200 1800 40 M I 20 N"15k" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 281 "/usb/USBA_D-" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 1206 +Po 65539 13949 0 15 4CDB6C0D 4C7D3830 ~~ +Li 1206 +Sc 4C7D3830 +AR /4C5F1EDC/4C6552B7 +Op 0 0 0 +At SMD +T0 508 563 200 200 0 40 N V 25 N"C38" +T1 0 150 200 200 0 40 N I 25 N"4.7nF" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 290 "/usb/USB_CASE_DEV" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 +$MODULE 1206 +Po 54673 16543 900 15 4CDB6C20 4C7D3832 ~~ +Li 1206 +Sc 4C7D3832 +AR /4C5F1EDC/4C5F2D1E +Op 0 0 0 +At SMD +T0 992 -47 200 200 1800 40 N V 25 N"C16" +T1 0 150 200 200 900 40 N I 25 N"4.7nF" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 291 "/usb/USB_CASE_HOST" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 +$MODULE 1206 +Po 54602 18996 2700 15 4CDB6C27 4C8934E8 ~~ +Li 1206 +Sc 4C8934E8 +AR /4C4320F3/4C5D7DCB +Op 0 0 0 +At SMD +T0 -968 8 200 200 3600 40 N V 25 N"C12" +T1 0 150 200 200 2700 40 N I 25 N"47nF" +DS -798 384 -798 -384 50 21 +DS -798 -384 798 -384 50 21 +DS 798 -384 798 384 50 21 +DS 798 384 -798 384 50 21 +$PAD +Sh "1" R 355 668 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 20 "/ether/MAG_SHIELD" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 668 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1206 +$MODULE header25x2_smd_2mm +Po 56260 51142 0 0 4CDDC57B 4CBAFFD7 ~~ +Li header25x2_smd_2mm +Sc 4CBAFFD7 +AR /4CB0D95D/4CBAFE50 +Op 0 0 0 +At SMD +T0 8933 -1784 394 394 0 40 M V 20 N"P1" +T1 0 -150 200 200 0 40 M I 20 N"CONN_25X2" +DC 9645 -1771 9645 -1574 78 20 +DS 10039 1377 10039 -1377 39 20 +DS 10039 -1377 -10039 -1377 39 20 +DS -10039 -1377 -10039 1377 39 20 +DS -10039 1377 10039 1377 39 20 +$PAD +Sh "1" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 51 "/expansion/FPGA_BANK0_IO_8" +Po 9448 -747 +$EndPAD +$PAD +Sh "3" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 8661 -747 +$EndPAD +$PAD +Sh "5" R 393 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 307 "VCCO2" +Po 7873 -747 +$EndPAD +$PAD +Sh "7" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 24 "/expansion/FPGA_BANK0_IO_10" +Po 7086 -747 +$EndPAD +$PAD +Sh "9" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 77 "/fpga1/FPGA_BANK0_IO_11" +Po 6299 -747 +$EndPAD +$PAD +Sh "11" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 45 "/expansion/FPGA_BANK0_IO_5" +Po 5511 -747 +$EndPAD +$PAD +Sh "13" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 28 "/expansion/FPGA_BANK0_IO_17" +Po 4724 -747 +$EndPAD +$PAD +Sh "15" R 393 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 80 "/fpga1/FPGA_BANK0_IO_20" +Po 3936 -747 +$EndPAD +$PAD +Sh "17" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 83 "/fpga1/FPGA_BANK0_IO_28" +Po 3149 -747 +$EndPAD +$PAD +Sh "19" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 81 "/fpga1/FPGA_BANK0_IO_22" +Po 2362 -747 +$EndPAD +$PAD +Sh "21" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 31 "/expansion/FPGA_BANK0_IO_27" +Po 1574 -747 +$EndPAD +$PAD +Sh "23" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 39 "/expansion/FPGA_BANK0_IO_39" +Po 787 -747 +$EndPAD +$PAD +Sh "25" R 392 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 79 "/fpga1/FPGA_BANK0_IO_2" +Po 0 -747 +$EndPAD +$PAD +Sh "27" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 95 "/fpga1/FPGA_BANK0_IO_7" +Po -787 -747 +$EndPAD +$PAD +Sh "29" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 25 "/expansion/FPGA_BANK0_IO_12" +Po -1574 -747 +$EndPAD +$PAD +Sh "31" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 86 "/fpga1/FPGA_BANK0_IO_44" +Po -2362 -747 +$EndPAD +$PAD +Sh "33" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 43 "/expansion/FPGA_BANK0_IO_47" +Po -3149 -747 +$EndPAD +$PAD +Sh "35" R 393 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 41 "/expansion/FPGA_BANK0_IO_45" +Po -3936 -747 +$EndPAD +$PAD +Sh "37" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 90 "/fpga1/FPGA_BANK0_IO_52" +Po -4724 -747 +$EndPAD +$PAD +Sh "39" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 91 "/fpga1/FPGA_BANK0_IO_56" +Po -5511 -747 +$EndPAD +$PAD +Sh "41" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 89 "/fpga1/FPGA_BANK0_IO_51" +Po -6299 -747 +$EndPAD +$PAD +Sh "43" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 47 "/expansion/FPGA_BANK0_IO_54" +Po -7086 -747 +$EndPAD +$PAD +Sh "45" R 393 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 50 "/expansion/FPGA_BANK0_IO_63" +Po -7873 -747 +$EndPAD +$PAD +Sh "47" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 46 "/expansion/FPGA_BANK0_IO_53" +Po -8661 -747 +$EndPAD +$PAD +Sh "49" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 92 "/fpga1/FPGA_BANK0_IO_58" +Po -9448 -747 +$EndPAD +$PAD +Sh "2" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 23 "/expansion/FPGA_BANK0_IO_1" +Po 9448 747 +$EndPAD +$PAD +Sh "4" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 52 "/expansion/FPGA_BANK0_IO_9" +Po 8661 747 +$EndPAD +$PAD +Sh "6" R 393 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 26 "/expansion/FPGA_BANK0_IO_14" +Po 7873 747 +$EndPAD +$PAD +Sh "8" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 27 "/expansion/FPGA_BANK0_IO_15" +Po 7086 747 +$EndPAD +$PAD +Sh "10" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 33 "/expansion/FPGA_BANK0_IO_3" +Po 6299 747 +$EndPAD +$PAD +Sh "12" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 78 "/fpga1/FPGA_BANK0_IO_18" +Po 5511 747 +$EndPAD +$PAD +Sh "14" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 29 "/expansion/FPGA_BANK0_IO_21" +Po 4724 747 +$EndPAD +$PAD +Sh "16" R 393 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 30 "/expansion/FPGA_BANK0_IO_24" +Po 3936 747 +$EndPAD +$PAD +Sh "18" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 32 "/expansion/FPGA_BANK0_IO_29" +Po 3149 747 +$EndPAD +$PAD +Sh "20" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 34 "/expansion/FPGA_BANK0_IO_30" +Po 2362 747 +$EndPAD +$PAD +Sh "22" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 82 "/fpga1/FPGA_BANK0_IO_25" +Po 1574 747 +$EndPAD +$PAD +Sh "24" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 84 "/fpga1/FPGA_BANK0_IO_33" +Po 787 747 +$EndPAD +$PAD +Sh "26" R 392 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 35 "/expansion/FPGA_BANK0_IO_32" +Po 0 747 +$EndPAD +$PAD +Sh "28" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 93 "/fpga1/FPGA_BANK0_IO_6" +Po -787 747 +$EndPAD +$PAD +Sh "30" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 37 "/expansion/FPGA_BANK0_IO_36" +Po -1574 747 +$EndPAD +$PAD +Sh "32" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 85 "/fpga1/FPGA_BANK0_IO_40" +Po -2362 747 +$EndPAD +$PAD +Sh "34" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 40 "/expansion/FPGA_BANK0_IO_43" +Po -3149 747 +$EndPAD +$PAD +Sh "36" R 393 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 42 "/expansion/FPGA_BANK0_IO_46" +Po -3936 747 +$EndPAD +$PAD +Sh "38" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 88 "/fpga1/FPGA_BANK0_IO_50" +Po -4724 747 +$EndPAD +$PAD +Sh "40" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 87 "/fpga1/FPGA_BANK0_IO_48" +Po -5511 747 +$EndPAD +$PAD +Sh "42" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 36 "/expansion/FPGA_BANK0_IO_34" +Po -6299 747 +$EndPAD +$PAD +Sh "44" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 44 "/expansion/FPGA_BANK0_IO_49" +Po -7086 747 +$EndPAD +$PAD +Sh "46" R 393 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 94 "/fpga1/FPGA_BANK0_IO_62" +Po -7873 747 +$EndPAD +$PAD +Sh "48" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 48 "/expansion/FPGA_BANK0_IO_57" +Po -8661 747 +$EndPAD +$PAD +Sh "50" R 394 1181 0 0 0 +Dr 0 0 0 +At SMD N 00400001 +Ne 49 "/expansion/FPGA_BANK0_IO_60" +Po -9448 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 9448 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 8661 747 +$EndPAD +$PAD +Sh "" R 373 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 7873 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 7086 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 6299 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 5511 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 4724 747 +$EndPAD +$PAD +Sh "" R 373 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 3936 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 3149 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 2362 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 1574 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 787 747 +$EndPAD +$PAD +Sh "" R 373 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po 0 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -787 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -1574 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -2362 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -3149 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -3937 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -4724 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -5511 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -6299 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -7086 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -7874 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -8661 747 +$EndPAD +$PAD +Sh "" R 374 1103 0 0 0 +Dr 0 0 0 +At SMD N 00040000 +Ne 0 "" +Po -9448 747 +$EndPAD +$EndMODULE header25x2_smd_2mm +$MODULE 0402 +Po 48744 34720 0 0 4CCF2E75 4CCF29AA ~~ +Li 0402 +Sc 4CCF29AA +AR /4C7BC2A2/4CCF2730 +Op 0 0 0 +At SMD +T0 -646 -51 200 200 0 40 M V 20 N"R86" +T1 0 -150 200 200 0 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 196 "/fpga2/R_M0_LDQS" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 134 "/fpga2/M0_LDQS" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 49043 34224 0 0 4CCF2DB0 4CCF29AC ~~ +Li 0402 +Sc 4CCF29AC +AR /4C7BC2A2/4CCF272E +Op 0 0 0 +At SMD +T0 618 16 200 200 0 40 M V 20 N"R85" +T1 0 -150 200 200 0 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 195 "/fpga2/R_M0_LDM" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 258 "/sdram/M0_LDM" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 49583 33819 0 0 4CCF2D9C 4CCF29AE ~~ +Li 0402 +Sc 4CCF29AE +AR /4C7BC2A2/4CCF272F +Op 0 0 0 +At SMD +T0 -614 71 200 200 0 40 M V 20 N"R84" +T1 0 -150 200 200 0 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 200 "/fpga2/R_M0_WE#" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 260 "/sdram/M0_WE#" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 49583 33433 0 0 4CCF2DA3 4CCF29B0 ~~ +Li 0402 +Sc 4CCF29B0 +AR /4C7BC2A2/4CCF2733 +Op 0 0 0 +At SMD +T0 -603 16 200 200 0 40 M V 20 N"R83" +T1 0 -150 200 200 0 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 177 "/fpga2/R_M0_CAS#" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 248 "/sdram/M0_CAS#" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 65150 34567 0 0 4CCF2A7A 4CCF29B2 ~~ +Li 0402 +Sc 4CCF29B2 +AR /4C7BC2A2/4CCF27A8 +Op 0 0 0 +At SMD +T0 -614 27 200 200 0 40 M V 20 N"R82" +T1 0 -150 200 200 0 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 236 "/fpga2/R_M1_LDQS" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 157 "/fpga2/M1_LDQS" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 64957 34118 0 0 4CCF2A74 4CCF29B4 ~~ +Li 0402 +Sc 4CCF29B4 +AR /4C7BC2A2/4CCF27AA +Op 0 0 0 +At SMD +T0 -607 27 200 200 0 40 M V 20 N"R81" +T1 0 -150 200 200 0 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 235 "/fpga2/R_M1_LDM" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 278 "/sdram/M1_LDM" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 64949 33689 0 0 4CCF2A22 4CCF29B6 ~~ +Li 0402 +Sc 4CCF29B6 +AR /4C7BC2A2/4CCF27A9 +Op 0 0 0 +At SMD +T0 -610 8 200 200 0 40 M V 20 N"R80" +T1 0 -150 200 200 0 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 240 "/fpga2/R_M1_WE#" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 161 "/fpga2/M1_WE#" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 64953 33276 0 0 4CF99F27 4CD0CF47 ~~ +Li 0402 +Sc 4CD0CF47 +AR /4C7BC2A2/4CCF27A7 +Op 0 0 0 +At SMD +T0 -607 23 200 200 0 40 M V 20 N"R79" +T1 0 -150 200 200 0 40 M I 20 N"33" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 216 "/fpga2/R_M1_CAS#" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 146 "/fpga2/M1_CAS#" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 53949 39610 900 0 4CD364B9 4CD34E73 ~~ +Li 0402 +Sc 4CD34E73 +AR /4C7BC2B2/4CD34D8C +Op 0 0 0 +At SMD +T0 -705 31 200 200 900 40 M V 20 N"C156" +T1 0 -362 200 200 900 40 M I 20 N"10nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00440001 +Ne 307 "VCCO2" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE CRYSTAL +Po 53311 40102 1800 0 4CDDC543 4CD34E74 ~~ +Li CRYSTAL +Sc 4CD34E74 +AR /4C7BC2B2/4CD34D72 +Op 0 0 0 +T0 386 -650 394 394 1800 45 M V 20 N"X2" +T1 394 -961 600 600 1800 120 M I 20 N"FXO-HC536R" +DC 0 -433 -59 -423 30 20 +DS -374 955 -374 -325 30 20 +DS -374 -325 1240 -325 30 20 +DS 1240 -325 1240 955 30 20 +DS 1240 955 -374 955 30 20 +$PAD +Sh "1" R 551 453 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 0 "" +Po 0 0 +$EndPAD +$PAD +Sh "2" R 551 453 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 866 0 +$EndPAD +$PAD +Sh "3" R 551 453 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 38 "/expansion/FPGA_BANK0_IO_38" +Po 866 630 +$EndPAD +$PAD +Sh "4" R 551 453 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 307 "VCCO2" +Po 0 630 +$EndPAD +$EndMODULE CRYSTAL +$MODULE 0603 +Po 46984 19717 2700 0 4CF99F56 4C8934E6 ~~ +Li 0603 +Sc 4C8934E6 +AR /4C4320F3/4C5D7DC4 +Op 0 0 0 +At SMD +T0 23 390 200 200 2700 40 M V 20 N"R9" +T1 0 -150 200 200 2700 40 M I 20 N"1M" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 20 "/ether/MAG_SHIELD" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 58717 18953 0 0 4CDDCF7E 4C7D382E ~~ +Li 0603 +Sc 4C7D382E +AR /4C5F1EDC/4C5F2D27 +Op 0 0 0 +At SMD +T0 -36 417 200 200 0 40 M V 20 N"R10" +T1 0 -150 200 200 0 40 M I 20 N"1M" +DS -443 -227 -443 227 50 20 +DS -443 227 443 227 50 20 +DS 443 227 443 -227 50 20 +DS 443 -227 -443 -227 50 20 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 291 "/usb/USB_CASE_HOST" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00440001 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 58862 14728 2700 15 4CF99D98 4C7D382C ~~ +Li 0603 +Sc 4C7D382C +AR /4C5F1EDC/4C6552B6 +Op 0 0 0 +At SMD +T0 898 47 200 200 2700 40 N V 25 N"R15" +T1 0 150 200 200 2700 40 N I 25 N"1M" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 290 "/usb/USB_CASE_DEV" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE MINI-SO-8 +Po 69287 57331 0 15 4D137C34 4D13CF78 ~~ +Li MINI-SO-8 +Sc 4D13CF78 +AR /4C69ED5F/4D13C8D9 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"U9" +T1 0 150 200 200 0 40 N I 25 N"LM2621" +DC -472 551 -472 511 39 21 +DS -590 669 -590 -669 39 21 +DS -590 -669 590 -669 39 21 +DS 590 -669 590 669 39 21 +DS 590 669 -590 669 39 21 +$PAD +Sh "1" R 161 394 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -383 905 +$EndPAD +$PAD +Sh "8" R 161 394 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -383 -905 +$EndPAD +$PAD +Sh "2" R 161 394 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -127 905 +$EndPAD +$PAD +Sh "7" R 161 394 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -127 -905 +$EndPAD +$PAD +Sh "3" R 161 394 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 127 905 +$EndPAD +$PAD +Sh "6" R 161 394 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 127 -905 +$EndPAD +$PAD +Sh "4" R 161 394 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 383 905 +$EndPAD +$PAD +Sh "5" R 161 394 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 383 -905 +$EndPAD +$EndMODULE MINI-SO-8 +$MODULE MLF20m1 +Po 73240 56559 0 15 4D137C34 4D13CF79 ~~ +Li MLF20m1 +Sc 4D13CF79 +AR /4C69ED5F/4D13C8D1 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"U12" +T1 0 150 200 200 0 40 N I 25 N"BD9132MUV" +DC -866 -866 -866 -944 39 21 +DS -787 787 -787 -787 39 21 +DS -787 -787 787 -787 39 21 +DS 787 -787 787 787 39 21 +DS 787 787 -787 787 39 21 +$PAD +Sh "PAD" R 433 433 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -235 235 +$EndPAD +$PAD +Sh "PAD" R 433 433 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -235 -235 +$EndPAD +$PAD +Sh "PAD" R 433 433 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 235 235 +$EndPAD +$PAD +Sh "PAD" R 433 433 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 235 -235 +$EndPAD +$PAD +Sh "15" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -393 688 +$EndPAD +$PAD +Sh "1" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 304 "N-000178" +Po -393 -688 +$EndPAD +$PAD +Sh "14" R 99 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 688 +$EndPAD +$PAD +Sh "2" R 99 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -196 -688 +$EndPAD +$PAD +Sh "13" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 688 +$EndPAD +$PAD +Sh "3" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 -688 +$EndPAD +$PAD +Sh "12" R 99 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 688 +$EndPAD +$PAD +Sh "4" R 99 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 196 -688 +$EndPAD +$PAD +Sh "11" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 393 688 +$EndPAD +$PAD +Sh "5" R 98 157 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 393 -688 +$EndPAD +$PAD +Sh "20" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 -393 +$EndPAD +$PAD +Sh "6" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 -393 +$EndPAD +$PAD +Sh "19" R 157 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 -196 +$EndPAD +$PAD +Sh "7" R 157 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 -196 +$EndPAD +$PAD +Sh "18" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 0 +$EndPAD +$PAD +Sh "8" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 0 +$EndPAD +$PAD +Sh "17" R 157 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 196 +$EndPAD +$PAD +Sh "9" R 157 99 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 196 +$EndPAD +$PAD +Sh "16" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -688 393 +$EndPAD +$PAD +Sh "10" R 157 98 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 688 393 +$EndPAD +$EndMODULE MLF20m1 +$MODULE SON008V5060 +Po 73102 59043 0 15 4D137C34 4D13CF7A ~~ +Li SON008V5060 +Sc 4D13CF7A +AR /4C69ED5F/4D13C8C9 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"U11" +T1 0 150 200 200 0 40 N I 25 N"BD9130NV" +DC -1023 1259 -1023 1220 39 21 +DS -984 1200 -984 -1200 39 21 +DS -984 -1200 984 -1200 39 21 +DS 984 -1200 984 1200 39 21 +DS 984 1200 -984 1200 39 21 +$PAD +Sh "PAD" R 1652 1416 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 0 +$EndPAD +$PAD +Sh "1" R 197 355 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -749 1003 +$EndPAD +$PAD +Sh "8" R 197 355 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -749 -1003 +$EndPAD +$PAD +Sh "2" R 197 355 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -249 1003 +$EndPAD +$PAD +Sh "7" R 197 355 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -249 -1003 +$EndPAD +$PAD +Sh "3" R 197 355 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 249 1003 +$EndPAD +$PAD +Sh "6" R 197 355 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 249 -1003 +$EndPAD +$PAD +Sh "4" R 197 355 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 749 1003 +$EndPAD +$PAD +Sh "5" R 197 355 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 749 -1003 +$EndPAD +$EndMODULE SON008V5060 +$MODULE UDFN6 +Po 68559 47728 0 15 4D137C34 4D13CF7B ~~ +Li UDFN6 +Sc 4D13CF7B +AR /4C69ED5F/4D13C8E1 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"U10" +T1 0 150 200 200 0 40 N I 25 N"NCP1529" +DC -511 511 -511 472 39 21 +DS -452 452 -452 -452 39 21 +DS -452 -452 452 -452 39 21 +DS 452 -452 452 452 39 21 +DS 452 452 -452 452 39 21 +$PAD +Sh "PAD" R 668 372 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 0 +$EndPAD +$PAD +Sh "1" R 157 185 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -255 340 +$EndPAD +$PAD +Sh "6" R 157 185 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -255 -340 +$EndPAD +$PAD +Sh "2" R 156 185 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 340 +$EndPAD +$PAD +Sh "5" R 156 185 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 0 -340 +$EndPAD +$PAD +Sh "3" R 157 185 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 255 340 +$EndPAD +$PAD +Sh "4" R 157 185 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po 255 -340 +$EndPAD +$EndMODULE UDFN6 +$COTATION +Ge 0 25 0 +Va 39410 +Te "100.101 mm" +Po 44133 33051 394 591 99 2701 1 +Sb 0 44607 13346 44647 52756 99 +Sd 0 44961 52756 43660 52756 99 +Sg 0 44921 13346 43620 13346 99 +S1 0 44647 52756 44416 52313 99 +S2 0 44647 52756 44877 52313 99 +S3 0 44607 13346 44377 13789 99 +S4 0 44607 13346 44838 13789 99 +$endCOTATION +$COTATION +Ge 0 25 0 +Va 21220 +Te "53.899 mm" +Po 56319 54665 394 591 99 0 1 +Sb 0 45709 54172 66929 54172 99 +Sd 0 66929 53465 66929 55159 99 +Sg 0 45709 53465 45709 55159 99 +S1 0 66929 54172 66486 54402 99 +S2 0 66929 54172 66486 53942 99 +S3 0 45709 54172 46152 54402 99 +S4 0 45709 54172 46152 53942 99 +$endCOTATION +$DRAWSEGMENT +Po 0 66929 13386 45709 13386 150 +De 28 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 66929 52756 66929 13386 150 +De 28 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 45709 52756 66929 52756 150 +De 28 0 900 0 0 +$EndDRAWSEGMENT +$DRAWSEGMENT +Po 0 45709 13386 45709 52756 150 +De 28 0 900 0 0 +$EndDRAWSEGMENT +$TRACK +Po 0 55290 39386 55290 38875 79 -1 +De 0 0 1 0 800 +Po 0 55689 35740 55874 35555 79 -1 +De 0 0 1 0 0 +Po 0 55362 35740 55689 35740 79 -1 +De 0 0 1 0 0 +Po 0 55268 35834 55362 35740 79 -1 +De 0 0 1 0 0 +Po 0 55268 36056 55268 35834 79 -1 +De 0 0 1 0 0 +Po 0 55350 36138 55268 36056 79 -1 +De 0 0 1 0 0 +Po 0 55504 36138 55350 36138 79 -1 +De 0 0 1 0 0 +Po 0 55772 36406 55504 36138 79 -1 +De 0 0 1 0 0 +Po 0 55772 37633 55772 36406 79 -1 +De 0 0 1 0 0 +Po 0 55685 37720 55772 37633 79 -1 +De 0 0 1 0 0 +Po 0 55516 37720 55685 37720 79 -1 +De 0 0 1 0 0 +Po 0 55409 37827 55516 37720 79 -1 +De 0 0 1 0 0 +Po 0 55409 37976 55409 37827 79 -1 +De 0 0 1 0 0 +Po 0 55630 38197 55409 37976 79 -1 +De 0 0 1 0 0 +Po 0 55630 38535 55630 38197 79 -1 +De 0 0 1 0 0 +Po 0 55290 38875 55630 38535 79 -1 +De 0 0 1 0 0 +Po 0 55735 39594 55735 39961 79 -1 +De 15 0 1 0 800 +Po 0 55295 39391 55290 39386 79 -1 +De 0 0 1 0 400 +Po 0 55295 40015 55295 39391 79 -1 +De 0 0 1 0 0 +Po 0 55374 40094 55295 40015 79 -1 +De 0 0 1 0 0 +Po 0 55602 40094 55374 40094 79 -1 +De 0 0 1 0 0 +Po 3 55602 40094 55602 40094 157 -1 +De 15 1 1 0 0 +Po 0 55735 39961 55602 40094 79 -1 +De 15 0 1 0 0 +Po 0 54892 33395 54840 33395 79 -1 +De 15 0 1 0 800 +Po 0 54709 33264 54713 33264 79 -1 +De 0 0 1 0 0 +Po 3 54709 33264 54709 33264 157 -1 +De 15 1 1 0 0 +Po 0 54840 33395 54709 33264 79 -1 +De 15 0 1 0 0 +Po 0 55286 33788 55281 33788 79 -1 +De 15 0 1 0 800 +Po 3 55087 33594 55087 33594 157 -1 +De 15 1 1 0 0 +Po 0 55281 33788 55087 33594 79 -1 +De 15 0 1 0 0 +Po 0 55286 35361 55265 35361 79 -1 +De 15 0 1 0 800 +Po 3 55079 35547 55079 35547 157 -1 +De 15 1 1 0 0 +Po 0 55265 35361 55079 35547 79 -1 +De 15 0 1 0 0 +Po 0 56272 35524 55905 35524 79 -1 +De 0 0 1 0 800 +Po 0 55905 35524 55874 35555 79 -1 +De 0 0 1 0 0 +Po 0 56068 35361 55874 35555 79 -1 +De 15 0 1 0 0 +Po 0 56068 35361 56073 35361 79 -1 +De 15 0 1 0 400 +Po 3 55874 35555 55874 35555 157 -1 +De 15 1 1 0 0 +Po 0 57252 35755 57252 35756 79 -1 +De 15 0 1 0 800 +Po 3 57445 35949 57445 35949 157 -1 +De 15 1 1 0 0 +Po 0 57252 35756 57445 35949 79 -1 +De 15 0 1 0 0 +Po 0 57252 34968 57263 34968 79 -1 +De 15 0 1 0 800 +Po 3 57429 35134 57429 35134 157 -1 +De 15 1 1 0 0 +Po 0 57263 34968 57429 35134 79 -1 +De 15 0 1 0 0 +Po 0 56859 35361 56861 35361 79 -1 +De 15 0 1 0 800 +Po 3 57043 35539 57043 35539 157 -1 +De 15 1 1 0 0 +Po 0 57039 35539 57043 35539 79 -1 +De 15 0 1 0 0 +Po 0 56861 35361 57039 35539 79 -1 +De 15 0 1 0 0 +Po 0 56272 35148 56596 35148 79 -1 +De 0 0 1 0 800 +Po 0 56596 35148 56622 35122 79 -1 +De 0 0 1 0 0 +Po 0 56272 33600 55883 33600 79 -1 +De 0 0 1 0 800 +Po 0 55883 33600 55874 33591 79 -1 +De 0 0 1 0 0 +Po 0 55509 34382 55509 34009 79 -1 +De 0 0 1 0 800 +Po 0 55509 34009 55500 34000 79 -1 +De 0 0 1 0 0 +Po 0 57030 34382 57030 34735 79 -1 +De 0 0 1 0 800 +Po 0 56869 34574 57043 34748 79 -1 +De 15 0 1 0 0 +Po 3 57043 34748 57043 34748 157 -1 +De 15 1 1 0 0 +Po 0 56869 34574 56859 34574 79 -1 +De 15 0 1 0 400 +Po 0 57030 34735 57043 34748 79 -1 +De 0 0 1 0 0 +Po 0 55286 34574 55277 34574 79 -1 +De 15 0 1 0 800 +Po 0 55098 34752 55098 34756 79 -1 +De 0 0 1 0 0 +Po 0 55110 34740 55098 34752 79 -1 +De 0 0 1 0 0 +Po 3 55110 34740 55110 34740 157 -1 +De 15 1 1 0 0 +Po 0 55111 34740 55110 34740 79 -1 +De 15 0 1 0 0 +Po 0 55277 34574 55111 34740 79 -1 +De 15 0 1 0 0 +Po 0 57252 34182 57252 34177 79 -1 +De 15 0 1 0 800 +Po 3 57437 33992 57437 33992 157 -1 +De 15 1 1 0 0 +Po 0 57252 34177 57437 33992 79 -1 +De 15 0 1 0 0 +Po 0 55282 34574 55286 34574 79 -1 +De 15 0 1 0 400 +Po 0 56073 34574 56064 34574 79 -1 +De 15 0 1 0 800 +Po 3 55894 34744 55894 34744 157 -1 +De 15 1 1 0 0 +Po 0 56064 34574 55894 34744 79 -1 +De 15 0 1 0 0 +Po 0 56465 34182 56465 34169 79 -1 +De 15 0 1 0 800 +Po 3 56630 34004 56630 34004 157 -1 +De 15 1 1 0 0 +Po 0 56465 34169 56630 34004 79 -1 +De 15 0 1 0 0 +Po 0 56465 34968 56468 34968 79 -1 +De 15 0 1 0 800 +Po 0 56622 35122 56622 35114 79 -1 +De 0 0 1 0 0 +Po 3 56622 35122 56622 35122 157 -1 +De 15 1 1 0 0 +Po 0 56468 34968 56622 35122 79 -1 +De 15 0 1 0 0 +Po 0 55679 34968 55679 34971 79 -1 +De 15 0 1 0 800 +Po 3 55520 35130 55520 35130 157 -1 +De 15 1 1 0 0 +Po 0 55679 34971 55520 35130 79 -1 +De 15 0 1 0 0 +Po 0 55679 34182 55679 34179 79 -1 +De 15 0 1 0 800 +Po 0 55500 34000 55504 34000 79 -1 +De 0 0 1 0 0 +Po 3 55500 34000 55500 34000 157 -1 +De 15 1 1 0 0 +Po 0 55679 34179 55500 34000 79 -1 +De 15 0 1 0 0 +Po 0 56859 33788 56859 33783 79 -1 +De 15 0 1 0 800 +Po 0 56859 33783 57051 33591 79 -1 +De 15 0 1 0 0 +Po 0 57252 33395 57247 33395 79 -1 +De 15 0 1 0 800 +Po 0 57047 33587 57047 33583 79 -1 +De 0 0 1 0 0 +Po 0 57051 33591 57047 33587 79 -1 +De 0 0 1 0 0 +Po 3 57051 33591 57051 33591 157 -1 +De 15 1 1 0 0 +Po 0 57247 33395 57051 33591 79 -1 +De 15 0 1 0 0 +Po 0 55679 33395 55679 33396 79 -1 +De 15 0 1 0 800 +Po 0 55679 33396 55874 33591 79 -1 +De 15 0 1 0 0 +Po 3 55874 33591 55874 33591 157 -1 +De 15 1 1 0 0 +Po 0 56071 33788 55874 33591 79 -1 +De 15 0 1 0 0 +Po 0 56073 33788 56071 33788 79 -1 +De 15 0 1 0 800 +Po 0 55874 33591 55874 33587 79 -1 +De 0 0 1 0 0 +Po 0 56465 33395 56465 33382 79 -1 +De 15 0 1 0 800 +Po 3 56634 33213 56634 33213 157 -1 +De 15 1 1 0 0 +Po 0 56465 33382 56634 33213 79 -1 +De 15 0 1 0 0 +Po 0 48851 26272 49099 26272 118 -1 +De 0 0 2 0 800 +Po 0 50069 27242 50069 27352 118 -1 +De 0 0 2 0 0 +Po 0 49099 26272 50069 27242 118 -1 +De 0 0 2 0 0 +Po 0 48851 25878 48851 26272 79 -1 +De 0 0 2 0 C00 +Po 0 50288 27354 50071 27354 79 -1 +De 15 0 2 0 800 +Po 0 50071 27354 50069 27352 79 -1 +De 15 0 2 0 0 +Po 3 50069 27352 50069 27352 157 -1 +De 15 1 2 0 0 +Po 0 49960 27461 49930 27461 39 -1 +De 0 0 2 0 400 +Po 0 50069 27352 49960 27461 39 -1 +De 0 0 2 0 0 +Po 0 56073 36543 56162 36543 59 -1 +De 15 0 3 0 800 +Po 3 56272 36433 56272 36433 157 -1 +De 15 1 3 0 0 +Po 0 56162 36543 56272 36433 59 -1 +De 15 0 3 0 0 +Po 0 59007 34382 59007 34347 59 -1 +De 0 0 3 0 800 +Po 0 58827 33398 58827 33395 59 -1 +De 15 0 3 0 400 +Po 0 58634 33591 58827 33398 59 -1 +De 15 0 3 0 0 +Po 3 58634 33591 58634 33591 157 -1 +De 15 1 3 0 0 +Po 0 58807 33764 58634 33591 59 -1 +De 0 0 3 0 0 +Po 0 59094 33764 58807 33764 59 -1 +De 0 0 3 0 0 +Po 0 59217 33887 59094 33764 59 -1 +De 0 0 3 0 0 +Po 0 59217 34137 59217 33887 59 -1 +De 0 0 3 0 0 +Po 0 59007 34347 59217 34137 59 -1 +De 0 0 3 0 0 +Po 0 59843 31213 59843 31185 79 -1 +De 0 0 3 0 0 +Po 0 60980 30048 61043 30048 79 -1 +De 0 0 3 0 400 +Po 0 59843 31185 60980 30048 79 -1 +De 0 0 3 0 0 +Po 0 59366 31673 59457 31673 79 -1 +De 0 0 3 0 0 +Po 0 60008 31048 60008 31032 79 -1 +De 15 0 3 0 400 +Po 0 59843 31213 60008 31048 79 -1 +De 15 0 3 0 0 +Po 3 59843 31213 59843 31213 157 -1 +De 15 1 3 0 0 +Po 0 59843 31287 59843 31213 79 -1 +De 0 0 3 0 0 +Po 0 59457 31673 59843 31287 79 -1 +De 0 0 3 0 0 +Po 0 59811 32417 59681 32417 79 -1 +De 0 0 3 0 0 +Po 0 59366 32102 59366 31673 79 -1 +De 0 0 3 0 0 +Po 0 59681 32417 59366 32102 79 -1 +De 0 0 3 0 0 +Po 0 50190 35166 50190 35102 79 -1 +De 0 0 3 0 800 +Po 0 50402 34890 50472 34890 79 -1 +De 15 0 3 0 0 +Po 0 50394 34898 50402 34890 79 -1 +De 15 0 3 0 0 +Po 3 50394 34898 50394 34898 157 -1 +De 15 1 3 0 0 +Po 0 50190 35102 50394 34898 79 -1 +De 0 0 3 0 0 +Po 0 50654 38909 50826 38909 118 -1 +De 15 0 3 0 0 +Po 3 50654 38909 50654 38909 157 -1 +De 15 1 3 0 0 +Po 0 50826 38909 50995 38740 118 -1 +De 15 0 3 0 400 +Po 0 49090 39457 49090 39005 118 -1 +De 15 0 3 0 800 +Po 0 49090 39005 49355 38740 118 -1 +De 15 0 3 0 0 +Po 0 49355 38740 50995 38740 118 -1 +De 15 0 3 0 400 +Po 0 47035 32862 46587 32414 118 -1 +De 0 0 3 0 0 +Po 0 46587 30949 47005 30531 118 -1 +De 0 0 3 0 400 +Po 0 46587 32414 46587 30949 118 -1 +De 0 0 3 0 0 +Po 0 46599 33035 46531 33103 118 -1 +De 0 0 3 0 0 +Po 0 46531 35388 46678 35535 118 -1 +De 0 0 3 0 400 +Po 0 46531 33103 46531 35388 118 -1 +De 0 0 3 0 0 +Po 0 47035 32862 46968 32929 118 -1 +De 0 0 3 0 0 +Po 0 46705 32929 46599 33035 118 -1 +De 0 0 3 0 0 +Po 0 46599 33035 46587 33047 118 -1 +De 0 0 3 0 0 +Po 0 46767 32929 46705 32929 118 -1 +De 0 0 3 0 0 +Po 0 46968 32929 46767 32929 118 -1 +De 0 0 3 0 0 +Po 0 46643 35925 46690 35972 118 -1 +De 15 0 3 0 800 +Po 0 46690 35972 46925 35972 118 -1 +De 15 0 3 0 0 +Po 3 46925 35972 46925 35972 157 -1 +De 15 1 3 0 0 +Po 0 46925 35972 46854 35972 118 -1 +De 0 0 3 0 0 +Po 0 46854 35972 46794 35972 118 -1 +De 0 0 3 0 0 +Po 0 46794 35972 46794 35920 118 -1 +De 0 0 3 0 0 +Po 0 46794 35920 46794 35651 118 -1 +De 0 0 3 0 0 +Po 0 46794 35651 46678 35535 118 -1 +De 0 0 3 0 400 +Po 0 47005 30531 47005 30485 118 -1 +De 0 0 3 0 800 +Po 0 47005 30485 46323 29803 118 -1 +De 0 0 3 0 0 +Po 0 46323 29803 46331 29811 118 -1 +De 0 0 3 0 0 +Po 3 46331 29811 46331 29811 157 -1 +De 15 1 3 0 0 +Po 0 46331 29811 46430 29712 118 -1 +De 15 0 3 0 0 +Po 0 46430 29712 46430 29400 118 -1 +De 15 0 3 0 400 +Po 0 47617 33169 47617 33019 79 -1 +De 0 0 3 0 800 +Po 0 47460 32862 47035 32862 79 -1 +De 0 0 3 0 0 +Po 0 47617 33019 47460 32862 79 -1 +De 0 0 3 0 0 +Po 0 46949 32937 46949 32933 79 -1 +De 0 0 3 0 0 +Po 0 46949 32933 47020 32862 79 -1 +De 0 0 3 0 0 +Po 0 47020 32862 47035 32862 79 -1 +De 0 0 3 0 0 +Po 0 47039 32866 47157 32866 79 -1 +De 2 0 3 0 0 +Po 3 47035 32862 47035 32862 157 -1 +De 15 1 3 0 0 +Po 0 47035 32862 47039 32866 79 -1 +De 2 0 3 0 0 +Po 0 46949 32937 46957 32937 79 -1 +De 0 0 3 0 0 +Po 0 46832 37071 46832 36915 79 -1 +De 0 0 3 0 800 +Po 0 46832 36915 46748 36831 79 -1 +De 0 0 3 0 0 +Po 0 46748 36831 46748 35634 79 -1 +De 0 0 3 0 0 +Po 0 46748 35634 46678 35564 79 -1 +De 0 0 3 0 0 +Po 0 46678 35564 46678 35535 79 -1 +De 0 0 3 0 400 +Po 0 46643 37460 46816 37460 79 -1 +De 15 0 3 0 800 +Po 0 46839 37110 46843 37106 79 -1 +De 2 0 3 0 0 +Po 0 46839 37437 46839 37110 79 -1 +De 2 0 3 0 0 +Po 0 46827 37449 46839 37437 79 -1 +De 2 0 3 0 0 +Po 3 46827 37449 46827 37449 157 -1 +De 15 1 3 0 0 +Po 0 46816 37460 46827 37449 79 -1 +De 15 0 3 0 0 +Po 0 60256 39098 60272 39098 79 -1 +De 0 0 3 0 0 +Po 0 60843 38527 61000 38527 79 -1 +De 0 0 3 0 400 +Po 0 60272 39098 60843 38527 79 -1 +De 0 0 3 0 0 +Po 0 61000 38527 60798 38527 79 -1 +De 0 0 3 0 800 +Po 0 60798 38527 60370 38099 79 -1 +De 0 0 3 0 0 +Po 0 60370 38099 60370 37520 79 -1 +De 0 0 3 0 0 +Po 0 60370 37520 60607 37283 79 -1 +De 0 0 3 0 0 +Po 0 56073 36543 56073 36541 79 -1 +De 15 0 3 0 800 +Po 0 66016 34698 65859 34698 79 -1 +De 0 0 3 0 800 +Po 0 65778 34391 65956 34391 79 -1 +De 15 0 3 0 400 +Po 0 65665 34504 65778 34391 79 -1 +De 15 0 3 0 0 +Po 3 65665 34504 65665 34504 157 -1 +De 15 1 3 0 0 +Po 0 65859 34698 65665 34504 79 -1 +De 0 0 3 0 0 +Po 0 58181 31575 58185 31575 79 -1 +De 2 0 3 0 0 +Po 0 58185 31575 58417 31807 79 -1 +De 2 0 3 0 0 +Po 0 58417 31807 59196 31807 79 -1 +De 2 0 3 0 0 +Po 0 59196 31807 59330 31673 79 -1 +De 2 0 3 0 0 +Po 0 59330 31673 59366 31673 79 -1 +De 2 0 3 0 0 +Po 0 59221 31818 59366 31673 79 -1 +De 15 0 3 0 0 +Po 0 59221 31818 59221 31820 79 -1 +De 15 0 3 0 400 +Po 3 59366 31673 59366 31673 157 -1 +De 15 1 3 0 0 +Po 0 58040 31426 58193 31579 79 -1 +De 15 0 3 0 800 +Po 0 58197 31575 58181 31575 79 -1 +De 2 0 3 0 0 +Po 0 58181 31575 58224 31575 79 -1 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100644 --- a/xue-rnc/xue-rnc.brd +++ b/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Thu 23 Dec 2010 05:39:51 PM COT +PCBNEW-BOARD Version 1 date Sun 26 Dec 2010 07:07:39 PM COT # Created by Pcbnew(2010-10-01 BZR 2513)-testing @@ -6,21 +6,21 @@ $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 13FF801F -Links 737 -NoConn 57 -Di 45633 12844 74358 60460 +Links 814 +NoConn 134 +Di 45633 12844 74358 63523 Ndraw 6 Ntrack 4940 Nzone 0 BoardThickness 630 -Nmodule 172 -Nnets 308 +Nmodule 206 +Nnets 330 $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "23 dec 2010" +Date "27 dec 2010" Rev "" Comp "" Comment1 "" @@ -107,23 +107,23 @@ Na 7 "/ether/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/ether/ETH_CRS" +Na 8 "/ether/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/ether/ETH_INT" +Na 9 "/ether/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/ether/ETH_LED0" +Na 10 "/ether/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/ether/ETH_LED1" +Na 11 "/ether/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/ether/ETH_MDIO" +Na 12 "/ether/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT @@ -135,91 +135,91 @@ Na 14 "/ether/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/ether/ETH_RXDV" +Na 15 "/ether/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/ether/ETH_RXER" +Na 16 "/ether/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/ether/ETH_TXER" +Na 17 "/ether/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/ether/MAG_RX+" +Na 18 "/ether/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/ether/MAG_RX-" +Na 19 "/ether/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/ether/MAG_SHIELD" +Na 20 "/ether/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/ether/MAG_TX+" +Na 21 "/ether/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/ether/MAG_TX-" +Na 22 "/ether/MAG_RX+" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/expansion/FPGA_BANK0_IO_1" +Na 23 "/ether/MAG_RX-" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/expansion/FPGA_BANK0_IO_10" +Na 24 "/ether/MAG_SHIELD" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/expansion/FPGA_BANK0_IO_12" +Na 25 "/ether/MAG_TX+" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/expansion/FPGA_BANK0_IO_14" +Na 26 "/ether/MAG_TX-" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/expansion/FPGA_BANK0_IO_15" +Na 27 "/expansion/FPGA_BANK0_IO_1" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/expansion/FPGA_BANK0_IO_17" +Na 28 "/expansion/FPGA_BANK0_IO_12" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/expansion/FPGA_BANK0_IO_21" +Na 29 "/expansion/FPGA_BANK0_IO_15" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/expansion/FPGA_BANK0_IO_24" +Na 30 "/expansion/FPGA_BANK0_IO_17" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/expansion/FPGA_BANK0_IO_27" +Na 31 "/expansion/FPGA_BANK0_IO_18" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/expansion/FPGA_BANK0_IO_29" +Na 32 "/expansion/FPGA_BANK0_IO_21" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/expansion/FPGA_BANK0_IO_3" +Na 33 "/expansion/FPGA_BANK0_IO_25" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/expansion/FPGA_BANK0_IO_30" +Na 34 "/expansion/FPGA_BANK0_IO_27" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/expansion/FPGA_BANK0_IO_32" +Na 35 "/expansion/FPGA_BANK0_IO_28" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/expansion/FPGA_BANK0_IO_34" +Na 36 "/expansion/FPGA_BANK0_IO_32" St ~ $EndEQUIPOT $EQUIPOT @@ -239,23 +239,23 @@ Na 40 "/expansion/FPGA_BANK0_IO_43" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/expansion/FPGA_BANK0_IO_45" +Na 41 "/expansion/FPGA_BANK0_IO_46" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/expansion/FPGA_BANK0_IO_46" +Na 42 "/expansion/FPGA_BANK0_IO_49" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/expansion/FPGA_BANK0_IO_47" +Na 43 "/expansion/FPGA_BANK0_IO_5" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/expansion/FPGA_BANK0_IO_49" +Na 44 "/expansion/FPGA_BANK0_IO_50" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/expansion/FPGA_BANK0_IO_5" +Na 45 "/expansion/FPGA_BANK0_IO_52" St ~ $EndEQUIPOT $EQUIPOT @@ -267,267 +267,267 @@ Na 47 "/expansion/FPGA_BANK0_IO_54" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/expansion/FPGA_BANK0_IO_57" +Na 48 "/expansion/FPGA_BANK0_IO_56" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/expansion/FPGA_BANK0_IO_60" +Na 49 "/expansion/FPGA_BANK0_IO_63" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/expansion/FPGA_BANK0_IO_63" +Na 50 "/expansion/FPGA_BANK0_IO_9" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/expansion/FPGA_BANK0_IO_8" +Na 51 "/flash/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/expansion/FPGA_BANK0_IO_9" +Na 52 "/flash/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/flash/NF_CLE" +Na 53 "/flash/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/flash/NF_D2" +Na 54 "/flash/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/flash/NF_D4" +Na 55 "/flash/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/flash/NF_D5" +Na 56 "/flash/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/flash/NF_RE_N" +Na 57 "/flash/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/flash/NF_WE_N" +Na 58 "/fpga1/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/flash/SD_CMD" +Na 59 "/fpga1/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/flash/SD_DAT1" +Na 60 "/fpga1/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/flash/SD_DAT2" +Na 61 "/fpga1/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/flash/SD_DAT3" +Na 62 "/fpga1/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/fpga1/ETH_CLK" +Na 63 "/fpga1/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/fpga1/ETH_COL" +Na 64 "/fpga1/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/fpga1/ETH_MDC" +Na 65 "/fpga1/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/fpga1/ETH_RESET_N" +Na 66 "/fpga1/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/fpga1/ETH_RXC" +Na 67 "/fpga1/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/fpga1/ETH_RXD1" +Na 68 "/fpga1/FPGA_BANK0_IO_10" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/fpga1/ETH_RXD2" +Na 69 "/fpga1/FPGA_BANK0_IO_11" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/fpga1/ETH_RXD3" +Na 70 "/fpga1/FPGA_BANK0_IO_14" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/fpga1/ETH_TXC" +Na 71 "/fpga1/FPGA_BANK0_IO_2" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/fpga1/ETH_TXD0" +Na 72 "/fpga1/FPGA_BANK0_IO_20" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/fpga1/ETH_TXD1" +Na 73 "/fpga1/FPGA_BANK0_IO_22" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/fpga1/ETH_TXD2" +Na 74 "/fpga1/FPGA_BANK0_IO_24" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/fpga1/ETH_TXD3" +Na 75 "/fpga1/FPGA_BANK0_IO_29" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/fpga1/ETH_TXEN" +Na 76 "/fpga1/FPGA_BANK0_IO_3" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/fpga1/FPGA_BANK0_IO_11" +Na 77 "/fpga1/FPGA_BANK0_IO_30" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/fpga1/FPGA_BANK0_IO_18" +Na 78 "/fpga1/FPGA_BANK0_IO_33" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/fpga1/FPGA_BANK0_IO_2" +Na 79 "/fpga1/FPGA_BANK0_IO_34" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/fpga1/FPGA_BANK0_IO_20" +Na 80 "/fpga1/FPGA_BANK0_IO_40" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/fpga1/FPGA_BANK0_IO_22" +Na 81 "/fpga1/FPGA_BANK0_IO_44" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/fpga1/FPGA_BANK0_IO_25" +Na 82 "/fpga1/FPGA_BANK0_IO_45" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/fpga1/FPGA_BANK0_IO_28" +Na 83 "/fpga1/FPGA_BANK0_IO_47" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/fpga1/FPGA_BANK0_IO_33" +Na 84 "/fpga1/FPGA_BANK0_IO_48" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/fpga1/FPGA_BANK0_IO_40" +Na 85 "/fpga1/FPGA_BANK0_IO_51" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/fpga1/FPGA_BANK0_IO_44" +Na 86 "/fpga1/FPGA_BANK0_IO_57" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/fpga1/FPGA_BANK0_IO_48" +Na 87 "/fpga1/FPGA_BANK0_IO_58" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/fpga1/FPGA_BANK0_IO_50" +Na 88 "/fpga1/FPGA_BANK0_IO_6" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/fpga1/FPGA_BANK0_IO_51" +Na 89 "/fpga1/FPGA_BANK0_IO_60" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/fpga1/FPGA_BANK0_IO_52" +Na 90 "/fpga1/FPGA_BANK0_IO_62" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/fpga1/FPGA_BANK0_IO_56" +Na 91 "/fpga1/FPGA_BANK0_IO_7" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/fpga1/FPGA_BANK0_IO_58" +Na 92 "/fpga1/FPGA_BANK0_IO_8" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/fpga1/FPGA_BANK0_IO_6" +Na 93 "/fpga1/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/fpga1/FPGA_BANK0_IO_62" +Na 94 "/fpga1/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/fpga1/FPGA_BANK0_IO_7" +Na 95 "/fpga1/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/fpga1/NF_ALE" +Na 96 "/fpga1/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/fpga1/NF_CS1_N" +Na 97 "/fpga1/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/fpga1/NF_D0" +Na 98 "/fpga1/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/fpga1/NF_D1" +Na 99 "/fpga1/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/fpga1/NF_D3" +Na 100 "/fpga1/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/fpga1/NF_D6" +Na 101 "/fpga1/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/fpga1/NF_D7" +Na 102 "/fpga1/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/fpga1/NF_RNB" +Na 103 "/fpga1/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/fpga1/PROG_CCLK" +Na 104 "/fpga1/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/fpga1/PROG_CSO" +Na 105 "/fpga1/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/fpga1/PROG_MISO0" +Na 106 "/fpga1/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/fpga1/PROG_MISO1" +Na 107 "/fpga1/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/fpga1/PROG_MISO2" +Na 108 "/fpga1/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/fpga1/PROG_MISO3" +Na 109 "/fpga1/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/fpga1/SD_CLK" +Na 110 "/fpga1/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/fpga1/SD_DAT0" +Na 111 "/fpga1/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/fpga2/M0_A1" +Na 112 "/fpga2/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/fpga2/M0_A10" +Na 113 "/fpga2/M0_A1" St ~ $EndEQUIPOT $EQUIPOT @@ -535,15 +535,15 @@ Na 114 "/fpga2/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/fpga2/M0_A12" +Na 115 "/fpga2/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/fpga2/M0_A2" +Na 116 "/fpga2/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/fpga2/M0_A3" +Na 117 "/fpga2/M0_A4" St ~ $EndEQUIPOT $EQUIPOT @@ -559,39 +559,39 @@ Na 120 "/fpga2/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/fpga2/M0_A8" +Na 121 "/fpga2/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/fpga2/M0_A9" +Na 122 "/fpga2/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/fpga2/M0_BA1" +Na 123 "/fpga2/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/fpga2/M0_CKE" +Na 124 "/fpga2/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/fpga2/M0_CLK" +Na 125 "/fpga2/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/fpga2/M0_DQ0" +Na 126 "/fpga2/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/fpga2/M0_DQ10" +Na 127 "/fpga2/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/fpga2/M0_DQ11" +Na 128 "/fpga2/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/fpga2/M0_DQ12" +Na 129 "/fpga2/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT @@ -599,7 +599,7 @@ Na 130 "/fpga2/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/fpga2/M0_DQ2" +Na 131 "/fpga2/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT @@ -607,19 +607,19 @@ Na 132 "/fpga2/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/fpga2/M0_DQ9" +Na 133 "/fpga2/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/fpga2/M0_LDQS" +Na 134 "/fpga2/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/fpga2/M0_RAS#" +Na 135 "/fpga2/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/fpga2/M0_UDM" +Na 136 "/fpga2/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT @@ -627,23 +627,23 @@ Na 137 "/fpga2/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/fpga2/M1_A0" +Na 138 "/fpga2/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/fpga2/M1_A1" +Na 139 "/fpga2/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/fpga2/M1_A2" +Na 140 "/fpga2/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/fpga2/M1_A3" +Na 141 "/fpga2/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/fpga2/M1_A4" +Na 142 "/fpga2/M1_A2" St ~ $EndEQUIPOT $EQUIPOT @@ -651,543 +651,543 @@ Na 143 "/fpga2/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/fpga2/M1_BA0" +Na 144 "/fpga2/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/fpga2/M1_BA1" +Na 145 "/fpga2/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/fpga2/M1_CAS#" +Na 146 "/fpga2/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/fpga2/M1_CKE" +Na 147 "/fpga2/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/fpga2/M1_DQ10" +Na 148 "/fpga2/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/fpga2/M1_DQ12" +Na 149 "/fpga2/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/fpga2/M1_DQ13" +Na 150 "/fpga2/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/fpga2/M1_DQ3" +Na 151 "/fpga2/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/fpga2/M1_DQ4" +Na 152 "/fpga2/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/fpga2/M1_DQ5" +Na 153 "/fpga2/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/fpga2/M1_DQ6" +Na 154 "/fpga2/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/fpga2/M1_DQ7" +Na 155 "/fpga2/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/fpga2/M1_DQ8" +Na 156 "/fpga2/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/fpga2/M1_LDQS" +Na 157 "/fpga2/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/fpga2/M1_RAS#" +Na 158 "/fpga2/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/fpga2/M1_UDM" +Na 159 "/fpga2/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/fpga2/M1_UDQS" +Na 160 "/fpga2/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/fpga2/M1_WE#" +Na 161 "/fpga2/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/fpga2/R_M0_A0" +Na 162 "/fpga2/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/fpga2/R_M0_A1" +Na 163 "/fpga2/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/fpga2/R_M0_A10" +Na 164 "/fpga2/R_M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/fpga2/R_M0_A11" +Na 165 "/fpga2/R_M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/fpga2/R_M0_A12" +Na 166 "/fpga2/R_M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/fpga2/R_M0_A2" +Na 167 "/fpga2/R_M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/fpga2/R_M0_A3" +Na 168 "/fpga2/R_M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/fpga2/R_M0_A4" +Na 169 "/fpga2/R_M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/fpga2/R_M0_A5" +Na 170 "/fpga2/R_M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/fpga2/R_M0_A6" +Na 171 "/fpga2/R_M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/fpga2/R_M0_A7" +Na 172 "/fpga2/R_M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/fpga2/R_M0_A8" +Na 173 "/fpga2/R_M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/fpga2/R_M0_A9" +Na 174 "/fpga2/R_M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/fpga2/R_M0_BA0" +Na 175 "/fpga2/R_M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/fpga2/R_M0_BA1" +Na 176 "/fpga2/R_M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/fpga2/R_M0_CAS#" +Na 177 "/fpga2/R_M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/fpga2/R_M0_CKE" +Na 178 "/fpga2/R_M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/fpga2/R_M0_DQ0" +Na 179 "/fpga2/R_M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 180 "/fpga2/R_M0_DQ1" +Na 180 "/fpga2/R_M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/fpga2/R_M0_DQ10" +Na 181 "/fpga2/R_M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/fpga2/R_M0_DQ11" +Na 182 "/fpga2/R_M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/fpga2/R_M0_DQ12" +Na 183 "/fpga2/R_M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/fpga2/R_M0_DQ13" +Na 184 "/fpga2/R_M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "/fpga2/R_M0_DQ14" +Na 185 "/fpga2/R_M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "/fpga2/R_M0_DQ15" +Na 186 "/fpga2/R_M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "/fpga2/R_M0_DQ2" +Na 187 "/fpga2/R_M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "/fpga2/R_M0_DQ3" +Na 188 "/fpga2/R_M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "/fpga2/R_M0_DQ4" +Na 189 "/fpga2/R_M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "/fpga2/R_M0_DQ5" +Na 190 "/fpga2/R_M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "/fpga2/R_M0_DQ6" +Na 191 "/fpga2/R_M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "/fpga2/R_M0_DQ7" +Na 192 "/fpga2/R_M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "/fpga2/R_M0_DQ8" +Na 193 "/fpga2/R_M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "/fpga2/R_M0_DQ9" +Na 194 "/fpga2/R_M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "/fpga2/R_M0_LDM" +Na 195 "/fpga2/R_M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "/fpga2/R_M0_LDQS" +Na 196 "/fpga2/R_M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "/fpga2/R_M0_RAS#" +Na 197 "/fpga2/R_M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "/fpga2/R_M0_UDM" +Na 198 "/fpga2/R_M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "/fpga2/R_M0_UDQS" +Na 199 "/fpga2/R_M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "/fpga2/R_M0_WE#" +Na 200 "/fpga2/R_M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 201 "/fpga2/R_M1_A0" +Na 201 "/fpga2/R_M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 202 "/fpga2/R_M1_A1" +Na 202 "/fpga2/R_M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 203 "/fpga2/R_M1_A10" +Na 203 "/fpga2/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 204 "/fpga2/R_M1_A11" +Na 204 "/fpga2/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 205 "/fpga2/R_M1_A12" +Na 205 "/fpga2/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 206 "/fpga2/R_M1_A2" +Na 206 "/fpga2/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 207 "/fpga2/R_M1_A3" +Na 207 "/fpga2/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 208 "/fpga2/R_M1_A4" +Na 208 "/fpga2/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 209 "/fpga2/R_M1_A5" +Na 209 "/fpga2/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 210 "/fpga2/R_M1_A6" +Na 210 "/fpga2/R_M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 211 "/fpga2/R_M1_A7" +Na 211 "/fpga2/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 212 "/fpga2/R_M1_A8" +Na 212 "/fpga2/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 213 "/fpga2/R_M1_A9" +Na 213 "/fpga2/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 214 "/fpga2/R_M1_BA0" +Na 214 "/fpga2/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 215 "/fpga2/R_M1_BA1" +Na 215 "/fpga2/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 216 "/fpga2/R_M1_CAS#" +Na 216 "/fpga2/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 217 "/fpga2/R_M1_CKE" +Na 217 "/fpga2/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 218 "/fpga2/R_M1_CS#" +Na 218 "/fpga2/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 219 "/fpga2/R_M1_DQ0" +Na 219 "/fpga2/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 220 "/fpga2/R_M1_DQ1" +Na 220 "/fpga2/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 221 "/fpga2/R_M1_DQ10" +Na 221 "/fpga2/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 222 "/fpga2/R_M1_DQ11" +Na 222 "/fpga2/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 223 "/fpga2/R_M1_DQ12" +Na 223 "/fpga2/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 224 "/fpga2/R_M1_DQ13" +Na 224 "/fpga2/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 225 "/fpga2/R_M1_DQ14" +Na 225 "/fpga2/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 226 "/fpga2/R_M1_DQ15" +Na 226 "/fpga2/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 227 "/fpga2/R_M1_DQ2" +Na 227 "/fpga2/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 228 "/fpga2/R_M1_DQ3" +Na 228 "/fpga2/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 229 "/fpga2/R_M1_DQ4" +Na 229 "/fpga2/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 230 "/fpga2/R_M1_DQ5" +Na 230 "/fpga2/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 231 "/fpga2/R_M1_DQ6" +Na 231 "/fpga2/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 232 "/fpga2/R_M1_DQ7" +Na 232 "/fpga2/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 233 "/fpga2/R_M1_DQ8" +Na 233 "/fpga2/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 234 "/fpga2/R_M1_DQ9" +Na 234 "/fpga2/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 235 "/fpga2/R_M1_LDM" +Na 235 "/fpga2/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 236 "/fpga2/R_M1_LDQS" +Na 236 "/fpga2/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 237 "/fpga2/R_M1_RAS#" +Na 237 "/fpga2/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 238 "/fpga2/R_M1_UDM" +Na 238 "/fpga2/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 239 "/fpga2/R_M1_UDQS" +Na 239 "/fpga2/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 240 "/fpga2/R_M1_WE#" +Na 240 "/fpga2/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 241 "/fpga2/USBA_RCV" +Na 241 "/fpga2/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 242 "/fpga2/USBA_VM" +Na 242 "/fpga2/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 243 "/fpga2/USBA_VP" +Na 243 "/fpga2/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 244 "/fpga2/USBD_RCV" +Na 244 "/fpga2/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 245 "/sdram/M0_A0" +Na 245 "/fpga2/USBD_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 246 "/sdram/M0_A4" +Na 246 "/fpga2/USBD_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 247 "/sdram/M0_BA0" +Na 247 "/fpga2/USBD_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 248 "/sdram/M0_CAS#" +Na 248 "/sdram/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 249 "/sdram/M0_CLK#" +Na 249 "/sdram/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 250 "/sdram/M0_DQ1" +Na 250 "/sdram/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 251 "/sdram/M0_DQ13" +Na 251 "/sdram/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 252 "/sdram/M0_DQ15" +Na 252 "/sdram/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 253 "/sdram/M0_DQ4" +Na 253 "/sdram/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 254 "/sdram/M0_DQ5" +Na 254 "/sdram/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 255 "/sdram/M0_DQ6" +Na 255 "/sdram/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 256 "/sdram/M0_DQ7" +Na 256 "/sdram/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 257 "/sdram/M0_DQ8" +Na 257 "/sdram/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 258 "/sdram/M0_LDM" +Na 258 "/sdram/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 259 "/sdram/M0_VREF" +Na 259 "/sdram/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 260 "/sdram/M0_WE#" +Na 260 "/sdram/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 261 "/sdram/M1_A10" +Na 261 "/sdram/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 262 "/sdram/M1_A11" +Na 262 "/sdram/M0_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 263 "/sdram/M1_A12" +Na 263 "/sdram/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 264 "/sdram/M1_A6" +Na 264 "/sdram/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 265 "/sdram/M1_A7" +Na 265 "/sdram/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 266 "/sdram/M1_A8" +Na 266 "/sdram/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 267 "/sdram/M1_A9" +Na 267 "/sdram/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 268 "/sdram/M1_CLK" +Na 268 "/sdram/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 269 "/sdram/M1_CLK#" +Na 269 "/sdram/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 270 "/sdram/M1_CS#" +Na 270 "/sdram/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 271 "/sdram/M1_DQ0" +Na 271 "/sdram/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 272 "/sdram/M1_DQ1" +Na 272 "/sdram/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 273 "/sdram/M1_DQ11" +Na 273 "/sdram/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 274 "/sdram/M1_DQ14" +Na 274 "/sdram/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 275 "/sdram/M1_DQ15" +Na 275 "/sdram/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 276 "/sdram/M1_DQ2" +Na 276 "/sdram/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 277 "/sdram/M1_DQ9" +Na 277 "/sdram/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 278 "/sdram/M1_LDM" +Na 278 "/sdram/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT @@ -1195,35 +1195,35 @@ Na 279 "/sdram/M1_VREF" St ~ $EndEQUIPOT $EQUIPOT -Na 280 "/usb/USBA_D+" +Na 280 "/sdram/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 281 "/usb/USBA_D-" +Na 281 "/usb/USBA_D+" St ~ $EndEQUIPOT $EQUIPOT -Na 282 "/usb/USBA_OE_N" +Na 282 "/usb/USBA_D-" St ~ $EndEQUIPOT $EQUIPOT -Na 283 "/usb/USBA_SPD" +Na 283 "/usb/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 284 "/usb/USBD_D+" +Na 284 "/usb/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 285 "/usb/USBD_D-" +Na 285 "/usb/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 286 "/usb/USBD_OE_N" +Na 286 "/usb/USBD_D+" St ~ $EndEQUIPOT $EQUIPOT -Na 287 "/usb/USBD_SPD" +Na 287 "/usb/USBD_D-" St ~ $EndEQUIPOT $EQUIPOT @@ -1251,59 +1251,147 @@ Na 293 "N-000120" St ~ $EndEQUIPOT $EQUIPOT -Na 294 "N-000121" +Na 294 "N-000131" St ~ $EndEQUIPOT $EQUIPOT -Na 295 "N-000133" +Na 295 "N-000132" St ~ $EndEQUIPOT $EQUIPOT -Na 296 "N-000142" +Na 296 "N-000141" St ~ $EndEQUIPOT $EQUIPOT -Na 297 "N-000143" +Na 297 "N-000142" St ~ $EndEQUIPOT $EQUIPOT -Na 298 "N-000144" +Na 298 "N-000143" St ~ $EndEQUIPOT $EQUIPOT -Na 299 "N-000145" +Na 299 "N-000144" St ~ $EndEQUIPOT $EQUIPOT -Na 300 "N-000146" +Na 300 "N-000147" St ~ $EndEQUIPOT $EQUIPOT -Na 301 "N-000147" +Na 301 "N-000149" St ~ $EndEQUIPOT $EQUIPOT -Na 302 "N-000149" +Na 302 "N-000150" St ~ $EndEQUIPOT $EQUIPOT -Na 303 "N-000150" +Na 303 "N-000153" St ~ $EndEQUIPOT $EQUIPOT -Na 304 "N-000178" +Na 304 "N-000157" St ~ $EndEQUIPOT $EQUIPOT -Na 305 "N-000356" +Na 305 "N-000158" St ~ $EndEQUIPOT $EQUIPOT -Na 306 "N-000359" +Na 306 "N-000160" St ~ $EndEQUIPOT $EQUIPOT -Na 307 "VCCO2" +Na 307 "N-000161" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 308 "N-000163" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 309 "N-000164" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 310 "N-000165" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 311 "N-000166" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 312 "N-000167" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 313 "N-000168" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 314 "N-000169" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 315 "N-000170" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 316 "N-000171" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 317 "N-000172" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 318 "N-000174" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 319 "N-000177" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 320 "N-000178" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 321 "N-000179" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 322 "N-000182" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 323 "N-000183" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 324 "N-000188" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 325 "N-000189" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 326 "N-000190" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 327 "N-000347" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 328 "N-000350" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 329 "VCCO2" St ~ $EndEQUIPOT $NCLASS @@ -1319,15 +1407,19 @@ AddNet "" AddNet "+1.8V" AddNet "/ether/ETH_A1.8V" AddNet "/ether/ETH_A3.3V" -AddNet "/ether/ETH_CRS" +AddNet "/ether/ETH_CLK" +AddNet "/ether/ETH_COL" AddNet "/ether/ETH_INT" AddNet "/ether/ETH_LED0" AddNet "/ether/ETH_LED1" -AddNet "/ether/ETH_MDIO" AddNet "/ether/ETH_PLL1.8V" AddNet "/ether/ETH_RXD0" -AddNet "/ether/ETH_RXDV" -AddNet "/ether/ETH_RXER" +AddNet "/ether/ETH_RXD2" +AddNet "/ether/ETH_RXD3" +AddNet "/ether/ETH_TXC" +AddNet "/ether/ETH_TXD0" +AddNet "/ether/ETH_TXD2" +AddNet "/ether/ETH_TXD3" AddNet "/ether/ETH_TXER" AddNet "/ether/MAG_RX+" AddNet "/ether/MAG_RX-" @@ -1335,86 +1427,81 @@ AddNet "/ether/MAG_SHIELD" AddNet "/ether/MAG_TX+" AddNet "/ether/MAG_TX-" AddNet "/expansion/FPGA_BANK0_IO_1" -AddNet "/expansion/FPGA_BANK0_IO_10" AddNet "/expansion/FPGA_BANK0_IO_12" -AddNet "/expansion/FPGA_BANK0_IO_14" AddNet "/expansion/FPGA_BANK0_IO_15" AddNet "/expansion/FPGA_BANK0_IO_17" +AddNet "/expansion/FPGA_BANK0_IO_18" AddNet "/expansion/FPGA_BANK0_IO_21" -AddNet "/expansion/FPGA_BANK0_IO_24" +AddNet "/expansion/FPGA_BANK0_IO_25" AddNet "/expansion/FPGA_BANK0_IO_27" -AddNet "/expansion/FPGA_BANK0_IO_29" -AddNet "/expansion/FPGA_BANK0_IO_3" -AddNet "/expansion/FPGA_BANK0_IO_30" +AddNet "/expansion/FPGA_BANK0_IO_28" AddNet "/expansion/FPGA_BANK0_IO_32" -AddNet "/expansion/FPGA_BANK0_IO_34" AddNet "/expansion/FPGA_BANK0_IO_36" AddNet "/expansion/FPGA_BANK0_IO_38" AddNet "/expansion/FPGA_BANK0_IO_39" AddNet "/expansion/FPGA_BANK0_IO_43" -AddNet "/expansion/FPGA_BANK0_IO_45" AddNet "/expansion/FPGA_BANK0_IO_46" -AddNet "/expansion/FPGA_BANK0_IO_47" AddNet "/expansion/FPGA_BANK0_IO_49" AddNet "/expansion/FPGA_BANK0_IO_5" +AddNet "/expansion/FPGA_BANK0_IO_50" +AddNet "/expansion/FPGA_BANK0_IO_52" AddNet "/expansion/FPGA_BANK0_IO_53" AddNet "/expansion/FPGA_BANK0_IO_54" -AddNet "/expansion/FPGA_BANK0_IO_57" -AddNet "/expansion/FPGA_BANK0_IO_60" +AddNet "/expansion/FPGA_BANK0_IO_56" AddNet "/expansion/FPGA_BANK0_IO_63" -AddNet "/expansion/FPGA_BANK0_IO_8" AddNet "/expansion/FPGA_BANK0_IO_9" -AddNet "/flash/NF_CLE" -AddNet "/flash/NF_D2" -AddNet "/flash/NF_D4" +AddNet "/flash/NF_D3" AddNet "/flash/NF_D5" -AddNet "/flash/NF_RE_N" +AddNet "/flash/NF_RNB" AddNet "/flash/NF_WE_N" AddNet "/flash/SD_CMD" -AddNet "/flash/SD_DAT1" +AddNet "/flash/SD_DAT0" AddNet "/flash/SD_DAT2" -AddNet "/flash/SD_DAT3" -AddNet "/fpga1/ETH_CLK" -AddNet "/fpga1/ETH_COL" +AddNet "/fpga1/ETH_CRS" AddNet "/fpga1/ETH_MDC" +AddNet "/fpga1/ETH_MDIO" AddNet "/fpga1/ETH_RESET_N" AddNet "/fpga1/ETH_RXC" AddNet "/fpga1/ETH_RXD1" -AddNet "/fpga1/ETH_RXD2" -AddNet "/fpga1/ETH_RXD3" -AddNet "/fpga1/ETH_TXC" -AddNet "/fpga1/ETH_TXD0" +AddNet "/fpga1/ETH_RXDV" +AddNet "/fpga1/ETH_RXER" AddNet "/fpga1/ETH_TXD1" -AddNet "/fpga1/ETH_TXD2" -AddNet "/fpga1/ETH_TXD3" AddNet "/fpga1/ETH_TXEN" +AddNet "/fpga1/FPGA_BANK0_IO_10" AddNet "/fpga1/FPGA_BANK0_IO_11" -AddNet "/fpga1/FPGA_BANK0_IO_18" +AddNet "/fpga1/FPGA_BANK0_IO_14" AddNet "/fpga1/FPGA_BANK0_IO_2" AddNet "/fpga1/FPGA_BANK0_IO_20" AddNet "/fpga1/FPGA_BANK0_IO_22" -AddNet "/fpga1/FPGA_BANK0_IO_25" -AddNet "/fpga1/FPGA_BANK0_IO_28" +AddNet "/fpga1/FPGA_BANK0_IO_24" +AddNet "/fpga1/FPGA_BANK0_IO_29" +AddNet "/fpga1/FPGA_BANK0_IO_3" +AddNet "/fpga1/FPGA_BANK0_IO_30" AddNet "/fpga1/FPGA_BANK0_IO_33" +AddNet "/fpga1/FPGA_BANK0_IO_34" AddNet "/fpga1/FPGA_BANK0_IO_40" AddNet "/fpga1/FPGA_BANK0_IO_44" +AddNet "/fpga1/FPGA_BANK0_IO_45" +AddNet "/fpga1/FPGA_BANK0_IO_47" AddNet "/fpga1/FPGA_BANK0_IO_48" -AddNet "/fpga1/FPGA_BANK0_IO_50" AddNet "/fpga1/FPGA_BANK0_IO_51" -AddNet "/fpga1/FPGA_BANK0_IO_52" -AddNet "/fpga1/FPGA_BANK0_IO_56" +AddNet "/fpga1/FPGA_BANK0_IO_57" AddNet "/fpga1/FPGA_BANK0_IO_58" AddNet "/fpga1/FPGA_BANK0_IO_6" +AddNet "/fpga1/FPGA_BANK0_IO_60" AddNet "/fpga1/FPGA_BANK0_IO_62" AddNet "/fpga1/FPGA_BANK0_IO_7" +AddNet "/fpga1/FPGA_BANK0_IO_8" AddNet "/fpga1/NF_ALE" +AddNet "/fpga1/NF_CLE" AddNet "/fpga1/NF_CS1_N" AddNet "/fpga1/NF_D0" AddNet "/fpga1/NF_D1" -AddNet "/fpga1/NF_D3" +AddNet "/fpga1/NF_D2" +AddNet "/fpga1/NF_D4" AddNet "/fpga1/NF_D6" AddNet "/fpga1/NF_D7" -AddNet "/fpga1/NF_RNB" +AddNet "/fpga1/NF_RE_N" AddNet "/fpga1/PROG_CCLK" AddNet "/fpga1/PROG_CSO" AddNet "/fpga1/PROG_MISO0" @@ -1422,57 +1509,60 @@ AddNet "/fpga1/PROG_MISO1" AddNet "/fpga1/PROG_MISO2" AddNet "/fpga1/PROG_MISO3" AddNet "/fpga1/SD_CLK" -AddNet "/fpga1/SD_DAT0" +AddNet "/fpga1/SD_DAT1" +AddNet "/fpga1/SD_DAT3" +AddNet "/fpga2/M0_A0" AddNet "/fpga2/M0_A1" -AddNet "/fpga2/M0_A10" AddNet "/fpga2/M0_A11" -AddNet "/fpga2/M0_A12" AddNet "/fpga2/M0_A2" AddNet "/fpga2/M0_A3" +AddNet "/fpga2/M0_A4" AddNet "/fpga2/M0_A5" AddNet "/fpga2/M0_A6" AddNet "/fpga2/M0_A7" -AddNet "/fpga2/M0_A8" AddNet "/fpga2/M0_A9" -AddNet "/fpga2/M0_BA1" -AddNet "/fpga2/M0_CKE" -AddNet "/fpga2/M0_CLK" +AddNet "/fpga2/M0_CAS#" +AddNet "/fpga2/M0_CLK#" AddNet "/fpga2/M0_DQ0" +AddNet "/fpga2/M0_DQ1" AddNet "/fpga2/M0_DQ10" AddNet "/fpga2/M0_DQ11" AddNet "/fpga2/M0_DQ12" +AddNet "/fpga2/M0_DQ13" AddNet "/fpga2/M0_DQ14" -AddNet "/fpga2/M0_DQ2" +AddNet "/fpga2/M0_DQ15" AddNet "/fpga2/M0_DQ3" -AddNet "/fpga2/M0_DQ9" +AddNet "/fpga2/M0_DQ5" +AddNet "/fpga2/M0_DQ7" +AddNet "/fpga2/M0_LDM" AddNet "/fpga2/M0_LDQS" -AddNet "/fpga2/M0_RAS#" -AddNet "/fpga2/M0_UDM" AddNet "/fpga2/M0_UDQS" +AddNet "/fpga2/M0_WE#" AddNet "/fpga2/M1_A0" AddNet "/fpga2/M1_A1" +AddNet "/fpga2/M1_A12" AddNet "/fpga2/M1_A2" -AddNet "/fpga2/M1_A3" -AddNet "/fpga2/M1_A4" AddNet "/fpga2/M1_A5" -AddNet "/fpga2/M1_BA0" -AddNet "/fpga2/M1_BA1" +AddNet "/fpga2/M1_A6" +AddNet "/fpga2/M1_A7" +AddNet "/fpga2/M1_A8" +AddNet "/fpga2/M1_A9" AddNet "/fpga2/M1_CAS#" -AddNet "/fpga2/M1_CKE" +AddNet "/fpga2/M1_CLK" +AddNet "/fpga2/M1_CLK#" +AddNet "/fpga2/M1_CS#" +AddNet "/fpga2/M1_DQ0" +AddNet "/fpga2/M1_DQ1" AddNet "/fpga2/M1_DQ10" AddNet "/fpga2/M1_DQ12" AddNet "/fpga2/M1_DQ13" -AddNet "/fpga2/M1_DQ3" -AddNet "/fpga2/M1_DQ4" +AddNet "/fpga2/M1_DQ15" +AddNet "/fpga2/M1_DQ2" AddNet "/fpga2/M1_DQ5" -AddNet "/fpga2/M1_DQ6" -AddNet "/fpga2/M1_DQ7" AddNet "/fpga2/M1_DQ8" +AddNet "/fpga2/M1_DQ9" +AddNet "/fpga2/M1_LDM" AddNet "/fpga2/M1_LDQS" -AddNet "/fpga2/M1_RAS#" -AddNet "/fpga2/M1_UDM" -AddNet "/fpga2/M1_UDQS" -AddNet "/fpga2/M1_WE#" AddNet "/fpga2/R_M0_A0" AddNet "/fpga2/R_M0_A1" AddNet "/fpga2/R_M0_A10" @@ -1553,70 +1643,90 @@ AddNet "/fpga2/R_M1_UDM" AddNet "/fpga2/R_M1_UDQS" AddNet "/fpga2/R_M1_WE#" AddNet "/fpga2/USBA_RCV" -AddNet "/fpga2/USBA_VM" AddNet "/fpga2/USBA_VP" +AddNet "/fpga2/USBD_OE_N" AddNet "/fpga2/USBD_RCV" -AddNet "/sdram/M0_A0" -AddNet "/sdram/M0_A4" +AddNet "/fpga2/USBD_SPD" +AddNet "/sdram/M0_A10" +AddNet "/sdram/M0_A12" +AddNet "/sdram/M0_A8" AddNet "/sdram/M0_BA0" -AddNet "/sdram/M0_CAS#" -AddNet "/sdram/M0_CLK#" -AddNet "/sdram/M0_DQ1" -AddNet "/sdram/M0_DQ13" -AddNet "/sdram/M0_DQ15" +AddNet "/sdram/M0_BA1" +AddNet "/sdram/M0_CKE" +AddNet "/sdram/M0_CLK" +AddNet "/sdram/M0_DQ2" AddNet "/sdram/M0_DQ4" -AddNet "/sdram/M0_DQ5" AddNet "/sdram/M0_DQ6" -AddNet "/sdram/M0_DQ7" AddNet "/sdram/M0_DQ8" -AddNet "/sdram/M0_LDM" +AddNet "/sdram/M0_DQ9" +AddNet "/sdram/M0_RAS#" +AddNet "/sdram/M0_UDM" AddNet "/sdram/M0_VREF" -AddNet "/sdram/M0_WE#" AddNet "/sdram/M1_A10" AddNet "/sdram/M1_A11" -AddNet "/sdram/M1_A12" -AddNet "/sdram/M1_A6" -AddNet "/sdram/M1_A7" -AddNet "/sdram/M1_A8" -AddNet "/sdram/M1_A9" -AddNet "/sdram/M1_CLK" -AddNet "/sdram/M1_CLK#" -AddNet "/sdram/M1_CS#" -AddNet "/sdram/M1_DQ0" -AddNet "/sdram/M1_DQ1" +AddNet "/sdram/M1_A3" +AddNet "/sdram/M1_A4" +AddNet "/sdram/M1_BA0" +AddNet "/sdram/M1_BA1" +AddNet "/sdram/M1_CKE" AddNet "/sdram/M1_DQ11" AddNet "/sdram/M1_DQ14" -AddNet "/sdram/M1_DQ15" -AddNet "/sdram/M1_DQ2" -AddNet "/sdram/M1_DQ9" -AddNet "/sdram/M1_LDM" +AddNet "/sdram/M1_DQ3" +AddNet "/sdram/M1_DQ4" +AddNet "/sdram/M1_DQ6" +AddNet "/sdram/M1_DQ7" +AddNet "/sdram/M1_RAS#" +AddNet "/sdram/M1_UDM" +AddNet "/sdram/M1_UDQS" AddNet "/sdram/M1_VREF" +AddNet "/sdram/M1_WE#" AddNet "/usb/USBA_D+" AddNet "/usb/USBA_D-" AddNet "/usb/USBA_OE_N" AddNet "/usb/USBA_SPD" +AddNet "/usb/USBA_VM" AddNet "/usb/USBD_D+" AddNet "/usb/USBD_D-" -AddNet "/usb/USBD_OE_N" -AddNet "/usb/USBD_SPD" AddNet "/usb/USBD_VM" AddNet "/usb/USBD_VP" AddNet "/usb/USB_CASE_DEV" AddNet "/usb/USB_CASE_HOST" AddNet "N-000120" -AddNet "N-000121" -AddNet "N-000133" +AddNet "N-000131" +AddNet "N-000132" +AddNet "N-000141" AddNet "N-000142" AddNet "N-000143" AddNet "N-000144" -AddNet "N-000145" -AddNet "N-000146" AddNet "N-000147" AddNet "N-000149" AddNet "N-000150" +AddNet "N-000153" +AddNet "N-000157" +AddNet "N-000158" +AddNet "N-000160" +AddNet "N-000161" +AddNet "N-000163" +AddNet "N-000164" +AddNet "N-000165" +AddNet "N-000166" +AddNet "N-000167" +AddNet "N-000168" +AddNet "N-000169" +AddNet "N-000170" +AddNet "N-000171" +AddNet "N-000172" +AddNet "N-000174" +AddNet "N-000177" AddNet "N-000178" -AddNet "N-000356" -AddNet "N-000359" +AddNet "N-000179" +AddNet "N-000182" +AddNet "N-000183" +AddNet "N-000188" +AddNet "N-000189" +AddNet "N-000190" +AddNet "N-000347" +AddNet "N-000350" AddNet "VCCO2" $EndNCLASS $NCLASS @@ -1736,105 +1846,105 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/fpga1/ETH_CLK" +Ne 8 "/ether/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/fpga1/ETH_RXD1" +Ne 63 "/fpga1/ETH_RXD1" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/ether/ETH_RXDV" +Ne 64 "/fpga1/ETH_RXDV" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/fpga1/ETH_RXC" +Ne 62 "/fpga1/ETH_RXC" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/fpga1/ETH_TXD3" +Ne 20 "/ether/ETH_TXD3" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/fpga1/ETH_COL" +Ne 9 "/ether/ETH_COL" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/ether/ETH_INT" +Ne 10 "/ether/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/fpga1/NF_D6" +Ne 100 "/fpga1/NF_D6" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/flash/NF_D4" +Ne 99 "/fpga1/NF_D4" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/flash/NF_D2" +Ne 98 "/fpga1/NF_D2" Po 590 -4133 $EndPAD $PAD Sh "A14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/fpga1/NF_ALE" +Ne 93 "/fpga1/NF_ALE" Po 983 -4133 $EndPAD $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/fpga1/NF_RNB" +Ne 53 "/flash/NF_RNB" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/flash/SD_DAT2" +Ne 57 "/flash/SD_DAT2" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/fpga1/SD_CLK" +Ne 109 "/fpga1/SD_CLK" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/fpga1/SD_DAT0" +Ne 56 "/flash/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -1848,14 +1958,14 @@ $PAD Sh "A20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 244 "/fpga2/USBD_RCV" +Ne 246 "/fpga2/USBD_RCV" Po 3346 -4133 $EndPAD $PAD Sh "A21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 286 "/usb/USBD_OE_N" +Ne 245 "/fpga2/USBD_OE_N" Po 3739 -4133 $EndPAD $PAD @@ -1918,7 +2028,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/ether/ETH_RXER" +Ne 65 "/fpga1/ETH_RXER" Po -1377 -3739 $EndPAD $PAD @@ -1932,7 +2042,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/ether/ETH_CRS" +Ne 58 "/fpga1/ETH_CRS" Po -590 -3739 $EndPAD $PAD @@ -1946,7 +2056,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/fpga1/NF_D3" +Ne 51 "/flash/NF_D3" Po 196 -3739 $EndPAD $PAD @@ -1960,7 +2070,7 @@ $PAD Sh "B14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/flash/NF_CLE" +Ne 94 "/fpga1/NF_CLE" Po 983 -3739 $EndPAD $PAD @@ -1974,7 +2084,7 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/flash/SD_DAT3" +Ne 111 "/fpga1/SD_DAT3" Po 1771 -3739 $EndPAD $PAD @@ -1988,7 +2098,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/flash/SD_DAT1" +Ne 110 "/fpga1/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -2002,7 +2112,7 @@ $PAD Sh "B20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 287 "/usb/USBD_SPD" +Ne 247 "/fpga2/USBD_SPD" Po 3346 -3739 $EndPAD $PAD @@ -2023,7 +2133,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/fpga2/R_M0_A11" +Ne 167 "/fpga2/R_M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -2051,56 +2161,56 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/fpga1/ETH_RXD3" +Ne 16 "/ether/ETH_RXD3" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/fpga1/ETH_RXD2" +Ne 15 "/ether/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/fpga1/ETH_RESET_N" +Ne 61 "/fpga1/ETH_RESET_N" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/fpga1/ETH_TXC" +Ne 17 "/ether/ETH_TXC" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/fpga1/ETH_TXD1" +Ne 66 "/fpga1/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/fpga1/ETH_TXD2" +Ne 19 "/ether/ETH_TXD2" Po -590 -3346 $EndPAD $PAD Sh "C11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/flash/NF_D5" +Ne 52 "/flash/NF_D5" Po -196 -3346 $EndPAD $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/fpga1/NF_D0" +Ne 96 "/fpga1/NF_D0" Po 196 -3346 $EndPAD $PAD @@ -2114,21 +2224,21 @@ $PAD Sh "C14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/flash/NF_WE_N" +Ne 54 "/flash/NF_WE_N" Po 983 -3346 $EndPAD $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/flash/NF_RE_N" +Ne 102 "/fpga1/NF_RE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/flash/SD_CMD" +Ne 55 "/flash/SD_CMD" Po 1771 -3346 $EndPAD $PAD @@ -2149,14 +2259,14 @@ $PAD Sh "C19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 282 "/usb/USBA_OE_N" +Ne 283 "/usb/USBA_OE_N" Po 2952 -3346 $EndPAD $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 212 "/fpga2/R_M1_A8" +Ne 214 "/fpga2/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -2170,21 +2280,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 213 "/fpga2/R_M1_A9" +Ne 215 "/fpga2/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/fpga2/R_M0_A12" +Ne 168 "/fpga2/R_M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/fpga2/R_M0_CKE" +Ne 180 "/fpga2/R_M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -2212,42 +2322,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/ether/ETH_MDIO" +Ne 60 "/fpga1/ETH_MDIO" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/fpga1/ETH_MDC" +Ne 59 "/fpga1/ETH_MDC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/ether/ETH_TXER" +Ne 21 "/ether/ETH_TXER" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/fpga1/ETH_TXEN" +Ne 67 "/fpga1/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/fpga1/ETH_TXD0" +Ne 18 "/ether/ETH_TXD0" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/fpga1/NF_D7" +Ne 101 "/fpga1/NF_D7" Po -196 -2952 $EndPAD $PAD @@ -2268,14 +2378,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/fpga1/NF_D1" +Ne 97 "/fpga1/NF_D1" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/fpga1/NF_CS1_N" +Ne 95 "/fpga1/NF_CS1_N" Po 1377 -2952 $EndPAD $PAD @@ -2303,35 +2413,35 @@ $PAD Sh "D19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 243 "/fpga2/USBA_VP" +Ne 244 "/fpga2/USBA_VP" Po 2952 -2952 $EndPAD $PAD Sh "D20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 242 "/fpga2/USBA_VM" +Ne 285 "/usb/USBA_VM" Po 3346 -2952 $EndPAD $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/fpga2/R_M1_CKE" +Ne 219 "/fpga2/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 205 "/fpga2/R_M1_A12" +Ne 207 "/fpga2/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/fpga2/R_M0_A9" +Ne 176 "/fpga2/R_M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -2345,7 +2455,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/fpga2/R_M0_A8" +Ne 175 "/fpga2/R_M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -2464,7 +2574,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 211 "/fpga2/R_M1_A7" +Ne 213 "/fpga2/R_M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -2478,7 +2588,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "/fpga2/R_M1_A2" +Ne 208 "/fpga2/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -2492,14 +2602,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 200 "/fpga2/R_M0_WE#" +Ne 202 "/fpga2/R_M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/fpga2/R_M0_A4" +Ne 171 "/fpga2/R_M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -2590,14 +2700,14 @@ $PAD Sh "F16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 283 "/usb/USBA_SPD" +Ne 284 "/usb/USBA_SPD" Po 1771 -2165 $EndPAD $PAD Sh "F17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 241 "/fpga2/USBA_RCV" +Ne 243 "/fpga2/USBA_RCV" Po 2165 -2165 $EndPAD $PAD @@ -2611,35 +2721,35 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 204 "/fpga2/R_M1_A11" +Ne 206 "/fpga2/R_M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 208 "/fpga2/R_M1_A4" +Ne 210 "/fpga2/R_M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "/fpga2/R_M1_A0" +Ne 203 "/fpga2/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 202 "/fpga2/R_M1_A1" +Ne 204 "/fpga2/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/fpga2/R_M0_BA1" +Ne 178 "/fpga2/R_M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -2653,14 +2763,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/fpga2/R_M0_BA0" +Ne 177 "/fpga2/R_M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/fpga2/R_M0_A10" +Ne 166 "/fpga2/R_M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -2765,14 +2875,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 203 "/fpga2/R_M1_A10" +Ne 205 "/fpga2/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 207 "/fpga2/R_M1_A3" +Ne 209 "/fpga2/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2793,42 +2903,42 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/fpga2/R_M0_A1" +Ne 165 "/fpga2/R_M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/fpga2/R_M0_A0" +Ne 164 "/fpga2/R_M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 249 "/sdram/M0_CLK#" +Ne 123 "/fpga2/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/fpga2/M0_CLK" +Ne 254 "/sdram/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/fpga2/R_M0_A2" +Ne 169 "/fpga2/R_M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/fpga2/R_M0_A7" +Ne 174 "/fpga2/R_M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -2898,7 +3008,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 218 "/fpga2/R_M1_CS#" +Ne 220 "/fpga2/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -2919,35 +3029,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 240 "/fpga2/R_M1_WE#" +Ne 242 "/fpga2/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 268 "/sdram/M1_CLK" +Ne 149 "/fpga2/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 237 "/fpga2/R_M1_RAS#" +Ne 239 "/fpga2/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 216 "/fpga2/R_M1_CAS#" +Ne 218 "/fpga2/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/fpga2/R_M0_DQ5" +Ne 192 "/fpga2/R_M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -2961,14 +3071,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/fpga2/R_M0_DQ4" +Ne 191 "/fpga2/R_M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/fpga2/R_M0_A6" +Ne 173 "/fpga2/R_M0_A6" Po -2952 -983 $EndPAD $PAD @@ -3059,7 +3169,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 214 "/fpga2/R_M1_BA0" +Ne 216 "/fpga2/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -3073,14 +3183,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 269 "/sdram/M1_CLK#" +Ne 150 "/fpga2/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "/fpga2/R_M1_DQ4" +Ne 231 "/fpga2/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD @@ -3094,49 +3204,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 230 "/fpga2/R_M1_DQ5" +Ne 232 "/fpga2/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 192 "/fpga2/R_M0_DQ7" +Ne 194 "/fpga2/R_M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/fpga2/R_M0_DQ6" +Ne 193 "/fpga2/R_M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/fpga2/R_M0_A5" +Ne 172 "/fpga2/R_M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/fpga2/R_M0_CAS#" +Ne 179 "/fpga2/R_M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 197 "/fpga2/R_M0_RAS#" +Ne 199 "/fpga2/R_M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/fpga2/R_M0_A3" +Ne 170 "/fpga2/R_M0_A3" Po -2165 -590 $EndPAD $PAD @@ -3213,7 +3323,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 215 "/fpga2/R_M1_BA1" +Ne 217 "/fpga2/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -3227,28 +3337,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 210 "/fpga2/R_M1_A6" +Ne 212 "/fpga2/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 209 "/fpga2/R_M1_A5" +Ne 211 "/fpga2/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "/fpga2/R_M1_DQ6" +Ne 233 "/fpga2/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 232 "/fpga2/R_M1_DQ7" +Ne 234 "/fpga2/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -3269,14 +3379,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 196 "/fpga2/R_M0_LDQS" +Ne 198 "/fpga2/R_M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 195 "/fpga2/R_M0_LDM" +Ne 197 "/fpga2/R_M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -3381,14 +3491,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 235 "/fpga2/R_M1_LDM" +Ne 237 "/fpga2/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 236 "/fpga2/R_M1_LDQS" +Ne 238 "/fpga2/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -3409,21 +3519,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/fpga2/R_M0_DQ3" +Ne 190 "/fpga2/R_M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/fpga2/R_M0_DQ2" +Ne 189 "/fpga2/R_M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 198 "/fpga2/R_M0_UDM" +Ne 200 "/fpga2/R_M0_UDM" Po -3346 196 $EndPAD $PAD @@ -3542,28 +3652,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 238 "/fpga2/R_M1_UDM" +Ne 240 "/fpga2/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 227 "/fpga2/R_M1_DQ2" +Ne 229 "/fpga2/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 228 "/fpga2/R_M1_DQ3" +Ne 230 "/fpga2/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 180 "/fpga2/R_M0_DQ1" +Ne 182 "/fpga2/R_M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -3577,7 +3687,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/fpga2/R_M0_DQ0" +Ne 181 "/fpga2/R_M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -3696,7 +3806,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 219 "/fpga2/R_M1_DQ0" +Ne 221 "/fpga2/R_M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -3710,21 +3820,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 220 "/fpga2/R_M1_DQ1" +Ne 222 "/fpga2/R_M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 194 "/fpga2/R_M0_DQ9" +Ne 196 "/fpga2/R_M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 193 "/fpga2/R_M0_DQ8" +Ne 195 "/fpga2/R_M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3857,21 +3967,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 233 "/fpga2/R_M1_DQ8" +Ne 235 "/fpga2/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 234 "/fpga2/R_M1_DQ9" +Ne 236 "/fpga2/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/fpga2/R_M0_DQ11" +Ne 184 "/fpga2/R_M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3885,7 +3995,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/fpga2/R_M0_DQ10" +Ne 183 "/fpga2/R_M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3927,7 +4037,7 @@ $PAD Sh "R9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/fpga1/FPGA_BANK0_IO_58" +Ne 87 "/fpga1/FPGA_BANK0_IO_58" Po -983 1377 $EndPAD $PAD @@ -3976,7 +4086,7 @@ $PAD Sh "R16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/expansion/FPGA_BANK0_IO_12" +Ne 28 "/expansion/FPGA_BANK0_IO_12" Po 1771 1377 $EndPAD $PAD @@ -4004,7 +4114,7 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/fpga2/R_M1_DQ10" +Ne 223 "/fpga2/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -4018,7 +4128,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "/fpga2/R_M1_DQ11" +Ne 224 "/fpga2/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -4032,7 +4142,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 199 "/fpga2/R_M0_UDQS" +Ne 201 "/fpga2/R_M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -4053,7 +4163,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/fpga1/PROG_CSO" +Ne 104 "/fpga1/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -4067,7 +4177,7 @@ $PAD Sh "T7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/expansion/FPGA_BANK0_IO_60" +Ne 89 "/fpga1/FPGA_BANK0_IO_60" Po -1771 1771 $EndPAD $PAD @@ -4081,7 +4191,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -983 1771 $EndPAD $PAD @@ -4102,14 +4212,14 @@ $PAD Sh "T12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/expansion/FPGA_BANK0_IO_34" +Ne 79 "/fpga1/FPGA_BANK0_IO_34" Po 196 1771 $EndPAD $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po 590 1771 $EndPAD $PAD @@ -4123,28 +4233,28 @@ $PAD Sh "T15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/fpga1/FPGA_BANK0_IO_7" +Ne 91 "/fpga1/FPGA_BANK0_IO_7" Po 1377 1771 $EndPAD $PAD Sh "T16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/fpga1/FPGA_BANK0_IO_6" +Ne 88 "/fpga1/FPGA_BANK0_IO_6" Po 1771 1771 $EndPAD $PAD Sh "T17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/fpga1/FPGA_BANK0_IO_2" +Ne 71 "/fpga1/FPGA_BANK0_IO_2" Po 2165 1771 $EndPAD $PAD Sh "T18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/expansion/FPGA_BANK0_IO_1" +Ne 27 "/expansion/FPGA_BANK0_IO_1" Po 2558 1771 $EndPAD $PAD @@ -4165,7 +4275,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 239 "/fpga2/R_M1_UDQS" +Ne 241 "/fpga2/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -4179,7 +4289,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/fpga2/R_M0_DQ13" +Ne 186 "/fpga2/R_M0_DQ13" Po -4133 2165 $EndPAD $PAD @@ -4193,7 +4303,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/fpga2/R_M0_DQ12" +Ne 185 "/fpga2/R_M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -4214,7 +4324,7 @@ $PAD Sh "U6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/fpga1/FPGA_BANK0_IO_62" +Ne 90 "/fpga1/FPGA_BANK0_IO_62" Po -2165 2165 $EndPAD $PAD @@ -4235,14 +4345,14 @@ $PAD Sh "U9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/fpga1/FPGA_BANK0_IO_51" +Ne 85 "/fpga1/FPGA_BANK0_IO_51" Po -983 2165 $EndPAD $PAD Sh "U10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/fpga1/FPGA_BANK0_IO_56" +Ne 48 "/expansion/FPGA_BANK0_IO_56" Po -590 2165 $EndPAD $PAD @@ -4263,14 +4373,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/fpga1/PROG_MISO3" +Ne 108 "/fpga1/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/fpga1/PROG_MISO2" +Ne 107 "/fpga1/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -4284,14 +4394,14 @@ $PAD Sh "U16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/expansion/FPGA_BANK0_IO_9" +Ne 50 "/expansion/FPGA_BANK0_IO_9" Po 1771 2165 $EndPAD $PAD Sh "U17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/expansion/FPGA_BANK0_IO_8" +Ne 92 "/fpga1/FPGA_BANK0_IO_8" Po 2165 2165 $EndPAD $PAD @@ -4312,7 +4422,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 223 "/fpga2/R_M1_DQ12" +Ne 225 "/fpga2/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -4326,21 +4436,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 224 "/fpga2/R_M1_DQ13" +Ne 226 "/fpga2/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 186 "/fpga2/R_M0_DQ15" +Ne 188 "/fpga2/R_M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "/fpga2/R_M0_DQ14" +Ne 187 "/fpga2/R_M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -4361,7 +4471,7 @@ $PAD Sh "V5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/expansion/FPGA_BANK0_IO_63" +Ne 49 "/expansion/FPGA_BANK0_IO_63" Po -2558 2558 $EndPAD $PAD @@ -4375,21 +4485,21 @@ $PAD Sh "V7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/expansion/FPGA_BANK0_IO_49" +Ne 42 "/expansion/FPGA_BANK0_IO_49" Po -1771 2558 $EndPAD $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -1377 2558 $EndPAD $PAD Sh "V9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/fpga1/FPGA_BANK0_IO_52" +Ne 45 "/expansion/FPGA_BANK0_IO_52" Po -983 2558 $EndPAD $PAD @@ -4410,7 +4520,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po 196 2558 $EndPAD $PAD @@ -4431,35 +4541,35 @@ $PAD Sh "V15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/expansion/FPGA_BANK0_IO_17" +Ne 30 "/expansion/FPGA_BANK0_IO_17" Po 1377 2558 $EndPAD $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po 1771 2558 $EndPAD $PAD Sh "V17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/expansion/FPGA_BANK0_IO_14" +Ne 70 "/fpga1/FPGA_BANK0_IO_14" Po 2165 2558 $EndPAD $PAD Sh "V18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/fpga1/FPGA_BANK0_IO_11" +Ne 69 "/fpga1/FPGA_BANK0_IO_11" Po 2558 2558 $EndPAD $PAD Sh "V19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/expansion/FPGA_BANK0_IO_10" +Ne 68 "/fpga1/FPGA_BANK0_IO_10" Po 2952 2558 $EndPAD $PAD @@ -4473,14 +4583,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 225 "/fpga2/R_M1_DQ14" +Ne 227 "/fpga2/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 226 "/fpga2/R_M1_DQ15" +Ne 228 "/fpga2/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -4515,14 +4625,14 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -2558 2952 $EndPAD $PAD Sh "W6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/expansion/FPGA_BANK0_IO_57" +Ne 86 "/fpga1/FPGA_BANK0_IO_57" Po -2165 2952 $EndPAD $PAD @@ -4536,28 +4646,28 @@ $PAD Sh "W8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/fpga1/FPGA_BANK0_IO_48" +Ne 84 "/fpga1/FPGA_BANK0_IO_48" Po -1377 2952 $EndPAD $PAD Sh "W9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/fpga1/FPGA_BANK0_IO_50" +Ne 44 "/expansion/FPGA_BANK0_IO_50" Po -983 2952 $EndPAD $PAD Sh "W10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/expansion/FPGA_BANK0_IO_46" +Ne 41 "/expansion/FPGA_BANK0_IO_46" Po -590 2952 $EndPAD $PAD Sh "W11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/fpga1/FPGA_BANK0_IO_44" +Ne 81 "/fpga1/FPGA_BANK0_IO_44" Po -196 2952 $EndPAD $PAD @@ -4571,21 +4681,21 @@ $PAD Sh "W13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/expansion/FPGA_BANK0_IO_27" +Ne 34 "/expansion/FPGA_BANK0_IO_27" Po 590 2952 $EndPAD $PAD Sh "W14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/expansion/FPGA_BANK0_IO_30" +Ne 77 "/fpga1/FPGA_BANK0_IO_30" Po 983 2952 $EndPAD $PAD Sh "W15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/fpga1/FPGA_BANK0_IO_25" +Ne 33 "/expansion/FPGA_BANK0_IO_25" Po 1377 2952 $EndPAD $PAD @@ -4599,7 +4709,7 @@ $PAD Sh "W17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/expansion/FPGA_BANK0_IO_15" +Ne 29 "/expansion/FPGA_BANK0_IO_15" Po 2165 2952 $EndPAD $PAD @@ -4697,21 +4807,21 @@ $PAD Sh "Y9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/expansion/FPGA_BANK0_IO_45" +Ne 82 "/fpga1/FPGA_BANK0_IO_45" Po -983 3346 $EndPAD $PAD Sh "Y10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/expansion/FPGA_BANK0_IO_47" +Ne 83 "/fpga1/FPGA_BANK0_IO_47" Po -590 3346 $EndPAD $PAD Sh "Y11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/fpga1/FPGA_BANK0_IO_40" +Ne 80 "/fpga1/FPGA_BANK0_IO_40" Po -196 3346 $EndPAD $PAD @@ -4739,35 +4849,35 @@ $PAD Sh "Y15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/expansion/FPGA_BANK0_IO_32" +Ne 36 "/expansion/FPGA_BANK0_IO_32" Po 1377 3346 $EndPAD $PAD Sh "Y16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/expansion/FPGA_BANK0_IO_24" +Ne 74 "/fpga1/FPGA_BANK0_IO_24" Po 1771 3346 $EndPAD $PAD Sh "Y17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/fpga1/FPGA_BANK0_IO_20" +Ne 72 "/fpga1/FPGA_BANK0_IO_20" Po 2165 3346 $EndPAD $PAD Sh "Y18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/expansion/FPGA_BANK0_IO_5" +Ne 43 "/expansion/FPGA_BANK0_IO_5" Po 2558 3346 $EndPAD $PAD Sh "Y19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/expansion/FPGA_BANK0_IO_3" +Ne 76 "/fpga1/FPGA_BANK0_IO_3" Po 2952 3346 $EndPAD $PAD @@ -4788,14 +4898,14 @@ $PAD Sh "Y22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 306 "N-000359" +Ne 328 "N-000350" Po 4133 3346 $EndPAD $PAD Sh "AA1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 305 "N-000356" +Ne 327 "N-000347" Po -4133 3739 $EndPAD $PAD @@ -4809,7 +4919,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -3346 3739 $EndPAD $PAD @@ -4837,7 +4947,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -1771 3739 $EndPAD $PAD @@ -4865,7 +4975,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -196 3739 $EndPAD $PAD @@ -4886,21 +4996,21 @@ $PAD Sh "AA14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/fpga1/FPGA_BANK0_IO_22" +Ne 73 "/fpga1/FPGA_BANK0_IO_22" Po 983 3739 $EndPAD $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po 1377 3739 $EndPAD $PAD Sh "AA16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/fpga1/FPGA_BANK0_IO_28" +Ne 35 "/expansion/FPGA_BANK0_IO_28" Po 1771 3739 $EndPAD $PAD @@ -4914,35 +5024,35 @@ $PAD Sh "AA18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/fpga1/FPGA_BANK0_IO_18" +Ne 31 "/expansion/FPGA_BANK0_IO_18" Po 2558 3739 $EndPAD $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po 2952 3739 $EndPAD $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/fpga1/PROG_MISO1" +Ne 106 "/fpga1/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/fpga1/PROG_CCLK" +Ne 103 "/fpga1/PROG_CCLK" Po 3739 3739 $EndPAD $PAD Sh "AA22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po 4133 3739 $EndPAD $PAD @@ -5047,21 +5157,21 @@ $PAD Sh "AB15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/fpga1/FPGA_BANK0_IO_33" +Ne 78 "/fpga1/FPGA_BANK0_IO_33" Po 1377 4133 $EndPAD $PAD Sh "AB16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/expansion/FPGA_BANK0_IO_29" +Ne 75 "/fpga1/FPGA_BANK0_IO_29" Po 1771 4133 $EndPAD $PAD Sh "AB17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/expansion/FPGA_BANK0_IO_21" +Ne 32 "/expansion/FPGA_BANK0_IO_21" Po 2165 4133 $EndPAD $PAD @@ -5082,7 +5192,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/fpga1/PROG_MISO0" +Ne 105 "/fpga1/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -5173,14 +5283,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 198 "/fpga2/R_M0_UDM" +Ne 200 "/fpga2/R_M0_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 136 "/fpga2/M0_UDM" +Ne 261 "/sdram/M0_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5201,7 +5311,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 199 "/fpga2/R_M0_UDQS" +Ne 201 "/fpga2/R_M0_UDQS" Po -176 0 $EndPAD $PAD @@ -5229,14 +5339,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 178 "/fpga2/R_M0_CKE" +Ne 180 "/fpga2/R_M0_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 124 "/fpga2/M0_CKE" +Ne 253 "/sdram/M0_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5257,14 +5367,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 125 "/fpga2/M0_CLK" +Ne 254 "/sdram/M0_CLK" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 249 "/sdram/M0_CLK#" +Ne 123 "/fpga2/M0_CLK#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5283,56 +5393,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/fpga2/R_M0_A0" +Ne 164 "/fpga2/R_M0_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/fpga2/R_M0_A1" +Ne 165 "/fpga2/R_M0_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/fpga2/R_M0_A2" +Ne 169 "/fpga2/R_M0_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/fpga2/R_M0_A3" +Ne 170 "/fpga2/R_M0_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 117 "/fpga2/M0_A3" +Ne 116 "/fpga2/M0_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 116 "/fpga2/M0_A2" +Ne 115 "/fpga2/M0_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 112 "/fpga2/M0_A1" +Ne 113 "/fpga2/M0_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 245 "/sdram/M0_A0" +Ne 112 "/fpga2/M0_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5351,56 +5461,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 197 "/fpga2/R_M0_RAS#" +Ne 199 "/fpga2/R_M0_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 175 "/fpga2/R_M0_BA0" +Ne 177 "/fpga2/R_M0_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 176 "/fpga2/R_M0_BA1" +Ne 178 "/fpga2/R_M0_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/fpga2/R_M0_A10" +Ne 166 "/fpga2/R_M0_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 113 "/fpga2/M0_A10" +Ne 248 "/sdram/M0_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 123 "/fpga2/M0_BA1" +Ne 252 "/sdram/M0_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 247 "/sdram/M0_BA0" +Ne 251 "/sdram/M0_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 135 "/fpga2/M0_RAS#" +Ne 260 "/sdram/M0_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5419,35 +5529,35 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 172 "/fpga2/R_M0_A7" +Ne 174 "/fpga2/R_M0_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/fpga2/R_M0_A6" +Ne 173 "/fpga2/R_M0_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/fpga2/R_M0_A5" +Ne 172 "/fpga2/R_M0_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/fpga2/R_M0_A4" +Ne 171 "/fpga2/R_M0_A4" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 246 "/sdram/M0_A4" +Ne 117 "/fpga2/M0_A4" Po 295 177 $EndPAD $PAD @@ -5487,42 +5597,42 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/fpga2/R_M0_A12" +Ne 168 "/fpga2/R_M0_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/fpga2/R_M0_A11" +Ne 167 "/fpga2/R_M0_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 174 "/fpga2/R_M0_A9" +Ne 176 "/fpga2/R_M0_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 173 "/fpga2/R_M0_A8" +Ne 175 "/fpga2/R_M0_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 121 "/fpga2/M0_A8" +Ne 250 "/sdram/M0_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 122 "/fpga2/M0_A9" +Ne 121 "/fpga2/M0_A9" Po 98 177 $EndPAD $PAD @@ -5536,7 +5646,7 @@ $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 115 "/fpga2/M0_A12" +Ne 249 "/sdram/M0_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5555,56 +5665,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 189 "/fpga2/R_M0_DQ4" +Ne 191 "/fpga2/R_M0_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 190 "/fpga2/R_M0_DQ5" +Ne 192 "/fpga2/R_M0_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 191 "/fpga2/R_M0_DQ6" +Ne 193 "/fpga2/R_M0_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 192 "/fpga2/R_M0_DQ7" +Ne 194 "/fpga2/R_M0_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 256 "/sdram/M0_DQ7" +Ne 134 "/fpga2/M0_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 255 "/sdram/M0_DQ6" +Ne 257 "/sdram/M0_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 254 "/sdram/M0_DQ5" +Ne 133 "/fpga2/M0_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 253 "/sdram/M0_DQ4" +Ne 256 "/sdram/M0_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5623,28 +5733,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 179 "/fpga2/R_M0_DQ0" +Ne 181 "/fpga2/R_M0_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 180 "/fpga2/R_M0_DQ1" +Ne 182 "/fpga2/R_M0_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 187 "/fpga2/R_M0_DQ2" +Ne 189 "/fpga2/R_M0_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 188 "/fpga2/R_M0_DQ3" +Ne 190 "/fpga2/R_M0_DQ3" Po 295 -177 $EndPAD $PAD @@ -5658,21 +5768,21 @@ $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 131 "/fpga2/M0_DQ2" +Ne 255 "/sdram/M0_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 250 "/sdram/M0_DQ1" +Ne 125 "/fpga2/M0_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 126 "/fpga2/M0_DQ0" +Ne 124 "/fpga2/M0_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5691,56 +5801,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 193 "/fpga2/R_M0_DQ8" +Ne 195 "/fpga2/R_M0_DQ8" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 194 "/fpga2/R_M0_DQ9" +Ne 196 "/fpga2/R_M0_DQ9" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/fpga2/R_M0_DQ10" +Ne 183 "/fpga2/R_M0_DQ10" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/fpga2/R_M0_DQ11" +Ne 184 "/fpga2/R_M0_DQ11" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 128 "/fpga2/M0_DQ11" +Ne 127 "/fpga2/M0_DQ11" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 127 "/fpga2/M0_DQ10" +Ne 126 "/fpga2/M0_DQ10" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 133 "/fpga2/M0_DQ9" +Ne 259 "/sdram/M0_DQ9" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 257 "/sdram/M0_DQ8" +Ne 258 "/sdram/M0_DQ8" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5759,35 +5869,35 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/fpga2/R_M0_DQ12" +Ne 185 "/fpga2/R_M0_DQ12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/fpga2/R_M0_DQ13" +Ne 186 "/fpga2/R_M0_DQ13" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 185 "/fpga2/R_M0_DQ14" +Ne 187 "/fpga2/R_M0_DQ14" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 186 "/fpga2/R_M0_DQ15" +Ne 188 "/fpga2/R_M0_DQ15" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 252 "/sdram/M0_DQ15" +Ne 131 "/fpga2/M0_DQ15" Po 295 177 $EndPAD $PAD @@ -5801,14 +5911,14 @@ $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 251 "/sdram/M0_DQ13" +Ne 129 "/fpga2/M0_DQ13" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 129 "/fpga2/M0_DQ12" +Ne 128 "/fpga2/M0_DQ12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5829,14 +5939,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 239 "/fpga2/R_M1_UDQS" +Ne 241 "/fpga2/R_M1_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/fpga2/M1_UDQS" +Ne 278 "/sdram/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5857,14 +5967,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 218 "/fpga2/R_M1_CS#" +Ne 220 "/fpga2/R_M1_CS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 270 "/sdram/M1_CS#" +Ne 151 "/fpga2/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5885,14 +5995,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 217 "/fpga2/R_M1_CKE" +Ne 219 "/fpga2/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 147 "/fpga2/M1_CKE" +Ne 269 "/sdram/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5913,14 +6023,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 238 "/fpga2/R_M1_UDM" +Ne 240 "/fpga2/R_M1_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/fpga2/M1_UDM" +Ne 277 "/sdram/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5939,56 +6049,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 275 "/sdram/M1_DQ15" +Ne 157 "/fpga2/M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 274 "/sdram/M1_DQ14" +Ne 271 "/sdram/M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/fpga2/M1_DQ13" +Ne 156 "/fpga2/M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/fpga2/M1_DQ12" +Ne 155 "/fpga2/M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 223 "/fpga2/R_M1_DQ12" +Ne 225 "/fpga2/R_M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 224 "/fpga2/R_M1_DQ13" +Ne 226 "/fpga2/R_M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 225 "/fpga2/R_M1_DQ14" +Ne 227 "/fpga2/R_M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 226 "/fpga2/R_M1_DQ15" +Ne 228 "/fpga2/R_M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6007,56 +6117,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 273 "/sdram/M1_DQ11" +Ne 270 "/sdram/M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 148 "/fpga2/M1_DQ10" +Ne 154 "/fpga2/M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 277 "/sdram/M1_DQ9" +Ne 161 "/fpga2/M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/fpga2/M1_DQ8" +Ne 160 "/fpga2/M1_DQ8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 233 "/fpga2/R_M1_DQ8" +Ne 235 "/fpga2/R_M1_DQ8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 234 "/fpga2/R_M1_DQ9" +Ne 236 "/fpga2/R_M1_DQ9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 221 "/fpga2/R_M1_DQ10" +Ne 223 "/fpga2/R_M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 222 "/fpga2/R_M1_DQ11" +Ne 224 "/fpga2/R_M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6077,14 +6187,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 269 "/sdram/M1_CLK#" +Ne 150 "/fpga2/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 268 "/sdram/M1_CLK" +Ne 149 "/fpga2/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6103,56 +6213,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 263 "/sdram/M1_A12" +Ne 141 "/fpga2/M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 262 "/sdram/M1_A11" +Ne 264 "/sdram/M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 267 "/sdram/M1_A9" +Ne 147 "/fpga2/M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 266 "/sdram/M1_A8" +Ne 146 "/fpga2/M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 212 "/fpga2/R_M1_A8" +Ne 214 "/fpga2/R_M1_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 213 "/fpga2/R_M1_A9" +Ne 215 "/fpga2/R_M1_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 204 "/fpga2/R_M1_A11" +Ne 206 "/fpga2/R_M1_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 205 "/fpga2/R_M1_A12" +Ne 207 "/fpga2/R_M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6171,14 +6281,14 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 265 "/sdram/M1_A7" +Ne 145 "/fpga2/M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 264 "/sdram/M1_A6" +Ne 144 "/fpga2/M1_A6" Po -98 -177 $EndPAD $PAD @@ -6192,35 +6302,35 @@ $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/fpga2/M1_A4" +Ne 266 "/sdram/M1_A4" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 208 "/fpga2/R_M1_A4" +Ne 210 "/fpga2/R_M1_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 209 "/fpga2/R_M1_A5" +Ne 211 "/fpga2/R_M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 210 "/fpga2/R_M1_A6" +Ne 212 "/fpga2/R_M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 211 "/fpga2/R_M1_A7" +Ne 213 "/fpga2/R_M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6239,56 +6349,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 219 "/fpga2/R_M1_DQ0" +Ne 221 "/fpga2/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 220 "/fpga2/R_M1_DQ1" +Ne 222 "/fpga2/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 227 "/fpga2/R_M1_DQ2" +Ne 229 "/fpga2/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 228 "/fpga2/R_M1_DQ3" +Ne 230 "/fpga2/R_M1_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 151 "/fpga2/M1_DQ3" +Ne 272 "/sdram/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 276 "/sdram/M1_DQ2" +Ne 158 "/fpga2/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 272 "/sdram/M1_DQ1" +Ne 153 "/fpga2/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 271 "/sdram/M1_DQ0" +Ne 152 "/fpga2/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6307,56 +6417,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "/fpga2/R_M1_DQ4" +Ne 231 "/fpga2/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 230 "/fpga2/R_M1_DQ5" +Ne 232 "/fpga2/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "/fpga2/R_M1_DQ6" +Ne 233 "/fpga2/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 232 "/fpga2/R_M1_DQ7" +Ne 234 "/fpga2/R_M1_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/fpga2/M1_DQ7" +Ne 275 "/sdram/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 154 "/fpga2/M1_DQ6" +Ne 274 "/sdram/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/fpga2/M1_DQ5" +Ne 159 "/fpga2/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 152 "/fpga2/M1_DQ4" +Ne 273 "/sdram/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6375,56 +6485,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 237 "/fpga2/R_M1_RAS#" +Ne 239 "/fpga2/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 214 "/fpga2/R_M1_BA0" +Ne 216 "/fpga2/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 215 "/fpga2/R_M1_BA1" +Ne 217 "/fpga2/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 203 "/fpga2/R_M1_A10" +Ne 205 "/fpga2/R_M1_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 261 "/sdram/M1_A10" +Ne 263 "/sdram/M1_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 145 "/fpga2/M1_BA1" +Ne 268 "/sdram/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/fpga2/M1_BA0" +Ne 267 "/sdram/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/fpga2/M1_RAS#" +Ne 276 "/sdram/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6443,56 +6553,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "/fpga2/R_M1_A0" +Ne 203 "/fpga2/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 202 "/fpga2/R_M1_A1" +Ne 204 "/fpga2/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 206 "/fpga2/R_M1_A2" +Ne 208 "/fpga2/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 207 "/fpga2/R_M1_A3" +Ne 209 "/fpga2/R_M1_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 141 "/fpga2/M1_A3" +Ne 265 "/sdram/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 140 "/fpga2/M1_A2" +Ne 142 "/fpga2/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 139 "/fpga2/M1_A1" +Ne 140 "/fpga2/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 138 "/fpga2/M1_A0" +Ne 139 "/fpga2/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6743,49 +6853,49 @@ $PAD Sh "8" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -750 -1050 $EndPAD $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/fpga1/PROG_CSO" +Ne 104 "/fpga1/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/fpga1/PROG_MISO3" +Ne 108 "/fpga1/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/fpga1/PROG_CCLK" +Ne 103 "/fpga1/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/fpga1/PROG_MISO0" +Ne 105 "/fpga1/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/fpga1/PROG_MISO1" +Ne 106 "/fpga1/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/fpga1/PROG_MISO2" +Ne 107 "/fpga1/PROG_MISO2" Po 250 1050 $EndPAD $PAD @@ -6987,7 +7097,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -570 0 $EndPAD $PAD @@ -7183,7 +7293,7 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -373 0 $EndPAD $PAD @@ -7463,7 +7573,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7547,7 +7657,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7631,7 +7741,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7687,7 +7797,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7715,7 +7825,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 284 "/usb/USBD_D+" +Ne 286 "/usb/USBD_D+" Po -294 0 $EndPAD $PAD @@ -7743,7 +7853,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 285 "/usb/USBD_D-" +Ne 287 "/usb/USBD_D-" Po -294 0 $EndPAD $PAD @@ -7799,7 +7909,7 @@ $PAD Sh "1" R 197 354 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 297 "N-000143" +Ne 303 "N-000153" Po -294 0 $EndPAD $PAD @@ -7827,14 +7937,14 @@ $PAD Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 303 "N-000150" +Ne 302 "N-000150" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 302 "N-000149" +Ne 301 "N-000149" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7855,7 +7965,7 @@ $PAD Sh "1" R 197 354 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 296 "N-000142" +Ne 300 "N-000147" Po -294 0 $EndPAD $PAD @@ -8275,7 +8385,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 259 "/sdram/M0_VREF" +Ne 262 "/sdram/M0_VREF" Po -176 0 $EndPAD $PAD @@ -8310,7 +8420,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 259 "/sdram/M0_VREF" +Ne 262 "/sdram/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8387,7 +8497,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 259 "/sdram/M0_VREF" +Ne 262 "/sdram/M0_VREF" Po -176 0 $EndPAD $PAD @@ -8422,7 +8532,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 259 "/sdram/M0_VREF" +Ne 262 "/sdram/M0_VREF" Po 176 0 $EndPAD $EndMODULE 0402 @@ -8448,28 +8558,28 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 302 "N-000149" +Ne 301 "N-000149" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 281 "/usb/USBA_D-" +Ne 282 "/usb/USBA_D-" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 280 "/usb/USBA_D+" +Ne 281 "/usb/USBA_D+" Po 0 -787 $EndPAD $PAD Sh "4" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 296 "N-000142" +Ne 300 "N-000147" Po 0 0 $EndPAD $PAD @@ -8518,7 +8628,7 @@ $PAD Sh "1" R 355 984 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 303 "N-000150" +Ne 302 "N-000150" Po -570 0 $EndPAD $PAD @@ -8630,7 +8740,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 280 "/usb/USBA_D+" +Ne 281 "/usb/USBA_D+" Po -294 0 $EndPAD $PAD @@ -8658,7 +8768,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 281 "/usb/USBA_D-" +Ne 282 "/usb/USBA_D-" Po -294 0 $EndPAD $PAD @@ -8938,7 +9048,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 12 "/ether/ETH_MDIO" +Ne 60 "/fpga1/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -8966,7 +9076,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 295 "N-000133" +Ne 293 "N-000120" Po -176 0 $EndPAD $PAD @@ -9001,7 +9111,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 21 "/ether/MAG_TX+" +Ne 25 "/ether/MAG_TX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9029,7 +9139,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 22 "/ether/MAG_TX-" +Ne 26 "/ether/MAG_TX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9057,7 +9167,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/ether/MAG_RX+" +Ne 22 "/ether/MAG_RX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9085,7 +9195,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 19 "/ether/MAG_RX-" +Ne 23 "/ether/MAG_RX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9106,14 +9216,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 294 "N-000121" +Ne 294 "N-000131" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 10 "/ether/ETH_LED0" +Ne 11 "/ether/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9134,14 +9244,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 293 "N-000120" +Ne 295 "N-000132" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 11 "/ether/ETH_LED1" +Ne 12 "/ether/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9170,7 +9280,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/fpga2/M0_DQ0" +Ne 124 "/fpga2/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -9184,14 +9294,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 250 "/sdram/M0_DQ1" +Ne 125 "/fpga2/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/fpga2/M0_DQ2" +Ne 255 "/sdram/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -9212,7 +9322,7 @@ $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 253 "/sdram/M0_DQ4" +Ne 256 "/sdram/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -9226,14 +9336,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 254 "/sdram/M0_DQ5" +Ne 133 "/fpga2/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 255 "/sdram/M0_DQ6" +Ne 257 "/sdram/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -9247,7 +9357,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 256 "/sdram/M0_DQ7" +Ne 134 "/fpga2/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -9268,7 +9378,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/fpga2/M0_LDQS" +Ne 136 "/fpga2/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -9296,28 +9406,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 258 "/sdram/M0_LDM" +Ne 135 "/fpga2/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 260 "/sdram/M0_WE#" +Ne 138 "/fpga2/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 248 "/sdram/M0_CAS#" +Ne 122 "/fpga2/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/fpga2/M0_RAS#" +Ne 260 "/sdram/M0_RAS#" Po 1535 2176 $EndPAD $PAD @@ -9338,49 +9448,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 247 "/sdram/M0_BA0" +Ne 251 "/sdram/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/fpga2/M0_BA1" +Ne 252 "/sdram/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/fpga2/M0_A10" +Ne 248 "/sdram/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 245 "/sdram/M0_A0" +Ne 112 "/fpga2/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/fpga2/M0_A1" +Ne 113 "/fpga2/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/fpga2/M0_A2" +Ne 115 "/fpga2/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/fpga2/M0_A3" +Ne 116 "/fpga2/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -9401,7 +9511,7 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 246 "/sdram/M0_A4" +Ne 117 "/fpga2/M0_A4" Po 3838 -2176 $EndPAD $PAD @@ -9429,14 +9539,14 @@ $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/fpga2/M0_A8" +Ne 250 "/sdram/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/fpga2/M0_A9" +Ne 121 "/fpga2/M0_A9" Po 2558 -2176 $EndPAD $PAD @@ -9450,7 +9560,7 @@ $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/fpga2/M0_A12" +Ne 249 "/sdram/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -9464,28 +9574,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 249 "/sdram/M0_CLK#" +Ne 123 "/fpga2/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/fpga2/M0_CKE" +Ne 253 "/sdram/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/fpga2/M0_CLK" +Ne 254 "/sdram/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/fpga2/M0_UDM" +Ne 261 "/sdram/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -9499,7 +9609,7 @@ $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 259 "/sdram/M0_VREF" +Ne 262 "/sdram/M0_VREF" Po 255 -2176 $EndPAD $PAD @@ -9534,7 +9644,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 257 "/sdram/M0_DQ8" +Ne 258 "/sdram/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -9548,14 +9658,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/fpga2/M0_DQ9" +Ne 259 "/sdram/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/fpga2/M0_DQ10" +Ne 126 "/fpga2/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -9569,14 +9679,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/fpga2/M0_DQ11" +Ne 127 "/fpga2/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/fpga2/M0_DQ12" +Ne 128 "/fpga2/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -9590,7 +9700,7 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 251 "/sdram/M0_DQ13" +Ne 129 "/fpga2/M0_DQ13" Po -3070 -2176 $EndPAD $PAD @@ -9611,7 +9721,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 252 "/sdram/M0_DQ15" +Ne 131 "/fpga2/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -9647,7 +9757,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 271 "/sdram/M1_DQ0" +Ne 152 "/fpga2/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -9661,14 +9771,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 272 "/sdram/M1_DQ1" +Ne 153 "/fpga2/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 276 "/sdram/M1_DQ2" +Ne 158 "/fpga2/M1_DQ2" Po -3070 2176 $EndPAD $PAD @@ -9682,14 +9792,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/fpga2/M1_DQ3" +Ne 272 "/sdram/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/fpga2/M1_DQ4" +Ne 273 "/sdram/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -9703,14 +9813,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/fpga2/M1_DQ5" +Ne 159 "/fpga2/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/fpga2/M1_DQ6" +Ne 274 "/sdram/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -9724,7 +9834,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/fpga2/M1_DQ7" +Ne 275 "/sdram/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -9745,7 +9855,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/fpga2/M1_LDQS" +Ne 163 "/fpga2/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -9773,35 +9883,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 278 "/sdram/M1_LDM" +Ne 162 "/fpga2/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/fpga2/M1_WE#" +Ne 280 "/sdram/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/fpga2/M1_CAS#" +Ne 148 "/fpga2/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/fpga2/M1_RAS#" +Ne 276 "/sdram/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 270 "/sdram/M1_CS#" +Ne 151 "/fpga2/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -9815,49 +9925,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/fpga2/M1_BA0" +Ne 267 "/sdram/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/fpga2/M1_BA1" +Ne 268 "/sdram/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 261 "/sdram/M1_A10" +Ne 263 "/sdram/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/fpga2/M1_A0" +Ne 139 "/fpga2/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/fpga2/M1_A1" +Ne 140 "/fpga2/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/fpga2/M1_A2" +Ne 142 "/fpga2/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/fpga2/M1_A3" +Ne 265 "/sdram/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -9878,7 +9988,7 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/fpga2/M1_A4" +Ne 266 "/sdram/M1_A4" Po 3838 -2176 $EndPAD $PAD @@ -9892,42 +10002,42 @@ $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 264 "/sdram/M1_A6" +Ne 144 "/fpga2/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 265 "/sdram/M1_A7" +Ne 145 "/fpga2/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 266 "/sdram/M1_A8" +Ne 146 "/fpga2/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 267 "/sdram/M1_A9" +Ne 147 "/fpga2/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 262 "/sdram/M1_A11" +Ne 264 "/sdram/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 263 "/sdram/M1_A12" +Ne 141 "/fpga2/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -9941,28 +10051,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 269 "/sdram/M1_CLK#" +Ne 150 "/fpga2/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/fpga2/M1_CKE" +Ne 269 "/sdram/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 268 "/sdram/M1_CLK" +Ne 149 "/fpga2/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/fpga2/M1_UDM" +Ne 277 "/sdram/M1_UDM" Po 767 -2176 $EndPAD $PAD @@ -9990,7 +10100,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/fpga2/M1_UDQS" +Ne 278 "/sdram/M1_UDQS" Po -255 -2176 $EndPAD $PAD @@ -10011,7 +10121,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/fpga2/M1_DQ8" +Ne 160 "/fpga2/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10025,14 +10135,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 277 "/sdram/M1_DQ9" +Ne 161 "/fpga2/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/fpga2/M1_DQ10" +Ne 154 "/fpga2/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -10046,14 +10156,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 273 "/sdram/M1_DQ11" +Ne 270 "/sdram/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/fpga2/M1_DQ12" +Ne 155 "/fpga2/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10067,14 +10177,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/fpga2/M1_DQ13" +Ne 156 "/fpga2/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 274 "/sdram/M1_DQ14" +Ne 271 "/sdram/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10088,7 +10198,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 275 "/sdram/M1_DQ15" +Ne 157 "/fpga2/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10115,35 +10225,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 20 "/ether/MAG_SHIELD" +Ne 24 "/ether/MAG_SHIELD" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 20 "/ether/MAG_SHIELD" +Ne 24 "/ether/MAG_SHIELD" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 20 "/ether/MAG_SHIELD" +Ne 24 "/ether/MAG_SHIELD" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 20 "/ether/MAG_SHIELD" +Ne 24 "/ether/MAG_SHIELD" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 21 "/ether/MAG_TX+" +Ne 25 "/ether/MAG_TX+" Po -1750 -2500 $EndPAD $PAD @@ -10164,14 +10274,14 @@ $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 18 "/ether/MAG_RX+" +Ne 22 "/ether/MAG_RX+" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 22 "/ether/MAG_TX-" +Ne 26 "/ether/MAG_TX-" Po -1250 -3500 $EndPAD $PAD @@ -10192,7 +10302,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 19 "/ether/MAG_RX-" +Ne 23 "/ether/MAG_RX-" Po 1750 -3500 $EndPAD $PAD @@ -10206,7 +10316,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 294 "N-000121" +Ne 294 "N-000131" Po -1150 -5400 $EndPAD $PAD @@ -10220,7 +10330,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 293 "N-000120" +Ne 295 "N-000132" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -10245,21 +10355,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 61 "/flash/SD_DAT2" +Ne 57 "/flash/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 62 "/flash/SD_DAT3" +Ne 111 "/fpga1/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 59 "/flash/SD_CMD" +Ne 55 "/flash/SD_CMD" Po -433 0 $EndPAD $PAD @@ -10273,7 +10383,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 110 "/fpga1/SD_CLK" +Ne 109 "/fpga1/SD_CLK" Po 433 0 $EndPAD $PAD @@ -10287,14 +10397,14 @@ $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 111 "/fpga1/SD_DAT0" +Ne 56 "/flash/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 60 "/flash/SD_DAT1" +Ne 110 "/fpga1/SD_DAT1" Po 1732 0 $EndPAD $PAD @@ -10586,28 +10696,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/fpga1/NF_RNB" +Ne 53 "/flash/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/fpga1/NF_RNB" +Ne 53 "/flash/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/flash/NF_RE_N" +Ne 102 "/fpga1/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/fpga1/NF_CS1_N" +Ne 95 "/fpga1/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -10656,21 +10766,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/flash/NF_CLE" +Ne 94 "/fpga1/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/fpga1/NF_ALE" +Ne 93 "/fpga1/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/flash/NF_WE_N" +Ne 54 "/flash/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -10747,28 +10857,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/fpga1/NF_D0" +Ne 96 "/fpga1/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/fpga1/NF_D1" +Ne 97 "/fpga1/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/flash/NF_D2" +Ne 98 "/fpga1/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/fpga1/NF_D3" +Ne 51 "/flash/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -10831,28 +10941,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/flash/NF_D4" +Ne 99 "/fpga1/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/flash/NF_D5" +Ne 52 "/flash/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/fpga1/NF_D6" +Ne 100 "/fpga1/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/fpga1/NF_D7" +Ne 101 "/fpga1/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -10909,21 +11019,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/ether/ETH_RXER" +Ne 65 "/fpga1/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/fpga1/ETH_RXC" +Ne 62 "/fpga1/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/ether/ETH_RXDV" +Ne 64 "/fpga1/ETH_RXDV" Po -1613 491 $EndPAD $PAD @@ -10951,42 +11061,42 @@ $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/fpga1/ETH_RXD1" +Ne 63 "/fpga1/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/fpga1/ETH_RXD2" +Ne 15 "/ether/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/fpga1/ETH_RXD3" +Ne 16 "/ether/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/fpga1/ETH_MDC" +Ne 59 "/fpga1/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/ether/ETH_MDIO" +Ne 60 "/fpga1/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/fpga1/ETH_RESET_N" +Ne 61 "/fpga1/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD @@ -11000,7 +11110,7 @@ $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/fpga1/ETH_CLK" +Ne 8 "/ether/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -11035,14 +11145,14 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/ether/MAG_TX+" +Ne 25 "/ether/MAG_TX+" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/ether/MAG_TX-" +Ne 26 "/ether/MAG_TX-" Po 491 -1613 $EndPAD $PAD @@ -11063,28 +11173,28 @@ $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 295 "N-000133" +Ne 293 "N-000120" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/ether/ETH_INT" +Ne 10 "/ether/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/ether/ETH_LED0" +Ne 11 "/ether/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/ether/ETH_LED1" +Ne 12 "/ether/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -11119,14 +11229,14 @@ $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/ether/MAG_RX-" +Ne 23 "/ether/MAG_RX-" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/ether/MAG_RX+" +Ne 22 "/ether/MAG_RX+" Po 1613 -491 $EndPAD $PAD @@ -11161,63 +11271,63 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/ether/ETH_TXER" +Ne 21 "/ether/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/fpga1/ETH_TXC" +Ne 17 "/ether/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/fpga1/ETH_TXEN" +Ne 67 "/fpga1/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/fpga1/ETH_TXD0" +Ne 18 "/ether/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/fpga1/ETH_TXD1" +Ne 66 "/fpga1/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/fpga1/ETH_TXD2" +Ne 19 "/ether/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/fpga1/ETH_TXD3" +Ne 20 "/ether/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/fpga1/ETH_COL" +Ne 9 "/ether/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/ether/ETH_CRS" +Ne 58 "/fpga1/ETH_CRS" Po 688 1613 $EndPAD $PAD @@ -11315,7 +11425,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 306 "N-000359" +Ne 328 "N-000350" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11343,7 +11453,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 305 "N-000356" +Ne 327 "N-000347" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11379,28 +11489,28 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 287 "/usb/USBD_SPD" +Ne 247 "/fpga2/USBD_SPD" Po -295 491 $EndPAD $PAD Sh "11" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 300 "N-000146" +Ne 299 "N-000144" Po -98 -491 $EndPAD $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 244 "/fpga2/USBD_RCV" +Ne 246 "/fpga2/USBD_RCV" Po -98 491 $EndPAD $PAD Sh "10" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 299 "N-000145" +Ne 298 "N-000143" Po 98 -491 $EndPAD $PAD @@ -11414,7 +11524,7 @@ $PAD Sh "9" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 286 "/usb/USBD_OE_N" +Ne 245 "/fpga2/USBD_OE_N" Po 295 -491 $EndPAD $PAD @@ -11513,49 +11623,49 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 283 "/usb/USBA_SPD" +Ne 284 "/usb/USBA_SPD" Po -295 491 $EndPAD $PAD Sh "11" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 298 "N-000144" +Ne 296 "N-000141" Po -98 -491 $EndPAD $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 241 "/fpga2/USBA_RCV" +Ne 243 "/fpga2/USBA_RCV" Po -98 491 $EndPAD $PAD Sh "10" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 301 "N-000147" +Ne 297 "N-000142" Po 98 -491 $EndPAD $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 243 "/fpga2/USBA_VP" +Ne 244 "/fpga2/USBA_VP" Po 98 491 $EndPAD $PAD Sh "9" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 282 "/usb/USBA_OE_N" +Ne 283 "/usb/USBA_OE_N" Po 295 -491 $EndPAD $PAD Sh "4" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 242 "/fpga2/USBA_VM" +Ne 285 "/usb/USBA_VM" Po 295 491 $EndPAD $PAD @@ -11896,28 +12006,28 @@ $PAD Sh "2" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 285 "/usb/USBD_D-" +Ne 287 "/usb/USBD_D-" Po 310 0 $EndPAD $PAD Sh "3" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 284 "/usb/USBD_D+" +Ne 286 "/usb/USBD_D+" Po 630 0 $EndPAD $PAD Sh "4" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 297 "N-000143" +Ne 303 "N-000153" Po 940 0 $EndPAD $PAD Sh "5" R 200 620 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 297 "N-000143" +Ne 303 "N-000153" Po 1260 0 $EndPAD $PAD @@ -11987,7 +12097,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 284 "/usb/USBD_D+" +Ne 286 "/usb/USBD_D+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12015,7 +12125,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 285 "/usb/USBD_D-" +Ne 287 "/usb/USBD_D-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12043,7 +12153,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 284 "/usb/USBD_D+" +Ne 286 "/usb/USBD_D+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12064,14 +12174,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 281 "/usb/USBA_D-" +Ne 282 "/usb/USBA_D-" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 301 "N-000147" +Ne 297 "N-000142" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12092,14 +12202,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 280 "/usb/USBA_D+" +Ne 281 "/usb/USBA_D+" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 298 "N-000144" +Ne 296 "N-000141" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12120,14 +12230,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 285 "/usb/USBD_D-" +Ne 287 "/usb/USBD_D-" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 299 "N-000145" +Ne 298 "N-000143" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12148,14 +12258,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 284 "/usb/USBD_D+" +Ne 286 "/usb/USBD_D+" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 300 "N-000146" +Ne 299 "N-000144" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12183,7 +12293,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 280 "/usb/USBA_D+" +Ne 281 "/usb/USBA_D+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12211,7 +12321,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 280 "/usb/USBA_D+" +Ne 281 "/usb/USBA_D+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12239,7 +12349,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 281 "/usb/USBA_D-" +Ne 282 "/usb/USBA_D-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12316,7 +12426,7 @@ $PAD Sh "1" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/ether/MAG_SHIELD" +Ne 24 "/ether/MAG_SHIELD" Po -570 0 $EndPAD $PAD @@ -12345,7 +12455,7 @@ $PAD Sh "1" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 51 "/expansion/FPGA_BANK0_IO_8" +Ne 92 "/fpga1/FPGA_BANK0_IO_8" Po 9448 -747 $EndPAD $PAD @@ -12359,63 +12469,63 @@ $PAD Sh "5" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po 7873 -747 $EndPAD $PAD Sh "7" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/expansion/FPGA_BANK0_IO_10" +Ne 68 "/fpga1/FPGA_BANK0_IO_10" Po 7086 -747 $EndPAD $PAD Sh "9" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 77 "/fpga1/FPGA_BANK0_IO_11" +Ne 69 "/fpga1/FPGA_BANK0_IO_11" Po 6299 -747 $EndPAD $PAD Sh "11" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 45 "/expansion/FPGA_BANK0_IO_5" +Ne 43 "/expansion/FPGA_BANK0_IO_5" Po 5511 -747 $EndPAD $PAD Sh "13" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/expansion/FPGA_BANK0_IO_17" +Ne 30 "/expansion/FPGA_BANK0_IO_17" Po 4724 -747 $EndPAD $PAD Sh "15" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 80 "/fpga1/FPGA_BANK0_IO_20" +Ne 72 "/fpga1/FPGA_BANK0_IO_20" Po 3936 -747 $EndPAD $PAD Sh "17" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 83 "/fpga1/FPGA_BANK0_IO_28" +Ne 35 "/expansion/FPGA_BANK0_IO_28" Po 3149 -747 $EndPAD $PAD Sh "19" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 81 "/fpga1/FPGA_BANK0_IO_22" +Ne 73 "/fpga1/FPGA_BANK0_IO_22" Po 2362 -747 $EndPAD $PAD Sh "21" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/expansion/FPGA_BANK0_IO_27" +Ne 34 "/expansion/FPGA_BANK0_IO_27" Po 1574 -747 $EndPAD $PAD @@ -12429,63 +12539,63 @@ $PAD Sh "25" R 392 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 79 "/fpga1/FPGA_BANK0_IO_2" +Ne 71 "/fpga1/FPGA_BANK0_IO_2" Po 0 -747 $EndPAD $PAD Sh "27" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/fpga1/FPGA_BANK0_IO_7" +Ne 91 "/fpga1/FPGA_BANK0_IO_7" Po -787 -747 $EndPAD $PAD Sh "29" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/expansion/FPGA_BANK0_IO_12" +Ne 28 "/expansion/FPGA_BANK0_IO_12" Po -1574 -747 $EndPAD $PAD Sh "31" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 86 "/fpga1/FPGA_BANK0_IO_44" +Ne 81 "/fpga1/FPGA_BANK0_IO_44" Po -2362 -747 $EndPAD $PAD Sh "33" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 43 "/expansion/FPGA_BANK0_IO_47" +Ne 83 "/fpga1/FPGA_BANK0_IO_47" Po -3149 -747 $EndPAD $PAD Sh "35" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/expansion/FPGA_BANK0_IO_45" +Ne 82 "/fpga1/FPGA_BANK0_IO_45" Po -3936 -747 $EndPAD $PAD Sh "37" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 90 "/fpga1/FPGA_BANK0_IO_52" +Ne 45 "/expansion/FPGA_BANK0_IO_52" Po -4724 -747 $EndPAD $PAD Sh "39" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 91 "/fpga1/FPGA_BANK0_IO_56" +Ne 48 "/expansion/FPGA_BANK0_IO_56" Po -5511 -747 $EndPAD $PAD Sh "41" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 89 "/fpga1/FPGA_BANK0_IO_51" +Ne 85 "/fpga1/FPGA_BANK0_IO_51" Po -6299 -747 $EndPAD $PAD @@ -12499,7 +12609,7 @@ $PAD Sh "45" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 50 "/expansion/FPGA_BANK0_IO_63" +Ne 49 "/expansion/FPGA_BANK0_IO_63" Po -7873 -747 $EndPAD $PAD @@ -12513,105 +12623,105 @@ $PAD Sh "49" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 92 "/fpga1/FPGA_BANK0_IO_58" +Ne 87 "/fpga1/FPGA_BANK0_IO_58" Po -9448 -747 $EndPAD $PAD Sh "2" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 23 "/expansion/FPGA_BANK0_IO_1" +Ne 27 "/expansion/FPGA_BANK0_IO_1" Po 9448 747 $EndPAD $PAD Sh "4" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 52 "/expansion/FPGA_BANK0_IO_9" +Ne 50 "/expansion/FPGA_BANK0_IO_9" Po 8661 747 $EndPAD $PAD Sh "6" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 26 "/expansion/FPGA_BANK0_IO_14" +Ne 70 "/fpga1/FPGA_BANK0_IO_14" Po 7873 747 $EndPAD $PAD Sh "8" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 27 "/expansion/FPGA_BANK0_IO_15" +Ne 29 "/expansion/FPGA_BANK0_IO_15" Po 7086 747 $EndPAD $PAD Sh "10" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 33 "/expansion/FPGA_BANK0_IO_3" +Ne 76 "/fpga1/FPGA_BANK0_IO_3" Po 6299 747 $EndPAD $PAD Sh "12" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 78 "/fpga1/FPGA_BANK0_IO_18" +Ne 31 "/expansion/FPGA_BANK0_IO_18" Po 5511 747 $EndPAD $PAD Sh "14" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 29 "/expansion/FPGA_BANK0_IO_21" +Ne 32 "/expansion/FPGA_BANK0_IO_21" Po 4724 747 $EndPAD $PAD Sh "16" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 30 "/expansion/FPGA_BANK0_IO_24" +Ne 74 "/fpga1/FPGA_BANK0_IO_24" Po 3936 747 $EndPAD $PAD Sh "18" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 32 "/expansion/FPGA_BANK0_IO_29" +Ne 75 "/fpga1/FPGA_BANK0_IO_29" Po 3149 747 $EndPAD $PAD Sh "20" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 34 "/expansion/FPGA_BANK0_IO_30" +Ne 77 "/fpga1/FPGA_BANK0_IO_30" Po 2362 747 $EndPAD $PAD Sh "22" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 82 "/fpga1/FPGA_BANK0_IO_25" +Ne 33 "/expansion/FPGA_BANK0_IO_25" Po 1574 747 $EndPAD $PAD Sh "24" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 84 "/fpga1/FPGA_BANK0_IO_33" +Ne 78 "/fpga1/FPGA_BANK0_IO_33" Po 787 747 $EndPAD $PAD Sh "26" R 392 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 35 "/expansion/FPGA_BANK0_IO_32" +Ne 36 "/expansion/FPGA_BANK0_IO_32" Po 0 747 $EndPAD $PAD Sh "28" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 93 "/fpga1/FPGA_BANK0_IO_6" +Ne 88 "/fpga1/FPGA_BANK0_IO_6" Po -787 747 $EndPAD $PAD @@ -12625,7 +12735,7 @@ $PAD Sh "32" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 85 "/fpga1/FPGA_BANK0_IO_40" +Ne 80 "/fpga1/FPGA_BANK0_IO_40" Po -2362 747 $EndPAD $PAD @@ -12639,56 +12749,56 @@ $PAD Sh "36" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 42 "/expansion/FPGA_BANK0_IO_46" +Ne 41 "/expansion/FPGA_BANK0_IO_46" Po -3936 747 $EndPAD $PAD Sh "38" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 88 "/fpga1/FPGA_BANK0_IO_50" +Ne 44 "/expansion/FPGA_BANK0_IO_50" Po -4724 747 $EndPAD $PAD Sh "40" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 87 "/fpga1/FPGA_BANK0_IO_48" +Ne 84 "/fpga1/FPGA_BANK0_IO_48" Po -5511 747 $EndPAD $PAD Sh "42" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 36 "/expansion/FPGA_BANK0_IO_34" +Ne 79 "/fpga1/FPGA_BANK0_IO_34" Po -6299 747 $EndPAD $PAD Sh "44" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 44 "/expansion/FPGA_BANK0_IO_49" +Ne 42 "/expansion/FPGA_BANK0_IO_49" Po -7086 747 $EndPAD $PAD Sh "46" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 94 "/fpga1/FPGA_BANK0_IO_62" +Ne 90 "/fpga1/FPGA_BANK0_IO_62" Po -7873 747 $EndPAD $PAD Sh "48" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 48 "/expansion/FPGA_BANK0_IO_57" +Ne 86 "/fpga1/FPGA_BANK0_IO_57" Po -8661 747 $EndPAD $PAD Sh "50" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 49 "/expansion/FPGA_BANK0_IO_60" +Ne 89 "/fpga1/FPGA_BANK0_IO_60" Po -9448 747 $EndPAD $PAD @@ -12884,14 +12994,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 196 "/fpga2/R_M0_LDQS" +Ne 198 "/fpga2/R_M0_LDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 134 "/fpga2/M0_LDQS" +Ne 136 "/fpga2/M0_LDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12912,14 +13022,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 195 "/fpga2/R_M0_LDM" +Ne 197 "/fpga2/R_M0_LDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 258 "/sdram/M0_LDM" +Ne 135 "/fpga2/M0_LDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12940,14 +13050,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 200 "/fpga2/R_M0_WE#" +Ne 202 "/fpga2/R_M0_WE#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 260 "/sdram/M0_WE#" +Ne 138 "/fpga2/M0_WE#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12968,14 +13078,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 177 "/fpga2/R_M0_CAS#" +Ne 179 "/fpga2/R_M0_CAS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 248 "/sdram/M0_CAS#" +Ne 122 "/fpga2/M0_CAS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -12996,14 +13106,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 236 "/fpga2/R_M1_LDQS" +Ne 238 "/fpga2/R_M1_LDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/fpga2/M1_LDQS" +Ne 163 "/fpga2/M1_LDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13024,14 +13134,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 235 "/fpga2/R_M1_LDM" +Ne 237 "/fpga2/R_M1_LDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 278 "/sdram/M1_LDM" +Ne 162 "/fpga2/M1_LDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13052,14 +13162,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 240 "/fpga2/R_M1_WE#" +Ne 242 "/fpga2/R_M1_WE#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/fpga2/M1_WE#" +Ne 280 "/sdram/M1_WE#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13080,14 +13190,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 216 "/fpga2/R_M1_CAS#" +Ne 218 "/fpga2/R_M1_CAS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 146 "/fpga2/M1_CAS#" +Ne 148 "/fpga2/M1_CAS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13115,7 +13225,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13157,7 +13267,7 @@ $PAD Sh "4" R 551 453 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 307 "VCCO2" +Ne 329 "VCCO2" Po 0 630 $EndPAD $EndMODULE CRYSTAL @@ -13178,7 +13288,7 @@ $PAD Sh "1" R 197 354 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 20 "/ether/MAG_SHIELD" +Ne 24 "/ether/MAG_SHIELD" Po -294 0 $EndPAD $PAD @@ -13263,56 +13373,56 @@ $PAD Sh "1" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 292 "GND" Po -383 905 $EndPAD $PAD Sh "8" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 326 "N-000190" Po -383 -905 $EndPAD $PAD Sh "2" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 316 "N-000171" Po -127 905 $EndPAD $PAD Sh "7" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 317 "N-000172" Po -127 -905 $EndPAD $PAD Sh "3" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 324 "N-000188" Po 127 905 $EndPAD $PAD Sh "6" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 316 "N-000171" Po 127 -905 $EndPAD $PAD Sh "4" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 325 "N-000189" Po 383 905 $EndPAD $PAD Sh "5" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 292 "GND" Po 383 -905 $EndPAD $EndMODULE MINI-SO-8 @@ -13369,7 +13479,7 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 304 "N-000178" +Ne 313 "N-000168" Po -393 -688 $EndPAD $PAD @@ -13383,91 +13493,91 @@ $PAD Sh "2" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 313 "N-000168" Po -196 -688 $EndPAD $PAD Sh "13" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 319 "N-000177" Po 0 688 $EndPAD $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 313 "N-000168" Po 0 -688 $EndPAD $PAD Sh "12" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 314 "N-000169" Po 196 688 $EndPAD $PAD Sh "4" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 313 "N-000168" Po 196 -688 $EndPAD $PAD Sh "11" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 320 "N-000178" Po 393 688 $EndPAD $PAD Sh "5" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 313 "N-000168" Po 393 -688 $EndPAD $PAD Sh "20" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 320 "N-000178" Po -688 -393 $EndPAD $PAD Sh "6" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 321 "N-000179" Po 688 -393 $EndPAD $PAD Sh "19" R 157 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 320 "N-000178" Po -688 -196 $EndPAD $PAD Sh "7" R 157 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 321 "N-000179" Po 688 -196 $EndPAD $PAD Sh "18" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 320 "N-000178" Po -688 0 $EndPAD $PAD Sh "8" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 321 "N-000179" Po 688 0 $EndPAD $PAD @@ -13481,7 +13591,7 @@ $PAD Sh "9" R 157 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 307 "N-000161" Po 688 196 $EndPAD $PAD @@ -13495,7 +13605,7 @@ $PAD Sh "10" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 306 "N-000160" Po 688 393 $EndPAD $EndMODULE MLF20m1 @@ -13524,7 +13634,7 @@ $PAD Sh "1" R 197 355 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 305 "N-000158" Po -749 1003 $EndPAD $PAD @@ -13538,42 +13648,42 @@ $PAD Sh "2" R 197 355 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 310 "N-000165" Po -249 1003 $EndPAD $PAD Sh "7" R 197 355 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 310 "N-000165" Po -249 -1003 $EndPAD $PAD Sh "3" R 197 355 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 304 "N-000157" Po 249 1003 $EndPAD $PAD Sh "6" R 197 355 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 309 "N-000164" Po 249 -1003 $EndPAD $PAD Sh "4" R 197 355 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 292 "GND" Po 749 1003 $EndPAD $PAD Sh "5" R 197 355 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 292 "GND" Po 749 -1003 $EndPAD $EndMODULE SON008V5060 @@ -13602,7 +13712,7 @@ $PAD Sh "1" R 157 185 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 322 "N-000182" Po -255 340 $EndPAD $PAD @@ -13616,14 +13726,14 @@ $PAD Sh "2" R 156 185 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 292 "GND" Po 0 340 $EndPAD $PAD Sh "5" R 156 185 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 311 "N-000166" Po 0 -340 $EndPAD $PAD @@ -13637,10 +13747,962 @@ $PAD Sh "4" R 157 185 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 292 "GND" Po 255 -340 $EndPAD $EndMODULE UDFN6 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8BD ~~ +Li 0402 +Sc 4D17D8BD +AR /4C69ED5F/4D13F523 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R96" +T1 0 150 200 200 0 40 N I 25 N"R" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 323 "N-000183" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 305 "N-000158" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8BF ~~ +Li 0402 +Sc 4D17D8BF +AR /4C69ED5F/4D13F52F +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R95" +T1 0 150 200 200 0 40 N I 25 N"R" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 305 "N-000158" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8C1 ~~ +Li 0402 +Sc 4D17D8C1 +AR /4C69ED5F/4D13F539 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R87" +T1 0 150 200 200 0 40 N I 25 N"R" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 304 "N-000157" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 308 "N-000163" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8C3 ~~ +Li 0402 +Sc 4D17D8C3 +AR /4C69ED5F/4D13F557 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C161" +T1 0 150 200 200 0 40 N I 25 N"CAP" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 308 "N-000163" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8C5 ~~ +Li 0402 +Sc 4D17D8C5 +AR /4C69ED5F/4D13FB88 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R91" +T1 0 150 200 200 0 40 N I 25 N"R" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 318 "N-000174" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 314 "N-000169" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8C7 ~~ +Li 0402 +Sc 4D17D8C7 +AR /4C69ED5F/4D13FBBF +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C166" +T1 0 150 200 200 0 40 N I 25 N"CAP" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 307 "N-000161" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 313 "N-000168" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8C9 ~~ +Li 0402 +Sc 4D17D8C9 +AR /4C69ED5F/4D13FC4E +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R93" +T1 0 150 200 200 0 40 N I 25 N"R" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 306 "N-000160" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 321 "N-000179" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8CB ~~ +Li 0402 +Sc 4D17D8CB +AR /4C69ED5F/4D13FCCF +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C163" +T1 0 150 200 200 0 40 N I 25 N"CAP" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 306 "N-000160" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8CD ~~ +Li 0402 +Sc 4D17D8CD +AR /4C69ED5F/4D13FD6A +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R90" +T1 0 150 200 200 0 40 N I 25 N"R" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 314 "N-000169" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8CF ~~ +Li 0402 +Sc 4D17D8CF +AR /4C69ED5F/4D13FE0D +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R88" +T1 0 150 200 200 0 40 N I 25 N"12k" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 315 "N-000170" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 319 "N-000177" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8D1 ~~ +Li 0402 +Sc 4D17D8D1 +AR /4C69ED5F/4D13FE2C +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C162" +T1 0 150 200 200 0 40 N I 25 N"560pF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 315 "N-000170" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8D3 ~~ +Li 0402 +Sc 4D17D8D3 +AR /4C69ED5F/4D13FEFF +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C174" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 318 "N-000174" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8D5 ~~ +Li 0402 +Sc 4D17D8D5 +AR /4C69ED5F/4D13FF2F +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C171" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 323 "N-000183" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8D7 ~~ +Li 0402 +Sc 4D17D8D7 +AR /4C69ED5F/4D140162 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C169" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 322 "N-000182" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8D9 ~~ +Li 0402 +Sc 4D17D8D9 +AR /4C69ED5F/4D140603 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R94" +T1 0 150 200 200 0 40 N I 25 N"200k" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 324 "N-000188" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 316 "N-000171" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8DB ~~ +Li 0402 +Sc 4D17D8DB +AR /4C69ED5F/4D140604 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R89" +T1 0 150 200 200 0 40 N I 25 N"50k_1%" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 325 "N-000189" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8DD ~~ +Li 0402 +Sc 4D17D8DD +AR /4C69ED5F/4D14063B +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C173" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 317 "N-000172" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8DF ~~ +Li 0402 +Sc 4D17D8DF +AR /4C69ED5F/4D140643 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C158" +T1 0 150 200 200 0 40 N I 25 N"22uF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 312 "N-000167" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8E1 ~~ +Li 0402 +Sc 4D17D8E1 +AR /4C69ED5F/4D140650 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R92" +T1 0 150 200 200 0 40 N I 25 N"150k_1%" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 325 "N-000189" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 317 "N-000172" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8E3 ~~ +Li 0402 +Sc 4D17D8E3 +AR /4C69ED5F/4D140659 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C164" +T1 0 150 200 200 0 40 N I 25 N"39pF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 317 "N-000172" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 325 "N-000189" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8E5 ~~ +Li 0402 +Sc 4D17D8E5 +AR /4C69ED5F/4D140674 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"R97" +T1 0 150 200 200 0 40 N I 25 N"500" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 316 "N-000171" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 317 "N-000172" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 72005 62832 0 15 4D17D728 4D17D8E7 ~~ +Li 0402 +Sc 4D17D8E7 +AR /4C69ED5F/4D1408E4 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C165" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 316 "N-000171" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0603 +Po 72005 62832 0 15 4D17D728 4D17D8E8 ~~ +Li 0603 +Sc 4D17D8E8 +AR /4C69ED5F/4D14016D +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C160" +T1 0 150 200 200 0 40 N I 25 N"4.7uF" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0805 +Po 72005 62832 0 15 4D17D728 4D17D8E9 ~~ +Li 0805 +Sc 4D17D8E9 +AR /4C69ED5F/4D140163 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C167" +T1 0 150 200 200 0 40 N I 25 N"10uF" +DS -561 305 -561 -305 50 21 +DS -561 -305 561 -305 50 21 +DS 561 -305 561 305 50 21 +DS 561 305 -561 305 50 21 +$PAD +Sh "1" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 322 "N-000182" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0805 +Po 72005 62832 0 15 4D17D728 4D17D8EB ~~ +Li 0805 +Sc 4D17D8EB +AR /4C69ED5F/4D140153 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L9" +T1 0 150 200 200 0 40 N I 25 N"2.2uF" +DS -561 305 -561 -305 50 21 +DS -561 -305 561 -305 50 21 +DS 561 -305 561 305 50 21 +DS 561 305 -561 305 50 21 +$PAD +Sh "1" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 322 "N-000182" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 311 "N-000166" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0805 +Po 72005 62832 0 15 4D17D728 4D17D8ED ~~ +Li 0805 +Sc 4D17D8ED +AR /4C69ED5F/4D160B09 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"D1" +T1 0 150 200 200 0 40 N I 25 N"MBRS140T3" +DS -561 305 -561 -305 50 21 +DS -561 -305 561 -305 50 21 +DS 561 -305 561 305 50 21 +DS 561 305 -561 305 50 21 +$PAD +Sh "1" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 326 "N-000190" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 317 "N-000172" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 1210 +Po 72005 62832 0 15 4D17D728 4D17D8EE ~~ +Li 1210 +Sc 4D17D8EE +AR /4C69ED5F/4D13F1A3 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C157" +T1 0 150 200 200 0 40 N I 25 N"CAP" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 72005 62832 0 15 4D17D728 4D17D8F0 ~~ +Li 1210 +Sc 4D17D8F0 +AR /4C69ED5F/4D13F22A +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L10" +T1 0 150 200 200 0 40 N I 25 N"INDUCTOR" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 323 "N-000183" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 309 "N-000164" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 72005 62832 0 15 4D17D728 4D17D8F2 ~~ +Li 1210 +Sc 4D17D8F2 +AR /4C69ED5F/4D13FB89 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L11" +T1 0 150 200 200 0 40 N I 25 N"2.2uH" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 318 "N-000174" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 313 "N-000168" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 72005 62832 0 15 4D17D728 4D17D8F4 ~~ +Li 1210 +Sc 4D17D8F4 +AR /4C69ED5F/4D13FB8D +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C172" +T1 0 150 200 200 0 40 N I 25 N"22uF" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 318 "N-000174" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 72005 62832 0 15 4D17D728 4D17D8F6 ~~ +Li 1210 +Sc 4D17D8F6 +AR /4C69ED5F/4D13FEB6 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C159" +T1 0 150 200 200 0 40 N I 25 N"22uF" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 0 "" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 72005 62832 0 15 4D17D728 4D17D8F8 ~~ +Li 1210 +Sc 4D17D8F8 +AR /4C69ED5F/4D13FF30 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C168" +T1 0 150 200 200 0 40 N I 25 N"CAP" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 323 "N-000183" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 72005 62832 0 15 4D17D728 4D17D8FA ~~ +Li 1210 +Sc 4D17D8FA +AR /4C69ED5F/4D1405EB +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L8" +T1 0 150 200 200 0 40 N I 25 N"6.8uH" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 326 "N-000190" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 312 "N-000167" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 72005 62832 0 15 4D17D728 4D17D8FC ~~ +Li 1210 +Sc 4D17D8FC +AR /4C69ED5F/4D14063A +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C170" +T1 0 150 200 200 0 40 N I 25 N"68uF" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 317 "N-000172" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 570 0 +$EndPAD +$EndMODULE 1210 $COTATION Ge 0 25 0 Va 39410 @@ -15260,133 +16322,133 @@ Po 3 47431 25453 47431 25453 157 -1 De 15 1 7 0 0 Po 0 47365 25387 47431 25453 118 -1 De 15 0 7 0 0 -Po 0 52087 27530 52087 28563 39 -1 +Po 0 50965 29675 52973 29675 39 -1 De 0 0 8 0 0 -Po 0 50574 25584 52077 27087 39 -1 -De 15 0 8 0 0 -Po 0 52077 27087 52077 27520 39 -1 -De 15 0 8 0 0 -Po 0 52077 27520 52087 27530 39 -1 -De 15 0 8 0 0 -Po 3 52087 27530 52087 27530 157 -1 -De 15 1 8 0 0 -Po 0 50288 25584 50574 25584 39 -1 -De 15 0 8 0 800 -Po 0 55476 30436 55679 30639 39 -1 +Po 0 53317 30049 53317 30245 39 -1 De 15 0 8 0 400 -Po 0 55476 30054 55476 30436 39 -1 -De 15 0 8 0 0 -Po 0 55465 30043 55476 30054 39 -1 -De 15 0 8 0 0 -Po 3 55465 30043 55465 30043 157 -1 +Po 3 53219 29951 53219 29951 157 -1 De 15 1 8 0 0 -Po 0 55469 30039 55465 30043 39 -1 +Po 0 53317 30049 53219 29951 39 -1 +De 15 0 8 0 0 +Po 0 53219 29921 53219 29951 39 -1 De 0 0 8 0 0 -Po 0 55469 29981 55469 30039 39 -1 +Po 0 52973 29675 53219 29921 39 -1 De 0 0 8 0 0 -Po 0 54530 29042 55469 29981 39 -1 +Po 0 47413 26960 47062 26960 39 -1 +De 15 0 8 0 400 +Po 0 47805 27352 47413 26960 39 -1 +De 15 0 8 0 0 +Po 3 47805 27352 47805 27352 157 -1 +De 15 1 8 0 0 +Po 0 47815 27362 47805 27352 39 -1 De 0 0 8 0 0 -Po 0 52566 29042 54530 29042 39 -1 +Po 0 47815 27382 47815 27362 39 -1 De 0 0 8 0 0 -Po 0 52087 28563 52566 29042 39 -1 +Po 0 49134 28701 47815 27382 39 -1 De 0 0 8 0 0 -Po 0 52254 27677 52254 28545 39 -1 -De 0 0 9 0 0 -Po 0 49757 24738 49950 24931 39 -1 +Po 0 49991 28701 49134 28701 39 -1 +De 0 0 8 0 0 +Po 0 50955 29665 50965 29675 39 -1 +De 0 0 8 0 0 +Po 0 50965 29675 49991 28701 39 -1 +De 0 0 8 0 0 +Po 0 55291 30075 55291 30240 39 -1 De 15 0 9 0 0 -Po 0 49950 24931 50473 24931 39 -1 -De 15 0 9 0 0 -Po 0 50473 24931 50684 25142 39 -1 -De 15 0 9 0 0 -Po 0 50684 25142 50684 25506 39 -1 -De 15 0 9 0 0 -Po 0 50684 25506 52254 27076 39 -1 -De 15 0 9 0 0 -Po 0 52254 27076 52254 27677 39 -1 -De 15 0 9 0 0 -Po 3 52254 27677 52254 27677 157 -1 -De 15 1 9 0 0 -Po 0 49757 24659 49757 24738 39 -1 -De 15 0 9 0 800 -Po 0 55679 29896 55679 30245 39 -1 +Po 0 55291 30240 55286 30245 39 -1 De 15 0 9 0 400 -Po 0 55661 29878 55679 29896 39 -1 +Po 0 55286 30245 55285 30245 39 -1 +De 15 0 9 0 800 +Po 0 51919 27677 51919 28655 39 -1 +De 0 0 9 0 0 +Po 0 50594 25781 51919 27106 39 -1 De 15 0 9 0 0 -Po 3 55661 29878 55661 29878 157 -1 +Po 0 51919 27106 51919 27677 39 -1 +De 15 0 9 0 0 +Po 3 51919 27677 51919 27677 157 -1 De 15 1 9 0 0 -Po 0 55661 29854 55661 29878 39 -1 +Po 0 50288 25781 50594 25781 39 -1 +De 15 0 9 0 800 +Po 0 55291 30035 55291 30075 39 -1 +De 15 0 9 0 0 +Po 0 55291 30075 55291 30079 39 -1 +De 15 0 9 0 0 +Po 0 55205 29949 55291 30035 39 -1 +De 15 0 9 0 0 +Po 3 55205 29949 55205 29949 157 -1 +De 15 1 9 0 0 +Po 0 55205 29945 55205 29949 39 -1 De 0 0 9 0 0 -Po 0 54740 28933 55661 29854 39 -1 +Po 0 54929 29669 55205 29945 39 -1 De 0 0 9 0 0 -Po 0 52642 28933 54740 28933 39 -1 +Po 0 54756 29669 54929 29669 39 -1 De 0 0 9 0 0 -Po 0 52254 28545 52642 28933 39 -1 +Po 0 54230 29143 54756 29669 39 -1 De 0 0 9 0 0 -Po 0 49855 24130 49846 24130 79 -1 -De 0 0 10 0 800 -Po 0 49846 24130 49764 24212 79 -1 +Po 0 52407 29143 54230 29143 39 -1 +De 0 0 9 0 0 +Po 0 51919 28655 52407 29143 39 -1 +De 0 0 9 0 0 +Po 0 52254 27677 52254 28545 39 -1 De 0 0 10 0 0 -Po 0 49560 24659 49560 24421 79 -1 -De 15 0 10 0 800 -Po 0 49764 24212 49764 24209 79 -1 -De 0 0 10 0 0 -Po 0 49657 24319 49764 24212 79 -1 -De 0 0 10 0 0 -Po 3 49657 24319 49657 24319 157 -1 +Po 0 49757 24738 49950 24931 39 -1 +De 15 0 10 0 0 +Po 0 49950 24931 50473 24931 39 -1 +De 15 0 10 0 0 +Po 0 50473 24931 50684 25142 39 -1 +De 15 0 10 0 0 +Po 0 50684 25142 50684 25506 39 -1 +De 15 0 10 0 0 +Po 0 50684 25506 52254 27076 39 -1 +De 15 0 10 0 0 +Po 0 52254 27076 52254 27677 39 -1 +De 15 0 10 0 0 +Po 3 52254 27677 52254 27677 157 -1 De 15 1 10 0 0 -Po 0 49657 24324 49657 24319 79 -1 +Po 0 49757 24659 49757 24738 39 -1 +De 15 0 10 0 800 +Po 0 55679 29896 55679 30245 39 -1 +De 15 0 10 0 400 +Po 0 55661 29878 55679 29896 39 -1 De 15 0 10 0 0 -Po 0 49560 24421 49657 24324 79 -1 -De 15 0 10 0 0 -Po 0 49363 24659 49363 24987 79 -1 +Po 3 55661 29878 55661 29878 157 -1 +De 15 1 10 0 0 +Po 0 55661 29854 55661 29878 39 -1 +De 0 0 10 0 0 +Po 0 54740 28933 55661 29854 39 -1 +De 0 0 10 0 0 +Po 0 52642 28933 54740 28933 39 -1 +De 0 0 10 0 0 +Po 0 52254 28545 52642 28933 39 -1 +De 0 0 10 0 0 +Po 0 49855 24130 49846 24130 79 -1 +De 0 0 11 0 800 +Po 0 49846 24130 49764 24212 79 -1 +De 0 0 11 0 0 +Po 0 49560 24659 49560 24421 79 -1 De 15 0 11 0 800 -Po 0 49241 24143 49241 24124 79 -1 -De 0 0 11 0 400 -Po 0 49360 24262 49241 24143 79 -1 +Po 0 49764 24212 49764 24209 79 -1 De 0 0 11 0 0 -Po 0 49360 24970 49360 24262 79 -1 +Po 0 49657 24319 49764 24212 79 -1 De 0 0 11 0 0 -Po 3 49360 24970 49360 24970 157 -1 +Po 3 49657 24319 49657 24319 157 -1 De 15 1 11 0 0 -Po 0 49360 24984 49360 24970 79 -1 +Po 0 49657 24324 49657 24319 79 -1 De 15 0 11 0 0 -Po 0 49363 24987 49360 24984 79 -1 +Po 0 49560 24421 49657 24324 79 -1 De 15 0 11 0 0 -Po 0 47361 27878 47361 28070 39 -1 -De 0 0 12 0 800 -Po 0 47361 28070 47677 28386 39 -1 -De 0 0 12 0 0 -Po 0 47628 28337 47677 28386 39 -1 -De 0 0 12 0 0 -Po 0 54104 31426 54017 31339 39 -1 +Po 0 49363 24659 49363 24987 79 -1 De 15 0 12 0 800 -Po 0 51291 29550 53113 29550 39 -1 -De 3 0 12 0 0 -Po 0 47593 28302 47677 28386 39 -1 -De 15 0 12 0 0 -Po 3 47677 28386 47677 28386 157 -1 +Po 0 49241 24143 49241 24124 79 -1 +De 0 0 12 0 400 +Po 0 49360 24262 49241 24143 79 -1 +De 0 0 12 0 0 +Po 0 49360 24970 49360 24262 79 -1 +De 0 0 12 0 0 +Po 3 49360 24970 49360 24970 157 -1 De 15 1 12 0 0 -Po 0 47677 28386 48093 28802 39 -1 -De 3 0 12 0 0 -Po 0 48093 28802 50431 28802 39 -1 -De 3 0 12 0 0 -Po 0 50431 28802 51179 29550 39 -1 -De 3 0 12 0 0 -Po 0 51179 29550 51291 29550 39 -1 -De 3 0 12 0 0 -Po 0 47593 28302 47593 27885 39 -1 -De 15 0 12 0 400 -Po 3 53898 31220 53898 31220 157 -1 -De 15 1 12 0 0 -Po 0 53720 31042 53898 31220 39 -1 -De 3 0 12 0 0 -Po 0 53720 30157 53720 31042 39 -1 -De 3 0 12 0 0 -Po 0 53113 29550 53720 30157 39 -1 -De 3 0 12 0 0 -Po 0 53997 31319 53898 31220 39 -1 +Po 0 49360 24984 49360 24970 79 -1 De 15 0 12 0 0 -Po 0 54017 31339 53997 31319 39 -1 +Po 0 49363 24987 49360 24984 79 -1 De 15 0 12 0 0 Po 0 47515 26665 47515 27059 118 -1 De 0 0 13 0 C00 @@ -15426,580 +16488,606 @@ Po 0 49803 28650 49806 28650 39 -1 De 15 0 14 0 0 Po 0 48577 28348 48879 28650 39 -1 De 15 0 14 0 0 -Po 0 54055 30039 54075 30059 39 -1 +Po 0 53524 30315 53642 30433 39 -1 De 15 0 15 0 0 -Po 0 51052 29248 51082 29278 39 -1 +Po 0 53150 29606 53524 29980 39 -1 De 15 0 15 0 0 -Po 0 51082 29278 53293 29278 39 -1 +Po 0 53524 29980 53524 30315 39 -1 De 15 0 15 0 0 -Po 0 53293 29278 54054 30039 39 -1 +Po 0 50984 29606 50865 29487 39 -1 De 15 0 15 0 0 -Po 0 54054 30039 54055 30039 39 -1 -De 15 0 15 0 0 -Po 0 50610 28806 51052 29248 39 -1 -De 15 0 15 0 0 -Po 0 54104 30089 54104 30245 39 -1 -De 15 0 15 0 400 -Po 0 54075 30060 54104 30089 39 -1 -De 15 0 15 0 0 -Po 0 54075 30059 54075 30060 39 -1 -De 15 0 15 0 0 -Po 0 49166 27885 49166 28199 39 -1 +Po 0 48184 27885 48184 28239 39 -1 De 15 0 15 0 800 -Po 0 50347 28543 50610 28806 39 -1 +Po 0 50230 28852 50481 29103 39 -1 De 15 0 15 0 0 -Po 0 50610 28806 50601 28797 39 -1 +Po 0 48797 28852 50230 28852 39 -1 De 15 0 15 0 0 -Po 0 49510 28543 50347 28543 39 -1 +Po 0 48184 28239 48797 28852 39 -1 De 15 0 15 0 0 -Po 0 49166 28199 49510 28543 39 -1 +Po 0 50865 29487 50481 29103 39 -1 De 15 0 15 0 0 -Po 0 54774 30531 54774 30532 39 -1 +Po 0 50984 29606 53150 29606 39 -1 +De 15 0 15 0 0 +Po 0 53878 30806 54104 31032 39 -1 +De 15 0 15 0 400 +Po 0 53878 30571 53878 30806 39 -1 +De 15 0 15 0 0 +Po 0 53740 30433 53878 30571 39 -1 +De 15 0 15 0 0 +Po 0 53642 30433 53740 30433 39 -1 +De 15 0 15 0 0 +Po 0 53110 30728 53110 30748 39 -1 De 15 0 16 0 0 -Po 0 49560 27885 49560 28142 39 -1 -De 15 0 16 0 800 -Po 0 54685 30442 54774 30531 39 -1 +Po 0 53110 30748 53208 30846 39 -1 De 15 0 16 0 0 -Po 0 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0 Po 0 53169 39330 53311 39472 79 -1 -De 0 0 307 0 400 +De 0 0 329 0 400 Po 0 53124 38800 53124 38990 79 -1 -De 0 0 307 0 800 +De 0 0 329 0 800 Po 0 53124 38990 53169 39035 79 -1 -De 0 0 307 0 0 +De 0 0 329 0 0 Po 0 53270 39136 53270 39580 79 -1 -De 15 0 307 0 400 +De 15 0 329 0 400 Po 0 53169 39035 53270 39136 79 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 3 53169 39035 53169 39035 157 -1 -De 15 1 307 0 0 +De 15 1 329 0 0 Po 0 59566 39482 59915 39482 39 -1 -De 15 0 307 0 800 +De 15 0 329 0 800 Po 0 59915 39482 59925 39492 39 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 0 60075 40850 59961 40736 39 -1 -De 2 0 307 0 0 +De 2 0 329 0 0 Po 3 59961 40736 59961 40736 157 -1 -De 15 1 307 0 0 +De 15 1 329 0 0 Po 0 59961 40736 59925 40700 39 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 0 59925 40700 59925 39492 39 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 0 60075 40855 60075 40850 39 -1 -De 2 0 307 0 0 +De 2 0 329 0 0 Po 0 60236 38650 60236 38673 39 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 0 59925 39492 59925 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0 800 Po 3 57756 37941 57756 37941 157 -1 -De 15 1 307 0 0 +De 15 1 329 0 0 Po 0 57646 38051 57756 37941 39 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 0 56300 38324 55903 38324 39 -1 -De 0 0 307 0 800 +De 0 0 329 0 800 Po 0 56068 38117 55882 38303 79 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 3 55882 38303 55882 38303 157 -1 -De 15 1 307 0 0 +De 15 1 329 0 0 Po 0 56068 38117 56073 38117 79 -1 -De 15 0 307 0 400 +De 15 0 329 0 400 Po 0 55903 38324 55882 38303 39 -1 -De 0 0 307 0 0 +De 0 0 329 0 0 Po 0 59221 38122 59221 38117 39 -1 -De 15 0 307 0 400 +De 15 0 329 0 400 Po 0 57646 38117 57657 38117 39 -1 -De 15 0 307 0 800 +De 15 0 329 0 800 Po 0 52923 38117 52923 38093 79 -1 -De 15 0 307 0 800 +De 15 0 329 0 800 Po 0 52923 38117 52926 38117 79 -1 -De 15 0 307 0 800 +De 15 0 329 0 800 Po 0 56300 37226 56300 37092 79 -1 -De 0 0 307 0 800 +De 0 0 329 0 800 Po 0 56454 36936 56465 36936 79 -1 -De 15 0 307 0 400 +De 15 0 329 0 400 Po 0 56299 37091 56454 36936 79 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 3 56299 37091 56299 37091 157 -1 -De 15 1 307 0 0 +De 15 1 329 0 0 Po 0 56300 37092 56299 37091 79 -1 -De 0 0 307 0 0 +De 0 0 329 0 0 Po 0 56487 36936 56465 36936 79 -1 -De 15 0 307 0 400 +De 15 0 329 0 400 Po 0 54892 36936 54887 36936 79 -1 -De 15 0 307 0 800 +De 15 0 329 0 800 Po 3 54713 37110 54713 37110 157 -1 -De 15 1 307 0 0 +De 15 1 329 0 0 Po 0 54887 36936 54713 37110 79 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 0 52906 38117 52923 38117 79 -1 -De 15 0 307 0 400 +De 15 0 329 0 400 Po 0 54498 38117 54493 38117 79 -1 -De 15 0 307 0 800 +De 15 0 329 0 800 Po 3 54323 38287 54323 38287 157 -1 -De 15 1 307 0 0 +De 15 1 329 0 0 Po 0 54493 38117 54323 38287 79 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 0 53711 37330 53705 37330 79 -1 -De 15 0 307 0 800 +De 15 0 329 0 800 Po 3 53543 37492 53543 37492 157 -1 -De 15 1 307 0 0 +De 15 1 329 0 0 Po 0 53705 37330 53543 37492 79 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 Po 0 58040 36936 58046 36936 79 -1 -De 15 0 307 0 800 +De 15 0 329 0 800 Po 3 58236 37126 58236 37126 157 -1 -De 15 1 307 0 0 +De 15 1 329 0 0 Po 0 58046 36936 58236 37126 79 -1 -De 15 0 307 0 0 +De 15 0 329 0 0 $EndTRACK $ZONE $EndZONE @@ -23573,7 +24635,7 @@ ZLayer 4 ZAux 47 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 57465 32756 0 ZCorner 57465 32441 0 ZCorner 57807 32441 0 @@ -26393,7 +27455,7 @@ ZLayer 4 ZAux 61 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 50610 40110 0 ZCorner 51756 37996 0 ZCorner 51843 37949 0 @@ -32369,7 +33431,7 @@ ZLayer 1 ZAux 16 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 66094 41240 0 ZCorner 66339 30043 0 ZCorner 66339 29488 0 @@ -41427,7 +42489,7 @@ ZLayer 2 ZAux 9 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 58146 36236 0 ZCorner 58146 33566 0 ZCorner 63350 28362 0 @@ -42695,12 +43757,12 @@ $POLYSCORNERS $endPOLYSCORNERS $endCZONE_OUTLINE $CZONE_OUTLINE -ZInfo 4C75FAF2 307 "VCCO2" +ZInfo 4C75FAF2 329 "VCCO2" ZLayer 4 ZAux 31 F ZClearance 59 T ZMinThickness 59 -ZOptions 1 16 F 79 79 +ZOptions 1 16 S 79 79 ZCorner 65760 42028 0 ZCorner 63937 40205 0 ZCorner 60787 40205 0 @@ -43836,7 +44898,7 @@ ZLayer 15 ZAux 6 E ZClearance 98 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 65205 16941 0 ZCorner 65205 13362 0 ZCorner 58594 13362 0 @@ -44448,7 +45510,7 @@ ZLayer 15 ZAux 12 E ZClearance 98 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 58630 21457 0 ZCorner 58630 18008 0 ZCorner 59331 17307 0 @@ -45264,7 +46326,7 @@ ZLayer 0 ZAux 12 E ZClearance 98 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 58634 21461 0 ZCorner 58634 18012 0 ZCorner 59331 17315 0 @@ -45992,7 +47054,7 @@ ZLayer 0 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 54925 19335 0 ZCorner 54925 18299 0 ZCorner 53984 17358 0 @@ -46465,7 +47527,7 @@ ZLayer 15 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 46189 19343 0 ZCorner 54929 19335 0 ZCorner 54929 18299 0 @@ -46970,7 +48032,7 @@ ZLayer 1 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 46185 19339 0 ZCorner 54929 19335 0 ZCorner 54929 18303 0 @@ -47425,7 +48487,7 @@ ZLayer 4 ZAux 9 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 54925 19339 0 ZCorner 54925 18299 0 ZCorner 53984 17358 0 @@ -47881,7 +48943,7 @@ ZLayer 2 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 54929 19335 0 ZCorner 54929 18295 0 ZCorner 53988 17354 0 @@ -48336,7 +49398,7 @@ ZLayer 3 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 46185 19339 0 ZCorner 54929 19335 0 ZCorner 54929 18291 0 diff --git a/xue-rnc/xue-rnc.cmp b/xue-rnc/xue-rnc.cmp index 4d1b72f..030b01f 100644 --- a/xue-rnc/xue-rnc.cmp +++ b/xue-rnc/xue-rnc.cmp @@ -1,4 +1,4 @@ -Cmp-Mod V01 Created by CvPCB (2010-10-01 BZR 2513)-testing date = Thu 23 Dec 2010 05:28:43 PM COT +Cmp-Mod V01 Created by CvPCB (2010-10-01 BZR 2513)-testing date = Sun 26 Dec 2010 07:06:32 PM COT BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; @@ -581,6 +581,139 @@ ValeurCmp = 10nF; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4D13F1A3; +Reference = C157; +ValeurCmp = CAP; +IdModule = 1210; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D140643; +Reference = C158; +ValeurCmp = 22uF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FEB6; +Reference = C159; +ValeurCmp = 22uF; +IdModule = 1210; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D14016D; +Reference = C160; +ValeurCmp = 4.7uF; +IdModule = 0603; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13F557; +Reference = C161; +ValeurCmp = CAP; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FE2C; +Reference = C162; +ValeurCmp = 560pF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FCCF; +Reference = C163; +ValeurCmp = CAP; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D140659; +Reference = C164; +ValeurCmp = 39pF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D1408E4; +Reference = C165; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FBBF; +Reference = C166; +ValeurCmp = CAP; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D140163; +Reference = C167; +ValeurCmp = 10uF; +IdModule = 0805; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FF30; +Reference = C168; +ValeurCmp = CAP; +IdModule = 1210; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D140162; +Reference = C169; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D14063A; +Reference = C170; +ValeurCmp = 68uF; +IdModule = 1210; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FF2F; +Reference = C171; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FB8D; +Reference = C172; +ValeurCmp = 22uF; +IdModule = 1210; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D14063B; +Reference = C173; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FEFF; +Reference = C174; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D160B09; +Reference = D1; +ValeurCmp = MBRS140T3; +IdModule = 0805; +EndCmp + BeginCmp TimeStamp = /4C5F1EDC/4C5F2B55; Reference = F1; @@ -658,6 +791,34 @@ ValeurCmp = FB; IdModule = 0603; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4D1405EB; +Reference = L8; +ValeurCmp = 6.8uH; +IdModule = 1210; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D140153; +Reference = L9; +ValeurCmp = 2.2uF; +IdModule = 0805; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13F22A; +Reference = L10; +ValeurCmp = INDUCTOR; +IdModule = 1210; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FB89; +Reference = L11; +ValeurCmp = 2.2uH; +IdModule = 1210; +EndCmp + BeginCmp TimeStamp = /4CB0D95D/4CBAFE50; Reference = P1; @@ -973,6 +1134,83 @@ ValeurCmp = 33; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4D13F539; +Reference = R87; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FE0D; +Reference = R88; +ValeurCmp = 12k; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D140604; +Reference = R89; +ValeurCmp = 50k_1%; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FD6A; +Reference = R90; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FB88; +Reference = R91; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D140650; +Reference = R92; +ValeurCmp = 150k_1%; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13FC4E; +Reference = R93; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D140603; +Reference = R94; +ValeurCmp = 200k; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13F52F; +Reference = R95; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D13F523; +Reference = R96; +ValeurCmp = R; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C69ED5F/4D140674; +Reference = R97; +ValeurCmp = 500; +IdModule = 0402; +EndCmp + BeginCmp TimeStamp = /4C7BC2A2/4C69C6B2; Reference = RP1; diff --git a/xue-rnc/xue-rnc.net b/xue-rnc/xue-rnc.net index a05e673..44679f2 100644 --- a/xue-rnc/xue-rnc.net +++ b/xue-rnc/xue-rnc.net @@ -1,54 +1,190 @@ -# EESchema Netlist Version 1.1 created Thu 23 Dec 2010 05:38:09 PM COT +# EESchema Netlist Version 1.1 created Sun 26 Dec 2010 07:07:08 PM COT ( - ( /4C69ED5F/4D13C8E1 UDFN6 U10 NCP1529 {Lib=NCP1529} + ( /4C69ED5F/4D160B09 0805 D1 MBRS140T3 {Lib=DIODESCH} + ( 1 N-000190 ) + ( 2 N-000172 ) + ) + ( /4C69ED5F/4D1408E4 0402 C165 100nF {Lib=CAP} + ( 1 N-000171 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D140674 0402 R97 500 {Lib=R} + ( 1 N-000171 ) + ( 2 N-000172 ) + ) + ( /4C69ED5F/4D140659 0402 C164 39pF {Lib=CAP} + ( 1 N-000172 ) + ( 2 N-000189 ) + ) + ( /4C69ED5F/4D140650 0402 R92 150k_1% {Lib=R} + ( 1 N-000189 ) + ( 2 N-000172 ) + ) + ( /4C69ED5F/4D140643 0402 C158 22uF {Lib=CAP} + ( 1 N-000167 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D14063B 0402 C173 100nF {Lib=CAP} + ( 1 N-000172 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D14063A 1210 C170 68uF {Lib=CAP} + ( 1 N-000172 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D140604 0402 R89 50k_1% {Lib=R} + ( 1 GND ) + ( 2 N-000189 ) + ) + ( /4C69ED5F/4D140603 0402 R94 200k {Lib=R} + ( 1 N-000188 ) + ( 2 N-000171 ) + ) + ( /4C69ED5F/4D1405EB 1210 L8 6.8uH {Lib=INDUCTOR} + ( 1 N-000190 ) + ( 2 N-000167 ) + ) + ( /4C69ED5F/4D140153 0805 L9 2.2uF {Lib=INDUCTOR} + ( 1 N-000182 ) + ( 2 N-000166 ) + ) + ( /4C69ED5F/4D14016D 0603 C160 4.7uF {Lib=CAP} ( 1 ? ) - ( 2 ? ) + ( 2 GND ) + ) + ( /4C69ED5F/4D140163 0805 C167 10uF {Lib=CAP} + ( 1 N-000182 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D140162 0402 C169 100nF {Lib=CAP} + ( 1 N-000182 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D13FF30 1210 C168 CAP {Lib=CAP} + ( 1 N-000183 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D13FF2F 0402 C171 100nF {Lib=CAP} + ( 1 N-000183 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D13FEFF 0402 C174 100nF {Lib=CAP} + ( 1 N-000174 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D13FEB6 1210 C159 22uF {Lib=CAP} + ( 1 ? ) + ( 2 GND ) + ) + ( /4C69ED5F/4D13FE2C 0402 C162 560pF {Lib=CAP} + ( 1 N-000170 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D13FE0D 0402 R88 12k {Lib=R} + ( 1 N-000170 ) + ( 2 N-000177 ) + ) + ( /4C69ED5F/4D13FD6A 0402 R90 R {Lib=R} + ( 1 GND ) + ( 2 N-000169 ) + ) + ( /4C69ED5F/4D13FCCF 0402 C163 CAP {Lib=CAP} + ( 1 GND ) + ( 2 N-000160 ) + ) + ( /4C69ED5F/4D13FC4E 0402 R93 R {Lib=R} + ( 1 N-000160 ) + ( 2 N-000179 ) + ) + ( /4C69ED5F/4D13FBBF 0402 C166 CAP {Lib=CAP} + ( 1 N-000161 ) + ( 2 N-000168 ) + ) + ( /4C69ED5F/4D13FB8D 1210 C172 22uF {Lib=CAP} + ( 1 N-000174 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D13FB89 1210 L11 2.2uH {Lib=INDUCTOR} + ( 1 N-000174 ) + ( 2 N-000168 ) + ) + ( /4C69ED5F/4D13FB88 0402 R91 R {Lib=R} + ( 1 N-000174 ) + ( 2 N-000169 ) + ) + ( /4C69ED5F/4D13F557 0402 C161 CAP {Lib=CAP} + ( 1 N-000163 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D13F539 0402 R87 R {Lib=R} + ( 1 N-000157 ) + ( 2 N-000163 ) + ) + ( /4C69ED5F/4D13F52F 0402 R95 R {Lib=R} + ( 1 N-000158 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D13F523 0402 R96 R {Lib=R} + ( 1 N-000183 ) + ( 2 N-000158 ) + ) + ( /4C69ED5F/4D13F22A 1210 L10 INDUCTOR {Lib=INDUCTOR} + ( 1 N-000183 ) + ( 2 N-000164 ) + ) + ( /4C69ED5F/4D13F1A3 1210 C157 CAP {Lib=CAP} + ( 1 ? ) + ( 2 GND ) + ) + ( /4C69ED5F/4D13C8E1 UDFN6 U10 NCP1529 {Lib=NCP1529} + ( 1 N-000182 ) + ( 2 GND ) ( 3 ? ) - ( 4 ? ) - ( 5 ? ) + ( 4 GND ) + ( 5 N-000166 ) ( 6 ? ) ) ( /4C69ED5F/4D13C8D9 MINI-SO-8 U9 LM2621 {Lib=LM2621} - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) - ( 7 ? ) - ( 8 ? ) + ( 1 GND ) + ( 2 N-000171 ) + ( 3 N-000188 ) + ( 4 N-000189 ) + ( 5 GND ) + ( 6 N-000171 ) + ( 7 N-000172 ) + ( 8 N-000190 ) ) ( /4C69ED5F/4D13C8D1 MLF20m1 U12 BD9132MUV {Lib=BD9132MUV} - ( 1 N-000178 ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) - ( 7 ? ) - ( 8 ? ) - ( 9 ? ) - ( 10 ? ) - ( 11 ? ) - ( 12 ? ) - ( 13 ? ) + ( 1 N-000168 ) + ( 2 N-000168 ) + ( 3 N-000168 ) + ( 4 N-000168 ) + ( 5 N-000168 ) + ( 6 N-000179 ) + ( 7 N-000179 ) + ( 8 N-000179 ) + ( 9 N-000161 ) + ( 10 N-000160 ) + ( 11 N-000178 ) + ( 12 N-000169 ) + ( 13 N-000177 ) ( 14 ? ) ( 15 ? ) ( 16 ? ) ( 17 ? ) - ( 18 ? ) - ( 19 ? ) - ( 20 ? ) + ( 18 N-000178 ) + ( 19 N-000178 ) + ( 20 N-000178 ) ( PAD ? ) ) ( /4C69ED5F/4D13C8C9 SON008V5060 U11 BD9130NV {Lib=BD9130NV} - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 ? ) - ( 7 ? ) + ( 1 N-000158 ) + ( 2 N-000165 ) + ( 3 N-000157 ) + ( 4 GND ) + ( 5 GND ) + ( 6 N-000164 ) + ( 7 N-000165 ) ( 8 ? ) ) ( /4C7BC2B2/4CD34D8C 0402 C156 10nF {Lib=C} @@ -83,11 +219,11 @@ ) ( /4C7BC2B2/4C7168DD 0402 R30 330 {Lib=R} ( 1 +3.3V ) - ( 2 N-000359 ) + ( 2 N-000350 ) ) ( /4C7BC2B2/4C716877 0402 R29 4.7k {Lib=R} ( 1 +3.3V ) - ( 2 N-000356 ) + ( 2 N-000347 ) ) ( /4C7BC2B2/4C6B29DA 0402 C77 470nF {Lib=C} ( 1 +2.5V ) @@ -225,26 +361,26 @@ ( A1 GND ) ( A2 ? ) ( A3 GND ) - ( A4 /fpga1/ETH_CLK ) + ( A4 /ether/ETH_CLK ) ( A5 /fpga1/ETH_RXD1 ) - ( A6 /ether/ETH_RXDV ) + ( A6 /fpga1/ETH_RXDV ) ( A7 /fpga1/ETH_RXC ) - ( A8 /fpga1/ETH_TXD3 ) - ( A9 /fpga1/ETH_COL ) + ( A8 /ether/ETH_TXD3 ) + ( A9 /ether/ETH_COL ) ( A10 /ether/ETH_INT ) ( A11 /fpga1/NF_D6 ) - ( A12 /flash/NF_D4 ) - ( A13 /flash/NF_D2 ) + ( A12 /fpga1/NF_D4 ) + ( A13 /fpga1/NF_D2 ) ( A14 /fpga1/NF_ALE ) - ( A15 /fpga1/NF_RNB ) + ( A15 /flash/NF_RNB ) ( A16 /flash/SD_DAT2 ) ( A17 /fpga1/SD_CLK ) - ( A18 /fpga1/SD_DAT0 ) + ( A18 /flash/SD_DAT0 ) ( A19 ? ) ( A20 /fpga2/USBD_RCV ) - ( A21 /usb/USBD_OE_N ) + ( A21 /fpga2/USBD_OE_N ) ( A22 GND ) - ( AA1 N-000356 ) + ( AA1 N-000347 ) ( AA2 ? ) ( AA3 VCCO2 ) ( AA4 ? ) @@ -259,9 +395,9 @@ ( AA13 GND ) ( AA14 /fpga1/FPGA_BANK0_IO_22 ) ( AA15 VCCO2 ) - ( AA16 /fpga1/FPGA_BANK0_IO_28 ) + ( AA16 /expansion/FPGA_BANK0_IO_28 ) ( AA17 GND ) - ( AA18 /fpga1/FPGA_BANK0_IO_18 ) + ( AA18 /expansion/FPGA_BANK0_IO_18 ) ( AA19 VCCO2 ) ( AA20 /fpga1/PROG_MISO1 ) ( AA21 /fpga1/PROG_CCLK ) @@ -281,7 +417,7 @@ ( AB13 /expansion/FPGA_BANK0_IO_39 ) ( AB14 ? ) ( AB15 /fpga1/FPGA_BANK0_IO_33 ) - ( AB16 /expansion/FPGA_BANK0_IO_29 ) + ( AB16 /fpga1/FPGA_BANK0_IO_29 ) ( AB17 /expansion/FPGA_BANK0_IO_21 ) ( AB18 ? ) ( AB19 ? ) @@ -295,36 +431,36 @@ ( B5 GND ) ( B6 /ether/ETH_RXD0 ) ( B7 +3.3V ) - ( B8 /ether/ETH_RXER ) + ( B8 /fpga1/ETH_RXER ) ( B9 GND ) - ( B10 /ether/ETH_CRS ) + ( B10 /fpga1/ETH_CRS ) ( B11 +3.3V ) - ( B12 /fpga1/NF_D3 ) + ( B12 /flash/NF_D3 ) ( B13 GND ) - ( B14 /flash/NF_CLE ) + ( B14 /fpga1/NF_CLE ) ( B15 +3.3V ) - ( B16 /flash/SD_DAT3 ) + ( B16 /fpga1/SD_DAT3 ) ( B17 GND ) - ( B18 /flash/SD_DAT1 ) + ( B18 /fpga1/SD_DAT1 ) ( B19 +3.3V ) - ( B20 /usb/USBD_SPD ) + ( B20 /fpga2/USBD_SPD ) ( B21 /usb/USBD_VP ) ( B22 /usb/USBD_VM ) ( C1 /fpga2/R_M0_A11 ) ( C2 +2.5V ) ( C3 ? ) ( C4 ? ) - ( C5 /fpga1/ETH_RXD3 ) - ( C6 /fpga1/ETH_RXD2 ) + ( C5 /ether/ETH_RXD3 ) + ( C6 /ether/ETH_RXD2 ) ( C7 /fpga1/ETH_RESET_N ) - ( C8 /fpga1/ETH_TXC ) + ( C8 /ether/ETH_TXC ) ( C9 /fpga1/ETH_TXD1 ) - ( C10 /fpga1/ETH_TXD2 ) + ( C10 /ether/ETH_TXD2 ) ( C11 /flash/NF_D5 ) ( C12 /fpga1/NF_D0 ) ( C13 ? ) ( C14 /flash/NF_WE_N ) - ( C15 /flash/NF_RE_N ) + ( C15 /fpga1/NF_RE_N ) ( C16 /flash/SD_CMD ) ( C17 ? ) ( C18 ? ) @@ -337,11 +473,11 @@ ( D3 ? ) ( D4 GND ) ( D5 ? ) - ( D6 /ether/ETH_MDIO ) + ( D6 /fpga1/ETH_MDIO ) ( D7 /fpga1/ETH_MDC ) ( D8 /ether/ETH_TXER ) ( D9 /fpga1/ETH_TXEN ) - ( D10 /fpga1/ETH_TXD0 ) + ( D10 /ether/ETH_TXD0 ) ( D11 /fpga1/NF_D7 ) ( D12 ? ) ( D13 ? ) @@ -351,7 +487,7 @@ ( D17 ? ) ( D18 GND ) ( D19 /fpga2/USBA_VP ) - ( D20 /fpga2/USBA_VM ) + ( D20 /usb/USBA_VM ) ( D21 /fpga2/R_M1_CKE ) ( D22 /fpga2/R_M1_A12 ) ( E1 /fpga2/R_M0_A9 ) @@ -422,8 +558,8 @@ ( G22 ? ) ( H1 /fpga2/R_M0_A1 ) ( H2 /fpga2/R_M0_A0 ) - ( H3 /sdram/M0_CLK# ) - ( H4 /fpga2/M0_CLK ) + ( H3 /fpga2/M0_CLK# ) + ( H4 /sdram/M0_CLK ) ( H5 /fpga2/R_M0_A2 ) ( H6 /fpga2/R_M0_A7 ) ( H7 GND ) @@ -439,7 +575,7 @@ ( H17 ? ) ( H18 ? ) ( H19 /fpga2/R_M1_WE# ) - ( H20 /sdram/M1_CLK ) + ( H20 /fpga2/M1_CLK ) ( H21 /fpga2/R_M1_RAS# ) ( H22 /fpga2/R_M1_CAS# ) ( J1 /fpga2/R_M0_DQ5 ) @@ -460,7 +596,7 @@ ( J16 ? ) ( J17 /fpga2/R_M1_BA0 ) ( J18 +2.5V ) - ( J19 /sdram/M1_CLK# ) + ( J19 /fpga2/M1_CLK# ) ( J20 /fpga2/R_M1_DQ4 ) ( J21 GND ) ( J22 /fpga2/R_M1_DQ5 ) @@ -602,12 +738,12 @@ ( T4 ? ) ( T5 /fpga1/PROG_CSO ) ( T6 ? ) - ( T7 /expansion/FPGA_BANK0_IO_60 ) + ( T7 /fpga1/FPGA_BANK0_IO_60 ) ( T8 /expansion/FPGA_BANK0_IO_53 ) ( T9 VCCO2 ) ( T10 ? ) ( T11 ? ) - ( T12 /expansion/FPGA_BANK0_IO_34 ) + ( T12 /fpga1/FPGA_BANK0_IO_34 ) ( T13 VCCO2 ) ( T14 /expansion/FPGA_BANK0_IO_36 ) ( T15 /fpga1/FPGA_BANK0_IO_7 ) @@ -627,14 +763,14 @@ ( U7 GND ) ( U8 /expansion/FPGA_BANK0_IO_54 ) ( U9 /fpga1/FPGA_BANK0_IO_51 ) - ( U10 /fpga1/FPGA_BANK0_IO_56 ) + ( U10 /expansion/FPGA_BANK0_IO_56 ) ( U11 +2.5V ) ( U12 ? ) ( U13 /fpga1/PROG_MISO3 ) ( U14 /fpga1/PROG_MISO2 ) ( U15 GND ) ( U16 /expansion/FPGA_BANK0_IO_9 ) - ( U17 /expansion/FPGA_BANK0_IO_8 ) + ( U17 /fpga1/FPGA_BANK0_IO_8 ) ( U18 +2.5V ) ( U19 ? ) ( U20 /fpga2/R_M1_DQ12 ) @@ -648,7 +784,7 @@ ( V6 +2.5V ) ( V7 /expansion/FPGA_BANK0_IO_49 ) ( V8 VCCO2 ) - ( V9 /fpga1/FPGA_BANK0_IO_52 ) + ( V9 /expansion/FPGA_BANK0_IO_52 ) ( V10 GND ) ( V11 /expansion/FPGA_BANK0_IO_43 ) ( V12 VCCO2 ) @@ -656,9 +792,9 @@ ( V14 GND ) ( V15 /expansion/FPGA_BANK0_IO_17 ) ( V16 VCCO2 ) - ( V17 /expansion/FPGA_BANK0_IO_14 ) + ( V17 /fpga1/FPGA_BANK0_IO_14 ) ( V18 /fpga1/FPGA_BANK0_IO_11 ) - ( V19 /expansion/FPGA_BANK0_IO_10 ) + ( V19 /fpga1/FPGA_BANK0_IO_10 ) ( V20 ? ) ( V21 /fpga2/R_M1_DQ14 ) ( V22 /fpga2/R_M1_DQ15 ) @@ -667,16 +803,16 @@ ( W3 ? ) ( W4 ? ) ( W5 VCCO2 ) - ( W6 /expansion/FPGA_BANK0_IO_57 ) + ( W6 /fpga1/FPGA_BANK0_IO_57 ) ( W7 GND ) ( W8 /fpga1/FPGA_BANK0_IO_48 ) - ( W9 /fpga1/FPGA_BANK0_IO_50 ) + ( W9 /expansion/FPGA_BANK0_IO_50 ) ( W10 /expansion/FPGA_BANK0_IO_46 ) ( W11 /fpga1/FPGA_BANK0_IO_44 ) ( W12 ? ) ( W13 /expansion/FPGA_BANK0_IO_27 ) - ( W14 /expansion/FPGA_BANK0_IO_30 ) - ( W15 /fpga1/FPGA_BANK0_IO_25 ) + ( W14 /fpga1/FPGA_BANK0_IO_30 ) + ( W15 /expansion/FPGA_BANK0_IO_25 ) ( W16 GND ) ( W17 /expansion/FPGA_BANK0_IO_15 ) ( W18 ? ) @@ -692,28 +828,28 @@ ( Y6 ? ) ( Y7 ? ) ( Y8 ? ) - ( Y9 /expansion/FPGA_BANK0_IO_45 ) - ( Y10 /expansion/FPGA_BANK0_IO_47 ) + ( Y9 /fpga1/FPGA_BANK0_IO_45 ) + ( Y10 /fpga1/FPGA_BANK0_IO_47 ) ( Y11 /fpga1/FPGA_BANK0_IO_40 ) ( Y12 ? ) ( Y13 /expansion/FPGA_BANK0_IO_38 ) ( Y14 ? ) ( Y15 /expansion/FPGA_BANK0_IO_32 ) - ( Y16 /expansion/FPGA_BANK0_IO_24 ) + ( Y16 /fpga1/FPGA_BANK0_IO_24 ) ( Y17 /fpga1/FPGA_BANK0_IO_20 ) ( Y18 /expansion/FPGA_BANK0_IO_5 ) - ( Y19 /expansion/FPGA_BANK0_IO_3 ) + ( Y19 /fpga1/FPGA_BANK0_IO_3 ) ( Y20 +3.3V ) ( Y21 ? ) - ( Y22 N-000359 ) + ( Y22 N-000350 ) ) ( /4C7BC2A2/4CCF27AA 0402 R81 33 {Lib=R} ( 1 /fpga2/R_M1_LDM ) - ( 2 /sdram/M1_LDM ) + ( 2 /fpga2/M1_LDM ) ) ( /4C7BC2A2/4CCF27A9 0402 R80 33 {Lib=R} ( 1 /fpga2/R_M1_WE# ) - ( 2 /fpga2/M1_WE# ) + ( 2 /sdram/M1_WE# ) ) ( /4C7BC2A2/4CCF27A8 0402 R82 33 {Lib=R} ( 1 /fpga2/R_M1_LDQS ) @@ -725,7 +861,7 @@ ) ( /4C7BC2A2/4CCF2733 0402 R83 33 {Lib=R} ( 1 /fpga2/R_M0_CAS# ) - ( 2 /sdram/M0_CAS# ) + ( 2 /fpga2/M0_CAS# ) ) ( /4C7BC2A2/4CCF2730 0402 R86 33 {Lib=R} ( 1 /fpga2/R_M0_LDQS ) @@ -733,15 +869,15 @@ ) ( /4C7BC2A2/4CCF272F 0402 R84 33 {Lib=R} ( 1 /fpga2/R_M0_WE# ) - ( 2 /sdram/M0_WE# ) + ( 2 /fpga2/M0_WE# ) ) ( /4C7BC2A2/4CCF272E 0402 R85 33 {Lib=R} ( 1 /fpga2/R_M0_LDM ) - ( 2 /sdram/M0_LDM ) + ( 2 /fpga2/M0_LDM ) ) ( /4C7BC2A2/4C6B216E 0402 R23 33 {Lib=R} ( 1 /fpga2/R_M0_UDM ) - ( 2 /fpga2/M0_UDM ) + ( 2 /sdram/M0_UDM ) ) ( /4C7BC2A2/4C6B216D 0402 R22 33 {Lib=R} ( 1 /fpga2/R_M0_UDQS ) @@ -749,11 +885,11 @@ ) ( /4C7BC2A2/4C6B216B 0402 R24 33 {Lib=R} ( 1 /fpga2/R_M0_CKE ) - ( 2 /fpga2/M0_CKE ) + ( 2 /sdram/M0_CKE ) ) ( /4C7BC2A2/4C6B1B90 0402 R21 120 {Lib=R} - ( 1 /fpga2/M0_CLK ) - ( 2 /sdram/M0_CLK# ) + ( 1 /sdram/M0_CLK ) + ( 2 /fpga2/M0_CLK# ) ) ( /4C7BC2A2/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4} ( 1 /fpga2/R_M0_A0 ) @@ -763,24 +899,24 @@ ( 5 /fpga2/M0_A3 ) ( 6 /fpga2/M0_A2 ) ( 7 /fpga2/M0_A1 ) - ( 8 /sdram/M0_A0 ) + ( 8 /fpga2/M0_A0 ) ) ( /4C7BC2A2/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4} ( 1 /fpga2/R_M0_RAS# ) ( 2 /fpga2/R_M0_BA0 ) ( 3 /fpga2/R_M0_BA1 ) ( 4 /fpga2/R_M0_A10 ) - ( 5 /fpga2/M0_A10 ) - ( 6 /fpga2/M0_BA1 ) + ( 5 /sdram/M0_A10 ) + ( 6 /sdram/M0_BA1 ) ( 7 /sdram/M0_BA0 ) - ( 8 /fpga2/M0_RAS# ) + ( 8 /sdram/M0_RAS# ) ) ( /4C7BC2A2/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4} ( 1 /fpga2/R_M0_A7 ) ( 2 /fpga2/R_M0_A6 ) ( 3 /fpga2/R_M0_A5 ) ( 4 /fpga2/R_M0_A4 ) - ( 5 /sdram/M0_A4 ) + ( 5 /fpga2/M0_A4 ) ( 6 /fpga2/M0_A5 ) ( 7 /fpga2/M0_A6 ) ( 8 /fpga2/M0_A7 ) @@ -790,19 +926,19 @@ ( 2 /fpga2/R_M0_A11 ) ( 3 /fpga2/R_M0_A9 ) ( 4 /fpga2/R_M0_A8 ) - ( 5 /fpga2/M0_A8 ) + ( 5 /sdram/M0_A8 ) ( 6 /fpga2/M0_A9 ) ( 7 /fpga2/M0_A11 ) - ( 8 /fpga2/M0_A12 ) + ( 8 /sdram/M0_A12 ) ) ( /4C7BC2A2/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4} ( 1 /fpga2/R_M0_DQ4 ) ( 2 /fpga2/R_M0_DQ5 ) ( 3 /fpga2/R_M0_DQ6 ) ( 4 /fpga2/R_M0_DQ7 ) - ( 5 /sdram/M0_DQ7 ) + ( 5 /fpga2/M0_DQ7 ) ( 6 /sdram/M0_DQ6 ) - ( 7 /sdram/M0_DQ5 ) + ( 7 /fpga2/M0_DQ5 ) ( 8 /sdram/M0_DQ4 ) ) ( /4C7BC2A2/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 {Lib=R_PACK4} @@ -811,8 +947,8 @@ ( 3 /fpga2/R_M0_DQ2 ) ( 4 /fpga2/R_M0_DQ3 ) ( 5 /fpga2/M0_DQ3 ) - ( 6 /fpga2/M0_DQ2 ) - ( 7 /sdram/M0_DQ1 ) + ( 6 /sdram/M0_DQ2 ) + ( 7 /fpga2/M0_DQ1 ) ( 8 /fpga2/M0_DQ0 ) ) ( /4C7BC2A2/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4} @@ -822,7 +958,7 @@ ( 4 /fpga2/R_M0_DQ11 ) ( 5 /fpga2/M0_DQ11 ) ( 6 /fpga2/M0_DQ10 ) - ( 7 /fpga2/M0_DQ9 ) + ( 7 /sdram/M0_DQ9 ) ( 8 /sdram/M0_DQ8 ) ) ( /4C7BC2A2/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4} @@ -830,31 +966,31 @@ ( 2 /fpga2/R_M0_DQ13 ) ( 3 /fpga2/R_M0_DQ14 ) ( 4 /fpga2/R_M0_DQ15 ) - ( 5 /sdram/M0_DQ15 ) + ( 5 /fpga2/M0_DQ15 ) ( 6 /fpga2/M0_DQ14 ) - ( 7 /sdram/M0_DQ13 ) + ( 7 /fpga2/M0_DQ13 ) ( 8 /fpga2/M0_DQ12 ) ) ( /4C7BC2A2/4C69E7DD 0402 R19 33 {Lib=R} ( 1 /fpga2/R_M1_UDQS ) - ( 2 /fpga2/M1_UDQS ) + ( 2 /sdram/M1_UDQS ) ) ( /4C7BC2A2/4C69E92D 0402 R20 33 {Lib=R} ( 1 /fpga2/R_M1_CS# ) - ( 2 /sdram/M1_CS# ) + ( 2 /fpga2/M1_CS# ) ) ( /4C7BC2A2/4C69E7F8 0402 R17 33 {Lib=R} ( 1 /fpga2/R_M1_CKE ) - ( 2 /fpga2/M1_CKE ) + ( 2 /sdram/M1_CKE ) ) ( /4C7BC2A2/4C69E7C2 0402 R18 33 {Lib=R} ( 1 /fpga2/R_M1_UDM ) - ( 2 /fpga2/M1_UDM ) + ( 2 /sdram/M1_UDM ) ) ( /4C7BC2A2/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4} ( 1 /sdram/M1_DQ11 ) ( 2 /fpga2/M1_DQ10 ) - ( 3 /sdram/M1_DQ9 ) + ( 3 /fpga2/M1_DQ9 ) ( 4 /fpga2/M1_DQ8 ) ( 5 /fpga2/R_M1_DQ8 ) ( 6 /fpga2/R_M1_DQ9 ) @@ -862,7 +998,7 @@ ( 8 /fpga2/R_M1_DQ11 ) ) ( /4C7BC2A2/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} - ( 1 /sdram/M1_DQ15 ) + ( 1 /fpga2/M1_DQ15 ) ( 2 /sdram/M1_DQ14 ) ( 3 /fpga2/M1_DQ13 ) ( 4 /fpga2/M1_DQ12 ) @@ -872,24 +1008,24 @@ ( 8 /fpga2/R_M1_DQ15 ) ) ( /4C7BC2A2/4C69DF7A 0402 R16 120 {Lib=R} - ( 1 /sdram/M1_CLK# ) - ( 2 /sdram/M1_CLK ) + ( 1 /fpga2/M1_CLK# ) + ( 2 /fpga2/M1_CLK ) ) ( /4C7BC2A2/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4} - ( 1 /sdram/M1_A12 ) + ( 1 /fpga2/M1_A12 ) ( 2 /sdram/M1_A11 ) - ( 3 /sdram/M1_A9 ) - ( 4 /sdram/M1_A8 ) + ( 3 /fpga2/M1_A9 ) + ( 4 /fpga2/M1_A8 ) ( 5 /fpga2/R_M1_A8 ) ( 6 /fpga2/R_M1_A9 ) ( 7 /fpga2/R_M1_A11 ) ( 8 /fpga2/R_M1_A12 ) ) ( /4C7BC2A2/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4} - ( 1 /sdram/M1_A7 ) - ( 2 /sdram/M1_A6 ) + ( 1 /fpga2/M1_A7 ) + ( 2 /fpga2/M1_A6 ) ( 3 /fpga2/M1_A5 ) - ( 4 /fpga2/M1_A4 ) + ( 4 /sdram/M1_A4 ) ( 5 /fpga2/R_M1_A4 ) ( 6 /fpga2/R_M1_A5 ) ( 7 /fpga2/R_M1_A6 ) @@ -900,20 +1036,20 @@ ( 2 /fpga2/R_M1_DQ1 ) ( 3 /fpga2/R_M1_DQ2 ) ( 4 /fpga2/R_M1_DQ3 ) - ( 5 /fpga2/M1_DQ3 ) - ( 6 /sdram/M1_DQ2 ) - ( 7 /sdram/M1_DQ1 ) - ( 8 /sdram/M1_DQ0 ) + ( 5 /sdram/M1_DQ3 ) + ( 6 /fpga2/M1_DQ2 ) + ( 7 /fpga2/M1_DQ1 ) + ( 8 /fpga2/M1_DQ0 ) ) ( /4C7BC2A2/4C69D3A3 $noname RP4 R_PACK4 {Lib=R_PACK4} ( 1 /fpga2/R_M1_DQ4 ) ( 2 /fpga2/R_M1_DQ5 ) ( 3 /fpga2/R_M1_DQ6 ) ( 4 /fpga2/R_M1_DQ7 ) - ( 5 /fpga2/M1_DQ7 ) - ( 6 /fpga2/M1_DQ6 ) + ( 5 /sdram/M1_DQ7 ) + ( 6 /sdram/M1_DQ6 ) ( 7 /fpga2/M1_DQ5 ) - ( 8 /fpga2/M1_DQ4 ) + ( 8 /sdram/M1_DQ4 ) ) ( /4C7BC2A2/4C69CEE8 $noname RP2 R_PACK4 {Lib=R_PACK4} ( 1 /fpga2/R_M1_RAS# ) @@ -921,16 +1057,16 @@ ( 3 /fpga2/R_M1_BA1 ) ( 4 /fpga2/R_M1_A10 ) ( 5 /sdram/M1_A10 ) - ( 6 /fpga2/M1_BA1 ) - ( 7 /fpga2/M1_BA0 ) - ( 8 /fpga2/M1_RAS# ) + ( 6 /sdram/M1_BA1 ) + ( 7 /sdram/M1_BA0 ) + ( 8 /sdram/M1_RAS# ) ) ( /4C7BC2A2/4C69C6B2 $noname RP1 R_PACK4 {Lib=R_PACK4} ( 1 /fpga2/R_M1_A0 ) ( 2 /fpga2/R_M1_A1 ) ( 3 /fpga2/R_M1_A2 ) ( 4 /fpga2/R_M1_A3 ) - ( 5 /fpga2/M1_A3 ) + ( 5 /sdram/M1_A3 ) ( 6 /fpga2/M1_A2 ) ( 7 /fpga2/M1_A1 ) ( 8 /fpga2/M1_A0 ) @@ -963,13 +1099,13 @@ ) ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} ( 1 /flash/SD_DAT2 ) - ( 2 /flash/SD_DAT3 ) + ( 2 /fpga1/SD_DAT3 ) ( 3 /flash/SD_CMD ) ( 4 +3.3V ) ( 5 /fpga1/SD_CLK ) ( 6 GND ) - ( 7 /fpga1/SD_DAT0 ) - ( 8 /flash/SD_DAT1 ) + ( 7 /flash/SD_DAT0 ) + ( 8 /fpga1/SD_DAT1 ) ( CASE GND ) ( CD ? ) ( COM GND ) @@ -980,9 +1116,9 @@ ( 3 ? ) ( 4 ? ) ( 5 ? ) - ( 6 /fpga1/NF_RNB ) - ( 7 /fpga1/NF_RNB ) - ( 8 /flash/NF_RE_N ) + ( 6 /flash/NF_RNB ) + ( 7 /flash/NF_RNB ) + ( 8 /fpga1/NF_RE_N ) ( 9 /fpga1/NF_CS1_N ) ( 10 ? ) ( 11 ? ) @@ -990,7 +1126,7 @@ ( 13 GND ) ( 14 ? ) ( 15 ? ) - ( 16 /flash/NF_CLE ) + ( 16 /fpga1/NF_CLE ) ( 17 /fpga1/NF_ALE ) ( 18 /flash/NF_WE_N ) ( 19 +3.3V ) @@ -1005,8 +1141,8 @@ ( 28 ? ) ( 29 /fpga1/NF_D0 ) ( 30 /fpga1/NF_D1 ) - ( 31 /flash/NF_D2 ) - ( 32 /fpga1/NF_D3 ) + ( 31 /fpga1/NF_D2 ) + ( 32 /flash/NF_D3 ) ( 33 ? ) ( 34 ? ) ( 35 ? ) @@ -1015,7 +1151,7 @@ ( 38 ? ) ( 39 ? ) ( 40 ? ) - ( 41 /flash/NF_D4 ) + ( 41 /fpga1/NF_D4 ) ( 42 /flash/NF_D5 ) ( 43 /fpga1/NF_D6 ) ( 44 /fpga1/NF_D7 ) @@ -1026,61 +1162,61 @@ ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /sdram/M1_DQ0 ) + ( 2 /fpga2/M1_DQ0 ) ( 3 +2.5V ) - ( 4 /sdram/M1_DQ1 ) - ( 5 /sdram/M1_DQ2 ) + ( 4 /fpga2/M1_DQ1 ) + ( 5 /fpga2/M1_DQ2 ) ( 6 GND ) - ( 7 /fpga2/M1_DQ3 ) - ( 8 /fpga2/M1_DQ4 ) + ( 7 /sdram/M1_DQ3 ) + ( 8 /sdram/M1_DQ4 ) ( 9 +2.5V ) ( 10 /fpga2/M1_DQ5 ) - ( 11 /fpga2/M1_DQ6 ) + ( 11 /sdram/M1_DQ6 ) ( 12 GND ) - ( 13 /fpga2/M1_DQ7 ) + ( 13 /sdram/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /fpga2/M1_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /sdram/M1_LDM ) - ( 21 /fpga2/M1_WE# ) + ( 20 /fpga2/M1_LDM ) + ( 21 /sdram/M1_WE# ) ( 22 /fpga2/M1_CAS# ) - ( 23 /fpga2/M1_RAS# ) - ( 24 /sdram/M1_CS# ) + ( 23 /sdram/M1_RAS# ) + ( 24 /fpga2/M1_CS# ) ( 25 ? ) - ( 26 /fpga2/M1_BA0 ) - ( 27 /fpga2/M1_BA1 ) + ( 26 /sdram/M1_BA0 ) + ( 27 /sdram/M1_BA1 ) ( 28 /sdram/M1_A10 ) ( 29 /fpga2/M1_A0 ) ( 30 /fpga2/M1_A1 ) ( 31 /fpga2/M1_A2 ) - ( 32 /fpga2/M1_A3 ) + ( 32 /sdram/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /fpga2/M1_A4 ) + ( 35 /sdram/M1_A4 ) ( 36 /fpga2/M1_A5 ) - ( 37 /sdram/M1_A6 ) - ( 38 /sdram/M1_A7 ) - ( 39 /sdram/M1_A8 ) - ( 40 /sdram/M1_A9 ) + ( 37 /fpga2/M1_A6 ) + ( 38 /fpga2/M1_A7 ) + ( 39 /fpga2/M1_A8 ) + ( 40 /fpga2/M1_A9 ) ( 41 /sdram/M1_A11 ) - ( 42 /sdram/M1_A12 ) + ( 42 /fpga2/M1_A12 ) ( 43 ? ) - ( 44 /sdram/M1_CLK# ) - ( 45 /fpga2/M1_CKE ) - ( 46 /sdram/M1_CLK ) - ( 47 /fpga2/M1_UDM ) + ( 44 /fpga2/M1_CLK# ) + ( 45 /sdram/M1_CKE ) + ( 46 /fpga2/M1_CLK ) + ( 47 /sdram/M1_UDM ) ( 48 GND ) ( 49 /sdram/M1_VREF ) ( 50 ? ) - ( 51 /fpga2/M1_UDQS ) + ( 51 /sdram/M1_UDQS ) ( 52 GND ) ( 53 ? ) ( 54 /fpga2/M1_DQ8 ) ( 55 +2.5V ) - ( 56 /sdram/M1_DQ9 ) + ( 56 /fpga2/M1_DQ9 ) ( 57 /fpga2/M1_DQ10 ) ( 58 GND ) ( 59 /sdram/M1_DQ11 ) @@ -1089,7 +1225,7 @@ ( 62 /fpga2/M1_DQ13 ) ( 63 /sdram/M1_DQ14 ) ( 64 GND ) - ( 65 /sdram/M1_DQ15 ) + ( 65 /fpga2/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} @@ -1192,50 +1328,50 @@ ( 1 +2.5V ) ( 2 /fpga2/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /sdram/M0_DQ1 ) - ( 5 /fpga2/M0_DQ2 ) + ( 4 /fpga2/M0_DQ1 ) + ( 5 /sdram/M0_DQ2 ) ( 6 GND ) ( 7 /fpga2/M0_DQ3 ) ( 8 /sdram/M0_DQ4 ) ( 9 +2.5V ) - ( 10 /sdram/M0_DQ5 ) + ( 10 /fpga2/M0_DQ5 ) ( 11 /sdram/M0_DQ6 ) ( 12 GND ) - ( 13 /sdram/M0_DQ7 ) + ( 13 /fpga2/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /fpga2/M0_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /sdram/M0_LDM ) - ( 21 /sdram/M0_WE# ) - ( 22 /sdram/M0_CAS# ) - ( 23 /fpga2/M0_RAS# ) + ( 20 /fpga2/M0_LDM ) + ( 21 /fpga2/M0_WE# ) + ( 22 /fpga2/M0_CAS# ) + ( 23 /sdram/M0_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /sdram/M0_BA0 ) - ( 27 /fpga2/M0_BA1 ) - ( 28 /fpga2/M0_A10 ) - ( 29 /sdram/M0_A0 ) + ( 27 /sdram/M0_BA1 ) + ( 28 /sdram/M0_A10 ) + ( 29 /fpga2/M0_A0 ) ( 30 /fpga2/M0_A1 ) ( 31 /fpga2/M0_A2 ) ( 32 /fpga2/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /sdram/M0_A4 ) + ( 35 /fpga2/M0_A4 ) ( 36 /fpga2/M0_A5 ) ( 37 /fpga2/M0_A6 ) ( 38 /fpga2/M0_A7 ) - ( 39 /fpga2/M0_A8 ) + ( 39 /sdram/M0_A8 ) ( 40 /fpga2/M0_A9 ) ( 41 /fpga2/M0_A11 ) - ( 42 /fpga2/M0_A12 ) + ( 42 /sdram/M0_A12 ) ( 43 ? ) - ( 44 /sdram/M0_CLK# ) - ( 45 /fpga2/M0_CKE ) - ( 46 /fpga2/M0_CLK ) - ( 47 /fpga2/M0_UDM ) + ( 44 /fpga2/M0_CLK# ) + ( 45 /sdram/M0_CKE ) + ( 46 /sdram/M0_CLK ) + ( 47 /sdram/M0_UDM ) ( 48 GND ) ( 49 /sdram/M0_VREF ) ( 50 ? ) @@ -1244,16 +1380,16 @@ ( 53 ? ) ( 54 /sdram/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /fpga2/M0_DQ9 ) + ( 56 /sdram/M0_DQ9 ) ( 57 /fpga2/M0_DQ10 ) ( 58 GND ) ( 59 /fpga2/M0_DQ11 ) ( 60 /fpga2/M0_DQ12 ) ( 61 +2.5V ) - ( 62 /sdram/M0_DQ13 ) + ( 62 /fpga2/M0_DQ13 ) ( 63 /fpga2/M0_DQ14 ) ( 64 GND ) - ( 65 /sdram/M0_DQ15 ) + ( 65 /fpga2/M0_DQ15 ) ( 66 GND ) ) ( /4C4320F3/4C5D8114 0402 C9 100nF {Lib=C} @@ -1305,11 +1441,11 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7F39 0402 R1 4.7K {Lib=R} - ( 1 /ether/ETH_MDIO ) + ( 1 /fpga1/ETH_MDIO ) ( 2 +3.3V ) ) ( /4C4320F3/4C5D7ECF 0402 R2 6.65K {Lib=R} - ( 1 N-000133 ) + ( 1 N-000120 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 0402 C11 100nF {Lib=C} @@ -1329,28 +1465,28 @@ ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /ether/ETH_MDIO ) + ( 1 /fpga1/ETH_MDIO ) ( 2 /fpga1/ETH_MDC ) - ( 3 /fpga1/ETH_RXD3 ) - ( 4 /fpga1/ETH_RXD2 ) + ( 3 /ether/ETH_RXD3 ) + ( 4 /ether/ETH_RXD2 ) ( 5 /fpga1/ETH_RXD1 ) ( 6 /ether/ETH_RXD0 ) ( 7 +3.3V ) ( 8 GND ) - ( 9 /ether/ETH_RXDV ) + ( 9 /fpga1/ETH_RXDV ) ( 10 /fpga1/ETH_RXC ) - ( 11 /ether/ETH_RXER ) + ( 11 /fpga1/ETH_RXER ) ( 12 GND ) ( 13 +1.8V ) ( 14 /ether/ETH_TXER ) - ( 15 /fpga1/ETH_TXC ) + ( 15 /ether/ETH_TXC ) ( 16 /fpga1/ETH_TXEN ) - ( 17 /fpga1/ETH_TXD0 ) + ( 17 /ether/ETH_TXD0 ) ( 18 /fpga1/ETH_TXD1 ) - ( 19 /fpga1/ETH_TXD2 ) - ( 20 /fpga1/ETH_TXD3 ) - ( 21 /fpga1/ETH_COL ) - ( 22 /ether/ETH_CRS ) + ( 19 /ether/ETH_TXD2 ) + ( 20 /ether/ETH_TXD3 ) + ( 21 /ether/ETH_COL ) + ( 22 /fpga1/ETH_CRS ) ( 23 GND ) ( 24 +3.3V ) ( 25 /ether/ETH_INT ) @@ -1365,7 +1501,7 @@ ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000133 ) + ( 37 N-000120 ) ( 38 /ether/ETH_A3.3V ) ( 39 GND ) ( 40 /ether/MAG_TX- ) @@ -1374,7 +1510,7 @@ ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 /fpga1/ETH_CLK ) + ( 46 /ether/ETH_CLK ) ( 47 /ether/ETH_PLL1.8V ) ( 48 /fpga1/ETH_RESET_N ) ) @@ -1395,11 +1531,11 @@ ( 2 /ether/MAG_RX+ ) ) ( /4C4320F3/4C5D71DB 0402 R8 220 {Lib=R} - ( 1 N-000120 ) + ( 1 N-000132 ) ( 2 /ether/ETH_LED1 ) ) ( /4C4320F3/4C5D719D 0402 R7 220 {Lib=R} - ( 1 N-000121 ) + ( 1 N-000131 ) ( 2 /ether/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} @@ -1412,9 +1548,9 @@ ( 7 /ether/MAG_RX+ ) ( 8 /ether/MAG_RX- ) ( 9 +3.3V ) - ( 10 N-000121 ) + ( 10 N-000131 ) ( 11 +3.3V ) - ( 12 N-000120 ) + ( 12 N-000132 ) ( 13 /ether/MAG_SHIELD ) ( 14 /ether/MAG_SHIELD ) ) @@ -1432,19 +1568,19 @@ ) ( /4C5F1EDC/4C7D354D 0402 R49 24 {Lib=R} ( 1 /usb/USBD_D+ ) - ( 2 N-000146 ) + ( 2 N-000144 ) ) ( /4C5F1EDC/4C7D354C $noname R50 24 {Lib=R} ( 1 /usb/USBD_D- ) - ( 2 N-000145 ) + ( 2 N-000143 ) ) ( /4C5F1EDC/4C7D350E 0402 R52 24 {Lib=R} ( 1 /usb/USBA_D- ) - ( 2 N-000147 ) + ( 2 N-000142 ) ) ( /4C5F1EDC/4C7D3508 0402 R51 24 {Lib=R} ( 1 /usb/USBA_D+ ) - ( 2 N-000144 ) + ( 2 N-000141 ) ) ( /4C5F1EDC/4C7D32A3 0402 R48 15k {Lib=R} ( 1 +3.3V ) @@ -1462,23 +1598,23 @@ ( 1 ? ) ( 2 /usb/USBD_D- ) ( 3 /usb/USBD_D+ ) - ( 4 N-000143 ) - ( 5 N-000143 ) + ( 4 N-000153 ) + ( 5 N-000153 ) ( 6 /usb/USB_CASE_DEV ) ( 7 /usb/USB_CASE_DEV ) ( 8 /usb/USB_CASE_DEV ) ( 9 /usb/USB_CASE_DEV ) ) ( /4C5F1EDC/4C71BA25 MLF16 U7 MIC2550-MLF {Lib=MIC2550-MLF} - ( 1 /usb/USBD_SPD ) + ( 1 /fpga2/USBD_SPD ) ( 2 /fpga2/USBD_RCV ) ( 3 /usb/USBD_VP ) ( 4 /usb/USBD_VM ) ( 6 GND ) ( 7 GND ) - ( 9 /usb/USBD_OE_N ) - ( 10 N-000145 ) - ( 11 N-000146 ) + ( 9 /fpga2/USBD_OE_N ) + ( 10 N-000143 ) + ( 11 N-000144 ) ( 12 +3.3V ) ( 14 +3.3V ) ( 15 +2.5V ) @@ -1487,12 +1623,12 @@ ( 1 /usb/USBA_SPD ) ( 2 /fpga2/USBA_RCV ) ( 3 /fpga2/USBA_VP ) - ( 4 /fpga2/USBA_VM ) + ( 4 /usb/USBA_VM ) ( 6 GND ) ( 7 GND ) ( 9 /usb/USBA_OE_N ) - ( 10 N-000147 ) - ( 11 N-000144 ) + ( 10 N-000142 ) + ( 11 N-000141 ) ( 12 +3.3V ) ( 14 +3.3V ) ( 15 +2.5V ) @@ -1526,7 +1662,7 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} - ( 1 N-000143 ) + ( 1 N-000153 ) ( 2 GND ) ) ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} @@ -1534,7 +1670,7 @@ ( 2 N-000149 ) ) ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000142 ) + ( 1 N-000147 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D27 0603 R10 1M {Lib=R} @@ -1561,7 +1697,7 @@ ( 1 N-000149 ) ( 2 /usb/USBA_D- ) ( 3 /usb/USBA_D+ ) - ( 4 N-000142 ) + ( 4 N-000147 ) ( S1 /usb/USB_CASE_HOST ) ( S2 /usb/USB_CASE_HOST ) ( S3 /usb/USB_CASE_HOST ) @@ -1580,28 +1716,28 @@ ( 2 GND ) ) ( /4CB0D95D/4CBAFE50 header25x2_smd_2mm P1 CONN_25X2 {Lib=CONN_25X2} - ( 1 /expansion/FPGA_BANK0_IO_8 ) + ( 1 /fpga1/FPGA_BANK0_IO_8 ) ( 2 /expansion/FPGA_BANK0_IO_1 ) ( 3 GND ) ( 4 /expansion/FPGA_BANK0_IO_9 ) ( 5 VCCO2 ) - ( 6 /expansion/FPGA_BANK0_IO_14 ) - ( 7 /expansion/FPGA_BANK0_IO_10 ) + ( 6 /fpga1/FPGA_BANK0_IO_14 ) + ( 7 /fpga1/FPGA_BANK0_IO_10 ) ( 8 /expansion/FPGA_BANK0_IO_15 ) ( 9 /fpga1/FPGA_BANK0_IO_11 ) - ( 10 /expansion/FPGA_BANK0_IO_3 ) + ( 10 /fpga1/FPGA_BANK0_IO_3 ) ( 11 /expansion/FPGA_BANK0_IO_5 ) - ( 12 /fpga1/FPGA_BANK0_IO_18 ) + ( 12 /expansion/FPGA_BANK0_IO_18 ) ( 13 /expansion/FPGA_BANK0_IO_17 ) ( 14 /expansion/FPGA_BANK0_IO_21 ) ( 15 /fpga1/FPGA_BANK0_IO_20 ) - ( 16 /expansion/FPGA_BANK0_IO_24 ) - ( 17 /fpga1/FPGA_BANK0_IO_28 ) - ( 18 /expansion/FPGA_BANK0_IO_29 ) + ( 16 /fpga1/FPGA_BANK0_IO_24 ) + ( 17 /expansion/FPGA_BANK0_IO_28 ) + ( 18 /fpga1/FPGA_BANK0_IO_29 ) ( 19 /fpga1/FPGA_BANK0_IO_22 ) - ( 20 /expansion/FPGA_BANK0_IO_30 ) + ( 20 /fpga1/FPGA_BANK0_IO_30 ) ( 21 /expansion/FPGA_BANK0_IO_27 ) - ( 22 /fpga1/FPGA_BANK0_IO_25 ) + ( 22 /expansion/FPGA_BANK0_IO_25 ) ( 23 /expansion/FPGA_BANK0_IO_39 ) ( 24 /fpga1/FPGA_BANK0_IO_33 ) ( 25 /fpga1/FPGA_BANK0_IO_2 ) @@ -1612,28 +1748,188 @@ ( 30 /expansion/FPGA_BANK0_IO_36 ) ( 31 /fpga1/FPGA_BANK0_IO_44 ) ( 32 /fpga1/FPGA_BANK0_IO_40 ) - ( 33 /expansion/FPGA_BANK0_IO_47 ) + ( 33 /fpga1/FPGA_BANK0_IO_47 ) ( 34 /expansion/FPGA_BANK0_IO_43 ) - ( 35 /expansion/FPGA_BANK0_IO_45 ) + ( 35 /fpga1/FPGA_BANK0_IO_45 ) ( 36 /expansion/FPGA_BANK0_IO_46 ) - ( 37 /fpga1/FPGA_BANK0_IO_52 ) - ( 38 /fpga1/FPGA_BANK0_IO_50 ) - ( 39 /fpga1/FPGA_BANK0_IO_56 ) + ( 37 /expansion/FPGA_BANK0_IO_52 ) + ( 38 /expansion/FPGA_BANK0_IO_50 ) + ( 39 /expansion/FPGA_BANK0_IO_56 ) ( 40 /fpga1/FPGA_BANK0_IO_48 ) ( 41 /fpga1/FPGA_BANK0_IO_51 ) - ( 42 /expansion/FPGA_BANK0_IO_34 ) + ( 42 /fpga1/FPGA_BANK0_IO_34 ) ( 43 /expansion/FPGA_BANK0_IO_54 ) ( 44 /expansion/FPGA_BANK0_IO_49 ) ( 45 /expansion/FPGA_BANK0_IO_63 ) ( 46 /fpga1/FPGA_BANK0_IO_62 ) ( 47 /expansion/FPGA_BANK0_IO_53 ) - ( 48 /expansion/FPGA_BANK0_IO_57 ) + ( 48 /fpga1/FPGA_BANK0_IO_57 ) ( 49 /fpga1/FPGA_BANK0_IO_58 ) - ( 50 /expansion/FPGA_BANK0_IO_60 ) + ( 50 /fpga1/FPGA_BANK0_IO_60 ) ) ) * { Allowed footprints by component: +$component D1 + D? + S* +$endlist +$component C165 + SM* + C? + C1-1 +$endlist +$component R97 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C164 + SM* + C? + C1-1 +$endlist +$component R92 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C158 + SM* + C? + C1-1 +$endlist +$component C173 + SM* + C? + C1-1 +$endlist +$component C170 + SM* + C? + C1-1 +$endlist +$component R89 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R94 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C160 + SM* + C? + C1-1 +$endlist +$component C167 + SM* + C? + C1-1 +$endlist +$component C169 + SM* + C? + C1-1 +$endlist +$component C168 + SM* + C? + C1-1 +$endlist +$component C171 + SM* + C? + C1-1 +$endlist +$component C174 + SM* + C? + C1-1 +$endlist +$component C159 + SM* + C? + C1-1 +$endlist +$component C162 + SM* + C? + C1-1 +$endlist +$component R88 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R90 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C163 + SM* + C? + C1-1 +$endlist +$component R93 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C166 + SM* + C? + C1-1 +$endlist +$component C172 + SM* + C? + C1-1 +$endlist +$component R91 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C161 + SM* + C? + C1-1 +$endlist +$component R87 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R95 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R96 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C157 + SM* + C? + C1-1 +$endlist $component C156 SM* C? @@ -2316,109 +2612,109 @@ $endlist $endfootprintlist } { Pin List by Nets -Net 1 "/fpga2/M0_CKE" "M0_CKE" +Net 1 "/sdram/M0_CKE" "M0_CKE" U2 45 R24 2 -Net 2 "/sdram/M0_CAS#" "M0_CAS#" - U2 22 +Net 2 "/fpga2/M0_CAS#" "M0_CAS#" R83 2 -Net 3 "/fpga2/M1_WE#" "M1_WE#" - U3 21 + U2 22 +Net 3 "/sdram/M1_WE#" "M1_WE#" R80 2 -Net 4 "/fpga2/M1_RAS#" "M1_RAS#" - U3 23 + U3 21 +Net 4 "/sdram/M1_RAS#" "M1_RAS#" RP2 8 -Net 5 "/fpga2/M0_RAS#" "M0_RAS#" - U2 23 + U3 23 +Net 5 "/sdram/M0_RAS#" "M0_RAS#" RP15 8 -Net 6 "/sdram/M0_WE#" "M0_WE#" - U2 21 + U2 23 +Net 6 "/fpga2/M0_WE#" "M0_WE#" R84 2 -Net 7 "/flash/NF_RE_N" "NF_RE_N" + U2 21 +Net 7 "/fpga1/NF_RE_N" "NF_RE_N" U1 C15 U5 8 Net 8 "/fpga1/NF_CS1_N" "NF_CS1_N" - U1 D15 U5 9 + U1 D15 Net 9 "/fpga1/NF_ALE" "NF_ALE" U5 17 U1 A14 Net 10 "/fpga2/M0_LDQS" "M0_LDQS" - R86 2 U2 16 -Net 11 "/fpga2/M0_UDM" "M0_UDM" + R86 2 +Net 11 "/sdram/M0_UDM" "M0_UDM" U2 47 R23 2 -Net 12 "/fpga2/M1_CKE" "M1_CKE" +Net 12 "/sdram/M1_CKE" "M1_CKE" U3 45 R17 2 Net 13 "/fpga2/M1_CAS#" "M1_CAS#" - U3 22 R79 2 + U3 22 Net 14 "/fpga1/SD_CLK" "SD_CLK" J1 5 U1 A17 -Net 15 "/sdram/M0_CLK#" "M0_CLK#" +Net 15 "/fpga2/M0_CLK#" "M0_CLK#" U1 H3 R21 2 U2 44 -Net 16 "/fpga2/M0_CLK" "M0_CLK" +Net 16 "/sdram/M0_CLK" "M0_CLK" + R21 1 U2 46 U1 H4 - R21 1 -Net 17 "/sdram/M1_CLK#" "M1_CLK#" - U3 44 - U1 J19 +Net 17 "/fpga2/M1_CLK#" "M1_CLK#" R16 1 -Net 18 "/sdram/M1_CLK" "M1_CLK" + U1 J19 + U3 44 +Net 18 "/fpga2/M1_CLK" "M1_CLK" U3 46 U1 H20 R16 2 Net 19 "/usb/USBD_VM" "USBD_VM" U1 B22 U7 4 -Net 20 "/sdram/M0_LDM" "M0_LDM" - U2 20 +Net 20 "/fpga2/M0_LDM" "M0_LDM" R85 2 + U2 20 Net 21 "/fpga2/M0_UDQS" "M0_UDQS" - R22 2 U2 51 -Net 22 "/fpga2/M1_UDQS" "M1_UDQS" + R22 2 +Net 22 "/sdram/M1_UDQS" "M1_UDQS" U3 51 R19 2 -Net 23 "/sdram/M1_LDM" "M1_LDM" - U3 20 +Net 23 "/fpga2/M1_LDM" "M1_LDM" R81 2 + U3 20 Net 24 "/fpga2/M1_LDQS" "M1_LDQS" U3 16 R82 2 -Net 25 "/fpga2/M1_UDM" "M1_UDM" +Net 25 "/sdram/M1_UDM" "M1_UDM" R18 2 U3 47 -Net 26 "/sdram/M1_CS#" "M1_CS#" - U3 24 +Net 26 "/fpga2/M1_CS#" "M1_CS#" R20 2 + U3 24 Net 27 "/usb/USBD_VP" "USBD_VP" - U7 3 U1 B21 + U7 3 Net 28 "/fpga2/USBD_RCV" "USBD_RCV" U7 2 U1 A20 -Net 29 "/usb/USBD_OE_N" "USBD_OE_N" - U7 9 +Net 29 "/fpga2/USBD_OE_N" "USBD_OE_N" U1 A21 -Net 30 "/usb/USBD_SPD" "USBD_SPD" + U7 9 +Net 30 "/fpga2/USBD_SPD" "USBD_SPD" U1 B20 U7 1 -Net 31 "/fpga2/USBA_VM" "USBA_VM" +Net 31 "/usb/USBA_VM" "USBA_VM" U6 4 U1 D20 Net 32 "/fpga2/USBA_VP" "USBA_VP" U1 D19 U6 3 Net 33 "/fpga2/USBA_RCV" "USBA_RCV" - U6 2 U1 F17 + U6 2 Net 34 "/usb/USBA_OE_N" "USBA_OE_N" U6 9 U1 C19 @@ -2426,888 +2722,1053 @@ Net 35 "/usb/USBA_SPD" "USBA_SPD" U1 F16 U6 1 Net 36 "/ether/ETH_INT" "ETH_INT" - U1 A10 U4 25 + U1 A10 Net 37 "/fpga1/ETH_RESET_N" "ETH_RESET_N" - U4 48 U1 C7 -Net 38 "/fpga1/ETH_COL" "ETH_COL" - U4 21 + U4 48 +Net 38 "/ether/ETH_COL" "ETH_COL" U1 A9 -Net 39 "/ether/ETH_MDIO" "ETH_MDIO" - R1 1 + U4 21 +Net 39 "/fpga1/ETH_MDIO" "ETH_MDIO" U4 1 U1 D6 + R1 1 Net 40 "/fpga1/ETH_MDC" "ETH_MDC" - U4 2 U1 D7 + U4 2 Net 41 "/fpga1/PROG_CSO" "PROG_CSO" - U8 1 U1 T5 + U8 1 Net 42 "/fpga1/PROG_CCLK" "PROG_CCLK" - U1 AA21 U8 6 -Net 54 "/ether/ETH_RXDV" "ETH_RXDV" + U1 AA21 +Net 54 "/fpga1/ETH_RXDV" "ETH_RXDV" U4 9 U1 A6 -Net 55 "/ether/ETH_RXER" "ETH_RXER" - U1 B8 +Net 55 "/fpga1/ETH_RXER" "ETH_RXER" U4 11 + U1 B8 Net 56 "/ether/ETH_TXER" "ETH_TXER" - U4 14 U1 D8 + U4 14 Net 57 "/fpga1/ETH_TXEN" "ETH_TXEN" - U4 16 U1 D9 -Net 58 "/fpga1/ETH_TXC" "ETH_TXC" + U4 16 +Net 58 "/ether/ETH_TXC" "ETH_TXC" U1 C8 U4 15 Net 59 "/fpga1/ETH_RXC" "ETH_RXC" - U1 A7 U4 10 -Net 60 "/fpga1/ETH_CLK" "ETH_CLK" + U1 A7 +Net 60 "/ether/ETH_CLK" "ETH_CLK" U4 46 U1 A4 -Net 61 "/ether/ETH_CRS" "ETH_CRS" - U4 22 +Net 61 "/fpga1/ETH_CRS" "ETH_CRS" U1 B10 + U4 22 Net 62 "/flash/NF_WE_N" "NF_WE_N" - U1 C14 U5 18 -Net 63 "/flash/NF_CLE" "NF_CLE" + U1 C14 +Net 63 "/fpga1/NF_CLE" "NF_CLE" U5 16 U1 B14 -Net 64 "/fpga1/NF_RNB" "NF_RNB" +Net 64 "/flash/NF_RNB" "NF_RNB" U1 A15 - U5 6 U5 7 + U5 6 Net 65 "/flash/SD_CMD" "SD_CMD" J1 3 U1 C16 -Net 73 "+2.5V" "+2.5V" - U3 15 - U3 18 - U1 J18 - U1 L7 - U1 W21 - U3 55 - U3 1 - U1 R21 - U1 E19 +Net 72 "+2.5V" "+2.5V" U3 61 - U1 U18 - U1 N18 + U2 9 U3 9 U3 3 - U1 N5 - U1 J5 - U1 L21 - U1 G21 - U1 C21 - U3 33 - U1 F6 - U1 U5 - U1 U11 - C56 1 - U1 G12 - U1 N8 - U1 H9 - C59 1 - U1 F4 - U1 R10 - U1 H15 - U1 K15 - U1 M15 - U1 D16 - U1 R12 - C15 1 - C37 1 + U3 1 C17 1 + U2 1 + U2 3 + U2 61 + U2 18 + C33 1 + C22 1 + C23 1 + U1 C21 + C25 1 + U1 G21 + U1 L21 + U1 J5 + C24 1 + U7 15 + U2 33 + C27 1 + C32 1 + U6 15 + C30 1 + C31 1 + C29 1 + C28 1 C19 1 R11 1 R13 1 - C46 1 - C49 1 - U2 9 - U2 1 - U2 3 - C51 1 - C53 1 U1 W2 - U1 F11 - U1 L8 - U7 15 + U1 F4 + U1 C2 + U1 G2 U1 L2 U1 R2 - U6 15 - C68 1 - C65 1 - C62 1 - C40 1 - C43 1 - C52 1 + C26 1 + U1 N5 + U1 U5 + U1 F6 + U1 L7 + C21 1 + U2 55 + U1 J18 + U1 N18 + U1 U18 + U1 E19 + U2 15 + U1 R21 + U1 W21 + U1 L16 + C37 1 C54 1 C57 1 C60 1 C63 1 C66 1 - U1 C2 - U1 G2 - U1 R6 + C62 1 + C65 1 + C68 1 + U1 L8 U1 V6 - C31 1 - C29 1 - C28 1 - C33 1 - C22 1 - C23 1 - C25 1 - C24 1 - C26 1 + U1 R6 + U1 R12 + U1 D16 + U1 M15 + U1 K15 C77 1 - C21 1 - U1 L16 - C27 1 - C32 1 - C30 1 - U2 55 - U2 18 - U2 61 C94 1 + C46 1 + C49 1 + C51 1 + C53 1 + C56 1 + C59 1 + C40 1 + C43 1 + C52 1 + U1 H15 + U1 R10 + U1 H9 + U1 N8 + U1 G12 + U1 U11 + U1 F11 + C15 1 + U3 15 + U3 33 C70 1 C71 1 C34 1 - U2 33 - U2 15 -Net 87 "/sdram/M0_VREF" "M0_VREF" - R11 2 - R12 1 + U3 18 + U3 55 +Net 87 "/sdram/M1_VREF" "M1_VREF" + R14 1 + R13 2 + C20 1 + U3 49 + C19 2 +Net 88 "/sdram/M0_VREF" "M0_VREF" C17 2 C18 1 + R12 1 U2 49 -Net 88 "/sdram/M1_VREF" "M1_VREF" - C20 1 - C19 2 - R13 2 - R14 1 - U3 49 -Net 119 "+3.3V" "+3.3V" - R3 1 - C50 1 - C47 1 - C44 1 - C41 1 - R4 1 - U5 37 - U1 B4 - U1 B7 - U7 14 - U7 12 - U1 E13 - U1 G14 - U1 B15 + R11 2 +Net 89 "+3.3V" "+3.3V" + C5 1 + C3 1 + R30 1 + C1 1 + C10 1 + R55 1 + C72 1 + C73 1 + C13 1 + R29 1 + J4 9 C91 1 - C90 1 + U1 B11 U1 G10 - U6 14 - U6 12 U1 E9 U1 B19 U1 E17 - U4 24 - U4 7 - U1 B11 - R48 1 - R1 2 - C11 1 - C10 1 - L2 1 - C5 1 - C3 1 - C1 1 - C74 1 - C73 1 - U1 Y20 - C72 1 - C36 1 - J4 6 - J4 9 - J4 11 - C75 2 J1 4 - C13 1 - R5 1 - R6 1 - R55 1 - R29 1 + C50 1 + C47 1 + C44 1 + J4 11 + C41 1 J4 3 U5 12 - C35 1 - C14 1 U5 19 - R30 1 + U5 37 + U1 Y20 + C11 1 + U4 24 + U1 B15 + U1 G14 + R5 1 + R6 1 + R4 1 + R3 1 + U1 E13 + U1 B7 + U1 B4 + C90 1 + U4 7 + R1 2 + J4 6 + R48 1 + C14 1 + L2 1 + U7 14 + U7 12 + C74 1 + C75 2 + U6 14 + U6 12 + C36 1 + C35 1 Net 120 "" "" - J4 12 - R8 1 -Net 121 "" "" + U4 37 + R2 1 +Net 121 "/ether/ETH_A3.3V" "ETH_A3.3V" + C7 1 + U4 38 + C8 1 + L2 2 +Net 122 "/ether/ETH_LED1" "ETH_LED1" + R8 2 + U4 27 +Net 130 "/ether/MAG_SHIELD" "MAG_SHIELD" + J4 13 + J4 14 + R9 1 + C12 1 +Net 131 "" "" J4 10 R7 1 -Net 124 "/ether/ETH_PLL1.8V" "ETH_PLL1.8V" +Net 132 "" "" + R8 1 + J4 12 +Net 133 "/ether/ETH_LED0" "ETH_LED0" + U4 26 + R7 2 +Net 134 "/ether/ETH_PLL1.8V" "ETH_PLL1.8V" L3 2 C9 1 U4 47 -Net 125 "+1.8V" "+1.8V" - U4 13 - L1 1 +Net 135 "+1.8V" "+1.8V" C2 1 + U4 13 C4 1 -Net 126 "/ether/ETH_A1.8V" "ETH_A1.8V" + L1 1 +Net 136 "/ether/MAG_TX-" "MAG_TX-" + J4 2 + R4 2 + U4 40 +Net 137 "/ether/MAG_TX+" "MAG_TX+" + J4 1 + R3 2 + U4 41 +Net 138 "/ether/MAG_RX+" "MAG_RX+" + R5 2 + J4 7 + U4 33 +Net 139 "/ether/MAG_RX-" "MAG_RX-" + J4 8 + U4 32 + R6 2 +Net 140 "/ether/ETH_A1.8V" "ETH_A1.8V" U4 31 L3 1 C6 1 L1 2 -Net 130 "/ether/MAG_RX-" "MAG_RX-" - J4 8 - U4 32 - R6 2 -Net 133 "" "" - U4 37 - R2 1 -Net 134 "/ether/MAG_TX-" "MAG_TX-" - U4 40 - J4 2 - R4 2 -Net 135 "/ether/ETH_LED1" "ETH_LED1" - R8 2 - U4 27 -Net 136 "/ether/ETH_A3.3V" "ETH_A3.3V" - L2 2 - C8 1 - C7 1 - U4 38 -Net 137 "/ether/MAG_TX+" "MAG_TX+" - R3 2 - U4 41 - J4 1 -Net 138 "/ether/ETH_LED0" "ETH_LED0" - R7 2 - U4 26 -Net 139 "/ether/MAG_RX+" "MAG_RX+" - R5 2 - J4 7 - U4 33 -Net 140 "/ether/MAG_SHIELD" "MAG_SHIELD" - R9 1 - C12 1 - J4 13 - J4 14 -Net 142 "" "" - J5 4 - L5 1 -Net 143 "" "" - L7 1 - J7 4 - J7 5 -Net 144 "" "" - U6 11 +Net 141 "" "" R51 2 -Net 145 "" "" - U7 10 + U6 11 +Net 142 "" "" + U6 10 + R52 2 +Net 143 "" "" R50 2 -Net 146 "" "" + U7 10 +Net 144 "" "" U7 11 R49 2 +Net 146 "/usb/USBA_D-" "USBA_D-" + J5 2 + V2 1 + R52 1 + R46 2 + V2 1 Net 147 "" "" - R52 2 - U6 10 + L5 1 + J5 4 +Net 148 "/usb/USB_CASE_DEV" "USB_CASE_DEV" + C38 1 + J7 8 + R15 1 + J7 9 + J7 6 + J7 7 Net 149 "" "" - L4 2 J5 1 + L4 2 Net 150 "" "" F1 1 L4 1 -Net 151 "/usb/USB_CASE_HOST" "USB_CASE_HOST" +Net 152 "/usb/USB_CASE_HOST" "USB_CASE_HOST" + R10 1 J5 S4 J5 S3 - C16 1 J5 S2 J5 S1 - R10 1 -Net 152 "/usb/USB_CASE_DEV" "USB_CASE_DEV" - R15 1 - C38 1 - J7 6 - J7 7 - J7 8 - J7 9 -Net 153 "/usb/USBD_D-" "USBD_D-" - V4 1 - R50 1 - V4 1 + C16 1 +Net 153 "" "" + J7 5 + J7 4 + L7 1 +Net 154 "/usb/USBD_D+" "USBD_D+" + J7 3 + R49 1 + V3 1 + V3 1 + R55 2 + R53 2 +Net 155 "/usb/USBD_D-" "USBD_D-" R54 2 + V4 1 + V4 1 J7 2 -Net 154 "/usb/USBA_D-" "USBA_D-" - R52 1 - R46 2 - J5 2 - V2 1 - V2 1 -Net 155 "/usb/USBA_D+" "USBA_D+" + R50 1 +Net 156 "/usb/USBA_D+" "USBA_D+" J5 3 - R51 1 + V1 1 V1 1 R48 2 R47 2 - V1 1 -Net 156 "/usb/USBD_D+" "USBD_D+" - J7 3 - R55 2 - V3 1 - V3 1 - R49 1 - R53 2 + R51 1 +Net 157 "" "" + U11 3 + R87 1 +Net 158 "" "" + R95 1 + R96 2 + U11 1 +Net 160 "" "" + C163 2 + R93 1 + U12 10 +Net 161 "" "" + C166 1 + U12 9 +Net 163 "" "" + R87 2 + C161 1 +Net 164 "" "" + U11 6 + L10 2 +Net 165 "" "" + U11 2 + U11 7 +Net 166 "" "" + U10 5 + L9 2 +Net 167 "" "" + L8 2 + C158 1 +Net 168 "" "" + U12 3 + U12 4 + U12 1 + U12 1 + U12 1 + U12 5 + U12 1 + C166 2 + L11 2 + U12 2 + U12 1 +Net 169 "" "" + U12 12 + R91 2 + R90 2 +Net 170 "" "" + R88 1 + C162 1 +Net 171 "" "" + R94 2 + U9 6 + R97 1 + C165 1 + U9 2 +Net 172 "" "" + C170 1 + C173 1 + R92 2 + C164 1 + R97 2 + D1 2 + U9 7 +Net 174 "" "" + R91 1 + L11 1 + C172 1 + C174 1 +Net 177 "" "" + R88 2 + U12 13 Net 178 "" "" - U12 1 - U12 1 - U12 1 - U12 1 - U12 1 -Net 200 "/fpga2/R_M1_A7" "R_M1_A7" + U12 18 + U12 19 + U12 11 + U12 20 +Net 179 "" "" + U12 6 + U12 7 + U12 8 + R93 2 +Net 182 "" "" + L9 1 + C169 1 + U10 1 + C167 1 +Net 183 "" "" + C171 1 + C168 1 + L10 1 + R96 1 +Net 188 "" "" + R94 1 + U9 3 +Net 189 "" "" + C164 2 + R92 1 + R89 2 + U9 4 +Net 190 "" "" + D1 1 + U9 8 + L8 1 +Net 191 "/fpga2/R_M1_A7" "R_M1_A7" RP6 8 U1 E20 -Net 201 "/fpga2/R_M1_A8" "R_M1_A8" +Net 192 "/fpga2/R_M1_A8" "R_M1_A8" RP7 5 U1 C20 -Net 202 "/fpga2/R_M1_A9" "R_M1_A9" +Net 193 "/fpga2/R_M1_A9" "R_M1_A9" RP7 6 U1 C22 -Net 203 "/fpga2/R_M1_A11" "R_M1_A11" - RP7 7 +Net 194 "/fpga2/R_M1_A11" "R_M1_A11" U1 F19 -Net 204 "/fpga2/R_M1_A12" "R_M1_A12" + RP7 7 +Net 195 "/fpga2/R_M1_A12" "R_M1_A12" U1 D22 RP7 8 -Net 205 "/fpga2/R_M1_A4" "R_M1_A4" +Net 196 "/fpga2/R_M1_A4" "R_M1_A4" RP6 5 U1 F20 -Net 206 "/fpga2/R_M1_A5" "R_M1_A5" +Net 197 "/fpga2/R_M1_A5" "R_M1_A5" U1 K20 RP6 6 -Net 207 "/fpga2/R_M1_A6" "R_M1_A6" - RP6 7 +Net 198 "/fpga2/R_M1_A6" "R_M1_A6" U1 K19 -Net 208 "/fpga2/R_M1_A10" "R_M1_A10" + RP6 7 +Net 199 "/fpga2/R_M1_A10" "R_M1_A10" U1 G19 RP2 4 -Net 209 "/fpga2/R_M1_A0" "R_M1_A0" - U1 F21 +Net 200 "/fpga2/R_M1_A0" "R_M1_A0" RP1 1 -Net 210 "/fpga2/R_M1_A1" "R_M1_A1" + U1 F21 +Net 201 "/fpga2/R_M1_A1" "R_M1_A1" U1 F22 RP1 2 -Net 211 "/fpga2/R_M1_A2" "R_M1_A2" - U1 E22 +Net 202 "/fpga2/R_M1_A2" "R_M1_A2" RP1 3 -Net 212 "/fpga2/R_M1_A3" "R_M1_A3" + U1 E22 +Net 203 "/fpga2/R_M1_A3" "R_M1_A3" U1 G20 RP1 4 -Net 213 "/fpga2/R_M1_BA0" "R_M1_BA0" +Net 204 "/fpga2/R_M1_BA0" "R_M1_BA0" U1 J17 RP2 2 -Net 214 "/fpga2/R_M1_BA1" "R_M1_BA1" - RP2 3 +Net 205 "/fpga2/R_M1_BA1" "R_M1_BA1" U1 K17 -Net 217 "/fpga2/R_M1_DQ4" "R_M1_DQ4" - RP4 1 + RP2 3 +Net 208 "/fpga2/R_M1_DQ4" "R_M1_DQ4" U1 J20 -Net 218 "/fpga2/R_M1_LDQS" "R_M1_LDQS" + RP4 1 +Net 209 "/fpga2/R_M1_LDQS" "R_M1_LDQS" U1 L20 R82 1 -Net 219 "/fpga2/R_M1_UDM" "R_M1_UDM" +Net 210 "/fpga2/R_M1_UDM" "R_M1_UDM" R18 1 U1 M20 -Net 220 "/fpga2/R_M1_DQ0" "R_M1_DQ0" - RP5 1 +Net 211 "/fpga2/R_M1_DQ0" "R_M1_DQ0" U1 N20 -Net 222 "/fpga2/R_M1_DQ10" "R_M1_DQ10" - U1 R20 + RP5 1 +Net 213 "/fpga2/R_M1_DQ10" "R_M1_DQ10" RP9 7 -Net 224 "/fpga2/R_M1_DQ12" "R_M1_DQ12" - RP8 5 + U1 R20 +Net 215 "/fpga2/R_M1_DQ12" "R_M1_DQ12" U1 U20 -Net 227 "/fpga2/R_M1_CKE" "R_M1_CKE" + RP8 5 +Net 218 "/fpga2/R_M1_CKE" "R_M1_CKE" R17 1 U1 D21 -Net 228 "/fpga2/R_M1_RAS#" "R_M1_RAS#" +Net 219 "/fpga2/R_M1_RAS#" "R_M1_RAS#" U1 H21 RP2 1 -Net 229 "/fpga2/R_M1_DQ6" "R_M1_DQ6" +Net 220 "/fpga2/R_M1_DQ6" "R_M1_DQ6" U1 K21 RP4 3 -Net 230 "/fpga2/R_M1_DQ2" "R_M1_DQ2" - U1 M21 +Net 221 "/fpga2/R_M1_DQ2" "R_M1_DQ2" RP5 3 -Net 236 "/fpga2/R_M0_A2" "R_M0_A2" - RP14 3 + U1 M21 +Net 227 "/fpga2/R_M0_A2" "R_M0_A2" U1 H5 -Net 241 "/fpga2/R_M0_A7" "R_M0_A7" - RP17 1 + RP14 3 +Net 232 "/fpga2/R_M0_A7" "R_M0_A7" U1 H6 -Net 243 "/fpga2/R_M0_A3" "R_M0_A3" - U1 K6 + RP17 1 +Net 234 "/fpga2/R_M0_A3" "R_M0_A3" RP14 4 -Net 267 "/fpga2/R_M1_WE#" "R_M1_WE#" + U1 K6 +Net 258 "/fpga2/R_M1_WE#" "R_M1_WE#" U1 H19 R80 1 -Net 268 "/fpga2/R_M1_LDM" "R_M1_LDM" +Net 259 "/fpga2/R_M1_LDM" "R_M1_LDM" U1 L19 R81 1 -Net 275 "/fpga2/R_M1_DQ8" "R_M1_DQ8" - U1 P21 +Net 266 "/fpga2/R_M1_DQ8" "R_M1_DQ8" RP9 5 -Net 276 "/fpga2/R_M1_DQ14" "R_M1_DQ14" - RP8 7 + U1 P21 +Net 267 "/fpga2/R_M1_DQ14" "R_M1_DQ14" U1 V21 -Net 278 "/fpga2/R_M1_CAS#" "R_M1_CAS#" + RP8 7 +Net 269 "/fpga2/R_M1_CAS#" "R_M1_CAS#" U1 H22 R79 1 -Net 279 "/fpga2/R_M1_DQ5" "R_M1_DQ5" - U1 J22 +Net 270 "/fpga2/R_M1_DQ5" "R_M1_DQ5" RP4 2 -Net 280 "/fpga2/R_M1_DQ7" "R_M1_DQ7" - U1 K22 + U1 J22 +Net 271 "/fpga2/R_M1_DQ7" "R_M1_DQ7" RP4 4 -Net 282 "/fpga2/R_M1_DQ3" "R_M1_DQ3" + U1 K22 +Net 273 "/fpga2/R_M1_DQ3" "R_M1_DQ3" U1 M22 RP5 4 -Net 283 "/fpga2/R_M1_DQ1" "R_M1_DQ1" - U1 N22 +Net 274 "/fpga2/R_M1_DQ1" "R_M1_DQ1" RP5 2 -Net 284 "/fpga2/R_M1_DQ9" "R_M1_DQ9" - U1 P22 + U1 N22 +Net 275 "/fpga2/R_M1_DQ9" "R_M1_DQ9" RP9 6 -Net 285 "/fpga2/R_M1_DQ11" "R_M1_DQ11" + U1 P22 +Net 276 "/fpga2/R_M1_DQ11" "R_M1_DQ11" RP9 8 U1 R22 -Net 287 "/fpga2/R_M1_DQ13" "R_M1_DQ13" - RP8 6 +Net 278 "/fpga2/R_M1_DQ13" "R_M1_DQ13" U1 U22 -Net 288 "/fpga2/R_M1_DQ15" "R_M1_DQ15" + RP8 6 +Net 279 "/fpga2/R_M1_DQ15" "R_M1_DQ15" U1 V22 RP8 8 -Net 301 "/fpga2/R_M0_A8" "R_M0_A8" +Net 292 "/fpga2/R_M0_A8" "R_M0_A8" RP18 4 U1 E3 -Net 302 "/fpga2/R_M0_A4" "R_M0_A4" +Net 293 "/fpga2/R_M0_A4" "R_M0_A4" RP17 4 U1 F3 -Net 303 "/fpga2/R_M0_BA0" "R_M0_BA0" +Net 294 "/fpga2/R_M0_BA0" "R_M0_BA0" RP15 2 U1 G3 -Net 304 "/fpga2/R_M0_DQ4" "R_M0_DQ4" - U1 J3 +Net 295 "/fpga2/R_M0_DQ4" "R_M0_DQ4" RP12 1 -Net 305 "/fpga2/R_M0_A5" "R_M0_A5" + U1 J3 +Net 296 "/fpga2/R_M0_A5" "R_M0_A5" U1 K3 RP17 3 -Net 306 "/fpga2/R_M0_DQ0" "R_M0_DQ0" +Net 297 "/fpga2/R_M0_DQ0" "R_M0_DQ0" U1 N3 RP13 1 -Net 308 "/fpga2/R_M0_DQ10" "R_M0_DQ10" - RP11 3 +Net 299 "/fpga2/R_M0_DQ10" "R_M0_DQ10" U1 R3 -Net 310 "/fpga2/R_M0_DQ12" "R_M0_DQ12" + RP11 3 +Net 301 "/fpga2/R_M0_DQ12" "R_M0_DQ12" RP10 1 U1 U3 -Net 315 "/fpga2/R_M0_A10" "R_M0_A10" - U1 G4 +Net 306 "/fpga2/R_M0_A10" "R_M0_A10" RP15 4 -Net 316 "/fpga2/R_M0_A6" "R_M0_A6" + U1 G4 +Net 307 "/fpga2/R_M0_A6" "R_M0_A6" U1 J4 RP17 2 -Net 321 "/fpga2/R_M0_A11" "R_M0_A11" +Net 312 "/fpga2/R_M0_A11" "R_M0_A11" RP18 2 U1 C1 -Net 322 "/fpga2/R_M0_A12" "R_M0_A12" +Net 313 "/fpga2/R_M0_A12" "R_M0_A12" U1 D1 RP18 1 -Net 323 "/fpga2/R_M0_A9" "R_M0_A9" +Net 314 "/fpga2/R_M0_A9" "R_M0_A9" RP18 3 U1 E1 -Net 325 "/fpga2/R_M0_BA1" "R_M0_BA1" - RP15 3 +Net 316 "/fpga2/R_M0_BA1" "R_M0_BA1" U1 G1 -Net 326 "/fpga2/R_M0_A1" "R_M0_A1" - U1 H1 + RP15 3 +Net 317 "/fpga2/R_M0_A1" "R_M0_A1" RP14 2 -Net 327 "/fpga2/R_M0_DQ5" "R_M0_DQ5" - U1 J1 + U1 H1 +Net 318 "/fpga2/R_M0_DQ5" "R_M0_DQ5" RP12 2 -Net 328 "/fpga2/R_M0_DQ7" "R_M0_DQ7" - RP12 4 + U1 J1 +Net 319 "/fpga2/R_M0_DQ7" "R_M0_DQ7" U1 K1 -Net 330 "/fpga2/R_M0_DQ3" "R_M0_DQ3" + RP12 4 +Net 321 "/fpga2/R_M0_DQ3" "R_M0_DQ3" U1 M1 RP13 4 -Net 331 "/fpga2/R_M0_DQ1" "R_M0_DQ1" +Net 322 "/fpga2/R_M0_DQ1" "R_M0_DQ1" U1 N1 RP13 2 -Net 332 "/fpga2/R_M0_DQ9" "R_M0_DQ9" +Net 323 "/fpga2/R_M0_DQ9" "R_M0_DQ9" U1 P1 RP11 2 -Net 333 "/fpga2/R_M0_DQ11" "R_M0_DQ11" - U1 R1 +Net 324 "/fpga2/R_M0_DQ11" "R_M0_DQ11" RP11 4 -Net 335 "/fpga2/R_M0_DQ13" "R_M0_DQ13" - U1 U1 + U1 R1 +Net 326 "/fpga2/R_M0_DQ13" "R_M0_DQ13" RP10 2 -Net 336 "/fpga2/R_M0_DQ15" "R_M0_DQ15" + U1 U1 +Net 327 "/fpga2/R_M0_DQ15" "R_M0_DQ15" RP10 4 U1 V1 -Net 341 "/fpga2/R_M0_A0" "R_M0_A0" +Net 332 "/fpga2/R_M0_A0" "R_M0_A0" RP14 1 U1 H2 -Net 342 "/fpga2/R_M0_DQ6" "R_M0_DQ6" +Net 333 "/fpga2/R_M0_DQ6" "R_M0_DQ6" U1 K2 RP12 3 -Net 343 "/fpga2/R_M0_DQ2" "R_M0_DQ2" +Net 334 "/fpga2/R_M0_DQ2" "R_M0_DQ2" U1 M2 RP13 3 -Net 344 "/fpga2/R_M0_DQ8" "R_M0_DQ8" +Net 335 "/fpga2/R_M0_DQ8" "R_M0_DQ8" RP11 1 U1 P2 -Net 345 "/fpga2/R_M0_DQ14" "R_M0_DQ14" - U1 V2 +Net 336 "/fpga2/R_M0_DQ14" "R_M0_DQ14" RP10 3 -Net 346 "/fpga2/R_M0_RAS#" "R_M0_RAS#" + U1 V2 +Net 337 "/fpga2/R_M0_RAS#" "R_M0_RAS#" U1 K5 RP15 1 -Net 347 "/fpga2/R_M0_LDM" "R_M0_LDM" - R85 1 +Net 338 "/fpga2/R_M0_LDM" "R_M0_LDM" U1 L4 -Net 348 "/fpga2/R_M0_CAS#" "R_M0_CAS#" + R85 1 +Net 339 "/fpga2/R_M0_CAS#" "R_M0_CAS#" R83 1 U1 K4 -Net 349 "/fpga2/R_M0_WE#" "R_M0_WE#" +Net 340 "/fpga2/R_M0_WE#" "R_M0_WE#" U1 F2 R84 1 -Net 350 "/fpga2/R_M1_UDQS" "R_M1_UDQS" +Net 341 "/fpga2/R_M1_UDQS" "R_M1_UDQS" U1 T21 R19 1 -Net 351 "/fpga2/R_M1_CS#" "R_M1_CS#" +Net 342 "/fpga2/R_M1_CS#" "R_M1_CS#" R20 1 U1 H16 -Net 352 "/fpga2/R_M0_LDQS" "R_M0_LDQS" +Net 343 "/fpga2/R_M0_LDQS" "R_M0_LDQS" R86 1 U1 L3 -Net 353 "/fpga2/R_M0_UDQS" "R_M0_UDQS" - U1 T2 +Net 344 "/fpga2/R_M0_UDQS" "R_M0_UDQS" R22 1 -Net 354 "/fpga2/R_M0_CKE" "R_M0_CKE" + U1 T2 +Net 345 "/fpga2/R_M0_CKE" "R_M0_CKE" R24 1 U1 D2 -Net 355 "/fpga2/R_M0_UDM" "R_M0_UDM" +Net 346 "/fpga2/R_M0_UDM" "R_M0_UDM" U1 M3 R23 1 -Net 356 "" "" - R29 2 +Net 347 "" "" U1 AA1 -Net 359 "" "" + R29 2 +Net 350 "" "" R30 2 U1 Y22 -Net 364 "+1.2V" "+1.2V" +Net 355 "+1.2V" "+1.2V" + U1 K11 + C76 1 + U1 J14 + U1 N10 + U1 L14 + U1 N14 + U1 R14 + U1 L10 + U1 J10 C93 1 C92 1 U1 J8 - U1 P13 C39 1 - U1 M13 - U1 M11 - U1 P11 - U1 N12 - U1 L12 - U1 J12 - U1 K9 - U1 M9 U1 P9 - C45 1 + U1 M9 + U1 K9 + U1 P11 + U1 M11 C48 1 - U1 R14 - U1 N14 - U1 L14 - U1 J14 - U1 J10 - U1 L10 - U1 N10 - C42 1 - C76 1 + U1 P13 + U1 J12 + U1 L12 + U1 N12 + C45 1 U1 K13 - U1 K11 -Net 397 "/fpga2/M1_BA1" "M1_BA1" + U1 M13 + C42 1 +Net 388 "/sdram/M1_BA1" "M1_BA1" RP2 6 U3 27 -Net 398 "/fpga2/M1_BA0" "M1_BA0" +Net 389 "/sdram/M1_BA0" "M1_BA0" U3 26 RP2 7 -Net 399 "/fpga2/M0_BA1" "M0_BA1" - U2 27 +Net 390 "/sdram/M0_BA1" "M0_BA1" RP15 6 -Net 400 "/sdram/M0_BA0" "M0_BA0" + U2 27 +Net 391 "/sdram/M0_BA0" "M0_BA0" RP15 7 U2 26 -Net 401 "/fpga1/PROG_MISO3" "PROG_MISO3" +Net 392 "/fpga1/PROG_MISO3" "PROG_MISO3" U8 7 U1 U13 -Net 402 "/fpga1/PROG_MISO2" "PROG_MISO2" - U8 3 +Net 393 "/fpga1/PROG_MISO2" "PROG_MISO2" U1 U14 -Net 403 "/fpga1/PROG_MISO1" "PROG_MISO1" - U8 2 + U8 3 +Net 394 "/fpga1/PROG_MISO1" "PROG_MISO1" U1 AA20 -Net 404 "/fpga1/PROG_MISO0" "PROG_MISO0" + U8 2 +Net 395 "/fpga1/PROG_MISO0" "PROG_MISO0" U8 5 U1 AB20 -Net 405 "/fpga1/NF_D7" "NF_D7" +Net 396 "/fpga1/NF_D7" "NF_D7" U1 D11 U5 44 -Net 406 "/fpga1/NF_D6" "NF_D6" +Net 397 "/fpga1/NF_D6" "NF_D6" U1 A11 U5 43 -Net 407 "/flash/NF_D5" "NF_D5" +Net 398 "/flash/NF_D5" "NF_D5" U5 42 U1 C11 -Net 408 "/flash/NF_D4" "NF_D4" - U1 A12 +Net 399 "/fpga1/NF_D4" "NF_D4" U5 41 -Net 409 "/fpga1/NF_D3" "NF_D3" - U1 B12 + U1 A12 +Net 400 "/flash/NF_D3" "NF_D3" U5 32 -Net 410 "/fpga2/M0_A12" "M0_A12" + U1 B12 +Net 401 "/sdram/M0_A12" "M0_A12" U2 42 RP18 8 -Net 411 "/fpga2/M0_A11" "M0_A11" +Net 402 "/fpga2/M0_A11" "M0_A11" RP18 7 U2 41 -Net 412 "/fpga2/M0_A10" "M0_A10" +Net 403 "/sdram/M0_A10" "M0_A10" RP15 5 U2 28 -Net 413 "/fpga2/M0_A9" "M0_A9" - RP18 6 +Net 404 "/fpga2/M0_A9" "M0_A9" U2 40 -Net 414 "/fpga2/M0_A8" "M0_A8" - U2 39 + RP18 6 +Net 405 "/sdram/M0_A8" "M0_A8" RP18 5 -Net 415 "/fpga2/M0_A7" "M0_A7" + U2 39 +Net 406 "/fpga2/M0_A7" "M0_A7" RP17 8 U2 38 -Net 416 "/fpga2/M0_A6" "M0_A6" +Net 407 "/fpga2/M0_A6" "M0_A6" RP17 7 U2 37 -Net 417 "/fpga2/M0_A5" "M0_A5" - U2 36 +Net 408 "/fpga2/M0_A5" "M0_A5" RP17 6 -Net 418 "/sdram/M0_A4" "M0_A4" - U2 35 + U2 36 +Net 409 "/fpga2/M0_A4" "M0_A4" RP17 5 -Net 419 "/fpga2/M0_A3" "M0_A3" + U2 35 +Net 410 "/fpga2/M0_A3" "M0_A3" RP14 5 U2 32 -Net 420 "/fpga2/M0_A2" "M0_A2" +Net 411 "/fpga2/M0_A2" "M0_A2" U2 31 RP14 6 -Net 421 "/fpga2/M0_A1" "M0_A1" +Net 412 "/fpga2/M0_A1" "M0_A1" U2 30 RP14 7 -Net 422 "/sdram/M0_A0" "M0_A0" - U2 29 +Net 413 "/fpga2/M0_A0" "M0_A0" RP14 8 -Net 423 "/sdram/M0_DQ15" "M0_DQ15" + U2 29 +Net 414 "/fpga2/M0_DQ15" "M0_DQ15" RP10 5 U2 65 -Net 424 "/fpga2/M0_DQ0" "M0_DQ0" - RP13 8 +Net 415 "/fpga2/M0_DQ0" "M0_DQ0" U2 2 -Net 425 "/sdram/M0_DQ1" "M0_DQ1" + RP13 8 +Net 416 "/fpga2/M0_DQ1" "M0_DQ1" U2 4 RP13 7 -Net 426 "/fpga2/M0_DQ2" "M0_DQ2" - RP13 6 +Net 417 "/sdram/M0_DQ2" "M0_DQ2" U2 5 -Net 427 "/fpga2/M0_DQ3" "M0_DQ3" + RP13 6 +Net 418 "/fpga2/M0_DQ3" "M0_DQ3" U2 7 RP13 5 -Net 428 "/sdram/M0_DQ4" "M0_DQ4" +Net 419 "/sdram/M0_DQ4" "M0_DQ4" U2 8 RP12 8 -Net 429 "/sdram/M0_DQ5" "M0_DQ5" +Net 420 "/fpga2/M0_DQ5" "M0_DQ5" U2 10 RP12 7 -Net 430 "/sdram/M0_DQ6" "M0_DQ6" - U2 11 +Net 421 "/sdram/M0_DQ6" "M0_DQ6" RP12 6 -Net 431 "/sdram/M0_DQ7" "M0_DQ7" - U2 13 + U2 11 +Net 422 "/fpga2/M0_DQ7" "M0_DQ7" RP12 5 -Net 432 "/sdram/M0_DQ8" "M0_DQ8" - U2 54 + U2 13 +Net 423 "/sdram/M0_DQ8" "M0_DQ8" RP11 8 -Net 433 "/fpga2/M0_DQ9" "M0_DQ9" + U2 54 +Net 424 "/sdram/M0_DQ9" "M0_DQ9" U2 56 RP11 7 -Net 434 "/fpga2/M0_DQ10" "M0_DQ10" - RP11 6 +Net 425 "/fpga2/M0_DQ10" "M0_DQ10" U2 57 -Net 435 "/fpga2/M0_DQ11" "M0_DQ11" + RP11 6 +Net 426 "/fpga2/M0_DQ11" "M0_DQ11" U2 59 RP11 5 -Net 436 "/fpga2/M0_DQ12" "M0_DQ12" - U2 60 +Net 427 "/fpga2/M0_DQ12" "M0_DQ12" RP10 8 -Net 437 "/sdram/M0_DQ13" "M0_DQ13" - U2 62 + U2 60 +Net 428 "/fpga2/M0_DQ13" "M0_DQ13" RP10 7 -Net 438 "/fpga2/M0_DQ14" "M0_DQ14" - RP10 6 + U2 62 +Net 429 "/fpga2/M0_DQ14" "M0_DQ14" U2 63 -Net 439 "/fpga2/M1_DQ6" "M1_DQ6" - U3 11 + RP10 6 +Net 430 "/sdram/M1_DQ6" "M1_DQ6" RP4 6 -Net 440 "/fpga2/M1_DQ7" "M1_DQ7" - RP4 5 + U3 11 +Net 431 "/sdram/M1_DQ7" "M1_DQ7" U3 13 -Net 441 "/fpga2/M1_DQ8" "M1_DQ8" - RP9 4 + RP4 5 +Net 432 "/fpga2/M1_DQ8" "M1_DQ8" U3 54 -Net 442 "/sdram/M1_DQ9" "M1_DQ9" + RP9 4 +Net 433 "/fpga2/M1_DQ9" "M1_DQ9" RP9 3 U3 56 -Net 443 "/fpga2/M1_DQ10" "M1_DQ10" +Net 434 "/fpga2/M1_DQ10" "M1_DQ10" U3 57 RP9 2 -Net 444 "/sdram/M1_DQ11" "M1_DQ11" +Net 435 "/sdram/M1_DQ11" "M1_DQ11" U3 59 RP9 1 -Net 445 "/fpga2/M1_DQ12" "M1_DQ12" - U3 60 +Net 436 "/fpga2/M1_DQ12" "M1_DQ12" RP8 4 -Net 446 "/fpga2/M1_DQ13" "M1_DQ13" + U3 60 +Net 437 "/fpga2/M1_DQ13" "M1_DQ13" U3 62 RP8 3 -Net 447 "/sdram/M1_DQ14" "M1_DQ14" - RP8 2 +Net 438 "/sdram/M1_DQ14" "M1_DQ14" U3 63 -Net 448 "/sdram/M1_DQ15" "M1_DQ15" - RP8 1 + RP8 2 +Net 439 "/fpga2/M1_DQ15" "M1_DQ15" U3 65 -Net 449 "/flash/NF_D2" "NF_D2" + RP8 1 +Net 440 "/fpga1/NF_D2" "NF_D2" U1 A13 U5 31 -Net 450 "/fpga1/NF_D1" "NF_D1" +Net 441 "/fpga1/NF_D1" "NF_D1" U1 D14 U5 30 -Net 451 "/fpga1/NF_D0" "NF_D0" +Net 442 "/fpga1/NF_D0" "NF_D0" U1 C12 U5 29 -Net 452 "/flash/SD_DAT3" "SD_DAT3" - J1 2 +Net 443 "/fpga1/SD_DAT3" "SD_DAT3" U1 B16 -Net 453 "/flash/SD_DAT2" "SD_DAT2" + J1 2 +Net 444 "/flash/SD_DAT2" "SD_DAT2" U1 A16 J1 1 -Net 454 "/flash/SD_DAT1" "SD_DAT1" - J1 8 +Net 445 "/fpga1/SD_DAT1" "SD_DAT1" U1 B18 -Net 455 "/fpga1/SD_DAT0" "SD_DAT0" - U1 A18 + J1 8 +Net 446 "/flash/SD_DAT0" "SD_DAT0" J1 7 -Net 456 "/sdram/M1_A12" "M1_A12" + U1 A18 +Net 447 "/fpga2/M1_A12" "M1_A12" RP7 1 U3 42 -Net 457 "/sdram/M1_A11" "M1_A11" - RP7 2 +Net 448 "/sdram/M1_A11" "M1_A11" U3 41 -Net 458 "/sdram/M1_A10" "M1_A10" + RP7 2 +Net 449 "/sdram/M1_A10" "M1_A10" U3 28 RP2 5 -Net 459 "/fpga2/M1_A0" "M1_A0" - U3 29 +Net 450 "/fpga2/M1_A0" "M1_A0" RP1 8 -Net 460 "/fpga2/M1_A1" "M1_A1" + U3 29 +Net 451 "/fpga2/M1_A1" "M1_A1" RP1 7 U3 30 -Net 461 "/fpga2/M1_A2" "M1_A2" +Net 452 "/fpga2/M1_A2" "M1_A2" U3 31 RP1 6 -Net 462 "/fpga2/M1_A3" "M1_A3" - RP1 5 +Net 453 "/sdram/M1_A3" "M1_A3" U3 32 -Net 463 "/fpga2/M1_A4" "M1_A4" + RP1 5 +Net 454 "/sdram/M1_A4" "M1_A4" U3 35 RP6 4 -Net 464 "/fpga2/M1_A5" "M1_A5" - RP6 3 +Net 455 "/fpga2/M1_A5" "M1_A5" U3 36 -Net 465 "/sdram/M1_A6" "M1_A6" - U3 37 + RP6 3 +Net 456 "/fpga2/M1_A6" "M1_A6" RP6 2 -Net 466 "/sdram/M1_A7" "M1_A7" + U3 37 +Net 457 "/fpga2/M1_A7" "M1_A7" RP6 1 U3 38 -Net 467 "/sdram/M1_A8" "M1_A8" - RP7 4 +Net 458 "/fpga2/M1_A8" "M1_A8" U3 39 -Net 468 "/sdram/M1_A9" "M1_A9" - RP7 3 + RP7 4 +Net 459 "/fpga2/M1_A9" "M1_A9" U3 40 -Net 470 "/expansion/FPGA_BANK0_IO_30" "FPGA_BANK0_IO_30" + RP7 3 +Net 461 "/fpga1/FPGA_BANK0_IO_30" "FPGA_BANK0_IO_30" U1 W14 P1 20 -Net 471 "/expansion/FPGA_BANK0_IO_29" "FPGA_BANK0_IO_29" - U1 AB16 +Net 462 "/fpga1/FPGA_BANK0_IO_29" "FPGA_BANK0_IO_29" P1 18 -Net 472 "/fpga1/FPGA_BANK0_IO_28" "FPGA_BANK0_IO_28" + U1 AB16 +Net 463 "/expansion/FPGA_BANK0_IO_28" "FPGA_BANK0_IO_28" P1 17 U1 AA16 -Net 473 "/expansion/FPGA_BANK0_IO_27" "FPGA_BANK0_IO_27" - U1 W13 +Net 464 "/expansion/FPGA_BANK0_IO_27" "FPGA_BANK0_IO_27" P1 21 -Net 475 "/fpga1/FPGA_BANK0_IO_25" "FPGA_BANK0_IO_25" + U1 W13 +Net 466 "/expansion/FPGA_BANK0_IO_25" "FPGA_BANK0_IO_25" P1 22 U1 W15 -Net 476 "/expansion/FPGA_BANK0_IO_24" "FPGA_BANK0_IO_24" - P1 16 +Net 467 "/fpga1/FPGA_BANK0_IO_24" "FPGA_BANK0_IO_24" U1 Y16 -Net 478 "/fpga1/FPGA_BANK0_IO_22" "FPGA_BANK0_IO_22" + P1 16 +Net 469 "/fpga1/FPGA_BANK0_IO_22" "FPGA_BANK0_IO_22" P1 19 U1 AA14 -Net 479 "/expansion/FPGA_BANK0_IO_21" "FPGA_BANK0_IO_21" +Net 470 "/expansion/FPGA_BANK0_IO_21" "FPGA_BANK0_IO_21" U1 AB17 P1 14 -Net 480 "/fpga1/FPGA_BANK0_IO_20" "FPGA_BANK0_IO_20" - P1 15 +Net 471 "/fpga1/FPGA_BANK0_IO_20" "FPGA_BANK0_IO_20" U1 Y17 -Net 482 "/fpga1/FPGA_BANK0_IO_18" "FPGA_BANK0_IO_18" + P1 15 +Net 473 "/expansion/FPGA_BANK0_IO_18" "FPGA_BANK0_IO_18" U1 AA18 P1 12 -Net 483 "/expansion/FPGA_BANK0_IO_17" "FPGA_BANK0_IO_17" +Net 474 "/expansion/FPGA_BANK0_IO_17" "FPGA_BANK0_IO_17" P1 13 U1 V15 -Net 484 "GND" "GND" - U2 6 - U4 8 - C20 2 - U2 64 - C18 2 - R12 2 - R14 2 - C22 2 +Net 475 "GND" "GND" + U4 39 + P1 3 + C10 2 + C11 2 + R2 2 + C12 2 + C5 2 + C3 2 + V4 2 + C77 2 + R9 2 + C8 2 + C7 2 + U1 AA13 + U1 AA17 + U7 7 + U1 U15 + U7 6 + C90 2 + C91 2 + C93 2 + L7 2 + C92 2 + C94 2 + C49 2 + C51 2 + C53 2 + V2 2 + C15 2 + U6 7 + U1 N17 + U6 6 + U1 D18 + C14 2 + U1 G18 + U1 L18 + U1 R18 + C13 2 + L5 2 + U1 W19 + U1 AA9 + U1 AB22 + C64 2 + C61 2 + C58 2 + C55 2 + R10 2 + C68 2 + C65 2 + C62 2 + R46 1 + R47 1 + C16 2 + C66 2 + C40 2 + C43 2 + C63 2 + C60 2 + C52 2 + C57 2 + C46 2 + C54 2 + C41 2 + C44 2 + C47 2 + C50 2 + C56 2 + C59 2 + C39 2 + C69 2 + C67 2 + C42 2 + C45 2 + C48 2 + U1 K10 + U1 M10 + U1 P10 + U1 V10 U1 K14 U1 M14 U1 P14 U1 V14 U1 E15 U1 J15 - R9 2 U1 N15 U1 AA5 U1 W16 @@ -3316,359 +3777,315 @@ Net 484 "GND" "GND" U1 M12 U1 P12 U1 A22 - U1 B13 - U1 J13 - U1 L13 - U1 N13 - C12 2 - C10 2 - C11 2 - R2 2 - U4 35 + J4 5 + J4 4 + R53 1 U1 E11 - U4 44 - U4 23 - U4 12 + R54 1 U1 J11 - C1 2 U1 L11 - C3 2 U1 N11 U1 E21 U1 J21 U1 N21 U1 U21 - C5 2 U1 AB1 - C90 2 U1 B9 U1 J9 - C7 2 U1 L9 U1 N9 - C8 2 - U1 K10 - U1 M10 - U1 P10 - U1 V10 - C2 2 - C4 2 - U2 52 - C6 2 - U2 12 - C9 2 - U2 66 - U3 58 - C34 2 - C71 2 - C70 2 - U2 34 - U2 24 - V1 2 - V4 2 - C37 2 - C36 2 - C35 2 - C76 2 - C77 2 - L7 2 - C69 2 - C67 2 - C64 2 - C61 2 - C16 2 - R10 2 - L5 2 - C13 2 - C14 2 - C15 2 - V2 2 - R47 1 - C52 2 - C43 2 - P1 3 - C40 2 - C48 2 - C45 2 - C42 2 - C39 2 - C59 2 - C56 2 - C50 2 - C47 2 - C44 2 - C41 2 - C53 2 - C51 2 - C49 2 - C58 2 - C55 2 - C68 2 - C65 2 - C62 2 - R15 2 - C38 2 - V3 2 - U7 7 - U7 6 - U6 6 - U6 7 - C66 2 - C63 2 - C60 2 - C57 2 - R46 1 - C54 2 - C46 2 - U1 E7 - U1 H7 - U1 U7 - U1 W7 - U4 39 - U1 A3 - U4 36 - J4 4 - C91 2 - U1 A1 - U1 E2 - U1 J2 - U1 N2 - U1 U2 U1 D4 U1 V4 U1 B5 U1 G5 U1 L5 U1 R5 - U1 D18 - U1 G18 - U1 L18 - U1 R18 - U1 W19 - U1 AA9 - U1 AB22 - U1 AA13 - U1 AA17 - U1 U15 - C92 2 - C94 2 - C93 2 - R53 1 - R54 1 - U1 N17 + U1 E7 + U1 H7 + U1 U7 + U1 W7 + C2 2 + C4 2 + C6 2 + C9 2 + V3 2 + U1 A3 + C76 2 + C37 2 + C38 2 + C36 2 + R15 2 + C35 2 + V1 2 + U1 B13 + U1 J13 + U1 L13 + U1 N13 + U1 A1 + U1 E2 + U1 J2 + U1 N2 + U1 U2 + U5 13 + U5 36 + C73 2 + C74 2 + C161 2 + R95 2 + C157 2 + U10 2 + U8 4 + U10 4 + C162 2 + R90 1 + C72 2 J1 CASE J1 CASE J1 CASE J1 COM - U3 6 - U3 64 - U2 48 - X2 2 - U3 34 J1 6 - U5 13 - U5 36 - U2 58 - C75 1 - C27 2 - C32 2 - C30 2 - C31 2 - C29 2 - C74 2 - C21 2 - J4 5 - C28 2 - C33 2 - C23 2 - C25 2 - C24 2 - C26 2 - U8 4 - U3 66 - C72 2 - C73 2 - C156 1 - U3 52 - U3 12 U3 48 -Net 485 "VCCO2" "VCCO2" - U1 AA11 - C156 2 - U1 AA15 - X2 4 - U1 V16 - U1 AA19 - U1 AA22 - U1 V12 - U1 W5 - U1 T9 - U1 V8 - U1 AA3 - U1 T13 - U1 AA7 - U8 8 - P1 5 - C55 1 + U3 58 + C169 2 + C25 2 + C167 2 + C23 2 + C160 2 + U3 52 + C33 2 + U3 34 + U3 64 + C70 2 + C71 2 + C34 2 + C27 2 + C21 2 + C26 2 + U3 66 + C24 2 + U3 6 + U3 12 + U2 58 + U2 48 + C28 2 + C29 2 + C31 2 + C30 2 + C32 2 + U9 5 + C20 2 + C18 2 + U2 64 + U2 66 + U2 12 + C165 2 + U2 52 + U2 24 + U2 34 + C158 2 + C173 2 + C163 1 + C172 2 + C75 1 + U2 6 + U11 4 + U11 5 + U9 1 + C22 2 + R14 2 + R12 2 + C171 2 + C174 2 + C159 2 + C170 2 + R89 1 + C168 2 + U4 12 + U4 35 + U4 44 + U4 23 + C1 2 + U4 8 + C156 1 + X2 2 + U4 36 +Net 476 "VCCO2" "VCCO2" C58 1 - C61 1 - C64 1 - C67 1 + C55 1 + U1 AA7 C69 1 -Net 486 "/expansion/FPGA_BANK0_IO_1" "FPGA_BANK0_IO_1" + C156 2 + U1 AA19 + U1 AA15 + P1 5 + U1 V8 + U1 T9 + C67 1 + C61 1 + U1 V12 + U1 AA22 + U1 V16 + X2 4 + U1 AA11 + U8 8 + C64 1 + U1 T13 + U1 AA3 + U1 W5 +Net 477 "/expansion/FPGA_BANK0_IO_1" "FPGA_BANK0_IO_1" U1 T18 P1 2 -Net 487 "/fpga1/FPGA_BANK0_IO_2" "FPGA_BANK0_IO_2" +Net 478 "/fpga1/FPGA_BANK0_IO_2" "FPGA_BANK0_IO_2" P1 25 U1 T17 -Net 488 "/expansion/FPGA_BANK0_IO_3" "FPGA_BANK0_IO_3" - P1 10 +Net 479 "/fpga1/FPGA_BANK0_IO_3" "FPGA_BANK0_IO_3" U1 Y19 -Net 490 "/expansion/FPGA_BANK0_IO_5" "FPGA_BANK0_IO_5" + P1 10 +Net 481 "/expansion/FPGA_BANK0_IO_5" "FPGA_BANK0_IO_5" U1 Y18 P1 11 -Net 491 "/fpga1/FPGA_BANK0_IO_6" "FPGA_BANK0_IO_6" - U1 T16 +Net 482 "/fpga1/FPGA_BANK0_IO_6" "FPGA_BANK0_IO_6" P1 28 -Net 492 "/fpga1/FPGA_BANK0_IO_7" "FPGA_BANK0_IO_7" + U1 T16 +Net 483 "/fpga1/FPGA_BANK0_IO_7" "FPGA_BANK0_IO_7" P1 27 U1 T15 -Net 493 "/expansion/FPGA_BANK0_IO_8" "FPGA_BANK0_IO_8" +Net 484 "/fpga1/FPGA_BANK0_IO_8" "FPGA_BANK0_IO_8" U1 U17 P1 1 -Net 494 "/expansion/FPGA_BANK0_IO_9" "FPGA_BANK0_IO_9" +Net 485 "/expansion/FPGA_BANK0_IO_9" "FPGA_BANK0_IO_9" U1 U16 P1 4 -Net 495 "/expansion/FPGA_BANK0_IO_10" "FPGA_BANK0_IO_10" +Net 486 "/fpga1/FPGA_BANK0_IO_10" "FPGA_BANK0_IO_10" U1 V19 P1 7 -Net 496 "/fpga1/FPGA_BANK0_IO_11" "FPGA_BANK0_IO_11" - U1 V18 +Net 487 "/fpga1/FPGA_BANK0_IO_11" "FPGA_BANK0_IO_11" P1 9 -Net 497 "/expansion/FPGA_BANK0_IO_12" "FPGA_BANK0_IO_12" + U1 V18 +Net 488 "/expansion/FPGA_BANK0_IO_12" "FPGA_BANK0_IO_12" P1 29 U1 R16 -Net 499 "/expansion/FPGA_BANK0_IO_14" "FPGA_BANK0_IO_14" +Net 490 "/fpga1/FPGA_BANK0_IO_14" "FPGA_BANK0_IO_14" U1 V17 P1 6 -Net 500 "/expansion/FPGA_BANK0_IO_15" "FPGA_BANK0_IO_15" +Net 491 "/expansion/FPGA_BANK0_IO_15" "FPGA_BANK0_IO_15" P1 8 U1 W17 -Net 502 "/expansion/FPGA_BANK0_IO_63" "FPGA_BANK0_IO_63" +Net 493 "/expansion/FPGA_BANK0_IO_63" "FPGA_BANK0_IO_63" U1 V5 P1 45 -Net 503 "/fpga1/FPGA_BANK0_IO_62" "FPGA_BANK0_IO_62" +Net 494 "/fpga1/FPGA_BANK0_IO_62" "FPGA_BANK0_IO_62" P1 46 U1 U6 -Net 505 "/expansion/FPGA_BANK0_IO_60" "FPGA_BANK0_IO_60" - U1 T7 +Net 496 "/fpga1/FPGA_BANK0_IO_60" "FPGA_BANK0_IO_60" P1 50 -Net 507 "/fpga1/FPGA_BANK0_IO_58" "FPGA_BANK0_IO_58" - U1 R9 + U1 T7 +Net 498 "/fpga1/FPGA_BANK0_IO_58" "FPGA_BANK0_IO_58" P1 49 -Net 508 "/expansion/FPGA_BANK0_IO_57" "FPGA_BANK0_IO_57" - U1 W6 + U1 R9 +Net 499 "/fpga1/FPGA_BANK0_IO_57" "FPGA_BANK0_IO_57" P1 48 -Net 509 "/fpga1/FPGA_BANK0_IO_56" "FPGA_BANK0_IO_56" + U1 W6 +Net 500 "/expansion/FPGA_BANK0_IO_56" "FPGA_BANK0_IO_56" U1 U10 P1 39 -Net 511 "/expansion/FPGA_BANK0_IO_54" "FPGA_BANK0_IO_54" +Net 502 "/expansion/FPGA_BANK0_IO_54" "FPGA_BANK0_IO_54" P1 43 U1 U8 -Net 512 "/expansion/FPGA_BANK0_IO_53" "FPGA_BANK0_IO_53" - U1 T8 +Net 503 "/expansion/FPGA_BANK0_IO_53" "FPGA_BANK0_IO_53" P1 47 -Net 513 "/fpga1/FPGA_BANK0_IO_52" "FPGA_BANK0_IO_52" + U1 T8 +Net 504 "/expansion/FPGA_BANK0_IO_52" "FPGA_BANK0_IO_52" U1 V9 P1 37 -Net 514 "/fpga1/FPGA_BANK0_IO_51" "FPGA_BANK0_IO_51" +Net 505 "/fpga1/FPGA_BANK0_IO_51" "FPGA_BANK0_IO_51" U1 U9 P1 41 -Net 515 "/fpga1/FPGA_BANK0_IO_50" "FPGA_BANK0_IO_50" - U1 W9 +Net 506 "/expansion/FPGA_BANK0_IO_50" "FPGA_BANK0_IO_50" P1 38 -Net 516 "/expansion/FPGA_BANK0_IO_49" "FPGA_BANK0_IO_49" + U1 W9 +Net 507 "/expansion/FPGA_BANK0_IO_49" "FPGA_BANK0_IO_49" U1 V7 P1 44 -Net 517 "/expansion/FPGA_BANK0_IO_32" "FPGA_BANK0_IO_32" +Net 508 "/expansion/FPGA_BANK0_IO_32" "FPGA_BANK0_IO_32" U1 Y15 P1 26 -Net 518 "/fpga1/FPGA_BANK0_IO_33" "FPGA_BANK0_IO_33" - U1 AB15 +Net 509 "/fpga1/FPGA_BANK0_IO_33" "FPGA_BANK0_IO_33" P1 24 -Net 519 "/expansion/FPGA_BANK0_IO_34" "FPGA_BANK0_IO_34" - U1 T12 + U1 AB15 +Net 510 "/fpga1/FPGA_BANK0_IO_34" "FPGA_BANK0_IO_34" P1 42 -Net 521 "/expansion/FPGA_BANK0_IO_36" "FPGA_BANK0_IO_36" - U1 T14 + U1 T12 +Net 512 "/expansion/FPGA_BANK0_IO_36" "FPGA_BANK0_IO_36" P1 30 -Net 523 "/expansion/FPGA_BANK0_IO_38" "FPGA_BANK0_IO_38" - X2 3 + U1 T14 +Net 514 "/expansion/FPGA_BANK0_IO_38" "FPGA_BANK0_IO_38" U1 Y13 -Net 524 "/expansion/FPGA_BANK0_IO_39" "FPGA_BANK0_IO_39" - U1 AB13 + X2 3 +Net 515 "/expansion/FPGA_BANK0_IO_39" "FPGA_BANK0_IO_39" P1 23 -Net 525 "/fpga1/FPGA_BANK0_IO_40" "FPGA_BANK0_IO_40" - P1 32 + U1 AB13 +Net 516 "/fpga1/FPGA_BANK0_IO_40" "FPGA_BANK0_IO_40" U1 Y11 -Net 528 "/expansion/FPGA_BANK0_IO_43" "FPGA_BANK0_IO_43" - U1 V11 + P1 32 +Net 519 "/expansion/FPGA_BANK0_IO_43" "FPGA_BANK0_IO_43" P1 34 -Net 529 "/fpga1/FPGA_BANK0_IO_44" "FPGA_BANK0_IO_44" - P1 31 + U1 V11 +Net 520 "/fpga1/FPGA_BANK0_IO_44" "FPGA_BANK0_IO_44" U1 W11 -Net 530 "/expansion/FPGA_BANK0_IO_45" "FPGA_BANK0_IO_45" + P1 31 +Net 521 "/fpga1/FPGA_BANK0_IO_45" "FPGA_BANK0_IO_45" P1 35 U1 Y9 -Net 531 "/expansion/FPGA_BANK0_IO_46" "FPGA_BANK0_IO_46" +Net 522 "/expansion/FPGA_BANK0_IO_46" "FPGA_BANK0_IO_46" P1 36 U1 W10 -Net 532 "/expansion/FPGA_BANK0_IO_47" "FPGA_BANK0_IO_47" - U1 Y10 +Net 523 "/fpga1/FPGA_BANK0_IO_47" "FPGA_BANK0_IO_47" P1 33 -Net 533 "/fpga1/FPGA_BANK0_IO_48" "FPGA_BANK0_IO_48" + U1 Y10 +Net 524 "/fpga1/FPGA_BANK0_IO_48" "FPGA_BANK0_IO_48" P1 40 U1 W8 -Net 534 "/fpga2/M1_DQ5" "M1_DQ5" +Net 525 "/fpga2/M1_DQ5" "M1_DQ5" RP4 7 U3 10 -Net 535 "/fpga2/M1_DQ4" "M1_DQ4" +Net 526 "/sdram/M1_DQ4" "M1_DQ4" U3 8 RP4 8 -Net 536 "/fpga2/M1_DQ3" "M1_DQ3" - U3 7 +Net 527 "/sdram/M1_DQ3" "M1_DQ3" RP5 5 -Net 537 "/sdram/M1_DQ2" "M1_DQ2" + U3 7 +Net 528 "/fpga2/M1_DQ2" "M1_DQ2" U3 5 RP5 6 -Net 538 "/sdram/M1_DQ1" "M1_DQ1" +Net 529 "/fpga2/M1_DQ1" "M1_DQ1" U3 4 RP5 7 -Net 539 "/sdram/M1_DQ0" "M1_DQ0" +Net 530 "/fpga2/M1_DQ0" "M1_DQ0" RP5 8 U3 2 -Net 540 "/fpga1/ETH_TXD3" "ETH_TXD3" - U1 A8 +Net 531 "/ether/ETH_TXD3" "ETH_TXD3" U4 20 -Net 541 "/fpga1/ETH_TXD2" "ETH_TXD2" - U1 C10 + U1 A8 +Net 532 "/ether/ETH_TXD2" "ETH_TXD2" U4 19 -Net 542 "/fpga1/ETH_TXD1" "ETH_TXD1" + U1 C10 +Net 533 "/fpga1/ETH_TXD1" "ETH_TXD1" U1 C9 U4 18 -Net 543 "/ether/ETH_RXD0" "ETH_RXD0" +Net 534 "/ether/ETH_RXD0" "ETH_RXD0" U4 6 U1 B6 -Net 544 "/fpga1/ETH_RXD1" "ETH_RXD1" +Net 535 "/fpga1/ETH_RXD1" "ETH_RXD1" U1 A5 U4 5 -Net 545 "/fpga1/ETH_RXD2" "ETH_RXD2" +Net 536 "/ether/ETH_RXD2" "ETH_RXD2" U4 4 U1 C6 -Net 546 "/fpga1/ETH_RXD3" "ETH_RXD3" +Net 537 "/ether/ETH_RXD3" "ETH_RXD3" U4 3 U1 C5 -Net 547 "/fpga1/ETH_TXD0" "ETH_TXD0" +Net 538 "/ether/ETH_TXD0" "ETH_TXD0" U4 17 U1 D10 } diff --git a/xue-rnc/xue-rnc.pro b/xue-rnc/xue-rnc.pro index f7734e5..a00b655 100644 --- a/xue-rnc/xue-rnc.pro +++ b/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Thu 23 Dec 2010 05:39:53 PM COT +update=Sun 26 Dec 2010 07:07:39 PM COT version=1 last_client=pcbnew [common] @@ -150,6 +150,6 @@ LibName29=../modules/DFN10 LibName30=../modules/MLF16 LibName31=../modules/USBD LibName32=../modules/MLP6 -LibName33=/home/afc/devel/Qi/xue/modules/MINI-SO-8 -LibName34=/home/afc/devel/Qi/xue/modules/SON008V5060 -LibName35=/home/afc/devel/Qi/xue/modules/UDFN6 +LibName33=../modules/MINI-SO-8 +LibName34=../modules/SON008V5060 +LibName35=../modules/UDFN6 diff --git a/xue-rnc/xue-rnc.pro~ b/xue-rnc/xue-rnc.pro~ new file mode 100644 index 0000000..a6b4895 --- /dev/null +++ b/xue-rnc/xue-rnc.pro~ @@ -0,0 +1,155 @@ +update=Sun 26 Dec 2010 05:58:24 PM COT +version=1 +last_client=pcbnew +[common] +NetDir= +[eeschema] +version=1 +LibDir= +NetFmt=1 +HPGLSpd=20 +HPGLDm=15 +HPGLNum=1 +offX_A4=0 +offY_A4=0 +offX_A3=0 +offY_A3=0 +offX_A2=0 +offY_A2=0 +offX_A1=0 +offY_A1=0 +offX_A0=0 +offY_A0=0 +offX_A=0 +offY_A=0 +offX_B=0 +offY_B=0 +offX_C=0 +offY_C=0 +offX_D=0 +offY_D=0 +offX_E=0 +offY_E=0 +RptD_X=0 +RptD_Y=100 +RptLab=1 +LabSize=40 +PrintMonochrome=1 +ShowSheetReferenceAndTitleBlock=1 +[eeschema/libraries] +LibName1=power +LibName2=../components/r_pack2 +LibName3=../components/v0402mhs03 +LibName4=../components/usb-48204-0001 +LibName5=../components/microsmd075f +LibName6=../components/mic2550 +LibName7=../components/rj45-48025 +LibName8=../components/xue-nv +LibName9=../components/xc6slx75fgg484 +LibName10=../components/xc6slx45fgg484 +LibName11=../components/micron_mobile_ddr +LibName12=../components/micron_ddr_512Mb +LibName13=../components/k8001 +LibName14=device +LibName15=transistors +LibName16=conn +LibName17=linear +LibName18=regul +LibName19=74xx +LibName20=cmos4000 +LibName21=adc-dac +LibName22=memory +LibName23=xilinx +LibName24=special +LibName25=microcontrollers +LibName26=dsp +LibName27=microchip +LibName28=analog_switches +LibName29=motorola +LibName30=texas +LibName31=intel +LibName32=audio +LibName33=interface +LibName34=digital-audio +LibName35=philips +LibName36=display +LibName37=cypress +LibName38=siliconi +LibName39=opto +LibName40=atmel +LibName41=contrib +LibName42=valves +LibName43=../components/pasives-connectors +LibName44=../components/x25x64mb +LibName45=../components/attiny +LibName46=../components/PSU +LibName47=../components/tps793xx +LibName48=../components/reg102 +LibName49=../components/mt9m033 +LibName50=../components/m12-tu400a +LibName51=../components/ft2232c +LibName52=../components/fxo-hc536r +LibName53=../components/zx62d-b-5p8 +LibName54=../components/a7130 +[general] +version=1 +[cvpcb] +version=1 +NetIExt=net +[cvpcb/libraries] +EquName1=devcms +[pcbnew] +version=1 +PadDrlX=0 +PadDimH=196 +PadDimV=393 +BoardThickness=630 +SgPcb45=1 +TxtPcbV=591 +TxtPcbH=394 +TxtModV=600 +TxtModH=600 +TxtModW=120 +VEgarde=100 +DrawLar=150 +EdgeLar=150 +TxtLar=120 +MSegLar=59 +LastNetListRead=xue-rnc.net +[pcbnew/libraries] +LibDir= +LibName1=../modules/stdpass +LibName2=../modules/SD-48025 +LibName3=../modules/USB-48204 +LibName4=../modules/TSSOP-14 +LibName5=../modules/SMB-0402 +LibName6=../modules/SD-48025 +LibName7=../modules/MICROSD-500901 +LibName8=sockets +LibName9=connect +LibName10=discret +LibName11=pin_array +LibName12=divers +LibName13=libcms +LibName14=display +LibName15=valves +LibName16=led +LibName17=dip_sockets +LibName18=../modules/90vfbga_mobile_ddr +LibName19=../modules/FGG484bga-p10 +LibName20=../modules/LQFP48 +LibName21=../modules/48TSOP-NAND +LibName22=../modules/micro-sd +LibName23=../modules/60fbga_ddr +LibName24=../modules/66-tsop +LibName25=../modules/stdpass +LibName26=../modules/R_PACK4-0402 +LibName27=../modules/R_PACK2-0402 +LibName28=../modules/MLF20m1 +LibName29=../modules/DFN10 +LibName30=../modules/MLF16 +LibName31=../modules/USBD +LibName32=../modules/MLP6 +LibName33=/home/afc/devel/Qi/xue/modules/MINI-SO-8 +LibName34=/home/afc/devel/Qi/xue/modules/SON008V5060 +LibName35=/home/afc/devel/Qi/xue/modules/UDFN6 diff --git a/xue-rnc/xue-rnc.sch b/xue-rnc/xue-rnc.sch index 4a90724..4161e2f 100644 --- a/xue-rnc/xue-rnc.sch +++ b/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Sun 26 Dec 2010 05:23:16 PM COT +EESchema Schematic File Version 2 date Sun 26 Dec 2010 07:06:53 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -58,7 +58,7 @@ EELAYER END $Descr A3 16535 11700 Sheet 1 9 Title "" -Date "26 dec 2010" +Date "27 dec 2010" Rev "" Comp "" Comment1 ""