diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index 21f11f8..a8bfc8b 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:11:18 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -500,37 +500,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR9 +L GND #PWR018 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR9" H 6900 6200 30 0001 C CNN +F 0 "#PWR018" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR8 +L +2.5V #PWR019 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR8" H 6900 5750 20 0001 C CNN +F 0 "#PWR019" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR1 +L +2.5V #PWR020 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR1" H 1700 5750 20 0001 C CNN +F 0 "#PWR020" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR2 +L GND #PWR021 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR2" H 1700 6200 30 0001 C CNN +F 0 "#PWR021" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -546,19 +546,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR4 +L +2.5V #PWR022 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR4" H 3050 1700 20 0001 C CNN +F 0 "#PWR022" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR11 +L +2.5V #PWR023 U 1 1 4C61CFC6 P 8300 1750 -F 0 "#PWR11" H 8300 1700 20 0001 C CNN +F 0 "#PWR023" H 8300 1700 20 0001 C CNN F 1 "+2.5V" H 8300 1850 30 0000 C CNN 1 8300 1750 1 0 0 -1 @@ -624,37 +624,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR12 +L +2.5V #PWR024 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR12" H 8300 5700 20 0001 C CNN +F 0 "#PWR024" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR13 +L GND #PWR025 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR13" H 8300 6350 30 0001 C CNN +F 0 "#PWR025" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR6 +L GND #PWR026 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR6" H 3050 6350 30 0001 C CNN +F 0 "#PWR026" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR5 +L +2.5V #PWR027 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR5" H 3050 5700 20 0001 C CNN +F 0 "#PWR027" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -740,19 +740,19 @@ F 2 "0402" H 9850 1850 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR14 +L +2.5V #PWR028 U 1 1 4C61CE2F P 9850 1000 -F 0 "#PWR14" H 9850 950 20 0001 C CNN +F 0 "#PWR028" H 9850 950 20 0001 C CNN F 1 "+2.5V" H 9850 1100 30 0000 C CNN 1 9850 1000 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR7 +L +2.5V #PWR029 U 1 1 4C61CDF1 P 4550 900 -F 0 "#PWR7" H 4550 850 20 0001 C CNN +F 0 "#PWR029" H 4550 850 20 0001 C CNN F 1 "+2.5V" H 4550 1000 30 0000 C CNN 1 4550 900 1 0 0 -1 @@ -844,10 +844,10 @@ $EndComp Text HLabel 4950 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR3 +L GND #PWR030 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR3" H 3000 5200 30 0001 C CNN +F 0 "#PWR030" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1141,10 +1141,10 @@ Entry Wire Line Entry Wire Line 9950 3650 10050 3750 $Comp -L GND #PWR10 +L GND #PWR031 U 1 1 4C437C3F P 8250 5200 -F 0 "#PWR10" H 8250 5200 30 0001 C CNN +F 0 "#PWR031" H 8250 5200 30 0001 C CNN F 1 "GND" H 8250 5130 30 0001 C CNN 1 8250 5200 1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 1f34956..0d29eea 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:11:18 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -854,46 +854,46 @@ ETH_COL Text HLabel 14150 10650 0 60 BiDi ~ 0 ETH_CRS $Comp -L +3.3V #PWR24 +L +3.3V #PWR07 U 1 1 4C61E5B3 P 15850 8200 -F 0 "#PWR24" H 15850 8160 30 0001 C CNN +F 0 "#PWR07" H 15850 8160 30 0001 C CNN F 1 "+3.3V" H 15850 8310 30 0000 C CNN 1 15850 8200 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR23 +L +1.2V #PWR08 U 1 1 4C61E58C P 14050 12900 -F 0 "#PWR23" H 14050 13040 20 0001 C CNN +F 0 "#PWR08" H 14050 13040 20 0001 C CNN F 1 "+1.2V" H 14050 13010 30 0000 C CNN 1 14050 12900 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR21 +L +2.5V #PWR09 U 1 1 4C61E577 P 12550 12900 -F 0 "#PWR21" H 12550 12850 20 0001 C CNN +F 0 "#PWR09" H 12550 12850 20 0001 C CNN F 1 "+2.5V" H 12550 13000 30 0000 C CNN 1 12550 12900 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR25 +L +2.5V #PWR010 U 1 1 4C61E523 P 16000 600 -F 0 "#PWR25" H 16000 550 20 0001 C CNN +F 0 "#PWR010" H 16000 550 20 0001 C CNN F 1 "+2.5V" H 16000 700 30 0000 C CNN 1 16000 600 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR19 +L +2.5V #PWR011 U 1 1 4C61E51F P 5300 650 -F 0 "#PWR19" H 5300 600 20 0001 C CNN +F 0 "#PWR011" H 5300 600 20 0001 C CNN F 1 "+2.5V" H 5300 750 30 0000 C CNN 1 5300 650 1 0 0 -1 @@ -939,19 +939,19 @@ M0_BA[0..1] Text HLabel 12400 4850 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR20 +L GND #PWR012 U 1 1 4C60C24F P 12550 5100 -F 0 "#PWR20" H 12550 5100 30 0001 C CNN +F 0 "#PWR012" H 12550 5100 30 0001 C CNN F 1 "GND" H 12550 5030 30 0001 C CNN 1 12550 5100 -1 0 0 -1 $EndComp $Comp -L GND #PWR18 +L GND #PWR013 U 1 1 4C60C21D P 1600 5950 -F 0 "#PWR18" H 1600 5950 30 0001 C CNN +F 0 "#PWR013" H 1600 5950 30 0001 C CNN F 1 "GND" H 1600 5880 30 0001 C CNN 1 1600 5950 -1 0 0 -1 @@ -1427,10 +1427,10 @@ M0_CLK Text HLabel 7750 4700 2 60 Output ~ 0 M0_CLK# $Comp -L GND #PWR22 +L GND #PWR014 U 1 1 4C439B7E P 13950 15700 -F 0 "#PWR22" H 13950 15700 30 0001 C CNN +F 0 "#PWR014" H 13950 15700 30 0001 C CNN F 1 "GND" H 13950 15630 30 0001 C CNN 1 13950 15700 -1 0 0 -1 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index c8b8472..2fccd0d 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:11:18 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -231,10 +231,10 @@ SD_DAT3 Text Label 2800 5850 0 30 ~ 0 SD_CMD $Comp -L GND #PWR15 +L GND #PWR015 U 1 1 4C61D875 P 3050 6150 -F 0 "#PWR15" H 3050 6150 30 0001 C CNN +F 0 "#PWR015" H 3050 6150 30 0001 C CNN F 1 "GND" H 3050 6080 30 0001 C CNN 1 3050 6150 1 0 0 -1 @@ -246,19 +246,19 @@ SD_DAT0 Text Label 2800 5600 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR17 +L GND #PWR016 U 1 1 4C438ADC P 4400 5950 -F 0 "#PWR17" H 4400 5950 30 0001 C CNN +F 0 "#PWR016" H 4400 5950 30 0001 C CNN F 1 "GND" H 4400 5880 30 0001 C CNN 1 4400 5950 1 0 0 -1 $EndComp $Comp -L GND #PWR16 +L GND #PWR017 U 1 1 4C438AD5 P 3950 6300 -F 0 "#PWR16" H 3950 6300 30 0001 C CNN +F 0 "#PWR017" H 3950 6300 30 0001 C CNN F 1 "GND" H 3950 6230 30 0001 C CNN 1 3950 6300 1 0 0 -1 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index e08acc1..6f07d4a 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:11:18 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -55,6 +55,10 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Text Notes 2800 1000 0 60 ~ 0 +? +Wire Wire Line + 2800 1050 2800 1300 Wire Wire Line 4550 3050 4550 2950 Wire Wire Line @@ -165,19 +169,19 @@ Wire Wire Line Wire Wire Line 4550 3650 4550 3700 $Comp -L GND #PWR30 +L GND #PWR01 U 1 1 4C63F2B5 P 4550 3700 -F 0 "#PWR30" H 4550 3700 30 0001 C CNN +F 0 "#PWR01" H 4550 3700 30 0001 C CNN F 1 "GND" H 4550 3630 30 0001 C CNN 1 4550 3700 1 0 0 -1 $EndComp $Comp -L +5V #PWR29 +L +5V #PWR02 U 1 1 4C63F295 P 4350 1350 -F 0 "#PWR29" H 4350 1440 20 0001 C CNN +F 0 "#PWR02" H 4350 1440 20 0001 C CNN F 1 "+5V" H 4350 1440 30 0000 C CNN 1 4350 1350 1 0 0 -1 @@ -207,37 +211,37 @@ Warning!! VIF = 2.5!! ToDo: review the DS\n Text GLabel 2500 2400 3 40 BiDi ~ 0 3.3V $Comp -L +2.5V #PWR26 +L +2.5V #PWR03 U 1 1 4C63EC16 P 1550 2450 -F 0 "#PWR26" H 1550 2400 20 0001 C CNN +F 0 "#PWR03" H 1550 2400 20 0001 C CNN F 1 "+2.5V" H 1550 2550 30 0000 C CNN 1 1550 2450 1 0 0 -1 $EndComp $Comp -L GND #PWR28 +L GND #PWR04 U 1 1 4C63EA2A P 2800 1850 -F 0 "#PWR28" H 2800 1850 30 0001 C CNN +F 0 "#PWR04" H 2800 1850 30 0001 C CNN F 1 "GND" H 2800 1780 30 0001 C CNN 1 2800 1850 1 0 0 -1 $EndComp $Comp -L GND #PWR27 +L GND #PWR05 U 1 1 4C63EA1B P 2150 3800 -F 0 "#PWR27" H 2150 3800 30 0001 C CNN +F 0 "#PWR05" H 2150 3800 30 0001 C CNN F 1 "GND" H 2150 3730 30 0001 C CNN 1 2150 3800 1 0 0 -1 $EndComp $Comp -L GND #PWR31 +L GND #PWR06 U 1 1 4C63E9FA P 5600 3750 -F 0 "#PWR31" H 5600 3750 30 0001 C CNN +F 0 "#PWR06" H 5600 3750 30 0001 C CNN F 1 "GND" H 5600 3680 30 0001 C CNN 1 5600 3750 1 0 0 -1 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index a7035e2..59a5ddd 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:11:18 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 0e52a14..59d797c 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Thu 12 Aug 2010 08:11:18 AM COT +EESchema-LIBRARY Version 2.3 Date: Thu 12 Aug 2010 08:51:39 AM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index ebf478b..a16d853 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,22 +1,26 @@ -PCBNEW-BOARD Version 1 date Tue 10 Aug 2010 09:13:52 PM COT +PCBNEW-BOARD Version 1 date Thu 12 Aug 2010 12:06:58 PM COT + +# Created by Pcbnew(2010-07-15 BZR 2414)-unstable $GENERAL LayerCount 4 Ly 1FFF8007 -Links 420 -NoConn 420 -Di 41429 -2230 85564 44550 -Ndraw 0 +EnabledLayers 1FFF8007 +Links 423 +NoConn 423 +Di 44325 10878 68579 39600 +Ndraw 2 Ntrack 0 Nzone 0 -Nmodule 63 -Nnets 144 +BoardThickness 630 +Nmodule 65 +Nnets 150 $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "11 aug 2010" +Date "12 aug 2010" Rev "" Comp "" Comment1 "" @@ -34,20 +38,20 @@ Layer[1] Inner2 signal Layer[2] Inner3 signal Layer[15] Front signal TrackWidth 80 -TrackWidthHistory 80 -TrackWidthHistory 170 TrackClearence 100 ZoneClearence 200 +TrackMinWidth 80 DrawSegmWidth 150 EdgeSegmWidth 150 ViaSize 350 ViaDrill 250 -ViaAltDrill 250 -ViaSizeHistory 350 -ViaSizeHistory 450 +ViaMinSize 350 +ViaMinDrill 200 MicroViaSize 200 MicroViaDrill 50 MicroViasAllowed 0 +MicroViaMinSize 200 +MicroViaMinDrill 50 TextPcbWidth 120 TextPcbSize 600 800 EdgeModWidth 150 @@ -55,6 +59,7 @@ TextModSize 600 600 TextModWidth 120 PadSize 600 600 PadDrill 320 +Pad2MaskClearance 100 AuxiliaryAxisOrg 0 0 $EndSETUP @@ -63,577 +68,761 @@ Na 0 "" St ~ $EndEQUIPOT $EQUIPOT -Na 1 "GND" +Na 1 "+1.2V" St ~ $EndEQUIPOT $EQUIPOT -Na 2 "/FPGA_Spartan6/ETH_INT" +Na 2 "+2.5V" St ~ $EndEQUIPOT $EQUIPOT -Na 3 "/FPGA_Spartan6/ETH_RXD3" +Na 3 "+3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 4 "/FPGA_Spartan6/ETH_RXD1" +Na 4 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/FPGA_Spartan6/ETH_RXDV" +Na 5 "/DDR_Banks/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/FPGA_Spartan6/ETH_TXD0" +Na 6 "/DDR_Banks/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/FPGA_Spartan6/ETH_CLK" +Na 7 "/DDR_Banks/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/Non_volatile_memories/SD_DAT3" +Na 8 "/DDR_Banks/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/Non_volatile_memories/SD_CLK" +Na 9 "/DDR_Banks/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/FPGA_Spartan6/USBA_VM" +Na 10 "/DDR_Banks/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/FPGA_Spartan6/USBA_RCV" +Na 11 "/DDR_Banks/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "+3.3V" +Na 12 "/DDR_Banks/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/FPGA_Spartan6/ETH_RESET_N" +Na 13 "/DDR_Banks/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/FPGA_Spartan6/ETH_RXD0" +Na 14 "/DDR_Banks/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/FPGA_Spartan6/ETH_RXC" +Na 15 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/Non_volatile_memories/SD_DAT0" +Na 16 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/FPGA_Spartan6/USBA_VP" +Na 17 "/DDR_Banks/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_A11" +Na 18 "/DDR_Banks/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "+2.5V" +Na 19 "/DDR_Banks/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/FPGA_Spartan6/ETH_MDIO" +Na 20 "/DDR_Banks/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/FPGA_Spartan6/ETH_RXD2" +Na 21 "/DDR_Banks/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/FPGA_Spartan6/ETH_TXER" +Na 22 "/DDR_Banks/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/FPGA_Spartan6/ETH_TXEN" +Na 23 "/DDR_Banks/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/FPGA_Spartan6/ETH_TXC" +Na 24 "/DDR_Banks/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/Non_volatile_memories/SD_DAT1" +Na 25 "/DDR_Banks/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/Non_volatile_memories/SD_CMD" +Na 26 "/DDR_Banks/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_A8" +Na 27 "/DDR_Banks/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_A9" +Na 28 "/DDR_Banks/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M0_A12" +Na 29 "/DDR_Banks/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M0_CKE" +Na 30 "/DDR_Banks/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/FPGA_Spartan6/ETH_MDC" +Na 31 "/DDR_Banks/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/FPGA_Spartan6/ETH_TXD1" +Na 32 "/DDR_Banks/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/FPGA_Spartan6/ETH_TXD2" +Na 33 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/FPGA_Spartan6/ETH_RXER" +Na 34 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/FPGA_Spartan6/ETH_TXD3" +Na 35 "/Ethernet_Phy/ETH_1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/Non_volatile_memories/SD_DAT2" +Na 36 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/FPGA_Spartan6/USBA_SPD" +Na 37 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M1_CKE" +Na 38 "/Ethernet_Phy/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/DDR_Banks/M1_A12" +Na 39 "/Ethernet_Phy/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/DDR_Banks/M0_A9" +Na 40 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/DDR_Banks/M0_A8" +Na 41 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/FPGA_Spartan6/USBA_OE_N" +Na 42 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/DDR_Banks/M1_A7" +Na 43 "/Ethernet_Phy/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/DDR_Banks/M1_A2" +Na 44 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/DDR_Banks/M0_WE#" +Na 45 "/Ethernet_Phy/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/DDR_Banks/M0_A4" +Na 46 "/Ethernet_Phy/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/DDR_Banks/M1_A11" +Na 47 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/DDR_Banks/M1_A4" +Na 48 "/Ethernet_Phy/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/DDR_Banks/M1_A0" +Na 49 "/Ethernet_Phy/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/DDR_Banks/M1_A1" +Na 50 "/Ethernet_Phy/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/DDR_Banks/M0_BA1" +Na 51 "/Ethernet_Phy/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/DDR_Banks/M0_BA0" +Na 52 "/Ethernet_Phy/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/DDR_Banks/M0_A10" +Na 53 "/Ethernet_Phy/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/DDR_Banks/M1_A10" +Na 54 "/Ethernet_Phy/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/DDR_Banks/M1_A3" +Na 55 "/FPGA_Spartan6/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/DDR_Banks/M0_A1" +Na 56 "/FPGA_Spartan6/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/DDR_Banks/M0_A0" +Na 57 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/DDR_Banks/M0_CLK#" +Na 58 "/FPGA_Spartan6/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/DDR_Banks/M0_CLK" +Na 59 "/FPGA_Spartan6/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/DDR_Banks/M0_A2" +Na 60 "/FPGA_Spartan6/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/DDR_Banks/M0_A7" +Na 61 "/FPGA_Spartan6/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/DDR_Banks/M1_WE#" +Na 62 "/FPGA_Spartan6/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/DDR_Banks/M1_CLK" +Na 63 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/DDR_Banks/M1_RAS#" +Na 64 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/DDR_Banks/M1_CAS#" +Na 65 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/DDR_Banks/M0_DQ5" +Na 66 "/FPGA_Spartan6/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/DDR_Banks/M0_DQ4" +Na 67 "/FPGA_Spartan6/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/DDR_Banks/M0_A6" +Na 68 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "+1.2V" +Na 69 "/FPGA_Spartan6/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/DDR_Banks/M1_BA0" +Na 70 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/DDR_Banks/M1_CLK#" +Na 71 "/FPGA_Spartan6/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/DDR_Banks/M1_DQ4" +Na 72 "/FPGA_Spartan6/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/DDR_Banks/M1_DQ5" +Na 73 "/FPGA_Spartan6/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/DDR_Banks/M0_DQ7" +Na 74 "/FPGA_Spartan6/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/DDR_Banks/M0_DQ6" +Na 75 "/FPGA_Spartan6/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/DDR_Banks/M0_A5" +Na 76 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/DDR_Banks/M0_CAS#" +Na 77 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/DDR_Banks/M0_RAS#" +Na 78 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/DDR_Banks/M0_A3" +Na 79 "/FPGA_Spartan6/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/DDR_Banks/M1_BA1" +Na 80 "/FPGA_Spartan6/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/DDR_Banks/M1_A6" +Na 81 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/DDR_Banks/M1_A5" +Na 82 "/FPGA_Spartan6/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/DDR_Banks/M1_DQ6" +Na 83 "/FPGA_Spartan6/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/DDR_Banks/M1_DQ7" +Na 84 "/FPGA_Spartan6/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/DDR_Banks/M0_LDQS" +Na 85 "/FPGA_Spartan6/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/DDR_Banks/M0_LDM" +Na 86 "/FPGA_Spartan6/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/DDR_Banks/M1_LDM" +Na 87 "/FPGA_Spartan6/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/DDR_Banks/M1_LDQS" +Na 88 "/FPGA_Spartan6/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/DDR_Banks/M0_DQ3" +Na 89 "/FPGA_Spartan6/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/DDR_Banks/M0_DQ2" +Na 90 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/DDR_Banks/M0_UDM" +Na 91 "/FPGA_Spartan6/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/DDR_Banks/M1_UDM" +Na 92 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/DDR_Banks/M1_DQ2" +Na 93 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/DDR_Banks/M1_DQ3" +Na 94 "/FPGA_Spartan6/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/DDR_Banks/M0_DQ1" +Na 95 "/FPGA_Spartan6/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/DDR_Banks/M0_DQ0" +Na 96 "/FPGA_Spartan6/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/DDR_Banks/M1_DQ0" +Na 97 "/FPGA_Spartan6/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/DDR_Banks/M1_DQ1" +Na 98 "/FPGA_Spartan6/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/DDR_Banks/M0_DQ9" +Na 99 "/FPGA_Spartan6/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/DDR_Banks/M0_DQ8" +Na 100 "/FPGA_Spartan6/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/DDR_Banks/M1_DQ8" +Na 101 "/FPGA_Spartan6/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/DDR_Banks/M1_DQ9" +Na 102 "/FPGA_Spartan6/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/DDR_Banks/M0_DQ11" +Na 103 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/DDR_Banks/M0_DQ10" +Na 104 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/DDR_Banks/M1_DQ10" +Na 105 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/DDR_Banks/M1_DQ11" +Na 106 "/FPGA_Spartan6/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/DDR_Banks/M0_UDQS" +Na 107 "/FPGA_Spartan6/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "N-000101" +Na 108 "/FPGA_Spartan6/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/DDR_Banks/M1_UDQS" +Na 109 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/DDR_Banks/M0_DQ13" +Na 110 "/FPGA_Spartan6/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/DDR_Banks/M0_DQ12" +Na 111 "/FPGA_Spartan6/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/DDR_Banks/M1_DQ12" +Na 112 "/FPGA_Spartan6/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/DDR_Banks/M1_DQ13" +Na 113 "/FPGA_Spartan6/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/DDR_Banks/M0_DQ15" +Na 114 "/FPGA_Spartan6/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/DDR_Banks/M0_DQ14" +Na 115 "/FPGA_Spartan6/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/DDR_Banks/M1_DQ14" +Na 116 "/FPGA_Spartan6/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/DDR_Banks/M1_DQ15" +Na 117 "/FPGA_Spartan6/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "N-000069" +Na 118 "/Non_volatile_memories/FRB_N" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/Ethernet_Phy/ETH_PLL1.8V" +Na 119 "/Non_volatile_memories/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "N-000345" +Na 120 "/Non_volatile_memories/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "N-000340" +Na 121 "/Non_volatile_memories/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/Ethernet_Phy/ETH_A3.3V" +Na 122 "/Non_volatile_memories/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "N-000338" +Na 123 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/Ethernet_Phy/ETH_LED0" +Na 124 "/USB/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/Ethernet_Phy/ETH_LED1" +Na 125 "/USB/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/Ethernet_Phy/ETH_A1.8V" +Na 126 "3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "N-000339" +Na 127 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "N-000346" +Na 128 "N-000043" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/Ethernet_Phy/ETH_1.8V" +Na 129 "N-000044" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/Non_volatile_memories/FRB_N" +Na 130 "N-000045" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "N-000347" +Na 131 "N-000047" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "N-000343" +Na 132 "N-000101" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "N-000342" +Na 133 "N-000334" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "N-000360" +Na 134 "N-000335" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "N-000361" +Na 135 "N-000336" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "N-000047" +Na 136 "N-000337" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "N-000046" +Na 137 "N-000338" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "N-000363" +Na 138 "N-000344" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "N-000349" +Na 139 "N-000345" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "N-000348" +Na 140 "N-000346" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "N-000362" +Na 141 "N-000347" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "N-000045" +Na 142 "N-000350" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "N-000048" +Na 143 "N-000356" St ~ $EndEQUIPOT +$EQUIPOT +Na 144 "N-000357" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 145 "N-000358" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 146 "N-000360" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 147 "N-000361" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 148 "N-000362" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 149 "N-000363" +St ~ +$EndEQUIPOT +$NCLASS +Name "Default" +Desc "This is the default net class." +Clearance 100 +TrackWidth 80 +ViaDia 350 +ViaDrill 250 +uViaDia 200 +uViaDrill 50 +AddNet "" +AddNet "+1.2V" +AddNet "+2.5V" +AddNet "+3.3V" +AddNet "+5V" +AddNet "/DDR_Banks/M0_A10" +AddNet "/DDR_Banks/M0_A5" +AddNet "/DDR_Banks/M0_A7" +AddNet "/DDR_Banks/M0_BA0" +AddNet "/DDR_Banks/M0_CLK" +AddNet "/DDR_Banks/M0_DQ10" +AddNet "/DDR_Banks/M0_DQ13" +AddNet "/DDR_Banks/M0_DQ5" +AddNet "/DDR_Banks/M0_DQ6" +AddNet "/DDR_Banks/M0_DQ9" +AddNet "/DDR_Banks/M0_LDM" +AddNet "/DDR_Banks/M0_LDQS" +AddNet "/DDR_Banks/M0_UDM" +AddNet "/DDR_Banks/M0_UDQS" +AddNet "/DDR_Banks/M1_A10" +AddNet "/DDR_Banks/M1_A11" +AddNet "/DDR_Banks/M1_A4" +AddNet "/DDR_Banks/M1_A5" +AddNet "/DDR_Banks/M1_A6" +AddNet "/DDR_Banks/M1_A9" +AddNet "/DDR_Banks/M1_BA0" +AddNet "/DDR_Banks/M1_CAS#" +AddNet "/DDR_Banks/M1_CKE" +AddNet "/DDR_Banks/M1_DQ0" +AddNet "/DDR_Banks/M1_DQ13" +AddNet "/DDR_Banks/M1_DQ3" +AddNet "/DDR_Banks/M1_DQ5" +AddNet "/DDR_Banks/M1_DQ6" +AddNet "/DDR_Banks/M1_LDM" +AddNet "/DDR_Banks/M1_RAS#" +AddNet "/Ethernet_Phy/ETH_1.8V" +AddNet "/Ethernet_Phy/ETH_A1.8V" +AddNet "/Ethernet_Phy/ETH_A3.3V" +AddNet "/Ethernet_Phy/ETH_COL" +AddNet "/Ethernet_Phy/ETH_CRS" +AddNet "/Ethernet_Phy/ETH_INT" +AddNet "/Ethernet_Phy/ETH_LED0" +AddNet "/Ethernet_Phy/ETH_LED1" +AddNet "/Ethernet_Phy/ETH_MDC" +AddNet "/Ethernet_Phy/ETH_PLL1.8V" +AddNet "/Ethernet_Phy/ETH_RXC" +AddNet "/Ethernet_Phy/ETH_RXD0" +AddNet "/Ethernet_Phy/ETH_RXD1" +AddNet "/Ethernet_Phy/ETH_RXDV" +AddNet "/Ethernet_Phy/ETH_RXER" +AddNet "/Ethernet_Phy/ETH_TXC" +AddNet "/Ethernet_Phy/ETH_TXD1" +AddNet "/Ethernet_Phy/ETH_TXD2" +AddNet "/Ethernet_Phy/ETH_TXEN" +AddNet "/Ethernet_Phy/ETH_TXER" +AddNet "/FPGA_Spartan6/ETH_CLK" +AddNet "/FPGA_Spartan6/ETH_MDIO" +AddNet "/FPGA_Spartan6/ETH_RESET_N" +AddNet "/FPGA_Spartan6/ETH_RXD2" +AddNet "/FPGA_Spartan6/ETH_RXD3" +AddNet "/FPGA_Spartan6/ETH_TXD0" +AddNet "/FPGA_Spartan6/ETH_TXD3" +AddNet "/FPGA_Spartan6/M0_A0" +AddNet "/FPGA_Spartan6/M0_A1" +AddNet "/FPGA_Spartan6/M0_A11" +AddNet "/FPGA_Spartan6/M0_A12" +AddNet "/FPGA_Spartan6/M0_A2" +AddNet "/FPGA_Spartan6/M0_A3" +AddNet "/FPGA_Spartan6/M0_A4" +AddNet "/FPGA_Spartan6/M0_A6" +AddNet "/FPGA_Spartan6/M0_A8" +AddNet "/FPGA_Spartan6/M0_A9" +AddNet "/FPGA_Spartan6/M0_BA1" +AddNet "/FPGA_Spartan6/M0_CAS#" +AddNet "/FPGA_Spartan6/M0_CKE" +AddNet "/FPGA_Spartan6/M0_CLK#" +AddNet "/FPGA_Spartan6/M0_DQ0" +AddNet "/FPGA_Spartan6/M0_DQ1" +AddNet "/FPGA_Spartan6/M0_DQ11" +AddNet "/FPGA_Spartan6/M0_DQ12" +AddNet "/FPGA_Spartan6/M0_DQ14" +AddNet "/FPGA_Spartan6/M0_DQ15" +AddNet "/FPGA_Spartan6/M0_DQ2" +AddNet "/FPGA_Spartan6/M0_DQ3" +AddNet "/FPGA_Spartan6/M0_DQ4" +AddNet "/FPGA_Spartan6/M0_DQ7" +AddNet "/FPGA_Spartan6/M0_DQ8" +AddNet "/FPGA_Spartan6/M0_RAS#" +AddNet "/FPGA_Spartan6/M0_WE#" +AddNet "/FPGA_Spartan6/M1_A0" +AddNet "/FPGA_Spartan6/M1_A1" +AddNet "/FPGA_Spartan6/M1_A12" +AddNet "/FPGA_Spartan6/M1_A2" +AddNet "/FPGA_Spartan6/M1_A3" +AddNet "/FPGA_Spartan6/M1_A7" +AddNet "/FPGA_Spartan6/M1_A8" +AddNet "/FPGA_Spartan6/M1_BA1" +AddNet "/FPGA_Spartan6/M1_CLK" +AddNet "/FPGA_Spartan6/M1_CLK#" +AddNet "/FPGA_Spartan6/M1_DQ1" +AddNet "/FPGA_Spartan6/M1_DQ10" +AddNet "/FPGA_Spartan6/M1_DQ11" +AddNet "/FPGA_Spartan6/M1_DQ12" +AddNet "/FPGA_Spartan6/M1_DQ14" +AddNet "/FPGA_Spartan6/M1_DQ15" +AddNet "/FPGA_Spartan6/M1_DQ2" +AddNet "/FPGA_Spartan6/M1_DQ4" +AddNet "/FPGA_Spartan6/M1_DQ7" +AddNet "/FPGA_Spartan6/M1_DQ8" +AddNet "/FPGA_Spartan6/M1_DQ9" +AddNet "/FPGA_Spartan6/M1_LDQS" +AddNet "/FPGA_Spartan6/M1_UDM" +AddNet "/FPGA_Spartan6/M1_UDQS" +AddNet "/FPGA_Spartan6/M1_WE#" +AddNet "/FPGA_Spartan6/SD_DAT3" +AddNet "/FPGA_Spartan6/USBA_OE_N" +AddNet "/FPGA_Spartan6/USBA_VM" +AddNet "/FPGA_Spartan6/USBA_VP" +AddNet "/Non_volatile_memories/FRB_N" +AddNet "/Non_volatile_memories/SD_CLK" +AddNet "/Non_volatile_memories/SD_CMD" +AddNet "/Non_volatile_memories/SD_DAT0" +AddNet "/Non_volatile_memories/SD_DAT1" +AddNet "/Non_volatile_memories/SD_DAT2" +AddNet "/USB/USBA_RCV" +AddNet "/USB/USBA_SPD" +AddNet "3.3V" +AddNet "GND" +AddNet "N-000043" +AddNet "N-000044" +AddNet "N-000045" +AddNet "N-000047" +AddNet "N-000101" +AddNet "N-000334" +AddNet "N-000335" +AddNet "N-000336" +AddNet "N-000337" +AddNet "N-000338" +AddNet "N-000344" +AddNet "N-000345" +AddNet "N-000346" +AddNet "N-000347" +AddNet "N-000350" +AddNet "N-000356" +AddNet "N-000357" +AddNet "N-000358" +AddNet "N-000360" +AddNet "N-000361" +AddNet "N-000362" +AddNet "N-000363" +$EndNCLASS $MODULE FGG484bga-p10 Po 56450 33930 0 15 4C4325AE 4C431E53 ~~ Li FGG484bga-p10 @@ -655,7 +844,7 @@ $PAD Sh "A1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -4133 -4133 $EndPAD $PAD @@ -676,49 +865,49 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 40 "/Ethernet_Phy/ETH_INT" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/FPGA_Spartan6/ETH_INT" +Ne 56 "/FPGA_Spartan6/ETH_MDIO" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/FPGA_Spartan6/ETH_RXD3" +Ne 47 "/Ethernet_Phy/ETH_RXD1" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/FPGA_Spartan6/ETH_RXD1" +Ne 48 "/Ethernet_Phy/ETH_RXDV" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/FPGA_Spartan6/ETH_RXDV" +Ne 54 "/Ethernet_Phy/ETH_TXER" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/FPGA_Spartan6/ETH_TXD0" +Ne 52 "/Ethernet_Phy/ETH_TXD2" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/FPGA_Spartan6/ETH_CLK" +Ne 38 "/Ethernet_Phy/ETH_COL" Po -590 -4133 $EndPAD $PAD @@ -753,28 +942,28 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/Non_volatile_memories/SD_DAT3" +Ne 114 "/FPGA_Spartan6/SD_DAT3" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/Non_volatile_memories/SD_CLK" +Ne 119 "/Non_volatile_memories/SD_CLK" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/FPGA_Spartan6/USBA_VM" +Ne 116 "/FPGA_Spartan6/USBA_VM" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/FPGA_Spartan6/USBA_RCV" +Ne 124 "/USB/USBA_RCV" Po 2558 -4133 $EndPAD $PAD @@ -802,7 +991,7 @@ $PAD Sh "A22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 4133 -4133 $EndPAD $PAD @@ -830,56 +1019,56 @@ $PAD Sh "B4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "+3.3V" +Ne 3 "+3.3V" Po -2952 -3739 $EndPAD $PAD Sh "B5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2558 -3739 $EndPAD $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/FPGA_Spartan6/ETH_RESET_N" +Ne 58 "/FPGA_Spartan6/ETH_RXD2" Po -2165 -3739 $EndPAD $PAD Sh "B7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "+3.3V" +Ne 3 "+3.3V" Po -1771 -3739 $EndPAD $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/FPGA_Spartan6/ETH_RXD0" +Ne 49 "/Ethernet_Phy/ETH_RXER" Po -1377 -3739 $EndPAD $PAD Sh "B9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -983 -3739 $EndPAD $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/FPGA_Spartan6/ETH_RXC" +Ne 39 "/Ethernet_Phy/ETH_CRS" Po -590 -3739 $EndPAD $PAD Sh "B11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "+3.3V" +Ne 3 "+3.3V" Po -196 -3739 $EndPAD $PAD @@ -893,7 +1082,7 @@ $PAD Sh "B13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 590 -3739 $EndPAD $PAD @@ -907,35 +1096,35 @@ $PAD Sh "B15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "+3.3V" +Ne 3 "+3.3V" Po 1377 -3739 $EndPAD $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/Non_volatile_memories/SD_DAT0" +Ne 121 "/Non_volatile_memories/SD_DAT0" Po 1771 -3739 $EndPAD $PAD Sh "B17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 2165 -3739 $EndPAD $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/FPGA_Spartan6/USBA_VP" +Ne 117 "/FPGA_Spartan6/USBA_VP" Po 2558 -3739 $EndPAD $PAD Sh "B19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "+3.3V" +Ne 3 "+3.3V" Po 2952 -3739 $EndPAD $PAD @@ -963,14 +1152,14 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_A11" +Ne 64 "/FPGA_Spartan6/M0_A11" Po -4133 -3346 $EndPAD $PAD Sh "C2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -3739 -3346 $EndPAD $PAD @@ -991,42 +1180,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 43 "/Ethernet_Phy/ETH_MDC" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/FPGA_Spartan6/ETH_MDIO" +Ne 59 "/FPGA_Spartan6/ETH_RXD3" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/FPGA_Spartan6/ETH_RXD2" +Ne 46 "/Ethernet_Phy/ETH_RXD0" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/FPGA_Spartan6/ETH_TXER" +Ne 60 "/FPGA_Spartan6/ETH_TXD0" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/FPGA_Spartan6/ETH_TXEN" +Ne 51 "/Ethernet_Phy/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/FPGA_Spartan6/ETH_TXC" +Ne 55 "/FPGA_Spartan6/ETH_CLK" Po -590 -3346 $EndPAD $PAD @@ -1068,14 +1257,14 @@ $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/Non_volatile_memories/SD_DAT1" +Ne 122 "/Non_volatile_memories/SD_DAT1" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/Non_volatile_memories/SD_CMD" +Ne 120 "/Non_volatile_memories/SD_CMD" Po 2165 -3346 $EndPAD $PAD @@ -1096,35 +1285,35 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_A8" +Ne 95 "/FPGA_Spartan6/M1_A8" Po 3346 -3346 $EndPAD $PAD Sh "C21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 3739 -3346 $EndPAD $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_A9" +Ne 24 "/DDR_Banks/M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M0_A12" +Ne 65 "/FPGA_Spartan6/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M0_CKE" +Ne 74 "/FPGA_Spartan6/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1138,7 +1327,7 @@ $PAD Sh "D4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2952 -2952 $EndPAD $PAD @@ -1152,35 +1341,35 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/FPGA_Spartan6/ETH_MDC" +Ne 57 "/FPGA_Spartan6/ETH_RESET_N" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/FPGA_Spartan6/ETH_TXD1" +Ne 61 "/FPGA_Spartan6/ETH_TXD3" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/FPGA_Spartan6/ETH_TXD2" +Ne 50 "/Ethernet_Phy/ETH_TXC" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/FPGA_Spartan6/ETH_RXER" +Ne 53 "/Ethernet_Phy/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/FPGA_Spartan6/ETH_TXD3" +Ne 45 "/Ethernet_Phy/ETH_RXC" Po -590 -2952 $EndPAD $PAD @@ -1215,28 +1404,28 @@ $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Non_volatile_memories/SD_DAT2" +Ne 123 "/Non_volatile_memories/SD_DAT2" Po 1377 -2952 $EndPAD $PAD Sh "D16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 1771 -2952 $EndPAD $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/FPGA_Spartan6/USBA_SPD" +Ne 125 "/USB/USBA_SPD" Po 2165 -2952 $EndPAD $PAD Sh "D18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 2558 -2952 $EndPAD $PAD @@ -1257,35 +1446,35 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_CKE" +Ne 27 "/DDR_Banks/M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M1_A12" +Ne 91 "/FPGA_Spartan6/M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/DDR_Banks/M0_A9" +Ne 71 "/FPGA_Spartan6/M0_A9" Po -4133 -2558 $EndPAD $PAD Sh "E2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -3739 -2558 $EndPAD $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/DDR_Banks/M0_A8" +Ne 70 "/FPGA_Spartan6/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1313,7 +1502,7 @@ $PAD Sh "E7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -1771 -2558 $EndPAD $PAD @@ -1327,7 +1516,7 @@ $PAD Sh "E9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "+3.3V" +Ne 3 "+3.3V" Po -983 -2558 $EndPAD $PAD @@ -1355,7 +1544,7 @@ $PAD Sh "E13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "+3.3V" +Ne 3 "+3.3V" Po 590 -2558 $EndPAD $PAD @@ -1369,21 +1558,21 @@ $PAD Sh "E15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 1377 -2558 $EndPAD $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/FPGA_Spartan6/USBA_OE_N" +Ne 115 "/FPGA_Spartan6/USBA_OE_N" Po 1771 -2558 $EndPAD $PAD Sh "E17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "+3.3V" +Ne 3 "+3.3V" Po 2165 -2558 $EndPAD $PAD @@ -1397,28 +1586,28 @@ $PAD Sh "E19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 2952 -2558 $EndPAD $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/DDR_Banks/M1_A7" +Ne 94 "/FPGA_Spartan6/M1_A7" Po 3346 -2558 $EndPAD $PAD Sh "E21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 3739 -2558 $EndPAD $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/DDR_Banks/M1_A2" +Ne 92 "/FPGA_Spartan6/M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -1432,21 +1621,21 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/DDR_Banks/M0_WE#" +Ne 88 "/FPGA_Spartan6/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/DDR_Banks/M0_A4" +Ne 68 "/FPGA_Spartan6/M0_A4" Po -3346 -2165 $EndPAD $PAD Sh "F4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2952 -2165 $EndPAD $PAD @@ -1460,7 +1649,7 @@ $PAD Sh "F6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2165 -2165 $EndPAD $PAD @@ -1495,7 +1684,7 @@ $PAD Sh "F11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -196 -2165 $EndPAD $PAD @@ -1551,63 +1740,63 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/DDR_Banks/M1_A11" +Ne 20 "/DDR_Banks/M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/DDR_Banks/M1_A4" +Ne 21 "/DDR_Banks/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/DDR_Banks/M1_A0" +Ne 89 "/FPGA_Spartan6/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/DDR_Banks/M1_A1" +Ne 90 "/FPGA_Spartan6/M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/DDR_Banks/M0_BA1" +Ne 72 "/FPGA_Spartan6/M0_BA1" Po -4133 -1771 $EndPAD $PAD Sh "G2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -3739 -1771 $EndPAD $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/DDR_Banks/M0_BA0" +Ne 8 "/DDR_Banks/M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/DDR_Banks/M0_A10" +Ne 5 "/DDR_Banks/M0_A10" Po -2952 -1771 $EndPAD $PAD Sh "G5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2558 -1771 $EndPAD $PAD @@ -1642,7 +1831,7 @@ $PAD Sh "G10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "+3.3V" +Ne 3 "+3.3V" Po -590 -1771 $EndPAD $PAD @@ -1656,7 +1845,7 @@ $PAD Sh "G12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 196 -1771 $EndPAD $PAD @@ -1670,7 +1859,7 @@ $PAD Sh "G14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "+3.3V" +Ne 3 "+3.3V" Po 983 -1771 $EndPAD $PAD @@ -1698,28 +1887,28 @@ $PAD Sh "G18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 2558 -1771 $EndPAD $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/DDR_Banks/M1_A10" +Ne 19 "/DDR_Banks/M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/DDR_Banks/M1_A3" +Ne 93 "/FPGA_Spartan6/M1_A3" Po 3346 -1771 $EndPAD $PAD Sh "G21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 3739 -1771 $EndPAD $PAD @@ -1733,49 +1922,49 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/DDR_Banks/M0_A1" +Ne 63 "/FPGA_Spartan6/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/DDR_Banks/M0_A0" +Ne 62 "/FPGA_Spartan6/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/DDR_Banks/M0_CLK#" +Ne 75 "/FPGA_Spartan6/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/DDR_Banks/M0_CLK" +Ne 9 "/DDR_Banks/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/DDR_Banks/M0_A2" +Ne 66 "/FPGA_Spartan6/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/DDR_Banks/M0_A7" +Ne 7 "/DDR_Banks/M0_A7" Po -2165 -1377 $EndPAD $PAD Sh "H7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -1771 -1377 $EndPAD $PAD @@ -1789,7 +1978,7 @@ $PAD Sh "H9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -983 -1377 $EndPAD $PAD @@ -1831,7 +2020,7 @@ $PAD Sh "H15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 1377 -1377 $EndPAD $PAD @@ -1859,63 +2048,63 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/DDR_Banks/M1_WE#" +Ne 113 "/FPGA_Spartan6/M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/DDR_Banks/M1_CLK" +Ne 97 "/FPGA_Spartan6/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/DDR_Banks/M1_RAS#" +Ne 34 "/DDR_Banks/M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/DDR_Banks/M1_CAS#" +Ne 26 "/DDR_Banks/M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/DDR_Banks/M0_DQ5" +Ne 12 "/DDR_Banks/M0_DQ5" Po -4133 -983 $EndPAD $PAD Sh "J2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -3739 -983 $EndPAD $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/DDR_Banks/M0_DQ4" +Ne 84 "/FPGA_Spartan6/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/DDR_Banks/M0_A6" +Ne 69 "/FPGA_Spartan6/M0_A6" Po -2952 -983 $EndPAD $PAD Sh "J5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2558 -983 $EndPAD $PAD @@ -1936,56 +2125,56 @@ $PAD Sh "J8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po -1377 -983 $EndPAD $PAD Sh "J9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -983 -983 $EndPAD $PAD Sh "J10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po -590 -983 $EndPAD $PAD Sh "J11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -196 -983 $EndPAD $PAD Sh "J12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po 196 -983 $EndPAD $PAD Sh "J13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 590 -983 $EndPAD $PAD Sh "J14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po 983 -983 $EndPAD $PAD Sh "J15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 1377 -983 $EndPAD $PAD @@ -1999,84 +2188,84 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/DDR_Banks/M1_BA0" +Ne 25 "/DDR_Banks/M1_BA0" Po 2165 -983 $EndPAD $PAD Sh "J18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 2558 -983 $EndPAD $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/DDR_Banks/M1_CLK#" +Ne 98 "/FPGA_Spartan6/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/DDR_Banks/M1_DQ4" +Ne 106 "/FPGA_Spartan6/M1_DQ4" Po 3346 -983 $EndPAD $PAD Sh "J21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 3739 -983 $EndPAD $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/DDR_Banks/M1_DQ5" +Ne 31 "/DDR_Banks/M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/DDR_Banks/M0_DQ7" +Ne 85 "/FPGA_Spartan6/M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/DDR_Banks/M0_DQ6" +Ne 13 "/DDR_Banks/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/DDR_Banks/M0_A5" +Ne 6 "/DDR_Banks/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/DDR_Banks/M0_CAS#" +Ne 73 "/FPGA_Spartan6/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/DDR_Banks/M0_RAS#" +Ne 87 "/FPGA_Spartan6/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/DDR_Banks/M0_A3" +Ne 67 "/FPGA_Spartan6/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2097,21 +2286,21 @@ $PAD Sh "K9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po -983 -590 $EndPAD $PAD Sh "K10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -590 -590 $EndPAD $PAD Sh "K11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po -196 -590 $EndPAD $PAD @@ -2125,21 +2314,21 @@ $PAD Sh "K13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po 590 -590 $EndPAD $PAD Sh "K14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 983 -590 $EndPAD $PAD Sh "K15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 1377 -590 $EndPAD $PAD @@ -2153,7 +2342,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/DDR_Banks/M1_BA1" +Ne 96 "/FPGA_Spartan6/M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2167,28 +2356,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/DDR_Banks/M1_A6" +Ne 23 "/DDR_Banks/M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/DDR_Banks/M1_A5" +Ne 22 "/DDR_Banks/M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/DDR_Banks/M1_DQ6" +Ne 32 "/DDR_Banks/M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/DDR_Banks/M1_DQ7" +Ne 107 "/FPGA_Spartan6/M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2202,28 +2391,28 @@ $PAD Sh "L2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -3739 -196 $EndPAD $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/DDR_Banks/M0_LDQS" +Ne 16 "/DDR_Banks/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/DDR_Banks/M0_LDM" +Ne 15 "/DDR_Banks/M0_LDM" Po -2952 -196 $EndPAD $PAD Sh "L5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2558 -196 $EndPAD $PAD @@ -2237,56 +2426,56 @@ $PAD Sh "L7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -1771 -196 $EndPAD $PAD Sh "L8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -1377 -196 $EndPAD $PAD Sh "L9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -983 -196 $EndPAD $PAD Sh "L10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po -590 -196 $EndPAD $PAD Sh "L11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -196 -196 $EndPAD $PAD Sh "L12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po 196 -196 $EndPAD $PAD Sh "L13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 590 -196 $EndPAD $PAD Sh "L14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po 983 -196 $EndPAD $PAD @@ -2300,7 +2489,7 @@ $PAD Sh "L16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 1771 -196 $EndPAD $PAD @@ -2314,28 +2503,28 @@ $PAD Sh "L18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 2558 -196 $EndPAD $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/DDR_Banks/M1_LDM" +Ne 33 "/DDR_Banks/M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/DDR_Banks/M1_LDQS" +Ne 110 "/FPGA_Spartan6/M1_LDQS" Po 3346 -196 $EndPAD $PAD Sh "L21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 3739 -196 $EndPAD $PAD @@ -2349,21 +2538,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/DDR_Banks/M0_DQ3" +Ne 83 "/FPGA_Spartan6/M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/DDR_Banks/M0_DQ2" +Ne 82 "/FPGA_Spartan6/M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/DDR_Banks/M0_UDM" +Ne 17 "/DDR_Banks/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2405,49 +2594,49 @@ $PAD Sh "M9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po -983 196 $EndPAD $PAD Sh "M10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -590 196 $EndPAD $PAD Sh "M11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po -196 196 $EndPAD $PAD Sh "M12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 196 196 $EndPAD $PAD Sh "M13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po 590 196 $EndPAD $PAD Sh "M14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 983 196 $EndPAD $PAD Sh "M15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 1377 196 $EndPAD $PAD @@ -2482,42 +2671,42 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/DDR_Banks/M1_UDM" +Ne 111 "/FPGA_Spartan6/M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/DDR_Banks/M1_DQ2" +Ne 105 "/FPGA_Spartan6/M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/DDR_Banks/M1_DQ3" +Ne 30 "/DDR_Banks/M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/DDR_Banks/M0_DQ1" +Ne 77 "/FPGA_Spartan6/M0_DQ1" Po -4133 590 $EndPAD $PAD Sh "N2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -3739 590 $EndPAD $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/DDR_Banks/M0_DQ0" +Ne 76 "/FPGA_Spartan6/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -2531,7 +2720,7 @@ $PAD Sh "N5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2558 590 $EndPAD $PAD @@ -2552,49 +2741,49 @@ $PAD Sh "N8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -1377 590 $EndPAD $PAD Sh "N9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -983 590 $EndPAD $PAD Sh "N10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po -590 590 $EndPAD $PAD Sh "N11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -196 590 $EndPAD $PAD Sh "N12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po 196 590 $EndPAD $PAD Sh "N13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 590 590 $EndPAD $PAD Sh "N14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po 983 590 $EndPAD $PAD @@ -2615,14 +2804,14 @@ $PAD Sh "N17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 2165 590 $EndPAD $PAD Sh "N18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 2558 590 $EndPAD $PAD @@ -2636,35 +2825,35 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/DDR_Banks/M1_DQ0" +Ne 28 "/DDR_Banks/M1_DQ0" Po 3346 590 $EndPAD $PAD Sh "N21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 3739 590 $EndPAD $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/DDR_Banks/M1_DQ1" +Ne 99 "/FPGA_Spartan6/M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/DDR_Banks/M0_DQ9" +Ne 14 "/DDR_Banks/M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/DDR_Banks/M0_DQ8" +Ne 86 "/FPGA_Spartan6/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -2713,42 +2902,42 @@ $PAD Sh "P9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po -983 983 $EndPAD $PAD Sh "P10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -590 983 $EndPAD $PAD Sh "P11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po -196 983 $EndPAD $PAD Sh "P12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 196 983 $EndPAD $PAD Sh "P13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po 590 983 $EndPAD $PAD Sh "P14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 983 983 $EndPAD $PAD @@ -2797,35 +2986,35 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/DDR_Banks/M1_DQ8" +Ne 108 "/FPGA_Spartan6/M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/DDR_Banks/M1_DQ9" +Ne 109 "/FPGA_Spartan6/M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/DDR_Banks/M0_DQ11" +Ne 78 "/FPGA_Spartan6/M0_DQ11" Po -4133 1377 $EndPAD $PAD Sh "R2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -3739 1377 $EndPAD $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/DDR_Banks/M0_DQ10" +Ne 10 "/DDR_Banks/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -2839,14 +3028,14 @@ $PAD Sh "R5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2558 1377 $EndPAD $PAD Sh "R6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2165 1377 $EndPAD $PAD @@ -2874,7 +3063,7 @@ $PAD Sh "R10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -590 1377 $EndPAD $PAD @@ -2888,7 +3077,7 @@ $PAD Sh "R12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 196 1377 $EndPAD $PAD @@ -2902,7 +3091,7 @@ $PAD Sh "R14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "+1.2V" +Ne 1 "+1.2V" Po 983 1377 $EndPAD $PAD @@ -2930,7 +3119,7 @@ $PAD Sh "R18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 2558 1377 $EndPAD $PAD @@ -2944,21 +3133,21 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/DDR_Banks/M1_DQ10" +Ne 100 "/FPGA_Spartan6/M1_DQ10" Po 3346 1377 $EndPAD $PAD Sh "R21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 3739 1377 $EndPAD $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/DDR_Banks/M1_DQ11" +Ne 101 "/FPGA_Spartan6/M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -2972,7 +3161,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/DDR_Banks/M0_UDQS" +Ne 18 "/DDR_Banks/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3021,7 +3210,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po -983 1771 $EndPAD $PAD @@ -3049,7 +3238,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po 590 1771 $EndPAD $PAD @@ -3105,7 +3294,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/DDR_Banks/M1_UDQS" +Ne 112 "/FPGA_Spartan6/M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3119,21 +3308,21 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/DDR_Banks/M0_DQ13" +Ne 11 "/DDR_Banks/M0_DQ13" Po -4133 2165 $EndPAD $PAD Sh "U2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -3739 2165 $EndPAD $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/DDR_Banks/M0_DQ12" +Ne 79 "/FPGA_Spartan6/M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3147,7 +3336,7 @@ $PAD Sh "U5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2558 2165 $EndPAD $PAD @@ -3161,7 +3350,7 @@ $PAD Sh "U7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -1771 2165 $EndPAD $PAD @@ -3189,7 +3378,7 @@ $PAD Sh "U11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -196 2165 $EndPAD $PAD @@ -3238,7 +3427,7 @@ $PAD Sh "U18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 2558 2165 $EndPAD $PAD @@ -3252,35 +3441,35 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/DDR_Banks/M1_DQ12" +Ne 102 "/FPGA_Spartan6/M1_DQ12" Po 3346 2165 $EndPAD $PAD Sh "U21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 3739 2165 $EndPAD $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/DDR_Banks/M1_DQ13" +Ne 29 "/DDR_Banks/M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/DDR_Banks/M0_DQ15" +Ne 81 "/FPGA_Spartan6/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/DDR_Banks/M0_DQ14" +Ne 80 "/FPGA_Spartan6/M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3294,7 +3483,7 @@ $PAD Sh "V4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2952 2558 $EndPAD $PAD @@ -3308,7 +3497,7 @@ $PAD Sh "V6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2165 2558 $EndPAD $PAD @@ -3322,7 +3511,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po -1377 2558 $EndPAD $PAD @@ -3336,7 +3525,7 @@ $PAD Sh "V10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -590 2558 $EndPAD $PAD @@ -3350,7 +3539,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po 196 2558 $EndPAD $PAD @@ -3364,7 +3553,7 @@ $PAD Sh "V14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 983 2558 $EndPAD $PAD @@ -3378,7 +3567,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po 1771 2558 $EndPAD $PAD @@ -3413,14 +3602,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/DDR_Banks/M1_DQ14" +Ne 103 "/FPGA_Spartan6/M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/DDR_Banks/M1_DQ15" +Ne 104 "/FPGA_Spartan6/M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -3434,7 +3623,7 @@ $PAD Sh "W2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -3739 2952 $EndPAD $PAD @@ -3455,7 +3644,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po -2558 2952 $EndPAD $PAD @@ -3469,7 +3658,7 @@ $PAD Sh "W7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -1771 2952 $EndPAD $PAD @@ -3532,7 +3721,7 @@ $PAD Sh "W16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 1771 2952 $EndPAD $PAD @@ -3553,7 +3742,7 @@ $PAD Sh "W19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 2952 2952 $EndPAD $PAD @@ -3567,7 +3756,7 @@ $PAD Sh "W21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 3739 2952 $EndPAD $PAD @@ -3749,7 +3938,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po -3346 3739 $EndPAD $PAD @@ -3763,7 +3952,7 @@ $PAD Sh "AA5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2558 3739 $EndPAD $PAD @@ -3777,7 +3966,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po -1771 3739 $EndPAD $PAD @@ -3791,7 +3980,7 @@ $PAD Sh "AA9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -983 3739 $EndPAD $PAD @@ -3805,7 +3994,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po -196 3739 $EndPAD $PAD @@ -3819,7 +4008,7 @@ $PAD Sh "AA13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 590 3739 $EndPAD $PAD @@ -3833,7 +4022,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po 1377 3739 $EndPAD $PAD @@ -3847,7 +4036,7 @@ $PAD Sh "AA17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 2165 3739 $EndPAD $PAD @@ -3861,7 +4050,7 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "N-000101" +Ne 132 "N-000101" Po 2952 3739 $EndPAD $PAD @@ -3889,7 +4078,7 @@ $PAD Sh "AB1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -4133 4133 $EndPAD $PAD @@ -4036,12 +4225,12 @@ $PAD Sh "AB22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 $MODULE LQFP48 -Po 53620 25730 900 15 4C433D64 4C432132 ~~ +Po 50667 25533 900 15 4C433D64 4C432132 ~~ Li LQFP48 Sc 4C432132 AR /4C4320F3/4C432132 @@ -4058,105 +4247,105 @@ $PAD Sh "12" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -1613 1082 $EndPAD $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/FPGA_Spartan6/ETH_RXER" +Ne 49 "/Ethernet_Phy/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/FPGA_Spartan6/ETH_RXC" +Ne 45 "/Ethernet_Phy/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/FPGA_Spartan6/ETH_RXDV" +Ne 48 "/Ethernet_Phy/ETH_RXDV" Po -1613 491 $EndPAD $PAD Sh "8" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -1613 295 $EndPAD $PAD Sh "7" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -1613 98 $EndPAD $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/FPGA_Spartan6/ETH_RXD0" +Ne 46 "/Ethernet_Phy/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 4 "/FPGA_Spartan6/ETH_RXD1" +Ne 47 "/Ethernet_Phy/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/FPGA_Spartan6/ETH_RXD2" +Ne 58 "/FPGA_Spartan6/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 3 "/FPGA_Spartan6/ETH_RXD3" +Ne 59 "/FPGA_Spartan6/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/FPGA_Spartan6/ETH_MDC" +Ne 43 "/Ethernet_Phy/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/FPGA_Spartan6/ETH_MDIO" +Ne 56 "/FPGA_Spartan6/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/FPGA_Spartan6/ETH_RESET_N" +Ne 57 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 44 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/FPGA_Spartan6/ETH_CLK" +Ne 55 "/FPGA_Spartan6/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -4170,7 +4359,7 @@ $PAD Sh "44" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -295 -1613 $EndPAD $PAD @@ -4191,56 +4380,56 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "N-000345" +Ne 133 "N-000334" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "N-000340" +Ne 140 "N-000346" Po 491 -1613 $EndPAD $PAD Sh "39" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 688 -1613 $EndPAD $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/Ethernet_Phy/ETH_A3.3V" +Ne 37 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000338" +Ne 138 "N-000344" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 2 "/FPGA_Spartan6/ETH_INT" +Ne 40 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/Ethernet_Phy/ETH_LED0" +Ne 41 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/Ethernet_Phy/ETH_LED1" +Ne 42 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4268,21 +4457,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/Ethernet_Phy/ETH_A1.8V" +Ne 36 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000339" +Ne 139 "N-000345" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "N-000346" +Ne 134 "N-000335" Po 1613 -491 $EndPAD $PAD @@ -4296,109 +4485,109 @@ $PAD Sh "35" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 1613 -885 $EndPAD $PAD Sh "36" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 1613 -1082 $EndPAD $PAD Sh "13" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/Ethernet_Phy/ETH_1.8V" +Ne 35 "/Ethernet_Phy/ETH_1.8V" Po -1082 1613 $EndPAD $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/FPGA_Spartan6/ETH_TXER" +Ne 54 "/Ethernet_Phy/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/FPGA_Spartan6/ETH_TXC" +Ne 50 "/Ethernet_Phy/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/FPGA_Spartan6/ETH_TXEN" +Ne 53 "/Ethernet_Phy/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/FPGA_Spartan6/ETH_TXD0" +Ne 60 "/FPGA_Spartan6/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/FPGA_Spartan6/ETH_TXD1" +Ne 51 "/Ethernet_Phy/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/FPGA_Spartan6/ETH_TXD2" +Ne 52 "/Ethernet_Phy/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/FPGA_Spartan6/ETH_TXD3" +Ne 61 "/FPGA_Spartan6/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 38 "/Ethernet_Phy/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 39 "/Ethernet_Phy/ETH_CRS" Po 688 1613 $EndPAD $PAD Sh "23" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 885 1613 $EndPAD $PAD Sh "24" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po 1082 1613 $EndPAD $EndMODULE LQFP48 $MODULE NAND-48TSOP -Po 83000 40000 0 15 4B8F4C98 4B76F108 ~~ +Po 60630 26181 900 15 4B8F4C98 4B76F108 ~~ Li NAND-48TSOP Sc 4B76F108 AR /4C4227FE/4B76F108 Op 0 0 0 -T0 -1816 4454 157 157 1800 20 N V 21 N"U5" -T1 0 118 118 118 1800 20 N I 21 N"NAND" +T0 -1816 4454 157 157 2700 20 N V 21 N"U5" +T1 0 118 118 118 2700 20 N I 21 N"NAND" DS -2470 3900 -2470 -3900 60 24 DS -2470 -3900 2430 -3900 60 24 DS 2430 -3900 2430 3900 60 24 @@ -4613,336 +4802,336 @@ DS -2240 -3500 -2240 -3900 30 26 DS -2240 -3900 -2290 -3900 30 26 DS -2290 -3900 -2290 -3500 30 26 $PAD -Sh "1" R 100 600 0 0 0 +Sh "1" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -2270 3850 $EndPAD $PAD -Sh "2" R 100 600 0 0 0 +Sh "2" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -2070 3850 $EndPAD $PAD -Sh "3" R 100 600 0 0 0 +Sh "3" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -1870 3850 $EndPAD $PAD -Sh "4" R 100 600 0 0 0 +Sh "4" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -1680 3850 $EndPAD $PAD -Sh "5" R 100 600 0 0 0 +Sh "5" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -1480 3850 $EndPAD $PAD -Sh "6" R 100 600 0 0 0 +Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/Non_volatile_memories/FRB_N" +Ne 118 "/Non_volatile_memories/FRB_N" Po -1280 3850 $EndPAD $PAD -Sh "7" R 100 600 0 0 0 +Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/Non_volatile_memories/FRB_N" +Ne 118 "/Non_volatile_memories/FRB_N" Po -1090 3850 $EndPAD $PAD -Sh "8" R 100 600 0 0 0 +Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -890 3850 $EndPAD $PAD -Sh "9" R 100 600 0 0 0 +Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -690 3850 $EndPAD $PAD -Sh "10" R 100 600 0 0 0 +Sh "10" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -500 3850 $EndPAD $PAD -Sh "11" R 100 600 0 0 0 +Sh "11" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -300 3850 $EndPAD $PAD -Sh "12" R 100 600 0 0 0 +Sh "12" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -100 3850 $EndPAD $PAD -Sh "13" R 100 600 0 0 0 +Sh "13" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 100 3850 $EndPAD $PAD -Sh "14" R 100 600 0 0 0 +Sh "14" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 290 3850 $EndPAD $PAD -Sh "15" R 100 600 0 0 0 +Sh "15" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 490 3850 $EndPAD $PAD -Sh "16" R 100 600 0 0 0 +Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 690 3850 $EndPAD $PAD -Sh "17" R 100 600 0 0 0 +Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 880 3850 $EndPAD $PAD -Sh "18" R 100 600 0 0 0 +Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1080 3850 $EndPAD $PAD -Sh "19" R 100 600 0 0 0 +Sh "19" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po 1280 3850 $EndPAD $PAD -Sh "20" R 100 600 0 0 0 +Sh "20" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1470 3850 $EndPAD $PAD -Sh "21" R 100 600 0 0 0 +Sh "21" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1670 3850 $EndPAD $PAD -Sh "22" R 100 600 0 0 0 +Sh "22" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1870 3850 $EndPAD $PAD -Sh "23" R 100 600 0 0 0 +Sh "23" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 2060 3850 $EndPAD $PAD -Sh "24" R 100 600 0 0 0 +Sh "24" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 2260 3850 $EndPAD $PAD -Sh "25" R 100 600 0 0 0 +Sh "25" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 2260 -3850 $EndPAD $PAD -Sh "26" R 100 600 0 0 0 +Sh "26" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 2060 -3850 $EndPAD $PAD -Sh "27" R 100 600 0 0 0 +Sh "27" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1870 -3850 $EndPAD $PAD -Sh "28" R 100 600 0 0 0 +Sh "28" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1670 -3850 $EndPAD $PAD -Sh "29" R 100 600 0 0 0 +Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1470 -3850 $EndPAD $PAD -Sh "30" R 100 600 0 0 0 +Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1280 -3850 $EndPAD $PAD -Sh "31" R 100 600 0 0 0 +Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 1080 -3850 $EndPAD $PAD -Sh "32" R 100 600 0 0 0 +Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 880 -3850 $EndPAD $PAD -Sh "33" R 100 600 0 0 0 +Sh "33" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 690 -3850 $EndPAD $PAD -Sh "34" R 100 600 0 0 0 +Sh "34" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 490 -3850 $EndPAD $PAD -Sh "35" R 100 600 0 0 0 +Sh "35" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po 290 -3850 $EndPAD $PAD -Sh "36" R 100 600 0 0 0 +Sh "36" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 100 -3850 $EndPAD $PAD -Sh "37" R 100 600 0 0 0 +Sh "37" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -100 -3850 $EndPAD $PAD -Sh "38" R 100 600 0 0 0 +Sh "38" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -300 -3850 $EndPAD $PAD -Sh "39" R 100 600 0 0 0 +Sh "39" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -500 -3850 $EndPAD $PAD -Sh "40" R 100 600 0 0 0 +Sh "40" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -690 -3850 $EndPAD $PAD -Sh "41" R 100 600 0 0 0 +Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -890 -3850 $EndPAD $PAD -Sh "42" R 100 600 0 0 0 +Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -1090 -3850 $EndPAD $PAD -Sh "43" R 100 600 0 0 0 +Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -1280 -3850 $EndPAD $PAD -Sh "44" R 100 600 0 0 0 +Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -1480 -3850 $EndPAD $PAD -Sh "45" R 100 600 0 0 0 +Sh "45" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -1680 -3850 $EndPAD $PAD -Sh "46" R 100 600 0 0 0 +Sh "46" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -1870 -3850 $EndPAD $PAD -Sh "47" R 100 600 0 0 0 +Sh "47" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" Po -2070 -3850 $EndPAD $PAD -Sh "48" R 100 600 0 0 0 +Sh "48" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 0 "" @@ -4950,7 +5139,7 @@ Po -2270 -3850 $EndPAD $EndMODULE NAND-48TSOP $MODULE MICROSD-500901 -Po 60500 500 1800 15 4C5F34DA 4B76F5E2 ~~ +Po 62795 14370 1800 15 4C5F34DA 4B76F5E2 ~~ Li MICROSD-500901 Sc 4B76F5E2 AR /4C4227FE/4B76F5E2 @@ -4970,21 +5159,21 @@ $PAD Sh "1" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 36 "/Non_volatile_memories/SD_DAT2" +Ne 123 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 8 "/Non_volatile_memories/SD_DAT3" +Ne 114 "/FPGA_Spartan6/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 26 "/Non_volatile_memories/SD_CMD" +Ne 120 "/Non_volatile_memories/SD_CMD" Po -433 0 $EndPAD $PAD @@ -4998,61 +5187,61 @@ $PAD Sh "5" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 9 "/Non_volatile_memories/SD_CLK" +Ne 119 "/Non_volatile_memories/SD_CLK" Po 433 0 $EndPAD $PAD Sh "6" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 866 0 $EndPAD $PAD Sh "7" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 16 "/Non_volatile_memories/SD_DAT0" +Ne 121 "/Non_volatile_memories/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 25 "/Non_volatile_memories/SD_DAT1" +Ne 122 "/Non_volatile_memories/SD_DAT1" Po 1732 0 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 2707 -1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2707 -1024 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2707 2244 $EndPAD $PAD Sh "CASE" R 571 787 0 0 1800 Dr 0 0 0 At STD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 2707 2244 $EndPAD $EndMODULE MICROSD-500901 $MODULE SD-48025 -Po 53840 15540 1800 15 00000000 4C5D6F5A ~~ +Po 50887 15343 1800 15 00000000 4C5D6F5A ~~ Li SD-48025 Sc 4C5D6F5A AR /4C4320F3/4C5D6F5A @@ -5067,117 +5256,117 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 131 "N-000347" +Ne 135 "N-000336" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 131 "N-000347" +Ne 135 "N-000336" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 131 "N-000347" +Ne 135 "N-000336" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 131 "N-000347" +Ne 135 "N-000336" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 120 "N-000345" +Ne 133 "N-000334" Po -1750 -2500 $EndPAD $PAD Sh "3" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 118 "N-000069" +Ne 126 "3.3V" Po -750 -2500 $EndPAD $PAD Sh "5" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 1 "GND" +Ne 127 "GND" Po 250 -2500 $EndPAD $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 128 "N-000346" +Ne 134 "N-000335" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 121 "N-000340" +Ne 140 "N-000346" Po -1250 -3500 $EndPAD $PAD Sh "4" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 1 "GND" +Ne 127 "GND" Po -250 -3500 $EndPAD $PAD Sh "6" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 118 "N-000069" +Ne 126 "3.3V" Po 750 -3500 $EndPAD $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 127 "N-000339" +Ne 139 "N-000345" Po 1750 -3500 $EndPAD $PAD Sh "9" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 118 "N-000069" +Ne 126 "3.3V" Po -2150 -5400 $EndPAD $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 132 "N-000343" +Ne 136 "N-000337" Po -1150 -5400 $EndPAD $PAD Sh "11" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 118 "N-000069" +Ne 126 "3.3V" Po 1150 -5400 $EndPAD $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 133 "N-000342" +Ne 142 "N-000350" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 $MODULE TSSOP-14 -Po 59770 18070 2700 15 4C60642A 4C5F2025 ~~ +Po 60361 20235 2700 15 4C60642A 4C5F2025 ~~ Li TSSOP-14 Sc 4C5F2025 AR /4C5F1EDC/4C5F2025 @@ -5201,35 +5390,35 @@ $PAD Sh "1" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 2 "+2.5V" Po -767 1112 $EndPAD $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/FPGA_Spartan6/USBA_SPD" +Ne 125 "/USB/USBA_SPD" Po -511 1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/FPGA_Spartan6/USBA_RCV" +Ne 124 "/USB/USBA_RCV" Po -255 1112 $EndPAD $PAD Sh "4" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/FPGA_Spartan6/USBA_VP" +Ne 117 "/FPGA_Spartan6/USBA_VP" Po 0 1112 $EndPAD $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/FPGA_Spartan6/USBA_VM" +Ne 116 "/FPGA_Spartan6/USBA_VM" Po 255 1112 $EndPAD $PAD @@ -5243,42 +5432,42 @@ $PAD Sh "7" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 767 1112 $EndPAD $PAD Sh "8" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 767 -1112 $EndPAD $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/FPGA_Spartan6/USBA_OE_N" +Ne 115 "/FPGA_Spartan6/USBA_OE_N" Po 511 -1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 134 "N-000360" +Ne 143 "N-000356" Po 255 -1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 135 "N-000361" +Ne 146 "N-000360" Po 0 -1112 $EndPAD $PAD Sh "12" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -255 -1112 $EndPAD $PAD @@ -5292,7 +5481,7 @@ $PAD Sh "14" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -767 -1112 $EndPAD $EndMODULE TSSOP-14 @@ -5314,91 +5503,91 @@ $PAD Sh "1" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -4094 2176 $EndPAD $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/DDR_Banks/M1_DQ0" +Ne 28 "/DDR_Banks/M1_DQ0" Po -3838 2176 $EndPAD $PAD Sh "3" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -3582 2176 $EndPAD $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/DDR_Banks/M1_DQ1" +Ne 99 "/FPGA_Spartan6/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/DDR_Banks/M1_DQ2" +Ne 105 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/DDR_Banks/M1_DQ3" +Ne 30 "/DDR_Banks/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/DDR_Banks/M1_DQ4" +Ne 106 "/FPGA_Spartan6/M1_DQ4" Po -2303 2176 $EndPAD $PAD Sh "9" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2047 2176 $EndPAD $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/DDR_Banks/M1_DQ5" +Ne 31 "/DDR_Banks/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/DDR_Banks/M1_DQ6" +Ne 32 "/DDR_Banks/M1_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/DDR_Banks/M1_DQ7" +Ne 107 "/FPGA_Spartan6/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5412,14 +5601,14 @@ $PAD Sh "15" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -511 2176 $EndPAD $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/DDR_Banks/M1_LDQS" +Ne 110 "/FPGA_Spartan6/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -5433,7 +5622,7 @@ $PAD Sh "18" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 255 2176 $EndPAD $PAD @@ -5447,35 +5636,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/DDR_Banks/M1_LDM" +Ne 33 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/DDR_Banks/M1_WE#" +Ne 113 "/FPGA_Spartan6/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/DDR_Banks/M1_CAS#" +Ne 26 "/DDR_Banks/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/DDR_Banks/M1_RAS#" +Ne 34 "/DDR_Banks/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 1791 2176 $EndPAD $PAD @@ -5489,119 +5678,119 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/DDR_Banks/M1_BA0" +Ne 25 "/DDR_Banks/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/DDR_Banks/M1_BA1" +Ne 96 "/FPGA_Spartan6/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/DDR_Banks/M1_A10" +Ne 19 "/DDR_Banks/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/DDR_Banks/M1_A0" +Ne 89 "/FPGA_Spartan6/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/DDR_Banks/M1_A1" +Ne 90 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/DDR_Banks/M1_A2" +Ne 92 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/DDR_Banks/M1_A3" +Ne 93 "/FPGA_Spartan6/M1_A3" Po 3838 2176 $EndPAD $PAD Sh "33" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 4094 2176 $EndPAD $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/DDR_Banks/M1_A4" +Ne 21 "/DDR_Banks/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/DDR_Banks/M1_A5" +Ne 22 "/DDR_Banks/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/DDR_Banks/M1_A6" +Ne 23 "/DDR_Banks/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/DDR_Banks/M1_A7" +Ne 94 "/FPGA_Spartan6/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_A8" +Ne 95 "/FPGA_Spartan6/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_A9" +Ne 24 "/DDR_Banks/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/DDR_Banks/M1_A11" +Ne 20 "/DDR_Banks/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M1_A12" +Ne 91 "/FPGA_Spartan6/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -5615,42 +5804,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/DDR_Banks/M1_CLK#" +Ne 98 "/FPGA_Spartan6/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_CKE" +Ne 27 "/DDR_Banks/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/DDR_Banks/M1_CLK" +Ne 97 "/FPGA_Spartan6/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/DDR_Banks/M1_UDM" +Ne 111 "/FPGA_Spartan6/M1_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 136 "N-000047" +Ne 129 "N-000044" Po 255 -2176 $EndPAD $PAD @@ -5664,14 +5853,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/DDR_Banks/M1_UDQS" +Ne 112 "/FPGA_Spartan6/M1_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -511 -2176 $EndPAD $PAD @@ -5685,91 +5874,91 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/DDR_Banks/M1_DQ8" +Ne 108 "/FPGA_Spartan6/M1_DQ8" Po -1023 -2176 $EndPAD $PAD Sh "55" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -1279 -2176 $EndPAD $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/DDR_Banks/M1_DQ9" +Ne 109 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/DDR_Banks/M1_DQ10" +Ne 100 "/FPGA_Spartan6/M1_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/DDR_Banks/M1_DQ11" +Ne 101 "/FPGA_Spartan6/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/DDR_Banks/M1_DQ12" +Ne 102 "/FPGA_Spartan6/M1_DQ12" Po -2558 -2176 $EndPAD $PAD Sh "61" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2814 -2176 $EndPAD $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/DDR_Banks/M1_DQ13" +Ne 29 "/DDR_Banks/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/DDR_Banks/M1_DQ14" +Ne 103 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/DDR_Banks/M1_DQ15" +Ne 104 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 @@ -5791,91 +5980,91 @@ $PAD Sh "1" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -4094 2176 $EndPAD $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/DDR_Banks/M0_DQ0" +Ne 76 "/FPGA_Spartan6/M0_DQ0" Po -3838 2176 $EndPAD $PAD Sh "3" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -3582 2176 $EndPAD $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/DDR_Banks/M0_DQ1" +Ne 77 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/DDR_Banks/M0_DQ2" +Ne 82 "/FPGA_Spartan6/M0_DQ2" Po -3070 2176 $EndPAD $PAD Sh "6" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2814 2176 $EndPAD $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/DDR_Banks/M0_DQ3" +Ne 83 "/FPGA_Spartan6/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/DDR_Banks/M0_DQ4" +Ne 84 "/FPGA_Spartan6/M0_DQ4" Po -2303 2176 $EndPAD $PAD Sh "9" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2047 2176 $EndPAD $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/DDR_Banks/M0_DQ5" +Ne 12 "/DDR_Banks/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/DDR_Banks/M0_DQ6" +Ne 13 "/DDR_Banks/M0_DQ6" Po -1535 2176 $EndPAD $PAD Sh "12" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -1279 2176 $EndPAD $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/DDR_Banks/M0_DQ7" +Ne 85 "/FPGA_Spartan6/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5889,14 +6078,14 @@ $PAD Sh "15" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -511 2176 $EndPAD $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/DDR_Banks/M0_LDQS" +Ne 16 "/DDR_Banks/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -5910,7 +6099,7 @@ $PAD Sh "18" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 255 2176 $EndPAD $PAD @@ -5924,35 +6113,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/DDR_Banks/M0_LDM" +Ne 15 "/DDR_Banks/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/DDR_Banks/M0_WE#" +Ne 88 "/FPGA_Spartan6/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/DDR_Banks/M0_CAS#" +Ne 73 "/FPGA_Spartan6/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/DDR_Banks/M0_RAS#" +Ne 87 "/FPGA_Spartan6/M0_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 1791 2176 $EndPAD $PAD @@ -5966,119 +6155,119 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/DDR_Banks/M0_BA0" +Ne 8 "/DDR_Banks/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/DDR_Banks/M0_BA1" +Ne 72 "/FPGA_Spartan6/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/DDR_Banks/M0_A10" +Ne 5 "/DDR_Banks/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/DDR_Banks/M0_A0" +Ne 62 "/FPGA_Spartan6/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/DDR_Banks/M0_A1" +Ne 63 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/DDR_Banks/M0_A2" +Ne 66 "/FPGA_Spartan6/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/DDR_Banks/M0_A3" +Ne 67 "/FPGA_Spartan6/M0_A3" Po 3838 2176 $EndPAD $PAD Sh "33" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po 4094 2176 $EndPAD $PAD Sh "34" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 4094 -2176 $EndPAD $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/DDR_Banks/M0_A4" +Ne 68 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/DDR_Banks/M0_A5" +Ne 6 "/DDR_Banks/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/DDR_Banks/M0_A6" +Ne 69 "/FPGA_Spartan6/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/DDR_Banks/M0_A7" +Ne 7 "/DDR_Banks/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/DDR_Banks/M0_A8" +Ne 70 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/DDR_Banks/M0_A9" +Ne 71 "/FPGA_Spartan6/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_A11" +Ne 64 "/FPGA_Spartan6/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M0_A12" +Ne 65 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6092,42 +6281,42 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/DDR_Banks/M0_CLK#" +Ne 75 "/FPGA_Spartan6/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M0_CKE" +Ne 74 "/FPGA_Spartan6/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/DDR_Banks/M0_CLK" +Ne 9 "/DDR_Banks/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/DDR_Banks/M0_UDM" +Ne 17 "/DDR_Banks/M0_UDM" Po 767 -2176 $EndPAD $PAD Sh "48" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 511 -2176 $EndPAD $PAD Sh "49" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000046" +Ne 130 "N-000045" Po 255 -2176 $EndPAD $PAD @@ -6141,14 +6330,14 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/DDR_Banks/M0_UDQS" +Ne 18 "/DDR_Banks/M0_UDQS" Po -255 -2176 $EndPAD $PAD Sh "52" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -511 -2176 $EndPAD $PAD @@ -6162,96 +6351,96 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/DDR_Banks/M0_DQ8" +Ne 86 "/FPGA_Spartan6/M0_DQ8" Po -1023 -2176 $EndPAD $PAD Sh "55" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -1279 -2176 $EndPAD $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/DDR_Banks/M0_DQ9" +Ne 14 "/DDR_Banks/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/DDR_Banks/M0_DQ10" +Ne 10 "/DDR_Banks/M0_DQ10" Po -1791 -2176 $EndPAD $PAD Sh "58" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -2047 -2176 $EndPAD $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/DDR_Banks/M0_DQ11" +Ne 78 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/DDR_Banks/M0_DQ12" +Ne 79 "/FPGA_Spartan6/M0_DQ12" Po -2558 -2176 $EndPAD $PAD Sh "61" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -2814 -2176 $EndPAD $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/DDR_Banks/M0_DQ13" +Ne 11 "/DDR_Banks/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/DDR_Banks/M0_DQ14" +Ne 80 "/FPGA_Spartan6/M0_DQ14" Po -3326 -2176 $EndPAD $PAD Sh "64" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -3582 -2176 $EndPAD $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/DDR_Banks/M0_DQ15" +Ne 81 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD Sh "66" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 $MODULE 0402 -Po 65839 23126 1800 15 4C5FF890 4C5F2D27 ~~ +Po 61115 22732 1800 15 4C5FF890 4C5F2D27 ~~ Li 0402 Sc 4C5F2D27 AR /4C5F1EDC/4C5F2D27 @@ -6267,19 +6456,19 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 138 "N-000363" +Ne 147 "N-000361" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 56000 26000 0 15 4C5FF890 4C5D7DC4 ~~ +Po 53047 25803 0 15 4C5FF890 4C5D7DC4 ~~ Li 0402 Sc 4C5D7DC4 AR /4C4320F3/4C5D7DC4 @@ -6295,19 +6484,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "N-000347" +Ne 135 "N-000336" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 53543 22244 0 15 4C5FF890 4C5D71DB ~~ +Po 50590 22047 0 15 4C5FF890 4C5D71DB ~~ Li 0402 Sc 4C5D71DB AR /4C4320F3/4C5D71DB @@ -6323,19 +6512,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "N-000342" +Ne 142 "N-000350" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/Ethernet_Phy/ETH_LED1" +Ne 42 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 54921 22047 0 15 4C5FF890 4C5D719D ~~ +Po 51968 21850 0 15 4C5FF890 4C5D719D ~~ Li 0402 Sc 4C5D719D AR /4C4320F3/4C5D719D @@ -6351,19 +6540,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "N-000343" +Ne 136 "N-000337" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/Ethernet_Phy/ETH_LED0" +Ne 41 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 49016 27362 0 15 4C5FF890 4C5D7AF9 ~~ +Po 46063 27165 0 15 4C5FF890 4C5D7AF9 ~~ Li 0402 Sc 4C5D7AF9 AR /4C4320F3/4C5D7AF9 @@ -6379,19 +6568,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "N-000339" +Ne 139 "N-000345" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51000 25000 0 15 4C5FF890 4C5D7AF7 ~~ +Po 48047 24803 0 15 4C5FF890 4C5D7AF7 ~~ Li 0402 Sc 4C5D7AF7 AR /4C4320F3/4C5D7AF7 @@ -6407,19 +6596,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "N-000346" +Ne 134 "N-000335" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 48622 25197 0 15 4C5FF890 4C5D7AFC ~~ +Po 45669 25000 0 15 4C5FF890 4C5D7AFC ~~ Li 0402 Sc 4C5D7AFC AR /4C4320F3/4C5D7AFC @@ -6435,19 +6624,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "N-000340" +Ne 140 "N-000346" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 41929 18504 0 15 4C5FF890 4C5D7AFE ~~ +Po 45669 21063 0 15 4C5FF890 4C5D7AFE ~~ Li 0402 Sc 4C5D7AFE AR /4C4320F3/4C5D7AFE @@ -6463,19 +6652,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "N-000345" +Ne 133 "N-000334" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 52559 22835 0 15 4C5FF890 4C5D7ECF ~~ +Po 49606 22638 0 15 4C5FF890 4C5D7ECF ~~ Li 0402 Sc 4C5D7ECF AR /4C4320F3/4C5D7ECF @@ -6491,19 +6680,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "N-000338" +Ne 138 "N-000344" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51575 22835 0 15 4C5FF890 4C5D7F39 ~~ +Po 48622 22638 0 15 4C5FF890 4C5D7F39 ~~ Li 0402 Sc 4C5D7F39 AR /4C4320F3/4C5D7F39 @@ -6519,19 +6708,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/FPGA_Spartan6/ETH_MDIO" +Ne 56 "/FPGA_Spartan6/ETH_MDIO" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 66232 24701 1800 15 4C5FF890 4C5F2D1E ~~ +Po 61220 23425 1800 15 4C5FF890 4C5F2D1E ~~ Li 0402 Sc 4C5F2D1E AR /4C5F1EDC/4C5F2D1E @@ -6547,19 +6736,19 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 138 "N-000363" +Ne 147 "N-000361" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 50787 26969 0 15 4C5FF890 4C5D7DCB ~~ +Po 47834 26772 0 15 4C5FF890 4C5D7DCB ~~ Li 0402 Sc 4C5D7DCB AR /4C4320F3/4C5D7DCB @@ -6575,19 +6764,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "N-000347" +Ne 135 "N-000336" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 55709 23425 0 15 4C5FF890 4C5D7E43 ~~ +Po 52756 23228 0 15 4C5FF890 4C5D7E43 ~~ Li 0402 Sc 4C5D7E43 AR /4C4320F3/4C5D7E43 @@ -6603,19 +6792,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 56000 27000 0 15 4C5FF890 4C5D7E41 ~~ +Po 53047 26803 0 15 4C5FF890 4C5D7E41 ~~ Li 0402 Sc 4C5D7E41 AR /4C4320F3/4C5D7E41 @@ -6631,19 +6820,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 56000 24500 0 15 4C5FF890 4C5D8114 ~~ +Po 53047 24303 0 15 4C5FF890 4C5D8114 ~~ Li 0402 Sc 4C5D8114 AR /4C4320F3/4C5D8114 @@ -6659,19 +6848,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 44 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "N-000349" +Ne 141 "N-000347" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 56000 24000 0 15 4C5FF890 4C5D7FA7 ~~ +Po 53047 23803 0 15 4C5FF890 4C5D7FA7 ~~ Li 0402 Sc 4C5D7FA7 AR /4C4320F3/4C5D7FA7 @@ -6687,19 +6876,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/Ethernet_Phy/ETH_A3.3V" +Ne 37 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 48425 23622 0 15 4C5FF890 4C5D8104 ~~ +Po 45472 23425 0 15 4C5FF890 4C5D8104 ~~ Li 0402 Sc 4C5D8104 AR /4C4320F3/4C5D8104 @@ -6715,19 +6904,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/Ethernet_Phy/ETH_A1.8V" +Ne 36 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "N-000349" +Ne 141 "N-000347" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 56890 22835 0 15 4C5FF890 4C5D7FA3 ~~ +Po 53937 22638 0 15 4C5FF890 4C5D7FA3 ~~ Li 0402 Sc 4C5D7FA3 AR /4C4320F3/4C5D7FA3 @@ -6743,19 +6932,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51000 22000 1800 15 4C5FF890 4C5D80F0 ~~ +Po 48047 21803 1800 15 4C5FF890 4C5D80F0 ~~ Li 0402 Sc 4C5D80F0 AR /4C4320F3/4C5D80F0 @@ -6771,19 +6960,19 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000348" +Ne 137 "N-000338" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 139 "N-000349" +Ne 141 "N-000347" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 50000 24016 0 15 4C5FF890 4C5D7FA1 ~~ +Po 47047 23819 0 15 4C5FF890 4C5D7FA1 ~~ Li 0402 Sc 4C5D7FA1 AR /4C4320F3/4C5D7FA1 @@ -6799,19 +6988,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51772 27756 0 15 4C5FF890 4C5D80ED ~~ +Po 48819 27559 0 15 4C5FF890 4C5D80ED ~~ Li 0402 Sc 4C5D80ED AR /4C4320F3/4C5D80ED @@ -6827,19 +7016,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/Ethernet_Phy/ETH_1.8V" +Ne 35 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0603 -Po 60327 21354 1800 15 4C5FF890 4C5F2CA3 ~~ +Po 60918 22141 1800 15 4C5FF890 4C5F2CA3 ~~ Li 0603 Sc 4C5F2CA3 AR /4C5F1EDC/4C5F2CA3 @@ -6855,19 +7044,19 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 134 "N-000360" +Ne 143 "N-000356" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 58555 12496 1800 15 4C5FF890 4C5F2CA7 ~~ +Po 63977 18307 1800 15 4C5FF890 4C5F2CA7 ~~ Li 0603 Sc 4C5F2CA7 AR /4C5F1EDC/4C5F2CA7 @@ -6883,19 +7072,19 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 135 "N-000361" +Ne 146 "N-000360" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 50000 22500 0 15 4C5FF890 4C5D810A ~~ +Po 47047 22303 0 15 4C5FF890 4C5D810A ~~ Li 0603 Sc 4C5D810A AR /4C4320F3/4C5D810A @@ -6911,19 +7100,19 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/Ethernet_Phy/ETH_A1.8V" +Ne 36 "/Ethernet_Phy/ETH_A1.8V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 44 "/Ethernet_Phy/ETH_PLL1.8V" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 50000 22000 0 15 4C5FF890 4C5D7FB7 ~~ +Po 47047 21803 0 15 4C5FF890 4C5D7FB7 ~~ Li 0603 Sc 4C5D7FB7 AR /4C4320F3/4C5D7FB7 @@ -6939,19 +7128,19 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/Ethernet_Phy/ETH_A3.3V" +Ne 37 "/Ethernet_Phy/ETH_A3.3V" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 56087 25394 0 15 4C5FF890 4C5D80F3 ~~ +Po 53134 25197 0 15 4C5FF890 4C5D80F3 ~~ Li 0603 Sc 4C5D80F3 AR /4C4320F3/4C5D80F3 @@ -6967,19 +7156,19 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "N-000348" +Ne 137 "N-000338" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/Ethernet_Phy/ETH_A1.8V" +Ne 36 "/Ethernet_Phy/ETH_A1.8V" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 64067 24504 1800 15 4C5FF890 4C5F2039 ~~ +Po 59843 22638 1800 15 4C5FF890 4C5F2039 ~~ Li 0603 Sc 4C5F2039 AR /4C5F1EDC/4C5F2039 @@ -6995,19 +7184,19 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 149 "N-000363" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 64067 25488 1800 15 4C5FF890 4C5F2037 ~~ +Po 58465 22441 1800 15 4C5FF890 4C5F2037 ~~ Li 0603 Sc 4C5F2037 AR /4C5F1EDC/4C5F2037 @@ -7023,19 +7212,19 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 149 "N-000363" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 64067 23126 1800 15 4C5FF890 4C5F2033 ~~ +Po 64173 23031 1800 15 4C5FF890 4C5F2033 ~~ Li 0603 Sc 4C5F2033 AR /4C5F1EDC/4C5F2033 @@ -7051,19 +7240,19 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 149 "N-000363" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 63083 18402 1800 15 4C5FF890 4C5D7FA5 ~~ +Po 63674 20567 1800 15 4C5FF890 4C5D7FA5 ~~ Li 0603 Sc 4C5D7FA5 AR /4C4320F3/4C5D7FA5 @@ -7079,19 +7268,19 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/Ethernet_Phy/ETH_A3.3V" +Ne 37 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 50197 25787 0 15 4C5FF890 4C5D7F9F ~~ +Po 47244 25590 0 15 4C5FF890 4C5D7F9F ~~ Li 0603 Sc 4C5D7F9F AR /4C4320F3/4C5D7F9F @@ -7107,19 +7296,19 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "N-000069" +Ne 126 "3.3V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 1210 -Po 72138 25291 1800 15 4C5FF890 4C5F2B55 ~~ +Po 67126 18110 1800 15 4C5FF890 4C5F2B55 ~~ Li 1210 Sc 4C5F2B55 AR /4C5F1EDC/4C5F2B55 @@ -7135,19 +7324,19 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 141 "N-000362" +Ne 144 "N-000357" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 4 "+5V" Po 570 0 $EndPAD $EndMODULE 1210 $MODULE USB-48204 -Po 64067 13496 1800 15 4C5F28A8 4C5F23DD ~~ +Po 57677 16339 1800 15 4C5F28A8 4C5F23DD ~~ Li USB-48204 Sc 4C5F23DD AR /4C5F1EDC/4C5F23DD @@ -7168,56 +7357,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 141 "N-000362" +Ne 148 "N-000362" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 134 "N-000360" +Ne 143 "N-000356" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 135 "N-000361" +Ne 146 "N-000360" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 135 "N-000361" +Ne 146 "N-000360" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 138 "N-000363" +Ne 147 "N-000361" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 138 "N-000363" +Ne 147 "N-000361" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 138 "N-000363" +Ne 147 "N-000361" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 138 "N-000363" +Ne 147 "N-000361" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -7238,14 +7427,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000046" +Ne 130 "N-000045" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7266,19 +7455,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000046" +Ne 130 "N-000045" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "N-000045" +Ne 131 "N-000047" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 63000 28500 0 15 4C5FF890 4C61CCE2 ~~ +Po 62205 29134 0 15 4C5FF890 4C61CCE2 ~~ Li 0402 Sc 4C61CCE2 AR /4C421DD3/4C61CCE2 @@ -7294,19 +7483,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "N-000047" +Ne 129 "N-000044" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "N-000048" +Ne 128 "N-000043" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 64000 28500 0 15 4C5FF890 4C61CCE3 ~~ +Po 63976 28937 0 15 4C5FF890 4C61CCE3 ~~ Li 0402 Sc 4C61CCE3 AR /4C421DD3/4C61CCE3 @@ -7322,14 +7511,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "N-000047" +Ne 129 "N-000044" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7350,14 +7539,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000046" +Ne 130 "N-000045" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7378,14 +7567,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "N-000046" +Ne 130 "N-000045" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "N-000045" +Ne 131 "N-000047" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7406,14 +7595,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "N-000047" +Ne 129 "N-000044" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7434,14 +7623,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7462,14 +7651,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7490,14 +7679,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7518,14 +7707,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7546,14 +7735,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7574,14 +7763,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7602,14 +7791,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7630,14 +7819,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7658,14 +7847,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7686,14 +7875,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7714,19 +7903,19 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 66000 27500 0 15 4C5FF890 4C61CFA0 ~~ +Po 66339 29331 0 15 4C5FF890 4C61CFA0 ~~ Li 0603 Sc 4C61CFA0 AR /4C421DD3/4C61CFA0 @@ -7742,14 +7931,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7770,14 +7959,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "N-000047" +Ne 129 "N-000044" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "N-000048" +Ne 128 "N-000043" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7798,14 +7987,14 @@ $PAD Sh "1" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 570 0 $EndPAD $EndMODULE 1206 @@ -7826,17 +8015,99 @@ $PAD Sh "1" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "+2.5V" +Ne 2 "+2.5V" Po -570 0 $EndPAD $PAD Sh "2" R 355 668 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 1 "GND" +Ne 127 "GND" Po 570 0 $EndPAD $EndMODULE 1206 +$MODULE 0603 +Po 62796 15551 0 15 4C5FF890 4C63FC7B ~~ +Li 0603 +Sc 4C63FC7B +AR /4C5F1EDC/4C63F248 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L5" +T1 0 150 200 200 0 40 N I 25 N"FB" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 145 "N-000358" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 127 "GND" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$MODULE 0603 +Po 63977 19488 0 15 4C5FF890 4C63FC7D ~~ +Li 0603 +Sc 4C63FC7D +AR /4C5F1EDC/4C63F252 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L4" +T1 0 150 200 200 0 40 N I 25 N"FB" +DS -443 227 -443 -227 50 21 +DS -443 -227 443 -227 50 21 +DS 443 -227 443 227 50 21 +DS 443 227 -443 227 50 21 +$PAD +Sh "1" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 144 "N-000357" +Po -294 0 +$EndPAD +$PAD +Sh "2" R 197 354 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 148 "N-000362" +Po 294 0 +$EndPAD +$EndMODULE 0603 +$COTATION +Ge 0 24 0 +Va 21654 +Te "55.001 mm" +Po 56693 42174 600 800 120 0 1 +Sb 0 45866 41534 67520 41534 120 +Sd 0 67520 40748 67520 42814 120 +Sg 0 45866 40748 45866 42814 120 +S1 0 67520 41534 67077 41764 120 +S2 0 67520 41534 67077 41304 120 +S3 0 45866 41534 46309 41764 120 +S4 0 45866 41534 46309 41304 120 +$endCOTATION +$COTATION +Ge 0 24 0 +Va 32087 +Te "81.501 mm" +Po 75442 29232 600 800 120 2700 1 +Sb 0 74802 13189 74802 45276 120 +Sd 0 70276 45276 76082 45276 120 +Sg 0 70276 13189 76082 13189 120 +S1 0 74802 45276 74572 44833 120 +S2 0 74802 45276 75032 44833 120 +S3 0 74802 13189 74572 13632 120 +S4 0 74802 13189 75032 13632 120 +$endCOTATION $TRACK $EndTRACK $ZONE diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index c9dadbc..c6c1f7f 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,5 +1,13 @@ -# EESchema Netlist Version 1.1 created Tue 10 Aug 2010 09:23:17 PM COT +# EESchema Netlist Version 1.1 created Thu 12 Aug 2010 08:51:33 AM COT ( + ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} + ( 1 N-000357 ) + ( 2 N-000362 ) + ) + ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} + ( 1 N-000358 ) + ( 2 GND ) + ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} ( 1 N-000361 ) ( 2 GND ) @@ -9,533 +17,533 @@ ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000359 ) + ( 1 N-000360 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000358 ) + ( 1 N-000356 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000360 ) - ( 2 ? ) + ( 1 N-000357 ) + ( 2 +5V ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} ( S1 N-000361 ) ( S2 N-000361 ) ( S3 N-000361 ) ( S4 N-000361 ) - ( 1 N-000360 ) - ( 2 N-000358 ) - ( 3 N-000359 ) - ( 4 GND ) + ( 1 N-000362 ) + ( 2 N-000356 ) + ( 3 N-000360 ) + ( 4 N-000358 ) ) ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} - ( 1 N-000069 ) + ( 1 N-000363 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} - ( 1 N-000069 ) + ( 1 N-000363 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} - ( 1 N-000069 ) + ( 1 N-000363 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} - ( 1 N-000069 ) - ( 2 /FPGA_Spartan6/USBA_SPD ) - ( 3 /FPGA_Spartan6/USBA_RCV ) + ( 1 +2.5V ) + ( 2 /USB/USBA_SPD ) + ( 3 /USB/USBA_RCV ) ( 4 /FPGA_Spartan6/USBA_VP ) ( 5 /FPGA_Spartan6/USBA_VM ) ( 7 GND ) ( 8 GND ) ( 9 /FPGA_Spartan6/USBA_OE_N ) - ( 10 N-000358 ) - ( 11 N-000359 ) - ( 12 N-000069 ) - ( 14 N-000069 ) + ( 10 N-000356 ) + ( 11 N-000360 ) + ( 12 3.3V ) + ( 14 3.3V ) ) ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} - ( H9 +2.5V ) - ( U11 +2.5V ) - ( F11 +2.5V ) - ( R6 +2.5V ) - ( M15 +2.5V ) - ( V6 +2.5V ) - ( G12 +2.5V ) - ( H15 +2.5V ) - ( D16 +2.5V ) - ( K15 +2.5V ) - ( R12 +2.5V ) - ( N8 +2.5V ) - ( R10 +2.5V ) - ( L8 +2.5V ) - ( N10 +1.2V ) - ( P11 +1.2V ) - ( P13 +1.2V ) - ( P9 +1.2V ) - ( R14 +1.2V ) - ( N12 +1.2V ) - ( J10 +1.2V ) - ( J12 +1.2V ) - ( J14 +1.2V ) - ( J8 +1.2V ) - ( K11 +1.2V ) - ( K13 +1.2V ) - ( K9 +1.2V ) - ( L10 +1.2V ) - ( L12 +1.2V ) - ( L14 +1.2V ) - ( M11 +1.2V ) - ( M13 +1.2V ) - ( M9 +1.2V ) - ( N14 +1.2V ) - ( G13 ? ) - ( G8 ? ) - ( G9 ? ) - ( H10 ? ) - ( H11 ? ) - ( H12 ? ) - ( H13 ? ) - ( H14 ? ) - ( P16 ? ) - ( D13 ? ) - ( AA1 ? ) - ( N15 ? ) - ( G15 ? ) - ( E18 ? ) - ( A19 ? ) - ( C18 ? ) - ( G11 ? ) - ( F9 ? ) - ( F8 ? ) - ( F15 ? ) - ( F14 ? ) - ( F13 ? ) - ( F12 ? ) - ( F10 ? ) - ( E8 ? ) - ( E14 ? ) - ( E12 ? ) - ( E10 ? ) - ( D12 ? ) - ( P15 ? ) - ( R17 ? ) - ( Y22 ? ) - ( P10 GND ) - ( V10 GND ) - ( M10 GND ) - ( K10 GND ) - ( L13 GND ) - ( A1 GND ) - ( N13 GND ) - ( A22 GND ) - ( R5 GND ) - ( AA13 GND ) - ( W19 GND ) - ( AA17 GND ) - ( K14 GND ) - ( AA5 GND ) - ( L5 GND ) - ( AA9 GND ) - ( M14 GND ) - ( AB1 GND ) - ( N2 GND ) - ( AB22 GND ) - ( P14 GND ) - ( B13 GND ) - ( U21 GND ) - ( B17 GND ) - ( V4 GND ) - ( B5 GND ) - ( J9 GND ) - ( B9 GND ) - ( K12 ? ) - ( D18 GND ) - ( L11 GND ) - ( D4 GND ) - ( L18 GND ) - ( E11 ? ) - ( L9 GND ) - ( E15 GND ) - ( M12 GND ) - ( E2 GND ) - ( N11 GND ) - ( E21 GND ) - ( N17 GND ) - ( E7 GND ) - ( N21 GND ) - ( G18 GND ) - ( P12 GND ) - ( G5 GND ) - ( R18 GND ) - ( H7 GND ) - ( U2 GND ) - ( J11 GND ) - ( U7 GND ) - ( J13 GND ) - ( V14 GND ) - ( J15 GND ) - ( W16 GND ) - ( J2 GND ) - ( W7 GND ) - ( J21 GND ) - ( N9 GND ) - ( AA15 N-000101 ) - ( V16 N-000101 ) - ( T13 N-000101 ) - ( V8 N-000101 ) - ( V12 N-000101 ) - ( AA3 N-000101 ) - ( T9 N-000101 ) - ( AA19 N-000101 ) - ( AA11 N-000101 ) - ( W5 N-000101 ) - ( AA7 N-000101 ) - ( AA12 ? ) - ( AB12 ? ) - ( Y11 ? ) - ( AB11 ? ) - ( R11 ? ) - ( T11 ? ) - ( AA10 ? ) - ( AB10 ? ) - ( V11 ? ) - ( W11 ? ) - ( Y9 ? ) - ( AB9 ? ) - ( W10 ? ) - ( Y10 ? ) - ( AA8 ? ) - ( AB8 ? ) - ( W8 ? ) - ( V7 ? ) - ( W9 ? ) - ( Y8 ? ) - ( Y7 ? ) - ( AB7 ? ) - ( AA6 ? ) - ( AB6 ? ) - ( U9 ? ) - ( V9 ? ) - ( T8 ? ) - ( U8 ? ) - ( T10 ? ) - ( U10 ? ) - ( W6 ? ) - ( Y6 ? ) - ( Y5 ? ) - ( AB5 ? ) - ( AA4 ? ) - ( AB4 ? ) - ( Y3 ? ) - ( AB3 ? ) - ( R9 ? ) - ( R8 ? ) - ( T7 ? ) - ( R7 ? ) - ( W4 ? ) - ( Y4 ? ) - ( U6 ? ) - ( V5 ? ) - ( AA2 ? ) - ( AB2 ? ) - ( T6 ? ) - ( T5 ? ) - ( AB13 ? ) - ( Y13 ? ) - ( Y12 ? ) - ( W12 ? ) - ( R13 ? ) - ( T14 ? ) - ( U12 ? ) - ( T12 ? ) - ( AB15 ? ) - ( Y15 ? ) - ( Y14 ? ) - ( W14 ? ) - ( AB16 ? ) - ( AA16 ? ) - ( W13 ? ) - ( V13 ? ) - ( W15 ? ) - ( Y16 ? ) - ( AB14 ? ) - ( AA14 ? ) - ( AB17 ? ) - ( Y17 ? ) - ( AB18 ? ) - ( AA18 ? ) - ( V15 ? ) - ( U15 ? ) - ( U13 ? ) - ( U14 ? ) - ( W17 ? ) - ( V17 ? ) - ( R15 ? ) - ( R16 ? ) - ( V18 ? ) - ( V19 ? ) - ( U16 ? ) - ( U17 ? ) - ( T15 ? ) - ( T16 ? ) - ( Y18 ? ) - ( W18 ? ) - ( AB19 ? ) - ( Y19 ? ) - ( T17 ? ) - ( T18 ? ) - ( AB20 ? ) - ( AA20 ? ) - ( AB21 ? ) - ( AA21 ? ) - ( AA22 ? ) - ( W2 +2.5V ) - ( L2 +2.5V ) + ( P7 ? ) + ( N7 ? ) + ( M7 ? ) ( L7 +2.5V ) - ( C2 +2.5V ) - ( N5 +2.5V ) - ( R2 +2.5V ) - ( U5 +2.5V ) - ( G2 +2.5V ) - ( F4 +2.5V ) - ( F6 +2.5V ) - ( J5 +2.5V ) - ( M3 /DDR_Banks/M0_UDM ) - ( L4 /DDR_Banks/M0_LDM ) - ( K5 /DDR_Banks/M0_RAS# ) - ( K4 /DDR_Banks/M0_CAS# ) - ( K3 /DDR_Banks/M0_A5 ) - ( J4 /DDR_Banks/M0_A6 ) - ( K6 /DDR_Banks/M0_A3 ) - ( J6 ? ) - ( H4 /DDR_Banks/M0_CLK ) - ( H3 /DDR_Banks/M0_CLK# ) - ( H2 /DDR_Banks/M0_A0 ) - ( H1 /DDR_Banks/M0_A1 ) - ( G3 /DDR_Banks/M0_BA0 ) - ( G1 /DDR_Banks/M0_BA1 ) - ( H6 /DDR_Banks/M0_A7 ) - ( H5 /DDR_Banks/M0_A2 ) - ( F2 /DDR_Banks/M0_WE# ) - ( F1 ? ) - ( G4 /DDR_Banks/M0_A10 ) - ( F3 /DDR_Banks/M0_A4 ) - ( E3 /DDR_Banks/M0_A8 ) - ( E1 /DDR_Banks/M0_A9 ) - ( D2 /DDR_Banks/M0_CKE ) - ( D1 /DDR_Banks/M0_A12 ) - ( C3 ? ) - ( C1 /DDR_Banks/M0_A11 ) - ( G6 ? ) - ( F5 ? ) ( K7 ? ) - ( K8 ? ) - ( D5 ? ) - ( E4 ? ) ( J7 ? ) - ( H8 ? ) - ( B2 ? ) - ( B1 ? ) ( G7 ? ) ( F7 ? ) - ( D3 ? ) - ( C4 ? ) - ( E5 ? ) - ( E6 ? ) - ( A2 ? ) - ( B3 ? ) - ( J1 /DDR_Banks/M0_DQ5 ) - ( J3 /DDR_Banks/M0_DQ4 ) - ( K1 /DDR_Banks/M0_DQ7 ) - ( K2 /DDR_Banks/M0_DQ6 ) - ( L1 ? ) - ( L3 /DDR_Banks/M0_LDQS ) - ( M1 /DDR_Banks/M0_DQ3 ) - ( M2 /DDR_Banks/M0_DQ2 ) - ( N1 /DDR_Banks/M0_DQ1 ) - ( N3 /DDR_Banks/M0_DQ0 ) - ( P1 /DDR_Banks/M0_DQ9 ) - ( P2 /DDR_Banks/M0_DQ8 ) - ( R1 /DDR_Banks/M0_DQ11 ) - ( R3 /DDR_Banks/M0_DQ10 ) - ( T1 ? ) - ( T2 /DDR_Banks/M0_UDQS ) - ( U1 /DDR_Banks/M0_DQ13 ) - ( U3 /DDR_Banks/M0_DQ12 ) - ( V1 /DDR_Banks/M0_DQ15 ) - ( V2 /DDR_Banks/M0_DQ14 ) - ( M4 ? ) - ( M5 ? ) - ( N4 ? ) - ( P3 ? ) - ( L6 ? ) - ( M6 ? ) - ( P4 ? ) - ( R4 ? ) - ( M8 ? ) - ( M7 ? ) - ( N7 ? ) - ( N6 ? ) - ( V3 ? ) - ( U4 ? ) - ( T3 ? ) - ( T4 ? ) - ( P5 ? ) ( P6 ? ) - ( P7 ? ) - ( P8 ? ) - ( W1 ? ) - ( W3 ? ) - ( Y1 ? ) - ( W21 +2.5V ) - ( C21 +2.5V ) - ( G21 +2.5V ) - ( J18 +2.5V ) - ( L16 +2.5V ) - ( L21 +2.5V ) - ( N18 +2.5V ) - ( R21 +2.5V ) - ( U18 +2.5V ) - ( E19 +2.5V ) - ( L19 /DDR_Banks/M1_LDM ) - ( J20 /DDR_Banks/M1_DQ4 ) - ( J22 /DDR_Banks/M1_DQ5 ) - ( K21 /DDR_Banks/M1_DQ6 ) - ( K22 /DDR_Banks/M1_DQ7 ) - ( L20 /DDR_Banks/M1_LDQS ) - ( L22 ? ) - ( M21 /DDR_Banks/M1_DQ2 ) - ( M22 /DDR_Banks/M1_DQ3 ) - ( N20 /DDR_Banks/M1_DQ0 ) - ( N22 /DDR_Banks/M1_DQ1 ) - ( P21 /DDR_Banks/M1_DQ8 ) - ( P22 /DDR_Banks/M1_DQ9 ) - ( R20 /DDR_Banks/M1_DQ10 ) - ( R22 /DDR_Banks/M1_DQ11 ) - ( T21 /DDR_Banks/M1_UDQS ) - ( T22 ? ) - ( U20 /DDR_Banks/M1_DQ12 ) - ( U22 /DDR_Banks/M1_DQ13 ) - ( V21 /DDR_Banks/M1_DQ14 ) - ( V22 /DDR_Banks/M1_DQ15 ) - ( M19 ? ) - ( N19 ? ) - ( M16 ? ) - ( L15 ? ) - ( P19 ? ) - ( P20 ? ) - ( W20 ? ) - ( W22 ? ) - ( L17 ? ) - ( K18 ? ) - ( U19 ? ) - ( V20 ? ) - ( M17 ? ) - ( M18 ? ) - ( P17 ? ) - ( N16 ? ) - ( P18 ? ) - ( R19 ? ) - ( T19 ? ) - ( T20 ? ) - ( M20 /DDR_Banks/M1_UDM ) - ( H22 /DDR_Banks/M1_CAS# ) + ( N6 ? ) + ( M6 ? ) + ( L6 ? ) + ( K6 /FPGA_Spartan6/M0_A3 ) + ( J6 ? ) + ( H6 /DDR_Banks/M0_A7 ) + ( G6 ? ) + ( F6 +2.5V ) + ( E6 ? ) + ( U5 +2.5V ) + ( P5 ? ) + ( N5 +2.5V ) + ( M5 ? ) + ( K5 /FPGA_Spartan6/M0_RAS# ) + ( J5 +2.5V ) + ( H5 /FPGA_Spartan6/M0_A2 ) + ( F5 ? ) + ( E5 ? ) + ( D5 ? ) + ( U4 ? ) ( H21 /DDR_Banks/M1_RAS# ) - ( K19 /DDR_Banks/M1_A6 ) - ( K20 /DDR_Banks/M1_A5 ) - ( G22 ? ) - ( G20 /DDR_Banks/M1_A3 ) - ( J19 /DDR_Banks/M1_CLK# ) - ( H20 /DDR_Banks/M1_CLK ) - ( F22 /DDR_Banks/M1_A1 ) - ( F21 /DDR_Banks/M1_A0 ) - ( K17 /DDR_Banks/M1_BA1 ) - ( J17 /DDR_Banks/M1_BA0 ) - ( E22 /DDR_Banks/M1_A2 ) - ( E20 /DDR_Banks/M1_A7 ) - ( H18 ? ) - ( H19 /DDR_Banks/M1_WE# ) - ( F20 /DDR_Banks/M1_A4 ) - ( G19 /DDR_Banks/M1_A10 ) - ( C22 /DDR_Banks/M1_A9 ) - ( C20 /DDR_Banks/M1_A8 ) - ( D22 /DDR_Banks/M1_A12 ) + ( G21 +2.5V ) + ( F21 /FPGA_Spartan6/M1_A0 ) ( D21 /DDR_Banks/M1_CKE ) - ( F19 /DDR_Banks/M1_A11 ) - ( F18 ? ) - ( D20 ? ) - ( D19 ? ) - ( H17 ? ) - ( H16 ? ) - ( J16 ? ) - ( K16 ? ) - ( A21 ? ) - ( A20 ? ) - ( B22 ? ) + ( C21 +2.5V ) ( B21 ? ) - ( F17 ? ) - ( F16 ? ) - ( G17 ? ) - ( G16 ? ) + ( A21 ? ) + ( W20 ? ) + ( V20 ? ) + ( U20 /FPGA_Spartan6/M1_DQ12 ) + ( T20 ? ) + ( R20 /FPGA_Spartan6/M1_DQ10 ) + ( P20 ? ) + ( N20 /DDR_Banks/M1_DQ0 ) + ( M20 /FPGA_Spartan6/M1_UDM ) + ( L20 /FPGA_Spartan6/M1_LDQS ) + ( K20 /DDR_Banks/M1_A5 ) + ( J20 /FPGA_Spartan6/M1_DQ4 ) + ( H20 /FPGA_Spartan6/M1_CLK ) + ( G20 /FPGA_Spartan6/M1_A3 ) + ( F20 /DDR_Banks/M1_A4 ) + ( E20 /FPGA_Spartan6/M1_A7 ) + ( D20 ? ) + ( C20 /FPGA_Spartan6/M1_A8 ) ( B20 ? ) - ( B4 +3.3V ) - ( B7 +3.3V ) - ( E13 +3.3V ) - ( E17 +3.3V ) + ( A20 ? ) + ( P8 ? ) + ( M8 ? ) + ( K8 ? ) + ( H8 ? ) + ( B3 ? ) + ( W2 +2.5V ) + ( V2 /FPGA_Spartan6/M0_DQ14 ) + ( T2 /DDR_Banks/M0_UDQS ) + ( R2 +2.5V ) + ( P2 /FPGA_Spartan6/M0_DQ8 ) + ( M2 /FPGA_Spartan6/M0_DQ2 ) + ( L2 +2.5V ) + ( K2 /DDR_Banks/M0_DQ6 ) + ( H2 /FPGA_Spartan6/M0_A0 ) + ( G2 +2.5V ) + ( F2 /FPGA_Spartan6/M0_WE# ) + ( D2 /FPGA_Spartan6/M0_CKE ) + ( C2 +2.5V ) + ( B2 ? ) + ( A2 ? ) + ( Y1 ? ) + ( W1 ? ) + ( V1 /FPGA_Spartan6/M0_DQ15 ) + ( U1 /DDR_Banks/M0_DQ13 ) + ( T1 ? ) + ( R1 /FPGA_Spartan6/M0_DQ11 ) + ( P1 /DDR_Banks/M0_DQ9 ) + ( N1 /FPGA_Spartan6/M0_DQ1 ) + ( M1 /FPGA_Spartan6/M0_DQ3 ) + ( L1 ? ) + ( K1 /FPGA_Spartan6/M0_DQ7 ) + ( J1 /DDR_Banks/M0_DQ5 ) + ( H1 /FPGA_Spartan6/M0_A1 ) + ( G1 /FPGA_Spartan6/M0_BA1 ) + ( T4 ? ) + ( R4 ? ) + ( P4 ? ) + ( N4 ? ) + ( M4 ? ) + ( L4 /DDR_Banks/M0_LDM ) + ( K4 /FPGA_Spartan6/M0_CAS# ) + ( J4 /FPGA_Spartan6/M0_A6 ) + ( H4 /DDR_Banks/M0_CLK ) + ( G4 /DDR_Banks/M0_A10 ) + ( F4 +2.5V ) + ( E4 ? ) + ( C4 ? ) + ( W3 ? ) + ( V3 ? ) + ( U3 /FPGA_Spartan6/M0_DQ12 ) + ( T3 ? ) + ( R3 /DDR_Banks/M0_DQ10 ) + ( P3 ? ) + ( N3 /FPGA_Spartan6/M0_DQ0 ) + ( M3 /DDR_Banks/M0_UDM ) + ( L3 /DDR_Banks/M0_LDQS ) + ( K3 /DDR_Banks/M0_A5 ) + ( J3 /FPGA_Spartan6/M0_DQ4 ) + ( H3 /FPGA_Spartan6/M0_CLK# ) + ( G3 /DDR_Banks/M0_BA0 ) + ( F3 /FPGA_Spartan6/M0_A4 ) + ( E3 /FPGA_Spartan6/M0_A8 ) + ( D3 ? ) + ( C3 ? ) ( G10 +3.3V ) - ( G14 +3.3V ) - ( B11 +3.3V ) - ( B15 +3.3V ) - ( B19 +3.3V ) + ( D10 /Ethernet_Phy/ETH_RXC ) + ( C10 /FPGA_Spartan6/ETH_CLK ) + ( B10 /Ethernet_Phy/ETH_CRS ) + ( A10 /Ethernet_Phy/ETH_COL ) ( E9 +3.3V ) - ( A11 ? ) - ( D11 ? ) - ( C12 ? ) - ( B12 ? ) - ( A12 ? ) - ( C13 ? ) - ( A13 ? ) + ( D9 /Ethernet_Phy/ETH_TXEN ) + ( C9 /Ethernet_Phy/ETH_TXD1 ) + ( A9 /Ethernet_Phy/ETH_TXD2 ) + ( D8 /Ethernet_Phy/ETH_TXC ) + ( C8 /FPGA_Spartan6/ETH_TXD0 ) + ( B8 /Ethernet_Phy/ETH_RXER ) + ( A8 /Ethernet_Phy/ETH_TXER ) + ( D7 /FPGA_Spartan6/ETH_TXD3 ) + ( C7 /Ethernet_Phy/ETH_RXD0 ) + ( B7 +3.3V ) + ( A7 /Ethernet_Phy/ETH_RXDV ) + ( D6 /FPGA_Spartan6/ETH_RESET_N ) + ( C6 /FPGA_Spartan6/ETH_RXD3 ) + ( B6 /FPGA_Spartan6/ETH_RXD2 ) + ( A6 /Ethernet_Phy/ETH_RXD1 ) + ( C5 /Ethernet_Phy/ETH_MDC ) + ( A5 /FPGA_Spartan6/ETH_MDIO ) + ( B4 +3.3V ) + ( A4 /Ethernet_Phy/ETH_INT ) + ( U19 ? ) + ( T19 ? ) + ( R19 ? ) + ( P19 ? ) + ( N19 ? ) + ( B19 +3.3V ) + ( B18 /FPGA_Spartan6/USBA_VP ) + ( A18 /USB/USBA_RCV ) + ( E17 +3.3V ) + ( D17 /USB/USBA_SPD ) + ( C17 /Non_volatile_memories/SD_CMD ) + ( A17 /FPGA_Spartan6/USBA_VM ) + ( E16 /FPGA_Spartan6/USBA_OE_N ) + ( C16 /Non_volatile_memories/SD_DAT1 ) + ( B16 /Non_volatile_memories/SD_DAT0 ) + ( A16 /Non_volatile_memories/SD_CLK ) + ( D15 /Non_volatile_memories/SD_DAT2 ) + ( C15 ? ) + ( B15 +3.3V ) + ( A15 /FPGA_Spartan6/SD_DAT3 ) + ( G14 +3.3V ) ( D14 ? ) ( C14 ? ) ( B14 ? ) ( A14 ? ) - ( C15 ? ) - ( A15 /Non_volatile_memories/SD_DAT3 ) - ( D15 /Non_volatile_memories/SD_DAT2 ) - ( C16 /Non_volatile_memories/SD_DAT1 ) - ( B16 /Non_volatile_memories/SD_DAT0 ) - ( A16 /Non_volatile_memories/SD_CLK ) - ( C17 /Non_volatile_memories/SD_CMD ) - ( A17 /FPGA_Spartan6/USBA_VM ) - ( B18 /FPGA_Spartan6/USBA_VP ) - ( A18 /FPGA_Spartan6/USBA_RCV ) - ( E16 /FPGA_Spartan6/USBA_OE_N ) - ( D17 /FPGA_Spartan6/USBA_SPD ) + ( E13 +3.3V ) + ( C13 ? ) + ( A13 ? ) + ( C12 ? ) + ( B12 ? ) + ( A12 ? ) + ( D11 ? ) ( C11 ? ) - ( A10 /FPGA_Spartan6/ETH_COL ) - ( B10 /FPGA_Spartan6/ETH_CRS ) - ( C10 /FPGA_Spartan6/ETH_CLK ) - ( D10 /FPGA_Spartan6/ETH_RXC ) - ( D8 /FPGA_Spartan6/ETH_TXC ) - ( D7 /FPGA_Spartan6/ETH_TXD3 ) - ( A9 /FPGA_Spartan6/ETH_TXD2 ) - ( C9 /FPGA_Spartan6/ETH_TXD1 ) - ( C8 /FPGA_Spartan6/ETH_TXD0 ) - ( D9 /FPGA_Spartan6/ETH_TXEN ) - ( A8 /FPGA_Spartan6/ETH_TXER ) - ( B8 /FPGA_Spartan6/ETH_RXER ) - ( A7 /FPGA_Spartan6/ETH_RXDV ) - ( C7 /FPGA_Spartan6/ETH_RXD0 ) - ( A6 /FPGA_Spartan6/ETH_RXD1 ) - ( B6 /FPGA_Spartan6/ETH_RXD2 ) - ( C6 /FPGA_Spartan6/ETH_RXD3 ) - ( D6 /FPGA_Spartan6/ETH_RESET_N ) - ( A5 /FPGA_Spartan6/ETH_MDIO ) - ( C5 /FPGA_Spartan6/ETH_MDC ) - ( A4 /FPGA_Spartan6/ETH_INT ) + ( B11 +3.3V ) + ( A11 ? ) + ( H16 ? ) + ( G16 ? ) + ( F16 ? ) + ( L15 ? ) + ( W22 ? ) + ( V22 /FPGA_Spartan6/M1_DQ15 ) + ( U22 /DDR_Banks/M1_DQ13 ) + ( T22 ? ) + ( R22 /FPGA_Spartan6/M1_DQ11 ) + ( P22 /FPGA_Spartan6/M1_DQ9 ) + ( N22 /FPGA_Spartan6/M1_DQ1 ) + ( M22 /DDR_Banks/M1_DQ3 ) + ( L22 ? ) + ( K22 /FPGA_Spartan6/M1_DQ7 ) + ( J22 /DDR_Banks/M1_DQ5 ) + ( H22 /DDR_Banks/M1_CAS# ) + ( G22 ? ) + ( F22 /FPGA_Spartan6/M1_A1 ) + ( E22 /FPGA_Spartan6/M1_A2 ) + ( D22 /FPGA_Spartan6/M1_A12 ) + ( C22 /DDR_Banks/M1_A9 ) + ( B22 ? ) + ( W21 +2.5V ) + ( V21 /FPGA_Spartan6/M1_DQ14 ) + ( T21 /FPGA_Spartan6/M1_UDQS ) + ( R21 +2.5V ) + ( P21 /FPGA_Spartan6/M1_DQ8 ) + ( M21 /FPGA_Spartan6/M1_DQ2 ) + ( L21 +2.5V ) + ( K21 /DDR_Banks/M1_DQ6 ) + ( M19 ? ) + ( L19 /DDR_Banks/M1_LDM ) + ( K19 /DDR_Banks/M1_A6 ) + ( J19 /FPGA_Spartan6/M1_CLK# ) + ( H19 /FPGA_Spartan6/M1_WE# ) + ( G19 /DDR_Banks/M1_A10 ) + ( F19 /DDR_Banks/M1_A11 ) + ( E19 +2.5V ) + ( D19 ? ) + ( U18 +2.5V ) + ( P18 ? ) + ( N18 +2.5V ) + ( M18 ? ) + ( K18 ? ) + ( J18 +2.5V ) + ( H18 ? ) + ( F18 ? ) + ( P17 ? ) + ( M17 ? ) + ( L17 ? ) + ( K17 /FPGA_Spartan6/M1_BA1 ) + ( J17 /DDR_Banks/M1_BA0 ) + ( H17 ? ) + ( G17 ? ) + ( F17 ? ) + ( N16 ? ) + ( M16 ? ) + ( L16 +2.5V ) + ( K16 ? ) + ( J16 ? ) + ( J14 +1.2V ) + ( H14 ? ) + ( F14 ? ) + ( E14 ? ) + ( P13 +1.2V ) + ( N13 GND ) + ( M13 +1.2V ) + ( L13 GND ) + ( K13 +1.2V ) + ( J13 GND ) + ( H13 ? ) + ( G13 ? ) + ( F13 ? ) + ( D13 ? ) + ( B13 GND ) + ( Y22 ? ) + ( A22 GND ) + ( R12 +2.5V ) + ( P12 GND ) + ( N12 +1.2V ) + ( M12 GND ) + ( L12 +1.2V ) + ( K12 ? ) + ( J12 +1.2V ) + ( H12 ? ) + ( G12 +2.5V ) + ( F12 ? ) + ( E12 ? ) + ( D12 ? ) + ( AB1 GND ) + ( A19 ? ) + ( R18 GND ) + ( L18 GND ) + ( G18 GND ) + ( E18 ? ) + ( D18 GND ) + ( C18 ? ) + ( R17 ? ) + ( N17 GND ) + ( B17 GND ) + ( W16 GND ) + ( P16 ? ) + ( D16 +2.5V ) + ( AA5 GND ) + ( P15 ? ) + ( N15 ? ) + ( M15 +2.5V ) + ( K15 +2.5V ) + ( J15 GND ) + ( H15 +2.5V ) + ( G15 ? ) + ( F15 ? ) + ( E15 GND ) + ( V14 GND ) + ( R14 +1.2V ) + ( P14 GND ) + ( N14 +1.2V ) + ( M14 GND ) + ( L14 +1.2V ) + ( K14 GND ) + ( L9 GND ) + ( K9 +1.2V ) + ( J9 GND ) + ( H9 +2.5V ) + ( G9 ? ) + ( F9 ? ) + ( B9 GND ) + ( N8 +2.5V ) + ( L8 +2.5V ) + ( J8 +1.2V ) + ( G8 ? ) + ( F8 ? ) + ( E8 ? ) + ( W7 GND ) + ( U7 GND ) + ( H7 GND ) + ( E7 GND ) + ( V6 +2.5V ) + ( R6 +2.5V ) + ( R5 GND ) + ( L5 GND ) + ( G5 GND ) + ( B5 GND ) + ( V4 GND ) + ( D4 GND ) + ( U2 GND ) + ( N2 GND ) + ( J2 GND ) + ( E2 GND ) + ( A1 GND ) + ( AA1 ? ) + ( U21 GND ) + ( N21 GND ) + ( J21 GND ) + ( E21 GND ) + ( U11 +2.5V ) + ( P11 +1.2V ) + ( N11 GND ) + ( M11 +1.2V ) + ( L11 GND ) + ( K11 +1.2V ) + ( J11 GND ) + ( H11 ? ) + ( G11 ? ) + ( F11 +2.5V ) + ( E11 ? ) + ( V10 GND ) + ( R10 +2.5V ) + ( P10 GND ) + ( N10 +1.2V ) + ( M10 GND ) + ( L10 +1.2V ) + ( K10 GND ) + ( J10 +1.2V ) + ( H10 ? ) + ( F10 ? ) + ( E10 ? ) + ( P9 +1.2V ) + ( N9 GND ) + ( M9 +1.2V ) + ( V19 ? ) + ( AB8 ? ) + ( AA8 ? ) + ( Y18 ? ) + ( W18 ? ) + ( V18 ? ) + ( T18 ? ) + ( AB7 ? ) + ( AA7 N-000101 ) + ( Y17 ? ) + ( W17 ? ) + ( V17 ? ) + ( U17 ? ) + ( T17 ? ) + ( AB6 ? ) + ( AA6 ? ) + ( Y16 ? ) + ( V16 N-000101 ) + ( U16 ? ) + ( T16 ? ) + ( R16 ? ) + ( AB5 ? ) + ( Y15 ? ) + ( W15 ? ) + ( V15 ? ) + ( U15 ? ) + ( T15 ? ) + ( R15 ? ) + ( AB4 ? ) + ( AA4 ? ) + ( F1 ? ) + ( E1 /FPGA_Spartan6/M0_A9 ) + ( D1 /FPGA_Spartan6/M0_A12 ) + ( C1 /FPGA_Spartan6/M0_A11 ) + ( B1 ? ) + ( AB19 ? ) + ( AA19 N-000101 ) + ( AB18 ? ) + ( AA18 ? ) + ( AB17 ? ) + ( AB16 ? ) + ( AA16 ? ) + ( AB15 ? ) + ( AA15 N-000101 ) + ( AB14 ? ) + ( AA14 ? ) + ( AB13 ? ) + ( AA22 ? ) + ( AB12 ? ) + ( AA12 ? ) + ( AB21 ? ) + ( AA21 ? ) + ( AB11 ? ) + ( AA11 N-000101 ) + ( AB20 ? ) + ( AA20 ? ) + ( AB10 ? ) + ( AA10 ? ) + ( AB9 ? ) + ( Y19 ? ) + ( V9 ? ) + ( U9 ? ) + ( T9 N-000101 ) + ( R9 ? ) + ( Y8 ? ) + ( W8 ? ) + ( V8 N-000101 ) + ( U8 ? ) + ( T8 ? ) + ( R8 ? ) + ( Y7 ? ) + ( V7 ? ) + ( T7 ? ) + ( R7 ? ) + ( Y6 ? ) + ( W6 ? ) + ( U6 ? ) + ( T6 ? ) + ( Y5 ? ) + ( W5 N-000101 ) + ( V5 ? ) + ( T5 ? ) + ( Y4 ? ) + ( W4 ? ) + ( Y3 ? ) + ( AA17 GND ) + ( AA13 GND ) + ( AB22 GND ) + ( AA9 GND ) + ( W19 GND ) + ( Y14 ? ) + ( W14 ? ) + ( U14 ? ) + ( T14 ? ) + ( AB3 ? ) + ( AA3 N-000101 ) + ( Y13 ? ) + ( W13 ? ) + ( V13 ? ) + ( U13 ? ) + ( T13 N-000101 ) + ( R13 ? ) + ( AB2 ? ) + ( AA2 ? ) + ( Y12 ? ) + ( W12 ? ) + ( V12 N-000101 ) + ( U12 ? ) + ( T12 ? ) + ( Y11 ? ) + ( W11 ? ) + ( V11 ? ) + ( T11 ? ) + ( R11 ? ) + ( Y10 ? ) + ( W10 ? ) + ( U10 ? ) + ( T10 ? ) + ( Y9 ? ) + ( W9 ? ) ) ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} ( 1 /Ethernet_Phy/ETH_PLL1.8V ) @@ -550,11 +558,11 @@ ( 2 N-000347 ) ) ( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR} - ( 1 N-000346 ) + ( 1 N-000338 ) ( 2 /Ethernet_Phy/ETH_A1.8V ) ) ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} - ( 1 N-000346 ) + ( 1 N-000338 ) ( 2 N-000347 ) ) ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} @@ -562,7 +570,7 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7FB7 $noname L2 FB {Lib=INDUCTOR} - ( 1 N-000069 ) + ( 1 3.3V ) ( 2 /Ethernet_Phy/ETH_A3.3V ) ) ( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C} @@ -574,83 +582,83 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C} - ( 1 N-000069 ) + ( 1 3.3V ) ( 2 GND ) ) ( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C} - ( 1 N-000069 ) + ( 1 3.3V ) ( 2 GND ) ) ( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C} - ( 1 N-000069 ) + ( 1 3.3V ) ( 2 GND ) ) ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} ( 1 /FPGA_Spartan6/ETH_MDIO ) - ( 2 N-000069 ) + ( 2 3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000336 ) + ( 1 N-000344 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} - ( 1 N-000069 ) + ( 1 3.3V ) ( 2 GND ) ) ( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C} - ( 1 N-000069 ) + ( 1 3.3V ) ( 2 GND ) ) ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000345 ) + ( 1 N-000336 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000345 ) + ( 1 N-000336 ) ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} ( 1 /FPGA_Spartan6/ETH_MDIO ) - ( 2 /FPGA_Spartan6/ETH_MDC ) + ( 2 /Ethernet_Phy/ETH_MDC ) ( 3 /FPGA_Spartan6/ETH_RXD3 ) ( 4 /FPGA_Spartan6/ETH_RXD2 ) - ( 5 /FPGA_Spartan6/ETH_RXD1 ) - ( 6 /FPGA_Spartan6/ETH_RXD0 ) - ( 7 N-000069 ) + ( 5 /Ethernet_Phy/ETH_RXD1 ) + ( 6 /Ethernet_Phy/ETH_RXD0 ) + ( 7 3.3V ) ( 8 GND ) - ( 9 /FPGA_Spartan6/ETH_RXDV ) - ( 10 /FPGA_Spartan6/ETH_RXC ) - ( 11 /FPGA_Spartan6/ETH_RXER ) + ( 9 /Ethernet_Phy/ETH_RXDV ) + ( 10 /Ethernet_Phy/ETH_RXC ) + ( 11 /Ethernet_Phy/ETH_RXER ) ( 12 GND ) ( 13 /Ethernet_Phy/ETH_1.8V ) - ( 14 /FPGA_Spartan6/ETH_TXER ) - ( 15 /FPGA_Spartan6/ETH_TXC ) - ( 16 /FPGA_Spartan6/ETH_TXEN ) + ( 14 /Ethernet_Phy/ETH_TXER ) + ( 15 /Ethernet_Phy/ETH_TXC ) + ( 16 /Ethernet_Phy/ETH_TXEN ) ( 17 /FPGA_Spartan6/ETH_TXD0 ) - ( 18 /FPGA_Spartan6/ETH_TXD1 ) - ( 19 /FPGA_Spartan6/ETH_TXD2 ) + ( 18 /Ethernet_Phy/ETH_TXD1 ) + ( 19 /Ethernet_Phy/ETH_TXD2 ) ( 20 /FPGA_Spartan6/ETH_TXD3 ) - ( 21 /FPGA_Spartan6/ETH_COL ) - ( 22 /FPGA_Spartan6/ETH_CRS ) + ( 21 /Ethernet_Phy/ETH_COL ) + ( 22 /Ethernet_Phy/ETH_CRS ) ( 23 GND ) - ( 24 N-000069 ) - ( 25 /FPGA_Spartan6/ETH_INT ) + ( 24 3.3V ) + ( 25 /Ethernet_Phy/ETH_INT ) ( 26 /Ethernet_Phy/ETH_LED0 ) ( 27 /Ethernet_Phy/ETH_LED1 ) ( 28 ? ) ( 29 ? ) ( 30 ? ) ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000337 ) - ( 33 N-000344 ) + ( 32 N-000345 ) + ( 33 N-000335 ) ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000336 ) + ( 37 N-000344 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) - ( 40 N-000338 ) - ( 41 N-000343 ) + ( 40 N-000346 ) + ( 41 N-000334 ) ( 42 ? ) ( 43 ? ) ( 44 GND ) @@ -660,51 +668,51 @@ ( 48 /FPGA_Spartan6/ETH_RESET_N ) ) ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} - ( 1 N-000069 ) - ( 2 N-000343 ) + ( 1 3.3V ) + ( 2 N-000334 ) ) ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} - ( 1 N-000069 ) - ( 2 N-000338 ) + ( 1 3.3V ) + ( 2 N-000346 ) ) ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} - ( 1 N-000069 ) - ( 2 N-000337 ) + ( 1 3.3V ) + ( 2 N-000345 ) ) ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} - ( 1 N-000069 ) - ( 2 N-000344 ) + ( 1 3.3V ) + ( 2 N-000335 ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000340 ) + ( 1 N-000350 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000341 ) + ( 1 N-000337 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000343 ) - ( 2 N-000338 ) - ( 3 N-000069 ) + ( 1 N-000334 ) + ( 2 N-000346 ) + ( 3 3.3V ) ( 4 GND ) ( 5 GND ) - ( 6 N-000069 ) - ( 7 N-000344 ) - ( 8 N-000337 ) - ( 9 N-000069 ) - ( 10 N-000341 ) - ( 11 N-000069 ) - ( 12 N-000340 ) - ( 13 N-000345 ) - ( 14 N-000345 ) + ( 6 3.3V ) + ( 7 N-000335 ) + ( 8 N-000345 ) + ( 9 3.3V ) + ( 10 N-000337 ) + ( 11 3.3V ) + ( 12 N-000350 ) + ( 13 N-000336 ) + ( 14 N-000336 ) ) ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} ( CASE GND ) - ( CD ? ) ( COM GND ) + ( CD ? ) ( 1 /Non_volatile_memories/SD_DAT2 ) - ( 2 /Non_volatile_memories/SD_DAT3 ) + ( 2 /FPGA_Spartan6/SD_DAT3 ) ( 3 /Non_volatile_memories/SD_CMD ) ( 4 ? ) ( 5 /Non_volatile_memories/SD_CLK ) @@ -724,14 +732,14 @@ ( 9 ? ) ( 10 ? ) ( 11 ? ) - ( 12 N-000069 ) + ( 12 3.3V ) ( 13 GND ) ( 14 ? ) ( 15 ? ) ( 16 ? ) ( 17 ? ) ( 18 ? ) - ( 19 N-000069 ) + ( 19 3.3V ) ( 20 ? ) ( 21 ? ) ( 22 ? ) @@ -749,7 +757,7 @@ ( 34 ? ) ( 35 ? ) ( 36 GND ) - ( 37 N-000069 ) + ( 37 3.3V ) ( 38 ? ) ( 39 ? ) ( 40 ? ) @@ -820,118 +828,118 @@ ) ( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R} ( 1 +2.5V ) - ( 2 N-000047 ) + ( 2 N-000044 ) ) ( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R} - ( 1 N-000047 ) - ( 2 N-000048 ) + ( 1 N-000044 ) + ( 2 N-000043 ) ) ( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R} - ( 1 N-000046 ) - ( 2 N-000045 ) + ( 1 N-000045 ) + ( 2 N-000047 ) ) ( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R} ( 1 +2.5V ) - ( 2 N-000046 ) + ( 2 N-000045 ) ) ( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP} ( 1 +2.5V ) - ( 2 N-000047 ) + ( 2 N-000044 ) ) ( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP} - ( 1 N-000047 ) - ( 2 N-000048 ) + ( 1 N-000044 ) + ( 2 N-000043 ) ) ( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP} - ( 1 N-000046 ) - ( 2 N-000045 ) + ( 1 N-000045 ) + ( 2 N-000047 ) ) ( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP} ( 1 +2.5V ) - ( 2 N-000046 ) + ( 2 N-000045 ) ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) ( 2 /DDR_Banks/M1_DQ0 ) ( 3 +2.5V ) - ( 4 /DDR_Banks/M1_DQ1 ) - ( 5 /DDR_Banks/M1_DQ2 ) + ( 4 /FPGA_Spartan6/M1_DQ1 ) + ( 5 /FPGA_Spartan6/M1_DQ2 ) ( 6 GND ) ( 7 /DDR_Banks/M1_DQ3 ) - ( 8 /DDR_Banks/M1_DQ4 ) + ( 8 /FPGA_Spartan6/M1_DQ4 ) ( 9 +2.5V ) ( 10 /DDR_Banks/M1_DQ5 ) ( 11 /DDR_Banks/M1_DQ6 ) ( 12 GND ) - ( 13 /DDR_Banks/M1_DQ7 ) + ( 13 /FPGA_Spartan6/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /DDR_Banks/M1_LDQS ) + ( 16 /FPGA_Spartan6/M1_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) ( 20 /DDR_Banks/M1_LDM ) - ( 21 /DDR_Banks/M1_WE# ) + ( 21 /FPGA_Spartan6/M1_WE# ) ( 22 /DDR_Banks/M1_CAS# ) ( 23 /DDR_Banks/M1_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /DDR_Banks/M1_BA0 ) - ( 27 /DDR_Banks/M1_BA1 ) + ( 27 /FPGA_Spartan6/M1_BA1 ) ( 28 /DDR_Banks/M1_A10 ) - ( 29 /DDR_Banks/M1_A0 ) - ( 30 /DDR_Banks/M1_A1 ) - ( 31 /DDR_Banks/M1_A2 ) - ( 32 /DDR_Banks/M1_A3 ) + ( 29 /FPGA_Spartan6/M1_A0 ) + ( 30 /FPGA_Spartan6/M1_A1 ) + ( 31 /FPGA_Spartan6/M1_A2 ) + ( 32 /FPGA_Spartan6/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /DDR_Banks/M1_A4 ) ( 36 /DDR_Banks/M1_A5 ) ( 37 /DDR_Banks/M1_A6 ) - ( 38 /DDR_Banks/M1_A7 ) - ( 39 /DDR_Banks/M1_A8 ) + ( 38 /FPGA_Spartan6/M1_A7 ) + ( 39 /FPGA_Spartan6/M1_A8 ) ( 40 /DDR_Banks/M1_A9 ) ( 41 /DDR_Banks/M1_A11 ) - ( 42 /DDR_Banks/M1_A12 ) + ( 42 /FPGA_Spartan6/M1_A12 ) ( 43 ? ) - ( 44 /DDR_Banks/M1_CLK# ) + ( 44 /FPGA_Spartan6/M1_CLK# ) ( 45 /DDR_Banks/M1_CKE ) - ( 46 /DDR_Banks/M1_CLK ) - ( 47 /DDR_Banks/M1_UDM ) + ( 46 /FPGA_Spartan6/M1_CLK ) + ( 47 /FPGA_Spartan6/M1_UDM ) ( 48 GND ) - ( 49 N-000047 ) + ( 49 N-000044 ) ( 50 ? ) - ( 51 /DDR_Banks/M1_UDQS ) + ( 51 /FPGA_Spartan6/M1_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M1_DQ8 ) + ( 54 /FPGA_Spartan6/M1_DQ8 ) ( 55 +2.5V ) - ( 56 /DDR_Banks/M1_DQ9 ) - ( 57 /DDR_Banks/M1_DQ10 ) + ( 56 /FPGA_Spartan6/M1_DQ9 ) + ( 57 /FPGA_Spartan6/M1_DQ10 ) ( 58 GND ) - ( 59 /DDR_Banks/M1_DQ11 ) - ( 60 /DDR_Banks/M1_DQ12 ) + ( 59 /FPGA_Spartan6/M1_DQ11 ) + ( 60 /FPGA_Spartan6/M1_DQ12 ) ( 61 +2.5V ) ( 62 /DDR_Banks/M1_DQ13 ) - ( 63 /DDR_Banks/M1_DQ14 ) + ( 63 /FPGA_Spartan6/M1_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M1_DQ15 ) + ( 65 /FPGA_Spartan6/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /DDR_Banks/M0_DQ0 ) + ( 2 /FPGA_Spartan6/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /DDR_Banks/M0_DQ1 ) - ( 5 /DDR_Banks/M0_DQ2 ) + ( 4 /FPGA_Spartan6/M0_DQ1 ) + ( 5 /FPGA_Spartan6/M0_DQ2 ) ( 6 GND ) - ( 7 /DDR_Banks/M0_DQ3 ) - ( 8 /DDR_Banks/M0_DQ4 ) + ( 7 /FPGA_Spartan6/M0_DQ3 ) + ( 8 /FPGA_Spartan6/M0_DQ4 ) ( 9 +2.5V ) ( 10 /DDR_Banks/M0_DQ5 ) ( 11 /DDR_Banks/M0_DQ6 ) ( 12 GND ) - ( 13 /DDR_Banks/M0_DQ7 ) + ( 13 /FPGA_Spartan6/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /DDR_Banks/M0_LDQS ) @@ -939,51 +947,51 @@ ( 18 +2.5V ) ( 19 ? ) ( 20 /DDR_Banks/M0_LDM ) - ( 21 /DDR_Banks/M0_WE# ) - ( 22 /DDR_Banks/M0_CAS# ) - ( 23 /DDR_Banks/M0_RAS# ) + ( 21 /FPGA_Spartan6/M0_WE# ) + ( 22 /FPGA_Spartan6/M0_CAS# ) + ( 23 /FPGA_Spartan6/M0_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /DDR_Banks/M0_BA0 ) - ( 27 /DDR_Banks/M0_BA1 ) + ( 27 /FPGA_Spartan6/M0_BA1 ) ( 28 /DDR_Banks/M0_A10 ) - ( 29 /DDR_Banks/M0_A0 ) - ( 30 /DDR_Banks/M0_A1 ) - ( 31 /DDR_Banks/M0_A2 ) - ( 32 /DDR_Banks/M0_A3 ) + ( 29 /FPGA_Spartan6/M0_A0 ) + ( 30 /FPGA_Spartan6/M0_A1 ) + ( 31 /FPGA_Spartan6/M0_A2 ) + ( 32 /FPGA_Spartan6/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /DDR_Banks/M0_A4 ) + ( 35 /FPGA_Spartan6/M0_A4 ) ( 36 /DDR_Banks/M0_A5 ) - ( 37 /DDR_Banks/M0_A6 ) + ( 37 /FPGA_Spartan6/M0_A6 ) ( 38 /DDR_Banks/M0_A7 ) - ( 39 /DDR_Banks/M0_A8 ) - ( 40 /DDR_Banks/M0_A9 ) - ( 41 /DDR_Banks/M0_A11 ) - ( 42 /DDR_Banks/M0_A12 ) + ( 39 /FPGA_Spartan6/M0_A8 ) + ( 40 /FPGA_Spartan6/M0_A9 ) + ( 41 /FPGA_Spartan6/M0_A11 ) + ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) - ( 44 /DDR_Banks/M0_CLK# ) - ( 45 /DDR_Banks/M0_CKE ) + ( 44 /FPGA_Spartan6/M0_CLK# ) + ( 45 /FPGA_Spartan6/M0_CKE ) ( 46 /DDR_Banks/M0_CLK ) ( 47 /DDR_Banks/M0_UDM ) ( 48 GND ) - ( 49 N-000046 ) + ( 49 N-000045 ) ( 50 ? ) ( 51 /DDR_Banks/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /DDR_Banks/M0_DQ8 ) + ( 54 /FPGA_Spartan6/M0_DQ8 ) ( 55 +2.5V ) ( 56 /DDR_Banks/M0_DQ9 ) ( 57 /DDR_Banks/M0_DQ10 ) ( 58 GND ) - ( 59 /DDR_Banks/M0_DQ11 ) - ( 60 /DDR_Banks/M0_DQ12 ) + ( 59 /FPGA_Spartan6/M0_DQ11 ) + ( 60 /FPGA_Spartan6/M0_DQ12 ) ( 61 +2.5V ) ( 62 /DDR_Banks/M0_DQ13 ) - ( 63 /DDR_Banks/M0_DQ14 ) + ( 63 /FPGA_Spartan6/M0_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M0_DQ15 ) + ( 65 /FPGA_Spartan6/M0_DQ15 ) ( 66 GND ) ) ) @@ -993,6 +1001,7 @@ $component R10 R? SM0603 SM0805 + R?-* $endlist $component C16 SM* @@ -1063,11 +1072,13 @@ $component R1 R? SM0603 SM0805 + R?-* $endlist $component R2 R? SM0603 SM0805 + R?-* $endlist $component C11 SM* @@ -1088,36 +1099,43 @@ $component R9 R? SM0603 SM0805 + R?-* $endlist $component R3 R? SM0603 SM0805 + R?-* $endlist $component R4 R? SM0603 SM0805 + R?-* $endlist $component R6 R? SM0603 SM0805 + R?-* $endlist $component R5 R? SM0603 SM0805 + R?-* $endlist $component R8 R? SM0603 SM0805 + R?-* $endlist $component R7 R? SM0603 SM0805 + R?-* $endlist $component C34 SM* @@ -1193,21 +1211,25 @@ $component R13 R? SM0603 SM0805 + R?-* $endlist $component R14 R? SM0603 SM0805 + R?-* $endlist $component R12 R? SM0603 SM0805 + R?-* $endlist $component R11 R? SM0603 SM0805 + R?-* $endlist $component C19 SM* @@ -1232,717 +1254,724 @@ $endlist $endfootprintlist } { Pin List by Nets -Net 2 "/FPGA Spartan6/ETH_COL" "ETH_COL" - U1 A10 - U4 21 -Net 3 "/Non volatile memories/SD_CLK" "SD_CLK" - J1 5 - U1 A16 -Net 4 "/FPGA Spartan6/USBA_VM" "USBA_VM" - U1 A17 - U6 5 -Net 5 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" - U1 A18 - U6 3 -Net 6 "/FPGA Spartan6/USBA_SPD" "USBA_SPD" - U1 D17 - U6 2 -Net 7 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" - U1 A8 - U4 14 -Net 8 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" - U1 B8 - U4 11 -Net 9 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" - U1 A5 - R1 1 - U4 1 -Net 10 "/FPGA Spartan6/ETH_RXC" "ETH_RXC" - U1 D10 - U4 10 -Net 11 "GND" "GND" - C34 2 - C33 2 - C28 2 - C29 2 - C31 2 - C30 2 - C32 2 - C27 2 - C21 2 - C26 2 - C24 2 - C25 2 - C23 2 - C22 2 - U3 24 - U3 34 - U3 48 - U3 66 - U3 6 - U3 12 - U3 52 - U3 58 - U3 64 - U2 24 - U2 34 - U2 48 - U2 66 - U2 6 - U2 12 - U2 52 - U2 58 - U2 64 - J1 CASE - J1 CASE - J1 CASE - J1 6 - J1 COM - U5 36 - U5 13 - U1 P10 - U1 V10 - U1 M10 - U1 K10 - U1 L13 - U1 A1 - U1 N13 - U1 A22 - U1 R5 - U1 AA13 - U1 W19 - U1 AA17 - U1 K14 - U1 AA5 - U1 L5 - U1 AA9 - U1 M14 - U1 AB1 - U1 N2 - U1 AB22 - U1 P14 - U1 B13 - U1 U21 - U1 B17 - U1 V4 - U1 B5 - U1 J9 - U1 B9 - U1 D18 - U1 L11 - U1 D4 - U1 L18 - U1 L9 - U1 E15 - U1 M12 - U1 E2 - U1 N11 - U1 E21 - U1 N17 - U1 E7 - U1 N21 - U1 G18 - U1 P12 - U1 G5 - U1 R18 - U1 H7 - U1 U2 - U1 J11 - U1 U7 - U1 J13 - U1 V14 - U1 J15 - U1 W16 - U1 J2 - U1 W7 - U1 J21 - U1 N9 - C2 2 - C8 2 - C7 2 - C5 2 - C3 2 - C1 2 - R2 2 - C11 2 - C10 2 - C12 2 - R9 2 - U4 8 - U4 12 - U4 23 - U4 35 - U4 36 - U4 39 - U4 44 - J4 5 - J4 4 - R10 2 - C16 2 - V1 2 - V2 2 - J5 4 - C15 2 - C14 2 - C13 2 - U6 8 - U6 7 -Net 12 "/DDR Banks/M1_LDM" "M1_LDM" - U3 20 - U1 L19 -Net 13 "/DDR Banks/M1_CKE" "M1_CKE" - U3 45 - U1 D21 -Net 14 "/DDR Banks/M1_CAS#" "M1_CAS#" - U3 22 - U1 H22 -Net 15 "/DDR Banks/M0_CKE" "M0_CKE" - U2 45 - U1 D2 -Net 16 "/DDR Banks/M0_WE#" "M0_WE#" - U2 21 - U1 F2 -Net 17 "/DDR Banks/M0_CAS#" "M0_CAS#" - U2 22 - U1 K4 -Net 18 "/DDR Banks/M0_UDM" "M0_UDM" - U2 47 - U1 M3 -Net 19 "/DDR Banks/M0_UDQS" "M0_UDQS" - U2 51 - U1 T2 -Net 20 "/DDR Banks/M1_CLK#" "M1_CLK#" - U3 44 - U1 J19 -Net 21 "/DDR Banks/M0_CLK#" "M0_CLK#" - U2 44 - U1 H3 -Net 22 "/DDR Banks/M0_CLK" "M0_CLK" - U2 46 - U1 H4 -Net 23 "/DDR Banks/M1_CLK" "M1_CLK" - U3 46 - U1 H20 -Net 24 "/DDR Banks/M0_LDM" "M0_LDM" - U2 20 - U1 L4 -Net 25 "/DDR Banks/M0_LDQS" "M0_LDQS" - U2 16 - U1 L3 -Net 26 "/DDR Banks/M0_RAS#" "M0_RAS#" - U2 23 - U1 K5 -Net 27 "/DDR Banks/M1_RAS#" "M1_RAS#" - U3 23 - U1 H21 -Net 28 "/DDR Banks/M1_WE#" "M1_WE#" - U3 21 - U1 H19 -Net 29 "/DDR Banks/M1_UDM" "M1_UDM" - U3 47 - U1 M20 -Net 30 "/DDR Banks/M1_LDQS" "M1_LDQS" - U3 16 - U1 L20 -Net 31 "/DDR Banks/M1_UDQS" "M1_UDQS" - U3 51 - U1 T21 -Net 32 "/FPGA Spartan6/ETH_INT" "ETH_INT" - U1 A4 - U4 25 -Net 33 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" - U1 D6 - U4 48 -Net 34 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" - U1 C5 - U4 2 -Net 35 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" - U1 A7 - U4 9 -Net 36 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" - U1 D8 - U4 15 -Net 37 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" - U1 D9 - U4 16 -Net 38 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" - U1 C10 +Net 1 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" U4 46 -Net 39 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" - U1 E16 - U6 9 -Net 40 "/FPGA Spartan6/USBA_VP" "USBA_VP" - U1 B18 - U6 4 -Net 41 "/Non volatile memories/SD_CMD" "SD_CMD" + U1 C10 +Net 2 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" + U1 K4 + U2 22 +Net 3 "/FPGA Spartan6/M1_WE#" "M1_WE#" + U1 H19 + U3 21 +Net 4 "/DDR Banks/M1_RAS#" "M1_RAS#" + U1 H21 + U3 23 +Net 5 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" + U1 K5 + U2 23 +Net 6 "/FPGA Spartan6/M0_WE#" "M0_WE#" + U1 F2 + U2 21 +Net 8 "/Non volatile memories/SD_CMD" "SD_CMD" J1 3 U1 C17 -Net 42 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" - U1 B10 +Net 9 "/Non volatile memories/SD_CLK" "SD_CLK" + U1 A16 + J1 5 +Net 10 "/Ethernet Phy/ETH_INT" "ETH_INT" + U1 A4 + U4 25 +Net 11 "/Ethernet Phy/ETH_TXER" "ETH_TXER" + U1 A8 + U4 14 +Net 12 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" + U4 16 + U1 D9 +Net 13 "/Ethernet Phy/ETH_TXC" "ETH_TXC" + U4 15 + U1 D8 +Net 14 "/Ethernet Phy/ETH_RXER" "ETH_RXER" + U1 B8 + U4 11 +Net 15 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" + U4 9 + U1 A7 +Net 16 "/Ethernet Phy/ETH_MDC" "ETH_MDC" + U1 C5 + U4 2 +Net 17 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" + U4 1 + U1 A5 + R1 1 +Net 18 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" + U4 48 + U1 D6 +Net 19 "/Ethernet Phy/ETH_RXC" "ETH_RXC" + U1 D10 + U4 10 +Net 20 "/Ethernet Phy/ETH_COL" "ETH_COL" + U4 21 + U1 A10 +Net 21 "/Ethernet Phy/ETH_CRS" "ETH_CRS" U4 22 -Net 44 "+2.5V" "+2.5V" - C34 1 - C33 1 - C28 1 - C29 1 - C31 1 - C30 1 - C32 1 - C27 1 - C21 1 - C26 1 - C24 1 - C25 1 - C23 1 - C22 1 - R13 1 - R11 1 - C19 1 - C17 1 - U3 1 - U3 18 - U3 33 - U3 3 - U3 9 - U3 15 - U3 55 - U3 61 - U2 1 - U2 18 - U2 33 - U2 3 - U2 9 - U2 15 - U2 55 - U2 61 - U1 H9 - U1 U11 - U1 F11 - U1 R6 - U1 M15 - U1 V6 - U1 G12 - U1 H15 - U1 D16 - U1 K15 - U1 R12 - U1 N8 - U1 R10 - U1 L8 - U1 W2 - U1 L2 - U1 L7 - U1 C2 - U1 N5 - U1 R2 - U1 U5 - U1 G2 - U1 F4 - U1 F6 - U1 J5 - U1 W21 - U1 C21 - U1 G21 - U1 J18 - U1 L16 - U1 L21 - U1 N18 - U1 R21 - U1 U18 - U1 E19 -Net 45 "" "" - R12 2 - C18 2 -Net 46 "" "" - R12 1 - R11 2 - C18 1 - C17 2 - U2 49 -Net 47 "" "" + U1 B10 +Net 22 "/FPGA Spartan6/M1_UDM" "M1_UDM" + U3 47 + U1 M20 +Net 23 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" + U1 L20 + U3 16 +Net 24 "/DDR Banks/M1_LDM" "M1_LDM" + U1 L19 + U3 20 +Net 25 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" + U1 T21 + U3 51 +Net 26 "/DDR Banks/M0_UDQS" "M0_UDQS" + U1 T2 + U2 51 +Net 27 "/DDR Banks/M0_LDM" "M0_LDM" + U1 L4 + U2 20 +Net 28 "/DDR Banks/M1_CAS#" "M1_CAS#" + U3 22 + U1 H22 +Net 29 "/DDR Banks/M1_CKE" "M1_CKE" + U3 45 + U1 D21 +Net 30 "GND" "GND" + U2 66 + U1 B5 + U3 66 + U1 M12 + U3 48 + U1 J15 + U3 58 + U3 52 + U2 34 + U2 64 + U2 24 + U2 58 + U1 AB1 + U2 48 + U3 12 + U2 6 + U3 6 + U1 J13 + U1 A22 + U4 39 + U1 P14 + U1 V14 + U1 E15 + U1 H7 + U4 36 + U1 B13 + U1 G5 + U3 24 + U3 34 + U3 64 + U1 L5 + U1 P12 + U4 35 + U1 R5 + U1 E7 + U1 AA17 + U1 AA5 + U1 W16 + U1 B17 + U1 N17 + U1 D18 + U1 G18 + U1 L18 + U1 R18 + U1 W19 + U1 AA9 + U1 AB22 + U1 AA13 + J1 CASE + U2 52 + U2 12 + U1 A1 + U1 E2 + U1 J2 + U1 N2 + U1 U2 + U1 D4 + U1 V4 + J1 6 + J1 COM + J1 CASE + J1 CASE + U5 36 + U5 13 + U1 L11 + U4 44 + U1 N11 + C3 2 + U4 23 + U1 E21 + U1 J21 + U4 12 + C1 2 + U1 N21 + U1 U21 + U1 L13 + U1 U7 + U1 W7 + C2 2 + U1 P10 + U1 V10 + U1 J11 + R9 2 + U1 N13 + C8 2 + U4 8 + C12 2 + C7 2 + C10 2 + C5 2 + C11 2 + R2 2 + C21 2 + C27 2 + C32 2 + C30 2 + C31 2 + C33 2 + C22 2 + C23 2 + C25 2 + C24 2 + C26 2 + C28 2 + C29 2 + U1 N9 + C34 2 + U1 B9 + U1 J9 + U1 L9 + J4 5 + U6 8 + U6 7 + U1 K14 + C13 2 + C14 2 + C15 2 + V2 2 + V1 2 + C16 2 + R10 2 + U1 M14 + J4 4 + L5 2 + U1 K10 + U1 M10 +Net 31 "/FPGA Spartan6/M0_CKE" "M0_CKE" + U2 45 + U1 D2 +Net 32 "/DDR Banks/M0_LDQS" "M0_LDQS" + U1 L3 + U2 16 +Net 33 "/DDR Banks/M0_UDM" "M0_UDM" + U2 47 + U1 M3 +Net 34 "/FPGA Spartan6/USBA_VP" "USBA_VP" + U1 B18 + U6 4 +Net 35 "/USB/USBA_RCV" "USBA_RCV" + U6 3 + U1 A18 +Net 36 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" + U6 9 + U1 E16 +Net 37 "/USB/USBA_SPD" "USBA_SPD" + U6 2 + U1 D17 +Net 38 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" + U1 H3 + U2 44 +Net 39 "/DDR Banks/M0_CLK" "M0_CLK" + U1 H4 + U2 46 +Net 40 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" + U3 44 + U1 J19 +Net 41 "/FPGA Spartan6/M1_CLK" "M1_CLK" + U1 H20 + U3 46 +Net 42 "/FPGA Spartan6/USBA_VM" "USBA_VM" + U1 A17 + U6 5 +Net 43 "" "" + C20 2 + R14 2 +Net 44 "" "" R13 2 R14 1 C19 2 - C20 1 U3 49 -Net 48 "" "" - R14 2 - C20 2 -Net 64 "/Non volatile memories/FRB_N" "FRB_N" + C20 1 +Net 45 "" "" + C18 1 + R12 1 + C17 2 + R11 2 + U2 49 +Net 46 "+2.5V" "+2.5V" + U1 N8 + U1 G2 + U1 L16 + U1 R10 + U1 C2 + U1 F11 + U1 H9 + U1 L8 + U3 15 + U1 L2 + U1 E19 + U1 U18 + U1 G21 + U1 N18 + U1 J18 + C33 1 + U3 3 + U1 W21 + U1 R2 + U3 55 + U1 U11 + U1 D16 + U1 W2 + U1 R21 + U1 L21 + U1 G12 + U3 18 + U1 R12 + U3 33 + U2 61 + C22 1 + C23 1 + U3 61 + C25 1 + U2 33 + C24 1 + C28 1 + C26 1 + U2 1 + C34 1 + U2 3 + U2 9 + U1 C21 + C31 1 + C30 1 + C32 1 + R11 1 + R13 1 + U1 M15 + U1 K15 + U3 9 + U1 N5 + U6 1 + U1 U5 + U1 V6 + U2 15 + C19 1 + U1 F4 + U1 F6 + U1 J5 + C29 1 + U1 H15 + U1 L7 + U3 1 + C17 1 + C27 1 + U2 18 + C21 1 + U2 55 + U1 R6 +Net 47 "" "" + C18 2 + R12 2 +Net 93 "/Non volatile memories/FRB_N" "FRB_N" U5 7 U5 6 -Net 69 "" "" +Net 94 "3.3V" "3.3V" + L2 1 + U4 7 + J4 11 + C5 1 + C10 1 + J4 9 + J4 6 + R5 1 + U6 12 + J4 3 + R3 1 + R4 1 + U6 14 + R6 1 + R1 2 U5 37 U5 19 U5 12 - L2 1 - C5 1 - C3 1 - C1 1 - R1 2 C11 1 - C10 1 - U4 7 + C1 1 U4 24 - R3 1 - R4 1 - R6 1 - R5 1 - J4 11 - J4 9 - J4 6 - J4 3 - C15 1 - C14 1 - C13 1 - U6 14 - U6 12 - U6 1 -Net 99 "+1.2V" "+1.2V" - U1 N10 - U1 P11 - U1 P13 + C3 1 +Net 98 "+1.2V" "+1.2V" U1 P9 U1 R14 - U1 N12 - U1 J10 - U1 J12 - U1 J14 + U1 P11 + U1 N14 + U1 L10 + U1 N10 + U1 L12 U1 J8 - U1 K11 U1 K13 U1 K9 - U1 L10 - U1 L12 - U1 L14 - U1 M11 - U1 M13 + U1 J12 U1 M9 - U1 N14 + U1 L14 + U1 J14 + U1 M11 + U1 P13 + U1 M13 + U1 N12 + U1 K11 + U1 J10 Net 100 "+3.3V" "+3.3V" - U1 B4 - U1 B7 - U1 E13 - U1 E17 - U1 G10 - U1 G14 - U1 B11 - U1 B15 - U1 B19 U1 E9 + U1 G10 + U1 B4 + U1 B11 + U1 E13 + U1 G14 + U1 B15 + U1 B7 + U1 B19 + U1 E17 Net 101 "" "" - U1 AA15 - U1 V16 - U1 T13 - U1 V8 U1 V12 - U1 AA3 + U1 AA7 + U1 T13 U1 T9 - U1 AA19 U1 AA11 U1 W5 - U1 AA7 -Net 334 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + U1 V16 + U1 V8 + U1 AA3 + U1 AA15 + U1 AA19 +Net 333 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + R7 2 + U4 26 +Net 334 "" "" + J4 1 + U4 41 + R3 2 +Net 335 "" "" + U4 33 + J4 7 + R5 2 +Net 336 "" "" + R9 1 + C12 1 + J4 13 + J4 14 +Net 337 "" "" + R7 1 + J4 10 +Net 338 "" "" + L1 1 + C4 1 +Net 339 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" + C2 1 + U4 13 +Net 340 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + L3 2 + C9 1 + U4 47 +Net 343 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + U4 31 + L1 2 L3 1 C6 1 - L1 2 - U4 31 -Net 335 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - L2 2 - C8 1 - C7 1 - U4 38 -Net 336 "" "" +Net 344 "" "" R2 1 U4 37 -Net 337 "" "" +Net 345 "" "" + J4 8 U4 32 R6 2 - J4 8 -Net 338 "" "" +Net 346 "" "" U4 40 R4 2 J4 2 -Net 339 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - U4 27 +Net 347 "" "" + C4 2 + C6 2 + C9 2 +Net 348 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + U4 38 + L2 2 + C8 1 + C7 1 +Net 349 "/Ethernet Phy/ETH_LED1" "ETH_LED1" R8 2 -Net 340 "" "" + U4 27 +Net 350 "" "" R8 1 J4 12 -Net 341 "" "" - R7 1 - J4 10 -Net 342 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - U4 26 - R7 2 -Net 343 "" "" - U4 41 - R3 2 - J4 1 -Net 344 "" "" - U4 33 - R5 2 - J4 7 -Net 345 "" "" - C12 1 - R9 1 - J4 13 - J4 14 -Net 346 "" "" - L1 1 - C4 1 -Net 347 "" "" - C9 2 - C6 2 - C4 2 -Net 348 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" - C2 1 - U4 13 -Net 349 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - C9 1 - L3 2 - U4 47 -Net 358 "" "" +Net 356 "" "" V2 1 - V2 1 - J5 2 U6 10 -Net 359 "" "" - V1 1 - V1 1 + J5 2 + V2 1 +Net 357 "" "" + F1 1 + L4 1 +Net 358 "" "" + J5 4 + L5 1 +Net 360 "" "" J5 3 U6 11 -Net 360 "" "" - F1 1 - J5 1 + V1 1 + V1 1 Net 361 "" "" + J5 S4 + J5 S3 R10 1 C16 1 - J5 S1 J5 S2 - J5 S3 - J5 S4 -Net 362 "/DDR Banks/M0_A0" "M0_A0" - U2 29 - U1 H2 -Net 363 "/DDR Banks/M0_A1" "M0_A1" - U2 30 - U1 H1 -Net 364 "/DDR Banks/M0_A2" "M0_A2" - U2 31 - U1 H5 -Net 365 "/DDR Banks/M0_A3" "M0_A3" - U2 32 - U1 K6 -Net 366 "/DDR Banks/M0_A4" "M0_A4" - U2 35 - U1 F3 -Net 367 "/DDR Banks/M0_A5" "M0_A5" - U2 36 - U1 K3 -Net 368 "/DDR Banks/M0_A6" "M0_A6" - U2 37 - U1 J4 -Net 369 "/DDR Banks/M0_A7" "M0_A7" - U2 38 - U1 H6 -Net 370 "/DDR Banks/M0_A8" "M0_A8" - U2 39 - U1 E3 -Net 371 "/DDR Banks/M0_A9" "M0_A9" - U2 40 - U1 E1 -Net 372 "/DDR Banks/M0_A10" "M0_A10" - U2 28 - U1 G4 -Net 373 "/DDR Banks/M0_A11" "M0_A11" - U2 41 - U1 C1 -Net 374 "/DDR Banks/M0_A12" "M0_A12" - U2 42 - U1 D1 -Net 375 "/DDR Banks/M1_A0" "M1_A0" - U3 29 - U1 F21 -Net 376 "/DDR Banks/M1_A1" "M1_A1" - U3 30 - U1 F22 -Net 377 "/DDR Banks/M1_A2" "M1_A2" - U3 31 - U1 E22 -Net 378 "/DDR Banks/M1_A3" "M1_A3" - U3 32 - U1 G20 -Net 379 "/DDR Banks/M1_A4" "M1_A4" - U3 35 - U1 F20 -Net 380 "/DDR Banks/M1_A5" "M1_A5" - U3 36 - U1 K20 -Net 381 "/DDR Banks/M1_A6" "M1_A6" - U3 37 - U1 K19 -Net 382 "/DDR Banks/M1_A7" "M1_A7" - U3 38 - U1 E20 -Net 383 "/DDR Banks/M1_A8" "M1_A8" - U3 39 - U1 C20 -Net 384 "/DDR Banks/M1_A9" "M1_A9" - U3 40 - U1 C22 -Net 385 "/DDR Banks/M1_A10" "M1_A10" - U3 28 - U1 G19 -Net 386 "/DDR Banks/M1_A11" "M1_A11" - U3 41 - U1 F19 -Net 387 "/DDR Banks/M1_A12" "M1_A12" - U3 42 - U1 D22 -Net 388 "/DDR Banks/M0_DQ0" "M0_DQ0" - U2 2 - U1 N3 -Net 389 "/DDR Banks/M0_DQ1" "M0_DQ1" - U2 4 - U1 N1 -Net 390 "/DDR Banks/M0_DQ2" "M0_DQ2" - U2 5 - U1 M2 -Net 391 "/DDR Banks/M0_DQ3" "M0_DQ3" - U2 7 - U1 M1 -Net 392 "/DDR Banks/M0_DQ4" "M0_DQ4" - U2 8 - U1 J3 -Net 393 "/DDR Banks/M0_DQ5" "M0_DQ5" - U2 10 - U1 J1 -Net 394 "/DDR Banks/M0_DQ6" "M0_DQ6" - U2 11 - U1 K2 -Net 395 "/DDR Banks/M0_DQ7" "M0_DQ7" - U2 13 - U1 K1 -Net 396 "/DDR Banks/M0_DQ8" "M0_DQ8" - U2 54 - U1 P2 -Net 397 "/DDR Banks/M0_DQ9" "M0_DQ9" - U2 56 - U1 P1 -Net 398 "/DDR Banks/M0_DQ10" "M0_DQ10" - U2 57 - U1 R3 -Net 399 "/DDR Banks/M0_DQ11" "M0_DQ11" - U2 59 - U1 R1 -Net 400 "/DDR Banks/M0_DQ12" "M0_DQ12" - U2 60 - U1 U3 -Net 401 "/DDR Banks/M0_DQ13" "M0_DQ13" - U2 62 - U1 U1 -Net 402 "/DDR Banks/M0_DQ14" "M0_DQ14" - U2 63 - U1 V2 -Net 403 "/DDR Banks/M0_DQ15" "M0_DQ15" - U2 65 - U1 V1 -Net 404 "/DDR Banks/M1_DQ0" "M1_DQ0" - U3 2 - U1 N20 -Net 405 "/DDR Banks/M1_DQ1" "M1_DQ1" - U3 4 - U1 N22 -Net 406 "/DDR Banks/M1_DQ2" "M1_DQ2" - U3 5 - U1 M21 -Net 407 "/DDR Banks/M1_DQ3" "M1_DQ3" - U3 7 - U1 M22 -Net 408 "/DDR Banks/M1_DQ4" "M1_DQ4" - U3 8 - U1 J20 -Net 409 "/DDR Banks/M1_DQ5" "M1_DQ5" - U3 10 - U1 J22 -Net 410 "/DDR Banks/M1_DQ6" "M1_DQ6" - U3 11 - U1 K21 -Net 411 "/DDR Banks/M1_DQ7" "M1_DQ7" - U3 13 - U1 K22 -Net 412 "/DDR Banks/M1_DQ8" "M1_DQ8" - U3 54 - U1 P21 -Net 413 "/DDR Banks/M1_DQ9" "M1_DQ9" - U3 56 - U1 P22 -Net 414 "/DDR Banks/M1_DQ10" "M1_DQ10" - U3 57 - U1 R20 -Net 415 "/DDR Banks/M1_DQ11" "M1_DQ11" - U3 59 - U1 R22 -Net 416 "/DDR Banks/M1_DQ12" "M1_DQ12" - U3 60 - U1 U20 -Net 417 "/DDR Banks/M1_DQ13" "M1_DQ13" - U3 62 - U1 U22 -Net 418 "/DDR Banks/M1_DQ14" "M1_DQ14" - U3 63 - U1 V21 -Net 419 "/DDR Banks/M1_DQ15" "M1_DQ15" - U3 65 - U1 V22 -Net 420 "/DDR Banks/M1_BA0" "M1_BA0" - U3 26 - U1 J17 -Net 421 "/DDR Banks/M1_BA1" "M1_BA1" - U3 27 - U1 K17 -Net 422 "/DDR Banks/M0_BA0" "M0_BA0" - U2 26 - U1 G3 -Net 423 "/DDR Banks/M0_BA1" "M0_BA1" - U2 27 - U1 G1 -Net 424 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" - U1 C8 - U4 17 -Net 425 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" - U1 C9 - U4 18 -Net 426 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" - U1 A9 - U4 19 -Net 427 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" - U1 D7 - U4 20 -Net 428 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" - U1 C7 - U4 6 -Net 429 "/FPGA Spartan6/ETH_RXD1" "ETH_RXD1" - U1 A6 - U4 5 -Net 430 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" - U1 B6 - U4 4 -Net 431 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" - U1 C6 - U4 3 -Net 432 "/Non volatile memories/SD_DAT0" "SD_DAT0" - J1 7 - U1 B16 -Net 433 "/Non volatile memories/SD_DAT1" "SD_DAT1" - J1 8 - U1 C16 -Net 434 "/Non volatile memories/SD_DAT2" "SD_DAT2" - J1 1 - U1 D15 -Net 435 "/Non volatile memories/SD_DAT3" "SD_DAT3" + J5 S1 +Net 362 "" "" + L4 2 + J5 1 +Net 363 "" "" + C13 1 + C14 1 + C15 1 +Net 371 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" J1 2 U1 A15 +Net 372 "/Non volatile memories/SD_DAT2" "SD_DAT2" + U1 D15 + J1 1 +Net 373 "/Non volatile memories/SD_DAT1" "SD_DAT1" + J1 8 + U1 C16 +Net 374 "/Non volatile memories/SD_DAT0" "SD_DAT0" + U1 B16 + J1 7 +Net 375 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" + U1 D7 + U4 20 +Net 376 "/FPGA Spartan6/M1_BA1" "M1_BA1" + U1 K17 + U3 27 +Net 377 "/DDR Banks/M1_BA0" "M1_BA0" + U3 26 + U1 J17 +Net 378 "/FPGA Spartan6/M0_BA1" "M0_BA1" + U1 G1 + U2 27 +Net 379 "/DDR Banks/M0_BA0" "M0_BA0" + U1 G3 + U2 26 +Net 389 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" + U1 C6 + U4 3 +Net 390 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" + U4 4 + U1 B6 +Net 391 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" + U1 A6 + U4 5 +Net 392 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" + U1 C7 + U4 6 +Net 393 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" + U4 19 + U1 A9 +Net 394 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" + U1 C9 + U4 18 +Net 395 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" + U4 17 + U1 C8 +Net 396 "/DDR Banks/M1_A9" "M1_A9" + U1 C22 + U3 40 +Net 397 "/FPGA Spartan6/M1_A8" "M1_A8" + U3 39 + U1 C20 +Net 398 "/FPGA Spartan6/M1_A7" "M1_A7" + U1 E20 + U3 38 +Net 399 "/DDR Banks/M1_A6" "M1_A6" + U1 K19 + U3 37 +Net 400 "/DDR Banks/M1_A5" "M1_A5" + U1 K20 + U3 36 +Net 401 "/DDR Banks/M1_A4" "M1_A4" + U1 F20 + U3 35 +Net 402 "/FPGA Spartan6/M1_A3" "M1_A3" + U3 32 + U1 G20 +Net 403 "/FPGA Spartan6/M1_A2" "M1_A2" + U3 31 + U1 E22 +Net 404 "/FPGA Spartan6/M1_A1" "M1_A1" + U3 30 + U1 F22 +Net 405 "/FPGA Spartan6/M1_A0" "M1_A0" + U3 29 + U1 F21 +Net 406 "/FPGA Spartan6/M0_A12" "M0_A12" + U1 D1 + U2 42 +Net 407 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" + U3 65 + U1 V22 +Net 408 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" + U1 V21 + U3 63 +Net 409 "/DDR Banks/M1_DQ13" "M1_DQ13" + U3 62 + U1 U22 +Net 410 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" + U3 60 + U1 U20 +Net 411 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" + U3 59 + U1 R22 +Net 412 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" + U1 R20 + U3 57 +Net 413 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" + U3 56 + U1 P22 +Net 414 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" + U3 54 + U1 P21 +Net 415 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" + U1 K22 + U3 13 +Net 416 "/DDR Banks/M1_DQ6" "M1_DQ6" + U3 11 + U1 K21 +Net 417 "/DDR Banks/M1_DQ5" "M1_DQ5" + U3 10 + U1 J22 +Net 418 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" + U3 8 + U1 J20 +Net 419 "/DDR Banks/M1_DQ3" "M1_DQ3" + U3 7 + U1 M22 +Net 420 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" + U3 5 + U1 M21 +Net 421 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" + U1 N22 + U3 4 +Net 422 "/DDR Banks/M1_DQ0" "M1_DQ0" + U3 2 + U1 N20 +Net 423 "/FPGA Spartan6/M1_A12" "M1_A12" + U3 42 + U1 D22 +Net 424 "/DDR Banks/M1_A11" "M1_A11" + U1 F19 + U3 41 +Net 425 "/DDR Banks/M1_A10" "M1_A10" + U3 28 + U1 G19 +Net 426 "/DDR Banks/M0_DQ10" "M0_DQ10" + U2 57 + U1 R3 +Net 427 "/DDR Banks/M0_DQ9" "M0_DQ9" + U2 56 + U1 P1 +Net 428 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" + U2 54 + U1 P2 +Net 429 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" + U1 K1 + U2 13 +Net 430 "/DDR Banks/M0_DQ6" "M0_DQ6" + U2 11 + U1 K2 +Net 431 "/DDR Banks/M0_DQ5" "M0_DQ5" + U1 J1 + U2 10 +Net 432 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" + U2 8 + U1 J3 +Net 433 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" + U2 7 + U1 M1 +Net 434 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" + U2 5 + U1 M2 +Net 435 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" + U2 4 + U1 N1 +Net 436 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" + U1 N3 + U2 2 +Net 437 "/FPGA Spartan6/M0_A11" "M0_A11" + U1 C1 + U2 41 +Net 438 "/DDR Banks/M0_A10" "M0_A10" + U2 28 + U1 G4 +Net 439 "/FPGA Spartan6/M0_A9" "M0_A9" + U2 40 + U1 E1 +Net 440 "/FPGA Spartan6/M0_A8" "M0_A8" + U2 39 + U1 E3 +Net 441 "/DDR Banks/M0_A7" "M0_A7" + U1 H6 + U2 38 +Net 442 "/FPGA Spartan6/M0_A6" "M0_A6" + U1 J4 + U2 37 +Net 443 "/DDR Banks/M0_A5" "M0_A5" + U1 K3 + U2 36 +Net 444 "/FPGA Spartan6/M0_A4" "M0_A4" + U1 F3 + U2 35 +Net 445 "/FPGA Spartan6/M0_A3" "M0_A3" + U1 K6 + U2 32 +Net 446 "/FPGA Spartan6/M0_A2" "M0_A2" + U1 H5 + U2 31 +Net 447 "/FPGA Spartan6/M0_A1" "M0_A1" + U2 30 + U1 H1 +Net 448 "/FPGA Spartan6/M0_A0" "M0_A0" + U1 H2 + U2 29 +Net 449 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" + U2 65 + U1 V1 +Net 450 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" + U1 V2 + U2 63 +Net 451 "/DDR Banks/M0_DQ13" "M0_DQ13" + U1 U1 + U2 62 +Net 452 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" + U1 U3 + U2 60 +Net 453 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" + U1 R1 + U2 59 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 9bc6356..e1fcc2c 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Wed 11 Aug 2010 07:25:38 AM COT +update=Thu 12 Aug 2010 12:07:08 PM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 7cac646..30b77d8 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:11:18 AM COT +EESchema Schematic File Version 2 date Thu 12 Aug 2010 08:51:39 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001