diff --git a/BOOKSHELF b/BOOKSHELF index 267fa29..2f89fbe 100644 --- a/BOOKSHELF +++ b/BOOKSHELF @@ -95,3 +95,6 @@ N: BQ24070 A: U13 D: http://focus.ti.com/lit/ds/symlink/bq24071.pdf +N: PJ-031CH +A: J8 +D: http://products.cui.com/getPDF.aspx?filename=PJ-031CH.pdf diff --git a/components/pasives-connectors.lib b/components/pasives-connectors.lib index 96419f4..0b665b6 100644 --- a/components/pasives-connectors.lib +++ b/components/pasives-connectors.lib @@ -1,8 +1,8 @@ -EESchema-LIBRARY Version 2.3 Date: Tue 10 Aug 2010 04:58:24 PM COT +EESchema-LIBRARY Version 2.3 Date: Fri 31 Dec 2010 09:39:59 AM COT # -# C +# Cap # -DEF C C 0 10 N Y 1 F N +DEF Cap C 0 10 N Y 1 F N F0 "C" 50 100 50 H V L CNN F1 "Cap" 50 -100 50 H V L CNN $FPLIST @@ -19,7 +19,6 @@ X ~ 2 0 -100 65 U 40 40 1 1 P ENDDRAW ENDDEF # -# # FAN4010 # DEF FAN4010 U 0 40 Y Y 1 F N @@ -36,4 +35,21 @@ X NC 6 550 -100 300 L 50 50 1 1 I N ENDDRAW ENDDEF # +# PJ +# +DEF PJ J 0 20 Y Y 1 F N +F0 "J" -200 -100 60 H V C CNN +F1 "PJ" -200 300 60 H V C CNN +DRAW +A 300 175 25 -899 899 0 1 0 f 300 150 300 200 +P 5 0 1 0 -150 0 150 0 200 50 250 0 250 0 N +P 5 0 1 0 300 150 -150 150 -150 200 300 200 300 200 f +P 6 0 1 0 -250 250 -250 -50 -150 -50 -150 250 -250 250 -250 250 f +P 6 0 1 0 -150 100 50 100 100 0 100 100 50 100 50 100 N +X 1 1 -550 200 300 R 50 50 1 1 w +X 2 2 -550 100 300 R 50 50 1 1 w +X 3 3 -550 0 300 R 50 50 1 1 w +ENDDRAW +ENDDEF +# #End Library diff --git a/xue-rnc/ether.sch b/xue-rnc/ether.sch index 913410b..39c96c0 100644 --- a/xue-rnc/ether.sch +++ b/xue-rnc/ether.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT +EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -53,13 +53,12 @@ LIBS:ft2232c LIBS:fxo-hc536r LIBS:zx62d-b-5p8 LIBS:a7130 -LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 7 9 Title "" -Date "29 dec 2010" +Date "31 dec 2010" Rev "" Comp "" Comment1 "" diff --git a/xue-rnc/expansion.sch b/xue-rnc/expansion.sch index e2911e2..dae52b1 100644 --- a/xue-rnc/expansion.sch +++ b/xue-rnc/expansion.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT +EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -53,13 +53,12 @@ LIBS:ft2232c LIBS:fxo-hc536r LIBS:zx62d-b-5p8 LIBS:a7130 -LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 9 9 Title "" -Date "29 dec 2010" +Date "31 dec 2010" Rev "" Comp "" Comment1 "" diff --git a/xue-rnc/flash.sch b/xue-rnc/flash.sch index dd0c6ed..0f049f1 100644 --- a/xue-rnc/flash.sch +++ b/xue-rnc/flash.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT +EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -53,13 +53,12 @@ LIBS:ft2232c LIBS:fxo-hc536r LIBS:zx62d-b-5p8 LIBS:a7130 -LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 5 9 Title "" -Date "29 dec 2010" +Date "31 dec 2010" Rev "" Comp "" Comment1 "" @@ -252,19 +251,19 @@ F 1 "100nF" H 4000 5400 50 0000 L CNN -1 0 0 1 $EndComp $Comp -L GND #PWR051 +L GND #PWR24 U 1 1 4C65D6AB P 9350 3150 -F 0 "#PWR051" H 9350 3150 30 0001 C CNN +F 0 "#PWR24" H 9350 3150 30 0001 C CNN F 1 "GND" H 9350 3080 30 0001 C CNN 1 9350 3150 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR052 +L +3.3V #PWR23 U 1 1 4C65D69B P 9350 2650 -F 0 "#PWR052" H 9350 2610 30 0001 C CNN +F 0 "#PWR23" H 9350 2610 30 0001 C CNN F 1 "+3.3V" H 9350 2760 30 0000 C CNN 1 9350 2650 1 0 0 -1 @@ -328,10 +327,10 @@ SPI_DQ[0..3] Text HLabel 2450 1700 0 60 Input ~ 0 SPI_FLASH_CS# $Comp -L GND #PWR053 +L GND #PWR17 U 1 1 4C65ABE9 P 2650 2450 -F 0 "#PWR053" H 2650 2450 30 0001 C CNN +F 0 "#PWR17" H 2650 2450 30 0001 C CNN F 1 "GND" H 2650 2380 30 0001 C CNN 1 2650 2450 1 0 0 -1 @@ -364,19 +363,19 @@ Entry Wire Line Entry Wire Line 8150 3150 8250 3050 $Comp -L +3.3V #PWR054 +L +3.3V #PWR21 U 1 1 4C646C14 P 7950 2900 -F 0 "#PWR054" H 7950 2860 30 0001 C CNN +F 0 "#PWR21" H 7950 2860 30 0001 C CNN F 1 "+3.3V" H 7950 3010 30 0000 C CNN 1 7950 2900 1 0 0 -1 $EndComp $Comp -L GND #PWR055 +L GND #PWR22 U 1 1 4C646BEA P 7950 3000 -F 0 "#PWR055" H 7950 3000 30 0001 C CNN +F 0 "#PWR22" H 7950 3000 30 0001 C CNN F 1 "GND" H 7950 2930 30 0001 C CNN 1 7950 3000 1 0 0 -1 @@ -426,10 +425,10 @@ SD_DAT3 Text Label 4200 6100 0 30 ~ 0 SD_CMD $Comp -L GND #PWR056 +L GND #PWR18 U 1 1 4C61D875 P 3950 5800 -F 0 "#PWR056" H 3950 5800 30 0001 C CNN +F 0 "#PWR18" H 3950 5800 30 0001 C CNN F 1 "GND" H 3950 5730 30 0001 C CNN 1 3950 5800 1 0 0 -1 @@ -441,19 +440,19 @@ SD_DAT0 Text Label 4200 5850 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR057 +L GND #PWR20 U 1 1 4C438ADC P 5800 6200 -F 0 "#PWR057" H 5800 6200 30 0001 C CNN +F 0 "#PWR20" H 5800 6200 30 0001 C CNN F 1 "GND" H 5800 6130 30 0001 C CNN 1 5800 6200 1 0 0 -1 $EndComp $Comp -L GND #PWR058 +L GND #PWR19 U 1 1 4C438AD5 P 5350 6550 -F 0 "#PWR058" H 5350 6550 30 0001 C CNN +F 0 "#PWR19" H 5350 6550 30 0001 C CNN F 1 "GND" H 5350 6480 30 0001 C CNN 1 5350 6550 1 0 0 -1 diff --git a/xue-rnc/fpga1.sch b/xue-rnc/fpga1.sch index 4574994..1e32920 100644 --- a/xue-rnc/fpga1.sch +++ b/xue-rnc/fpga1.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT +EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -53,13 +53,12 @@ LIBS:ft2232c LIBS:fxo-hc536r LIBS:zx62d-b-5p8 LIBS:a7130 -LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 3 9 Title "" -Date "29 dec 2010" +Date "31 dec 2010" Rev "" Comp "" Comment1 "" @@ -1267,10 +1266,10 @@ FPGA_BANK0_IO_38 Text Notes 7900 3650 0 40 ~ 0 M[1]=Low (master), High (slave) $Comp -L GND #PWR025 +L GND #PWR95 U 1 1 4CD361EC P 7900 3900 -F 0 "#PWR025" H 7900 3900 30 0001 C CNN +F 0 "#PWR95" H 7900 3900 30 0001 C CNN F 1 "GND" H 7900 3830 30 0001 C CNN 1 7900 3900 1 0 0 -1 @@ -1280,10 +1279,10 @@ M[0]=Low (parallel), High (serial) Text GLabel 8000 1200 1 30 BiDi ~ 0 VCCO2 $Comp -L GND #PWR026 +L GND #PWR82 U 1 1 4CD35A7F P 1450 2350 -F 0 "#PWR026" H 1450 2350 30 0001 C CNN +F 0 "#PWR82" H 1450 2350 30 0001 C CNN F 1 "GND" H 1450 2280 30 0001 C CNN 1 1450 2350 0 1 1 0 @@ -1292,19 +1291,19 @@ Text Notes 15200 7550 0 40 ~ 0 FPGA CLOCK NoConn ~ 13800 7200 $Comp -L GND #PWR027 +L GND #PWR98 U 1 1 4CD34DDD P 13750 7450 -F 0 "#PWR027" H 13750 7450 30 0001 C CNN +F 0 "#PWR98" H 13750 7450 30 0001 C CNN F 1 "GND" H 13750 7380 30 0001 C CNN 1 13750 7450 1 0 0 -1 $EndComp $Comp -L GND #PWR028 +L GND #PWR99 U 1 1 4CD34DC9 P 15050 6700 -F 0 "#PWR028" H 15050 6700 30 0001 C CNN +F 0 "#PWR99" H 15050 6700 30 0001 C CNN F 1 "GND" H 15050 6630 30 0001 C CNN 1 15050 6700 -1 0 0 1 @@ -1603,10 +1602,10 @@ FPGA_BANK0_IO_1 Text Label 9250 7050 0 60 ~ 0 FPGA_BANK0_IO_0 $Comp -L GND #PWR029 +L GND #PWR89 U 1 1 4CB241C7 P 4750 8950 -F 0 "#PWR029" H 4750 8950 30 0001 C CNN +F 0 "#PWR89" H 4750 8950 30 0001 C CNN F 1 "GND" H 4750 8880 30 0001 C CNN 1 4750 8950 1 0 0 -1 @@ -1948,19 +1947,19 @@ F 2 "0402" H 650 6550 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR030 +L +3.3V #PWR77 U 1 1 4C7168D5 P 650 6250 -F 0 "#PWR030" H 650 6210 30 0001 C CNN +F 0 "#PWR77" H 650 6210 30 0001 C CNN F 1 "+3.3V" H 650 6360 30 0000 C CNN 1 650 6250 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR031 +L +3.3V #PWR97 U 1 1 4C716889 P 8450 6600 -F 0 "#PWR031" H 8450 6560 30 0001 C CNN +F 0 "#PWR97" H 8450 6560 30 0001 C CNN F 1 "+3.3V" H 8450 6710 30 0000 C CNN 1 8450 6600 1 0 0 -1 @@ -1976,10 +1975,10 @@ F 2 "0402" H 8450 6900 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR032 +L GND #PWR96 U 1 1 4C716816 P 8050 7350 -F 0 "#PWR032" H 8050 7350 30 0001 C CNN +F 0 "#PWR96" H 8050 7350 30 0001 C CNN F 1 "GND" H 8050 7280 30 0001 C CNN 1 8050 7350 1 0 0 -1 @@ -2039,28 +2038,28 @@ $EndComp Text GLabel 12100 650 0 30 BiDi ~ 0 VCCO2 $Comp -L +3.3V #PWR033 +L +3.3V #PWR78 U 1 1 4C65CF66 P 1100 9500 -F 0 "#PWR033" H 1100 9460 30 0001 C CNN +F 0 "#PWR78" H 1100 9460 30 0001 C CNN F 1 "+3.3V" H 1100 9610 30 0000 C CNN 1 1100 9500 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR034 +L +2.5V #PWR85 U 1 1 4C65C84B P 3550 10450 -F 0 "#PWR034" H 3550 10400 20 0001 C CNN +F 0 "#PWR85" H 3550 10400 20 0001 C CNN F 1 "+2.5V" H 3550 10550 30 0000 C CNN 1 3550 10450 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR035 +L +2.5V #PWR80 U 1 1 4C65C837 P 1100 10400 -F 0 "#PWR035" H 1100 10350 20 0001 C CNN +F 0 "#PWR80" H 1100 10350 20 0001 C CNN F 1 "+2.5V" H 1100 10500 30 0000 C CNN 1 1100 10400 1 0 0 -1 @@ -2108,10 +2107,10 @@ F 2 "0402" H 2500 10700 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR036 +L GND #PWR81 U 1 1 4C656D9B P 1100 11000 -F 0 "#PWR036" H 1100 11000 30 0001 C CNN +F 0 "#PWR81" H 1100 11000 30 0001 C CNN F 1 "GND" H 1100 10930 30 0001 C CNN 1 1100 11000 1 0 0 -1 @@ -2179,10 +2178,10 @@ F 2 "0602" H 4950 9800 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR037 +L GND #PWR84 U 1 1 4C656D47 P 3550 10100 -F 0 "#PWR037" H 3550 10100 30 0001 C CNN +F 0 "#PWR84" H 3550 10100 30 0001 C CNN F 1 "GND" H 3550 10030 30 0001 C CNN 1 3550 10100 1 0 0 -1 @@ -2240,10 +2239,10 @@ F 2 "0402" H 4950 10750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR038 +L GND #PWR86 U 1 1 4C656CFD P 3550 11050 -F 0 "#PWR038" H 3550 11050 30 0001 C CNN +F 0 "#PWR86" H 3550 11050 30 0001 C CNN F 1 "GND" H 3550 10980 30 0001 C CNN 1 3550 11050 1 0 0 -1 @@ -2291,10 +2290,10 @@ F 2 "1210" H 3550 10750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR039 +L GND #PWR79 U 1 1 4C656CBC P 1100 10100 -F 0 "#PWR039" H 1100 10100 30 0001 C CNN +F 0 "#PWR79" H 1100 10100 30 0001 C CNN F 1 "GND" H 1100 10030 30 0001 C CNN 1 1100 10100 1 0 0 -1 @@ -2344,10 +2343,10 @@ $EndComp Text Notes 6050 10450 0 30 ~ 0 VCC_AUX Decoupling Capacitors (7) $Comp -L GND #PWR040 +L GND #PWR94 U 1 1 4C656C68 P 5950 11050 -F 0 "#PWR040" H 5950 11050 30 0001 C CNN +F 0 "#PWR94" H 5950 11050 30 0001 C CNN F 1 "GND" H 5950 10980 30 0001 C CNN 1 5950 11050 1 0 0 -1 @@ -2423,19 +2422,19 @@ F 2 "1210" H 5950 10750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR041 +L +2.5V #PWR93 U 1 1 4C656BBA P 5950 10450 -F 0 "#PWR041" H 5950 10400 20 0001 C CNN +F 0 "#PWR93" H 5950 10400 20 0001 C CNN F 1 "+2.5V" H 5950 10550 30 0000 C CNN 1 5950 10450 1 0 0 -1 $EndComp $Comp -L GND #PWR042 +L GND #PWR92 U 1 1 4C656BA8 P 5950 10050 -F 0 "#PWR042" H 5950 10050 30 0001 C CNN +F 0 "#PWR92" H 5950 10050 30 0001 C CNN F 1 "GND" H 5950 9980 30 0001 C CNN 1 5950 10050 1 0 0 -1 @@ -2473,10 +2472,10 @@ F 2 "0603" H 6300 9750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR043 +L +1.2V #PWR91 U 1 1 4C656AA1 P 5950 9450 -F 0 "#PWR043" H 5950 9590 20 0001 C CNN +F 0 "#PWR91" H 5950 9590 20 0001 C CNN F 1 "+1.2V" H 5950 9560 30 0000 C CNN 1 5950 9450 1 0 0 -1 @@ -2526,28 +2525,28 @@ NF_RE_N Text HLabel 5950 3350 2 60 BiDi ~ 0 NF_RNB $Comp -L +3.3V #PWR044 +L +3.3V #PWR87 U 1 1 4C61E5B3 P 3850 1800 -F 0 "#PWR044" H 3850 1760 30 0001 C CNN +F 0 "#PWR87" H 3850 1760 30 0001 C CNN F 1 "+3.3V" H 3850 1910 30 0000 C CNN 1 3850 1800 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR045 +L +1.2V #PWR90 U 1 1 4C61E58C P 4850 6150 -F 0 "#PWR045" H 4850 6290 20 0001 C CNN +F 0 "#PWR90" H 4850 6290 20 0001 C CNN F 1 "+1.2V" H 4850 6260 30 0000 C CNN 1 4850 6150 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR046 +L +2.5V #PWR83 U 1 1 4C61E577 P 3350 6150 -F 0 "#PWR046" H 3350 6100 20 0001 C CNN +F 0 "#PWR83" H 3350 6100 20 0001 C CNN F 1 "+2.5V" H 3350 6250 30 0000 C CNN 1 3350 6150 1 0 0 -1 @@ -2625,10 +2624,10 @@ ETH_MDC Text HLabel 2150 4450 0 60 BiDi ~ 0 ETH_INT $Comp -L GND #PWR047 +L GND #PWR88 U 1 1 4C439B7E P 4000 8000 -F 0 "#PWR047" H 4000 8000 30 0001 C CNN +F 0 "#PWR88" H 4000 8000 30 0001 C CNN F 1 "GND" H 4000 7930 30 0001 C CNN 1 4000 8000 -1 0 0 -1 diff --git a/xue-rnc/fpga2.sch b/xue-rnc/fpga2.sch index e599ecc..7dbbc12 100644 --- a/xue-rnc/fpga2.sch +++ b/xue-rnc/fpga2.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT +EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -53,13 +53,12 @@ LIBS:ft2232c LIBS:fxo-hc536r LIBS:zx62d-b-5p8 LIBS:a7130 -LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 4 9 Title "" -Date "29 dec 2010" +Date "31 dec 2010" Rev "" Comp "" Comment1 "" @@ -1563,19 +1562,19 @@ F 1 "R_PACK4" H 3400 6600 40 0000 C CNN -1 0 0 1 $EndComp $Comp -L +2.5V #PWR048 +L +2.5V #PWR75 U 1 1 4C61E523 P 9200 6250 -F 0 "#PWR048" H 9200 6200 20 0001 C CNN +F 0 "#PWR75" H 9200 6200 20 0001 C CNN F 1 "+2.5V" H 9200 6350 30 0000 C CNN 1 9200 6250 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR049 +L +2.5V #PWR76 U 1 1 4C61E51F P 9800 850 -F 0 "#PWR049" H 9800 800 20 0001 C CNN +F 0 "#PWR76" H 9800 800 20 0001 C CNN F 1 "+2.5V" H 9800 950 30 0000 C CNN 1 9800 850 1 0 0 -1 @@ -1593,10 +1592,10 @@ M1_BA[0..1] Text HLabel 4700 9500 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR050 +L GND #PWR74 U 1 1 4C60C21D P 6250 5650 -F 0 "#PWR050" H 6250 5650 30 0001 C CNN +F 0 "#PWR74" H 6250 5650 30 0001 C CNN F 1 "GND" H 6250 5580 30 0001 C CNN 1 6250 5650 -1 0 0 -1 diff --git a/xue-rnc/psu.sch b/xue-rnc/psu.sch index 25e2255..d4e70f1 100644 --- a/xue-rnc/psu.sch +++ b/xue-rnc/psu.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT +EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -53,13 +53,12 @@ LIBS:ft2232c LIBS:fxo-hc536r LIBS:zx62d-b-5p8 LIBS:a7130 -LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 2 9 Title "" -Date "29 dec 2010" +Date "31 dec 2010" Rev "" Comp "" Comment1 "" @@ -67,12 +66,15 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -Text Notes 6800 3850 0 120 Italic 24 -Design in progress!!! -Text Notes 6800 750 0 60 ~ 0 -BQ24070\nLiPo Charger\nSingle-Cell Li-Ion- or Li-Polymer- battery \nSupports Up to 2 Amps Total Current Wire Wire Line - 11800 1850 14450 1850 + 7150 4900 7150 5100 +Wire Wire Line + 7800 5100 7800 4800 +Connection ~ 7800 4900 +Wire Wire Line + 7950 4900 7800 4900 +Wire Wire Line + 14450 1850 11800 1850 Connection ~ 8400 1600 Wire Wire Line 8400 1450 8400 1700 @@ -84,7 +86,7 @@ Wire Wire Line 12200 2600 11800 2600 Connection ~ 12050 3350 Wire Wire Line - 12050 3350 12050 3450 + 12050 3450 12050 3350 Connection ~ 10850 3250 Wire Wire Line 10850 3350 10850 3250 @@ -150,7 +152,7 @@ Wire Wire Line 4850 9100 4850 10150 Connection ~ 2750 10150 Wire Wire Line - 2750 10100 2750 10250 + 2750 10250 2750 10100 Wire Wire Line 2500 10100 2500 10150 Wire Wire Line @@ -158,7 +160,7 @@ Wire Wire Line Wire Wire Line 2400 10150 2400 10100 Wire Wire Line - 1300 9100 850 9100 + 850 9100 1300 9100 Connection ~ 3450 9400 Wire Wire Line 3450 9400 3450 9300 @@ -206,7 +208,7 @@ Connection ~ 4800 7550 Connection ~ 4800 7250 Connection ~ 4800 7150 Wire Wire Line - 4800 7250 4800 7150 + 4800 7150 4800 7250 Wire Wire Line 4600 7300 4600 7250 Wire Wire Line @@ -266,7 +268,7 @@ Wire Wire Line Wire Wire Line 2250 5050 2250 4950 Wire Wire Line - 4300 4350 3300 4350 + 3300 4350 4300 4350 Wire Wire Line 3300 3750 4200 3750 Connection ~ 3900 3650 @@ -442,7 +444,7 @@ Wire Wire Line 1050 9200 1050 9100 Connection ~ 1050 9100 Wire Wire Line - 1900 9100 2000 9100 + 2000 9100 1900 9100 Wire Wire Line 2450 10250 2450 10150 Connection ~ 2450 10150 @@ -455,7 +457,7 @@ Wire Wire Line Wire Wire Line 3350 9700 3400 9700 Wire Wire Line - 4150 9400 3350 9400 + 3350 9400 4150 9400 Connection ~ 3950 9400 Wire Wire Line 4100 9650 4100 9850 @@ -474,7 +476,7 @@ Wire Wire Line Wire Wire Line 4850 10150 3750 10150 Wire Wire Line - 3250 10150 2750 10150 + 2750 10150 3250 10150 Wire Wire Line 4300 7300 4450 7150 Wire Wire Line @@ -482,7 +484,7 @@ Wire Wire Line Wire Wire Line 12000 2050 11800 2050 Wire Wire Line - 13100 2250 11800 2250 + 11800 2250 13100 2250 Wire Wire Line 12950 2300 12950 2250 Connection ~ 12950 2250 @@ -533,6 +535,60 @@ Wire Wire Line 13850 2550 13850 2400 Wire Wire Line 13850 1850 13850 2100 +Wire Wire Line + 7800 4800 7950 4800 +Wire Wire Line + 7800 4600 7800 4700 +Wire Wire Line + 7800 4700 7950 4700 +Wire Wire Line + 7150 4600 7150 4700 +Text GLabel 7150 4600 1 40 Input ~ 8 +Vin +$Comp +L GND #PWR66 +U 1 1 4D1DF63C +P 7150 5100 +F 0 "#PWR66" H 7150 5100 30 0001 C CNN +F 1 "GND" H 7150 5030 30 0001 C CNN + 1 7150 5100 + 1 0 0 -1 +$EndComp +$Comp +L CAP C180 +U 1 1 4D1DF629 +P 7150 4800 +F 0 "C180" H 7200 4900 50 0000 L CNN +F 1 "100nF" H 7200 4700 50 0000 L CNN +F 2 "0402" H 7150 4800 60 0001 C CNN + 1 7150 4800 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR67 +U 1 1 4D1DF611 +P 7800 5100 +F 0 "#PWR67" H 7800 5100 30 0001 C CNN +F 1 "GND" H 7800 5030 30 0001 C CNN + 1 7800 5100 + 1 0 0 -1 +$EndComp +Text GLabel 7800 4600 1 40 Input ~ 8 +Vin +$Comp +L PJ J8 +U 1 1 4D1DF550 +P 8500 4900 +F 0 "J8" H 8300 4800 60 0000 C CNN +F 1 "PJ" H 8300 5200 60 0000 C CNN +F 2 "PJ-CUI-TH" H 8500 4900 60 0001 C CNN + 1 8500 4900 + 1 0 0 -1 +$EndComp +Text Notes 6800 3850 0 120 Italic 24 +Design in progress!!! +Text Notes 6800 750 0 60 ~ 0 +BQ24070\nLiPo Charger\nSingle-Cell Li-Ion- or Li-Polymer- battery \nSupports Up to 2 Amps Total Current $Comp L CAP C178 U 1 1 4D1A14C5 @@ -554,10 +610,10 @@ F 2 "0402" H 14050 2250 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR01 +L GND #PWR73 U 1 1 4D1A14C3 P 13850 2550 -F 0 "#PWR01" H 13850 2550 30 0001 C CNN +F 0 "#PWR73" H 13850 2550 30 0001 C CNN F 1 "GND" H 13850 2480 30 0001 C CNN 1 13850 2550 1 0 0 -1 @@ -567,10 +623,10 @@ BQ24070 Text Notes 14250 3900 0 40 ~ 0 http://focus.ti.com/lit/ds/symlink/bq24071.pdf $Comp -L GND #PWR02 +L GND #PWR69 U 1 1 4D1A13BE P 9000 2700 -F 0 "#PWR02" H 9000 2700 30 0001 C CNN +F 0 "#PWR69" H 9000 2700 30 0001 C CNN F 1 "GND" H 9000 2630 30 0001 C CNN 1 9000 2700 1 0 0 -1 @@ -586,10 +642,10 @@ F 2 "0402" H 9000 2350 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR03 +L GND #PWR72 U 1 1 4D1A12B6 P 12950 2700 -F 0 "#PWR03" H 12950 2700 30 0001 C CNN +F 0 "#PWR72" H 12950 2700 30 0001 C CNN F 1 "GND" H 12950 2630 30 0001 C CNN 1 12950 2700 1 0 0 -1 @@ -615,19 +671,19 @@ F 2 "0402" H 11900 3050 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR04 +L GND #PWR71 U 1 1 4D1A120A P 12050 3450 -F 0 "#PWR04" H 12050 3450 30 0001 C CNN +F 0 "#PWR71" H 12050 3450 30 0001 C CNN F 1 "GND" H 12050 3380 30 0001 C CNN 1 12050 3450 1 0 0 -1 $EndComp $Comp -L GND #PWR05 +L GND #PWR70 U 1 1 4D1A1204 P 10850 3350 -F 0 "#PWR05" H 10850 3350 30 0001 C CNN +F 0 "#PWR70" H 10850 3350 30 0001 C CNN F 1 "GND" H 10850 3280 30 0001 C CNN 1 10850 3350 1 0 0 -1 @@ -643,10 +699,10 @@ F 2 "0805" H 12950 2400 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR06 +L GND #PWR68 U 1 1 4D1A0FF8 P 8400 2150 -F 0 "#PWR06" H 8400 2150 30 0001 C CNN +F 0 "#PWR68" H 8400 2150 30 0001 C CNN F 1 "GND" H 8400 2080 30 0001 C CNN 1 8400 2150 1 0 0 -1 @@ -698,19 +754,19 @@ $EndComp Text Notes 5100 11100 0 40 Italic 0 http://www.national.com/ds/LM/LM2621.pdf $Comp -L GND #PWR07 +L GND #PWR64 U 1 1 4D1409D1 P 5300 9650 -F 0 "#PWR07" H 5300 9650 30 0001 C CNN +F 0 "#PWR64" H 5300 9650 30 0001 C CNN F 1 "GND" H 5300 9580 30 0001 C CNN 1 5300 9650 1 0 0 -1 $EndComp $Comp -L GND #PWR08 +L GND #PWR61 U 1 1 4D14097D P 4100 9850 -F 0 "#PWR08" H 4100 9850 30 0001 C CNN +F 0 "#PWR61" H 4100 9850 30 0001 C CNN F 1 "GND" H 4100 9780 30 0001 C CNN 1 4100 9850 1 0 0 -1 @@ -726,28 +782,28 @@ F 2 "0402" H 4100 9550 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR09 +L GND #PWR57 U 1 1 4D14083D P 2750 10850 -F 0 "#PWR09" H 2750 10850 30 0001 C CNN +F 0 "#PWR57" H 2750 10850 30 0001 C CNN F 1 "GND" H 2750 10780 30 0001 C CNN 1 2750 10850 1 0 0 -1 $EndComp $Comp -L GND #PWR010 +L GND #PWR55 U 1 1 4D140715 P 2450 10250 -F 0 "#PWR010" H 2450 10250 30 0001 C CNN +F 0 "#PWR55" H 2450 10250 30 0001 C CNN F 1 "GND" H 2450 10180 30 0001 C CNN 1 2450 10250 1 0 0 -1 $EndComp $Comp -L GND #PWR011 +L GND #PWR49 U 1 1 4D140708 P 1050 9650 -F 0 "#PWR011" H 1050 9650 30 0001 C CNN +F 0 "#PWR49" H 1050 9650 30 0001 C CNN F 1 "GND" H 1050 9580 30 0001 C CNN 1 1050 9650 1 0 0 -1 @@ -843,10 +899,10 @@ F 2 "1210" H 1600 9100 60 0001 C CNN 0 1 1 0 $EndComp $Comp -L GND #PWR012 +L GND #PWR54 U 1 1 4D140270 P 2100 7600 -F 0 "#PWR012" H 2100 7600 30 0001 C CNN +F 0 "#PWR54" H 2100 7600 30 0001 C CNN F 1 "GND" H 2100 7530 30 0001 C CNN 1 2100 7600 1 0 0 -1 @@ -862,10 +918,10 @@ F 2 "0805" H 4000 7150 60 0001 C CNN 0 1 1 0 $EndComp $Comp -L GND #PWR013 +L GND #PWR51 U 1 1 4D14016E P 1300 7550 -F 0 "#PWR013" H 1300 7550 30 0001 C CNN +F 0 "#PWR51" H 1300 7550 30 0001 C CNN F 1 "GND" H 1300 7480 30 0001 C CNN 1 1300 7550 1 0 0 -1 @@ -901,10 +957,10 @@ F 2 "0402" H 5000 7400 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR014 +L GND #PWR62 U 1 1 4D140161 P 4800 7700 -F 0 "#PWR014" H 4800 7700 30 0001 C CNN +F 0 "#PWR62" H 4800 7700 30 0001 C CNN F 1 "GND" H 4800 7630 30 0001 C CNN 1 4800 7700 1 0 0 -1 @@ -912,10 +968,10 @@ $EndComp Text Notes 4550 8200 0 40 ~ 0 http://www.onsemi.com/pub_link/Collateral/NCP1529-D.PDF $Comp -L GND #PWR015 +L GND #PWR65 U 1 1 4D13FF19 P 5450 4900 -F 0 "#PWR015" H 5450 4900 30 0001 C CNN +F 0 "#PWR65" H 5450 4900 30 0001 C CNN F 1 "GND" H 5450 4830 30 0001 C CNN 1 5450 4900 1 0 0 -1 @@ -941,10 +997,10 @@ F 2 "0402" H 5250 1800 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR016 +L GND #PWR63 U 1 1 4D13FF2E P 5050 2100 -F 0 "#PWR016" H 5050 2100 30 0001 C CNN +F 0 "#PWR63" H 5050 2100 30 0001 C CNN F 1 "GND" H 5050 2030 30 0001 C CNN 1 5050 2100 1 0 0 -1 @@ -960,28 +1016,28 @@ F 2 "0402" H 5650 4600 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR017 +L GND #PWR59 U 1 1 4D13FEDF P 3050 3400 -F 0 "#PWR017" H 3050 3400 30 0001 C CNN +F 0 "#PWR59" H 3050 3400 30 0001 C CNN F 1 "GND" H 3050 3330 30 0001 C CNN 1 3050 3400 1 0 0 -1 $EndComp $Comp -L GND #PWR018 +L GND #PWR56 U 1 1 4D13FECF P 2650 5900 -F 0 "#PWR018" H 2650 5900 30 0001 C CNN +F 0 "#PWR56" H 2650 5900 30 0001 C CNN F 1 "GND" H 2650 5830 30 0001 C CNN 1 2650 5900 1 0 0 -1 $EndComp $Comp -L GND #PWR019 +L GND #PWR58 U 1 1 4D13FEC8 P 2850 5650 -F 0 "#PWR019" H 2850 5650 30 0001 C CNN +F 0 "#PWR58" H 2850 5650 30 0001 C CNN F 1 "GND" H 2850 5580 30 0001 C CNN 1 2850 5650 1 0 0 -1 @@ -997,10 +1053,10 @@ F 2 "0805" H 1100 4200 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR020 +L GND #PWR50 U 1 1 4D13FEB5 P 1100 4600 -F 0 "#PWR020" H 1100 4600 30 0001 C CNN +F 0 "#PWR50" H 1100 4600 30 0001 C CNN F 1 "GND" H 1100 4530 30 0001 C CNN 1 1100 4600 1 0 0 -1 @@ -1117,37 +1173,37 @@ Design in progress!!! Text Notes 1900 1100 0 40 ~ 0 ???\n $Comp -L GND #PWR021 +L GND #PWR53 U 1 1 4D13F926 P 1950 2000 -F 0 "#PWR021" H 1950 2000 30 0001 C CNN +F 0 "#PWR53" H 1950 2000 30 0001 C CNN F 1 "GND" H 1950 1930 30 0001 C CNN 1 1950 2000 1 0 0 -1 $EndComp $Comp -L GND #PWR022 +L GND #PWR52 U 1 1 4D13F8E2 P 1700 2550 -F 0 "#PWR022" H 1700 2550 30 0001 C CNN +F 0 "#PWR52" H 1700 2550 30 0001 C CNN F 1 "GND" H 1700 2480 30 0001 C CNN 1 1700 2550 1 0 0 -1 $EndComp $Comp -L GND #PWR023 +L GND #PWR48 U 1 1 4D13F81E P 1050 1900 -F 0 "#PWR023" H 1050 1900 30 0001 C CNN +F 0 "#PWR48" H 1050 1900 30 0001 C CNN F 1 "GND" H 1050 1830 30 0001 C CNN 1 1050 1900 1 0 0 -1 $EndComp $Comp -L GND #PWR024 +L GND #PWR60 U 1 1 4D13F818 P 3700 2400 -F 0 "#PWR024" H 3700 2400 30 0001 C CNN +F 0 "#PWR60" H 3700 2400 30 0001 C CNN F 1 "GND" H 3700 2330 30 0001 C CNN 1 3700 2400 1 0 0 -1 diff --git a/xue-rnc/sdram.sch b/xue-rnc/sdram.sch index b3ec1c9..bb8d610 100644 --- a/xue-rnc/sdram.sch +++ b/xue-rnc/sdram.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT +EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -53,13 +53,12 @@ LIBS:ft2232c LIBS:fxo-hc536r LIBS:zx62d-b-5p8 LIBS:a7130 -LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 6 9 Title "" -Date "29 dec 2010" +Date "31 dec 2010" Rev "" Comp "" Comment1 "" @@ -543,19 +542,19 @@ Entry Wire Line Entry Wire Line 10100 4400 10200 4500 $Comp -L GND #PWR059 +L GND #PWR16 U 1 1 4C699C4D P 9950 2100 -F 0 "#PWR059" H 9950 2100 30 0001 C CNN +F 0 "#PWR16" H 9950 2100 30 0001 C CNN F 1 "GND" H 9950 2030 30 0001 C CNN 1 9950 2100 1 0 0 -1 $EndComp $Comp -L GND #PWR060 +L GND #PWR8 U 1 1 4C699C48 P 4550 2150 -F 0 "#PWR060" H 4550 2150 30 0001 C CNN +F 0 "#PWR8" H 4550 2150 30 0001 C CNN F 1 "GND" H 4550 2080 30 0001 C CNN 1 4550 2150 1 0 0 -1 @@ -613,37 +612,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR061 +L GND #PWR10 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR061" H 6900 6200 30 0001 C CNN +F 0 "#PWR10" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR062 +L +2.5V #PWR9 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR062" H 6900 5750 20 0001 C CNN +F 0 "#PWR9" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR063 +L +2.5V #PWR1 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR063" H 1700 5750 20 0001 C CNN +F 0 "#PWR1" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR064 +L GND #PWR2 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR064" H 1700 6200 30 0001 C CNN +F 0 "#PWR2" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -659,19 +658,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR065 +L +2.5V #PWR4 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR065" H 3050 1700 20 0001 C CNN +F 0 "#PWR4" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR066 +L +2.5V #PWR14 U 1 1 4C61CFC6 P 8400 1700 -F 0 "#PWR066" H 8400 1650 20 0001 C CNN +F 0 "#PWR14" H 8400 1650 20 0001 C CNN F 1 "+2.5V" H 8400 1800 30 0000 C CNN 1 8400 1700 1 0 0 -1 @@ -737,37 +736,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR067 +L +2.5V #PWR11 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR067" H 8300 5700 20 0001 C CNN +F 0 "#PWR11" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR068 +L GND #PWR12 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR068" H 8300 6350 30 0001 C CNN +F 0 "#PWR12" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR069 +L GND #PWR6 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR069" H 3050 6350 30 0001 C CNN +F 0 "#PWR6" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR070 +L +2.5V #PWR5 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR070" H 3050 5700 20 0001 C CNN +F 0 "#PWR5" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -853,19 +852,19 @@ F 2 "0402" H 9950 1750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR071 +L +2.5V #PWR15 U 1 1 4C61CE2F P 9950 800 -F 0 "#PWR071" H 9950 750 20 0001 C CNN +F 0 "#PWR15" H 9950 750 20 0001 C CNN F 1 "+2.5V" H 9950 900 30 0000 C CNN 1 9950 800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR072 +L +2.5V #PWR7 U 1 1 4C61CDF1 P 4550 850 -F 0 "#PWR072" H 4550 800 20 0001 C CNN +F 0 "#PWR7" H 4550 800 20 0001 C CNN F 1 "+2.5V" H 4550 950 30 0000 C CNN 1 4550 850 1 0 0 -1 @@ -948,10 +947,10 @@ $EndComp Text HLabel 5000 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR073 +L GND #PWR3 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR073" H 3000 5200 30 0001 C CNN +F 0 "#PWR3" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1227,10 +1226,10 @@ Entry Wire Line Entry Wire Line 10100 3600 10200 3700 $Comp -L GND #PWR074 +L GND #PWR13 U 1 1 4C437C3F P 8350 5150 -F 0 "#PWR074" H 8350 5150 30 0001 C CNN +F 0 "#PWR13" H 8350 5150 30 0001 C CNN F 1 "GND" H 8350 5080 30 0001 C CNN 1 8350 5150 1 0 0 -1 diff --git a/xue-rnc/usb.sch b/xue-rnc/usb.sch index 3aba926..cd8ee01 100644 --- a/xue-rnc/usb.sch +++ b/xue-rnc/usb.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT +EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -53,13 +53,12 @@ LIBS:ft2232c LIBS:fxo-hc536r LIBS:zx62d-b-5p8 LIBS:a7130 -LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 8 9 Title "" -Date "29 dec 2010" +Date "31 dec 2010" Rev "" Comp "" Comment1 "" @@ -379,10 +378,10 @@ F 1 "15k" V 3975 6100 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR075 +L +3.3V #PWR41 U 1 1 4C7D365E P 3975 5750 -F 0 "#PWR075" H 3975 5710 30 0001 C CNN +F 0 "#PWR41" H 3975 5710 30 0001 C CNN F 1 "+3.3V" H 3975 5860 30 0000 C CNN 1 3975 5750 1 0 0 -1 @@ -394,10 +393,10 @@ USBA_D- Text Label 4125 6550 0 40 ~ 0 USBD_D- $Comp -L GND #PWR076 +L GND #PWR27 U 1 1 4C7D3584 P 1750 7150 -F 0 "#PWR076" H 1750 7150 30 0001 C CNN +F 0 "#PWR27" H 1750 7150 30 0001 C CNN F 1 "GND" H 1750 7080 30 0001 C CNN 1 1750 7150 1 0 0 -1 @@ -422,10 +421,10 @@ F 1 "24" V 2400 6550 50 0000 C CNN 0 1 1 0 $EndComp $Comp -L GND #PWR077 +L GND #PWR28 U 1 1 4C7D353A P 1850 3450 -F 0 "#PWR077" H 1850 3450 30 0001 C CNN +F 0 "#PWR28" H 1850 3450 30 0001 C CNN F 1 "GND" H 1850 3380 30 0001 C CNN 1 1850 3450 1 0 0 -1 @@ -455,10 +454,10 @@ USB_CASE_DEV Text Label 5850 2950 0 40 ~ 0 USB_CASE_HOST $Comp -L +3.3V #PWR078 +L +3.3V #PWR42 U 1 1 4C7D32BA P 4350 2050 -F 0 "#PWR078" H 4350 2010 30 0001 C CNN +F 0 "#PWR42" H 4350 2010 30 0001 C CNN F 1 "+3.3V" H 4350 2160 30 0000 C CNN 1 4350 2050 1 0 0 -1 @@ -526,91 +525,91 @@ F 2 "MLF16" H 1700 2750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR079 +L +3.3V #PWR34 U 1 1 4C695F50 P 2700 4600 -F 0 "#PWR079" H 2700 4560 30 0001 C CNN +F 0 "#PWR34" H 2700 4560 30 0001 C CNN F 1 "+3.3V" H 2700 4710 30 0000 C CNN 1 2700 4600 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR080 +L +3.3V #PWR29 U 1 1 4C695F4B P 2100 6100 -F 0 "#PWR080" H 2100 6060 30 0001 C CNN +F 0 "#PWR29" H 2100 6060 30 0001 C CNN F 1 "+3.3V" H 2100 6210 30 0000 C CNN 1 2100 6100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR081 +L +3.3V #PWR32 U 1 1 4C695F43 P 2650 1100 -F 0 "#PWR081" H 2650 1060 30 0001 C CNN +F 0 "#PWR32" H 2650 1060 30 0001 C CNN F 1 "+3.3V" H 2650 1210 30 0000 C CNN 1 2650 1100 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR082 +L +3.3V #PWR30 U 1 1 4C695F3B P 2200 2400 -F 0 "#PWR082" H 2200 2360 30 0001 C CNN +F 0 "#PWR30" H 2200 2360 30 0001 C CNN F 1 "+3.3V" H 2200 2510 30 0000 C CNN 1 2200 2400 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR083 +L +2.5V #PWR39 U 1 1 4C695DCD P 3200 4550 -F 0 "#PWR083" H 3200 4500 20 0001 C CNN +F 0 "#PWR39" H 3200 4500 20 0001 C CNN F 1 "+2.5V" H 3200 4650 30 0000 C CNN 1 3200 4550 1 0 0 -1 $EndComp $Comp -L GND #PWR084 +L GND #PWR40 U 1 1 4C695F0A P 3200 5550 -F 0 "#PWR084" H 3200 5550 30 0001 C CNN +F 0 "#PWR40" H 3200 5550 30 0001 C CNN F 1 "GND" H 3200 5480 30 0001 C CNN 1 3200 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR085 +L GND #PWR33 U 1 1 4C695F09 P 2650 5550 -F 0 "#PWR085" H 2650 5550 30 0001 C CNN +F 0 "#PWR33" H 2650 5550 30 0001 C CNN F 1 "GND" H 2650 5480 30 0001 C CNN 1 2650 5550 1 0 0 -1 $EndComp $Comp -L GND #PWR086 +L GND #PWR37 U 1 1 4C695DFE P 3150 1850 -F 0 "#PWR086" H 3150 1850 30 0001 C CNN +F 0 "#PWR37" H 3150 1850 30 0001 C CNN F 1 "GND" H 3150 1780 30 0001 C CNN 1 3150 1850 1 0 0 -1 $EndComp $Comp -L GND #PWR087 +L GND #PWR31 U 1 1 4C695DF8 P 2600 1850 -F 0 "#PWR087" H 2600 1850 30 0001 C CNN +F 0 "#PWR31" H 2600 1850 30 0001 C CNN F 1 "GND" H 2600 1780 30 0001 C CNN 1 2600 1850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR088 +L +2.5V #PWR36 U 1 1 4C695DA7 P 3150 1100 -F 0 "#PWR088" H 3150 1050 20 0001 C CNN +F 0 "#PWR36" H 3150 1050 20 0001 C CNN F 1 "+2.5V" H 3150 1200 30 0000 C CNN 1 3150 1100 1 0 0 -1 @@ -695,28 +694,28 @@ USBD_VP Text HLabel 1200 6750 0 40 BiDi ~ 0 USBD_VM $Comp -L GND #PWR089 +L GND #PWR46 U 1 1 4C6552B5 P 5500 7400 -F 0 "#PWR089" H 5500 7400 30 0001 C CNN +F 0 "#PWR46" H 5500 7400 30 0001 C CNN F 1 "GND" H 5500 7330 30 0001 C CNN 1 5500 7400 1 0 0 -1 $EndComp $Comp -L GND #PWR090 +L GND #PWR38 U 1 1 4C6552B4 P 3150 7500 -F 0 "#PWR090" H 3150 7500 30 0001 C CNN +F 0 "#PWR38" H 3150 7500 30 0001 C CNN F 1 "GND" H 3150 7430 30 0001 C CNN 1 3150 7500 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR091 +L +2.5V #PWR25 U 1 1 4C6552B2 P 1150 6150 -F 0 "#PWR091" H 1150 6100 20 0001 C CNN +F 0 "#PWR25" H 1150 6100 20 0001 C CNN F 1 "+2.5V" H 1150 6250 30 0000 C CNN 1 1150 6150 1 0 0 -1 @@ -732,28 +731,28 @@ F 2 "0603" H 4650 7000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR092 +L GND #PWR43 U 1 1 4C6552AE P 4650 7350 -F 0 "#PWR092" H 4650 7350 30 0001 C CNN +F 0 "#PWR43" H 4650 7350 30 0001 C CNN F 1 "GND" H 4650 7280 30 0001 C CNN 1 4650 7350 1 0 0 -1 $EndComp $Comp -L GND #PWR093 +L GND #PWR45 U 1 1 4C63F2B5 P 4900 3700 -F 0 "#PWR093" H 4900 3700 30 0001 C CNN +F 0 "#PWR45" H 4900 3700 30 0001 C CNN F 1 "GND" H 4900 3630 30 0001 C CNN 1 4900 3700 1 0 0 -1 $EndComp $Comp -L +5V #PWR094 +L +5V #PWR44 U 1 1 4C63F295 P 4700 1350 -F 0 "#PWR094" H 4700 1440 20 0001 C CNN +F 0 "#PWR44" H 4700 1440 20 0001 C CNN F 1 "+5V" H 4700 1440 30 0000 C CNN 1 4700 1350 1 0 0 -1 @@ -779,28 +778,28 @@ F 2 "0603" H 4900 3350 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR095 +L +2.5V #PWR26 U 1 1 4C63EC16 P 1250 2450 -F 0 "#PWR095" H 1250 2400 20 0001 C CNN +F 0 "#PWR26" H 1250 2400 20 0001 C CNN F 1 "+2.5V" H 1250 2550 30 0000 C CNN 1 1250 2450 1 0 0 -1 $EndComp $Comp -L GND #PWR096 +L GND #PWR35 U 1 1 4C63EA1B P 3100 3800 -F 0 "#PWR096" H 3100 3800 30 0001 C CNN +F 0 "#PWR35" H 3100 3800 30 0001 C CNN F 1 "GND" H 3100 3730 30 0001 C CNN 1 3100 3800 1 0 0 -1 $EndComp $Comp -L GND #PWR097 +L GND #PWR47 U 1 1 4C63E9FA P 5950 3750 -F 0 "#PWR097" H 5950 3750 30 0001 C CNN +F 0 "#PWR47" H 5950 3750 30 0001 C CNN F 1 "GND" H 5950 3680 30 0001 C CNN 1 5950 3750 1 0 0 -1 diff --git a/xue-rnc/xue-rnc.brd b/xue-rnc/xue-rnc.brd index 154e38f..0807718 100644 --- a/xue-rnc/xue-rnc.brd +++ b/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Wed 29 Dec 2010 01:38:30 PM COT +PCBNEW-BOARD Version 1 date Fri 31 Dec 2010 10:32:51 AM COT # Created by Pcbnew(2010-10-01 BZR 2513)-testing @@ -6,21 +6,21 @@ $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 13FF801F -Links 835 -NoConn 155 -Di 45633 12844 80041 52832 +Links 839 +NoConn 159 +Di 45633 7776 80041 52832 Ndraw 6 Ntrack 4940 Nzone 0 BoardThickness 630 -Nmodule 215 -Nnets 337 +Nmodule 217 +Nnets 338 $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "29 dec 2010" +Date "31 dec 2010" Rev "" Comp "" Comment1 "" @@ -68,8 +68,8 @@ TextPcbSize 394 591 EdgeModWidth 59 TextModSize 600 600 TextModWidth 120 -PadSize 196 393 -PadDrill 0 +PadSize 984 551 +PadDrill 748 Pad2MaskClearance 100 AuxiliaryAxisOrg 0 0 $EndSETUP @@ -107,419 +107,419 @@ Na 7 "/ether/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/ether/ETH_CLK" +Na 8 "/ether/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/ether/ETH_COL" +Na 9 "/ether/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/ether/ETH_CRS" +Na 10 "/ether/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/ether/ETH_INT" +Na 11 "/ether/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/ether/ETH_LED0" +Na 12 "/ether/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/ether/ETH_LED1" +Na 13 "/ether/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/ether/ETH_MDC" +Na 14 "/ether/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/ether/ETH_MDIO" +Na 15 "/ether/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/ether/ETH_PLL1.8V" +Na 16 "/ether/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/ether/ETH_RXC" +Na 17 "/ether/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/ether/ETH_RXDV" +Na 18 "/ether/MAG_RX+" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/ether/ETH_TXD0" +Na 19 "/ether/MAG_RX-" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/ether/ETH_TXD3" +Na 20 "/ether/MAG_SHIELD" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/ether/ETH_TXER" +Na 21 "/ether/MAG_TX+" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/ether/MAG_RX+" +Na 22 "/ether/MAG_TX-" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/ether/MAG_RX-" +Na 23 "/expansion/FPGA_BANK0_IO_11" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/ether/MAG_SHIELD" +Na 24 "/expansion/FPGA_BANK0_IO_12" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/ether/MAG_TX+" +Na 25 "/expansion/FPGA_BANK0_IO_14" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/ether/MAG_TX-" +Na 26 "/expansion/FPGA_BANK0_IO_15" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/expansion/FPGA_BANK0_IO_1" +Na 27 "/expansion/FPGA_BANK0_IO_22" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/expansion/FPGA_BANK0_IO_10" +Na 28 "/expansion/FPGA_BANK0_IO_24" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/expansion/FPGA_BANK0_IO_11" +Na 29 "/expansion/FPGA_BANK0_IO_28" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/expansion/FPGA_BANK0_IO_15" +Na 30 "/expansion/FPGA_BANK0_IO_3" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/expansion/FPGA_BANK0_IO_17" +Na 31 "/expansion/FPGA_BANK0_IO_33" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/expansion/FPGA_BANK0_IO_2" +Na 32 "/expansion/FPGA_BANK0_IO_34" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/expansion/FPGA_BANK0_IO_20" +Na 33 "/expansion/FPGA_BANK0_IO_36" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/expansion/FPGA_BANK0_IO_21" +Na 34 "/expansion/FPGA_BANK0_IO_38" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/expansion/FPGA_BANK0_IO_29" +Na 35 "/expansion/FPGA_BANK0_IO_39" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/expansion/FPGA_BANK0_IO_3" +Na 36 "/expansion/FPGA_BANK0_IO_40" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/expansion/FPGA_BANK0_IO_32" +Na 37 "/expansion/FPGA_BANK0_IO_43" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/expansion/FPGA_BANK0_IO_34" +Na 38 "/expansion/FPGA_BANK0_IO_44" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/expansion/FPGA_BANK0_IO_38" +Na 39 "/expansion/FPGA_BANK0_IO_45" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/expansion/FPGA_BANK0_IO_39" +Na 40 "/expansion/FPGA_BANK0_IO_46" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/expansion/FPGA_BANK0_IO_40" +Na 41 "/expansion/FPGA_BANK0_IO_47" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/expansion/FPGA_BANK0_IO_43" +Na 42 "/expansion/FPGA_BANK0_IO_48" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/expansion/FPGA_BANK0_IO_46" +Na 43 "/expansion/FPGA_BANK0_IO_5" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/expansion/FPGA_BANK0_IO_47" +Na 44 "/expansion/FPGA_BANK0_IO_51" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/expansion/FPGA_BANK0_IO_5" +Na 45 "/expansion/FPGA_BANK0_IO_62" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/expansion/FPGA_BANK0_IO_50" +Na 46 "/expansion/FPGA_BANK0_IO_7" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/expansion/FPGA_BANK0_IO_54" +Na 47 "/expansion/FPGA_BANK0_IO_9" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/expansion/FPGA_BANK0_IO_6" +Na 48 "/flash/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/expansion/FPGA_BANK0_IO_7" +Na 49 "/flash/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/expansion/FPGA_BANK0_IO_9" +Na 50 "/flash/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/flash/NF_ALE" +Na 51 "/flash/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/flash/NF_CLE" +Na 52 "/flash/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/flash/NF_CS1_N" +Na 53 "/flash/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/flash/NF_D0" +Na 54 "/fpga1/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/flash/NF_D1" +Na 55 "/fpga1/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/flash/NF_D3" +Na 56 "/fpga1/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/flash/NF_D5" +Na 57 "/fpga1/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/flash/NF_D7" +Na 58 "/fpga1/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/flash/NF_RE_N" +Na 59 "/fpga1/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/flash/SD_DAT2" +Na 60 "/fpga1/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/fpga1/ETH_RESET_N" +Na 61 "/fpga1/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/fpga1/ETH_RXD0" +Na 62 "/fpga1/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/fpga1/ETH_RXD1" +Na 63 "/fpga1/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/fpga1/ETH_RXD2" +Na 64 "/fpga1/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/fpga1/ETH_RXD3" +Na 65 "/fpga1/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/fpga1/ETH_RXER" +Na 66 "/fpga1/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/fpga1/ETH_TXC" +Na 67 "/fpga1/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/fpga1/ETH_TXD1" +Na 68 "/fpga1/FPGA_BANK0_IO_1" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/fpga1/ETH_TXD2" +Na 69 "/fpga1/FPGA_BANK0_IO_10" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/fpga1/ETH_TXEN" +Na 70 "/fpga1/FPGA_BANK0_IO_17" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/fpga1/FPGA_BANK0_IO_12" +Na 71 "/fpga1/FPGA_BANK0_IO_18" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/fpga1/FPGA_BANK0_IO_14" +Na 72 "/fpga1/FPGA_BANK0_IO_2" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/fpga1/FPGA_BANK0_IO_18" +Na 73 "/fpga1/FPGA_BANK0_IO_20" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/fpga1/FPGA_BANK0_IO_22" +Na 74 "/fpga1/FPGA_BANK0_IO_21" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/fpga1/FPGA_BANK0_IO_24" +Na 75 "/fpga1/FPGA_BANK0_IO_25" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/fpga1/FPGA_BANK0_IO_25" +Na 76 "/fpga1/FPGA_BANK0_IO_27" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/fpga1/FPGA_BANK0_IO_27" +Na 77 "/fpga1/FPGA_BANK0_IO_29" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/fpga1/FPGA_BANK0_IO_28" +Na 78 "/fpga1/FPGA_BANK0_IO_30" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/fpga1/FPGA_BANK0_IO_30" +Na 79 "/fpga1/FPGA_BANK0_IO_32" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/fpga1/FPGA_BANK0_IO_33" +Na 80 "/fpga1/FPGA_BANK0_IO_49" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/fpga1/FPGA_BANK0_IO_36" +Na 81 "/fpga1/FPGA_BANK0_IO_50" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/fpga1/FPGA_BANK0_IO_44" +Na 82 "/fpga1/FPGA_BANK0_IO_52" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/fpga1/FPGA_BANK0_IO_45" +Na 83 "/fpga1/FPGA_BANK0_IO_53" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/fpga1/FPGA_BANK0_IO_48" +Na 84 "/fpga1/FPGA_BANK0_IO_54" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/fpga1/FPGA_BANK0_IO_49" +Na 85 "/fpga1/FPGA_BANK0_IO_56" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/fpga1/FPGA_BANK0_IO_51" +Na 86 "/fpga1/FPGA_BANK0_IO_57" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/fpga1/FPGA_BANK0_IO_52" +Na 87 "/fpga1/FPGA_BANK0_IO_58" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/fpga1/FPGA_BANK0_IO_53" +Na 88 "/fpga1/FPGA_BANK0_IO_6" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/fpga1/FPGA_BANK0_IO_56" +Na 89 "/fpga1/FPGA_BANK0_IO_60" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/fpga1/FPGA_BANK0_IO_57" +Na 90 "/fpga1/FPGA_BANK0_IO_63" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/fpga1/FPGA_BANK0_IO_58" +Na 91 "/fpga1/FPGA_BANK0_IO_8" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/fpga1/FPGA_BANK0_IO_60" +Na 92 "/fpga1/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/fpga1/FPGA_BANK0_IO_62" +Na 93 "/fpga1/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/fpga1/FPGA_BANK0_IO_63" +Na 94 "/fpga1/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/fpga1/FPGA_BANK0_IO_8" +Na 95 "/fpga1/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/fpga1/NF_D2" +Na 96 "/fpga1/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/fpga1/NF_D4" +Na 97 "/fpga1/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/fpga1/NF_D6" +Na 98 "/fpga1/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/fpga1/NF_RNB" +Na 99 "/fpga1/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/fpga1/NF_WE_N" +Na 100 "/fpga1/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/fpga1/PROG_CCLK" +Na 101 "/fpga1/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/fpga1/PROG_CSO" +Na 102 "/fpga1/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/fpga1/PROG_MISO0" +Na 103 "/fpga1/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/fpga1/PROG_MISO1" +Na 104 "/fpga1/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/fpga1/PROG_MISO2" +Na 105 "/fpga1/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/fpga1/PROG_MISO3" +Na 106 "/fpga1/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/fpga1/SD_CLK" +Na 107 "/fpga1/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/fpga1/SD_CMD" +Na 108 "/fpga1/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/fpga1/SD_DAT0" +Na 109 "/fpga1/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/fpga1/SD_DAT1" +Na 110 "/fpga1/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/fpga1/SD_DAT3" +Na 111 "/fpga1/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT @@ -531,15 +531,15 @@ Na 113 "/fpga2/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/fpga2/M0_A12" +Na 114 "/fpga2/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/fpga2/M0_A2" +Na 115 "/fpga2/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/fpga2/M0_A4" +Na 116 "/fpga2/M0_A2" St ~ $EndEQUIPOT $EQUIPOT @@ -551,567 +551,567 @@ Na 118 "/fpga2/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/fpga2/M0_A8" +Na 119 "/fpga2/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/fpga2/M0_A9" +Na 120 "/fpga2/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/fpga2/M0_BA0" +Na 121 "/fpga2/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/fpga2/M0_CAS#" +Na 122 "/fpga2/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/fpga2/M0_CLK" +Na 123 "/fpga2/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/fpga2/M0_DQ0" +Na 124 "/fpga2/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/fpga2/M0_DQ1" +Na 125 "/fpga2/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/fpga2/M0_DQ10" +Na 126 "/fpga2/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/fpga2/M0_DQ11" +Na 127 "/fpga2/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/fpga2/M0_DQ15" +Na 128 "/fpga2/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/fpga2/M0_DQ2" +Na 129 "/fpga2/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/fpga2/M0_DQ3" +Na 130 "/fpga2/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/fpga2/M0_DQ6" +Na 131 "/fpga2/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/fpga2/M0_DQ7" +Na 132 "/fpga2/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/fpga2/M0_DQ9" +Na 133 "/fpga2/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/fpga2/M0_LDM" +Na 134 "/fpga2/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/fpga2/M0_LDQS" +Na 135 "/fpga2/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/fpga2/M0_UDM" +Na 136 "/fpga2/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/fpga2/M1_A0" +Na 137 "/fpga2/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/fpga2/M1_A11" +Na 138 "/fpga2/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/fpga2/M1_A2" +Na 139 "/fpga2/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/fpga2/M1_A6" +Na 140 "/fpga2/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/fpga2/M1_A7" +Na 141 "/fpga2/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/fpga2/M1_A8" +Na 142 "/fpga2/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/fpga2/M1_A9" +Na 143 "/fpga2/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/fpga2/M1_BA1" +Na 144 "/fpga2/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/fpga2/M1_CKE" +Na 145 "/fpga2/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/fpga2/M1_CLK" +Na 146 "/fpga2/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/fpga2/M1_CLK#" +Na 147 "/fpga2/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/fpga2/M1_CS#" +Na 148 "/fpga2/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/fpga2/M1_DQ0" +Na 149 "/fpga2/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/fpga2/M1_DQ10" +Na 150 "/fpga2/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/fpga2/M1_DQ11" +Na 151 "/fpga2/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/fpga2/M1_DQ14" +Na 152 "/fpga2/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/fpga2/M1_DQ15" +Na 153 "/fpga2/R_M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/fpga2/M1_DQ2" +Na 154 "/fpga2/R_M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/fpga2/M1_DQ3" +Na 155 "/fpga2/R_M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/fpga2/M1_DQ4" +Na 156 "/fpga2/R_M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/fpga2/M1_DQ7" +Na 157 "/fpga2/R_M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/fpga2/M1_DQ8" +Na 158 "/fpga2/R_M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/fpga2/M1_DQ9" +Na 159 "/fpga2/R_M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/fpga2/M1_LDM" +Na 160 "/fpga2/R_M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/fpga2/M1_UDQS" +Na 161 "/fpga2/R_M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/fpga2/R_M0_A0" +Na 162 "/fpga2/R_M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/fpga2/R_M0_A1" +Na 163 "/fpga2/R_M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/fpga2/R_M0_A10" +Na 164 "/fpga2/R_M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/fpga2/R_M0_A11" +Na 165 "/fpga2/R_M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/fpga2/R_M0_A12" +Na 166 "/fpga2/R_M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/fpga2/R_M0_A2" +Na 167 "/fpga2/R_M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/fpga2/R_M0_A3" +Na 168 "/fpga2/R_M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/fpga2/R_M0_A4" +Na 169 "/fpga2/R_M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/fpga2/R_M0_A5" +Na 170 "/fpga2/R_M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/fpga2/R_M0_A6" +Na 171 "/fpga2/R_M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/fpga2/R_M0_A7" +Na 172 "/fpga2/R_M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/fpga2/R_M0_A8" +Na 173 "/fpga2/R_M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/fpga2/R_M0_A9" +Na 174 "/fpga2/R_M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/fpga2/R_M0_BA0" +Na 175 "/fpga2/R_M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/fpga2/R_M0_BA1" +Na 176 "/fpga2/R_M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/fpga2/R_M0_CAS#" +Na 177 "/fpga2/R_M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/fpga2/R_M0_CKE" +Na 178 "/fpga2/R_M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/fpga2/R_M0_DQ0" +Na 179 "/fpga2/R_M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 180 "/fpga2/R_M0_DQ1" +Na 180 "/fpga2/R_M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/fpga2/R_M0_DQ10" +Na 181 "/fpga2/R_M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/fpga2/R_M0_DQ11" +Na 182 "/fpga2/R_M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/fpga2/R_M0_DQ12" +Na 183 "/fpga2/R_M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/fpga2/R_M0_DQ13" +Na 184 "/fpga2/R_M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "/fpga2/R_M0_DQ14" +Na 185 "/fpga2/R_M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "/fpga2/R_M0_DQ15" +Na 186 "/fpga2/R_M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "/fpga2/R_M0_DQ2" +Na 187 "/fpga2/R_M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "/fpga2/R_M0_DQ3" +Na 188 "/fpga2/R_M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "/fpga2/R_M0_DQ4" +Na 189 "/fpga2/R_M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "/fpga2/R_M0_DQ5" +Na 190 "/fpga2/R_M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "/fpga2/R_M0_DQ6" +Na 191 "/fpga2/R_M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "/fpga2/R_M0_DQ7" +Na 192 "/fpga2/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "/fpga2/R_M0_DQ8" +Na 193 "/fpga2/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "/fpga2/R_M0_DQ9" +Na 194 "/fpga2/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "/fpga2/R_M0_LDM" +Na 195 "/fpga2/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "/fpga2/R_M0_LDQS" +Na 196 "/fpga2/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "/fpga2/R_M0_RAS#" +Na 197 "/fpga2/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "/fpga2/R_M0_UDM" +Na 198 "/fpga2/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "/fpga2/R_M0_UDQS" +Na 199 "/fpga2/R_M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "/fpga2/R_M0_WE#" +Na 200 "/fpga2/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 201 "/fpga2/R_M1_A0" +Na 201 "/fpga2/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 202 "/fpga2/R_M1_A1" +Na 202 "/fpga2/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 203 "/fpga2/R_M1_A10" +Na 203 "/fpga2/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 204 "/fpga2/R_M1_A11" +Na 204 "/fpga2/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 205 "/fpga2/R_M1_A12" +Na 205 "/fpga2/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 206 "/fpga2/R_M1_A2" +Na 206 "/fpga2/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 207 "/fpga2/R_M1_A3" +Na 207 "/fpga2/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 208 "/fpga2/R_M1_A4" +Na 208 "/fpga2/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 209 "/fpga2/R_M1_A5" +Na 209 "/fpga2/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 210 "/fpga2/R_M1_A6" +Na 210 "/fpga2/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 211 "/fpga2/R_M1_A7" +Na 211 "/fpga2/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 212 "/fpga2/R_M1_A8" +Na 212 "/fpga2/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 213 "/fpga2/R_M1_A9" +Na 213 "/fpga2/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 214 "/fpga2/R_M1_BA0" +Na 214 "/fpga2/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 215 "/fpga2/R_M1_BA1" +Na 215 "/fpga2/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 216 "/fpga2/R_M1_CAS#" +Na 216 "/fpga2/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 217 "/fpga2/R_M1_CKE" +Na 217 "/fpga2/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 218 "/fpga2/R_M1_CS#" +Na 218 "/fpga2/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 219 "/fpga2/R_M1_DQ0" +Na 219 "/fpga2/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 220 "/fpga2/R_M1_DQ1" +Na 220 "/fpga2/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 221 "/fpga2/R_M1_DQ10" +Na 221 "/fpga2/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 222 "/fpga2/R_M1_DQ11" +Na 222 "/fpga2/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 223 "/fpga2/R_M1_DQ12" +Na 223 "/fpga2/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 224 "/fpga2/R_M1_DQ13" +Na 224 "/fpga2/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 225 "/fpga2/R_M1_DQ14" +Na 225 "/fpga2/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 226 "/fpga2/R_M1_DQ15" +Na 226 "/fpga2/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 227 "/fpga2/R_M1_DQ2" +Na 227 "/fpga2/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 228 "/fpga2/R_M1_DQ3" +Na 228 "/fpga2/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 229 "/fpga2/R_M1_DQ4" +Na 229 "/fpga2/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 230 "/fpga2/R_M1_DQ5" +Na 230 "/fpga2/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 231 "/fpga2/R_M1_DQ6" +Na 231 "/fpga2/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 232 "/fpga2/R_M1_DQ7" +Na 232 "/fpga2/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 233 "/fpga2/R_M1_DQ8" +Na 233 "/fpga2/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 234 "/fpga2/R_M1_DQ9" +Na 234 "/fpga2/USBD_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 235 "/fpga2/R_M1_LDM" +Na 235 "/fpga2/USBD_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 236 "/fpga2/R_M1_LDQS" +Na 236 "/fpga2/USBD_VP" St ~ $EndEQUIPOT $EQUIPOT -Na 237 "/fpga2/R_M1_RAS#" +Na 237 "/sdram/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 238 "/fpga2/R_M1_UDM" +Na 238 "/sdram/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 239 "/fpga2/R_M1_UDQS" +Na 239 "/sdram/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 240 "/fpga2/R_M1_WE#" +Na 240 "/sdram/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 241 "/fpga2/USBA_RCV" +Na 241 "/sdram/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 242 "/fpga2/USBA_VP" +Na 242 "/sdram/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 243 "/fpga2/USBD_RCV" +Na 243 "/sdram/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 244 "/fpga2/USBD_VM" +Na 244 "/sdram/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 245 "/fpga2/USBD_VP" +Na 245 "/sdram/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 246 "/sdram/M0_A1" +Na 246 "/sdram/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 247 "/sdram/M0_A11" +Na 247 "/sdram/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 248 "/sdram/M0_A3" +Na 248 "/sdram/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 249 "/sdram/M0_A6" +Na 249 "/sdram/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 250 "/sdram/M0_BA1" +Na 250 "/sdram/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 251 "/sdram/M0_CKE" +Na 251 "/sdram/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 252 "/sdram/M0_CLK#" +Na 252 "/sdram/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 253 "/sdram/M0_DQ12" +Na 253 "/sdram/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 254 "/sdram/M0_DQ13" +Na 254 "/sdram/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 255 "/sdram/M0_DQ14" +Na 255 "/sdram/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 256 "/sdram/M0_DQ4" +Na 256 "/sdram/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 257 "/sdram/M0_DQ5" +Na 257 "/sdram/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 258 "/sdram/M0_DQ8" +Na 258 "/sdram/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 259 "/sdram/M0_RAS#" +Na 259 "/sdram/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT @@ -1127,15 +1127,15 @@ Na 262 "/sdram/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 263 "/sdram/M1_A1" +Na 263 "/sdram/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 264 "/sdram/M1_A10" +Na 264 "/sdram/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 265 "/sdram/M1_A12" +Na 265 "/sdram/M1_A2" St ~ $EndEQUIPOT $EQUIPOT @@ -1147,35 +1147,35 @@ Na 267 "/sdram/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 268 "/sdram/M1_A5" +Na 268 "/sdram/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 269 "/sdram/M1_BA0" +Na 269 "/sdram/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 270 "/sdram/M1_CAS#" +Na 270 "/sdram/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 271 "/sdram/M1_DQ1" +Na 271 "/sdram/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 272 "/sdram/M1_DQ12" +Na 272 "/sdram/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 273 "/sdram/M1_DQ13" +Na 273 "/sdram/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 274 "/sdram/M1_DQ5" +Na 274 "/sdram/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 275 "/sdram/M1_DQ6" +Na 275 "/sdram/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT @@ -1183,11 +1183,11 @@ Na 276 "/sdram/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 277 "/sdram/M1_RAS#" +Na 277 "/sdram/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 278 "/sdram/M1_UDM" +Na 278 "/sdram/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT @@ -1227,11 +1227,11 @@ Na 287 "/usb/USBD_D-" St ~ $EndEQUIPOT $EQUIPOT -Na 288 "/usb/USBD_OE_N" +Na 288 "/usb/USBD_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 289 "/usb/USBD_SPD" +Na 289 "/usb/USBD_VM" St ~ $EndEQUIPOT $EQUIPOT @@ -1247,15 +1247,15 @@ Na 292 "GND" St ~ $EndEQUIPOT $EQUIPOT -Na 293 "N-000120" +Na 293 "N-000121" St ~ $EndEQUIPOT $EQUIPOT -Na 294 "N-000121" +Na 294 "N-000124" St ~ $EndEQUIPOT $EQUIPOT -Na 295 "N-000125" +Na 295 "N-000126" St ~ $EndEQUIPOT $EQUIPOT @@ -1315,11 +1315,11 @@ Na 309 "N-000163" St ~ $EndEQUIPOT $EQUIPOT -Na 310 "N-000165" +Na 310 "N-000164" St ~ $EndEQUIPOT $EQUIPOT -Na 311 "N-000166" +Na 311 "N-000165" St ~ $EndEQUIPOT $EQUIPOT @@ -1383,7 +1383,7 @@ Na 326 "N-000181" St ~ $EndEQUIPOT $EQUIPOT -Na 327 "N-000184" +Na 327 "N-000182" St ~ $EndEQUIPOT $EQUIPOT @@ -1395,33 +1395,37 @@ Na 329 "N-000186" St ~ $EndEQUIPOT $EQUIPOT -Na 330 "N-000190" +Na 330 "N-000187" St ~ $EndEQUIPOT $EQUIPOT -Na 331 "N-000201" +Na 331 "N-000191" St ~ $EndEQUIPOT $EQUIPOT -Na 332 "N-000202" +Na 332 "N-000197" St ~ $EndEQUIPOT $EQUIPOT -Na 333 "N-000203" +Na 333 "N-000198" St ~ $EndEQUIPOT $EQUIPOT -Na 334 "N-000362" +Na 334 "N-000363" St ~ $EndEQUIPOT $EQUIPOT -Na 335 "N-000365" +Na 335 "N-000366" St ~ $EndEQUIPOT $EQUIPOT Na 336 "VCCO2" St ~ $EndEQUIPOT +$EQUIPOT +Na 337 "Vin" +St ~ +$EndEQUIPOT $NCLASS Name "Default" Desc "This is the default net class." @@ -1435,160 +1439,151 @@ AddNet "" AddNet "+1.8V" AddNet "/ether/ETH_A1.8V" AddNet "/ether/ETH_A3.3V" -AddNet "/ether/ETH_CLK" AddNet "/ether/ETH_COL" -AddNet "/ether/ETH_CRS" AddNet "/ether/ETH_INT" AddNet "/ether/ETH_LED0" AddNet "/ether/ETH_LED1" -AddNet "/ether/ETH_MDC" AddNet "/ether/ETH_MDIO" AddNet "/ether/ETH_PLL1.8V" -AddNet "/ether/ETH_RXC" AddNet "/ether/ETH_RXDV" -AddNet "/ether/ETH_TXD0" -AddNet "/ether/ETH_TXD3" +AddNet "/ether/ETH_RXER" +AddNet "/ether/ETH_TXD2" AddNet "/ether/ETH_TXER" AddNet "/ether/MAG_RX+" AddNet "/ether/MAG_RX-" AddNet "/ether/MAG_SHIELD" AddNet "/ether/MAG_TX+" AddNet "/ether/MAG_TX-" -AddNet "/expansion/FPGA_BANK0_IO_1" -AddNet "/expansion/FPGA_BANK0_IO_10" AddNet "/expansion/FPGA_BANK0_IO_11" +AddNet "/expansion/FPGA_BANK0_IO_12" +AddNet "/expansion/FPGA_BANK0_IO_14" AddNet "/expansion/FPGA_BANK0_IO_15" -AddNet "/expansion/FPGA_BANK0_IO_17" -AddNet "/expansion/FPGA_BANK0_IO_2" -AddNet "/expansion/FPGA_BANK0_IO_20" -AddNet "/expansion/FPGA_BANK0_IO_21" -AddNet "/expansion/FPGA_BANK0_IO_29" +AddNet "/expansion/FPGA_BANK0_IO_22" +AddNet "/expansion/FPGA_BANK0_IO_24" +AddNet "/expansion/FPGA_BANK0_IO_28" AddNet "/expansion/FPGA_BANK0_IO_3" -AddNet "/expansion/FPGA_BANK0_IO_32" +AddNet "/expansion/FPGA_BANK0_IO_33" AddNet "/expansion/FPGA_BANK0_IO_34" +AddNet "/expansion/FPGA_BANK0_IO_36" AddNet "/expansion/FPGA_BANK0_IO_38" AddNet "/expansion/FPGA_BANK0_IO_39" AddNet "/expansion/FPGA_BANK0_IO_40" AddNet "/expansion/FPGA_BANK0_IO_43" +AddNet "/expansion/FPGA_BANK0_IO_44" +AddNet "/expansion/FPGA_BANK0_IO_45" AddNet "/expansion/FPGA_BANK0_IO_46" AddNet "/expansion/FPGA_BANK0_IO_47" +AddNet "/expansion/FPGA_BANK0_IO_48" AddNet "/expansion/FPGA_BANK0_IO_5" -AddNet "/expansion/FPGA_BANK0_IO_50" -AddNet "/expansion/FPGA_BANK0_IO_54" -AddNet "/expansion/FPGA_BANK0_IO_6" +AddNet "/expansion/FPGA_BANK0_IO_51" +AddNet "/expansion/FPGA_BANK0_IO_62" AddNet "/expansion/FPGA_BANK0_IO_7" AddNet "/expansion/FPGA_BANK0_IO_9" -AddNet "/flash/NF_ALE" -AddNet "/flash/NF_CLE" -AddNet "/flash/NF_CS1_N" -AddNet "/flash/NF_D0" -AddNet "/flash/NF_D1" -AddNet "/flash/NF_D3" -AddNet "/flash/NF_D5" -AddNet "/flash/NF_D7" -AddNet "/flash/NF_RE_N" -AddNet "/flash/SD_DAT2" +AddNet "/flash/NF_D2" +AddNet "/flash/NF_RNB" +AddNet "/flash/NF_WE_N" +AddNet "/flash/SD_CLK" +AddNet "/flash/SD_DAT1" +AddNet "/flash/SD_DAT3" +AddNet "/fpga1/ETH_CLK" +AddNet "/fpga1/ETH_CRS" +AddNet "/fpga1/ETH_MDC" AddNet "/fpga1/ETH_RESET_N" +AddNet "/fpga1/ETH_RXC" AddNet "/fpga1/ETH_RXD0" AddNet "/fpga1/ETH_RXD1" AddNet "/fpga1/ETH_RXD2" AddNet "/fpga1/ETH_RXD3" -AddNet "/fpga1/ETH_RXER" AddNet "/fpga1/ETH_TXC" +AddNet "/fpga1/ETH_TXD0" AddNet "/fpga1/ETH_TXD1" -AddNet "/fpga1/ETH_TXD2" +AddNet "/fpga1/ETH_TXD3" AddNet "/fpga1/ETH_TXEN" -AddNet "/fpga1/FPGA_BANK0_IO_12" -AddNet "/fpga1/FPGA_BANK0_IO_14" +AddNet "/fpga1/FPGA_BANK0_IO_1" +AddNet "/fpga1/FPGA_BANK0_IO_10" +AddNet "/fpga1/FPGA_BANK0_IO_17" AddNet "/fpga1/FPGA_BANK0_IO_18" -AddNet "/fpga1/FPGA_BANK0_IO_22" -AddNet "/fpga1/FPGA_BANK0_IO_24" +AddNet "/fpga1/FPGA_BANK0_IO_2" +AddNet "/fpga1/FPGA_BANK0_IO_20" +AddNet "/fpga1/FPGA_BANK0_IO_21" AddNet "/fpga1/FPGA_BANK0_IO_25" AddNet "/fpga1/FPGA_BANK0_IO_27" -AddNet "/fpga1/FPGA_BANK0_IO_28" +AddNet "/fpga1/FPGA_BANK0_IO_29" AddNet "/fpga1/FPGA_BANK0_IO_30" -AddNet "/fpga1/FPGA_BANK0_IO_33" -AddNet "/fpga1/FPGA_BANK0_IO_36" -AddNet "/fpga1/FPGA_BANK0_IO_44" -AddNet "/fpga1/FPGA_BANK0_IO_45" -AddNet "/fpga1/FPGA_BANK0_IO_48" +AddNet "/fpga1/FPGA_BANK0_IO_32" AddNet "/fpga1/FPGA_BANK0_IO_49" -AddNet "/fpga1/FPGA_BANK0_IO_51" +AddNet "/fpga1/FPGA_BANK0_IO_50" AddNet "/fpga1/FPGA_BANK0_IO_52" AddNet "/fpga1/FPGA_BANK0_IO_53" +AddNet "/fpga1/FPGA_BANK0_IO_54" AddNet "/fpga1/FPGA_BANK0_IO_56" AddNet "/fpga1/FPGA_BANK0_IO_57" AddNet "/fpga1/FPGA_BANK0_IO_58" +AddNet "/fpga1/FPGA_BANK0_IO_6" AddNet "/fpga1/FPGA_BANK0_IO_60" -AddNet "/fpga1/FPGA_BANK0_IO_62" AddNet "/fpga1/FPGA_BANK0_IO_63" AddNet "/fpga1/FPGA_BANK0_IO_8" -AddNet "/fpga1/NF_D2" +AddNet "/fpga1/NF_ALE" +AddNet "/fpga1/NF_CLE" +AddNet "/fpga1/NF_CS1_N" +AddNet "/fpga1/NF_D0" +AddNet "/fpga1/NF_D1" +AddNet "/fpga1/NF_D3" AddNet "/fpga1/NF_D4" +AddNet "/fpga1/NF_D5" AddNet "/fpga1/NF_D6" -AddNet "/fpga1/NF_RNB" -AddNet "/fpga1/NF_WE_N" +AddNet "/fpga1/NF_D7" +AddNet "/fpga1/NF_RE_N" AddNet "/fpga1/PROG_CCLK" AddNet "/fpga1/PROG_CSO" AddNet "/fpga1/PROG_MISO0" AddNet "/fpga1/PROG_MISO1" AddNet "/fpga1/PROG_MISO2" AddNet "/fpga1/PROG_MISO3" -AddNet "/fpga1/SD_CLK" AddNet "/fpga1/SD_CMD" AddNet "/fpga1/SD_DAT0" -AddNet "/fpga1/SD_DAT1" -AddNet "/fpga1/SD_DAT3" +AddNet "/fpga1/SD_DAT2" AddNet "/fpga2/M0_A0" AddNet "/fpga2/M0_A10" +AddNet "/fpga2/M0_A11" AddNet "/fpga2/M0_A12" AddNet "/fpga2/M0_A2" -AddNet "/fpga2/M0_A4" AddNet "/fpga2/M0_A5" AddNet "/fpga2/M0_A7" -AddNet "/fpga2/M0_A8" AddNet "/fpga2/M0_A9" -AddNet "/fpga2/M0_BA0" -AddNet "/fpga2/M0_CAS#" -AddNet "/fpga2/M0_CLK" -AddNet "/fpga2/M0_DQ0" AddNet "/fpga2/M0_DQ1" -AddNet "/fpga2/M0_DQ10" AddNet "/fpga2/M0_DQ11" -AddNet "/fpga2/M0_DQ15" AddNet "/fpga2/M0_DQ2" AddNet "/fpga2/M0_DQ3" -AddNet "/fpga2/M0_DQ6" -AddNet "/fpga2/M0_DQ7" +AddNet "/fpga2/M0_DQ5" +AddNet "/fpga2/M0_DQ8" AddNet "/fpga2/M0_DQ9" AddNet "/fpga2/M0_LDM" -AddNet "/fpga2/M0_LDQS" -AddNet "/fpga2/M0_UDM" AddNet "/fpga2/M1_A0" -AddNet "/fpga2/M1_A11" -AddNet "/fpga2/M1_A2" +AddNet "/fpga2/M1_A1" +AddNet "/fpga2/M1_A12" +AddNet "/fpga2/M1_A5" AddNet "/fpga2/M1_A6" -AddNet "/fpga2/M1_A7" AddNet "/fpga2/M1_A8" -AddNet "/fpga2/M1_A9" AddNet "/fpga2/M1_BA1" -AddNet "/fpga2/M1_CKE" +AddNet "/fpga2/M1_CAS#" AddNet "/fpga2/M1_CLK" AddNet "/fpga2/M1_CLK#" AddNet "/fpga2/M1_CS#" AddNet "/fpga2/M1_DQ0" -AddNet "/fpga2/M1_DQ10" -AddNet "/fpga2/M1_DQ11" +AddNet "/fpga2/M1_DQ12" +AddNet "/fpga2/M1_DQ13" AddNet "/fpga2/M1_DQ14" AddNet "/fpga2/M1_DQ15" -AddNet "/fpga2/M1_DQ2" AddNet "/fpga2/M1_DQ3" AddNet "/fpga2/M1_DQ4" +AddNet "/fpga2/M1_DQ5" +AddNet "/fpga2/M1_DQ6" AddNet "/fpga2/M1_DQ7" AddNet "/fpga2/M1_DQ8" AddNet "/fpga2/M1_DQ9" AddNet "/fpga2/M1_LDM" -AddNet "/fpga2/M1_UDQS" +AddNet "/fpga2/M1_RAS#" AddNet "/fpga2/R_M0_A0" AddNet "/fpga2/R_M0_A1" AddNet "/fpga2/R_M0_A10" @@ -1670,42 +1665,51 @@ AddNet "/fpga2/R_M1_UDQS" AddNet "/fpga2/R_M1_WE#" AddNet "/fpga2/USBA_RCV" AddNet "/fpga2/USBA_VP" +AddNet "/fpga2/USBD_OE_N" AddNet "/fpga2/USBD_RCV" -AddNet "/fpga2/USBD_VM" AddNet "/fpga2/USBD_VP" AddNet "/sdram/M0_A1" -AddNet "/sdram/M0_A11" AddNet "/sdram/M0_A3" +AddNet "/sdram/M0_A4" AddNet "/sdram/M0_A6" +AddNet "/sdram/M0_A8" +AddNet "/sdram/M0_BA0" AddNet "/sdram/M0_BA1" +AddNet "/sdram/M0_CAS#" AddNet "/sdram/M0_CKE" +AddNet "/sdram/M0_CLK" AddNet "/sdram/M0_CLK#" +AddNet "/sdram/M0_DQ0" +AddNet "/sdram/M0_DQ10" AddNet "/sdram/M0_DQ12" AddNet "/sdram/M0_DQ13" AddNet "/sdram/M0_DQ14" +AddNet "/sdram/M0_DQ15" AddNet "/sdram/M0_DQ4" -AddNet "/sdram/M0_DQ5" -AddNet "/sdram/M0_DQ8" +AddNet "/sdram/M0_DQ6" +AddNet "/sdram/M0_DQ7" +AddNet "/sdram/M0_LDQS" AddNet "/sdram/M0_RAS#" +AddNet "/sdram/M0_UDM" AddNet "/sdram/M0_UDQS" AddNet "/sdram/M0_VREF" AddNet "/sdram/M0_WE#" -AddNet "/sdram/M1_A1" AddNet "/sdram/M1_A10" -AddNet "/sdram/M1_A12" +AddNet "/sdram/M1_A11" +AddNet "/sdram/M1_A2" AddNet "/sdram/M1_A3" AddNet "/sdram/M1_A4" -AddNet "/sdram/M1_A5" +AddNet "/sdram/M1_A7" +AddNet "/sdram/M1_A9" AddNet "/sdram/M1_BA0" -AddNet "/sdram/M1_CAS#" +AddNet "/sdram/M1_CKE" AddNet "/sdram/M1_DQ1" -AddNet "/sdram/M1_DQ12" -AddNet "/sdram/M1_DQ13" -AddNet "/sdram/M1_DQ5" -AddNet "/sdram/M1_DQ6" +AddNet "/sdram/M1_DQ10" +AddNet "/sdram/M1_DQ11" +AddNet "/sdram/M1_DQ2" AddNet "/sdram/M1_LDQS" -AddNet "/sdram/M1_RAS#" AddNet "/sdram/M1_UDM" +AddNet "/sdram/M1_UDQS" AddNet "/sdram/M1_VREF" AddNet "/sdram/M1_WE#" AddNet "/usb/USBA_D+" @@ -1715,13 +1719,13 @@ AddNet "/usb/USBA_SPD" AddNet "/usb/USBA_VM" AddNet "/usb/USBD_D+" AddNet "/usb/USBD_D-" -AddNet "/usb/USBD_OE_N" AddNet "/usb/USBD_SPD" +AddNet "/usb/USBD_VM" AddNet "/usb/USB_CASE_DEV" AddNet "/usb/USB_CASE_HOST" -AddNet "N-000120" AddNet "N-000121" -AddNet "N-000125" +AddNet "N-000124" +AddNet "N-000126" AddNet "N-000141" AddNet "N-000142" AddNet "N-000143" @@ -1736,8 +1740,8 @@ AddNet "N-000160" AddNet "N-000161" AddNet "N-000162" AddNet "N-000163" +AddNet "N-000164" AddNet "N-000165" -AddNet "N-000166" AddNet "N-000167" AddNet "N-000168" AddNet "N-000169" @@ -1753,16 +1757,17 @@ AddNet "N-000178" AddNet "N-000179" AddNet "N-000180" AddNet "N-000181" -AddNet "N-000184" +AddNet "N-000182" AddNet "N-000185" AddNet "N-000186" -AddNet "N-000190" -AddNet "N-000201" -AddNet "N-000202" -AddNet "N-000203" -AddNet "N-000362" -AddNet "N-000365" +AddNet "N-000187" +AddNet "N-000191" +AddNet "N-000197" +AddNet "N-000198" +AddNet "N-000363" +AddNet "N-000366" AddNet "VCCO2" +AddNet "Vin" $EndNCLASS $NCLASS Name "ADDRESS/DDR" @@ -1878,14 +1883,14 @@ $PAD Sh "2" R 197 355 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 312 "N-000167" +Ne 314 "N-000169" Po -249 1003 $EndPAD $PAD Sh "7" R 197 355 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 312 "N-000167" +Ne 314 "N-000169" Po -249 -1003 $EndPAD $PAD @@ -1899,7 +1904,7 @@ $PAD Sh "6" R 197 355 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 311 "N-000166" +Ne 313 "N-000168" Po 249 -1003 $EndPAD $PAD @@ -1934,7 +1939,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 326 "N-000181" +Ne 327 "N-000182" Po -176 0 $EndPAD $PAD @@ -1997,7 +2002,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 310 "N-000165" +Ne 312 "N-000167" Po 176 0 $EndPAD $EndMODULE 0402 @@ -2018,7 +2023,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 326 "N-000181" +Ne 327 "N-000182" Po -176 0 $EndPAD $PAD @@ -2046,14 +2051,14 @@ $PAD Sh "1" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 326 "N-000181" +Ne 327 "N-000182" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 311 "N-000166" +Ne 313 "N-000168" Po 570 0 $EndPAD $EndMODULE 1210 @@ -2074,7 +2079,7 @@ $PAD Sh "1" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 326 "N-000181" +Ne 327 "N-000182" Po -570 0 $EndPAD $PAD @@ -2127,105 +2132,105 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/ether/ETH_CLK" +Ne 54 "/fpga1/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/fpga1/ETH_RXD1" +Ne 60 "/fpga1/ETH_RXD1" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/ether/ETH_RXDV" +Ne 14 "/ether/ETH_RXDV" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/ether/ETH_RXC" +Ne 58 "/fpga1/ETH_RXC" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/ether/ETH_TXD3" +Ne 66 "/fpga1/ETH_TXD3" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/ether/ETH_COL" +Ne 8 "/ether/ETH_COL" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/ether/ETH_INT" +Ne 9 "/ether/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/fpga1/NF_D6" +Ne 100 "/fpga1/NF_D6" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/fpga1/NF_D4" +Ne 98 "/fpga1/NF_D4" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/fpga1/NF_D2" +Ne 48 "/flash/NF_D2" Po 590 -4133 $EndPAD $PAD Sh "A14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/flash/NF_ALE" +Ne 92 "/fpga1/NF_ALE" Po 983 -4133 $EndPAD $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/fpga1/NF_RNB" +Ne 49 "/flash/NF_RNB" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/flash/SD_DAT2" +Ne 111 "/fpga1/SD_DAT2" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/fpga1/SD_CLK" +Ne 51 "/flash/SD_CLK" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/fpga1/SD_DAT0" +Ne 110 "/fpga1/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -2239,14 +2244,14 @@ $PAD Sh "A20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 243 "/fpga2/USBD_RCV" +Ne 235 "/fpga2/USBD_RCV" Po 3346 -4133 $EndPAD $PAD Sh "A21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 288 "/usb/USBD_OE_N" +Ne 234 "/fpga2/USBD_OE_N" Po 3739 -4133 $EndPAD $PAD @@ -2295,7 +2300,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/fpga1/ETH_RXD0" +Ne 59 "/fpga1/ETH_RXD0" Po -2165 -3739 $EndPAD $PAD @@ -2309,7 +2314,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/fpga1/ETH_RXER" +Ne 15 "/ether/ETH_RXER" Po -1377 -3739 $EndPAD $PAD @@ -2323,7 +2328,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/ether/ETH_CRS" +Ne 55 "/fpga1/ETH_CRS" Po -590 -3739 $EndPAD $PAD @@ -2337,7 +2342,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/flash/NF_D3" +Ne 97 "/fpga1/NF_D3" Po 196 -3739 $EndPAD $PAD @@ -2351,7 +2356,7 @@ $PAD Sh "B14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/flash/NF_CLE" +Ne 93 "/fpga1/NF_CLE" Po 983 -3739 $EndPAD $PAD @@ -2365,7 +2370,7 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/fpga1/SD_DAT3" +Ne 53 "/flash/SD_DAT3" Po 1771 -3739 $EndPAD $PAD @@ -2379,7 +2384,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/fpga1/SD_DAT1" +Ne 52 "/flash/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -2393,28 +2398,28 @@ $PAD Sh "B20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 289 "/usb/USBD_SPD" +Ne 288 "/usb/USBD_SPD" Po 3346 -3739 $EndPAD $PAD Sh "B21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "/fpga2/USBD_VP" +Ne 236 "/fpga2/USBD_VP" Po 3739 -3739 $EndPAD $PAD Sh "B22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 244 "/fpga2/USBD_VM" +Ne 289 "/usb/USBD_VM" Po 4133 -3739 $EndPAD $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/fpga2/R_M0_A11" +Ne 156 "/fpga2/R_M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -2442,56 +2447,56 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/fpga1/ETH_RXD3" +Ne 62 "/fpga1/ETH_RXD3" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/fpga1/ETH_RXD2" +Ne 61 "/fpga1/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/fpga1/ETH_RESET_N" +Ne 57 "/fpga1/ETH_RESET_N" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/fpga1/ETH_TXC" +Ne 63 "/fpga1/ETH_TXC" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/fpga1/ETH_TXD1" +Ne 65 "/fpga1/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/fpga1/ETH_TXD2" +Ne 16 "/ether/ETH_TXD2" Po -590 -3346 $EndPAD $PAD Sh "C11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/flash/NF_D5" +Ne 99 "/fpga1/NF_D5" Po -196 -3346 $EndPAD $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/flash/NF_D0" +Ne 95 "/fpga1/NF_D0" Po 196 -3346 $EndPAD $PAD @@ -2505,21 +2510,21 @@ $PAD Sh "C14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/fpga1/NF_WE_N" +Ne 50 "/flash/NF_WE_N" Po 983 -3346 $EndPAD $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/flash/NF_RE_N" +Ne 102 "/fpga1/NF_RE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/fpga1/SD_CMD" +Ne 109 "/fpga1/SD_CMD" Po 1771 -3346 $EndPAD $PAD @@ -2547,7 +2552,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 212 "/fpga2/R_M1_A8" +Ne 203 "/fpga2/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -2561,21 +2566,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 213 "/fpga2/R_M1_A9" +Ne 204 "/fpga2/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/fpga2/R_M0_A12" +Ne 157 "/fpga2/R_M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/fpga2/R_M0_CKE" +Ne 169 "/fpga2/R_M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -2603,42 +2608,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/ether/ETH_MDIO" +Ne 12 "/ether/ETH_MDIO" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/ether/ETH_MDC" +Ne 56 "/fpga1/ETH_MDC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/ether/ETH_TXER" +Ne 17 "/ether/ETH_TXER" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/fpga1/ETH_TXEN" +Ne 67 "/fpga1/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/ether/ETH_TXD0" +Ne 64 "/fpga1/ETH_TXD0" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/flash/NF_D7" +Ne 101 "/fpga1/NF_D7" Po -196 -2952 $EndPAD $PAD @@ -2659,14 +2664,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/flash/NF_D1" +Ne 96 "/fpga1/NF_D1" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/flash/NF_CS1_N" +Ne 94 "/fpga1/NF_CS1_N" Po 1377 -2952 $EndPAD $PAD @@ -2694,7 +2699,7 @@ $PAD Sh "D19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 242 "/fpga2/USBA_VP" +Ne 233 "/fpga2/USBA_VP" Po 2952 -2952 $EndPAD $PAD @@ -2708,21 +2713,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/fpga2/R_M1_CKE" +Ne 208 "/fpga2/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 205 "/fpga2/R_M1_A12" +Ne 196 "/fpga2/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/fpga2/R_M0_A9" +Ne 165 "/fpga2/R_M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -2736,7 +2741,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/fpga2/R_M0_A8" +Ne 164 "/fpga2/R_M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -2855,7 +2860,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 211 "/fpga2/R_M1_A7" +Ne 202 "/fpga2/R_M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -2869,7 +2874,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "/fpga2/R_M1_A2" +Ne 197 "/fpga2/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -2883,14 +2888,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 200 "/fpga2/R_M0_WE#" +Ne 191 "/fpga2/R_M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/fpga2/R_M0_A4" +Ne 160 "/fpga2/R_M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -2988,7 +2993,7 @@ $PAD Sh "F17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 241 "/fpga2/USBA_RCV" +Ne 232 "/fpga2/USBA_RCV" Po 2165 -2165 $EndPAD $PAD @@ -3002,35 +3007,35 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 204 "/fpga2/R_M1_A11" +Ne 195 "/fpga2/R_M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 208 "/fpga2/R_M1_A4" +Ne 199 "/fpga2/R_M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "/fpga2/R_M1_A0" +Ne 192 "/fpga2/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 202 "/fpga2/R_M1_A1" +Ne 193 "/fpga2/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/fpga2/R_M0_BA1" +Ne 167 "/fpga2/R_M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -3044,14 +3049,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/fpga2/R_M0_BA0" +Ne 166 "/fpga2/R_M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/fpga2/R_M0_A10" +Ne 155 "/fpga2/R_M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -3156,14 +3161,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 203 "/fpga2/R_M1_A10" +Ne 194 "/fpga2/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 207 "/fpga2/R_M1_A3" +Ne 198 "/fpga2/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -3184,42 +3189,42 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/fpga2/R_M0_A1" +Ne 154 "/fpga2/R_M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/fpga2/R_M0_A0" +Ne 153 "/fpga2/R_M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 252 "/sdram/M0_CLK#" +Ne 247 "/sdram/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/fpga2/M0_CLK" +Ne 246 "/sdram/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/fpga2/R_M0_A2" +Ne 158 "/fpga2/R_M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/fpga2/R_M0_A7" +Ne 163 "/fpga2/R_M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -3289,7 +3294,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 218 "/fpga2/R_M1_CS#" +Ne 209 "/fpga2/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -3310,35 +3315,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 240 "/fpga2/R_M1_WE#" +Ne 231 "/fpga2/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/fpga2/M1_CLK" +Ne 136 "/fpga2/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 237 "/fpga2/R_M1_RAS#" +Ne 228 "/fpga2/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 216 "/fpga2/R_M1_CAS#" +Ne 207 "/fpga2/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/fpga2/R_M0_DQ5" +Ne 181 "/fpga2/R_M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -3352,14 +3357,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/fpga2/R_M0_DQ4" +Ne 180 "/fpga2/R_M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/fpga2/R_M0_A6" +Ne 162 "/fpga2/R_M0_A6" Po -2952 -983 $EndPAD $PAD @@ -3450,7 +3455,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 214 "/fpga2/R_M1_BA0" +Ne 205 "/fpga2/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -3464,14 +3469,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/fpga2/M1_CLK#" +Ne 137 "/fpga2/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 229 "/fpga2/R_M1_DQ4" +Ne 220 "/fpga2/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD @@ -3485,49 +3490,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 230 "/fpga2/R_M1_DQ5" +Ne 221 "/fpga2/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 192 "/fpga2/R_M0_DQ7" +Ne 183 "/fpga2/R_M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/fpga2/R_M0_DQ6" +Ne 182 "/fpga2/R_M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/fpga2/R_M0_A5" +Ne 161 "/fpga2/R_M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/fpga2/R_M0_CAS#" +Ne 168 "/fpga2/R_M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 197 "/fpga2/R_M0_RAS#" +Ne 188 "/fpga2/R_M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/fpga2/R_M0_A3" +Ne 159 "/fpga2/R_M0_A3" Po -2165 -590 $EndPAD $PAD @@ -3604,7 +3609,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 215 "/fpga2/R_M1_BA1" +Ne 206 "/fpga2/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -3618,28 +3623,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 210 "/fpga2/R_M1_A6" +Ne 201 "/fpga2/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 209 "/fpga2/R_M1_A5" +Ne 200 "/fpga2/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 231 "/fpga2/R_M1_DQ6" +Ne 222 "/fpga2/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 232 "/fpga2/R_M1_DQ7" +Ne 223 "/fpga2/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -3660,14 +3665,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 196 "/fpga2/R_M0_LDQS" +Ne 187 "/fpga2/R_M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 195 "/fpga2/R_M0_LDM" +Ne 186 "/fpga2/R_M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -3772,14 +3777,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 235 "/fpga2/R_M1_LDM" +Ne 226 "/fpga2/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 236 "/fpga2/R_M1_LDQS" +Ne 227 "/fpga2/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -3800,21 +3805,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/fpga2/R_M0_DQ3" +Ne 179 "/fpga2/R_M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/fpga2/R_M0_DQ2" +Ne 178 "/fpga2/R_M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 198 "/fpga2/R_M0_UDM" +Ne 189 "/fpga2/R_M0_UDM" Po -3346 196 $EndPAD $PAD @@ -3933,28 +3938,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 238 "/fpga2/R_M1_UDM" +Ne 229 "/fpga2/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 227 "/fpga2/R_M1_DQ2" +Ne 218 "/fpga2/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 228 "/fpga2/R_M1_DQ3" +Ne 219 "/fpga2/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 180 "/fpga2/R_M0_DQ1" +Ne 171 "/fpga2/R_M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -3968,7 +3973,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/fpga2/R_M0_DQ0" +Ne 170 "/fpga2/R_M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -4087,7 +4092,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 219 "/fpga2/R_M1_DQ0" +Ne 210 "/fpga2/R_M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -4101,21 +4106,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 220 "/fpga2/R_M1_DQ1" +Ne 211 "/fpga2/R_M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 194 "/fpga2/R_M0_DQ9" +Ne 185 "/fpga2/R_M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 193 "/fpga2/R_M0_DQ8" +Ne 184 "/fpga2/R_M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -4248,21 +4253,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 233 "/fpga2/R_M1_DQ8" +Ne 224 "/fpga2/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 234 "/fpga2/R_M1_DQ9" +Ne 225 "/fpga2/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/fpga2/R_M0_DQ11" +Ne 173 "/fpga2/R_M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -4276,7 +4281,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/fpga2/R_M0_DQ10" +Ne 172 "/fpga2/R_M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -4318,7 +4323,7 @@ $PAD Sh "R9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/fpga1/FPGA_BANK0_IO_58" +Ne 87 "/fpga1/FPGA_BANK0_IO_58" Po -983 1377 $EndPAD $PAD @@ -4367,7 +4372,7 @@ $PAD Sh "R16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/fpga1/FPGA_BANK0_IO_12" +Ne 24 "/expansion/FPGA_BANK0_IO_12" Po 1771 1377 $EndPAD $PAD @@ -4395,7 +4400,7 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/fpga2/R_M1_DQ10" +Ne 212 "/fpga2/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -4409,7 +4414,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "/fpga2/R_M1_DQ11" +Ne 213 "/fpga2/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -4423,7 +4428,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 199 "/fpga2/R_M0_UDQS" +Ne 190 "/fpga2/R_M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -4444,7 +4449,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/fpga1/PROG_CSO" +Ne 104 "/fpga1/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -4458,14 +4463,14 @@ $PAD Sh "T7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/fpga1/FPGA_BANK0_IO_60" +Ne 89 "/fpga1/FPGA_BANK0_IO_60" Po -1771 1771 $EndPAD $PAD Sh "T8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/fpga1/FPGA_BANK0_IO_53" +Ne 83 "/fpga1/FPGA_BANK0_IO_53" Po -1377 1771 $EndPAD $PAD @@ -4493,7 +4498,7 @@ $PAD Sh "T12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/expansion/FPGA_BANK0_IO_34" +Ne 32 "/expansion/FPGA_BANK0_IO_34" Po 196 1771 $EndPAD $PAD @@ -4507,35 +4512,35 @@ $PAD Sh "T14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/fpga1/FPGA_BANK0_IO_36" +Ne 33 "/expansion/FPGA_BANK0_IO_36" Po 983 1771 $EndPAD $PAD Sh "T15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/expansion/FPGA_BANK0_IO_7" +Ne 46 "/expansion/FPGA_BANK0_IO_7" Po 1377 1771 $EndPAD $PAD Sh "T16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/expansion/FPGA_BANK0_IO_6" +Ne 88 "/fpga1/FPGA_BANK0_IO_6" Po 1771 1771 $EndPAD $PAD Sh "T17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/expansion/FPGA_BANK0_IO_2" +Ne 72 "/fpga1/FPGA_BANK0_IO_2" Po 2165 1771 $EndPAD $PAD Sh "T18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/expansion/FPGA_BANK0_IO_1" +Ne 68 "/fpga1/FPGA_BANK0_IO_1" Po 2558 1771 $EndPAD $PAD @@ -4556,7 +4561,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 239 "/fpga2/R_M1_UDQS" +Ne 230 "/fpga2/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -4570,7 +4575,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/fpga2/R_M0_DQ13" +Ne 175 "/fpga2/R_M0_DQ13" Po -4133 2165 $EndPAD $PAD @@ -4584,7 +4589,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/fpga2/R_M0_DQ12" +Ne 174 "/fpga2/R_M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -4605,7 +4610,7 @@ $PAD Sh "U6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/fpga1/FPGA_BANK0_IO_62" +Ne 45 "/expansion/FPGA_BANK0_IO_62" Po -2165 2165 $EndPAD $PAD @@ -4619,21 +4624,21 @@ $PAD Sh "U8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/expansion/FPGA_BANK0_IO_54" +Ne 84 "/fpga1/FPGA_BANK0_IO_54" Po -1377 2165 $EndPAD $PAD Sh "U9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/fpga1/FPGA_BANK0_IO_51" +Ne 44 "/expansion/FPGA_BANK0_IO_51" Po -983 2165 $EndPAD $PAD Sh "U10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/fpga1/FPGA_BANK0_IO_56" +Ne 85 "/fpga1/FPGA_BANK0_IO_56" Po -590 2165 $EndPAD $PAD @@ -4654,14 +4659,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/fpga1/PROG_MISO3" +Ne 108 "/fpga1/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/fpga1/PROG_MISO2" +Ne 107 "/fpga1/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -4675,14 +4680,14 @@ $PAD Sh "U16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/expansion/FPGA_BANK0_IO_9" +Ne 47 "/expansion/FPGA_BANK0_IO_9" Po 1771 2165 $EndPAD $PAD Sh "U17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/fpga1/FPGA_BANK0_IO_8" +Ne 91 "/fpga1/FPGA_BANK0_IO_8" Po 2165 2165 $EndPAD $PAD @@ -4703,7 +4708,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 223 "/fpga2/R_M1_DQ12" +Ne 214 "/fpga2/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -4717,21 +4722,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 224 "/fpga2/R_M1_DQ13" +Ne 215 "/fpga2/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 186 "/fpga2/R_M0_DQ15" +Ne 177 "/fpga2/R_M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "/fpga2/R_M0_DQ14" +Ne 176 "/fpga2/R_M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -4752,7 +4757,7 @@ $PAD Sh "V5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/fpga1/FPGA_BANK0_IO_63" +Ne 90 "/fpga1/FPGA_BANK0_IO_63" Po -2558 2558 $EndPAD $PAD @@ -4766,7 +4771,7 @@ $PAD Sh "V7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/fpga1/FPGA_BANK0_IO_49" +Ne 80 "/fpga1/FPGA_BANK0_IO_49" Po -1771 2558 $EndPAD $PAD @@ -4780,7 +4785,7 @@ $PAD Sh "V9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/fpga1/FPGA_BANK0_IO_52" +Ne 82 "/fpga1/FPGA_BANK0_IO_52" Po -983 2558 $EndPAD $PAD @@ -4794,7 +4799,7 @@ $PAD Sh "V11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/expansion/FPGA_BANK0_IO_43" +Ne 37 "/expansion/FPGA_BANK0_IO_43" Po -196 2558 $EndPAD $PAD @@ -4822,7 +4827,7 @@ $PAD Sh "V15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/expansion/FPGA_BANK0_IO_17" +Ne 70 "/fpga1/FPGA_BANK0_IO_17" Po 1377 2558 $EndPAD $PAD @@ -4836,21 +4841,21 @@ $PAD Sh "V17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/fpga1/FPGA_BANK0_IO_14" +Ne 25 "/expansion/FPGA_BANK0_IO_14" Po 2165 2558 $EndPAD $PAD Sh "V18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/expansion/FPGA_BANK0_IO_11" +Ne 23 "/expansion/FPGA_BANK0_IO_11" Po 2558 2558 $EndPAD $PAD Sh "V19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/expansion/FPGA_BANK0_IO_10" +Ne 69 "/fpga1/FPGA_BANK0_IO_10" Po 2952 2558 $EndPAD $PAD @@ -4864,14 +4869,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 225 "/fpga2/R_M1_DQ14" +Ne 216 "/fpga2/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 226 "/fpga2/R_M1_DQ15" +Ne 217 "/fpga2/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -4913,7 +4918,7 @@ $PAD Sh "W6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/fpga1/FPGA_BANK0_IO_57" +Ne 86 "/fpga1/FPGA_BANK0_IO_57" Po -2165 2952 $EndPAD $PAD @@ -4927,28 +4932,28 @@ $PAD Sh "W8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/fpga1/FPGA_BANK0_IO_48" +Ne 42 "/expansion/FPGA_BANK0_IO_48" Po -1377 2952 $EndPAD $PAD Sh "W9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/expansion/FPGA_BANK0_IO_50" +Ne 81 "/fpga1/FPGA_BANK0_IO_50" Po -983 2952 $EndPAD $PAD Sh "W10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/expansion/FPGA_BANK0_IO_46" +Ne 40 "/expansion/FPGA_BANK0_IO_46" Po -590 2952 $EndPAD $PAD Sh "W11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/fpga1/FPGA_BANK0_IO_44" +Ne 38 "/expansion/FPGA_BANK0_IO_44" Po -196 2952 $EndPAD $PAD @@ -4962,21 +4967,21 @@ $PAD Sh "W13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/fpga1/FPGA_BANK0_IO_27" +Ne 76 "/fpga1/FPGA_BANK0_IO_27" Po 590 2952 $EndPAD $PAD Sh "W14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/fpga1/FPGA_BANK0_IO_30" +Ne 78 "/fpga1/FPGA_BANK0_IO_30" Po 983 2952 $EndPAD $PAD Sh "W15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/fpga1/FPGA_BANK0_IO_25" +Ne 75 "/fpga1/FPGA_BANK0_IO_25" Po 1377 2952 $EndPAD $PAD @@ -4990,7 +4995,7 @@ $PAD Sh "W17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/expansion/FPGA_BANK0_IO_15" +Ne 26 "/expansion/FPGA_BANK0_IO_15" Po 2165 2952 $EndPAD $PAD @@ -5088,21 +5093,21 @@ $PAD Sh "Y9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/fpga1/FPGA_BANK0_IO_45" +Ne 39 "/expansion/FPGA_BANK0_IO_45" Po -983 3346 $EndPAD $PAD Sh "Y10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/expansion/FPGA_BANK0_IO_47" +Ne 41 "/expansion/FPGA_BANK0_IO_47" Po -590 3346 $EndPAD $PAD Sh "Y11" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/expansion/FPGA_BANK0_IO_40" +Ne 36 "/expansion/FPGA_BANK0_IO_40" Po -196 3346 $EndPAD $PAD @@ -5116,7 +5121,7 @@ $PAD Sh "Y13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/expansion/FPGA_BANK0_IO_38" +Ne 34 "/expansion/FPGA_BANK0_IO_38" Po 590 3346 $EndPAD $PAD @@ -5130,35 +5135,35 @@ $PAD Sh "Y15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/expansion/FPGA_BANK0_IO_32" +Ne 79 "/fpga1/FPGA_BANK0_IO_32" Po 1377 3346 $EndPAD $PAD Sh "Y16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/fpga1/FPGA_BANK0_IO_24" +Ne 28 "/expansion/FPGA_BANK0_IO_24" Po 1771 3346 $EndPAD $PAD Sh "Y17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/expansion/FPGA_BANK0_IO_20" +Ne 73 "/fpga1/FPGA_BANK0_IO_20" Po 2165 3346 $EndPAD $PAD Sh "Y18" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/expansion/FPGA_BANK0_IO_5" +Ne 43 "/expansion/FPGA_BANK0_IO_5" Po 2558 3346 $EndPAD $PAD Sh "Y19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/expansion/FPGA_BANK0_IO_3" +Ne 30 "/expansion/FPGA_BANK0_IO_3" Po 2952 3346 $EndPAD $PAD @@ -5179,14 +5184,14 @@ $PAD Sh "Y22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 335 "N-000365" +Ne 335 "N-000366" Po 4133 3346 $EndPAD $PAD Sh "AA1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 334 "N-000362" +Ne 334 "N-000363" Po -4133 3739 $EndPAD $PAD @@ -5277,7 +5282,7 @@ $PAD Sh "AA14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/fpga1/FPGA_BANK0_IO_22" +Ne 27 "/expansion/FPGA_BANK0_IO_22" Po 983 3739 $EndPAD $PAD @@ -5291,7 +5296,7 @@ $PAD Sh "AA16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/fpga1/FPGA_BANK0_IO_28" +Ne 29 "/expansion/FPGA_BANK0_IO_28" Po 1771 3739 $EndPAD $PAD @@ -5305,7 +5310,7 @@ $PAD Sh "AA18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/fpga1/FPGA_BANK0_IO_18" +Ne 71 "/fpga1/FPGA_BANK0_IO_18" Po 2558 3739 $EndPAD $PAD @@ -5319,14 +5324,14 @@ $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/fpga1/PROG_MISO1" +Ne 106 "/fpga1/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/fpga1/PROG_CCLK" +Ne 103 "/fpga1/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -5424,7 +5429,7 @@ $PAD Sh "AB13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/expansion/FPGA_BANK0_IO_39" +Ne 35 "/expansion/FPGA_BANK0_IO_39" Po 590 4133 $EndPAD $PAD @@ -5438,21 +5443,21 @@ $PAD Sh "AB15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/fpga1/FPGA_BANK0_IO_33" +Ne 31 "/expansion/FPGA_BANK0_IO_33" Po 1377 4133 $EndPAD $PAD Sh "AB16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/expansion/FPGA_BANK0_IO_29" +Ne 77 "/fpga1/FPGA_BANK0_IO_29" Po 1771 4133 $EndPAD $PAD Sh "AB17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/expansion/FPGA_BANK0_IO_21" +Ne 74 "/fpga1/FPGA_BANK0_IO_21" Po 2165 4133 $EndPAD $PAD @@ -5473,7 +5478,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/fpga1/PROG_MISO0" +Ne 105 "/fpga1/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -5564,14 +5569,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 198 "/fpga2/R_M0_UDM" +Ne 189 "/fpga2/R_M0_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 136 "/fpga2/M0_UDM" +Ne 259 "/sdram/M0_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5592,7 +5597,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 199 "/fpga2/R_M0_UDQS" +Ne 190 "/fpga2/R_M0_UDQS" Po -176 0 $EndPAD $PAD @@ -5620,14 +5625,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 178 "/fpga2/R_M0_CKE" +Ne 169 "/fpga2/R_M0_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 251 "/sdram/M0_CKE" +Ne 245 "/sdram/M0_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5648,14 +5653,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 123 "/fpga2/M0_CLK" +Ne 246 "/sdram/M0_CLK" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 252 "/sdram/M0_CLK#" +Ne 247 "/sdram/M0_CLK#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5674,49 +5679,49 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/fpga2/R_M0_A0" +Ne 153 "/fpga2/R_M0_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/fpga2/R_M0_A1" +Ne 154 "/fpga2/R_M0_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/fpga2/R_M0_A2" +Ne 158 "/fpga2/R_M0_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/fpga2/R_M0_A3" +Ne 159 "/fpga2/R_M0_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 248 "/sdram/M0_A3" +Ne 238 "/sdram/M0_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 115 "/fpga2/M0_A2" +Ne 116 "/fpga2/M0_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 246 "/sdram/M0_A1" +Ne 237 "/sdram/M0_A1" Po -98 177 $EndPAD $PAD @@ -5742,28 +5747,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 197 "/fpga2/R_M0_RAS#" +Ne 188 "/fpga2/R_M0_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 175 "/fpga2/R_M0_BA0" +Ne 166 "/fpga2/R_M0_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 176 "/fpga2/R_M0_BA1" +Ne 167 "/fpga2/R_M0_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/fpga2/R_M0_A10" +Ne 155 "/fpga2/R_M0_A10" Po 295 -177 $EndPAD $PAD @@ -5777,21 +5782,21 @@ $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 250 "/sdram/M0_BA1" +Ne 243 "/sdram/M0_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 121 "/fpga2/M0_BA0" +Ne 242 "/sdram/M0_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 259 "/sdram/M0_RAS#" +Ne 258 "/sdram/M0_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5810,35 +5815,35 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 172 "/fpga2/R_M0_A7" +Ne 163 "/fpga2/R_M0_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/fpga2/R_M0_A6" +Ne 162 "/fpga2/R_M0_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/fpga2/R_M0_A5" +Ne 161 "/fpga2/R_M0_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/fpga2/R_M0_A4" +Ne 160 "/fpga2/R_M0_A4" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 116 "/fpga2/M0_A4" +Ne 239 "/sdram/M0_A4" Po 295 177 $EndPAD $PAD @@ -5852,7 +5857,7 @@ $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 249 "/sdram/M0_A6" +Ne 240 "/sdram/M0_A6" Po -98 177 $EndPAD $PAD @@ -5878,56 +5883,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/fpga2/R_M0_A12" +Ne 157 "/fpga2/R_M0_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/fpga2/R_M0_A11" +Ne 156 "/fpga2/R_M0_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 174 "/fpga2/R_M0_A9" +Ne 165 "/fpga2/R_M0_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 173 "/fpga2/R_M0_A8" +Ne 164 "/fpga2/R_M0_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 119 "/fpga2/M0_A8" +Ne 241 "/sdram/M0_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 120 "/fpga2/M0_A9" +Ne 119 "/fpga2/M0_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 247 "/sdram/M0_A11" +Ne 114 "/fpga2/M0_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 114 "/fpga2/M0_A12" +Ne 115 "/fpga2/M0_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5946,56 +5951,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 189 "/fpga2/R_M0_DQ4" +Ne 180 "/fpga2/R_M0_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 190 "/fpga2/R_M0_DQ5" +Ne 181 "/fpga2/R_M0_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 191 "/fpga2/R_M0_DQ6" +Ne 182 "/fpga2/R_M0_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 192 "/fpga2/R_M0_DQ7" +Ne 183 "/fpga2/R_M0_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 132 "/fpga2/M0_DQ7" +Ne 256 "/sdram/M0_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 131 "/fpga2/M0_DQ6" +Ne 255 "/sdram/M0_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 257 "/sdram/M0_DQ5" +Ne 124 "/fpga2/M0_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 256 "/sdram/M0_DQ4" +Ne 254 "/sdram/M0_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6014,56 +6019,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 179 "/fpga2/R_M0_DQ0" +Ne 170 "/fpga2/R_M0_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 180 "/fpga2/R_M0_DQ1" +Ne 171 "/fpga2/R_M0_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 187 "/fpga2/R_M0_DQ2" +Ne 178 "/fpga2/R_M0_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 188 "/fpga2/R_M0_DQ3" +Ne 179 "/fpga2/R_M0_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 130 "/fpga2/M0_DQ3" +Ne 123 "/fpga2/M0_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 129 "/fpga2/M0_DQ2" +Ne 122 "/fpga2/M0_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 125 "/fpga2/M0_DQ1" +Ne 120 "/fpga2/M0_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 124 "/fpga2/M0_DQ0" +Ne 248 "/sdram/M0_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6082,56 +6087,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 193 "/fpga2/R_M0_DQ8" +Ne 184 "/fpga2/R_M0_DQ8" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 194 "/fpga2/R_M0_DQ9" +Ne 185 "/fpga2/R_M0_DQ9" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/fpga2/R_M0_DQ10" +Ne 172 "/fpga2/R_M0_DQ10" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/fpga2/R_M0_DQ11" +Ne 173 "/fpga2/R_M0_DQ11" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 127 "/fpga2/M0_DQ11" +Ne 121 "/fpga2/M0_DQ11" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 126 "/fpga2/M0_DQ10" +Ne 249 "/sdram/M0_DQ10" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 133 "/fpga2/M0_DQ9" +Ne 126 "/fpga2/M0_DQ9" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 258 "/sdram/M0_DQ8" +Ne 125 "/fpga2/M0_DQ8" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6150,56 +6155,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/fpga2/R_M0_DQ12" +Ne 174 "/fpga2/R_M0_DQ12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/fpga2/R_M0_DQ13" +Ne 175 "/fpga2/R_M0_DQ13" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 185 "/fpga2/R_M0_DQ14" +Ne 176 "/fpga2/R_M0_DQ14" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 186 "/fpga2/R_M0_DQ15" +Ne 177 "/fpga2/R_M0_DQ15" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 128 "/fpga2/M0_DQ15" +Ne 253 "/sdram/M0_DQ15" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 255 "/sdram/M0_DQ14" +Ne 252 "/sdram/M0_DQ14" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 254 "/sdram/M0_DQ13" +Ne 251 "/sdram/M0_DQ13" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 253 "/sdram/M0_DQ12" +Ne 250 "/sdram/M0_DQ12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6220,14 +6225,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 239 "/fpga2/R_M1_UDQS" +Ne 230 "/fpga2/R_M1_UDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/fpga2/M1_UDQS" +Ne 278 "/sdram/M1_UDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6248,14 +6253,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 218 "/fpga2/R_M1_CS#" +Ne 209 "/fpga2/R_M1_CS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 148 "/fpga2/M1_CS#" +Ne 138 "/fpga2/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6276,14 +6281,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 217 "/fpga2/R_M1_CKE" +Ne 208 "/fpga2/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 145 "/fpga2/M1_CKE" +Ne 271 "/sdram/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6304,14 +6309,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 238 "/fpga2/R_M1_UDM" +Ne 229 "/fpga2/R_M1_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 278 "/sdram/M1_UDM" +Ne 277 "/sdram/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6330,56 +6335,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/fpga2/M1_DQ15" +Ne 143 "/fpga2/M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 152 "/fpga2/M1_DQ14" +Ne 142 "/fpga2/M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 273 "/sdram/M1_DQ13" +Ne 141 "/fpga2/M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 272 "/sdram/M1_DQ12" +Ne 140 "/fpga2/M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 223 "/fpga2/R_M1_DQ12" +Ne 214 "/fpga2/R_M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 224 "/fpga2/R_M1_DQ13" +Ne 215 "/fpga2/R_M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 225 "/fpga2/R_M1_DQ14" +Ne 216 "/fpga2/R_M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 226 "/fpga2/R_M1_DQ15" +Ne 217 "/fpga2/R_M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6398,56 +6403,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 151 "/fpga2/M1_DQ11" +Ne 274 "/sdram/M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/fpga2/M1_DQ10" +Ne 273 "/sdram/M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/fpga2/M1_DQ9" +Ne 150 "/fpga2/M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/fpga2/M1_DQ8" +Ne 149 "/fpga2/M1_DQ8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 233 "/fpga2/R_M1_DQ8" +Ne 224 "/fpga2/R_M1_DQ8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 234 "/fpga2/R_M1_DQ9" +Ne 225 "/fpga2/R_M1_DQ9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 221 "/fpga2/R_M1_DQ10" +Ne 212 "/fpga2/R_M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 222 "/fpga2/R_M1_DQ11" +Ne 213 "/fpga2/R_M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6468,14 +6473,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 147 "/fpga2/M1_CLK#" +Ne 137 "/fpga2/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 146 "/fpga2/M1_CLK" +Ne 136 "/fpga2/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6494,56 +6499,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 265 "/sdram/M1_A12" +Ne 130 "/fpga2/M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 138 "/fpga2/M1_A11" +Ne 264 "/sdram/M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/fpga2/M1_A9" +Ne 269 "/sdram/M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/fpga2/M1_A8" +Ne 133 "/fpga2/M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 212 "/fpga2/R_M1_A8" +Ne 203 "/fpga2/R_M1_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 213 "/fpga2/R_M1_A9" +Ne 204 "/fpga2/R_M1_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 204 "/fpga2/R_M1_A11" +Ne 195 "/fpga2/R_M1_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 205 "/fpga2/R_M1_A12" +Ne 196 "/fpga2/R_M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6562,21 +6567,21 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 141 "/fpga2/M1_A7" +Ne 268 "/sdram/M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 140 "/fpga2/M1_A6" +Ne 132 "/fpga2/M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 268 "/sdram/M1_A5" +Ne 131 "/fpga2/M1_A5" Po 98 -177 $EndPAD $PAD @@ -6590,28 +6595,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 208 "/fpga2/R_M1_A4" +Ne 199 "/fpga2/R_M1_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 209 "/fpga2/R_M1_A5" +Ne 200 "/fpga2/R_M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 210 "/fpga2/R_M1_A6" +Ne 201 "/fpga2/R_M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 211 "/fpga2/R_M1_A7" +Ne 202 "/fpga2/R_M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6630,56 +6635,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 219 "/fpga2/R_M1_DQ0" +Ne 210 "/fpga2/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 220 "/fpga2/R_M1_DQ1" +Ne 211 "/fpga2/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 227 "/fpga2/R_M1_DQ2" +Ne 218 "/fpga2/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 228 "/fpga2/R_M1_DQ3" +Ne 219 "/fpga2/R_M1_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/fpga2/M1_DQ3" +Ne 144 "/fpga2/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 154 "/fpga2/M1_DQ2" +Ne 275 "/sdram/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 271 "/sdram/M1_DQ1" +Ne 272 "/sdram/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/fpga2/M1_DQ0" +Ne 139 "/fpga2/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6698,56 +6703,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 229 "/fpga2/R_M1_DQ4" +Ne 220 "/fpga2/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 230 "/fpga2/R_M1_DQ5" +Ne 221 "/fpga2/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 231 "/fpga2/R_M1_DQ6" +Ne 222 "/fpga2/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 232 "/fpga2/R_M1_DQ7" +Ne 223 "/fpga2/R_M1_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/fpga2/M1_DQ7" +Ne 148 "/fpga2/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 275 "/sdram/M1_DQ6" +Ne 147 "/fpga2/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 274 "/sdram/M1_DQ5" +Ne 146 "/fpga2/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/fpga2/M1_DQ4" +Ne 145 "/fpga2/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6766,56 +6771,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 237 "/fpga2/R_M1_RAS#" +Ne 228 "/fpga2/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 214 "/fpga2/R_M1_BA0" +Ne 205 "/fpga2/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 215 "/fpga2/R_M1_BA1" +Ne 206 "/fpga2/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 203 "/fpga2/R_M1_A10" +Ne 194 "/fpga2/R_M1_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 264 "/sdram/M1_A10" +Ne 263 "/sdram/M1_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/fpga2/M1_BA1" +Ne 134 "/fpga2/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 269 "/sdram/M1_BA0" +Ne 270 "/sdram/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 277 "/sdram/M1_RAS#" +Ne 152 "/fpga2/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6834,28 +6839,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "/fpga2/R_M1_A0" +Ne 192 "/fpga2/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 202 "/fpga2/R_M1_A1" +Ne 193 "/fpga2/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 206 "/fpga2/R_M1_A2" +Ne 197 "/fpga2/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 207 "/fpga2/R_M1_A3" +Ne 198 "/fpga2/R_M1_A3" Po 295 -177 $EndPAD $PAD @@ -6869,21 +6874,21 @@ $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 139 "/fpga2/M1_A2" +Ne 265 "/sdram/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 263 "/sdram/M1_A1" +Ne 129 "/fpga2/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 137 "/fpga2/M1_A0" +Ne 128 "/fpga2/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6939,7 +6944,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 16 "/ether/ETH_PLL1.8V" +Ne 13 "/ether/ETH_PLL1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7141,42 +7146,42 @@ $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/fpga1/PROG_CSO" +Ne 104 "/fpga1/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/fpga1/PROG_MISO3" +Ne 108 "/fpga1/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/fpga1/PROG_CCLK" +Ne 103 "/fpga1/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/fpga1/PROG_MISO0" +Ne 105 "/fpga1/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/fpga1/PROG_MISO1" +Ne 106 "/fpga1/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/fpga1/PROG_MISO2" +Ne 107 "/fpga1/PROG_MISO2" Po 250 1050 $EndPAD $PAD @@ -9245,7 +9250,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 16 "/ether/ETH_PLL1.8V" +Ne 13 "/ether/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD @@ -9329,7 +9334,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 15 "/ether/ETH_MDIO" +Ne 12 "/ether/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -9357,7 +9362,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 295 "N-000125" +Ne 295 "N-000126" Po -176 0 $EndPAD $PAD @@ -9392,7 +9397,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/ether/MAG_TX+" +Ne 21 "/ether/MAG_TX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9420,7 +9425,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/ether/MAG_TX-" +Ne 22 "/ether/MAG_TX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9448,7 +9453,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 22 "/ether/MAG_RX+" +Ne 18 "/ether/MAG_RX+" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9476,7 +9481,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/ether/MAG_RX-" +Ne 19 "/ether/MAG_RX-" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9497,14 +9502,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 294 "N-000121" +Ne 293 "N-000121" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 12 "/ether/ETH_LED0" +Ne 10 "/ether/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9525,14 +9530,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 293 "N-000120" +Ne 294 "N-000124" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 13 "/ether/ETH_LED1" +Ne 11 "/ether/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9561,7 +9566,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/fpga2/M0_DQ0" +Ne 248 "/sdram/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -9575,14 +9580,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/fpga2/M0_DQ1" +Ne 120 "/fpga2/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/fpga2/M0_DQ2" +Ne 122 "/fpga2/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -9596,14 +9601,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/fpga2/M0_DQ3" +Ne 123 "/fpga2/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 256 "/sdram/M0_DQ4" +Ne 254 "/sdram/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -9617,14 +9622,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 257 "/sdram/M0_DQ5" +Ne 124 "/fpga2/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/fpga2/M0_DQ6" +Ne 255 "/sdram/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -9638,7 +9643,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/fpga2/M0_DQ7" +Ne 256 "/sdram/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -9659,7 +9664,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/fpga2/M0_LDQS" +Ne 257 "/sdram/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -9687,7 +9692,7 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/fpga2/M0_LDM" +Ne 127 "/fpga2/M0_LDM" Po 767 2176 $EndPAD $PAD @@ -9701,14 +9706,14 @@ $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/fpga2/M0_CAS#" +Ne 244 "/sdram/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 259 "/sdram/M0_RAS#" +Ne 258 "/sdram/M0_RAS#" Po 1535 2176 $EndPAD $PAD @@ -9729,14 +9734,14 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/fpga2/M0_BA0" +Ne 242 "/sdram/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 250 "/sdram/M0_BA1" +Ne 243 "/sdram/M0_BA1" Po 2558 2176 $EndPAD $PAD @@ -9757,21 +9762,21 @@ $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 246 "/sdram/M0_A1" +Ne 237 "/sdram/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/fpga2/M0_A2" +Ne 116 "/fpga2/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 248 "/sdram/M0_A3" +Ne 238 "/sdram/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -9792,7 +9797,7 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/fpga2/M0_A4" +Ne 239 "/sdram/M0_A4" Po 3838 -2176 $EndPAD $PAD @@ -9806,7 +9811,7 @@ $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 249 "/sdram/M0_A6" +Ne 240 "/sdram/M0_A6" Po 3326 -2176 $EndPAD $PAD @@ -9820,28 +9825,28 @@ $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/fpga2/M0_A8" +Ne 241 "/sdram/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/fpga2/M0_A9" +Ne 119 "/fpga2/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 247 "/sdram/M0_A11" +Ne 114 "/fpga2/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/fpga2/M0_A12" +Ne 115 "/fpga2/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -9855,28 +9860,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 252 "/sdram/M0_CLK#" +Ne 247 "/sdram/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 251 "/sdram/M0_CKE" +Ne 245 "/sdram/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/fpga2/M0_CLK" +Ne 246 "/sdram/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/fpga2/M0_UDM" +Ne 259 "/sdram/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -9925,7 +9930,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 258 "/sdram/M0_DQ8" +Ne 125 "/fpga2/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -9939,14 +9944,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/fpga2/M0_DQ9" +Ne 126 "/fpga2/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/fpga2/M0_DQ10" +Ne 249 "/sdram/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -9960,14 +9965,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/fpga2/M0_DQ11" +Ne 121 "/fpga2/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 253 "/sdram/M0_DQ12" +Ne 250 "/sdram/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -9981,14 +9986,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 254 "/sdram/M0_DQ13" +Ne 251 "/sdram/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 255 "/sdram/M0_DQ14" +Ne 252 "/sdram/M0_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10002,7 +10007,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/fpga2/M0_DQ15" +Ne 253 "/sdram/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10038,7 +10043,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/fpga2/M1_DQ0" +Ne 139 "/fpga2/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -10052,14 +10057,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 271 "/sdram/M1_DQ1" +Ne 272 "/sdram/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/fpga2/M1_DQ2" +Ne 275 "/sdram/M1_DQ2" Po -3070 2176 $EndPAD $PAD @@ -10073,14 +10078,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/fpga2/M1_DQ3" +Ne 144 "/fpga2/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/fpga2/M1_DQ4" +Ne 145 "/fpga2/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -10094,14 +10099,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 274 "/sdram/M1_DQ5" +Ne 146 "/fpga2/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 275 "/sdram/M1_DQ6" +Ne 147 "/fpga2/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -10115,7 +10120,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/fpga2/M1_DQ7" +Ne 148 "/fpga2/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -10164,7 +10169,7 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/fpga2/M1_LDM" +Ne 151 "/fpga2/M1_LDM" Po 767 2176 $EndPAD $PAD @@ -10178,21 +10183,21 @@ $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 270 "/sdram/M1_CAS#" +Ne 135 "/fpga2/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 277 "/sdram/M1_RAS#" +Ne 152 "/fpga2/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/fpga2/M1_CS#" +Ne 138 "/fpga2/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -10206,42 +10211,42 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 269 "/sdram/M1_BA0" +Ne 270 "/sdram/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/fpga2/M1_BA1" +Ne 134 "/fpga2/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 264 "/sdram/M1_A10" +Ne 263 "/sdram/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/fpga2/M1_A0" +Ne 128 "/fpga2/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 263 "/sdram/M1_A1" +Ne 129 "/fpga2/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/fpga2/M1_A2" +Ne 265 "/sdram/M1_A2" Po 3582 2176 $EndPAD $PAD @@ -10276,49 +10281,49 @@ $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 268 "/sdram/M1_A5" +Ne 131 "/fpga2/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/fpga2/M1_A6" +Ne 132 "/fpga2/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/fpga2/M1_A7" +Ne 268 "/sdram/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/fpga2/M1_A8" +Ne 133 "/fpga2/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/fpga2/M1_A9" +Ne 269 "/sdram/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/fpga2/M1_A11" +Ne 264 "/sdram/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 265 "/sdram/M1_A12" +Ne 130 "/fpga2/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -10332,28 +10337,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/fpga2/M1_CLK#" +Ne 137 "/fpga2/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/fpga2/M1_CKE" +Ne 271 "/sdram/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/fpga2/M1_CLK" +Ne 136 "/fpga2/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 278 "/sdram/M1_UDM" +Ne 277 "/sdram/M1_UDM" Po 767 -2176 $EndPAD $PAD @@ -10381,7 +10386,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/fpga2/M1_UDQS" +Ne 278 "/sdram/M1_UDQS" Po -255 -2176 $EndPAD $PAD @@ -10402,7 +10407,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/fpga2/M1_DQ8" +Ne 149 "/fpga2/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10416,14 +10421,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/fpga2/M1_DQ9" +Ne 150 "/fpga2/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/fpga2/M1_DQ10" +Ne 273 "/sdram/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -10437,14 +10442,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/fpga2/M1_DQ11" +Ne 274 "/sdram/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 272 "/sdram/M1_DQ12" +Ne 140 "/fpga2/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10458,14 +10463,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 273 "/sdram/M1_DQ13" +Ne 141 "/fpga2/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/fpga2/M1_DQ14" +Ne 142 "/fpga2/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10479,7 +10484,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/fpga2/M1_DQ15" +Ne 143 "/fpga2/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10506,35 +10511,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 24 "/ether/MAG_SHIELD" +Ne 20 "/ether/MAG_SHIELD" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 24 "/ether/MAG_SHIELD" +Ne 20 "/ether/MAG_SHIELD" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 24 "/ether/MAG_SHIELD" +Ne 20 "/ether/MAG_SHIELD" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 24 "/ether/MAG_SHIELD" +Ne 20 "/ether/MAG_SHIELD" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 25 "/ether/MAG_TX+" +Ne 21 "/ether/MAG_TX+" Po -1750 -2500 $EndPAD $PAD @@ -10555,14 +10560,14 @@ $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 22 "/ether/MAG_RX+" +Ne 18 "/ether/MAG_RX+" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 26 "/ether/MAG_TX-" +Ne 22 "/ether/MAG_TX-" Po -1250 -3500 $EndPAD $PAD @@ -10583,7 +10588,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 23 "/ether/MAG_RX-" +Ne 19 "/ether/MAG_RX-" Po 1750 -3500 $EndPAD $PAD @@ -10597,7 +10602,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 294 "N-000121" +Ne 293 "N-000121" Po -1150 -5400 $EndPAD $PAD @@ -10611,7 +10616,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 293 "N-000120" +Ne 294 "N-000124" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -10636,21 +10641,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 60 "/flash/SD_DAT2" +Ne 111 "/fpga1/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 111 "/fpga1/SD_DAT3" +Ne 53 "/flash/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 108 "/fpga1/SD_CMD" +Ne 109 "/fpga1/SD_CMD" Po -433 0 $EndPAD $PAD @@ -10664,7 +10669,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 107 "/fpga1/SD_CLK" +Ne 51 "/flash/SD_CLK" Po 433 0 $EndPAD $PAD @@ -10678,14 +10683,14 @@ $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 109 "/fpga1/SD_DAT0" +Ne 110 "/fpga1/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 110 "/fpga1/SD_DAT1" +Ne 52 "/flash/SD_DAT1" Po 1732 0 $EndPAD $PAD @@ -10977,28 +10982,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/fpga1/NF_RNB" +Ne 49 "/flash/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/fpga1/NF_RNB" +Ne 49 "/flash/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/flash/NF_RE_N" +Ne 102 "/fpga1/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/flash/NF_CS1_N" +Ne 94 "/fpga1/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -11047,21 +11052,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/flash/NF_CLE" +Ne 93 "/fpga1/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/flash/NF_ALE" +Ne 92 "/fpga1/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/fpga1/NF_WE_N" +Ne 50 "/flash/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -11138,28 +11143,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/flash/NF_D0" +Ne 95 "/fpga1/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/flash/NF_D1" +Ne 96 "/fpga1/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/fpga1/NF_D2" +Ne 48 "/flash/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/flash/NF_D3" +Ne 97 "/fpga1/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -11222,28 +11227,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/fpga1/NF_D4" +Ne 98 "/fpga1/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/flash/NF_D5" +Ne 99 "/fpga1/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/fpga1/NF_D6" +Ne 100 "/fpga1/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/flash/NF_D7" +Ne 101 "/fpga1/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -11300,21 +11305,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/fpga1/ETH_RXER" +Ne 15 "/ether/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/ether/ETH_RXC" +Ne 58 "/fpga1/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/ether/ETH_RXDV" +Ne 14 "/ether/ETH_RXDV" Po -1613 491 $EndPAD $PAD @@ -11335,63 +11340,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/fpga1/ETH_RXD0" +Ne 59 "/fpga1/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/fpga1/ETH_RXD1" +Ne 60 "/fpga1/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/fpga1/ETH_RXD2" +Ne 61 "/fpga1/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/fpga1/ETH_RXD3" +Ne 62 "/fpga1/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/ether/ETH_MDC" +Ne 56 "/fpga1/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/ether/ETH_MDIO" +Ne 12 "/ether/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/fpga1/ETH_RESET_N" +Ne 57 "/fpga1/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/ether/ETH_PLL1.8V" +Ne 13 "/ether/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/ether/ETH_CLK" +Ne 54 "/fpga1/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -11426,14 +11431,14 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/ether/MAG_TX+" +Ne 21 "/ether/MAG_TX+" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/ether/MAG_TX-" +Ne 22 "/ether/MAG_TX-" Po 491 -1613 $EndPAD $PAD @@ -11454,28 +11459,28 @@ $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 295 "N-000125" +Ne 295 "N-000126" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/ether/ETH_INT" +Ne 9 "/ether/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/ether/ETH_LED0" +Ne 10 "/ether/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/ether/ETH_LED1" +Ne 11 "/ether/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -11510,14 +11515,14 @@ $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/ether/MAG_RX-" +Ne 19 "/ether/MAG_RX-" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/ether/MAG_RX+" +Ne 18 "/ether/MAG_RX+" Po 1613 -491 $EndPAD $PAD @@ -11552,63 +11557,63 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/ether/ETH_TXER" +Ne 17 "/ether/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/fpga1/ETH_TXC" +Ne 63 "/fpga1/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/fpga1/ETH_TXEN" +Ne 67 "/fpga1/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/ether/ETH_TXD0" +Ne 64 "/fpga1/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/fpga1/ETH_TXD1" +Ne 65 "/fpga1/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/fpga1/ETH_TXD2" +Ne 16 "/ether/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/ether/ETH_TXD3" +Ne 66 "/fpga1/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/ether/ETH_COL" +Ne 8 "/ether/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/ether/ETH_CRS" +Ne 55 "/fpga1/ETH_CRS" Po 688 1613 $EndPAD $PAD @@ -11706,7 +11711,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 335 "N-000365" +Ne 335 "N-000366" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11734,7 +11739,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 334 "N-000362" +Ne 334 "N-000363" Po 176 0 $EndPAD $EndMODULE 0402 @@ -11770,7 +11775,7 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 289 "/usb/USBD_SPD" +Ne 288 "/usb/USBD_SPD" Po -295 491 $EndPAD $PAD @@ -11784,7 +11789,7 @@ $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 243 "/fpga2/USBD_RCV" +Ne 235 "/fpga2/USBD_RCV" Po -98 491 $EndPAD $PAD @@ -11798,21 +11803,21 @@ $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 245 "/fpga2/USBD_VP" +Ne 236 "/fpga2/USBD_VP" Po 98 491 $EndPAD $PAD Sh "9" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 288 "/usb/USBD_OE_N" +Ne 234 "/fpga2/USBD_OE_N" Po 295 -491 $EndPAD $PAD Sh "4" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 244 "/fpga2/USBD_VM" +Ne 289 "/usb/USBD_VM" Po 295 491 $EndPAD $PAD @@ -11918,7 +11923,7 @@ $PAD Sh "2" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 241 "/fpga2/USBA_RCV" +Ne 232 "/fpga2/USBA_RCV" Po -98 491 $EndPAD $PAD @@ -11932,7 +11937,7 @@ $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 242 "/fpga2/USBA_VP" +Ne 233 "/fpga2/USBA_VP" Po 98 491 $EndPAD $PAD @@ -12707,7 +12712,7 @@ $PAD Sh "1" R 355 668 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/ether/MAG_SHIELD" +Ne 20 "/ether/MAG_SHIELD" Po -570 0 $EndPAD $PAD @@ -12736,7 +12741,7 @@ $PAD Sh "1" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/fpga1/FPGA_BANK0_IO_8" +Ne 91 "/fpga1/FPGA_BANK0_IO_8" Po 9448 -747 $EndPAD $PAD @@ -12757,329 +12762,329 @@ $PAD Sh "7" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/expansion/FPGA_BANK0_IO_10" +Ne 69 "/fpga1/FPGA_BANK0_IO_10" Po 7086 -747 $EndPAD $PAD Sh "9" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/expansion/FPGA_BANK0_IO_11" +Ne 23 "/expansion/FPGA_BANK0_IO_11" Po 6299 -747 $EndPAD $PAD Sh "11" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 45 "/expansion/FPGA_BANK0_IO_5" +Ne 43 "/expansion/FPGA_BANK0_IO_5" Po 5511 -747 $EndPAD $PAD Sh "13" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/expansion/FPGA_BANK0_IO_17" +Ne 70 "/fpga1/FPGA_BANK0_IO_17" Po 4724 -747 $EndPAD $PAD Sh "15" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/expansion/FPGA_BANK0_IO_20" +Ne 73 "/fpga1/FPGA_BANK0_IO_20" Po 3936 -747 $EndPAD $PAD Sh "17" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 78 "/fpga1/FPGA_BANK0_IO_28" +Ne 29 "/expansion/FPGA_BANK0_IO_28" Po 3149 -747 $EndPAD $PAD Sh "19" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 74 "/fpga1/FPGA_BANK0_IO_22" +Ne 27 "/expansion/FPGA_BANK0_IO_22" Po 2362 -747 $EndPAD $PAD Sh "21" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 77 "/fpga1/FPGA_BANK0_IO_27" +Ne 76 "/fpga1/FPGA_BANK0_IO_27" Po 1574 -747 $EndPAD $PAD Sh "23" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/expansion/FPGA_BANK0_IO_39" +Ne 35 "/expansion/FPGA_BANK0_IO_39" Po 787 -747 $EndPAD $PAD Sh "25" R 392 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/expansion/FPGA_BANK0_IO_2" +Ne 72 "/fpga1/FPGA_BANK0_IO_2" Po 0 -747 $EndPAD $PAD Sh "27" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 49 "/expansion/FPGA_BANK0_IO_7" +Ne 46 "/expansion/FPGA_BANK0_IO_7" Po -787 -747 $EndPAD $PAD Sh "29" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 71 "/fpga1/FPGA_BANK0_IO_12" +Ne 24 "/expansion/FPGA_BANK0_IO_12" Po -1574 -747 $EndPAD $PAD Sh "31" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 82 "/fpga1/FPGA_BANK0_IO_44" +Ne 38 "/expansion/FPGA_BANK0_IO_44" Po -2362 -747 $EndPAD $PAD Sh "33" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 44 "/expansion/FPGA_BANK0_IO_47" +Ne 41 "/expansion/FPGA_BANK0_IO_47" Po -3149 -747 $EndPAD $PAD Sh "35" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 83 "/fpga1/FPGA_BANK0_IO_45" +Ne 39 "/expansion/FPGA_BANK0_IO_45" Po -3936 -747 $EndPAD $PAD Sh "37" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 87 "/fpga1/FPGA_BANK0_IO_52" +Ne 82 "/fpga1/FPGA_BANK0_IO_52" Po -4724 -747 $EndPAD $PAD Sh "39" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 89 "/fpga1/FPGA_BANK0_IO_56" +Ne 85 "/fpga1/FPGA_BANK0_IO_56" Po -5511 -747 $EndPAD $PAD Sh "41" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 86 "/fpga1/FPGA_BANK0_IO_51" +Ne 44 "/expansion/FPGA_BANK0_IO_51" Po -6299 -747 $EndPAD $PAD Sh "43" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/expansion/FPGA_BANK0_IO_54" +Ne 84 "/fpga1/FPGA_BANK0_IO_54" Po -7086 -747 $EndPAD $PAD Sh "45" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/fpga1/FPGA_BANK0_IO_63" +Ne 90 "/fpga1/FPGA_BANK0_IO_63" Po -7873 -747 $EndPAD $PAD Sh "47" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 88 "/fpga1/FPGA_BANK0_IO_53" +Ne 83 "/fpga1/FPGA_BANK0_IO_53" Po -8661 -747 $EndPAD $PAD Sh "49" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 91 "/fpga1/FPGA_BANK0_IO_58" +Ne 87 "/fpga1/FPGA_BANK0_IO_58" Po -9448 -747 $EndPAD $PAD Sh "2" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 27 "/expansion/FPGA_BANK0_IO_1" +Ne 68 "/fpga1/FPGA_BANK0_IO_1" Po 9448 747 $EndPAD $PAD Sh "4" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 50 "/expansion/FPGA_BANK0_IO_9" +Ne 47 "/expansion/FPGA_BANK0_IO_9" Po 8661 747 $EndPAD $PAD Sh "6" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 72 "/fpga1/FPGA_BANK0_IO_14" +Ne 25 "/expansion/FPGA_BANK0_IO_14" Po 7873 747 $EndPAD $PAD Sh "8" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 30 "/expansion/FPGA_BANK0_IO_15" +Ne 26 "/expansion/FPGA_BANK0_IO_15" Po 7086 747 $EndPAD $PAD Sh "10" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 36 "/expansion/FPGA_BANK0_IO_3" +Ne 30 "/expansion/FPGA_BANK0_IO_3" Po 6299 747 $EndPAD $PAD Sh "12" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 73 "/fpga1/FPGA_BANK0_IO_18" +Ne 71 "/fpga1/FPGA_BANK0_IO_18" Po 5511 747 $EndPAD $PAD Sh "14" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 34 "/expansion/FPGA_BANK0_IO_21" +Ne 74 "/fpga1/FPGA_BANK0_IO_21" Po 4724 747 $EndPAD $PAD Sh "16" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 75 "/fpga1/FPGA_BANK0_IO_24" +Ne 28 "/expansion/FPGA_BANK0_IO_24" Po 3936 747 $EndPAD $PAD Sh "18" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 35 "/expansion/FPGA_BANK0_IO_29" +Ne 77 "/fpga1/FPGA_BANK0_IO_29" Po 3149 747 $EndPAD $PAD Sh "20" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 79 "/fpga1/FPGA_BANK0_IO_30" +Ne 78 "/fpga1/FPGA_BANK0_IO_30" Po 2362 747 $EndPAD $PAD Sh "22" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 76 "/fpga1/FPGA_BANK0_IO_25" +Ne 75 "/fpga1/FPGA_BANK0_IO_25" Po 1574 747 $EndPAD $PAD Sh "24" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 80 "/fpga1/FPGA_BANK0_IO_33" +Ne 31 "/expansion/FPGA_BANK0_IO_33" Po 787 747 $EndPAD $PAD Sh "26" R 392 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 37 "/expansion/FPGA_BANK0_IO_32" +Ne 79 "/fpga1/FPGA_BANK0_IO_32" Po 0 747 $EndPAD $PAD Sh "28" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 48 "/expansion/FPGA_BANK0_IO_6" +Ne 88 "/fpga1/FPGA_BANK0_IO_6" Po -787 747 $EndPAD $PAD Sh "30" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 81 "/fpga1/FPGA_BANK0_IO_36" +Ne 33 "/expansion/FPGA_BANK0_IO_36" Po -1574 747 $EndPAD $PAD Sh "32" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 41 "/expansion/FPGA_BANK0_IO_40" +Ne 36 "/expansion/FPGA_BANK0_IO_40" Po -2362 747 $EndPAD $PAD Sh "34" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 42 "/expansion/FPGA_BANK0_IO_43" +Ne 37 "/expansion/FPGA_BANK0_IO_43" Po -3149 747 $EndPAD $PAD Sh "36" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 43 "/expansion/FPGA_BANK0_IO_46" +Ne 40 "/expansion/FPGA_BANK0_IO_46" Po -3936 747 $EndPAD $PAD Sh "38" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 46 "/expansion/FPGA_BANK0_IO_50" +Ne 81 "/fpga1/FPGA_BANK0_IO_50" Po -4724 747 $EndPAD $PAD Sh "40" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 84 "/fpga1/FPGA_BANK0_IO_48" +Ne 42 "/expansion/FPGA_BANK0_IO_48" Po -5511 747 $EndPAD $PAD Sh "42" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 38 "/expansion/FPGA_BANK0_IO_34" +Ne 32 "/expansion/FPGA_BANK0_IO_34" Po -6299 747 $EndPAD $PAD Sh "44" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 85 "/fpga1/FPGA_BANK0_IO_49" +Ne 80 "/fpga1/FPGA_BANK0_IO_49" Po -7086 747 $EndPAD $PAD Sh "46" R 393 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 93 "/fpga1/FPGA_BANK0_IO_62" +Ne 45 "/expansion/FPGA_BANK0_IO_62" Po -7873 747 $EndPAD $PAD Sh "48" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 90 "/fpga1/FPGA_BANK0_IO_57" +Ne 86 "/fpga1/FPGA_BANK0_IO_57" Po -8661 747 $EndPAD $PAD Sh "50" R 394 1181 0 0 0 Dr 0 0 0 At SMD N 00400001 -Ne 92 "/fpga1/FPGA_BANK0_IO_60" +Ne 89 "/fpga1/FPGA_BANK0_IO_60" Po -9448 747 $EndPAD $PAD @@ -13275,14 +13280,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 196 "/fpga2/R_M0_LDQS" +Ne 187 "/fpga2/R_M0_LDQS" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 135 "/fpga2/M0_LDQS" +Ne 257 "/sdram/M0_LDQS" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13303,14 +13308,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 195 "/fpga2/R_M0_LDM" +Ne 186 "/fpga2/R_M0_LDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 134 "/fpga2/M0_LDM" +Ne 127 "/fpga2/M0_LDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13331,7 +13336,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 200 "/fpga2/R_M0_WE#" +Ne 191 "/fpga2/R_M0_WE#" Po -176 0 $EndPAD $PAD @@ -13359,14 +13364,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 177 "/fpga2/R_M0_CAS#" +Ne 168 "/fpga2/R_M0_CAS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 122 "/fpga2/M0_CAS#" +Ne 244 "/sdram/M0_CAS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13387,7 +13392,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 236 "/fpga2/R_M1_LDQS" +Ne 227 "/fpga2/R_M1_LDQS" Po -176 0 $EndPAD $PAD @@ -13415,14 +13420,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 235 "/fpga2/R_M1_LDM" +Ne 226 "/fpga2/R_M1_LDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/fpga2/M1_LDM" +Ne 151 "/fpga2/M1_LDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13443,7 +13448,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 240 "/fpga2/R_M1_WE#" +Ne 231 "/fpga2/R_M1_WE#" Po -176 0 $EndPAD $PAD @@ -13471,14 +13476,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 216 "/fpga2/R_M1_CAS#" +Ne 207 "/fpga2/R_M1_CAS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 270 "/sdram/M1_CAS#" +Ne 135 "/fpga2/M1_CAS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -13541,7 +13546,7 @@ $PAD Sh "3" R 551 453 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/expansion/FPGA_BANK0_IO_38" +Ne 34 "/expansion/FPGA_BANK0_IO_38" Po 866 630 $EndPAD $PAD @@ -13569,7 +13574,7 @@ $PAD Sh "1" R 197 354 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/ether/MAG_SHIELD" +Ne 20 "/ether/MAG_SHIELD" Po -294 0 $EndPAD $PAD @@ -13661,42 +13666,42 @@ $PAD Sh "8" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 315 "N-000170" +Ne 317 "N-000172" Po -383 -905 $EndPAD $PAD Sh "2" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 321 "N-000176" +Ne 322 "N-000177" Po -127 905 $EndPAD $PAD Sh "7" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 313 "N-000168" +Ne 315 "N-000170" Po -127 -905 $EndPAD $PAD Sh "3" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 314 "N-000169" +Ne 316 "N-000171" Po 127 905 $EndPAD $PAD Sh "6" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 321 "N-000176" +Ne 322 "N-000177" Po 127 -905 $EndPAD $PAD Sh "4" R 161 394 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 320 "N-000175" +Ne 321 "N-000176" Po 383 905 $EndPAD $PAD @@ -13760,7 +13765,7 @@ $PAD Sh "1" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 309 "N-000163" +Ne 311 "N-000165" Po -393 -688 $EndPAD $PAD @@ -13774,91 +13779,91 @@ $PAD Sh "2" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 309 "N-000163" +Ne 311 "N-000165" Po -196 -688 $EndPAD $PAD Sh "13" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 327 "N-000184" +Ne 328 "N-000185" Po 0 688 $EndPAD $PAD Sh "3" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 309 "N-000163" +Ne 311 "N-000165" Po 0 -688 $EndPAD $PAD Sh "12" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 316 "N-000171" +Ne 307 "N-000161" Po 196 688 $EndPAD $PAD Sh "4" R 99 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 309 "N-000163" +Ne 311 "N-000165" Po 196 -688 $EndPAD $PAD Sh "11" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 328 "N-000185" +Ne 329 "N-000186" Po 393 688 $EndPAD $PAD Sh "5" R 98 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 309 "N-000163" +Ne 311 "N-000165" Po 393 -688 $EndPAD $PAD Sh "20" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 328 "N-000185" +Ne 329 "N-000186" Po -688 -393 $EndPAD $PAD Sh "6" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 308 "N-000162" +Ne 309 "N-000163" Po 688 -393 $EndPAD $PAD Sh "19" R 157 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 328 "N-000185" +Ne 329 "N-000186" Po -688 -196 $EndPAD $PAD Sh "7" R 157 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 308 "N-000162" +Ne 309 "N-000163" Po 688 -196 $EndPAD $PAD Sh "18" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 328 "N-000185" +Ne 329 "N-000186" Po -688 0 $EndPAD $PAD Sh "8" R 157 98 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 308 "N-000162" +Ne 309 "N-000163" Po 688 0 $EndPAD $PAD @@ -13872,7 +13877,7 @@ $PAD Sh "9" R 157 99 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 307 "N-000161" +Ne 310 "N-000164" Po 688 196 $EndPAD $PAD @@ -13915,7 +13920,7 @@ $PAD Sh "1" R 157 185 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 330 "N-000190" +Ne 331 "N-000191" Po -255 340 $EndPAD $PAD @@ -13936,7 +13941,7 @@ $PAD Sh "5" R 156 185 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 318 "N-000173" +Ne 319 "N-000174" Po 0 -340 $EndPAD $PAD @@ -13971,7 +13976,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 310 "N-000165" +Ne 312 "N-000167" Po -176 0 $EndPAD $PAD @@ -13999,14 +14004,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 329 "N-000186" +Ne 330 "N-000187" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 316 "N-000171" +Ne 307 "N-000161" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14027,14 +14032,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 307 "N-000161" +Ne 310 "N-000164" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 309 "N-000163" +Ne 311 "N-000165" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14062,7 +14067,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 308 "N-000162" +Ne 309 "N-000163" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14118,7 +14123,7 @@ $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 316 "N-000171" +Ne 307 "N-000161" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14139,14 +14144,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 317 "N-000172" +Ne 308 "N-000162" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 327 "N-000184" +Ne 328 "N-000185" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14167,7 +14172,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 317 "N-000172" +Ne 308 "N-000162" Po -176 0 $EndPAD $PAD @@ -14195,7 +14200,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 329 "N-000186" +Ne 330 "N-000187" Po -176 0 $EndPAD $PAD @@ -14223,7 +14228,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 330 "N-000190" +Ne 331 "N-000191" Po -176 0 $EndPAD $PAD @@ -14251,14 +14256,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 314 "N-000169" +Ne 316 "N-000171" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 321 "N-000176" +Ne 322 "N-000177" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14286,7 +14291,7 @@ $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 320 "N-000175" +Ne 321 "N-000176" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14307,7 +14312,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 313 "N-000168" +Ne 315 "N-000170" Po -176 0 $EndPAD $PAD @@ -14335,14 +14340,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 320 "N-000175" +Ne 321 "N-000176" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 313 "N-000168" +Ne 315 "N-000170" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14363,14 +14368,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 313 "N-000168" +Ne 315 "N-000170" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 320 "N-000175" +Ne 321 "N-000176" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14391,14 +14396,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 321 "N-000176" +Ne 322 "N-000177" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 313 "N-000168" +Ne 315 "N-000170" Po 176 0 $EndPAD $EndMODULE 0402 @@ -14419,7 +14424,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 321 "N-000176" +Ne 322 "N-000177" Po -176 0 $EndPAD $PAD @@ -14447,7 +14452,7 @@ $PAD Sh "1" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 330 "N-000190" +Ne 331 "N-000191" Po -373 0 $EndPAD $PAD @@ -14475,14 +14480,14 @@ $PAD Sh "1" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 330 "N-000190" +Ne 331 "N-000191" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 318 "N-000173" +Ne 319 "N-000174" Po 373 0 $EndPAD $EndMODULE 0805 @@ -14503,14 +14508,14 @@ $PAD Sh "1" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 315 "N-000170" +Ne 317 "N-000172" Po -373 0 $EndPAD $PAD Sh "2" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 313 "N-000168" +Ne 315 "N-000170" Po 373 0 $EndPAD $EndMODULE 0805 @@ -14531,14 +14536,14 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 329 "N-000186" +Ne 330 "N-000187" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 309 "N-000163" +Ne 311 "N-000165" Po 570 0 $EndPAD $EndMODULE 1210 @@ -14559,7 +14564,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 329 "N-000186" +Ne 330 "N-000187" Po -570 0 $EndPAD $PAD @@ -14587,14 +14592,14 @@ $PAD Sh "1" R 355 984 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 315 "N-000170" +Ne 317 "N-000172" Po -570 0 $EndPAD $PAD Sh "2" R 355 984 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 319 "N-000174" +Ne 320 "N-000175" Po 570 0 $EndPAD $EndMODULE 1210 @@ -14615,7 +14620,7 @@ $PAD Sh "1" R 355 984 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 313 "N-000168" +Ne 315 "N-000170" Po -570 0 $EndPAD $PAD @@ -14643,7 +14648,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 322 "N-000177" +Ne 326 "N-000181" Po -176 0 $EndPAD $PAD @@ -14671,7 +14676,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 331 "N-000201" +Ne 318 "N-000173" Po -176 0 $EndPAD $PAD @@ -14727,7 +14732,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 332 "N-000202" +Ne 332 "N-000197" Po -176 0 $EndPAD $PAD @@ -14755,7 +14760,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 333 "N-000203" +Ne 333 "N-000198" Po -176 0 $EndPAD $PAD @@ -14783,7 +14788,7 @@ $PAD Sh "1" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 322 "N-000177" +Ne 326 "N-000181" Po -373 0 $EndPAD $PAD @@ -14839,7 +14844,7 @@ $PAD Sh "1" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 333 "N-000203" +Ne 333 "N-000198" Po -373 0 $EndPAD $PAD @@ -14924,14 +14929,14 @@ $PAD Sh "4" R 110 335 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 322 "N-000177" +Ne 326 "N-000181" Po -98 -678 $EndPAD $PAD Sh "14" R 110 335 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 332 "N-000202" +Ne 332 "N-000197" Po 98 678 $EndPAD $PAD @@ -15008,7 +15013,7 @@ $PAD Sh "10" R 335 110 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 331 "N-000201" +Ne 318 "N-000173" Po 875 295 $EndPAD $EndMODULE PVQFN-N20 @@ -15020,7 +15025,7 @@ AR /4C69ED5F/4D13F1A3 Op 0 0 0 At SMD T0 0 -150 200 200 900 40 N V 25 N"C157" -T1 0 150 200 200 900 40 N I 25 N"CAP" +T1 0 150 200 200 900 40 N I 25 N"10uF" DS -561 305 -561 -305 50 21 DS -561 -305 561 -305 50 21 DS 561 -305 561 305 50 21 @@ -15048,7 +15053,7 @@ AR /4C69ED5F/4D13FEB6 Op 0 0 0 At SMD T0 0 -150 200 200 0 40 N V 25 N"C159" -T1 0 150 200 200 0 40 N I 25 N"22uF" +T1 0 150 200 200 0 40 N I 25 N"10uF" DS -561 305 -561 -305 50 21 DS -561 -305 561 -305 50 21 DS 561 -305 561 305 50 21 @@ -15104,7 +15109,7 @@ AR /4C69ED5F/4D140643 Op 0 0 0 At SMD T0 0 150 200 200 900 40 M V 20 N"C158" -T1 0 -150 200 200 900 40 M I 20 N"22uF" +T1 0 -150 200 200 900 40 M I 20 N"10uF" DS -561 -305 -561 305 50 20 DS -561 305 561 305 50 20 DS 561 305 561 -305 50 20 @@ -15113,7 +15118,7 @@ $PAD Sh "1" R 275 510 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 319 "N-000174" +Ne 320 "N-000175" Po -373 0 $EndPAD $PAD @@ -15124,6 +15129,79 @@ Ne 292 "GND" Po 373 0 $EndPAD $EndMODULE 0805 +$MODULE 0402 +Po 67874 10882 0 15 4D1A6D35 4D1DF730 ~~ +Li 0402 +Sc 4D1DF730 +AR /4C69ED5F/4D1DF629 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"C180" +T1 0 150 200 200 0 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 337 "Vin" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 292 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE PJ-CUI-TH +Po 65976 11280 1800 15 4D1DF759 4D1DF74D ~~ +Li PJ-CUI-TH +Sc 4D1DF74D +AR /4C69ED5F/4D1DF550 +Op 0 0 0 +T0 1519 -1202 600 600 1800 120 N V 21 N"J8" +T1 2500 0 600 600 1800 120 N V 21 N"PJ" +DS 984 591 984 3346 59 21 +DS 984 3346 -984 3346 59 21 +DS -984 3346 -984 -984 59 21 +DS -984 -984 -591 -984 59 21 +DS 591 -984 984 -984 59 21 +DS 984 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-De 0 0 288 0 0 -Po 0 58327 27039 58327 28961 59 -1 -De 0 0 288 0 0 -Po 0 58069 26781 58327 27039 59 -1 -De 0 0 288 0 0 Po 0 59615 30639 59615 30653 59 -1 -De 15 0 289 0 800 +De 15 0 288 0 800 Po 0 57134 28456 58654 29976 59 -1 -De 0 0 289 0 0 +De 0 0 288 0 0 Po 0 57134 28456 57134 27763 59 -1 -De 0 0 289 0 400 +De 0 0 288 0 400 Po 0 58937 30259 58654 29976 59 -1 -De 0 0 289 0 0 +De 0 0 288 0 0 Po 0 58937 30331 58937 30259 59 -1 -De 0 0 289 0 0 +De 0 0 288 0 0 Po 0 59445 30839 58937 30331 59 -1 -De 0 0 289 0 0 +De 0 0 288 0 0 Po 0 59457 30839 59445 30839 59 -1 -De 0 0 289 0 0 +De 0 0 288 0 0 Po 0 59437 30823 59457 30839 59 -1 -De 0 0 289 0 0 +De 0 0 288 0 0 Po 3 59437 30823 59437 30823 157 -1 -De 15 1 289 0 0 +De 15 1 288 0 0 Po 0 59465 30803 59437 30823 59 -1 -De 15 0 289 0 0 +De 15 0 288 0 0 Po 0 59615 30653 59465 30803 59 -1 +De 15 0 288 0 0 +Po 0 57724 27763 57724 28530 59 -1 +De 0 0 289 0 800 +Po 0 60395 30639 60402 30639 59 -1 +De 15 0 289 0 400 +Po 0 60236 30480 60395 30639 59 -1 De 15 0 289 0 0 +Po 3 60236 30480 60236 30480 157 -1 +De 15 1 289 0 0 +Po 0 59949 30193 60236 30480 59 -1 +De 0 0 289 0 0 +Po 0 59949 30074 59949 30193 59 -1 +De 0 0 289 0 0 +Po 0 59508 29633 59949 30074 59 -1 +De 0 0 289 0 0 +Po 0 58827 29633 59508 29633 59 -1 +De 0 0 289 0 0 +Po 0 57724 28530 58827 29633 59 -1 +De 0 0 289 0 0 Po 0 58862 14434 59691 14434 157 -1 De 15 0 290 0 800 Po 0 59691 14434 60278 13847 157 -1 @@ -24759,13 +24837,13 @@ Po 3 48967 28159 48967 28159 157 -1 De 15 1 292 0 0 Po 0 48970 28156 48967 28159 79 -1 De 15 0 292 0 0 -Po 0 48889 24124 48074 23309 39 -1 -De 0 0 293 0 800 -Po 0 48074 23309 48074 22723 39 -1 -De 0 0 293 0 400 Po 0 50207 24130 50207 23890 39 -1 -De 0 0 294 0 800 +De 0 0 293 0 800 Po 0 50207 23890 51374 22723 39 -1 +De 0 0 293 0 400 +Po 0 48889 24124 48074 23309 39 -1 +De 0 0 294 0 800 +Po 0 48074 23309 48074 22723 39 -1 De 0 0 294 0 400 Po 0 47062 25190 46708 25190 39 -1 De 15 0 295 0 800 @@ -25056,7 +25134,7 @@ ZLayer 4 ZAux 47 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 57465 32756 0 ZCorner 57465 32441 0 ZCorner 57807 32441 0 @@ -27876,7 +27954,7 @@ ZLayer 4 ZAux 61 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 50610 40110 0 ZCorner 51756 37996 0 ZCorner 51843 37949 0 @@ -33852,7 +33930,7 @@ ZLayer 1 ZAux 16 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 66094 41240 0 ZCorner 66339 30043 0 ZCorner 66339 29488 0 @@ -42910,7 +42988,7 @@ ZLayer 2 ZAux 9 F ZClearance 59 T ZMinThickness 59 -ZOptions 0 16 F 79 79 +ZOptions 0 16 S 79 79 ZCorner 58146 36236 0 ZCorner 58146 33566 0 ZCorner 63350 28362 0 @@ -44183,7 +44261,7 @@ ZLayer 4 ZAux 31 F ZClearance 59 T ZMinThickness 59 -ZOptions 1 16 F 79 79 +ZOptions 1 16 S 79 79 ZCorner 65760 42028 0 ZCorner 63937 40205 0 ZCorner 60787 40205 0 @@ -45319,7 +45397,7 @@ ZLayer 15 ZAux 6 E ZClearance 98 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 65205 16941 0 ZCorner 65205 13362 0 ZCorner 58594 13362 0 @@ -45931,7 +46009,7 @@ ZLayer 15 ZAux 12 E ZClearance 98 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 58630 21457 0 ZCorner 58630 18008 0 ZCorner 59331 17307 0 @@ -46747,7 +46825,7 @@ ZLayer 0 ZAux 12 E ZClearance 98 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 58634 21461 0 ZCorner 58634 18012 0 ZCorner 59331 17315 0 @@ -47475,7 +47553,7 @@ ZLayer 0 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 54925 19335 0 ZCorner 54925 18299 0 ZCorner 53984 17358 0 @@ -47948,7 +48026,7 @@ ZLayer 15 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 46189 19343 0 ZCorner 54929 19335 0 ZCorner 54929 18299 0 @@ -48453,7 +48531,7 @@ ZLayer 1 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 46185 19339 0 ZCorner 54929 19335 0 ZCorner 54929 18303 0 @@ -48908,7 +48986,7 @@ ZLayer 4 ZAux 9 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 54925 19339 0 ZCorner 54925 18299 0 ZCorner 53984 17358 0 @@ -49364,7 +49442,7 @@ ZLayer 2 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 54929 19335 0 ZCorner 54929 18295 0 ZCorner 53988 17354 0 @@ -49819,7 +49897,7 @@ ZLayer 3 ZAux 8 E ZClearance 157 T ZMinThickness 100 -ZOptions 1 32 F 39 197 +ZOptions 1 32 S 39 197 ZCorner 46185 19339 0 ZCorner 54929 19335 0 ZCorner 54929 18291 0 diff --git a/xue-rnc/xue-rnc.cmp b/xue-rnc/xue-rnc.cmp index 0071a83..c6459ee 100644 --- a/xue-rnc/xue-rnc.cmp +++ b/xue-rnc/xue-rnc.cmp @@ -1,4 +1,4 @@ -Cmp-Mod V01 Genere par PcbNew le Wed 29 Dec 2010 01:08:56 PM COT +Cmp-Mod V01 Created by CvPCB (2010-10-01 BZR 2513)-testing date = Fri 31 Dec 2010 10:30:09 AM COT BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; @@ -742,6 +742,13 @@ ValeurCmp = 100nF; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4D1DF629; +Reference = C180; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + BeginCmp TimeStamp = /4C69ED5F/4D160B09; Reference = D1; @@ -784,6 +791,13 @@ ValeurCmp = ZX62D-B-5P8; IdModule = ZX62D-B-5P8; EndCmp +BeginCmp +TimeStamp = /4C69ED5F/4D1DF550; +Reference = J8; +ValeurCmp = PJ; +IdModule = PJ-CUI-TH; +EndCmp + BeginCmp TimeStamp = /4C4320F3/4C5D80F3; Reference = L1; diff --git a/xue-rnc/xue-rnc.net b/xue-rnc/xue-rnc.net index 195e935..f657b1a 100644 --- a/xue-rnc/xue-rnc.net +++ b/xue-rnc/xue-rnc.net @@ -1,4 +1,4 @@ -# EESchema Netlist Version 1.1 created Wed 29 Dec 2010 01:05:45 PM COT +# EESchema Netlist Version 1.1 created Fri 31 Dec 2010 10:30:09 AM COT ( ( /4C4320F3/4C5D7F9F 0603 C1 1uF ( 1 +3.3V ) @@ -337,7 +337,7 @@ ( 2 GND ) ) ( /4C69ED5F/4D140643 0805 C158 10uF - ( 1 N-000174 ) + ( 1 N-000175 ) ( 2 GND ) ) ( /4C69ED5F/4D13FEB6 0805 C159 10uF @@ -349,11 +349,11 @@ ( 2 GND ) ) ( /4C69ED5F/4D13F557 0402 C161 CAP - ( 1 N-000165 ) + ( 1 N-000167 ) ( 2 GND ) ) ( /4C69ED5F/4D13FE2C 0402 C162 560pF - ( 1 N-000172 ) + ( 1 N-000162 ) ( 2 GND ) ) ( /4C69ED5F/4D13FCCF 0402 C163 CAP @@ -361,55 +361,55 @@ ( 2 N-000160 ) ) ( /4C69ED5F/4D140659 0402 C164 39pF - ( 1 N-000168 ) - ( 2 N-000175 ) + ( 1 N-000170 ) + ( 2 N-000176 ) ) ( /4C69ED5F/4D1408E4 0402 C165 100nF - ( 1 N-000176 ) + ( 1 N-000177 ) ( 2 GND ) ) ( /4C69ED5F/4D13FBBF 0402 C166 CAP - ( 1 N-000161 ) - ( 2 N-000163 ) + ( 1 N-000164 ) + ( 2 N-000165 ) ) ( /4C69ED5F/4D140163 0805 C167 10uF - ( 1 N-000190 ) + ( 1 N-000191 ) ( 2 GND ) ) ( /4C69ED5F/4D13FF30 1210 C168 CAP - ( 1 N-000181 ) + ( 1 N-000182 ) ( 2 GND ) ) ( /4C69ED5F/4D140162 0402 C169 100nF - ( 1 N-000190 ) + ( 1 N-000191 ) ( 2 GND ) ) ( /4C69ED5F/4D14063A 1210 C170 68uF - ( 1 N-000168 ) + ( 1 N-000170 ) ( 2 GND ) ) ( /4C69ED5F/4D13FF2F 0402 C171 100nF - ( 1 N-000181 ) + ( 1 N-000182 ) ( 2 GND ) ) ( /4C69ED5F/4D13FB8D 1210 C172 22uF - ( 1 N-000186 ) + ( 1 N-000187 ) ( 2 GND ) ) ( /4C69ED5F/4D14063B 0402 C173 100nF - ( 1 N-000168 ) + ( 1 N-000170 ) ( 2 GND ) ) ( /4C69ED5F/4D13FEFF 0402 C174 100nF - ( 1 N-000186 ) + ( 1 N-000187 ) ( 2 GND ) ) ( /4C69ED5F/4D1A0FF6 0805 C175 10uF - ( 1 N-000177 ) + ( 1 N-000181 ) ( 2 GND ) ) ( /4C69ED5F/4D1A0FF7 0402 C176 100nF - ( 1 N-000177 ) + ( 1 N-000181 ) ( 2 GND ) ) ( /4C69ED5F/4D1A111E 0805 C177 10uF @@ -417,30 +417,34 @@ ( 2 GND ) ) ( /4C69ED5F/4D1A14C5 0805 C178 10uF - ( 1 N-000203 ) + ( 1 N-000198 ) ( 2 GND ) ) ( /4C69ED5F/4D1A14C4 0402 C179 100nF - ( 1 N-000203 ) + ( 1 N-000198 ) + ( 2 GND ) + ) + ( /4C69ED5F/4D1DF629 0402 C180 100nF + ( 1 Vin ) ( 2 GND ) ) ( /4C69ED5F/4D160B09 0805 D1 MBRS140T3 - ( 1 N-000170 ) - ( 2 N-000168 ) + ( 1 N-000172 ) + ( 2 N-000170 ) ) ( /4C5F1EDC/4C5F2B55 1210 F1 MICROSMD075F ( 1 N-000150 ) ( 2 +5V ) ) ( /4C4227FE/4B76F5E2 MICROSD-500901 J1 MICROSD - ( 1 /flash/SD_DAT2 ) - ( 2 /fpga1/SD_DAT3 ) + ( 1 /fpga1/SD_DAT2 ) + ( 2 /flash/SD_DAT3 ) ( 3 /fpga1/SD_CMD ) ( 4 +3.3V ) - ( 5 /fpga1/SD_CLK ) + ( 5 /flash/SD_CLK ) ( 6 GND ) ( 7 /fpga1/SD_DAT0 ) - ( 8 /fpga1/SD_DAT1 ) + ( 8 /flash/SD_DAT1 ) ( CASE GND ) ( CD ? ) ( COM GND ) @@ -457,7 +461,7 @@ ( 9 +3.3V ) ( 10 N-000121 ) ( 11 +3.3V ) - ( 12 N-000120 ) + ( 12 N-000124 ) ( 13 /ether/MAG_SHIELD ) ( 14 /ether/MAG_SHIELD ) ) @@ -482,6 +486,11 @@ ( 8 /usb/USB_CASE_DEV ) ( 9 /usb/USB_CASE_DEV ) ) + ( /4C69ED5F/4D1DF550 PJ-CUI-TH J8 PJ + ( 1 Vin ) + ( 2 GND ) + ( 3 GND ) + ) ( /4C4320F3/4C5D80F3 0402 L1 FB ( 1 +1.8V ) ( 2 /ether/ETH_A1.8V ) @@ -507,68 +516,68 @@ ( 2 GND ) ) ( /4C69ED5F/4D1405EB 1210 L8 6.8uH - ( 1 N-000170 ) - ( 2 N-000174 ) + ( 1 N-000172 ) + ( 2 N-000175 ) ) ( /4C69ED5F/4D140153 0805 L9 2.2uF - ( 1 N-000190 ) - ( 2 N-000173 ) + ( 1 N-000191 ) + ( 2 N-000174 ) ) ( /4C69ED5F/4D13F22A 1210 L10 INDUCTOR - ( 1 N-000181 ) - ( 2 N-000166 ) + ( 1 N-000182 ) + ( 2 N-000168 ) ) ( /4C69ED5F/4D13FB89 1210 L11 2.2uH - ( 1 N-000186 ) - ( 2 N-000163 ) + ( 1 N-000187 ) + ( 2 N-000165 ) ) ( /4CB0D95D/4CBAFE50 header25x2_smd_2mm P1 CONN_25X2 ( 1 /fpga1/FPGA_BANK0_IO_8 ) - ( 2 /expansion/FPGA_BANK0_IO_1 ) + ( 2 /fpga1/FPGA_BANK0_IO_1 ) ( 3 GND ) ( 4 /expansion/FPGA_BANK0_IO_9 ) ( 5 VCCO2 ) - ( 6 /fpga1/FPGA_BANK0_IO_14 ) - ( 7 /expansion/FPGA_BANK0_IO_10 ) + ( 6 /expansion/FPGA_BANK0_IO_14 ) + ( 7 /fpga1/FPGA_BANK0_IO_10 ) ( 8 /expansion/FPGA_BANK0_IO_15 ) ( 9 /expansion/FPGA_BANK0_IO_11 ) ( 10 /expansion/FPGA_BANK0_IO_3 ) ( 11 /expansion/FPGA_BANK0_IO_5 ) ( 12 /fpga1/FPGA_BANK0_IO_18 ) - ( 13 /expansion/FPGA_BANK0_IO_17 ) - ( 14 /expansion/FPGA_BANK0_IO_21 ) - ( 15 /expansion/FPGA_BANK0_IO_20 ) - ( 16 /fpga1/FPGA_BANK0_IO_24 ) - ( 17 /fpga1/FPGA_BANK0_IO_28 ) - ( 18 /expansion/FPGA_BANK0_IO_29 ) - ( 19 /fpga1/FPGA_BANK0_IO_22 ) + ( 13 /fpga1/FPGA_BANK0_IO_17 ) + ( 14 /fpga1/FPGA_BANK0_IO_21 ) + ( 15 /fpga1/FPGA_BANK0_IO_20 ) + ( 16 /expansion/FPGA_BANK0_IO_24 ) + ( 17 /expansion/FPGA_BANK0_IO_28 ) + ( 18 /fpga1/FPGA_BANK0_IO_29 ) + ( 19 /expansion/FPGA_BANK0_IO_22 ) ( 20 /fpga1/FPGA_BANK0_IO_30 ) ( 21 /fpga1/FPGA_BANK0_IO_27 ) ( 22 /fpga1/FPGA_BANK0_IO_25 ) ( 23 /expansion/FPGA_BANK0_IO_39 ) - ( 24 /fpga1/FPGA_BANK0_IO_33 ) - ( 25 /expansion/FPGA_BANK0_IO_2 ) - ( 26 /expansion/FPGA_BANK0_IO_32 ) + ( 24 /expansion/FPGA_BANK0_IO_33 ) + ( 25 /fpga1/FPGA_BANK0_IO_2 ) + ( 26 /fpga1/FPGA_BANK0_IO_32 ) ( 27 /expansion/FPGA_BANK0_IO_7 ) - ( 28 /expansion/FPGA_BANK0_IO_6 ) - ( 29 /fpga1/FPGA_BANK0_IO_12 ) - ( 30 /fpga1/FPGA_BANK0_IO_36 ) - ( 31 /fpga1/FPGA_BANK0_IO_44 ) + ( 28 /fpga1/FPGA_BANK0_IO_6 ) + ( 29 /expansion/FPGA_BANK0_IO_12 ) + ( 30 /expansion/FPGA_BANK0_IO_36 ) + ( 31 /expansion/FPGA_BANK0_IO_44 ) ( 32 /expansion/FPGA_BANK0_IO_40 ) ( 33 /expansion/FPGA_BANK0_IO_47 ) ( 34 /expansion/FPGA_BANK0_IO_43 ) - ( 35 /fpga1/FPGA_BANK0_IO_45 ) + ( 35 /expansion/FPGA_BANK0_IO_45 ) ( 36 /expansion/FPGA_BANK0_IO_46 ) ( 37 /fpga1/FPGA_BANK0_IO_52 ) - ( 38 /expansion/FPGA_BANK0_IO_50 ) + ( 38 /fpga1/FPGA_BANK0_IO_50 ) ( 39 /fpga1/FPGA_BANK0_IO_56 ) - ( 40 /fpga1/FPGA_BANK0_IO_48 ) - ( 41 /fpga1/FPGA_BANK0_IO_51 ) + ( 40 /expansion/FPGA_BANK0_IO_48 ) + ( 41 /expansion/FPGA_BANK0_IO_51 ) ( 42 /expansion/FPGA_BANK0_IO_34 ) - ( 43 /expansion/FPGA_BANK0_IO_54 ) + ( 43 /fpga1/FPGA_BANK0_IO_54 ) ( 44 /fpga1/FPGA_BANK0_IO_49 ) ( 45 /fpga1/FPGA_BANK0_IO_63 ) - ( 46 /fpga1/FPGA_BANK0_IO_62 ) + ( 46 /expansion/FPGA_BANK0_IO_62 ) ( 47 /fpga1/FPGA_BANK0_IO_53 ) ( 48 /fpga1/FPGA_BANK0_IO_57 ) ( 49 /fpga1/FPGA_BANK0_IO_58 ) @@ -579,7 +588,7 @@ ( 2 +3.3V ) ) ( /4C4320F3/4C5D7ECF 0402 R2 6.65K - ( 1 N-000125 ) + ( 1 N-000126 ) ( 2 GND ) ) ( /4C4320F3/4C5D7AFE 0402 R3 49.9 @@ -603,7 +612,7 @@ ( 2 /ether/ETH_LED0 ) ) ( /4C4320F3/4C5D71DB 0402 R8 220 - ( 1 N-000120 ) + ( 1 N-000124 ) ( 2 /ether/ETH_LED1 ) ) ( /4C4320F3/4C5D7DC4 0603 R9 1M @@ -640,7 +649,7 @@ ) ( /4C7BC2A2/4C69E7F8 0402 R17 33 ( 1 /fpga2/R_M1_CKE ) - ( 2 /fpga2/M1_CKE ) + ( 2 /sdram/M1_CKE ) ) ( /4C7BC2A2/4C69E7C2 0402 R18 33 ( 1 /fpga2/R_M1_UDM ) @@ -648,14 +657,14 @@ ) ( /4C7BC2A2/4C69E7DD 0402 R19 33 ( 1 /fpga2/R_M1_UDQS ) - ( 2 /fpga2/M1_UDQS ) + ( 2 /sdram/M1_UDQS ) ) ( /4C7BC2A2/4C69E92D 0402 R20 33 ( 1 /fpga2/R_M1_CS# ) ( 2 /fpga2/M1_CS# ) ) ( /4C7BC2A2/4C6B1B90 0402 R21 120 - ( 1 /fpga2/M0_CLK ) + ( 1 /sdram/M0_CLK ) ( 2 /sdram/M0_CLK# ) ) ( /4C7BC2A2/4C6B216D 0402 R22 33 @@ -664,7 +673,7 @@ ) ( /4C7BC2A2/4C6B216E 0402 R23 33 ( 1 /fpga2/R_M0_UDM ) - ( 2 /fpga2/M0_UDM ) + ( 2 /sdram/M0_UDM ) ) ( /4C7BC2A2/4C6B216B 0402 R24 33 ( 1 /fpga2/R_M0_CKE ) @@ -672,11 +681,11 @@ ) ( /4C7BC2B2/4C716877 0402 R29 4.7k ( 1 +3.3V ) - ( 2 N-000362 ) + ( 2 N-000363 ) ) ( /4C7BC2B2/4C7168DD 0402 R30 330 ( 1 +3.3V ) - ( 2 N-000365 ) + ( 2 N-000366 ) ) ( /4C5F1EDC/4C7D3075 0402 R46 15k ( 1 GND ) @@ -720,7 +729,7 @@ ) ( /4C7BC2A2/4CCF27A7 0402 R79 33 ( 1 /fpga2/R_M1_CAS# ) - ( 2 /sdram/M1_CAS# ) + ( 2 /fpga2/M1_CAS# ) ) ( /4C7BC2A2/4CCF27A9 0402 R80 33 ( 1 /fpga2/R_M1_WE# ) @@ -736,7 +745,7 @@ ) ( /4C7BC2A2/4CCF2733 0402 R83 33 ( 1 /fpga2/R_M0_CAS# ) - ( 2 /fpga2/M0_CAS# ) + ( 2 /sdram/M0_CAS# ) ) ( /4C7BC2A2/4CCF272F 0402 R84 33 ( 1 /fpga2/R_M0_WE# ) @@ -748,58 +757,58 @@ ) ( /4C7BC2A2/4CCF2730 0402 R86 33 ( 1 /fpga2/R_M0_LDQS ) - ( 2 /fpga2/M0_LDQS ) + ( 2 /sdram/M0_LDQS ) ) ( /4C69ED5F/4D13F539 0402 R87 R ( 1 N-000158 ) - ( 2 N-000165 ) + ( 2 N-000167 ) ) ( /4C69ED5F/4D13FE0D 0402 R88 12k - ( 1 N-000172 ) - ( 2 N-000184 ) + ( 1 N-000162 ) + ( 2 N-000185 ) ) ( /4C69ED5F/4D140604 0402 R89 50k_1% ( 1 GND ) - ( 2 N-000175 ) + ( 2 N-000176 ) ) ( /4C69ED5F/4D13FD6A 0402 R90 R ( 1 GND ) - ( 2 N-000171 ) + ( 2 N-000161 ) ) ( /4C69ED5F/4D13FB88 0402 R91 R - ( 1 N-000186 ) - ( 2 N-000171 ) + ( 1 N-000187 ) + ( 2 N-000161 ) ) ( /4C69ED5F/4D140650 0402 R92 150k_1% - ( 1 N-000175 ) - ( 2 N-000168 ) + ( 1 N-000176 ) + ( 2 N-000170 ) ) ( /4C69ED5F/4D13FC4E 0402 R93 R ( 1 N-000160 ) - ( 2 N-000162 ) + ( 2 N-000163 ) ) ( /4C69ED5F/4D140603 0402 R94 200k - ( 1 N-000169 ) - ( 2 N-000176 ) + ( 1 N-000171 ) + ( 2 N-000177 ) ) ( /4C69ED5F/4D13F52F 0402 R95 R ( 1 N-000159 ) ( 2 GND ) ) ( /4C69ED5F/4D13F523 0402 R96 R - ( 1 N-000181 ) + ( 1 N-000182 ) ( 2 N-000159 ) ) ( /4C69ED5F/4D140674 0402 R97 500 - ( 1 N-000176 ) - ( 2 N-000168 ) + ( 1 N-000177 ) + ( 2 N-000170 ) ) ( /4C69ED5F/4D1A13AE 0402 R98 R - ( 1 N-000202 ) + ( 1 N-000197 ) ( 2 GND ) ) ( /4C69ED5F/4D1A1278 0402 R99 R - ( 1 N-000201 ) + ( 1 N-000173 ) ( 2 GND ) ) ( /4C69ED5F/4D1A1280 0402 R100 R @@ -812,8 +821,8 @@ ( 3 /fpga2/R_M1_A2 ) ( 4 /fpga2/R_M1_A3 ) ( 5 /sdram/M1_A3 ) - ( 6 /fpga2/M1_A2 ) - ( 7 /sdram/M1_A1 ) + ( 6 /sdram/M1_A2 ) + ( 7 /fpga2/M1_A1 ) ( 8 /fpga2/M1_A0 ) ) ( /4C7BC2A2/4C69CEE8 R_PACK4-0402 RP2 R_PACK4 @@ -824,7 +833,7 @@ ( 5 /sdram/M1_A10 ) ( 6 /fpga2/M1_BA1 ) ( 7 /sdram/M1_BA0 ) - ( 8 /sdram/M1_RAS# ) + ( 8 /fpga2/M1_RAS# ) ) ( /4C7BC2A2/4C69D3A3 R_PACK4-0402 RP4 R_PACK4 ( 1 /fpga2/R_M1_DQ4 ) @@ -832,8 +841,8 @@ ( 3 /fpga2/R_M1_DQ6 ) ( 4 /fpga2/R_M1_DQ7 ) ( 5 /fpga2/M1_DQ7 ) - ( 6 /sdram/M1_DQ6 ) - ( 7 /sdram/M1_DQ5 ) + ( 6 /fpga2/M1_DQ6 ) + ( 7 /fpga2/M1_DQ5 ) ( 8 /fpga2/M1_DQ4 ) ) ( /4C7BC2A2/4C69D3A9 R_PACK4-0402 RP5 R_PACK4 @@ -842,14 +851,14 @@ ( 3 /fpga2/R_M1_DQ2 ) ( 4 /fpga2/R_M1_DQ3 ) ( 5 /fpga2/M1_DQ3 ) - ( 6 /fpga2/M1_DQ2 ) + ( 6 /sdram/M1_DQ2 ) ( 7 /sdram/M1_DQ1 ) ( 8 /fpga2/M1_DQ0 ) ) ( /4C7BC2A2/4C69DA8A R_PACK4-0402 RP6 R_PACK4 - ( 1 /fpga2/M1_A7 ) + ( 1 /sdram/M1_A7 ) ( 2 /fpga2/M1_A6 ) - ( 3 /sdram/M1_A5 ) + ( 3 /fpga2/M1_A5 ) ( 4 /sdram/M1_A4 ) ( 5 /fpga2/R_M1_A4 ) ( 6 /fpga2/R_M1_A5 ) @@ -857,9 +866,9 @@ ( 8 /fpga2/R_M1_A7 ) ) ( /4C7BC2A2/4C69DC05 R_PACK4-0402 RP7 R_PACK4 - ( 1 /sdram/M1_A12 ) - ( 2 /fpga2/M1_A11 ) - ( 3 /fpga2/M1_A9 ) + ( 1 /fpga2/M1_A12 ) + ( 2 /sdram/M1_A11 ) + ( 3 /sdram/M1_A9 ) ( 4 /fpga2/M1_A8 ) ( 5 /fpga2/R_M1_A8 ) ( 6 /fpga2/R_M1_A9 ) @@ -869,16 +878,16 @@ ( /4C7BC2A2/4C69E299 R_PACK4-0402 RP8 R_PACK4 ( 1 /fpga2/M1_DQ15 ) ( 2 /fpga2/M1_DQ14 ) - ( 3 /sdram/M1_DQ13 ) - ( 4 /sdram/M1_DQ12 ) + ( 3 /fpga2/M1_DQ13 ) + ( 4 /fpga2/M1_DQ12 ) ( 5 /fpga2/R_M1_DQ12 ) ( 6 /fpga2/R_M1_DQ13 ) ( 7 /fpga2/R_M1_DQ14 ) ( 8 /fpga2/R_M1_DQ15 ) ) ( /4C7BC2A2/4C69E3A6 R_PACK4-0402 RP9 R_PACK4 - ( 1 /fpga2/M1_DQ11 ) - ( 2 /fpga2/M1_DQ10 ) + ( 1 /sdram/M1_DQ11 ) + ( 2 /sdram/M1_DQ10 ) ( 3 /fpga2/M1_DQ9 ) ( 4 /fpga2/M1_DQ8 ) ( 5 /fpga2/R_M1_DQ8 ) @@ -891,7 +900,7 @@ ( 2 /fpga2/R_M0_DQ13 ) ( 3 /fpga2/R_M0_DQ14 ) ( 4 /fpga2/R_M0_DQ15 ) - ( 5 /fpga2/M0_DQ15 ) + ( 5 /sdram/M0_DQ15 ) ( 6 /sdram/M0_DQ14 ) ( 7 /sdram/M0_DQ13 ) ( 8 /sdram/M0_DQ12 ) @@ -902,18 +911,18 @@ ( 3 /fpga2/R_M0_DQ10 ) ( 4 /fpga2/R_M0_DQ11 ) ( 5 /fpga2/M0_DQ11 ) - ( 6 /fpga2/M0_DQ10 ) + ( 6 /sdram/M0_DQ10 ) ( 7 /fpga2/M0_DQ9 ) - ( 8 /sdram/M0_DQ8 ) + ( 8 /fpga2/M0_DQ8 ) ) ( /4C7BC2A2/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 ( 1 /fpga2/R_M0_DQ4 ) ( 2 /fpga2/R_M0_DQ5 ) ( 3 /fpga2/R_M0_DQ6 ) ( 4 /fpga2/R_M0_DQ7 ) - ( 5 /fpga2/M0_DQ7 ) - ( 6 /fpga2/M0_DQ6 ) - ( 7 /sdram/M0_DQ5 ) + ( 5 /sdram/M0_DQ7 ) + ( 6 /sdram/M0_DQ6 ) + ( 7 /fpga2/M0_DQ5 ) ( 8 /sdram/M0_DQ4 ) ) ( /4C7BC2A2/4C69FCE7 R_PACK4-0402 RP13 R_PACK4 @@ -924,7 +933,7 @@ ( 5 /fpga2/M0_DQ3 ) ( 6 /fpga2/M0_DQ2 ) ( 7 /fpga2/M0_DQ1 ) - ( 8 /fpga2/M0_DQ0 ) + ( 8 /sdram/M0_DQ0 ) ) ( /4C7BC2A2/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 ( 1 /fpga2/R_M0_A0 ) @@ -943,7 +952,7 @@ ( 4 /fpga2/R_M0_A10 ) ( 5 /fpga2/M0_A10 ) ( 6 /sdram/M0_BA1 ) - ( 7 /fpga2/M0_BA0 ) + ( 7 /sdram/M0_BA0 ) ( 8 /sdram/M0_RAS# ) ) ( /4C7BC2A2/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 @@ -951,7 +960,7 @@ ( 2 /fpga2/R_M0_A6 ) ( 3 /fpga2/R_M0_A5 ) ( 4 /fpga2/R_M0_A4 ) - ( 5 /fpga2/M0_A4 ) + ( 5 /sdram/M0_A4 ) ( 6 /fpga2/M0_A5 ) ( 7 /sdram/M0_A6 ) ( 8 /fpga2/M0_A7 ) @@ -961,35 +970,35 @@ ( 2 /fpga2/R_M0_A11 ) ( 3 /fpga2/R_M0_A9 ) ( 4 /fpga2/R_M0_A8 ) - ( 5 /fpga2/M0_A8 ) + ( 5 /sdram/M0_A8 ) ( 6 /fpga2/M0_A9 ) - ( 7 /sdram/M0_A11 ) + ( 7 /fpga2/M0_A11 ) ( 8 /fpga2/M0_A12 ) ) ( /4C7BC2B2/4C431E53 FGG484BGA-P10 U1 XC6SLX45FGG484 ( A1 GND ) ( A2 ? ) ( A3 GND ) - ( A4 /ether/ETH_CLK ) + ( A4 /fpga1/ETH_CLK ) ( A5 /fpga1/ETH_RXD1 ) ( A6 /ether/ETH_RXDV ) - ( A7 /ether/ETH_RXC ) - ( A8 /ether/ETH_TXD3 ) + ( A7 /fpga1/ETH_RXC ) + ( A8 /fpga1/ETH_TXD3 ) ( A9 /ether/ETH_COL ) ( A10 /ether/ETH_INT ) ( A11 /fpga1/NF_D6 ) ( A12 /fpga1/NF_D4 ) - ( A13 /fpga1/NF_D2 ) - ( A14 /flash/NF_ALE ) - ( A15 /fpga1/NF_RNB ) - ( A16 /flash/SD_DAT2 ) - ( A17 /fpga1/SD_CLK ) + ( A13 /flash/NF_D2 ) + ( A14 /fpga1/NF_ALE ) + ( A15 /flash/NF_RNB ) + ( A16 /fpga1/SD_DAT2 ) + ( A17 /flash/SD_CLK ) ( A18 /fpga1/SD_DAT0 ) ( A19 ? ) ( A20 /fpga2/USBD_RCV ) - ( A21 /usb/USBD_OE_N ) + ( A21 /fpga2/USBD_OE_N ) ( A22 GND ) - ( AA1 N-000362 ) + ( AA1 N-000363 ) ( AA2 ? ) ( AA3 VCCO2 ) ( AA4 ? ) @@ -1002,9 +1011,9 @@ ( AA11 VCCO2 ) ( AA12 ? ) ( AA13 GND ) - ( AA14 /fpga1/FPGA_BANK0_IO_22 ) + ( AA14 /expansion/FPGA_BANK0_IO_22 ) ( AA15 VCCO2 ) - ( AA16 /fpga1/FPGA_BANK0_IO_28 ) + ( AA16 /expansion/FPGA_BANK0_IO_28 ) ( AA17 GND ) ( AA18 /fpga1/FPGA_BANK0_IO_18 ) ( AA19 VCCO2 ) @@ -1025,9 +1034,9 @@ ( AB12 ? ) ( AB13 /expansion/FPGA_BANK0_IO_39 ) ( AB14 ? ) - ( AB15 /fpga1/FPGA_BANK0_IO_33 ) - ( AB16 /expansion/FPGA_BANK0_IO_29 ) - ( AB17 /expansion/FPGA_BANK0_IO_21 ) + ( AB15 /expansion/FPGA_BANK0_IO_33 ) + ( AB16 /fpga1/FPGA_BANK0_IO_29 ) + ( AB17 /fpga1/FPGA_BANK0_IO_21 ) ( AB18 ? ) ( AB19 ? ) ( AB20 /fpga1/PROG_MISO0 ) @@ -1040,21 +1049,21 @@ ( B5 GND ) ( B6 /fpga1/ETH_RXD0 ) ( B7 +3.3V ) - ( B8 /fpga1/ETH_RXER ) + ( B8 /ether/ETH_RXER ) ( B9 GND ) - ( B10 /ether/ETH_CRS ) + ( B10 /fpga1/ETH_CRS ) ( B11 +3.3V ) - ( B12 /flash/NF_D3 ) + ( B12 /fpga1/NF_D3 ) ( B13 GND ) - ( B14 /flash/NF_CLE ) + ( B14 /fpga1/NF_CLE ) ( B15 +3.3V ) - ( B16 /fpga1/SD_DAT3 ) + ( B16 /flash/SD_DAT3 ) ( B17 GND ) - ( B18 /fpga1/SD_DAT1 ) + ( B18 /flash/SD_DAT1 ) ( B19 +3.3V ) ( B20 /usb/USBD_SPD ) ( B21 /fpga2/USBD_VP ) - ( B22 /fpga2/USBD_VM ) + ( B22 /usb/USBD_VM ) ( C1 /fpga2/R_M0_A11 ) ( C2 +2.5V ) ( C3 ? ) @@ -1064,12 +1073,12 @@ ( C7 /fpga1/ETH_RESET_N ) ( C8 /fpga1/ETH_TXC ) ( C9 /fpga1/ETH_TXD1 ) - ( C10 /fpga1/ETH_TXD2 ) - ( C11 /flash/NF_D5 ) - ( C12 /flash/NF_D0 ) + ( C10 /ether/ETH_TXD2 ) + ( C11 /fpga1/NF_D5 ) + ( C12 /fpga1/NF_D0 ) ( C13 ? ) - ( C14 /fpga1/NF_WE_N ) - ( C15 /flash/NF_RE_N ) + ( C14 /flash/NF_WE_N ) + ( C15 /fpga1/NF_RE_N ) ( C16 /fpga1/SD_CMD ) ( C17 ? ) ( C18 ? ) @@ -1083,15 +1092,15 @@ ( D4 GND ) ( D5 ? ) ( D6 /ether/ETH_MDIO ) - ( D7 /ether/ETH_MDC ) + ( D7 /fpga1/ETH_MDC ) ( D8 /ether/ETH_TXER ) ( D9 /fpga1/ETH_TXEN ) - ( D10 /ether/ETH_TXD0 ) - ( D11 /flash/NF_D7 ) + ( D10 /fpga1/ETH_TXD0 ) + ( D11 /fpga1/NF_D7 ) ( D12 ? ) ( D13 ? ) - ( D14 /flash/NF_D1 ) - ( D15 /flash/NF_CS1_N ) + ( D14 /fpga1/NF_D1 ) + ( D15 /fpga1/NF_CS1_N ) ( D16 +2.5V ) ( D17 ? ) ( D18 GND ) @@ -1168,7 +1177,7 @@ ( H1 /fpga2/R_M0_A1 ) ( H2 /fpga2/R_M0_A0 ) ( H3 /sdram/M0_CLK# ) - ( H4 /fpga2/M0_CLK ) + ( H4 /sdram/M0_CLK ) ( H5 /fpga2/R_M0_A2 ) ( H6 /fpga2/R_M0_A7 ) ( H7 GND ) @@ -1334,7 +1343,7 @@ ( R13 ? ) ( R14 +1.2V ) ( R15 ? ) - ( R16 /fpga1/FPGA_BANK0_IO_12 ) + ( R16 /expansion/FPGA_BANK0_IO_12 ) ( R17 ? ) ( R18 GND ) ( R19 ? ) @@ -1354,11 +1363,11 @@ ( T11 ? ) ( T12 /expansion/FPGA_BANK0_IO_34 ) ( T13 VCCO2 ) - ( T14 /fpga1/FPGA_BANK0_IO_36 ) + ( T14 /expansion/FPGA_BANK0_IO_36 ) ( T15 /expansion/FPGA_BANK0_IO_7 ) - ( T16 /expansion/FPGA_BANK0_IO_6 ) - ( T17 /expansion/FPGA_BANK0_IO_2 ) - ( T18 /expansion/FPGA_BANK0_IO_1 ) + ( T16 /fpga1/FPGA_BANK0_IO_6 ) + ( T17 /fpga1/FPGA_BANK0_IO_2 ) + ( T18 /fpga1/FPGA_BANK0_IO_1 ) ( T19 ? ) ( T20 ? ) ( T21 /fpga2/R_M1_UDQS ) @@ -1368,10 +1377,10 @@ ( U3 /fpga2/R_M0_DQ12 ) ( U4 ? ) ( U5 +2.5V ) - ( U6 /fpga1/FPGA_BANK0_IO_62 ) + ( U6 /expansion/FPGA_BANK0_IO_62 ) ( U7 GND ) - ( U8 /expansion/FPGA_BANK0_IO_54 ) - ( U9 /fpga1/FPGA_BANK0_IO_51 ) + ( U8 /fpga1/FPGA_BANK0_IO_54 ) + ( U9 /expansion/FPGA_BANK0_IO_51 ) ( U10 /fpga1/FPGA_BANK0_IO_56 ) ( U11 +2.5V ) ( U12 ? ) @@ -1399,11 +1408,11 @@ ( V12 VCCO2 ) ( V13 ? ) ( V14 GND ) - ( V15 /expansion/FPGA_BANK0_IO_17 ) + ( V15 /fpga1/FPGA_BANK0_IO_17 ) ( V16 VCCO2 ) - ( V17 /fpga1/FPGA_BANK0_IO_14 ) + ( V17 /expansion/FPGA_BANK0_IO_14 ) ( V18 /expansion/FPGA_BANK0_IO_11 ) - ( V19 /expansion/FPGA_BANK0_IO_10 ) + ( V19 /fpga1/FPGA_BANK0_IO_10 ) ( V20 ? ) ( V21 /fpga2/R_M1_DQ14 ) ( V22 /fpga2/R_M1_DQ15 ) @@ -1414,10 +1423,10 @@ ( W5 VCCO2 ) ( W6 /fpga1/FPGA_BANK0_IO_57 ) ( W7 GND ) - ( W8 /fpga1/FPGA_BANK0_IO_48 ) - ( W9 /expansion/FPGA_BANK0_IO_50 ) + ( W8 /expansion/FPGA_BANK0_IO_48 ) + ( W9 /fpga1/FPGA_BANK0_IO_50 ) ( W10 /expansion/FPGA_BANK0_IO_46 ) - ( W11 /fpga1/FPGA_BANK0_IO_44 ) + ( W11 /expansion/FPGA_BANK0_IO_44 ) ( W12 ? ) ( W13 /fpga1/FPGA_BANK0_IO_27 ) ( W14 /fpga1/FPGA_BANK0_IO_30 ) @@ -1437,24 +1446,24 @@ ( Y6 ? ) ( Y7 ? ) ( Y8 ? ) - ( Y9 /fpga1/FPGA_BANK0_IO_45 ) + ( Y9 /expansion/FPGA_BANK0_IO_45 ) ( Y10 /expansion/FPGA_BANK0_IO_47 ) ( Y11 /expansion/FPGA_BANK0_IO_40 ) ( Y12 ? ) ( Y13 /expansion/FPGA_BANK0_IO_38 ) ( Y14 ? ) - ( Y15 /expansion/FPGA_BANK0_IO_32 ) - ( Y16 /fpga1/FPGA_BANK0_IO_24 ) - ( Y17 /expansion/FPGA_BANK0_IO_20 ) + ( Y15 /fpga1/FPGA_BANK0_IO_32 ) + ( Y16 /expansion/FPGA_BANK0_IO_24 ) + ( Y17 /fpga1/FPGA_BANK0_IO_20 ) ( Y18 /expansion/FPGA_BANK0_IO_5 ) ( Y19 /expansion/FPGA_BANK0_IO_3 ) ( Y20 +3.3V ) ( Y21 ? ) - ( Y22 N-000365 ) + ( Y22 N-000366 ) ) ( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG ( 1 +2.5V ) - ( 2 /fpga2/M0_DQ0 ) + ( 2 /sdram/M0_DQ0 ) ( 3 +2.5V ) ( 4 /fpga2/M0_DQ1 ) ( 5 /fpga2/M0_DQ2 ) @@ -1462,23 +1471,23 @@ ( 7 /fpga2/M0_DQ3 ) ( 8 /sdram/M0_DQ4 ) ( 9 +2.5V ) - ( 10 /sdram/M0_DQ5 ) - ( 11 /fpga2/M0_DQ6 ) + ( 10 /fpga2/M0_DQ5 ) + ( 11 /sdram/M0_DQ6 ) ( 12 GND ) - ( 13 /fpga2/M0_DQ7 ) + ( 13 /sdram/M0_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /fpga2/M0_LDQS ) + ( 16 /sdram/M0_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) ( 20 /fpga2/M0_LDM ) ( 21 /sdram/M0_WE# ) - ( 22 /fpga2/M0_CAS# ) + ( 22 /sdram/M0_CAS# ) ( 23 /sdram/M0_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 /fpga2/M0_BA0 ) + ( 26 /sdram/M0_BA0 ) ( 27 /sdram/M0_BA1 ) ( 28 /fpga2/M0_A10 ) ( 29 /fpga2/M0_A0 ) @@ -1487,29 +1496,29 @@ ( 32 /sdram/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /fpga2/M0_A4 ) + ( 35 /sdram/M0_A4 ) ( 36 /fpga2/M0_A5 ) ( 37 /sdram/M0_A6 ) ( 38 /fpga2/M0_A7 ) - ( 39 /fpga2/M0_A8 ) + ( 39 /sdram/M0_A8 ) ( 40 /fpga2/M0_A9 ) - ( 41 /sdram/M0_A11 ) + ( 41 /fpga2/M0_A11 ) ( 42 /fpga2/M0_A12 ) ( 43 ? ) ( 44 /sdram/M0_CLK# ) ( 45 /sdram/M0_CKE ) - ( 46 /fpga2/M0_CLK ) - ( 47 /fpga2/M0_UDM ) + ( 46 /sdram/M0_CLK ) + ( 47 /sdram/M0_UDM ) ( 48 GND ) ( 49 /sdram/M0_VREF ) ( 50 ? ) ( 51 /sdram/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /sdram/M0_DQ8 ) + ( 54 /fpga2/M0_DQ8 ) ( 55 +2.5V ) ( 56 /fpga2/M0_DQ9 ) - ( 57 /fpga2/M0_DQ10 ) + ( 57 /sdram/M0_DQ10 ) ( 58 GND ) ( 59 /fpga2/M0_DQ11 ) ( 60 /sdram/M0_DQ12 ) @@ -1517,7 +1526,7 @@ ( 62 /sdram/M0_DQ13 ) ( 63 /sdram/M0_DQ14 ) ( 64 GND ) - ( 65 /fpga2/M0_DQ15 ) + ( 65 /sdram/M0_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG @@ -1525,13 +1534,13 @@ ( 2 /fpga2/M1_DQ0 ) ( 3 +2.5V ) ( 4 /sdram/M1_DQ1 ) - ( 5 /fpga2/M1_DQ2 ) + ( 5 /sdram/M1_DQ2 ) ( 6 GND ) ( 7 /fpga2/M1_DQ3 ) ( 8 /fpga2/M1_DQ4 ) ( 9 +2.5V ) - ( 10 /sdram/M1_DQ5 ) - ( 11 /sdram/M1_DQ6 ) + ( 10 /fpga2/M1_DQ5 ) + ( 11 /fpga2/M1_DQ6 ) ( 12 GND ) ( 13 /fpga2/M1_DQ7 ) ( 14 ? ) @@ -1542,47 +1551,47 @@ ( 19 ? ) ( 20 /fpga2/M1_LDM ) ( 21 /sdram/M1_WE# ) - ( 22 /sdram/M1_CAS# ) - ( 23 /sdram/M1_RAS# ) + ( 22 /fpga2/M1_CAS# ) + ( 23 /fpga2/M1_RAS# ) ( 24 /fpga2/M1_CS# ) ( 25 ? ) ( 26 /sdram/M1_BA0 ) ( 27 /fpga2/M1_BA1 ) ( 28 /sdram/M1_A10 ) ( 29 /fpga2/M1_A0 ) - ( 30 /sdram/M1_A1 ) - ( 31 /fpga2/M1_A2 ) + ( 30 /fpga2/M1_A1 ) + ( 31 /sdram/M1_A2 ) ( 32 /sdram/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /sdram/M1_A4 ) - ( 36 /sdram/M1_A5 ) + ( 36 /fpga2/M1_A5 ) ( 37 /fpga2/M1_A6 ) - ( 38 /fpga2/M1_A7 ) + ( 38 /sdram/M1_A7 ) ( 39 /fpga2/M1_A8 ) - ( 40 /fpga2/M1_A9 ) - ( 41 /fpga2/M1_A11 ) - ( 42 /sdram/M1_A12 ) + ( 40 /sdram/M1_A9 ) + ( 41 /sdram/M1_A11 ) + ( 42 /fpga2/M1_A12 ) ( 43 ? ) ( 44 /fpga2/M1_CLK# ) - ( 45 /fpga2/M1_CKE ) + ( 45 /sdram/M1_CKE ) ( 46 /fpga2/M1_CLK ) ( 47 /sdram/M1_UDM ) ( 48 GND ) ( 49 /sdram/M1_VREF ) ( 50 ? ) - ( 51 /fpga2/M1_UDQS ) + ( 51 /sdram/M1_UDQS ) ( 52 GND ) ( 53 ? ) ( 54 /fpga2/M1_DQ8 ) ( 55 +2.5V ) ( 56 /fpga2/M1_DQ9 ) - ( 57 /fpga2/M1_DQ10 ) + ( 57 /sdram/M1_DQ10 ) ( 58 GND ) - ( 59 /fpga2/M1_DQ11 ) - ( 60 /sdram/M1_DQ12 ) + ( 59 /sdram/M1_DQ11 ) + ( 60 /fpga2/M1_DQ12 ) ( 61 +2.5V ) - ( 62 /sdram/M1_DQ13 ) + ( 62 /fpga2/M1_DQ13 ) ( 63 /fpga2/M1_DQ14 ) ( 64 GND ) ( 65 /fpga2/M1_DQ15 ) @@ -1590,7 +1599,7 @@ ) ( /4C4320F3/4C432132 LQFP48 U4 K8001 ( 1 /ether/ETH_MDIO ) - ( 2 /ether/ETH_MDC ) + ( 2 /fpga1/ETH_MDC ) ( 3 /fpga1/ETH_RXD3 ) ( 4 /fpga1/ETH_RXD2 ) ( 5 /fpga1/ETH_RXD1 ) @@ -1598,19 +1607,19 @@ ( 7 +3.3V ) ( 8 GND ) ( 9 /ether/ETH_RXDV ) - ( 10 /ether/ETH_RXC ) - ( 11 /fpga1/ETH_RXER ) + ( 10 /fpga1/ETH_RXC ) + ( 11 /ether/ETH_RXER ) ( 12 GND ) ( 13 +1.8V ) ( 14 /ether/ETH_TXER ) ( 15 /fpga1/ETH_TXC ) ( 16 /fpga1/ETH_TXEN ) - ( 17 /ether/ETH_TXD0 ) + ( 17 /fpga1/ETH_TXD0 ) ( 18 /fpga1/ETH_TXD1 ) - ( 19 /fpga1/ETH_TXD2 ) - ( 20 /ether/ETH_TXD3 ) + ( 19 /ether/ETH_TXD2 ) + ( 20 /fpga1/ETH_TXD3 ) ( 21 /ether/ETH_COL ) - ( 22 /ether/ETH_CRS ) + ( 22 /fpga1/ETH_CRS ) ( 23 GND ) ( 24 +3.3V ) ( 25 /ether/ETH_INT ) @@ -1625,7 +1634,7 @@ ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000125 ) + ( 37 N-000126 ) ( 38 /ether/ETH_A3.3V ) ( 39 GND ) ( 40 /ether/MAG_TX- ) @@ -1634,7 +1643,7 @@ ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 /ether/ETH_CLK ) + ( 46 /fpga1/ETH_CLK ) ( 47 /ether/ETH_PLL1.8V ) ( 48 /fpga1/ETH_RESET_N ) ) @@ -1644,19 +1653,19 @@ ( 3 ? ) ( 4 ? ) ( 5 ? ) - ( 6 /fpga1/NF_RNB ) - ( 7 /fpga1/NF_RNB ) - ( 8 /flash/NF_RE_N ) - ( 9 /flash/NF_CS1_N ) + ( 6 /flash/NF_RNB ) + ( 7 /flash/NF_RNB ) + ( 8 /fpga1/NF_RE_N ) + ( 9 /fpga1/NF_CS1_N ) ( 10 ? ) ( 11 ? ) ( 12 +3.3V ) ( 13 GND ) ( 14 ? ) ( 15 ? ) - ( 16 /flash/NF_CLE ) - ( 17 /flash/NF_ALE ) - ( 18 /fpga1/NF_WE_N ) + ( 16 /fpga1/NF_CLE ) + ( 17 /fpga1/NF_ALE ) + ( 18 /flash/NF_WE_N ) ( 19 +3.3V ) ( 20 ? ) ( 21 ? ) @@ -1667,10 +1676,10 @@ ( 26 ? ) ( 27 ? ) ( 28 ? ) - ( 29 /flash/NF_D0 ) - ( 30 /flash/NF_D1 ) - ( 31 /fpga1/NF_D2 ) - ( 32 /flash/NF_D3 ) + ( 29 /fpga1/NF_D0 ) + ( 30 /fpga1/NF_D1 ) + ( 31 /flash/NF_D2 ) + ( 32 /fpga1/NF_D3 ) ( 33 ? ) ( 34 ? ) ( 35 ? ) @@ -1680,9 +1689,9 @@ ( 39 ? ) ( 40 ? ) ( 41 /fpga1/NF_D4 ) - ( 42 /flash/NF_D5 ) + ( 42 /fpga1/NF_D5 ) ( 43 /fpga1/NF_D6 ) - ( 44 /flash/NF_D7 ) + ( 44 /fpga1/NF_D7 ) ( 45 ? ) ( 46 ? ) ( 47 ? ) @@ -1706,10 +1715,10 @@ ( 1 /usb/USBD_SPD ) ( 2 /fpga2/USBD_RCV ) ( 3 /fpga2/USBD_VP ) - ( 4 /fpga2/USBD_VM ) + ( 4 /usb/USBD_VM ) ( 6 GND ) ( 7 GND ) - ( 9 /usb/USBD_OE_N ) + ( 9 /fpga2/USBD_OE_N ) ( 10 N-000143 ) ( 11 N-000144 ) ( 12 +3.3V ) @@ -1728,70 +1737,70 @@ ) ( /4C69ED5F/4D13C8D9 MINI-SO-8 U9 LM2621 ( 1 GND ) - ( 2 N-000176 ) - ( 3 N-000169 ) - ( 4 N-000175 ) + ( 2 N-000177 ) + ( 3 N-000171 ) + ( 4 N-000176 ) ( 5 GND ) - ( 6 N-000176 ) - ( 7 N-000168 ) - ( 8 N-000170 ) + ( 6 N-000177 ) + ( 7 N-000170 ) + ( 8 N-000172 ) ) ( /4C69ED5F/4D13C8E1 UDFN6 U10 NCP1529 - ( 1 N-000190 ) + ( 1 N-000191 ) ( 2 GND ) ( 3 ? ) ( 4 GND ) - ( 5 N-000173 ) + ( 5 N-000174 ) ( 6 ? ) ) ( /4C69ED5F/4D13C8C9 SON008V5060 U11 BD9130NV ( 1 N-000159 ) - ( 2 N-000167 ) + ( 2 N-000169 ) ( 3 N-000158 ) ( 4 GND ) ( 5 GND ) - ( 6 N-000166 ) - ( 7 N-000167 ) + ( 6 N-000168 ) + ( 7 N-000169 ) ( 8 ? ) ) ( /4C69ED5F/4D13C8D1 MLF20m1 U12 BD9132MUV - ( 1 N-000163 ) - ( 2 N-000163 ) - ( 3 N-000163 ) - ( 4 N-000163 ) - ( 5 N-000163 ) - ( 6 N-000162 ) - ( 7 N-000162 ) - ( 8 N-000162 ) - ( 9 N-000161 ) + ( 1 N-000165 ) + ( 2 N-000165 ) + ( 3 N-000165 ) + ( 4 N-000165 ) + ( 5 N-000165 ) + ( 6 N-000163 ) + ( 7 N-000163 ) + ( 8 N-000163 ) + ( 9 N-000164 ) ( 10 N-000160 ) - ( 11 N-000185 ) - ( 12 N-000171 ) - ( 13 N-000184 ) + ( 11 N-000186 ) + ( 12 N-000161 ) + ( 13 N-000185 ) ( 14 ? ) ( 15 ? ) ( 16 ? ) ( 17 ? ) - ( 18 N-000185 ) - ( 19 N-000185 ) - ( 20 N-000185 ) + ( 18 N-000186 ) + ( 19 N-000186 ) + ( 20 N-000186 ) ( PAD ? ) ) ( /4C69ED5F/4D1A0F8D PVQFN-N20 U13 BQ2407[0,1] ( 1 ? ) ( 2 ? ) ( 3 ? ) - ( 4 N-000177 ) + ( 4 N-000181 ) ( 5 N-000179 ) ( 6 N-000179 ) ( 7 ? ) ( 8 ? ) ( 9 ? ) - ( 10 N-000201 ) + ( 10 N-000173 ) ( 11 GND ) ( 12 ? ) ( 13 N-000178 ) - ( 14 N-000202 ) + ( 14 N-000197 ) ( 15 N-000180 ) ( 16 N-000180 ) ( 17 N-000180 ) @@ -2354,6 +2363,11 @@ $component C179 C? C1-1 $endlist +$component C180 + SM* + C? + C1-1 +$endlist $component D1 D? S* diff --git a/xue-rnc/xue-rnc.pro b/xue-rnc/xue-rnc.pro index b1ae850..e9e8367 100644 --- a/xue-rnc/xue-rnc.pro +++ b/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Wed 29 Dec 2010 01:38:39 PM COT +update=Fri 31 Dec 2010 10:32:53 AM COT version=1 last_client=pcbnew [common] @@ -100,9 +100,9 @@ NetIExt=net EquName1=devcms [pcbnew] version=1 -PadDrlX=0 -PadDimH=196 -PadDimV=393 +PadDrlX=748 +PadDimH=984 +PadDimV=551 BoardThickness=630 SgPcb45=1 TxtPcbV=591 @@ -154,3 +154,4 @@ LibName33=../modules/MINI-SO-8 LibName34=../modules/SON008V5060 LibName35=../modules/UDFN6 LibName36=../modules/PVQFN-N20 +LibName37=../modules/PJ-CUI-TH diff --git a/xue-rnc/xue-rnc.sch b/xue-rnc/xue-rnc.sch index fd491c8..86b00ed 100644 --- a/xue-rnc/xue-rnc.sch +++ b/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 29 Dec 2010 01:09:52 PM COT +EESchema Schematic File Version 2 date Fri 31 Dec 2010 10:28:45 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -53,13 +53,12 @@ LIBS:ft2232c LIBS:fxo-hc536r LIBS:zx62d-b-5p8 LIBS:a7130 -LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 1 9 Title "" -Date "29 dec 2010" +Date "31 dec 2010" Rev "" Comp "" Comment1 ""