From ef72b751a541e601594c3e811a8f64a5c536cbc0 Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Sat, 14 Aug 2010 07:42:37 -0500 Subject: [PATCH] eth-phy placement --- kicad/xue-rnc/DRAM.sch | 2 +- kicad/xue-rnc/FPGA.sch | 2 +- kicad/xue-rnc/NV_MEMORIES.sch | 2 +- kicad/xue-rnc/USB.sch | 2 +- kicad/xue-rnc/eth_phy.sch | 5 +- kicad/xue-rnc/xue-rnc-cache.lib | 2 +- kicad/xue-rnc/xue-rnc.brd | 1422 ++++++------ kicad/xue-rnc/xue-rnc.cmp | 43 +- kicad/xue-rnc/xue-rnc.net | 3821 ++++++++++++------------------- kicad/xue-rnc/xue-rnc.pro | 2 +- kicad/xue-rnc/xue-rnc.sch | 2 +- 11 files changed, 2226 insertions(+), 3079 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index df37911..8046548 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 44d586f..581f4a0 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index dfe9ebc..4df5c5c 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 9f66fdf..d39cc05 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 41173b8..a0bf3db 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -383,6 +383,7 @@ U 1 1 4C5D810A P 3300 2500 F 0 "L3" V 3250 2500 40 0000 C CNN F 1 "INDUCTOR" V 3400 2500 40 0000 C CNN +F 2 "0402" H 3300 2500 60 0001 C CNN 1 3300 2500 0 -1 -1 0 $EndComp @@ -401,6 +402,7 @@ U 1 1 4C5D80F3 P 2200 2500 F 0 "L1" V 2150 2500 40 0000 C CNN F 1 "INDUCTOR" V 2300 2500 40 0000 C CNN +F 2 "0402" H 2200 2500 60 0001 C CNN 1 2200 2500 0 -1 -1 0 $EndComp @@ -436,6 +438,7 @@ U 1 1 4C5D7FB7 P 2400 1100 F 0 "L2" V 2350 1100 40 0000 C CNN F 1 "FB" V 2500 1100 40 0000 C CNN +F 2 "0402" H 2400 1100 60 0001 C CNN 1 2400 1100 0 -1 -1 0 $EndComp diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 6ddd2ab..8357830 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Fri 13 Aug 2010 07:13:52 PM COT +EESchema-LIBRARY Version 2.3 Date: Sat 14 Aug 2010 07:07:48 AM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index c3a5674..0daf45e 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Fri 13 Aug 2010 07:16:05 PM COT +PCBNEW-BOARD Version 1 date Sat 14 Aug 2010 07:26:51 AM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -8,7 +8,7 @@ Ly 1FFF801F EnabledLayers 1FFF801F Links 538 NoConn 538 -Di 40724 13449 70210 50403 +Di 43677 13510 70149 50342 Ndraw 4 Ntrack 0 Nzone 0 @@ -39,21 +39,21 @@ Layer[2] Inner3 signal Layer[3] Inner4 signal Layer[4] Inner5 signal Layer[15] Front signal -TrackWidth 80 -TrackClearence 100 +TrackWidth 39 +TrackClearence 39 ZoneClearence 200 -TrackMinWidth 80 +TrackMinWidth 39 DrawSegmWidth 150 EdgeSegmWidth 150 -ViaSize 350 -ViaDrill 250 -ViaMinSize 350 -ViaMinDrill 200 -MicroViaSize 200 -MicroViaDrill 50 +ViaSize 197 +ViaDrill 79 +ViaMinSize 197 +ViaMinDrill 79 +MicroViaSize 197 +MicroViaDrill 79 MicroViasAllowed 0 -MicroViaMinSize 200 -MicroViaMinDrill 50 +MicroViaMinSize 197 +MicroViaMinDrill 79 TextPcbWidth 120 TextPcbSize 600 800 EdgeModWidth 150 @@ -86,551 +86,551 @@ Na 4 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/DDR_Banks/M0_A0" +Na 5 "/DDR_Ban102" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A10" +Na 6 "/DDR_Ban103" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_A11" +Na 7 "/DDR_Ban106" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_A3" +Na 8 "/DDR_Ban108" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_A8" +Na 9 "/DDR_Ban112" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_BA1" +Na 10 "/DDR_Ban113" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_DQ0" +Na 11 "/DDR_Ban119" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_DQ13" +Na 12 "/DDR_Ban120" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_DQ2" +Na 13 "/DDR_Ban121" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_DQ4" +Na 14 "/DDR_Ban124" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_DQ5" +Na 15 "/DDR_Ban33" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_DQ6" +Na 16 "/DDR_Ban57" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_DQ8" +Na 17 "/DDR_Ban61" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_DQ9" +Na 18 "/DDR_Ban66" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M0_LDM" +Na 19 "/DDR_Ban68" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M0_LDQS" +Na 20 "/DDR_Ban78" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M0_UDM" +Na 21 "/DDR_Ban80" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M0_UDQS" +Na 22 "/DDR_Ban81" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M0_WE#" +Na 23 "/DDR_Ban83" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_A0" +Na 24 "/DDR_Ban85" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_A12" +Na 25 "/DDR_Ban88" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_BA0" +Na 26 "/DDR_Ban92" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_BA1" +Na 27 "/DDR_Ban97" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_DQ10" +Na 28 "/DDR_Ban98" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_DQ11" +Na 29 "/DDR_Ban99" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_DQ3" +Na 30 "/DDR_Banks/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_DQ4" +Na 31 "/DDR_Banks/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_LDM" +Na 32 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_RAS#" +Na 33 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/Ethernet_Phy/ETH_1.8V" +Na 34 "/Etherne1" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/Ethernet_Phy/ETH_A1.8V" +Na 35 "/Etherne11" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/Ethernet_Phy/ETH_A3.3V" +Na 36 "/Etherne12" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/Ethernet_Phy/ETH_CLK" +Na 37 "/Etherne13" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/Ethernet_Phy/ETH_COL" +Na 38 "/Etherne14" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/Ethernet_Phy/ETH_INT" +Na 39 "/Etherne15" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Ethernet_Phy/ETH_LED0" +Na 40 "/Etherne16" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_LED1" +Na 41 "/Etherne17" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_MDIO" +Na 42 "/Etherne19" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_PLL1.8V" +Na 43 "/Etherne2" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_RXC" +Na 44 "/Etherne29" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_RXD1" +Na 45 "/Etherne3" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_RXDV" +Na 46 "/Etherne37" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_RXER" +Na 47 "/Etherne39" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_TXC" +Na 48 "/Etherne4" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_TXD0" +Na 49 "/Etherne49" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/ETH_TXD3" +Na 50 "/Etherne50" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Ethernet_Phy/ETH_TXER" +Na 51 "/Etherne52" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Spartan6/ETH_CRS" +Na 52 "/FPGA_Sp10" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Spartan6/ETH_MDC" +Na 53 "/FPGA_Sp100" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Spartan6/ETH_RESET_N" +Na 54 "/FPGA_Sp101" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Spartan6/ETH_RXD0" +Na 55 "/FPGA_Sp104" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/ETH_RXD2" +Na 56 "/FPGA_Sp105" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/ETH_RXD3" +Na 57 "/FPGA_Sp107" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/ETH_TXD1" +Na 58 "/FPGA_Sp109" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/ETH_TXD2" +Na 59 "/FPGA_Sp110" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/ETH_TXEN" +Na 60 "/FPGA_Sp111" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/M0_A1" +Na 61 "/FPGA_Sp114" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/M0_A12" +Na 62 "/FPGA_Sp115" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/M0_A2" +Na 63 "/FPGA_Sp116" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/M0_A4" +Na 64 "/FPGA_Sp117" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/M0_A5" +Na 65 "/FPGA_Sp118" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/M0_A6" +Na 66 "/FPGA_Sp122" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/M0_A7" +Na 67 "/FPGA_Sp123" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/M0_A9" +Na 68 "/FPGA_Sp125" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_BA0" +Na 69 "/FPGA_Sp126" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_CAS#" +Na 70 "/FPGA_Sp127" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_CKE" +Na 71 "/FPGA_Sp128" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_CLK" +Na 72 "/FPGA_Sp129" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_CLK#" +Na 73 "/FPGA_Sp130" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_DQ1" +Na 74 "/FPGA_Sp131" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_DQ10" +Na 75 "/FPGA_Sp132" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_DQ11" +Na 76 "/FPGA_Sp133" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_DQ12" +Na 77 "/FPGA_Sp18" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_DQ14" +Na 78 "/FPGA_Sp23" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_DQ15" +Na 79 "/FPGA_Sp24" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_DQ3" +Na 80 "/FPGA_Sp25" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_DQ7" +Na 81 "/FPGA_Sp26" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_RAS#" +Na 82 "/FPGA_Sp27" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M1_A1" +Na 83 "/FPGA_Sp28" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M1_A10" +Na 84 "/FPGA_Sp30" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M1_A11" +Na 85 "/FPGA_Sp32" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M1_A2" +Na 86 "/FPGA_Sp34" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M1_A3" +Na 87 "/FPGA_Sp35" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M1_A4" +Na 88 "/FPGA_Sp36" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M1_A5" +Na 89 "/FPGA_Sp38" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M1_A6" +Na 90 "/FPGA_Sp41" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M1_A7" +Na 91 "/FPGA_Sp44" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M1_A8" +Na 92 "/FPGA_Sp45" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M1_A9" +Na 93 "/FPGA_Sp46" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_CAS#" +Na 94 "/FPGA_Sp47" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_CKE" +Na 95 "/FPGA_Sp48" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_CLK" +Na 96 "/FPGA_Sp51" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_CLK#" +Na 97 "/FPGA_Sp56" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_DQ0" +Na 98 "/FPGA_Sp58" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_DQ1" +Na 99 "/FPGA_Sp59" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_DQ12" +Na 100 "/FPGA_Sp60" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_DQ13" +Na 101 "/FPGA_Sp62" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_DQ14" +Na 102 "/FPGA_Sp63" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_DQ15" +Na 103 "/FPGA_Sp64" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_DQ2" +Na 104 "/FPGA_Sp65" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ5" +Na 105 "/FPGA_Sp67" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_DQ6" +Na 106 "/FPGA_Sp69" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_DQ7" +Na 107 "/FPGA_Sp7" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_DQ8" +Na 108 "/FPGA_Sp70" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ9" +Na 109 "/FPGA_Sp71" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_LDQS" +Na 110 "/FPGA_Sp72" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_UDM" +Na 111 "/FPGA_Sp73" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Spartan6/M1_UDQS" +Na 112 "/FPGA_Sp74" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_WE#" +Na 113 "/FPGA_Sp75" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Spartan6/NF_ALE" +Na 114 "/FPGA_Sp76" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/NF_D2" +Na 115 "/FPGA_Sp77" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/NF_RE_N" +Na 116 "/FPGA_Sp79" St ~ $EndEQUIPOT $EQUIPOT -Na 117 "/FPGA_Spartan6/NF_RNB" +Na 117 "/FPGA_Sp8" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA_Spartan6/PROG_CCLK" +Na 118 "/FPGA_Sp82" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/PROG_CSO" +Na 119 "/FPGA_Sp84" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Spartan6/PROG_MISO0" +Na 120 "/FPGA_Sp86" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Spartan6/PROG_MISO1" +Na 121 "/FPGA_Sp87" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Spartan6/PROG_MISO2" +Na 122 "/FPGA_Sp89" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Spartan6/PROG_MISO3" +Na 123 "/FPGA_Sp90" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Spartan6/SD_CLK" +Na 124 "/FPGA_Sp91" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Spartan6/SD_CMD" +Na 125 "/FPGA_Sp93" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Spartan6/SD_DAT1" +Na 126 "/FPGA_Sp94" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Spartan6/USBA_OE_N" +Na 127 "/FPGA_Sp95" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Spartan6/USBA_RCV" +Na 128 "/FPGA_Sp96" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/Non_volatile_memories/NF_CLE" +Na 129 "/Non_vol20" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/Non_volatile_memories/NF_CS1_N" +Na 130 "/Non_vol21" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/Non_volatile_memories/NF_D0" +Na 131 "/Non_vol22" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/Non_volatile_memories/NF_D1" +Na 132 "/Non_vol31" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/Non_volatile_memories/NF_D3" +Na 133 "/Non_vol40" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/Non_volatile_memories/NF_D4" +Na 134 "/Non_vol42" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/Non_volatile_memories/NF_D5" +Na 135 "/Non_vol43" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/Non_volatile_memories/NF_D6" +Na 136 "/Non_vol5" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/Non_volatile_memories/NF_D7" +Na 137 "/Non_vol53" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/Non_volatile_memories/NF_WE_N" +Na 138 "/Non_vol54" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/Non_volatile_memories/SD_DAT0" +Na 139 "/Non_vol55" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/Non_volatile_memories/SD_DAT2" +Na 140 "/Non_vol6" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/Non_volatile_memories/SD_DAT3" +Na 141 "/Non_vol9" St ~ $EndEQUIPOT $EQUIPOT @@ -768,154 +768,154 @@ $EndEQUIPOT $NCLASS Name "Default" Desc "This is the default net class." -Clearance 100 -TrackWidth 80 -ViaDia 350 -ViaDrill 250 -uViaDia 200 -uViaDrill 50 +Clearance 39 +TrackWidth 39 +ViaDia 197 +ViaDrill 79 +uViaDia 197 +uViaDrill 79 AddNet "" AddNet "+1.2V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" +AddNet "/DDR_Ban102" +AddNet "/DDR_Ban103" +AddNet "/DDR_Ban106" +AddNet "/DDR_Ban108" +AddNet "/DDR_Ban112" +AddNet "/DDR_Ban113" +AddNet "/DDR_Ban119" +AddNet "/DDR_Ban120" +AddNet "/DDR_Ban121" +AddNet "/DDR_Ban124" +AddNet "/DDR_Ban33" +AddNet "/DDR_Ban57" +AddNet "/DDR_Ban61" +AddNet "/DDR_Ban66" +AddNet "/DDR_Ban68" +AddNet "/DDR_Ban78" +AddNet "/DDR_Ban80" +AddNet "/DDR_Ban81" +AddNet "/DDR_Ban83" +AddNet "/DDR_Ban85" +AddNet "/DDR_Ban88" +AddNet "/DDR_Ban92" +AddNet "/DDR_Ban97" +AddNet "/DDR_Ban98" +AddNet "/DDR_Ban99" AddNet "/DDR_Banks/M0_A0" -AddNet "/DDR_Banks/M0_A10" -AddNet "/DDR_Banks/M0_A11" AddNet "/DDR_Banks/M0_A3" AddNet "/DDR_Banks/M0_A8" -AddNet "/DDR_Banks/M0_BA1" -AddNet "/DDR_Banks/M0_DQ0" -AddNet "/DDR_Banks/M0_DQ13" -AddNet "/DDR_Banks/M0_DQ2" -AddNet "/DDR_Banks/M0_DQ4" -AddNet "/DDR_Banks/M0_DQ5" -AddNet "/DDR_Banks/M0_DQ6" -AddNet "/DDR_Banks/M0_DQ8" -AddNet "/DDR_Banks/M0_DQ9" -AddNet "/DDR_Banks/M0_LDM" -AddNet "/DDR_Banks/M0_LDQS" -AddNet "/DDR_Banks/M0_UDM" -AddNet "/DDR_Banks/M0_UDQS" -AddNet "/DDR_Banks/M0_WE#" AddNet "/DDR_Banks/M1_A0" -AddNet "/DDR_Banks/M1_A12" -AddNet "/DDR_Banks/M1_BA0" -AddNet "/DDR_Banks/M1_BA1" -AddNet "/DDR_Banks/M1_DQ10" -AddNet "/DDR_Banks/M1_DQ11" -AddNet "/DDR_Banks/M1_DQ3" -AddNet "/DDR_Banks/M1_DQ4" -AddNet "/DDR_Banks/M1_LDM" -AddNet "/DDR_Banks/M1_RAS#" -AddNet "/Ethernet_Phy/ETH_1.8V" -AddNet "/Ethernet_Phy/ETH_A1.8V" -AddNet "/Ethernet_Phy/ETH_A3.3V" -AddNet "/Ethernet_Phy/ETH_CLK" -AddNet "/Ethernet_Phy/ETH_COL" -AddNet "/Ethernet_Phy/ETH_INT" -AddNet "/Ethernet_Phy/ETH_LED0" -AddNet "/Ethernet_Phy/ETH_LED1" -AddNet "/Ethernet_Phy/ETH_MDIO" -AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/ETH_RXC" -AddNet "/Ethernet_Phy/ETH_RXD1" -AddNet "/Ethernet_Phy/ETH_RXDV" -AddNet "/Ethernet_Phy/ETH_RXER" -AddNet "/Ethernet_Phy/ETH_TXC" -AddNet "/Ethernet_Phy/ETH_TXD0" -AddNet "/Ethernet_Phy/ETH_TXD3" -AddNet "/Ethernet_Phy/ETH_TXER" -AddNet "/FPGA_Spartan6/ETH_CRS" -AddNet "/FPGA_Spartan6/ETH_MDC" -AddNet "/FPGA_Spartan6/ETH_RESET_N" -AddNet "/FPGA_Spartan6/ETH_RXD0" -AddNet "/FPGA_Spartan6/ETH_RXD2" -AddNet "/FPGA_Spartan6/ETH_RXD3" -AddNet "/FPGA_Spartan6/ETH_TXD1" -AddNet "/FPGA_Spartan6/ETH_TXD2" -AddNet "/FPGA_Spartan6/ETH_TXEN" -AddNet "/FPGA_Spartan6/M0_A1" -AddNet "/FPGA_Spartan6/M0_A12" -AddNet "/FPGA_Spartan6/M0_A2" -AddNet "/FPGA_Spartan6/M0_A4" -AddNet "/FPGA_Spartan6/M0_A5" -AddNet "/FPGA_Spartan6/M0_A6" -AddNet "/FPGA_Spartan6/M0_A7" -AddNet "/FPGA_Spartan6/M0_A9" -AddNet "/FPGA_Spartan6/M0_BA0" -AddNet "/FPGA_Spartan6/M0_CAS#" -AddNet "/FPGA_Spartan6/M0_CKE" -AddNet "/FPGA_Spartan6/M0_CLK" -AddNet "/FPGA_Spartan6/M0_CLK#" -AddNet "/FPGA_Spartan6/M0_DQ1" -AddNet "/FPGA_Spartan6/M0_DQ10" -AddNet "/FPGA_Spartan6/M0_DQ11" -AddNet "/FPGA_Spartan6/M0_DQ12" -AddNet "/FPGA_Spartan6/M0_DQ14" -AddNet "/FPGA_Spartan6/M0_DQ15" -AddNet "/FPGA_Spartan6/M0_DQ3" -AddNet "/FPGA_Spartan6/M0_DQ7" -AddNet "/FPGA_Spartan6/M0_RAS#" -AddNet "/FPGA_Spartan6/M1_A1" -AddNet "/FPGA_Spartan6/M1_A10" -AddNet "/FPGA_Spartan6/M1_A11" -AddNet "/FPGA_Spartan6/M1_A2" -AddNet "/FPGA_Spartan6/M1_A3" -AddNet "/FPGA_Spartan6/M1_A4" -AddNet "/FPGA_Spartan6/M1_A5" -AddNet "/FPGA_Spartan6/M1_A6" -AddNet "/FPGA_Spartan6/M1_A7" -AddNet "/FPGA_Spartan6/M1_A8" -AddNet "/FPGA_Spartan6/M1_A9" -AddNet "/FPGA_Spartan6/M1_CAS#" -AddNet "/FPGA_Spartan6/M1_CKE" -AddNet "/FPGA_Spartan6/M1_CLK" -AddNet "/FPGA_Spartan6/M1_CLK#" -AddNet "/FPGA_Spartan6/M1_DQ0" -AddNet "/FPGA_Spartan6/M1_DQ1" -AddNet "/FPGA_Spartan6/M1_DQ12" -AddNet "/FPGA_Spartan6/M1_DQ13" -AddNet "/FPGA_Spartan6/M1_DQ14" -AddNet "/FPGA_Spartan6/M1_DQ15" -AddNet "/FPGA_Spartan6/M1_DQ2" -AddNet "/FPGA_Spartan6/M1_DQ5" -AddNet "/FPGA_Spartan6/M1_DQ6" -AddNet "/FPGA_Spartan6/M1_DQ7" -AddNet "/FPGA_Spartan6/M1_DQ8" -AddNet "/FPGA_Spartan6/M1_DQ9" -AddNet "/FPGA_Spartan6/M1_LDQS" -AddNet "/FPGA_Spartan6/M1_UDM" -AddNet "/FPGA_Spartan6/M1_UDQS" -AddNet "/FPGA_Spartan6/M1_WE#" -AddNet "/FPGA_Spartan6/NF_ALE" -AddNet "/FPGA_Spartan6/NF_D2" -AddNet "/FPGA_Spartan6/NF_RE_N" -AddNet "/FPGA_Spartan6/NF_RNB" -AddNet "/FPGA_Spartan6/PROG_CCLK" -AddNet "/FPGA_Spartan6/PROG_CSO" -AddNet "/FPGA_Spartan6/PROG_MISO0" -AddNet "/FPGA_Spartan6/PROG_MISO1" -AddNet "/FPGA_Spartan6/PROG_MISO2" -AddNet "/FPGA_Spartan6/PROG_MISO3" -AddNet "/FPGA_Spartan6/SD_CLK" -AddNet "/FPGA_Spartan6/SD_CMD" -AddNet "/FPGA_Spartan6/SD_DAT1" -AddNet "/FPGA_Spartan6/USBA_OE_N" -AddNet "/FPGA_Spartan6/USBA_RCV" -AddNet "/Non_volatile_memories/NF_CLE" -AddNet "/Non_volatile_memories/NF_CS1_N" -AddNet "/Non_volatile_memories/NF_D0" -AddNet "/Non_volatile_memories/NF_D1" -AddNet "/Non_volatile_memories/NF_D3" -AddNet "/Non_volatile_memories/NF_D4" -AddNet "/Non_volatile_memories/NF_D5" -AddNet "/Non_volatile_memories/NF_D6" -AddNet "/Non_volatile_memories/NF_D7" -AddNet "/Non_volatile_memories/NF_WE_N" -AddNet "/Non_volatile_memories/SD_DAT0" -AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "/Non_volatile_memories/SD_DAT3" +AddNet "/Etherne1" +AddNet "/Etherne11" +AddNet "/Etherne12" +AddNet "/Etherne13" +AddNet "/Etherne14" +AddNet "/Etherne15" +AddNet "/Etherne16" +AddNet "/Etherne17" +AddNet "/Etherne19" +AddNet "/Etherne2" +AddNet "/Etherne29" +AddNet "/Etherne3" +AddNet "/Etherne37" +AddNet "/Etherne39" +AddNet "/Etherne4" +AddNet "/Etherne49" +AddNet "/Etherne50" +AddNet "/Etherne52" +AddNet "/FPGA_Sp10" +AddNet "/FPGA_Sp100" +AddNet "/FPGA_Sp101" +AddNet "/FPGA_Sp104" +AddNet "/FPGA_Sp105" +AddNet "/FPGA_Sp107" +AddNet "/FPGA_Sp109" +AddNet "/FPGA_Sp110" +AddNet "/FPGA_Sp111" +AddNet "/FPGA_Sp114" +AddNet "/FPGA_Sp115" +AddNet "/FPGA_Sp116" +AddNet "/FPGA_Sp117" +AddNet "/FPGA_Sp118" +AddNet "/FPGA_Sp122" +AddNet "/FPGA_Sp123" +AddNet "/FPGA_Sp125" +AddNet "/FPGA_Sp126" +AddNet "/FPGA_Sp127" +AddNet "/FPGA_Sp128" +AddNet "/FPGA_Sp129" +AddNet "/FPGA_Sp130" +AddNet "/FPGA_Sp131" +AddNet "/FPGA_Sp132" +AddNet "/FPGA_Sp133" +AddNet "/FPGA_Sp18" +AddNet "/FPGA_Sp23" +AddNet "/FPGA_Sp24" +AddNet "/FPGA_Sp25" +AddNet "/FPGA_Sp26" +AddNet "/FPGA_Sp27" +AddNet "/FPGA_Sp28" +AddNet "/FPGA_Sp30" +AddNet "/FPGA_Sp32" +AddNet "/FPGA_Sp34" +AddNet "/FPGA_Sp35" +AddNet "/FPGA_Sp36" +AddNet "/FPGA_Sp38" +AddNet "/FPGA_Sp41" +AddNet "/FPGA_Sp44" +AddNet "/FPGA_Sp45" +AddNet "/FPGA_Sp46" +AddNet "/FPGA_Sp47" +AddNet "/FPGA_Sp48" +AddNet "/FPGA_Sp51" +AddNet "/FPGA_Sp56" +AddNet "/FPGA_Sp58" +AddNet "/FPGA_Sp59" +AddNet "/FPGA_Sp60" +AddNet "/FPGA_Sp62" +AddNet "/FPGA_Sp63" +AddNet "/FPGA_Sp64" +AddNet "/FPGA_Sp65" +AddNet "/FPGA_Sp67" +AddNet "/FPGA_Sp69" +AddNet "/FPGA_Sp7" +AddNet "/FPGA_Sp70" +AddNet "/FPGA_Sp71" +AddNet "/FPGA_Sp72" +AddNet "/FPGA_Sp73" +AddNet "/FPGA_Sp74" +AddNet "/FPGA_Sp75" +AddNet "/FPGA_Sp76" +AddNet "/FPGA_Sp77" +AddNet "/FPGA_Sp79" +AddNet "/FPGA_Sp8" +AddNet "/FPGA_Sp82" +AddNet "/FPGA_Sp84" +AddNet "/FPGA_Sp86" +AddNet "/FPGA_Sp87" +AddNet "/FPGA_Sp89" +AddNet "/FPGA_Sp90" +AddNet "/FPGA_Sp91" +AddNet "/FPGA_Sp93" +AddNet "/FPGA_Sp94" +AddNet "/FPGA_Sp95" +AddNet "/FPGA_Sp96" +AddNet "/Non_vol20" +AddNet "/Non_vol21" +AddNet "/Non_vol22" +AddNet "/Non_vol31" +AddNet "/Non_vol40" +AddNet "/Non_vol42" +AddNet "/Non_vol43" +AddNet "/Non_vol5" +AddNet "/Non_vol53" +AddNet "/Non_vol54" +AddNet "/Non_vol55" +AddNet "/Non_vol6" +AddNet "/Non_vol9" AddNet "/USB/USBA_SPD" AddNet "/USB/USBA_VM" AddNet "/USB/USBA_VP" @@ -979,7 +979,7 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE FGG484bga-p10 -Po 56450 33930 0 15 4C4325AE 4C65E045 ~~ +Po 56299 33858 0 15 4C4325AE 4C65E045 ~~ Li FGG484bga-p10 Sc 4C65E045 AR /4C431A63/4C431E53 @@ -1020,70 +1020,70 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_INT" +Ne 38 "/Etherne14" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_MDIO" +Ne 35 "/Etherne11" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_RXD1" +Ne 39 "/Etherne15" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_RXDV" +Ne 40 "/Etherne16" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_TXER" +Ne 41 "/Etherne17" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_TXD2" +Ne 77 "/FPGA_Sp18" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_COL" +Ne 42 "/Etherne19" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/Non_volatile_memories/NF_D7" +Ne 129 "/Non_vol20" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/Non_volatile_memories/NF_D3" +Ne 130 "/Non_vol21" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/Non_volatile_memories/NF_D1" +Ne 131 "/Non_vol22" Po 590 -4133 $EndPAD $PAD @@ -1097,28 +1097,28 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/NF_ALE" +Ne 78 "/FPGA_Sp23" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_RNB" +Ne 79 "/FPGA_Sp24" Po 1771 -4133 $EndPAD $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/Non_volatile_memories/SD_DAT2" +Ne 136 "/Non_vol5" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/Non_volatile_memories/SD_DAT0" +Ne 141 "/Non_vol9" Po 2558 -4133 $EndPAD $PAD @@ -1188,7 +1188,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_RXD2" +Ne 83 "/FPGA_Sp28" Po -2165 -3739 $EndPAD $PAD @@ -1202,7 +1202,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_RXER" +Ne 44 "/Etherne29" Po -1377 -3739 $EndPAD $PAD @@ -1216,7 +1216,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_CRS" +Ne 84 "/FPGA_Sp30" Po -590 -3739 $EndPAD $PAD @@ -1230,7 +1230,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/Non_volatile_memories/NF_D4" +Ne 132 "/Non_vol31" Po 196 -3739 $EndPAD $PAD @@ -1258,7 +1258,7 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_RE_N" +Ne 85 "/FPGA_Sp32" Po 1771 -3739 $EndPAD $PAD @@ -1272,7 +1272,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/SD_DAT1" +Ne 52 "/FPGA_Sp10" Po 2558 -3739 $EndPAD $PAD @@ -1307,7 +1307,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A11" +Ne 15 "/DDR_Ban33" Po -4133 -3346 $EndPAD $PAD @@ -1335,42 +1335,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_MDC" +Ne 86 "/FPGA_Sp34" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RXD3" +Ne 87 "/FPGA_Sp35" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_RXD0" +Ne 88 "/FPGA_Sp36" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_TXD0" +Ne 46 "/Etherne37" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_TXD1" +Ne 89 "/FPGA_Sp38" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_CLK" +Ne 47 "/Etherne39" Po -590 -3346 $EndPAD $PAD @@ -1384,14 +1384,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/Non_volatile_memories/NF_D5" +Ne 133 "/Non_vol40" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_D2" +Ne 90 "/FPGA_Sp41" Po 590 -3346 $EndPAD $PAD @@ -1405,21 +1405,21 @@ $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/Non_volatile_memories/NF_WE_N" +Ne 134 "/Non_vol42" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/Non_volatile_memories/NF_CS1_N" +Ne 135 "/Non_vol43" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/Non_volatile_memories/SD_DAT3" +Ne 140 "/Non_vol6" Po 2165 -3346 $EndPAD $PAD @@ -1440,7 +1440,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A8" +Ne 91 "/FPGA_Sp44" Po 3346 -3346 $EndPAD $PAD @@ -1454,21 +1454,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_A9" +Ne 92 "/FPGA_Sp45" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/M0_A12" +Ne 93 "/FPGA_Sp46" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_CKE" +Ne 94 "/FPGA_Sp47" Po -3739 -2952 $EndPAD $PAD @@ -1496,42 +1496,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_RESET_N" +Ne 95 "/FPGA_Sp48" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_TXD3" +Ne 49 "/Etherne49" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_TXC" +Ne 50 "/Etherne50" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_TXEN" +Ne 96 "/FPGA_Sp51" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_RXC" +Ne 51 "/Etherne52" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/Non_volatile_memories/NF_D6" +Ne 137 "/Non_vol53" Po -196 -2952 $EndPAD $PAD @@ -1552,14 +1552,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/Non_volatile_memories/NF_D0" +Ne 138 "/Non_vol54" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/Non_volatile_memories/NF_CLE" +Ne 139 "/Non_vol55" Po 1377 -2952 $EndPAD $PAD @@ -1573,7 +1573,7 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/SD_CMD" +Ne 107 "/FPGA_Sp7" Po 2165 -2952 $EndPAD $PAD @@ -1601,21 +1601,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_CKE" +Ne 97 "/FPGA_Sp56" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A12" +Ne 16 "/DDR_Ban57" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A9" +Ne 98 "/FPGA_Sp58" Po -4133 -2558 $EndPAD $PAD @@ -1629,7 +1629,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A8" +Ne 32 "/DDR_Banks/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1720,7 +1720,7 @@ $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/SD_CLK" +Ne 117 "/FPGA_Sp8" Po 1771 -2558 $EndPAD $PAD @@ -1748,7 +1748,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A7" +Ne 99 "/FPGA_Sp59" Po 3346 -2558 $EndPAD $PAD @@ -1762,7 +1762,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M1_A2" +Ne 100 "/FPGA_Sp60" Po 4133 -2558 $EndPAD $PAD @@ -1776,14 +1776,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M0_WE#" +Ne 17 "/DDR_Ban61" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A4" +Ne 101 "/FPGA_Sp62" Po -3346 -2165 $EndPAD $PAD @@ -1895,35 +1895,35 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M1_A11" +Ne 102 "/FPGA_Sp63" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M1_A4" +Ne 103 "/FPGA_Sp64" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A0" +Ne 33 "/DDR_Banks/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M1_A1" +Ne 104 "/FPGA_Sp65" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_BA1" +Ne 18 "/DDR_Ban66" Po -4133 -1771 $EndPAD $PAD @@ -1937,14 +1937,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_BA0" +Ne 105 "/FPGA_Sp67" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A10" +Ne 19 "/DDR_Ban68" Po -2952 -1771 $EndPAD $PAD @@ -2049,14 +2049,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M1_A10" +Ne 106 "/FPGA_Sp69" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M1_A3" +Ne 108 "/FPGA_Sp70" Po 3346 -1771 $EndPAD $PAD @@ -2077,42 +2077,42 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/M0_A1" +Ne 109 "/FPGA_Sp71" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_A0" +Ne 30 "/DDR_Banks/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_CLK#" +Ne 110 "/FPGA_Sp72" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_CLK" +Ne 111 "/FPGA_Sp73" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M0_A2" +Ne 112 "/FPGA_Sp74" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A7" +Ne 113 "/FPGA_Sp75" Po -2165 -1377 $EndPAD $PAD @@ -2203,35 +2203,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_WE#" +Ne 114 "/FPGA_Sp76" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_CLK" +Ne 115 "/FPGA_Sp77" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_RAS#" +Ne 20 "/DDR_Ban78" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_CAS#" +Ne 116 "/FPGA_Sp79" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ5" +Ne 21 "/DDR_Ban80" Po -4133 -983 $EndPAD $PAD @@ -2245,14 +2245,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ4" +Ne 22 "/DDR_Ban81" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A6" +Ne 118 "/FPGA_Sp82" Po -2952 -983 $EndPAD $PAD @@ -2343,7 +2343,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_BA0" +Ne 23 "/DDR_Ban83" Po 2165 -983 $EndPAD $PAD @@ -2357,14 +2357,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_CLK#" +Ne 119 "/FPGA_Sp84" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ4" +Ne 24 "/DDR_Ban85" Po 3346 -983 $EndPAD $PAD @@ -2378,49 +2378,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ5" +Ne 120 "/FPGA_Sp86" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ7" +Ne 121 "/FPGA_Sp87" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ6" +Ne 25 "/DDR_Ban88" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A5" +Ne 122 "/FPGA_Sp89" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_CAS#" +Ne 123 "/FPGA_Sp90" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_RAS#" +Ne 124 "/FPGA_Sp91" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A3" +Ne 31 "/DDR_Banks/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2497,7 +2497,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_BA1" +Ne 26 "/DDR_Ban92" Po 2165 -590 $EndPAD $PAD @@ -2511,28 +2511,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A6" +Ne 125 "/FPGA_Sp93" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A5" +Ne 126 "/FPGA_Sp94" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ6" +Ne 127 "/FPGA_Sp95" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ7" +Ne 128 "/FPGA_Sp96" Po 4133 -590 $EndPAD $PAD @@ -2553,14 +2553,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_LDQS" +Ne 27 "/DDR_Ban97" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_LDM" +Ne 28 "/DDR_Ban98" Po -2952 -196 $EndPAD $PAD @@ -2665,14 +2665,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_LDM" +Ne 29 "/DDR_Ban99" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_LDQS" +Ne 53 "/FPGA_Sp100" Po 3346 -196 $EndPAD $PAD @@ -2693,21 +2693,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ3" +Ne 54 "/FPGA_Sp101" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ2" +Ne 5 "/DDR_Ban102" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_UDM" +Ne 6 "/DDR_Ban103" Po -3346 196 $EndPAD $PAD @@ -2826,28 +2826,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_UDM" +Ne 55 "/FPGA_Sp104" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ2" +Ne 56 "/FPGA_Sp105" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ3" +Ne 7 "/DDR_Ban106" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_DQ1" +Ne 57 "/FPGA_Sp107" Po -4133 590 $EndPAD $PAD @@ -2861,7 +2861,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_DQ0" +Ne 8 "/DDR_Ban108" Po -3346 590 $EndPAD $PAD @@ -2952,7 +2952,7 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/USBA_RCV" +Ne 58 "/FPGA_Sp109" Po 1771 590 $EndPAD $PAD @@ -2980,7 +2980,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_DQ0" +Ne 59 "/FPGA_Sp110" Po 3346 590 $EndPAD $PAD @@ -2994,21 +2994,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_DQ1" +Ne 60 "/FPGA_Sp111" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_DQ9" +Ne 9 "/DDR_Ban112" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ8" +Ne 10 "/DDR_Ban113" Po -3739 983 $EndPAD $PAD @@ -3120,7 +3120,7 @@ $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/USBA_OE_N" +Ne 61 "/FPGA_Sp114" Po 2558 983 $EndPAD $PAD @@ -3141,21 +3141,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ8" +Ne 62 "/FPGA_Sp115" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ9" +Ne 63 "/FPGA_Sp116" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ11" +Ne 64 "/FPGA_Sp117" Po -4133 1377 $EndPAD $PAD @@ -3169,7 +3169,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_DQ10" +Ne 65 "/FPGA_Sp118" Po -3346 1377 $EndPAD $PAD @@ -3288,7 +3288,7 @@ $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_DQ10" +Ne 11 "/DDR_Ban119" Po 3346 1377 $EndPAD $PAD @@ -3302,7 +3302,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_DQ11" +Ne 12 "/DDR_Ban120" Po 4133 1377 $EndPAD $PAD @@ -3316,7 +3316,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_UDQS" +Ne 13 "/DDR_Ban121" Po -3739 1771 $EndPAD $PAD @@ -3337,7 +3337,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/PROG_CSO" +Ne 66 "/FPGA_Sp122" Po -2558 1771 $EndPAD $PAD @@ -3449,7 +3449,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_UDQS" +Ne 67 "/FPGA_Sp123" Po 3739 1771 $EndPAD $PAD @@ -3463,7 +3463,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_DQ13" +Ne 14 "/DDR_Ban124" Po -4133 2165 $EndPAD $PAD @@ -3477,7 +3477,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ12" +Ne 68 "/FPGA_Sp125" Po -3346 2165 $EndPAD $PAD @@ -3547,14 +3547,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/PROG_MISO3" +Ne 69 "/FPGA_Sp126" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/PROG_MISO2" +Ne 70 "/FPGA_Sp127" Po 983 2165 $EndPAD $PAD @@ -3596,7 +3596,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_DQ12" +Ne 71 "/FPGA_Sp128" Po 3346 2165 $EndPAD $PAD @@ -3610,21 +3610,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ13" +Ne 72 "/FPGA_Sp129" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ15" +Ne 73 "/FPGA_Sp130" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ14" +Ne 74 "/FPGA_Sp131" Po -3739 2558 $EndPAD $PAD @@ -3757,14 +3757,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ14" +Ne 75 "/FPGA_Sp132" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ15" +Ne 76 "/FPGA_Sp133" Po 4133 2558 $EndPAD $PAD @@ -4212,14 +4212,14 @@ $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/PROG_MISO1" +Ne 80 "/FPGA_Sp25" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/PROG_CCLK" +Ne 81 "/FPGA_Sp26" Po 3739 3739 $EndPAD $PAD @@ -4366,7 +4366,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/PROG_MISO0" +Ne 82 "/FPGA_Sp27" Po 3346 4133 $EndPAD $PAD @@ -4409,21 +4409,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_RXER" +Ne 44 "/Etherne29" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_RXC" +Ne 51 "/Etherne52" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_RXDV" +Ne 40 "/Etherne16" Po -1613 491 $EndPAD $PAD @@ -4444,63 +4444,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_RXD0" +Ne 88 "/FPGA_Sp36" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_RXD1" +Ne 39 "/Etherne15" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_RXD2" +Ne 83 "/FPGA_Sp28" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_RXD3" +Ne 87 "/FPGA_Sp35" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_MDC" +Ne 86 "/FPGA_Sp34" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_MDIO" +Ne 35 "/Etherne11" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_RESET_N" +Ne 95 "/FPGA_Sp48" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 48 "/Etherne4" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_CLK" +Ne 47 "/Etherne39" Po -688 -1613 $EndPAD $PAD @@ -4556,7 +4556,7 @@ $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_A3.3V" +Ne 45 "/Etherne3" Po 885 -1613 $EndPAD $PAD @@ -4570,21 +4570,21 @@ $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_INT" +Ne 38 "/Etherne14" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_LED0" +Ne 36 "/Etherne12" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_LED1" +Ne 37 "/Etherne13" Po 1613 688 $EndPAD $PAD @@ -4612,7 +4612,7 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_A1.8V" +Ne 43 "/Etherne2" Po 1613 -98 $EndPAD $PAD @@ -4654,70 +4654,70 @@ $PAD Sh "13" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Ethernet_Phy/ETH_1.8V" +Ne 34 "/Etherne1" Po -1082 1613 $EndPAD $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_TXER" +Ne 41 "/Etherne17" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_TXC" +Ne 50 "/Etherne50" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_TXEN" +Ne 96 "/FPGA_Sp51" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_TXD0" +Ne 46 "/Etherne37" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_TXD1" +Ne 89 "/FPGA_Sp38" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_TXD2" +Ne 77 "/FPGA_Sp18" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_TXD3" +Ne 49 "/Etherne49" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_COL" +Ne 42 "/Etherne19" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_CRS" +Ne 84 "/FPGA_Sp30" Po 688 1613 $EndPAD $PAD @@ -4995,28 +4995,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_RNB" +Ne 79 "/FPGA_Sp24" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 117 "/FPGA_Spartan6/NF_RNB" +Ne 79 "/FPGA_Sp24" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_RE_N" +Ne 85 "/FPGA_Sp32" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/Non_volatile_memories/NF_CS1_N" +Ne 135 "/Non_vol43" Po -690 3850 $EndPAD $PAD @@ -5065,21 +5065,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/Non_volatile_memories/NF_CLE" +Ne 139 "/Non_vol55" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/NF_ALE" +Ne 78 "/FPGA_Sp23" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/Non_volatile_memories/NF_WE_N" +Ne 134 "/Non_vol42" Po 1080 3850 $EndPAD $PAD @@ -5156,28 +5156,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/Non_volatile_memories/NF_D0" +Ne 138 "/Non_vol54" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/Non_volatile_memories/NF_D1" +Ne 131 "/Non_vol22" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_D2" +Ne 90 "/FPGA_Sp41" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/Non_volatile_memories/NF_D3" +Ne 130 "/Non_vol21" Po 880 -3850 $EndPAD $PAD @@ -5240,28 +5240,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/Non_volatile_memories/NF_D4" +Ne 132 "/Non_vol31" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/Non_volatile_memories/NF_D5" +Ne 133 "/Non_vol40" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/Non_volatile_memories/NF_D6" +Ne 137 "/Non_vol53" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/Non_volatile_memories/NF_D7" +Ne 129 "/Non_vol20" Po -1480 -3850 $EndPAD $PAD @@ -5314,21 +5314,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 140 "/Non_volatile_memories/SD_DAT2" +Ne 136 "/Non_vol5" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 141 "/Non_volatile_memories/SD_DAT3" +Ne 140 "/Non_vol6" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 125 "/FPGA_Spartan6/SD_CMD" +Ne 107 "/FPGA_Sp7" Po -433 0 $EndPAD $PAD @@ -5342,7 +5342,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 124 "/FPGA_Spartan6/SD_CLK" +Ne 117 "/FPGA_Sp8" Po 433 0 $EndPAD $PAD @@ -5356,14 +5356,14 @@ $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 139 "/Non_volatile_memories/SD_DAT0" +Ne 141 "/Non_vol9" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 126 "/FPGA_Spartan6/SD_DAT1" +Ne 52 "/FPGA_Sp10" Po 1732 0 $EndPAD $PAD @@ -5559,7 +5559,7 @@ $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 128 "/FPGA_Spartan6/USBA_RCV" +Ne 58 "/FPGA_Sp109" Po -255 -1112 $EndPAD $PAD @@ -5601,7 +5601,7 @@ $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 127 "/FPGA_Spartan6/USBA_OE_N" +Ne 61 "/FPGA_Sp114" Po 511 1112 $EndPAD $PAD @@ -5665,7 +5665,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_DQ0" +Ne 59 "/FPGA_Sp110" Po -3838 2176 $EndPAD $PAD @@ -5679,14 +5679,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_DQ1" +Ne 60 "/FPGA_Sp111" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ2" +Ne 56 "/FPGA_Sp105" Po -3070 2176 $EndPAD $PAD @@ -5700,14 +5700,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_DQ3" +Ne 7 "/DDR_Ban106" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_DQ4" +Ne 24 "/DDR_Ban85" Po -2303 2176 $EndPAD $PAD @@ -5721,14 +5721,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ5" +Ne 120 "/FPGA_Sp86" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ6" +Ne 127 "/FPGA_Sp95" Po -1535 2176 $EndPAD $PAD @@ -5742,7 +5742,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ7" +Ne 128 "/FPGA_Sp96" Po -1023 2176 $EndPAD $PAD @@ -5763,7 +5763,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_LDQS" +Ne 53 "/FPGA_Sp100" Po -255 2176 $EndPAD $PAD @@ -5791,28 +5791,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_LDM" +Ne 29 "/DDR_Ban99" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_WE#" +Ne 114 "/FPGA_Sp76" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_CAS#" +Ne 116 "/FPGA_Sp79" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_RAS#" +Ne 20 "/DDR_Ban78" Po 1535 2176 $EndPAD $PAD @@ -5833,49 +5833,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_BA0" +Ne 23 "/DDR_Ban83" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_BA1" +Ne 26 "/DDR_Ban92" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M1_A10" +Ne 106 "/FPGA_Sp69" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A0" +Ne 33 "/DDR_Banks/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M1_A1" +Ne 104 "/FPGA_Sp65" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M1_A2" +Ne 100 "/FPGA_Sp60" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M1_A3" +Ne 108 "/FPGA_Sp70" Po 3838 2176 $EndPAD $PAD @@ -5896,56 +5896,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M1_A4" +Ne 103 "/FPGA_Sp64" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A5" +Ne 126 "/FPGA_Sp94" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A6" +Ne 125 "/FPGA_Sp93" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A7" +Ne 99 "/FPGA_Sp59" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A8" +Ne 91 "/FPGA_Sp44" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_A9" +Ne 92 "/FPGA_Sp45" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M1_A11" +Ne 102 "/FPGA_Sp63" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A12" +Ne 16 "/DDR_Ban57" Po 2047 -2176 $EndPAD $PAD @@ -5959,28 +5959,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_CLK#" +Ne 119 "/FPGA_Sp84" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_CKE" +Ne 97 "/FPGA_Sp56" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_CLK" +Ne 115 "/FPGA_Sp77" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_UDM" +Ne 55 "/FPGA_Sp104" Po 767 -2176 $EndPAD $PAD @@ -6008,7 +6008,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_UDQS" +Ne 67 "/FPGA_Sp123" Po -255 -2176 $EndPAD $PAD @@ -6029,7 +6029,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ8" +Ne 62 "/FPGA_Sp115" Po -1023 -2176 $EndPAD $PAD @@ -6043,14 +6043,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ9" +Ne 63 "/FPGA_Sp116" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_DQ10" +Ne 11 "/DDR_Ban119" Po -1791 -2176 $EndPAD $PAD @@ -6064,14 +6064,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_DQ11" +Ne 12 "/DDR_Ban120" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_DQ12" +Ne 71 "/FPGA_Sp128" Po -2558 -2176 $EndPAD $PAD @@ -6085,14 +6085,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ13" +Ne 72 "/FPGA_Sp129" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ14" +Ne 75 "/FPGA_Sp132" Po -3326 -2176 $EndPAD $PAD @@ -6106,7 +6106,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ15" +Ne 76 "/FPGA_Sp133" Po -3838 -2176 $EndPAD $PAD @@ -6118,7 +6118,7 @@ Po -4094 -2176 $EndPAD $EndMODULE TSOP-66 $MODULE TSOP-66 -Po 49016 34055 900 15 4C6098A7 4C609B99 ~~ +Po 48819 34055 900 15 4C6098A7 4C609B99 ~~ Li TSOP-66 Sc 4C609B99 AR /4C421DD3/4C609B99 @@ -6142,7 +6142,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_DQ0" +Ne 8 "/DDR_Ban108" Po -3838 2176 $EndPAD $PAD @@ -6156,14 +6156,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_DQ1" +Ne 57 "/FPGA_Sp107" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ2" +Ne 5 "/DDR_Ban102" Po -3070 2176 $EndPAD $PAD @@ -6177,14 +6177,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ3" +Ne 54 "/FPGA_Sp101" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ4" +Ne 22 "/DDR_Ban81" Po -2303 2176 $EndPAD $PAD @@ -6198,14 +6198,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ5" +Ne 21 "/DDR_Ban80" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ6" +Ne 25 "/DDR_Ban88" Po -1535 2176 $EndPAD $PAD @@ -6219,7 +6219,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ7" +Ne 121 "/FPGA_Sp87" Po -1023 2176 $EndPAD $PAD @@ -6240,7 +6240,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M0_LDQS" +Ne 27 "/DDR_Ban97" Po -255 2176 $EndPAD $PAD @@ -6268,28 +6268,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M0_LDM" +Ne 28 "/DDR_Ban98" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M0_WE#" +Ne 17 "/DDR_Ban61" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_CAS#" +Ne 123 "/FPGA_Sp90" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_RAS#" +Ne 124 "/FPGA_Sp91" Po 1535 2176 $EndPAD $PAD @@ -6310,49 +6310,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_BA0" +Ne 105 "/FPGA_Sp67" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_BA1" +Ne 18 "/DDR_Ban66" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A10" +Ne 19 "/DDR_Ban68" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_A0" +Ne 30 "/DDR_Banks/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/M0_A1" +Ne 109 "/FPGA_Sp71" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M0_A2" +Ne 112 "/FPGA_Sp74" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A3" +Ne 31 "/DDR_Banks/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -6373,56 +6373,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A4" +Ne 101 "/FPGA_Sp62" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A5" +Ne 122 "/FPGA_Sp89" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A6" +Ne 118 "/FPGA_Sp82" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A7" +Ne 113 "/FPGA_Sp75" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A8" +Ne 32 "/DDR_Banks/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A9" +Ne 98 "/FPGA_Sp58" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A11" +Ne 15 "/DDR_Ban33" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/M0_A12" +Ne 93 "/FPGA_Sp46" Po 2047 -2176 $EndPAD $PAD @@ -6436,28 +6436,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_CLK#" +Ne 110 "/FPGA_Sp72" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_CKE" +Ne 94 "/FPGA_Sp47" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_CLK" +Ne 111 "/FPGA_Sp73" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M0_UDM" +Ne 6 "/DDR_Ban103" Po 767 -2176 $EndPAD $PAD @@ -6485,7 +6485,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M0_UDQS" +Ne 13 "/DDR_Ban121" Po -255 -2176 $EndPAD $PAD @@ -6506,7 +6506,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ8" +Ne 10 "/DDR_Ban113" Po -1023 -2176 $EndPAD $PAD @@ -6520,14 +6520,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_DQ9" +Ne 9 "/DDR_Ban112" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_DQ10" +Ne 65 "/FPGA_Sp118" Po -1791 -2176 $EndPAD $PAD @@ -6541,14 +6541,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ11" +Ne 64 "/FPGA_Sp117" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ12" +Ne 68 "/FPGA_Sp125" Po -2558 -2176 $EndPAD $PAD @@ -6562,14 +6562,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_DQ13" +Ne 14 "/DDR_Ban124" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ14" +Ne 74 "/FPGA_Sp131" Po -3326 -2176 $EndPAD $PAD @@ -6583,7 +6583,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ15" +Ne 73 "/FPGA_Sp130" Po -3838 -2176 $EndPAD $PAD @@ -6651,58 +6651,58 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51575 24409 2700 0 4C5FF890 4C5D71DB ~~ +Po 50000 24213 0 0 4C5FF890 4C5D71DB ~~ Li 0402 Sc 4C5D71DB AR /4C4320F3/4C5D71DB Op 0 0 0 At SMD -T0 0 150 200 200 2700 40 M V 20 N"R8" -T1 0 -150 200 200 2700 40 M I 20 N"220" +T0 0 150 200 200 0 40 M V 20 N"R8" +T1 0 -150 200 200 0 40 M I 20 N"220" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 2700 +Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 Ne 161 "N-000331" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 2700 +Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_LED1" +Ne 37 "/Etherne13" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 52165 24409 2700 0 4C5FF890 4C5D719D ~~ +Po 51575 24213 0 0 4C5FF890 4C5D719D ~~ Li 0402 Sc 4C5D719D AR /4C4320F3/4C5D719D Op 0 0 0 At SMD -T0 0 150 200 200 2700 40 M V 20 N"R7" -T1 0 -150 200 200 2700 40 M I 20 N"220" +T0 0 150 200 200 0 40 M V 20 N"R7" +T1 0 -150 200 200 0 40 M I 20 N"220" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 2700 +Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 Ne 153 "N-000315" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 2700 +Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/Ethernet_Phy/ETH_LED0" +Ne 36 "/Etherne12" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6863,7 +6863,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/Ethernet_Phy/ETH_MDIO" +Ne 35 "/Etherne11" Po -176 0 $EndPAD $PAD @@ -6931,27 +6931,27 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51771 27953 0 0 4C5FF890 4C5D7E43 ~~ +Po 51575 27953 1800 0 4C5FF890 4C5D7E43 ~~ Li 0402 Sc 4C5D7E43 AR /4C4320F3/4C5D7E43 Op 0 0 0 At SMD -T0 0 150 200 200 0 40 M V 20 N"C11" -T1 0 -150 200 200 0 40 M I 20 N"100nF" +T0 0 150 200 200 1800 40 M V 20 N"C11" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 Ne 145 "3.3V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 Ne 146 "GND" @@ -6959,27 +6959,27 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 52953 25787 2700 0 4C5FF890 4C5D7E41 ~~ +Po 52559 25984 1800 0 4C5FF890 4C5D7E41 ~~ Li 0402 Sc 4C5D7E41 AR /4C4320F3/4C5D7E41 Op 0 0 0 At SMD -T0 0 150 200 200 2700 40 M V 20 N"C10" -T1 0 -150 200 200 2700 40 M I 20 N"100nF" +T0 0 150 200 200 1800 40 M V 20 N"C10" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" DS -305 -168 -305 168 50 20 DS -305 168 305 168 50 20 DS 305 168 305 -168 50 20 DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 2700 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 Ne 145 "3.3V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 2700 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 Ne 146 "GND" @@ -6987,27 +6987,27 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 44882 26181 0 15 4C5FF890 4C5D8114 ~~ +Po 49213 27756 1800 15 4C5FF890 4C5D8114 ~~ Li 0402 Sc 4C5D8114 AR /4C4320F3/4C5D8114 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C9" -T1 0 150 200 200 0 40 N I 25 N"C" +T0 0 -150 200 200 1800 40 N V 25 N"C9" +T1 0 150 200 200 1800 40 N I 25 N"C" DS -305 168 -305 -168 50 21 DS -305 -168 305 -168 50 21 DS 305 -168 305 168 50 21 DS 305 168 -305 168 50 21 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 48 "/Etherne4" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 Ne 160 "N-000329" @@ -7031,7 +7031,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 36 "/Ethernet_Phy/ETH_A3.3V" +Ne 45 "/Etherne3" Po -176 0 $EndPAD $PAD @@ -7043,35 +7043,35 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 43110 28543 0 15 4C5FF890 4C5D8104 ~~ +Po 51575 25984 0 0 4C5FF890 4C668981 ~~ Li 0402 -Sc 4C5D8104 +Sc 4C668981 AR /4C4320F3/4C5D8104 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C6" -T1 0 150 200 200 0 40 N I 25 N"C" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 0 40 M V 20 N"C6" +T1 0 -150 200 200 0 40 M I 20 N"C" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_A1.8V" +At SMD N 00440001 +Ne 43 "/Etherne2" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 160 "N-000329" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 43701 26969 0 15 4C5FF890 4C5D7FA3 ~~ +Po 44291 29330 0 15 4C5FF890 4C5D7FA3 ~~ Li 0402 Sc 4C5D7FA3 AR /4C4320F3/4C5D7FA3 @@ -7099,35 +7099,35 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 42732 22984 1800 15 4C5FF890 4C5D80F0 ~~ +Po 51575 26772 1800 0 4C5FF890 4C5D80F0 ~~ Li 0402 Sc 4C5D80F0 AR /4C4320F3/4C5D80F0 Op 0 0 0 At SMD -T0 0 -150 200 200 1800 40 N V 25 N"C4" -T1 0 150 200 200 1800 40 N I 25 N"C" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C4" +T1 0 -150 200 200 1800 40 M I 20 N"C" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 156 "N-000321" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 160 "N-000329" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 47047 23819 0 15 4C5FF890 4C5D7FA1 ~~ +Po 44291 28740 0 15 4C5FF890 4C5D7FA1 ~~ Li 0402 Sc 4C5D7FA1 AR /4C4320F3/4C5D7FA1 @@ -7155,29 +7155,29 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 44685 27559 0 15 4C5FF890 4C5D80ED ~~ +Po 52559 27953 1800 0 4C5FF890 4C5D80ED ~~ Li 0402 Sc 4C5D80ED AR /4C4320F3/4C5D80ED Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C2" -T1 0 150 200 200 0 40 N I 25 N"C" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C2" +T1 0 -150 200 200 1800 40 M I 20 N"C" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 -Ne 34 "/Ethernet_Phy/ETH_1.8V" +At SMD N 00440001 +Ne 34 "/Etherne1" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 146 "GND" Po 176 0 $EndPAD @@ -7239,90 +7239,6 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 41732 23484 0 15 4C5FF890 4C5D810A ~~ -Li 0603 -Sc 4C5D810A -AR /4C4320F3/4C5D810A -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"L3" -T1 0 150 200 200 0 40 N I 25 N"INDUCTOR" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 -$PAD -Sh "1" R 197 354 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_A1.8V" -Po -294 0 -$EndPAD -$PAD -Sh "2" R 197 354 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" -Po 294 0 -$EndPAD -$EndMODULE 0603 -$MODULE 0603 -Po 41732 22984 0 15 4C5FF890 4C5D7FB7 ~~ -Li 0603 -Sc 4C5D7FB7 -AR /4C4320F3/4C5D7FB7 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"L2" -T1 0 150 200 200 0 40 N I 25 N"FB" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 -$PAD -Sh "1" R 197 354 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 145 "3.3V" -Po -294 0 -$EndPAD -$PAD -Sh "2" R 197 354 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_A3.3V" -Po 294 0 -$EndPAD -$EndMODULE 0603 -$MODULE 0603 -Po 45472 24409 0 15 4C5FF890 4C5D80F3 ~~ -Li 0603 -Sc 4C5D80F3 -AR /4C4320F3/4C5D80F3 -Op 0 0 0 -At SMD -T0 0 -150 200 200 0 40 N V 25 N"L1" -T1 0 150 200 200 0 40 N I 25 N"INDUCTOR" -DS -443 227 -443 -227 50 21 -DS -443 -227 443 -227 50 21 -DS 443 -227 443 227 50 21 -DS 443 227 -443 227 50 21 -$PAD -Sh "1" R 197 354 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 156 "N-000321" -Po -294 0 -$EndPAD -$PAD -Sh "2" R 197 354 0 0 0 -Dr 0 0 0 -At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_A1.8V" -Po 294 0 -$EndPAD -$EndMODULE 0603 -$MODULE 0603 Po 59843 22638 1800 15 4C5FF890 4C5F2039 ~~ Li 0603 Sc 4C5F2039 @@ -7423,7 +7339,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_A3.3V" +Ne 45 "/Etherne3" Po -294 0 $EndPAD $PAD @@ -7435,7 +7351,7 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0603 -Po 43504 27756 0 15 4C5FF890 4C5D7F9F ~~ +Po 44291 29921 0 15 4C5FF890 4C5D7F9F ~~ Li 0603 Sc 4C5D7F9F AR /4C4320F3/4C5D7F9F @@ -9507,42 +9423,42 @@ $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/PROG_CSO" +Ne 66 "/FPGA_Sp122" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/PROG_MISO3" +Ne 69 "/FPGA_Sp126" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/PROG_CCLK" +Ne 81 "/FPGA_Sp26" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/PROG_MISO0" +Ne 82 "/FPGA_Sp27" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/PROG_MISO1" +Ne 80 "/FPGA_Sp25" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/PROG_MISO2" +Ne 70 "/FPGA_Sp127" Po 250 1050 $EndPAD $PAD @@ -9699,6 +9615,90 @@ Ne 146 "GND" Po 294 0 $EndPAD $EndMODULE 0603 +$MODULE 0402 +Po 44291 28149 0 15 4C5FF890 4C5D7FB7 ~~ +Li 0402 +Sc 4C5D7FB7 +AR /4C4320F3/4C5D7FB7 +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L2" +T1 0 150 200 200 0 40 N I 25 N"FB" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 145 "3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 45 "/Etherne3" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 51575 26378 1800 0 4C5FF890 4C5D80F3 ~~ +Li 0402 +Sc 4C5D80F3 +AR /4C4320F3/4C5D80F3 +Op 0 0 0 +At SMD +T0 0 150 200 200 1800 40 M V 20 N"L1" +T1 0 -150 200 200 1800 40 M I 20 N"INDUCTOR" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 +$PAD +Sh "1" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 156 "N-000321" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 1800 +Dr 0 0 0 +At SMD N 00440001 +Ne 43 "/Etherne2" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 49213 27362 0 15 4C5FF890 4C5D810A ~~ +Li 0402 +Sc 4C5D810A +AR /4C4320F3/4C5D810A +Op 0 0 0 +At SMD +T0 0 -150 200 200 0 40 N V 25 N"L3" +T1 0 150 200 200 0 40 N I 25 N"INDUCTOR" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 43 "/Etherne2" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 0 +Dr 0 0 0 +At SMD N 00888000 +Ne 48 "/Etherne4" +Po 176 0 +$EndPAD +$EndMODULE 0402 $TEXTPCB Te "otra fuente" Po 65945 22244 600 800 120 0 @@ -9745,7 +9745,7 @@ ZLayer 15 ZAux 4 N ZClearance 200 T ZMinThickness 100 -ZOptions 0 16 F 200 200 +ZOptions 0 16 S 200 200 ZCorner 67126 44685 0 ZCorner 67126 14567 0 ZCorner 45079 14567 0 diff --git a/kicad/xue-rnc/xue-rnc.cmp b/kicad/xue-rnc/xue-rnc.cmp index 64de5c9..8779432 100644 --- a/kicad/xue-rnc/xue-rnc.cmp +++ b/kicad/xue-rnc/xue-rnc.cmp @@ -1,4 +1,4 @@ -Cmp-Mod V01 Created by CvPCB (2010-07-15 BZR 2414)-unstable date = Fri 13 Aug 2010 03:17:50 PM COT +Cmp-Mod V01 Genere par PcbNew le Sat 14 Aug 2010 07:11:10 AM COT BeginCmp TimeStamp = /4C4320F3/4C5D7F9F; @@ -483,6 +483,41 @@ ValeurCmp = 470nF; IdModule = 0402; EndCmp +BeginCmp +TimeStamp = /4C421DD3/4C65D2A9; +Reference = C70; +ValeurCmp = 10nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C421DD3/4C65D28E; +Reference = C71; +ValeurCmp = 10nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C4227FE/4C65D661; +Reference = C72; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C4227FE/4C65D67C; +Reference = C73; +ValeurCmp = 100nF; +IdModule = 0402; +EndCmp + +BeginCmp +TimeStamp = /4C4227FE/4C65D681; +Reference = C74; +ValeurCmp = 1uF; +IdModule = 0603; +EndCmp + BeginCmp TimeStamp = /4C5F1EDC/4C5F2B55; Reference = F1; @@ -522,21 +557,21 @@ BeginCmp TimeStamp = /4C4320F3/4C5D80F3; Reference = L1; ValeurCmp = INDUCTOR; -IdModule = 0603; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D7FB7; Reference = L2; ValeurCmp = FB; -IdModule = 0603; +IdModule = 0402; EndCmp BeginCmp TimeStamp = /4C4320F3/4C5D810A; Reference = L3; ValeurCmp = INDUCTOR; -IdModule = 0603; +IdModule = 0402; EndCmp BeginCmp diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 537ab02..f307de1 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,1221 +1,1376 @@ -# EESchema Netlist Version 1.1 created Fri 13 Aug 2010 07:14:02 PM COT +# EESchema Netlist Version 1.1 created Sat 14 Aug 2010 07:08:24 AM COT ( - ( /4C4227FE/4C65D681 0603 C74 1uF {Lib=CAP} - ( 1 +3.3V ) - ( 2 GND ) + ( /4C4320F3/4C5D7F9F 0603 C1 1uF + ( 1 3.3V ) + ( 2 GND ) ) - ( /4C4227FE/4C65D67C 0402 C73 100nF {Lib=CAP} - ( 1 +3.3V ) - ( 2 GND ) + ( /4C4320F3/4C5D80ED 0402 C2 C + ( 1 /Etherne1 ) + ( 2 GND ) ) - ( /4C4227FE/4C65D661 0402 C72 100nF {Lib=CAP} - ( 1 +3.3V ) - ( 2 GND ) + ( /4C4320F3/4C5D7FA1 0402 C3 100nF + ( 1 3.3V ) + ( 2 GND ) ) - ( /4C4227FE/4C65A75D $noname U8 X25X64MB {Lib=X25X64MB} - ( 1 /FPGA_Spartan6/PROG_CSO ) - ( 2 /FPGA_Spartan6/PROG_MISO1 ) - ( 3 /FPGA_Spartan6/PROG_MISO2 ) - ( 4 GND ) - ( 5 /FPGA_Spartan6/PROG_MISO0 ) - ( 6 /FPGA_Spartan6/PROG_CCLK ) - ( 7 /FPGA_Spartan6/PROG_MISO3 ) - ( 8 VCCO2 ) + ( /4C4320F3/4C5D80F0 0402 C4 C + ( 1 N-000321 ) + ( 2 N-000329 ) ) - ( /4C4227FE/4B76F5E2 $noname J1 MICROSD {Lib=MICROSD} + ( /4C4320F3/4C5D7FA3 0402 C5 100nF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D8104 0402 C6 C + ( 1 /Etherne2 ) + ( 2 N-000329 ) + ) + ( /4C4320F3/4C5D7FA5 0603 C7 1uF + ( 1 /Etherne3 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7FA7 0402 C8 100nF + ( 1 /Etherne3 ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D8114 0402 C9 C + ( 1 /Etherne4 ) + ( 2 N-000329 ) + ) + ( /4C4320F3/4C5D7E41 0402 C10 100nF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7E43 0402 C11 100nF + ( 1 3.3V ) + ( 2 GND ) + ) + ( /4C4320F3/4C5D7DCB 0402 C12 47nF + ( 1 N-000314 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2033 0603 C13 1uF + ( 1 N-000355 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2037 0603 C14 1uF + ( 1 N-000355 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2039 0603 C15 470nF + ( 1 N-000355 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2D1E 0402 C16 4.7nF + ( 1 N-000338 ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CC73 0402 C17 100nF + ( 1 +2.5V ) + ( 2 N-000052 ) + ) + ( /4C421DD3/4C61CC96 0402 C18 100nF + ( 1 N-000052 ) + ( 2 N-000054 ) + ) + ( /4C421DD3/4C61CCE3 0402 C19 100nF + ( 1 +2.5V ) + ( 2 N-000051 ) + ) + ( /4C421DD3/4C61CCE2 0402 C20 100nF + ( 1 N-000051 ) + ( 2 N-000050 ) + ) + ( /4C421DD3/4C61CF2F 0603 C21 1uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CEB9 0402 C22 100nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CEF7 0402 C23 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF17 0402 C24 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF16 0402 C25 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CF27 0402 C26 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA0 0603 C27 1uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA5 0402 C28 100nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA4 0402 C29 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA2 0402 C30 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA3 0402 C31 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61CFA1 0402 C32 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61D151 1206 C33 10uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C61D1D4 1206 C34 10uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C6552BE 0805 C35 1uF + ( 1 N-000351 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C6552BD 0805 C36 1uF + ( 1 N-000351 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C6552BC 0402 C37 470nF + ( 1 N-000351 ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C6552B7 0402 C38 4.7nF + ( 1 N-000352 ) + ( 2 GND ) + ) + ( /4C431A63/4C656A80 1210 C39 100uF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C656BF8 1210 C40 100uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CB7 1210 C41 100uF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656ABD 0805 C42 4.7uF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C656BF9 0805 C43 4.7uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CB9 0805 C44 4.7uF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656AC0 0402 C45 470nF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C16 0805 C46 4.7uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CBA 0402 C47 470nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656AC2 0402 C48 470nF + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C24 0402 C49 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656CBB 0402 C50 470nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C27 0402 C51 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656BFA 0402 C52 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656C49 0402 C53 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D97 1210 C54 100uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D43 1210 C55 100uF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656CF9 1210 C56 100uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D98 0805 C57 4.7uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D44 0805 C58 4.7uF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656CFA 0805 C59 4.7uF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D99 0402 C60 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D45 0402 C61 470nF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656CFB 0402 C62 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D9A 0402 C63 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D46 0402 C64 470nF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656CFC 0402 C65 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D9D 0402 C66 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D49 0402 C67 470nF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C431A63/4C656D08 0402 C68 470nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C431A63/4C656D53 0402 C69 470nF + ( 1 VCCO2 ) + ( 2 GND ) + ) + ( /4C421DD3/4C65D2A9 0402 C70 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C421DD3/4C65D28E 0402 C71 10nF + ( 1 +2.5V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65D661 0402 C72 100nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65D67C 0402 C73 100nF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C4227FE/4C65D681 0603 C74 1uF + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C5F1EDC/4C5F2B55 1210 F1 MICROSMD075F + ( 1 N-000354 ) + ( 2 +5V ) + ) + ( /4C5F1EDC/4C6552BA 1210 F2 MICROSMD075F + ( 1 N-000339 ) + ( 2 +5V ) + ) + ( /4C4227FE/4B76F5E2 MICROSD-500901 J1 MICROSD + ( 1 /Non_vol5 ) + ( 2 /Non_vol6 ) + ( 3 /FPGA_Sp7 ) + ( 4 ? ) + ( 5 /FPGA_Sp8 ) + ( 6 GND ) + ( 7 /Non_vol9 ) + ( 8 /FPGA_Sp10 ) ( CASE GND ) - ( COM GND ) - ( CD ? ) - ( 1 /Non_volatile_memories/SD_DAT2 ) - ( 2 /Non_volatile_memories/SD_DAT3 ) - ( 3 /FPGA_Spartan6/SD_CMD ) - ( 4 ? ) - ( 5 /FPGA_Spartan6/SD_CLK ) - ( 6 GND ) - ( 7 /Non_volatile_memories/SD_DAT0 ) - ( 8 /FPGA_Spartan6/SD_DAT1 ) + ( CD ? ) + ( COM GND ) ) - ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} - ( 1 ? ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 6 /FPGA_Spartan6/NF_RNB ) - ( 7 /FPGA_Spartan6/NF_RNB ) - ( 8 /FPGA_Spartan6/NF_RE_N ) - ( 9 /Non_volatile_memories/NF_CS1_N ) - ( 10 ? ) - ( 11 ? ) - ( 12 3.3V ) - ( 13 GND ) - ( 14 ? ) - ( 15 ? ) - ( 16 /Non_volatile_memories/NF_CLE ) - ( 17 /FPGA_Spartan6/NF_ALE ) - ( 18 /Non_volatile_memories/NF_WE_N ) - ( 19 3.3V ) - ( 20 ? ) - ( 21 ? ) - ( 22 ? ) - ( 23 ? ) - ( 24 ? ) - ( 25 ? ) - ( 26 ? ) - ( 27 ? ) - ( 28 ? ) - ( 29 /Non_volatile_memories/NF_D0 ) - ( 30 /Non_volatile_memories/NF_D1 ) - ( 31 /FPGA_Spartan6/NF_D2 ) - ( 32 /Non_volatile_memories/NF_D3 ) - ( 33 ? ) - ( 34 ? ) - ( 35 ? ) - ( 36 GND ) - ( 37 +3.3V ) - ( 38 ? ) - ( 39 ? ) - ( 40 ? ) - ( 41 /Non_volatile_memories/NF_D4 ) - ( 42 /Non_volatile_memories/NF_D5 ) - ( 43 /Non_volatile_memories/NF_D6 ) - ( 44 /Non_volatile_memories/NF_D7 ) - ( 45 ? ) - ( 46 ? ) - ( 47 ? ) - ( 48 ? ) + ( /4C4320F3/4C5D6F5A SD-48025 J4 RJ45-48025 + ( 1 N-000317 ) + ( 2 N-000328 ) + ( 3 3.3V ) + ( 4 GND ) + ( 5 GND ) + ( 6 3.3V ) + ( 7 N-000318 ) + ( 8 N-000327 ) + ( 9 3.3V ) + ( 10 N-000315 ) + ( 11 3.3V ) + ( 12 N-000331 ) + ( 13 N-000314 ) + ( 14 N-000314 ) ) - ( /4C5F1EDC/4C6552BF $noname U7 MIC2550AYTS {Lib=MIC2550AYTS} - ( 1 +2.5V ) - ( 2 ? ) - ( 3 ? ) - ( 4 ? ) - ( 5 ? ) - ( 7 GND ) - ( 8 GND ) - ( 9 ? ) - ( 10 N-000350 ) - ( 11 N-000345 ) - ( 12 3.3V ) - ( 14 3.3V ) + ( /4C5F1EDC/4C5F23DD USB-48204 J5 USB-48204-0001 + ( 1 N-000353 ) + ( 2 N-000337 ) + ( 3 N-000356 ) + ( 4 N-000349 ) + ( S1 N-000338 ) + ( S2 N-000338 ) + ( S3 N-000338 ) + ( S4 N-000338 ) ) - ( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C} - ( 1 N-000351 ) - ( 2 GND ) + ( /4C4320F3/4C5D80F3 0402 L1 INDUCTOR + ( 1 N-000321 ) + ( 2 /Etherne2 ) ) - ( /4C5F1EDC/4C6552BD $noname C36 1uF {Lib=C} - ( 1 N-000351 ) - ( 2 GND ) + ( /4C4320F3/4C5D7FB7 0402 L2 FB + ( 1 3.3V ) + ( 2 /Etherne3 ) ) - ( /4C5F1EDC/4C6552BC $noname C37 470nF {Lib=C} - ( 1 N-000351 ) - ( 2 GND ) + ( /4C4320F3/4C5D810A 0402 L3 INDUCTOR + ( 1 /Etherne2 ) + ( 2 /Etherne4 ) ) - ( /4C5F1EDC/4C6552BA $noname F2 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000339 ) - ( 2 +5V ) + ( /4C5F1EDC/4C63F252 0603 L4 FB + ( 1 N-000354 ) + ( 2 N-000353 ) ) - ( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000350 ) - ( 2 GND ) + ( /4C5F1EDC/4C63F248 0603 L5 FB + ( 1 N-000349 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000345 ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B0 0603 L6 FB + ( 1 N-000339 ) + ( 2 ? ) ) - ( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C} - ( 1 N-000352 ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B1 0603 L7 FB + ( 1 ? ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R} - ( 1 N-000352 ) - ( 2 GND ) + ( /4C4320F3/4C5D7F39 0402 R1 4.7K + ( 1 /Etherne11 ) + ( 2 3.3V ) ) - ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} - ( 1 ? ) - ( 2 GND ) + ( /4C4320F3/4C5D7ECF 0402 R2 6.65K + ( 1 N-000326 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C6552B0 0603 L6 FB {Lib=INDUCTOR} - ( 1 N-000339 ) - ( 2 ? ) + ( /4C4320F3/4C5D7AFE 0402 R3 49.9 + ( 1 3.3V ) + ( 2 N-000317 ) ) - ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000354 ) - ( 2 N-000353 ) + ( /4C4320F3/4C5D7AFC 0402 R4 49.9 + ( 1 3.3V ) + ( 2 N-000328 ) ) - ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000349 ) - ( 2 GND ) + ( /4C4320F3/4C5D7AF7 0402 R5 49.9 + ( 1 3.3V ) + ( 2 N-000318 ) ) - ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000338 ) - ( 2 GND ) + ( /4C4320F3/4C5D7AF9 0402 R6 49.9 + ( 1 3.3V ) + ( 2 N-000327 ) ) - ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000338 ) - ( 2 GND ) + ( /4C4320F3/4C5D719D 0402 R7 220 + ( 1 N-000315 ) + ( 2 /Etherne12 ) ) - ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000356 ) - ( 2 GND ) + ( /4C4320F3/4C5D71DB 0402 R8 220 + ( 1 N-000331 ) + ( 2 /Etherne13 ) ) - ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000337 ) - ( 2 GND ) + ( /4C4320F3/4C5D7DC4 0402 R9 1M + ( 1 N-000314 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000354 ) - ( 2 +5V ) + ( /4C5F1EDC/4C5F2D27 0402 R10 1M + ( 1 N-000338 ) + ( 2 GND ) ) - ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000338 ) - ( S2 N-000338 ) - ( S3 N-000338 ) - ( S4 N-000338 ) - ( 1 N-000353 ) - ( 2 N-000337 ) - ( 3 N-000356 ) - ( 4 N-000349 ) + ( /4C421DD3/4C61CD4A 0402 R11 1K_1% + ( 1 +2.5V ) + ( 2 N-000052 ) ) - ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} - ( 1 N-000355 ) - ( 2 GND ) + ( /4C421DD3/4C61CDB5 0402 R12 1K_1% + ( 1 N-000052 ) + ( 2 N-000054 ) ) - ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} - ( 1 N-000355 ) - ( 2 GND ) + ( /4C421DD3/4C61CE31 0402 R13 1K_1% + ( 1 +2.5V ) + ( 2 N-000051 ) ) - ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} - ( 1 N-000355 ) - ( 2 GND ) + ( /4C421DD3/4C61CE30 0402 R14 1K_1% + ( 1 N-000051 ) + ( 2 N-000050 ) ) - ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} - ( 1 +2.5V ) - ( 2 /USB/USBA_SPD ) - ( 3 /FPGA_Spartan6/USBA_RCV ) - ( 4 /USB/USBA_VP ) - ( 5 /USB/USBA_VM ) - ( 7 GND ) - ( 8 GND ) - ( 9 /FPGA_Spartan6/USBA_OE_N ) - ( 10 N-000337 ) - ( 11 N-000356 ) - ( 12 3.3V ) - ( 14 3.3V ) + ( /4C5F1EDC/4C6552B6 0402 R15 1M + ( 1 N-000352 ) + ( 2 GND ) ) - ( /4C431A63/4C656D9D $noname C66 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D9A $noname C63 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D99 $noname C60 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D98 $noname C57 4.7uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D97 $noname C54 100uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656D53 $noname C69 470nF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656D49 $noname C67 470nF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656D46 $noname C64 470nF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656D45 $noname C61 470nF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656D44 $noname C58 4.7uF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656D43 $noname C55 100uF {Lib=C} - ( 1 VCCO2 ) - ( 2 GND ) - ) - ( /4C431A63/4C656D08 $noname C68 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CFC $noname C65 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CFB $noname C62 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CFA $noname C59 4.7uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CF9 $noname C56 100uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CBB $noname C50 470nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CBA $noname C47 470nF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CB9 $noname C44 4.7uF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656CB7 $noname C41 100uF {Lib=C} - ( 1 +3.3V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C49 $noname C53 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C27 $noname C51 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C24 $noname C49 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656C16 $noname C46 4.7uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656BFA $noname C52 470nF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656BF9 $noname C43 4.7uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656BF8 $noname C40 100uF {Lib=C} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C431A63/4C656AC2 $noname C48 470nF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656AC0 $noname C45 470nF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656ABD $noname C42 4.7uF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C656A80 $noname C39 100uF {Lib=C} - ( 1 +1.2V ) - ( 2 GND ) - ) - ( /4C431A63/4C431E53 $noname U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484} - ( P7 ? ) - ( N7 ? ) - ( M7 ? ) - ( L7 +2.5V ) - ( K7 ? ) - ( J7 ? ) - ( G7 ? ) - ( F7 ? ) - ( P6 ? ) - ( N6 ? ) - ( M6 ? ) - ( L6 ? ) - ( K6 /DDR_Banks/M0_A3 ) - ( J6 ? ) - ( H6 /FPGA_Spartan6/M0_A7 ) - ( G6 ? ) - ( F6 +2.5V ) - ( E6 ? ) - ( U5 +2.5V ) - ( P5 ? ) - ( N5 +2.5V ) - ( M5 ? ) - ( K5 /FPGA_Spartan6/M0_RAS# ) - ( J5 +2.5V ) - ( H5 /FPGA_Spartan6/M0_A2 ) - ( F5 ? ) - ( E5 ? ) - ( D5 ? ) - ( U4 ? ) - ( H21 /DDR_Banks/M1_RAS# ) - ( G21 +2.5V ) - ( F21 /DDR_Banks/M1_A0 ) - ( D21 /FPGA_Spartan6/M1_CKE ) - ( C21 +2.5V ) - ( B21 ? ) - ( A21 ? ) - ( W20 ? ) - ( V20 ? ) - ( U20 /FPGA_Spartan6/M1_DQ12 ) - ( T20 ? ) - ( R20 /DDR_Banks/M1_DQ10 ) - ( P20 ? ) - ( N20 /FPGA_Spartan6/M1_DQ0 ) - ( M20 /FPGA_Spartan6/M1_UDM ) - ( L20 /FPGA_Spartan6/M1_LDQS ) - ( K20 /FPGA_Spartan6/M1_A5 ) - ( J20 /DDR_Banks/M1_DQ4 ) - ( H20 /FPGA_Spartan6/M1_CLK ) - ( G20 /FPGA_Spartan6/M1_A3 ) - ( F20 /FPGA_Spartan6/M1_A4 ) - ( E20 /FPGA_Spartan6/M1_A7 ) - ( D20 ? ) - ( C20 /FPGA_Spartan6/M1_A8 ) - ( B20 ? ) - ( A20 ? ) - ( P8 ? ) - ( M8 ? ) - ( K8 ? ) - ( H8 ? ) - ( B3 ? ) - ( W2 +2.5V ) - ( V2 /FPGA_Spartan6/M0_DQ14 ) - ( T2 /DDR_Banks/M0_UDQS ) - ( R2 +2.5V ) - ( P2 /DDR_Banks/M0_DQ8 ) - ( M2 /DDR_Banks/M0_DQ2 ) - ( L2 +2.5V ) - ( K2 /DDR_Banks/M0_DQ6 ) - ( H2 /DDR_Banks/M0_A0 ) - ( G2 +2.5V ) - ( F2 /DDR_Banks/M0_WE# ) - ( D2 /FPGA_Spartan6/M0_CKE ) - ( C2 +2.5V ) - ( B2 ? ) - ( A2 ? ) - ( Y1 ? ) - ( W1 ? ) - ( V1 /FPGA_Spartan6/M0_DQ15 ) - ( U1 /DDR_Banks/M0_DQ13 ) - ( T1 ? ) - ( R1 /FPGA_Spartan6/M0_DQ11 ) - ( P1 /DDR_Banks/M0_DQ9 ) - ( N1 /FPGA_Spartan6/M0_DQ1 ) - ( M1 /FPGA_Spartan6/M0_DQ3 ) - ( L1 ? ) - ( K1 /FPGA_Spartan6/M0_DQ7 ) - ( J1 /DDR_Banks/M0_DQ5 ) - ( H1 /FPGA_Spartan6/M0_A1 ) - ( G1 /DDR_Banks/M0_BA1 ) - ( T4 ? ) - ( R4 ? ) - ( P4 ? ) - ( N4 ? ) - ( M4 ? ) - ( L4 /DDR_Banks/M0_LDM ) - ( K4 /FPGA_Spartan6/M0_CAS# ) - ( J4 /FPGA_Spartan6/M0_A6 ) - ( H4 /FPGA_Spartan6/M0_CLK ) - ( G4 /DDR_Banks/M0_A10 ) - ( F4 +2.5V ) - ( E4 ? ) - ( C4 ? ) - ( W3 ? ) - ( V3 ? ) - ( U3 /FPGA_Spartan6/M0_DQ12 ) - ( T3 ? ) - ( R3 /FPGA_Spartan6/M0_DQ10 ) - ( P3 ? ) - ( N3 /DDR_Banks/M0_DQ0 ) - ( M3 /DDR_Banks/M0_UDM ) - ( L3 /DDR_Banks/M0_LDQS ) - ( K3 /FPGA_Spartan6/M0_A5 ) - ( J3 /DDR_Banks/M0_DQ4 ) - ( H3 /FPGA_Spartan6/M0_CLK# ) - ( G3 /FPGA_Spartan6/M0_BA0 ) - ( F3 /FPGA_Spartan6/M0_A4 ) - ( E3 /DDR_Banks/M0_A8 ) - ( D3 ? ) - ( C3 ? ) - ( G10 +3.3V ) - ( D10 /Ethernet_Phy/ETH_RXC ) - ( C10 /Ethernet_Phy/ETH_CLK ) - ( B10 /FPGA_Spartan6/ETH_CRS ) - ( A10 /Ethernet_Phy/ETH_COL ) - ( E9 +3.3V ) - ( D9 /FPGA_Spartan6/ETH_TXEN ) - ( C9 /FPGA_Spartan6/ETH_TXD1 ) - ( A9 /FPGA_Spartan6/ETH_TXD2 ) - ( D8 /Ethernet_Phy/ETH_TXC ) - ( C8 /Ethernet_Phy/ETH_TXD0 ) - ( B8 /Ethernet_Phy/ETH_RXER ) - ( A8 /Ethernet_Phy/ETH_TXER ) - ( D7 /Ethernet_Phy/ETH_TXD3 ) - ( C7 /FPGA_Spartan6/ETH_RXD0 ) - ( B7 +3.3V ) - ( A7 /Ethernet_Phy/ETH_RXDV ) - ( D6 /FPGA_Spartan6/ETH_RESET_N ) - ( C6 /FPGA_Spartan6/ETH_RXD3 ) - ( B6 /FPGA_Spartan6/ETH_RXD2 ) - ( A6 /Ethernet_Phy/ETH_RXD1 ) - ( C5 /FPGA_Spartan6/ETH_MDC ) - ( A5 /Ethernet_Phy/ETH_MDIO ) - ( B4 +3.3V ) - ( A4 /Ethernet_Phy/ETH_INT ) - ( U19 ? ) - ( T19 ? ) - ( R19 /USB/USBA_SPD ) - ( P19 ? ) - ( N19 ? ) - ( B19 +3.3V ) - ( B18 /FPGA_Spartan6/SD_DAT1 ) - ( A18 /Non_volatile_memories/SD_DAT0 ) - ( E17 +3.3V ) - ( D17 /FPGA_Spartan6/SD_CMD ) - ( C17 /Non_volatile_memories/SD_DAT3 ) - ( A17 /Non_volatile_memories/SD_DAT2 ) - ( E16 /FPGA_Spartan6/SD_CLK ) - ( C16 /Non_volatile_memories/NF_CS1_N ) - ( B16 /FPGA_Spartan6/NF_RE_N ) - ( A16 /FPGA_Spartan6/NF_RNB ) - ( D15 /Non_volatile_memories/NF_CLE ) - ( C15 /Non_volatile_memories/NF_WE_N ) - ( B15 +3.3V ) - ( A15 /FPGA_Spartan6/NF_ALE ) - ( G14 +3.3V ) - ( D14 /Non_volatile_memories/NF_D0 ) - ( C14 ? ) - ( B14 ? ) - ( A14 ? ) - ( E13 +3.3V ) - ( C13 /FPGA_Spartan6/NF_D2 ) - ( A13 /Non_volatile_memories/NF_D1 ) - ( C12 /Non_volatile_memories/NF_D5 ) - ( B12 /Non_volatile_memories/NF_D4 ) - ( A12 /Non_volatile_memories/NF_D3 ) - ( D11 /Non_volatile_memories/NF_D6 ) - ( C11 ? ) - ( B11 +3.3V ) - ( A11 /Non_volatile_memories/NF_D7 ) - ( H16 ? ) - ( G16 ? ) - ( F16 ? ) - ( L15 ? ) - ( W22 ? ) - ( V22 /FPGA_Spartan6/M1_DQ15 ) - ( U22 /FPGA_Spartan6/M1_DQ13 ) - ( T22 ? ) - ( R22 /DDR_Banks/M1_DQ11 ) - ( P22 /FPGA_Spartan6/M1_DQ9 ) - ( N22 /FPGA_Spartan6/M1_DQ1 ) - ( M22 /DDR_Banks/M1_DQ3 ) - ( L22 ? ) - ( K22 /FPGA_Spartan6/M1_DQ7 ) - ( J22 /FPGA_Spartan6/M1_DQ5 ) - ( H22 /FPGA_Spartan6/M1_CAS# ) - ( G22 ? ) - ( F22 /FPGA_Spartan6/M1_A1 ) - ( E22 /FPGA_Spartan6/M1_A2 ) - ( D22 /DDR_Banks/M1_A12 ) - ( C22 /FPGA_Spartan6/M1_A9 ) - ( B22 ? ) - ( W21 +2.5V ) - ( V21 /FPGA_Spartan6/M1_DQ14 ) - ( T21 /FPGA_Spartan6/M1_UDQS ) - ( R21 +2.5V ) - ( P21 /FPGA_Spartan6/M1_DQ8 ) - ( M21 /FPGA_Spartan6/M1_DQ2 ) - ( L21 +2.5V ) - ( K21 /FPGA_Spartan6/M1_DQ6 ) - ( M19 ? ) - ( L19 /DDR_Banks/M1_LDM ) - ( K19 /FPGA_Spartan6/M1_A6 ) - ( J19 /FPGA_Spartan6/M1_CLK# ) - ( H19 /FPGA_Spartan6/M1_WE# ) - ( G19 /FPGA_Spartan6/M1_A10 ) - ( F19 /FPGA_Spartan6/M1_A11 ) - ( E19 +2.5V ) - ( D19 ? ) - ( U18 +2.5V ) - ( P18 /FPGA_Spartan6/USBA_OE_N ) - ( N18 +2.5V ) - ( M18 /USB/USBA_VM ) - ( K18 ? ) - ( J18 +2.5V ) - ( H18 ? ) - ( F18 ? ) - ( P17 /USB/USBA_VP ) - ( M17 ? ) - ( L17 ? ) - ( K17 /DDR_Banks/M1_BA1 ) - ( J17 /DDR_Banks/M1_BA0 ) - ( H17 ? ) - ( G17 ? ) - ( F17 ? ) - ( N16 /FPGA_Spartan6/USBA_RCV ) - ( M16 ? ) - ( L16 +2.5V ) - ( K16 ? ) - ( J16 ? ) - ( J14 +1.2V ) - ( H14 ? ) - ( F14 ? ) - ( E14 ? ) - ( P13 +1.2V ) - ( N13 GND ) - ( M13 +1.2V ) - ( L13 GND ) - ( K13 +1.2V ) - ( J13 GND ) - ( H13 ? ) - ( G13 ? ) - ( F13 ? ) - ( D13 ? ) - ( B13 GND ) - ( Y22 ? ) - ( A22 GND ) - ( R12 +2.5V ) - ( P12 GND ) - ( N12 +1.2V ) - ( M12 GND ) - ( L12 +1.2V ) - ( K12 GND ) - ( J12 +1.2V ) - ( H12 ? ) - ( G12 +2.5V ) - ( F12 ? ) - ( E12 ? ) - ( D12 ? ) - ( AB1 GND ) - ( A19 ? ) - ( R18 GND ) - ( L18 GND ) - ( G18 GND ) - ( E18 ? ) - ( D18 GND ) - ( C18 ? ) - ( R17 ? ) - ( N17 GND ) - ( B17 GND ) - ( W16 GND ) - ( P16 ? ) - ( D16 +2.5V ) - ( AA5 GND ) - ( P15 ? ) - ( N15 ? ) - ( M15 +2.5V ) - ( K15 +2.5V ) - ( J15 GND ) - ( H15 +2.5V ) - ( G15 ? ) - ( F15 ? ) - ( E15 GND ) - ( V14 GND ) - ( R14 +1.2V ) - ( P14 GND ) - ( N14 +1.2V ) - ( M14 GND ) - ( L14 +1.2V ) - ( K14 GND ) - ( L9 GND ) - ( K9 +1.2V ) - ( J9 GND ) - ( H9 +2.5V ) - ( G9 ? ) - ( F9 ? ) - ( B9 GND ) - ( N8 +2.5V ) - ( L8 +2.5V ) - ( J8 +1.2V ) - ( G8 ? ) - ( F8 ? ) - ( E8 ? ) - ( W7 GND ) - ( U7 GND ) - ( H7 GND ) - ( E7 GND ) - ( V6 +2.5V ) - ( R6 +2.5V ) - ( R5 GND ) - ( L5 GND ) - ( G5 GND ) - ( B5 GND ) - ( V4 GND ) - ( D4 GND ) - ( U2 GND ) - ( N2 GND ) - ( J2 GND ) - ( E2 GND ) - ( A1 GND ) - ( AA1 ? ) - ( U21 GND ) - ( N21 GND ) - ( J21 GND ) - ( E21 GND ) - ( U11 +2.5V ) - ( P11 +1.2V ) - ( N11 GND ) - ( M11 +1.2V ) - ( L11 GND ) - ( K11 +1.2V ) - ( J11 GND ) - ( H11 ? ) - ( G11 ? ) - ( F11 +2.5V ) - ( E11 GND ) - ( V10 GND ) - ( R10 +2.5V ) - ( P10 GND ) - ( N10 +1.2V ) - ( M10 GND ) - ( L10 +1.2V ) - ( K10 GND ) - ( J10 +1.2V ) - ( H10 ? ) - ( F10 ? ) - ( E10 ? ) - ( P9 +1.2V ) - ( N9 GND ) - ( M9 +1.2V ) - ( V19 ? ) - ( AB8 ? ) - ( AA8 ? ) - ( Y18 ? ) - ( W18 ? ) - ( V18 ? ) - ( T18 ? ) - ( AB7 ? ) - ( AA7 N-000147 ) - ( Y17 ? ) - ( W17 ? ) - ( V17 ? ) - ( U17 ? ) - ( T17 ? ) - ( AB6 ? ) - ( AA6 ? ) - ( Y16 ? ) - ( V16 N-000147 ) - ( U16 ? ) - ( T16 ? ) - ( R16 ? ) - ( AB5 ? ) - ( Y15 ? ) - ( W15 ? ) - ( V15 ? ) - ( U15 ? ) - ( T15 ? ) - ( R15 ? ) - ( AB4 ? ) - ( AA4 ? ) - ( F1 ? ) - ( E1 /FPGA_Spartan6/M0_A9 ) - ( D1 /FPGA_Spartan6/M0_A12 ) - ( C1 /DDR_Banks/M0_A11 ) - ( B1 ? ) - ( AB19 ? ) - ( AA19 N-000147 ) - ( AB18 ? ) - ( AA18 ? ) - ( AB17 ? ) - ( AB16 ? ) - ( AA16 ? ) - ( AB15 ? ) - ( AA15 N-000147 ) - ( AB14 ? ) - ( AA14 ? ) - ( AB13 ? ) - ( AA22 ? ) - ( AB12 ? ) - ( AA12 ? ) - ( AB21 ? ) - ( AA21 /FPGA_Spartan6/PROG_CCLK ) - ( AB11 ? ) - ( AA11 N-000147 ) - ( AB20 /FPGA_Spartan6/PROG_MISO0 ) - ( AA20 /FPGA_Spartan6/PROG_MISO1 ) - ( AB10 ? ) + ( /4C431A63/4C431E53 FGG484bga-p10 U1 XC6SLX45FGG484 + ( A1 GND ) + ( A2 ? ) + ( A4 /Etherne14 ) + ( A5 /Etherne11 ) + ( A6 /Etherne15 ) + ( A7 /Etherne16 ) + ( A8 /Etherne17 ) + ( A9 /FPGA_Sp18 ) + ( A10 /Etherne19 ) + ( A11 /Non_vol20 ) + ( A12 /Non_vol21 ) + ( A13 /Non_vol22 ) + ( A14 ? ) + ( A15 /FPGA_Sp23 ) + ( A16 /FPGA_Sp24 ) + ( A17 /Non_vol5 ) + ( A18 /Non_vol9 ) + ( A19 ? ) + ( A20 ? ) + ( A21 ? ) + ( A22 GND ) + ( AA1 ? ) + ( AA2 ? ) + ( AA3 N-000147 ) + ( AA4 ? ) + ( AA5 GND ) + ( AA6 ? ) + ( AA7 N-000147 ) + ( AA8 ? ) + ( AA9 GND ) ( AA10 ? ) - ( AB9 ? ) - ( Y19 ? ) - ( V9 ? ) - ( U9 ? ) - ( T9 N-000147 ) - ( R9 ? ) - ( Y8 ? ) - ( W8 ? ) - ( V8 N-000147 ) - ( U8 ? ) - ( T8 ? ) - ( R8 ? ) - ( Y7 ? ) - ( V7 ? ) - ( T7 ? ) - ( R7 ? ) - ( Y6 ? ) - ( W6 ? ) - ( U6 ? ) - ( T6 ? ) - ( Y5 ? ) - ( W5 N-000147 ) - ( V5 ? ) - ( T5 /FPGA_Spartan6/PROG_CSO ) - ( Y4 ? ) - ( W4 ? ) - ( Y3 ? ) - ( AA17 GND ) + ( AA11 N-000147 ) + ( AA12 ? ) ( AA13 GND ) + ( AA14 ? ) + ( AA15 N-000147 ) + ( AA16 ? ) + ( AA17 GND ) + ( AA18 ? ) + ( AA19 N-000147 ) + ( AA20 /FPGA_Sp25 ) + ( AA21 /FPGA_Sp26 ) + ( AA22 ? ) + ( AB1 GND ) + ( AB2 ? ) + ( AB3 ? ) + ( AB4 ? ) + ( AB5 ? ) + ( AB6 ? ) + ( AB7 ? ) + ( AB8 ? ) + ( AB9 ? ) + ( AB10 ? ) + ( AB11 ? ) + ( AB12 ? ) + ( AB13 ? ) + ( AB14 ? ) + ( AB15 ? ) + ( AB16 ? ) + ( AB17 ? ) + ( AB18 ? ) + ( AB19 ? ) + ( AB20 /FPGA_Sp27 ) + ( AB21 ? ) ( AB22 GND ) - ( AA9 GND ) - ( W19 GND ) - ( Y14 ? ) - ( W14 ? ) - ( U14 /FPGA_Spartan6/PROG_MISO2 ) - ( T14 ? ) - ( AB3 ? ) - ( AA3 N-000147 ) - ( Y13 ? ) - ( W13 ? ) - ( V13 ? ) - ( U13 /FPGA_Spartan6/PROG_MISO3 ) - ( T13 N-000147 ) - ( R13 ? ) - ( AB2 ? ) - ( AA2 ? ) - ( Y12 ? ) - ( W12 ? ) - ( V12 N-000147 ) - ( U12 ? ) - ( T12 ? ) - ( Y11 ? ) - ( W11 ? ) - ( V11 ? ) - ( T11 ? ) - ( R11 ? ) - ( Y10 ? ) - ( W10 ? ) - ( U10 ? ) - ( T10 ? ) - ( Y9 ? ) - ( W9 ? ) + ( B1 ? ) + ( B2 ? ) + ( B3 ? ) + ( B4 +3.3V ) + ( B5 GND ) + ( B6 /FPGA_Sp28 ) + ( B7 +3.3V ) + ( B8 /Etherne29 ) + ( B9 GND ) + ( B10 /FPGA_Sp30 ) + ( B11 +3.3V ) + ( B12 /Non_vol31 ) + ( B13 GND ) + ( B14 ? ) + ( B15 +3.3V ) + ( B16 /FPGA_Sp32 ) + ( B17 GND ) + ( B18 /FPGA_Sp10 ) + ( B19 +3.3V ) + ( B20 ? ) + ( B21 ? ) + ( B22 ? ) + ( C1 /DDR_Ban33 ) + ( C2 +2.5V ) + ( C3 ? ) + ( C4 ? ) + ( C5 /FPGA_Sp34 ) + ( C6 /FPGA_Sp35 ) + ( C7 /FPGA_Sp36 ) + ( C8 /Etherne37 ) + ( C9 /FPGA_Sp38 ) + ( C10 /Etherne39 ) + ( C11 ? ) + ( C12 /Non_vol40 ) + ( C13 /FPGA_Sp41 ) + ( C14 ? ) + ( C15 /Non_vol42 ) + ( C16 /Non_vol43 ) + ( C17 /Non_vol6 ) + ( C18 ? ) + ( C20 /FPGA_Sp44 ) + ( C21 +2.5V ) + ( C22 /FPGA_Sp45 ) + ( D1 /FPGA_Sp46 ) + ( D2 /FPGA_Sp47 ) + ( D3 ? ) + ( D4 GND ) + ( D5 ? ) + ( D6 /FPGA_Sp48 ) + ( D7 /Etherne49 ) + ( D8 /Etherne50 ) + ( D9 /FPGA_Sp51 ) + ( D10 /Etherne52 ) + ( D11 /Non_vol53 ) + ( D12 ? ) + ( D13 ? ) + ( D14 /Non_vol54 ) + ( D15 /Non_vol55 ) + ( D16 +2.5V ) + ( D17 /FPGA_Sp7 ) + ( D18 GND ) + ( D19 ? ) + ( D20 ? ) + ( D21 /FPGA_Sp56 ) + ( D22 /DDR_Ban57 ) + ( E1 /FPGA_Sp58 ) + ( E2 GND ) + ( E3 /DDR_Banks/M0_A8 ) + ( E4 ? ) + ( E5 ? ) + ( E6 ? ) + ( E7 GND ) + ( E8 ? ) + ( E9 +3.3V ) + ( E10 ? ) + ( E11 GND ) + ( E12 ? ) + ( E13 +3.3V ) + ( E14 ? ) + ( E15 GND ) + ( E16 /FPGA_Sp8 ) + ( E17 +3.3V ) + ( E18 ? ) + ( E19 +2.5V ) + ( E20 /FPGA_Sp59 ) + ( E21 GND ) + ( E22 /FPGA_Sp60 ) + ( F1 ? ) + ( F2 /DDR_Ban61 ) + ( F3 /FPGA_Sp62 ) + ( F4 +2.5V ) + ( F5 ? ) + ( F6 +2.5V ) + ( F7 ? ) + ( F8 ? ) + ( F9 ? ) + ( F10 ? ) + ( F11 +2.5V ) + ( F12 ? ) + ( F13 ? ) + ( F14 ? ) + ( F15 ? ) + ( F16 ? ) + ( F17 ? ) + ( F18 ? ) + ( F19 /FPGA_Sp63 ) + ( F20 /FPGA_Sp64 ) + ( F21 /DDR_Banks/M1_A0 ) + ( F22 /FPGA_Sp65 ) + ( G1 /DDR_Ban66 ) + ( G2 +2.5V ) + ( G3 /FPGA_Sp67 ) + ( G4 /DDR_Ban68 ) + ( G5 GND ) + ( G6 ? ) + ( G7 ? ) + ( G8 ? ) + ( G9 ? ) + ( G10 +3.3V ) + ( G11 ? ) + ( G12 +2.5V ) + ( G13 ? ) + ( G14 +3.3V ) + ( G15 ? ) + ( G16 ? ) + ( G17 ? ) + ( G18 GND ) + ( G19 /FPGA_Sp69 ) + ( G20 /FPGA_Sp70 ) + ( G21 +2.5V ) + ( G22 ? ) + ( H1 /FPGA_Sp71 ) + ( H2 /DDR_Banks/M0_A0 ) + ( H3 /FPGA_Sp72 ) + ( H4 /FPGA_Sp73 ) + ( H5 /FPGA_Sp74 ) + ( H6 /FPGA_Sp75 ) + ( H7 GND ) + ( H8 ? ) + ( H9 +2.5V ) + ( H10 ? ) + ( H11 ? ) + ( H12 ? ) + ( H13 ? ) + ( H14 ? ) + ( H15 +2.5V ) + ( H16 ? ) + ( H17 ? ) + ( H18 ? ) + ( H19 /FPGA_Sp76 ) + ( H20 /FPGA_Sp77 ) + ( H21 /DDR_Ban78 ) + ( H22 /FPGA_Sp79 ) + ( J1 /DDR_Ban80 ) + ( J2 GND ) + ( J3 /DDR_Ban81 ) + ( J4 /FPGA_Sp82 ) + ( J5 +2.5V ) + ( J6 ? ) + ( J7 ? ) + ( J8 +1.2V ) + ( J9 GND ) + ( J10 +1.2V ) + ( J11 GND ) + ( J12 +1.2V ) + ( J13 GND ) + ( J14 +1.2V ) + ( J15 GND ) + ( J16 ? ) + ( J17 /DDR_Ban83 ) + ( J18 +2.5V ) + ( J19 /FPGA_Sp84 ) + ( J20 /DDR_Ban85 ) + ( J21 GND ) + ( J22 /FPGA_Sp86 ) + ( K1 /FPGA_Sp87 ) + ( K2 /DDR_Ban88 ) + ( K3 /FPGA_Sp89 ) + ( K4 /FPGA_Sp90 ) + ( K5 /FPGA_Sp91 ) + ( K6 /DDR_Banks/M0_A3 ) + ( K7 ? ) + ( K8 ? ) + ( K9 +1.2V ) + ( K10 GND ) + ( K11 +1.2V ) + ( K12 GND ) + ( K13 +1.2V ) + ( K14 GND ) + ( K15 +2.5V ) + ( K16 ? ) + ( K17 /DDR_Ban92 ) + ( K18 ? ) + ( K19 /FPGA_Sp93 ) + ( K20 /FPGA_Sp94 ) + ( K21 /FPGA_Sp95 ) + ( K22 /FPGA_Sp96 ) + ( L1 ? ) + ( L2 +2.5V ) + ( L3 /DDR_Ban97 ) + ( L4 /DDR_Ban98 ) + ( L5 GND ) + ( L6 ? ) + ( L7 +2.5V ) + ( L8 +2.5V ) + ( L9 GND ) + ( L10 +1.2V ) + ( L11 GND ) + ( L12 +1.2V ) + ( L13 GND ) + ( L14 +1.2V ) + ( L15 ? ) + ( L16 +2.5V ) + ( L17 ? ) + ( L18 GND ) + ( L19 /DDR_Ban99 ) + ( L20 /FPGA_Sp100 ) + ( L21 +2.5V ) + ( L22 ? ) + ( M1 /FPGA_Sp101 ) + ( M2 /DDR_Ban102 ) + ( M3 /DDR_Ban103 ) + ( M4 ? ) + ( M5 ? ) + ( M6 ? ) + ( M7 ? ) + ( M8 ? ) + ( M9 +1.2V ) + ( M10 GND ) + ( M11 +1.2V ) + ( M12 GND ) + ( M13 +1.2V ) + ( M14 GND ) + ( M15 +2.5V ) + ( M16 ? ) + ( M17 ? ) + ( M18 /USB/USBA_VM ) + ( M19 ? ) + ( M20 /FPGA_Sp104 ) + ( M21 /FPGA_Sp105 ) + ( M22 /DDR_Ban106 ) + ( N1 /FPGA_Sp107 ) + ( N2 GND ) + ( N3 /DDR_Ban108 ) + ( N4 ? ) + ( N5 +2.5V ) + ( N6 ? ) + ( N7 ? ) + ( N8 +2.5V ) + ( N9 GND ) + ( N10 +1.2V ) + ( N11 GND ) + ( N12 +1.2V ) + ( N13 GND ) + ( N14 +1.2V ) + ( N15 ? ) + ( N16 /FPGA_Sp109 ) + ( N17 GND ) + ( N18 +2.5V ) + ( N19 ? ) + ( N20 /FPGA_Sp110 ) + ( N21 GND ) + ( N22 /FPGA_Sp111 ) + ( P1 /DDR_Ban112 ) + ( P2 /DDR_Ban113 ) + ( P3 ? ) + ( P4 ? ) + ( P5 ? ) + ( P6 ? ) + ( P7 ? ) + ( P8 ? ) + ( P9 +1.2V ) + ( P10 GND ) + ( P11 +1.2V ) + ( P12 GND ) + ( P13 +1.2V ) + ( P14 GND ) + ( P15 ? ) + ( P16 ? ) + ( P17 /USB/USBA_VP ) + ( P18 /FPGA_Sp114 ) + ( P19 ? ) + ( P20 ? ) + ( P21 /FPGA_Sp115 ) + ( P22 /FPGA_Sp116 ) + ( R1 /FPGA_Sp117 ) + ( R2 +2.5V ) + ( R3 /FPGA_Sp118 ) + ( R4 ? ) + ( R5 GND ) + ( R6 +2.5V ) + ( R7 ? ) + ( R8 ? ) + ( R9 ? ) + ( R10 +2.5V ) + ( R11 ? ) + ( R12 +2.5V ) + ( R13 ? ) + ( R14 +1.2V ) + ( R15 ? ) + ( R16 ? ) + ( R17 ? ) + ( R18 GND ) + ( R19 /USB/USBA_SPD ) + ( R20 /DDR_Ban119 ) + ( R21 +2.5V ) + ( R22 /DDR_Ban120 ) + ( T1 ? ) + ( T2 /DDR_Ban121 ) + ( T3 ? ) + ( T4 ? ) + ( T5 /FPGA_Sp122 ) + ( T6 ? ) + ( T7 ? ) + ( T8 ? ) + ( T9 N-000147 ) + ( T10 ? ) + ( T11 ? ) + ( T12 ? ) + ( T13 N-000147 ) + ( T14 ? ) + ( T15 ? ) + ( T16 ? ) + ( T17 ? ) + ( T18 ? ) + ( T19 ? ) + ( T20 ? ) + ( T21 /FPGA_Sp123 ) + ( T22 ? ) + ( U1 /DDR_Ban124 ) + ( U2 GND ) + ( U3 /FPGA_Sp125 ) + ( U4 ? ) + ( U5 +2.5V ) + ( U6 ? ) + ( U7 GND ) + ( U8 ? ) + ( U9 ? ) + ( U10 ? ) + ( U11 +2.5V ) + ( U12 ? ) + ( U13 /FPGA_Sp126 ) + ( U14 /FPGA_Sp127 ) + ( U15 ? ) + ( U16 ? ) + ( U17 ? ) + ( U18 +2.5V ) + ( U19 ? ) + ( U20 /FPGA_Sp128 ) + ( U21 GND ) + ( U22 /FPGA_Sp129 ) + ( V1 /FPGA_Sp130 ) + ( V2 /FPGA_Sp131 ) + ( V3 ? ) + ( V4 GND ) + ( V5 ? ) + ( V6 +2.5V ) + ( V7 ? ) + ( V8 N-000147 ) + ( V9 ? ) + ( V10 GND ) + ( V11 ? ) + ( V12 N-000147 ) + ( V13 ? ) + ( V14 GND ) + ( V15 ? ) + ( V16 N-000147 ) + ( V17 ? ) + ( V18 ? ) + ( V19 ? ) + ( V20 ? ) + ( V21 /FPGA_Sp132 ) + ( V22 /FPGA_Sp133 ) + ( W1 ? ) + ( W2 +2.5V ) + ( W3 ? ) + ( W4 ? ) + ( W5 N-000147 ) + ( W6 ? ) + ( W7 GND ) + ( W8 ? ) + ( W9 ? ) + ( W10 ? ) + ( W11 ? ) + ( W12 ? ) + ( W13 ? ) + ( W14 ? ) + ( W15 ? ) + ( W16 GND ) + ( W17 ? ) + ( W18 ? ) + ( W19 GND ) + ( W20 ? ) + ( W21 +2.5V ) + ( W22 ? ) + ( Y1 ? ) + ( Y3 ? ) + ( Y4 ? ) + ( Y5 ? ) + ( Y6 ? ) + ( Y7 ? ) + ( Y8 ? ) + ( Y9 ? ) + ( Y10 ? ) + ( Y11 ? ) + ( Y12 ? ) + ( Y13 ? ) + ( Y14 ? ) + ( Y15 ? ) + ( Y16 ? ) + ( Y17 ? ) + ( Y18 ? ) + ( Y19 ? ) + ( Y22 ? ) ) - ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} - ( 1 /Ethernet_Phy/ETH_PLL1.8V ) - ( 2 N-000329 ) + ( /4C421DD3/4C609B99 TSOP-66 U2 MT46V32M16TG + ( 1 +2.5V ) + ( 2 /DDR_Ban108 ) + ( 3 +2.5V ) + ( 4 /FPGA_Sp107 ) + ( 5 /DDR_Ban102 ) + ( 6 GND ) + ( 7 /FPGA_Sp101 ) + ( 8 /DDR_Ban81 ) + ( 9 +2.5V ) + ( 10 /DDR_Ban80 ) + ( 11 /DDR_Ban88 ) + ( 12 GND ) + ( 13 /FPGA_Sp87 ) + ( 14 ? ) + ( 15 +2.5V ) + ( 16 /DDR_Ban97 ) + ( 17 ? ) + ( 18 +2.5V ) + ( 19 ? ) + ( 20 /DDR_Ban98 ) + ( 21 /DDR_Ban61 ) + ( 22 /FPGA_Sp90 ) + ( 23 /FPGA_Sp91 ) + ( 24 GND ) + ( 25 ? ) + ( 26 /FPGA_Sp67 ) + ( 27 /DDR_Ban66 ) + ( 28 /DDR_Ban68 ) + ( 29 /DDR_Banks/M0_A0 ) + ( 30 /FPGA_Sp71 ) + ( 31 /FPGA_Sp74 ) + ( 32 /DDR_Banks/M0_A3 ) + ( 33 +2.5V ) + ( 34 GND ) + ( 35 /FPGA_Sp62 ) + ( 36 /FPGA_Sp89 ) + ( 37 /FPGA_Sp82 ) + ( 38 /FPGA_Sp75 ) + ( 39 /DDR_Banks/M0_A8 ) + ( 40 /FPGA_Sp58 ) + ( 41 /DDR_Ban33 ) + ( 42 /FPGA_Sp46 ) + ( 43 ? ) + ( 44 /FPGA_Sp72 ) + ( 45 /FPGA_Sp47 ) + ( 46 /FPGA_Sp73 ) + ( 47 /DDR_Ban103 ) + ( 48 GND ) + ( 49 N-000052 ) + ( 50 ? ) + ( 51 /DDR_Ban121 ) + ( 52 GND ) + ( 53 ? ) + ( 54 /DDR_Ban113 ) + ( 55 +2.5V ) + ( 56 /DDR_Ban112 ) + ( 57 /FPGA_Sp118 ) + ( 58 GND ) + ( 59 /FPGA_Sp117 ) + ( 60 /FPGA_Sp125 ) + ( 61 +2.5V ) + ( 62 /DDR_Ban124 ) + ( 63 /FPGA_Sp131 ) + ( 64 GND ) + ( 65 /FPGA_Sp130 ) + ( 66 GND ) ) - ( /4C4320F3/4C5D810A $noname L3 INDUCTOR {Lib=INDUCTOR} - ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 /Ethernet_Phy/ETH_PLL1.8V ) + ( /4C421DD3/4C609C8E TSOP-66 U3 MT46V32M16TG + ( 1 +2.5V ) + ( 2 /FPGA_Sp110 ) + ( 3 +2.5V ) + ( 4 /FPGA_Sp111 ) + ( 5 /FPGA_Sp105 ) + ( 6 GND ) + ( 7 /DDR_Ban106 ) + ( 8 /DDR_Ban85 ) + ( 9 +2.5V ) + ( 10 /FPGA_Sp86 ) + ( 11 /FPGA_Sp95 ) + ( 12 GND ) + ( 13 /FPGA_Sp96 ) + ( 14 ? ) + ( 15 +2.5V ) + ( 16 /FPGA_Sp100 ) + ( 17 ? ) + ( 18 +2.5V ) + ( 19 ? ) + ( 20 /DDR_Ban99 ) + ( 21 /FPGA_Sp76 ) + ( 22 /FPGA_Sp79 ) + ( 23 /DDR_Ban78 ) + ( 24 GND ) + ( 25 ? ) + ( 26 /DDR_Ban83 ) + ( 27 /DDR_Ban92 ) + ( 28 /FPGA_Sp69 ) + ( 29 /DDR_Banks/M1_A0 ) + ( 30 /FPGA_Sp65 ) + ( 31 /FPGA_Sp60 ) + ( 32 /FPGA_Sp70 ) + ( 33 +2.5V ) + ( 34 GND ) + ( 35 /FPGA_Sp64 ) + ( 36 /FPGA_Sp94 ) + ( 37 /FPGA_Sp93 ) + ( 38 /FPGA_Sp59 ) + ( 39 /FPGA_Sp44 ) + ( 40 /FPGA_Sp45 ) + ( 41 /FPGA_Sp63 ) + ( 42 /DDR_Ban57 ) + ( 43 ? ) + ( 44 /FPGA_Sp84 ) + ( 45 /FPGA_Sp56 ) + ( 46 /FPGA_Sp77 ) + ( 47 /FPGA_Sp104 ) + ( 48 GND ) + ( 49 N-000051 ) + ( 50 ? ) + ( 51 /FPGA_Sp123 ) + ( 52 GND ) + ( 53 ? ) + ( 54 /FPGA_Sp115 ) + ( 55 +2.5V ) + ( 56 /FPGA_Sp116 ) + ( 57 /DDR_Ban119 ) + ( 58 GND ) + ( 59 /DDR_Ban120 ) + ( 60 /FPGA_Sp128 ) + ( 61 +2.5V ) + ( 62 /FPGA_Sp129 ) + ( 63 /FPGA_Sp132 ) + ( 64 GND ) + ( 65 /FPGA_Sp133 ) + ( 66 GND ) ) - ( /4C4320F3/4C5D8104 $noname C6 C {Lib=C} - ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 N-000329 ) + ( /4C4320F3/4C432132 LQFP48 U4 K8001 + ( 1 /Etherne11 ) + ( 2 /FPGA_Sp34 ) + ( 3 /FPGA_Sp35 ) + ( 4 /FPGA_Sp28 ) + ( 5 /Etherne15 ) + ( 6 /FPGA_Sp36 ) + ( 7 3.3V ) + ( 8 GND ) + ( 9 /Etherne16 ) + ( 10 /Etherne52 ) + ( 11 /Etherne29 ) + ( 12 GND ) + ( 13 /Etherne1 ) + ( 14 /Etherne17 ) + ( 15 /Etherne50 ) + ( 16 /FPGA_Sp51 ) + ( 17 /Etherne37 ) + ( 18 /FPGA_Sp38 ) + ( 19 /FPGA_Sp18 ) + ( 20 /Etherne49 ) + ( 21 /Etherne19 ) + ( 22 /FPGA_Sp30 ) + ( 23 GND ) + ( 24 3.3V ) + ( 25 /Etherne14 ) + ( 26 /Etherne12 ) + ( 27 /Etherne13 ) + ( 28 ? ) + ( 29 ? ) + ( 30 ? ) + ( 31 /Etherne2 ) + ( 32 N-000327 ) + ( 33 N-000318 ) + ( 34 ? ) + ( 35 GND ) + ( 36 GND ) + ( 37 N-000326 ) + ( 38 /Etherne3 ) + ( 39 GND ) + ( 40 N-000328 ) + ( 41 N-000317 ) + ( 42 ? ) + ( 43 ? ) + ( 44 GND ) + ( 45 ? ) + ( 46 /Etherne39 ) + ( 47 /Etherne4 ) + ( 48 /FPGA_Sp48 ) ) - ( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR} - ( 1 N-000321 ) - ( 2 /Ethernet_Phy/ETH_A1.8V ) + ( /4C4227FE/4B76F108 NAND-48TSOP U5 NAND + ( 1 ? ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 6 /FPGA_Sp24 ) + ( 7 /FPGA_Sp24 ) + ( 8 /FPGA_Sp32 ) + ( 9 /Non_vol43 ) + ( 10 ? ) + ( 11 ? ) + ( 12 3.3V ) + ( 13 GND ) + ( 14 ? ) + ( 15 ? ) + ( 16 /Non_vol55 ) + ( 17 /FPGA_Sp23 ) + ( 18 /Non_vol42 ) + ( 19 3.3V ) + ( 20 ? ) + ( 21 ? ) + ( 22 ? ) + ( 23 ? ) + ( 24 ? ) + ( 25 ? ) + ( 26 ? ) + ( 27 ? ) + ( 28 ? ) + ( 29 /Non_vol54 ) + ( 30 /Non_vol22 ) + ( 31 /FPGA_Sp41 ) + ( 32 /Non_vol21 ) + ( 33 ? ) + ( 34 ? ) + ( 35 ? ) + ( 36 GND ) + ( 37 +3.3V ) + ( 38 ? ) + ( 39 ? ) + ( 40 ? ) + ( 41 /Non_vol31 ) + ( 42 /Non_vol40 ) + ( 43 /Non_vol53 ) + ( 44 /Non_vol20 ) + ( 45 ? ) + ( 46 ? ) + ( 47 ? ) + ( 48 ? ) ) - ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} - ( 1 N-000321 ) - ( 2 N-000329 ) + ( /4C5F1EDC/4C5F2025 TSSOP-14 U6 MIC2550AYTS + ( 1 +2.5V ) + ( 2 /USB/USBA_SPD ) + ( 3 /FPGA_Sp109 ) + ( 4 /USB/USBA_VP ) + ( 5 /USB/USBA_VM ) + ( 7 GND ) + ( 8 GND ) + ( 9 /FPGA_Sp114 ) + ( 10 N-000337 ) + ( 11 N-000356 ) + ( 12 3.3V ) + ( 14 3.3V ) ) - ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} - ( 1 /Ethernet_Phy/ETH_1.8V ) - ( 2 GND ) + ( /4C5F1EDC/4C6552BF TSSOP-14 U7 MIC2550AYTS + ( 1 +2.5V ) + ( 2 ? ) + ( 3 ? ) + ( 4 ? ) + ( 5 ? ) + ( 7 GND ) + ( 8 GND ) + ( 9 ? ) + ( 10 N-000350 ) + ( 11 N-000345 ) + ( 12 3.3V ) + ( 14 3.3V ) ) - ( /4C4320F3/4C5D7FB7 $noname L2 FB {Lib=INDUCTOR} - ( 1 3.3V ) - ( 2 /Ethernet_Phy/ETH_A3.3V ) + ( /4C4227FE/4C65A75D SO8E U8 X25X64MB + ( 1 /FPGA_Sp122 ) + ( 2 /FPGA_Sp25 ) + ( 3 /FPGA_Sp127 ) + ( 4 GND ) + ( 5 /FPGA_Sp27 ) + ( 6 /FPGA_Sp26 ) + ( 7 /FPGA_Sp126 ) + ( 8 VCCO2 ) ) - ( /4C4320F3/4C5D7FA7 $noname C8 100nF {Lib=C} - ( 1 /Ethernet_Phy/ETH_A3.3V ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2CA7 0603 V1 V0402MHS03 + ( 1 N-000356 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7FA5 $noname C7 1uF {Lib=C} - ( 1 /Ethernet_Phy/ETH_A3.3V ) - ( 2 GND ) + ( /4C5F1EDC/4C5F2CA3 0603 V2 V0402MHS03 + ( 1 N-000337 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7FA3 $noname C5 100nF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) + ( /4C5F1EDC/4C6552B8 0603 V3 V0402MHS03 + ( 1 N-000345 ) + ( 2 GND ) ) - ( /4C4320F3/4C5D7FA1 $noname C3 100nF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7F9F $noname C1 1uF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7F39 $noname R1 4.7K {Lib=R} - ( 1 /Ethernet_Phy/ETH_MDIO ) - ( 2 3.3V ) - ) - ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000326 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7E41 $noname C10 100nF {Lib=C} - ( 1 3.3V ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000314 ) - ( 2 GND ) - ) - ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000314 ) - ( 2 GND ) - ) - ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} - ( 1 /Ethernet_Phy/ETH_MDIO ) - ( 2 /FPGA_Spartan6/ETH_MDC ) - ( 3 /FPGA_Spartan6/ETH_RXD3 ) - ( 4 /FPGA_Spartan6/ETH_RXD2 ) - ( 5 /Ethernet_Phy/ETH_RXD1 ) - ( 6 /FPGA_Spartan6/ETH_RXD0 ) - ( 7 3.3V ) - ( 8 GND ) - ( 9 /Ethernet_Phy/ETH_RXDV ) - ( 10 /Ethernet_Phy/ETH_RXC ) - ( 11 /Ethernet_Phy/ETH_RXER ) - ( 12 GND ) - ( 13 /Ethernet_Phy/ETH_1.8V ) - ( 14 /Ethernet_Phy/ETH_TXER ) - ( 15 /Ethernet_Phy/ETH_TXC ) - ( 16 /FPGA_Spartan6/ETH_TXEN ) - ( 17 /Ethernet_Phy/ETH_TXD0 ) - ( 18 /FPGA_Spartan6/ETH_TXD1 ) - ( 19 /FPGA_Spartan6/ETH_TXD2 ) - ( 20 /Ethernet_Phy/ETH_TXD3 ) - ( 21 /Ethernet_Phy/ETH_COL ) - ( 22 /FPGA_Spartan6/ETH_CRS ) - ( 23 GND ) - ( 24 3.3V ) - ( 25 /Ethernet_Phy/ETH_INT ) - ( 26 /Ethernet_Phy/ETH_LED0 ) - ( 27 /Ethernet_Phy/ETH_LED1 ) - ( 28 ? ) - ( 29 ? ) - ( 30 ? ) - ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000327 ) - ( 33 N-000318 ) - ( 34 ? ) - ( 35 GND ) - ( 36 GND ) - ( 37 N-000326 ) - ( 38 /Ethernet_Phy/ETH_A3.3V ) - ( 39 GND ) - ( 40 N-000328 ) - ( 41 N-000317 ) - ( 42 ? ) - ( 43 ? ) - ( 44 GND ) - ( 45 ? ) - ( 46 /Ethernet_Phy/ETH_CLK ) - ( 47 /Ethernet_Phy/ETH_PLL1.8V ) - ( 48 /FPGA_Spartan6/ETH_RESET_N ) - ) - ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000317 ) - ) - ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000328 ) - ) - ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000327 ) - ) - ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} - ( 1 3.3V ) - ( 2 N-000318 ) - ) - ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000331 ) - ( 2 /Ethernet_Phy/ETH_LED1 ) - ) - ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000315 ) - ( 2 /Ethernet_Phy/ETH_LED0 ) - ) - ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000317 ) - ( 2 N-000328 ) - ( 3 3.3V ) - ( 4 GND ) - ( 5 GND ) - ( 6 3.3V ) - ( 7 N-000318 ) - ( 8 N-000327 ) - ( 9 3.3V ) - ( 10 N-000315 ) - ( 11 3.3V ) - ( 12 N-000331 ) - ( 13 N-000314 ) - ( 14 N-000314 ) - ) - ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C65D28E 0402 C71 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61D1D4 1206 C34 10uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61D151 1206 C33 10uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA5 0402 C28 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA4 0402 C29 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA3 0402 C31 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA2 0402 C30 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA1 0402 C32 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CFA0 0603 C27 1uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF2F 0603 C21 1uF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF27 0402 C26 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF17 0402 C24 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CF16 0402 C25 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CEF7 0402 C23 10nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CEB9 0402 C22 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 GND ) - ) - ( /4C421DD3/4C61CE31 0402 R13 1K_1% {Lib=R} - ( 1 +2.5V ) - ( 2 N-000051 ) - ) - ( /4C421DD3/4C61CE30 0402 R14 1K_1% {Lib=R} - ( 1 N-000051 ) - ( 2 N-000050 ) - ) - ( /4C421DD3/4C61CDB5 0402 R12 1K_1% {Lib=R} - ( 1 N-000052 ) - ( 2 N-000054 ) - ) - ( /4C421DD3/4C61CD4A 0402 R11 1K_1% {Lib=R} - ( 1 +2.5V ) - ( 2 N-000052 ) - ) - ( /4C421DD3/4C61CCE3 0402 C19 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 N-000051 ) - ) - ( /4C421DD3/4C61CCE2 0402 C20 100nF {Lib=CAP} - ( 1 N-000051 ) - ( 2 N-000050 ) - ) - ( /4C421DD3/4C61CC96 0402 C18 100nF {Lib=CAP} - ( 1 N-000052 ) - ( 2 N-000054 ) - ) - ( /4C421DD3/4C61CC73 0402 C17 100nF {Lib=CAP} - ( 1 +2.5V ) - ( 2 N-000052 ) - ) - ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} - ( 1 +2.5V ) - ( 2 /FPGA_Spartan6/M1_DQ0 ) - ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M1_DQ1 ) - ( 5 /FPGA_Spartan6/M1_DQ2 ) - ( 6 GND ) - ( 7 /DDR_Banks/M1_DQ3 ) - ( 8 /DDR_Banks/M1_DQ4 ) - ( 9 +2.5V ) - ( 10 /FPGA_Spartan6/M1_DQ5 ) - ( 11 /FPGA_Spartan6/M1_DQ6 ) - ( 12 GND ) - ( 13 /FPGA_Spartan6/M1_DQ7 ) - ( 14 ? ) - ( 15 +2.5V ) - ( 16 /FPGA_Spartan6/M1_LDQS ) - ( 17 ? ) - ( 18 +2.5V ) - ( 19 ? ) - ( 20 /DDR_Banks/M1_LDM ) - ( 21 /FPGA_Spartan6/M1_WE# ) - ( 22 /FPGA_Spartan6/M1_CAS# ) - ( 23 /DDR_Banks/M1_RAS# ) - ( 24 GND ) - ( 25 ? ) - ( 26 /DDR_Banks/M1_BA0 ) - ( 27 /DDR_Banks/M1_BA1 ) - ( 28 /FPGA_Spartan6/M1_A10 ) - ( 29 /DDR_Banks/M1_A0 ) - ( 30 /FPGA_Spartan6/M1_A1 ) - ( 31 /FPGA_Spartan6/M1_A2 ) - ( 32 /FPGA_Spartan6/M1_A3 ) - ( 33 +2.5V ) - ( 34 GND ) - ( 35 /FPGA_Spartan6/M1_A4 ) - ( 36 /FPGA_Spartan6/M1_A5 ) - ( 37 /FPGA_Spartan6/M1_A6 ) - ( 38 /FPGA_Spartan6/M1_A7 ) - ( 39 /FPGA_Spartan6/M1_A8 ) - ( 40 /FPGA_Spartan6/M1_A9 ) - ( 41 /FPGA_Spartan6/M1_A11 ) - ( 42 /DDR_Banks/M1_A12 ) - ( 43 ? ) - ( 44 /FPGA_Spartan6/M1_CLK# ) - ( 45 /FPGA_Spartan6/M1_CKE ) - ( 46 /FPGA_Spartan6/M1_CLK ) - ( 47 /FPGA_Spartan6/M1_UDM ) - ( 48 GND ) - ( 49 N-000051 ) - ( 50 ? ) - ( 51 /FPGA_Spartan6/M1_UDQS ) - ( 52 GND ) - ( 53 ? ) - ( 54 /FPGA_Spartan6/M1_DQ8 ) - ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M1_DQ9 ) - ( 57 /DDR_Banks/M1_DQ10 ) - ( 58 GND ) - ( 59 /DDR_Banks/M1_DQ11 ) - ( 60 /FPGA_Spartan6/M1_DQ12 ) - ( 61 +2.5V ) - ( 62 /FPGA_Spartan6/M1_DQ13 ) - ( 63 /FPGA_Spartan6/M1_DQ14 ) - ( 64 GND ) - ( 65 /FPGA_Spartan6/M1_DQ15 ) - ( 66 GND ) - ) - ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} - ( 1 +2.5V ) - ( 2 /DDR_Banks/M0_DQ0 ) - ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M0_DQ1 ) - ( 5 /DDR_Banks/M0_DQ2 ) - ( 6 GND ) - ( 7 /FPGA_Spartan6/M0_DQ3 ) - ( 8 /DDR_Banks/M0_DQ4 ) - ( 9 +2.5V ) - ( 10 /DDR_Banks/M0_DQ5 ) - ( 11 /DDR_Banks/M0_DQ6 ) - ( 12 GND ) - ( 13 /FPGA_Spartan6/M0_DQ7 ) - ( 14 ? ) - ( 15 +2.5V ) - ( 16 /DDR_Banks/M0_LDQS ) - ( 17 ? ) - ( 18 +2.5V ) - ( 19 ? ) - ( 20 /DDR_Banks/M0_LDM ) - ( 21 /DDR_Banks/M0_WE# ) - ( 22 /FPGA_Spartan6/M0_CAS# ) - ( 23 /FPGA_Spartan6/M0_RAS# ) - ( 24 GND ) - ( 25 ? ) - ( 26 /FPGA_Spartan6/M0_BA0 ) - ( 27 /DDR_Banks/M0_BA1 ) - ( 28 /DDR_Banks/M0_A10 ) - ( 29 /DDR_Banks/M0_A0 ) - ( 30 /FPGA_Spartan6/M0_A1 ) - ( 31 /FPGA_Spartan6/M0_A2 ) - ( 32 /DDR_Banks/M0_A3 ) - ( 33 +2.5V ) - ( 34 GND ) - ( 35 /FPGA_Spartan6/M0_A4 ) - ( 36 /FPGA_Spartan6/M0_A5 ) - ( 37 /FPGA_Spartan6/M0_A6 ) - ( 38 /FPGA_Spartan6/M0_A7 ) - ( 39 /DDR_Banks/M0_A8 ) - ( 40 /FPGA_Spartan6/M0_A9 ) - ( 41 /DDR_Banks/M0_A11 ) - ( 42 /FPGA_Spartan6/M0_A12 ) - ( 43 ? ) - ( 44 /FPGA_Spartan6/M0_CLK# ) - ( 45 /FPGA_Spartan6/M0_CKE ) - ( 46 /FPGA_Spartan6/M0_CLK ) - ( 47 /DDR_Banks/M0_UDM ) - ( 48 GND ) - ( 49 N-000052 ) - ( 50 ? ) - ( 51 /DDR_Banks/M0_UDQS ) - ( 52 GND ) - ( 53 ? ) - ( 54 /DDR_Banks/M0_DQ8 ) - ( 55 +2.5V ) - ( 56 /DDR_Banks/M0_DQ9 ) - ( 57 /FPGA_Spartan6/M0_DQ10 ) - ( 58 GND ) - ( 59 /FPGA_Spartan6/M0_DQ11 ) - ( 60 /FPGA_Spartan6/M0_DQ12 ) - ( 61 +2.5V ) - ( 62 /DDR_Banks/M0_DQ13 ) - ( 63 /FPGA_Spartan6/M0_DQ14 ) - ( 64 GND ) - ( 65 /FPGA_Spartan6/M0_DQ15 ) - ( 66 GND ) + ( /4C5F1EDC/4C6552B9 0603 V4 V0402MHS03 + ( 1 N-000350 ) + ( 2 GND ) ) ) * { Allowed footprints by component: -$component C74 +$component C1 SM* C? C1-1 $endlist -$component C73 +$component C2 SM* C? C1-1 $endlist -$component C72 +$component C3 + SM* + C? + C1-1 +$endlist +$component C4 + SM* + C? + C1-1 +$endlist +$component C5 + SM* + C? + C1-1 +$endlist +$component C6 + SM* + C? + C1-1 +$endlist +$component C7 + SM* + C? + C1-1 +$endlist +$component C8 + SM* + C? + C1-1 +$endlist +$component C9 + SM* + C? + C1-1 +$endlist +$component C10 + SM* + C? + C1-1 +$endlist +$component C11 + SM* + C? + C1-1 +$endlist +$component C12 + SM* + C? + C1-1 +$endlist +$component C13 + SM* + C? + C1-1 +$endlist +$component C14 + SM* + C? + C1-1 +$endlist +$component C15 + SM* + C? + C1-1 +$endlist +$component C16 + SM* + C? + C1-1 +$endlist +$component C17 + SM* + C? + C1-1 +$endlist +$component C18 + SM* + C? + C1-1 +$endlist +$component C19 + SM* + C? + C1-1 +$endlist +$component C20 + SM* + C? + C1-1 +$endlist +$component C21 + SM* + C? + C1-1 +$endlist +$component C22 + SM* + C? + C1-1 +$endlist +$component C23 + SM* + C? + C1-1 +$endlist +$component C24 + SM* + C? + C1-1 +$endlist +$component C25 + SM* + C? + C1-1 +$endlist +$component C26 + SM* + C? + C1-1 +$endlist +$component C27 + SM* + C? + C1-1 +$endlist +$component C28 + SM* + C? + C1-1 +$endlist +$component C29 + SM* + C? + C1-1 +$endlist +$component C30 + SM* + C? + C1-1 +$endlist +$component C31 + SM* + C? + C1-1 +$endlist +$component C32 + SM* + C? + C1-1 +$endlist +$component C33 + SM* + C? + C1-1 +$endlist +$component C34 SM* C? C1-1 @@ -1240,164 +1395,7 @@ $component C38 C? C1-1 $endlist -$component R15 - R? - SM0603 - SM0805 - R?-* -$endlist -$component R10 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C16 - SM* - C? - C1-1 -$endlist -$component C15 - SM* - C? - C1-1 -$endlist -$component C14 - SM* - C? - C1-1 -$endlist -$component C13 - SM* - C? - C1-1 -$endlist -$component C66 - SM* - C? - C1-1 -$endlist -$component C63 - SM* - C? - C1-1 -$endlist -$component C60 - SM* - C? - C1-1 -$endlist -$component C57 - SM* - C? - C1-1 -$endlist -$component C54 - SM* - C? - C1-1 -$endlist -$component C69 - SM* - C? - C1-1 -$endlist -$component C67 - SM* - C? - C1-1 -$endlist -$component C64 - SM* - C? - C1-1 -$endlist -$component C61 - SM* - C? - C1-1 -$endlist -$component C58 - SM* - C? - C1-1 -$endlist -$component C55 - SM* - C? - C1-1 -$endlist -$component C68 - SM* - C? - C1-1 -$endlist -$component C65 - SM* - C? - C1-1 -$endlist -$component C62 - SM* - C? - C1-1 -$endlist -$component C59 - SM* - C? - C1-1 -$endlist -$component C56 - SM* - C? - C1-1 -$endlist -$component C50 - SM* - C? - C1-1 -$endlist -$component C47 - SM* - C? - C1-1 -$endlist -$component C44 - SM* - C? - C1-1 -$endlist -$component C41 - SM* - C? - C1-1 -$endlist -$component C53 - SM* - C? - C1-1 -$endlist -$component C51 - SM* - C? - C1-1 -$endlist -$component C49 - SM* - C? - C1-1 -$endlist -$component C46 - SM* - C? - C1-1 -$endlist -$component C52 - SM* - C? - C1-1 -$endlist -$component C43 +$component C39 SM* C? C1-1 @@ -1407,12 +1405,7 @@ $component C40 C? C1-1 $endlist -$component C48 - SM* - C? - C1-1 -$endlist -$component C45 +$component C41 SM* C? C1-1 @@ -1422,52 +1415,162 @@ $component C42 C? C1-1 $endlist -$component C39 +$component C43 SM* C? C1-1 $endlist -$component C9 +$component C44 SM* C? C1-1 $endlist -$component C6 +$component C45 SM* C? C1-1 $endlist -$component C4 +$component C46 SM* C? C1-1 $endlist -$component C2 +$component C47 SM* C? C1-1 $endlist -$component C8 +$component C48 SM* C? C1-1 $endlist -$component C7 +$component C49 SM* C? C1-1 $endlist -$component C5 +$component C50 SM* C? C1-1 $endlist -$component C3 +$component C51 SM* C? C1-1 $endlist -$component C1 +$component C52 + SM* + C? + C1-1 +$endlist +$component C53 + SM* + C? + C1-1 +$endlist +$component C54 + SM* + C? + C1-1 +$endlist +$component C55 + SM* + C? + C1-1 +$endlist +$component C56 + SM* + C? + C1-1 +$endlist +$component C57 + SM* + C? + C1-1 +$endlist +$component C58 + SM* + C? + C1-1 +$endlist +$component C59 + SM* + C? + C1-1 +$endlist +$component C60 + SM* + C? + C1-1 +$endlist +$component C61 + SM* + C? + C1-1 +$endlist +$component C62 + SM* + C? + C1-1 +$endlist +$component C63 + SM* + C? + C1-1 +$endlist +$component C64 + SM* + C? + C1-1 +$endlist +$component C65 + SM* + C? + C1-1 +$endlist +$component C66 + SM* + C? + C1-1 +$endlist +$component C67 + SM* + C? + C1-1 +$endlist +$component C68 + SM* + C? + C1-1 +$endlist +$component C69 + SM* + C? + C1-1 +$endlist +$component C70 + SM* + C? + C1-1 +$endlist +$component C71 + SM* + C? + C1-1 +$endlist +$component C72 + SM* + C? + C1-1 +$endlist +$component C73 + SM* + C? + C1-1 +$endlist +$component C74 SM* C? C1-1 @@ -1484,27 +1587,6 @@ $component R2 SM0805 R?-* $endlist -$component C11 - SM* - C? - C1-1 -$endlist -$component C10 - SM* - C? - C1-1 -$endlist -$component C12 - SM* - C? - C1-1 -$endlist -$component R9 - R? - SM0603 - SM0805 - R?-* -$endlist $component R3 R? SM0603 @@ -1517,19 +1599,13 @@ $component R4 SM0805 R?-* $endlist -$component R6 - R? - SM0603 - SM0805 - R?-* -$endlist $component R5 R? SM0603 SM0805 R?-* $endlist -$component R8 +$component R6 R? SM0603 SM0805 @@ -1541,85 +1617,35 @@ $component R7 SM0805 R?-* $endlist -$component C70 - SM* - C? - C1-1 +$component R8 + R? + SM0603 + SM0805 + R?-* $endlist -$component C71 - SM* - C? - C1-1 +$component R9 + R? + SM0603 + SM0805 + R?-* $endlist -$component C34 - SM* - C? - C1-1 +$component R10 + R? + SM0603 + SM0805 + R?-* $endlist -$component C33 - SM* - C? - C1-1 +$component R11 + R? + SM0603 + SM0805 + R?-* $endlist -$component C28 - SM* - C? - C1-1 -$endlist -$component C29 - SM* - C? - C1-1 -$endlist -$component C31 - SM* - C? - C1-1 -$endlist -$component C30 - SM* - C? - C1-1 -$endlist -$component C32 - SM* - C? - C1-1 -$endlist -$component C27 - SM* - C? - C1-1 -$endlist -$component C21 - SM* - C? - C1-1 -$endlist -$component C26 - SM* - C? - C1-1 -$endlist -$component C24 - SM* - C? - C1-1 -$endlist -$component C25 - SM* - C? - C1-1 -$endlist -$component C23 - SM* - C? - C1-1 -$endlist -$component C22 - SM* - C? - C1-1 +$component R12 + R? + SM0603 + SM0805 + R?-* $endlist $component R13 R? @@ -1633,928 +1659,11 @@ $component R14 SM0805 R?-* $endlist -$component R12 +$component R15 R? SM0603 SM0805 R?-* $endlist -$component R11 - R? - SM0603 - SM0805 - R?-* -$endlist -$component C19 - SM* - C? - C1-1 -$endlist -$component C20 - SM* - C? - C1-1 -$endlist -$component C18 - SM* - C? - C1-1 -$endlist -$component C17 - SM* - C? - C1-1 -$endlist $endfootprintlist } -{ Pin List by Nets -Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" - U8 1 - U1 T5 -Net 2 "/FPGA Spartan6/NF_RE_N" "NF_RE_N" - U1 B16 - U5 8 -Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" - U5 9 - U1 C16 -Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE" - U1 A15 - U5 17 -Net 5 "/Ethernet Phy/ETH_TXC" "ETH_TXC" - U1 D8 - U4 15 -Net 6 "/Ethernet Phy/ETH_RXC" "ETH_RXC" - U1 D10 - U4 10 -Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK" - U1 C10 - U4 46 -Net 8 "/USB/USBA_SPD" "USBA_SPD" - U1 R19 - U6 2 -Net 9 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" - U6 9 - U1 P18 -Net 10 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" - U6 3 - U1 N16 -Net 11 "/USB/USBA_VP" "USBA_VP" - U1 P17 - U6 4 -Net 12 "/USB/USBA_VM" "USBA_VM" - U1 M18 - U6 5 -Net 13 "/Ethernet Phy/ETH_COL" "ETH_COL" - U4 21 - U1 A10 -Net 14 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" - U4 22 - U1 B10 -Net 15 "/FPGA Spartan6/SD_CLK" "SD_CLK" - J1 5 - U1 E16 -Net 16 "/Ethernet Phy/ETH_INT" "ETH_INT" - U4 25 - U1 A4 -Net 17 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" - U1 C5 - U4 2 -Net 18 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" - U1 A5 - U4 1 - R1 1 -Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" - U4 48 - U1 D6 -Net 20 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" - U1 A7 - U4 9 -Net 21 "/Ethernet Phy/ETH_RXER" "ETH_RXER" - U1 B8 - U4 11 -Net 22 "/Ethernet Phy/ETH_TXER" "ETH_TXER" - U1 A8 - U4 14 -Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" - U1 D9 - U4 16 -Net 24 "/FPGA Spartan6/M1_UDM" "M1_UDM" - U3 47 - U1 M20 -Net 25 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" - U1 L20 - U3 16 -Net 26 "/DDR Banks/M1_LDM" "M1_LDM" - U1 L19 - U3 20 -Net 27 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" - U1 T21 - U3 51 -Net 28 "/DDR Banks/M0_UDQS" "M0_UDQS" - U2 51 - U1 T2 -Net 29 "/DDR Banks/M0_LDM" "M0_LDM" - U2 20 - U1 L4 -Net 30 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" - U1 H22 - U3 22 -Net 31 "/FPGA Spartan6/M1_CKE" "M1_CKE" - U3 45 - U1 D21 -Net 32 "/FPGA Spartan6/M1_CLK" "M1_CLK" - U1 H20 - U3 46 -Net 33 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" - U1 J19 - U3 44 -Net 34 "GND" "GND" - U2 34 - U2 24 - U3 64 - U2 64 - U1 A22 - U1 P12 - C47 2 - C44 2 - C41 2 - U3 6 - C53 2 - C51 2 - C49 2 - C46 2 - C2 2 - C55 2 - U3 52 - C58 2 - C61 2 - U3 12 - C64 2 - C40 2 - U3 66 - C43 2 - C52 2 - C50 2 - C56 2 - C59 2 - C62 2 - C65 2 - U3 34 - U3 24 - C68 2 - U1 AA17 - U1 K14 - U1 M14 - U1 P14 - U1 V14 - U1 E15 - C72 2 - C73 2 - C74 2 - U8 4 - U2 12 - J1 6 - U1 J13 - J1 COM - J1 CASE - J1 CASE - J1 CASE - U1 L13 - U1 N13 - C39 2 - C42 2 - C45 2 - U2 58 - U2 48 - C67 2 - C69 2 - C54 2 - C57 2 - U1 B13 - U2 66 - C60 2 - C63 2 - U2 6 - C66 2 - U3 58 - U3 48 - U2 52 - U1 AB1 - U5 36 - U1 K12 - U1 M12 - U1 W16 - U1 B17 - U1 N17 - U1 D18 - U1 G18 - U1 L18 - U1 R18 - U1 W19 - U1 AA9 - U1 AB22 - U1 AA13 - C48 2 - U1 N11 - U5 13 - U1 E21 - U1 J21 - U1 N21 - U1 U21 - C27 2 - C32 2 - C30 2 - C31 2 - C29 2 - C28 2 - C22 2 - C23 2 - C25 2 - C24 2 - C26 2 - C21 2 - U1 K10 - U1 M10 - U4 35 - U4 36 - U4 8 - U4 12 - U4 23 - U1 W7 - C34 2 - C71 2 - C70 2 - U1 B9 - U1 P10 - U1 V10 - U1 E11 - U1 J11 - U1 L11 - U1 E7 - U1 H7 - U1 U7 - C33 2 - V3 2 - V4 2 - U1 N2 - C15 2 - C14 2 - C13 2 - U1 U2 - U6 7 - U6 8 - L7 2 - U1 A1 - U1 E2 - U1 J2 - R15 2 - C38 2 - C12 2 - R9 2 - C8 2 - C7 2 - C5 2 - C3 2 - C1 2 - U4 44 - U1 D4 - U1 V4 - U1 B5 - U1 G5 - U1 L5 - U1 R5 - R10 2 - C16 2 - V2 2 - V1 2 - U4 39 - J4 5 - J4 4 - R2 2 - C11 2 - C10 2 - U1 AA5 - U1 J15 - U7 7 - U7 8 - C35 2 - C36 2 - C37 2 - L5 2 - U1 N9 - U1 J9 - U1 L9 -Net 35 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" - U1 H3 - U2 44 -Net 36 "/FPGA Spartan6/M0_CLK" "M0_CLK" - U1 H4 - U2 46 -Net 37 "/FPGA Spartan6/M0_CKE" "M0_CKE" - U1 D2 - U2 45 -Net 38 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" - U1 K4 - U2 22 -Net 39 "/FPGA Spartan6/M1_WE#" "M1_WE#" - U3 21 - U1 H19 -Net 40 "/DDR Banks/M1_RAS#" "M1_RAS#" - U3 23 - U1 H21 -Net 41 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" - U2 23 - U1 K5 -Net 42 "/DDR Banks/M0_WE#" "M0_WE#" - U1 F2 - U2 21 -Net 43 "/DDR Banks/M0_LDQS" "M0_LDQS" - U2 16 - U1 L3 -Net 44 "/DDR Banks/M0_UDM" "M0_UDM" - U1 M3 - U2 47 -Net 45 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" - U1 AA21 - U8 6 -Net 46 "/FPGA Spartan6/NF_RNB" "NF_RNB" - U5 6 - U5 7 - U1 A16 -Net 47 "/Non volatile memories/NF_WE_N" "NF_WE_N" - U5 18 - U1 C15 -Net 48 "/Non volatile memories/NF_CLE" "NF_CLE" - U1 D15 - U5 16 -Net 49 "/FPGA Spartan6/SD_CMD" "SD_CMD" - U1 D17 - J1 3 -Net 50 "" "" - R14 2 - C20 2 -Net 51 "" "" - R14 1 - C19 2 - C20 1 - U3 49 - R13 2 -Net 52 "" "" - U2 49 - C17 2 - C18 1 - R12 1 - R11 2 -Net 53 "+2.5V" "+2.5V" - U1 J5 - U1 U18 - U1 D16 - U1 M15 - U1 K15 - U1 H15 - U1 C2 - U1 H9 - U1 W2 - U1 R2 - U1 L2 - U1 G2 - U1 R6 - U1 V6 - U1 N18 - U1 J18 - U1 E19 - U1 W21 - U1 R21 - U1 L21 - U1 G21 - U1 C21 - U1 L16 - U1 R10 - U1 F11 - U1 L8 - U1 N8 - C70 1 - C71 1 - C34 1 - C33 1 - U6 1 - U7 1 - C21 1 - C26 1 - C24 1 - C25 1 - C23 1 - C22 1 - R13 1 - C28 1 - C29 1 - C31 1 - C30 1 - C32 1 - C27 1 - U1 U5 - U1 F6 - U1 F4 - U1 L7 - U1 G12 - U1 U11 - U2 61 - C66 1 - U2 1 - U2 3 - C63 1 - U2 9 - C60 1 - C57 1 - C54 1 - U2 18 - U2 33 - U1 R12 - U1 N5 - U3 18 - U3 61 - C68 1 - U3 33 - C65 1 - C62 1 - C59 1 - C56 1 - U2 15 - U2 55 - U3 3 - C53 1 - U3 9 - C51 1 - C49 1 - C46 1 - R11 1 - C19 1 - C17 1 - U3 1 - U3 15 - C52 1 - U3 55 - C43 1 - C40 1 -Net 54 "" "" - R12 2 - C18 2 -Net 99 "3.3V" "3.3V" - C10 1 - C11 1 - J4 3 - J4 6 - J4 9 - J4 11 - R5 1 - R6 1 - C5 1 - C3 1 - C1 1 - R1 2 - U4 24 - U4 7 - U7 14 - U7 12 - U6 12 - U6 14 - R3 1 - R4 1 - L2 1 - U5 12 - U5 19 -Net 100 "VCCO2" "VCCO2" - U8 8 - C69 1 - C67 1 - C64 1 - C61 1 - C58 1 - C55 1 -Net 101 "+3.3V" "+3.3V" - C72 1 - C73 1 - U1 B4 - C74 1 - U1 G10 - U1 E9 - C50 1 - U1 B7 - U1 B15 - U1 G14 - C41 1 - C44 1 - C47 1 - U1 E13 - U1 B11 - U1 B19 - U1 E17 - U5 37 -Net 147 "" "" - U1 T13 - U1 AA3 - U1 T9 - U1 AA11 - U1 AA19 - U1 AA15 - U1 V8 - U1 V16 - U1 W5 - U1 V12 - U1 AA7 -Net 234 "+1.2V" "+1.2V" - U1 P9 - C48 1 - U1 J10 - C45 1 - U1 M11 - U1 P11 - U1 J14 - U1 L14 - U1 N14 - U1 R14 - C42 1 - U1 N12 - U1 L12 - C39 1 - U1 P13 - U1 J12 - U1 M13 - U1 K13 - U1 L10 - U1 N10 - U1 K11 - U1 J8 - U1 K9 - U1 M9 -Net 314 "" "" - J4 14 - J4 13 - R9 1 - C12 1 -Net 315 "" "" - J4 10 - R7 1 -Net 316 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - R7 2 - U4 26 -Net 317 "" "" - R3 2 - J4 1 - U4 41 -Net 318 "" "" - U4 33 - J4 7 - R5 2 -Net 319 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" - C2 1 - U4 13 -Net 320 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - C6 1 - L3 1 - U4 31 - L1 2 -Net 321 "" "" - C4 1 - L1 1 -Net 322 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - C8 1 - U4 38 - L2 2 - C7 1 -Net 323 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - L3 2 - C9 1 - U4 47 -Net 326 "" "" - U4 37 - R2 1 -Net 327 "" "" - U4 32 - R6 2 - J4 8 -Net 328 "" "" - J4 2 - R4 2 - U4 40 -Net 329 "" "" - C4 2 - C6 2 - C9 2 -Net 330 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - U4 27 - R8 2 -Net 331 "" "" - J4 12 - R8 1 -Net 337 "" "" - J5 2 - V2 1 - V2 1 - U6 10 -Net 338 "" "" - J5 S1 - J5 S2 - J5 S3 - J5 S4 - R10 1 - C16 1 -Net 339 "" "" - L6 1 - F2 1 -Net 341 "+5V" "+5V" - F1 2 - F2 2 -Net 345 "" "" - V3 1 - V3 1 - U7 11 -Net 349 "" "" - L5 1 - J5 4 -Net 350 "" "" - U7 10 - V4 1 - V4 1 -Net 351 "" "" - C35 1 - C36 1 - C37 1 -Net 352 "" "" - C38 1 - R15 1 -Net 353 "" "" - L4 2 - J5 1 -Net 354 "" "" - F1 1 - L4 1 -Net 355 "" "" - C13 1 - C14 1 - C15 1 -Net 356 "" "" - U6 11 - V1 1 - J5 3 - V1 1 -Net 357 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" - U8 7 - U1 U13 -Net 358 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" - U8 3 - U1 U14 -Net 359 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" - U1 AA20 - U8 2 -Net 360 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" - U8 5 - U1 AB20 -Net 361 "/Non volatile memories/NF_D7" "NF_D7" - U1 A11 - U5 44 -Net 362 "/Non volatile memories/NF_D6" "NF_D6" - U5 43 - U1 D11 -Net 363 "/Non volatile memories/NF_D5" "NF_D5" - U1 C12 - U5 42 -Net 364 "/Non volatile memories/NF_D4" "NF_D4" - U1 B12 - U5 41 -Net 365 "/Non volatile memories/NF_D3" "NF_D3" - U5 32 - U1 A12 -Net 366 "/FPGA Spartan6/NF_D2" "NF_D2" - U5 31 - U1 C13 -Net 367 "/Non volatile memories/NF_D1" "NF_D1" - U5 30 - U1 A13 -Net 368 "/Non volatile memories/NF_D0" "NF_D0" - U5 29 - U1 D14 -Net 369 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" - U4 20 - U1 D7 -Net 370 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" - U4 19 - U1 A9 -Net 371 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" - U1 C9 - U4 18 -Net 372 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" - U1 C8 - U4 17 -Net 373 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" - U1 C6 - U4 3 -Net 374 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" - U1 B6 - U4 4 -Net 375 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" - U1 A6 - U4 5 -Net 376 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" - U4 6 - U1 C7 -Net 377 "/DDR Banks/M0_BA1" "M0_BA1" - U1 G1 - U2 27 -Net 378 "/FPGA Spartan6/M0_BA0" "M0_BA0" - U1 G3 - U2 26 -Net 379 "/DDR Banks/M1_BA1" "M1_BA1" - U1 K17 - U3 27 -Net 380 "/DDR Banks/M1_BA0" "M1_BA0" - U3 26 - U1 J17 -Net 381 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" - U3 65 - U1 V22 -Net 382 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" - U3 63 - U1 V21 -Net 383 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" - U3 62 - U1 U22 -Net 384 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" - U3 60 - U1 U20 -Net 385 "/DDR Banks/M1_DQ11" "M1_DQ11" - U1 R22 - U3 59 -Net 386 "/DDR Banks/M1_DQ10" "M1_DQ10" - U1 R20 - U3 57 -Net 387 "/Non volatile memories/SD_DAT3" "SD_DAT3" - U1 C17 - J1 2 -Net 388 "/Non volatile memories/SD_DAT2" "SD_DAT2" - J1 1 - U1 A17 -Net 389 "/FPGA Spartan6/SD_DAT1" "SD_DAT1" - U1 B18 - J1 8 -Net 390 "/Non volatile memories/SD_DAT0" "SD_DAT0" - U1 A18 - J1 7 -Net 391 "/FPGA Spartan6/M1_A7" "M1_A7" - U1 E20 - U3 38 -Net 392 "/FPGA Spartan6/M1_A6" "M1_A6" - U3 37 - U1 K19 -Net 393 "/FPGA Spartan6/M1_A5" "M1_A5" - U1 K20 - U3 36 -Net 394 "/FPGA Spartan6/M1_A4" "M1_A4" - U3 35 - U1 F20 -Net 395 "/FPGA Spartan6/M1_A3" "M1_A3" - U3 32 - U1 G20 -Net 396 "/FPGA Spartan6/M1_A2" "M1_A2" - U1 E22 - U3 31 -Net 397 "/FPGA Spartan6/M1_A1" "M1_A1" - U3 30 - U1 F22 -Net 398 "/DDR Banks/M1_A0" "M1_A0" - U3 29 - U1 F21 -Net 399 "/FPGA Spartan6/M0_A12" "M0_A12" - U1 D1 - U2 42 -Net 400 "/DDR Banks/M0_A11" "M0_A11" - U2 41 - U1 C1 -Net 401 "/DDR Banks/M0_A10" "M0_A10" - U1 G4 - U2 28 -Net 402 "/FPGA Spartan6/M0_A9" "M0_A9" - U1 E1 - U2 40 -Net 403 "/DDR Banks/M0_A8" "M0_A8" - U1 E3 - U2 39 -Net 404 "/FPGA Spartan6/M0_A7" "M0_A7" - U2 38 - U1 H6 -Net 405 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" - U1 P22 - U3 56 -Net 406 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" - U1 P21 - U3 54 -Net 407 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" - U3 13 - U1 K22 -Net 408 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" - U3 11 - U1 K21 -Net 409 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" - U3 10 - U1 J22 -Net 410 "/DDR Banks/M1_DQ4" "M1_DQ4" - U3 8 - U1 J20 -Net 411 "/DDR Banks/M1_DQ3" "M1_DQ3" - U3 7 - U1 M22 -Net 412 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" - U1 M21 - U3 5 -Net 413 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" - U3 4 - U1 N22 -Net 414 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" - U1 N20 - U3 2 -Net 415 "/DDR Banks/M1_A12" "M1_A12" - U1 D22 - U3 42 -Net 416 "/FPGA Spartan6/M1_A11" "M1_A11" - U3 41 - U1 F19 -Net 417 "/FPGA Spartan6/M1_A10" "M1_A10" - U1 G19 - U3 28 -Net 418 "/FPGA Spartan6/M1_A9" "M1_A9" - U3 40 - U1 C22 -Net 419 "/FPGA Spartan6/M1_A8" "M1_A8" - U1 C20 - U3 39 -Net 420 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" - U2 7 - U1 M1 -Net 421 "/DDR Banks/M0_DQ2" "M0_DQ2" - U1 M2 - U2 5 -Net 422 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" - U2 4 - U1 N1 -Net 423 "/DDR Banks/M0_DQ0" "M0_DQ0" - U2 2 - U1 N3 -Net 424 "/FPGA Spartan6/M0_A6" "M0_A6" - U2 37 - U1 J4 -Net 425 "/FPGA Spartan6/M0_A5" "M0_A5" - U1 K3 - U2 36 -Net 426 "/FPGA Spartan6/M0_A4" "M0_A4" - U1 F3 - U2 35 -Net 427 "/DDR Banks/M0_A3" "M0_A3" - U1 K6 - U2 32 -Net 428 "/FPGA Spartan6/M0_A2" "M0_A2" - U2 31 - U1 H5 -Net 429 "/FPGA Spartan6/M0_A1" "M0_A1" - U2 30 - U1 H1 -Net 430 "/DDR Banks/M0_A0" "M0_A0" - U1 H2 - U2 29 -Net 431 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" - U1 V1 - U2 65 -Net 432 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" - U1 V2 - U2 63 -Net 433 "/DDR Banks/M0_DQ13" "M0_DQ13" - U2 62 - U1 U1 -Net 434 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" - U1 U3 - U2 60 -Net 435 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" - U2 59 - U1 R1 -Net 436 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" - U1 R3 - U2 57 -Net 437 "/DDR Banks/M0_DQ9" "M0_DQ9" - U1 P1 - U2 56 -Net 438 "/DDR Banks/M0_DQ8" "M0_DQ8" - U2 54 - U1 P2 -Net 439 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" - U2 13 - U1 K1 -Net 440 "/DDR Banks/M0_DQ6" "M0_DQ6" - U2 11 - U1 K2 -Net 441 "/DDR Banks/M0_DQ5" "M0_DQ5" - U2 10 - U1 J1 -Net 442 "/DDR Banks/M0_DQ4" "M0_DQ4" - U2 8 - U1 J3 -} -#End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index f051cbe..0416fa9 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Fri 13 Aug 2010 07:16:08 PM COT +update=Sat 14 Aug 2010 07:09:03 AM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 26ead1c..b999a06 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT +EESchema Schematic File Version 2 date Sat 14 Aug 2010 07:07:48 AM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001