diff --git a/kicad/library/PSU.lib b/kicad/library/PSU.lib new file mode 100644 index 0000000..28aeeed --- /dev/null +++ b/kicad/library/PSU.lib @@ -0,0 +1,18 @@ +EESchema-LIBRARY Version 2.3 Date: Thu 19 Aug 2010 07:58:54 AM COT +# +# A7108 +# +DEF A7108 U 0 40 Y Y 1 F N +F0 "U" 100 400 60 H V C CNN +F1 "A7108" 100 100 60 H V C CNN +DRAW +S -200 450 400 -250 0 1 0 f +X EN 1 -500 -50 300 R 50 50 1 1 W +X GND 2 100 -550 300 U 50 50 1 1 W +X SW 3 700 300 300 L 50 50 1 1 W +X VIN 4 -500 300 300 R 50 50 1 1 W +X VFB 5 700 -50 300 L 50 50 1 1 W +ENDDRAW +ENDDEF +# +#End Library diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index d060d65..216b990 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 18 Aug 2010 10:06:32 PM COT +EESchema Schematic File Version 2 date Thu 19 Aug 2010 08:32:00 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -531,19 +531,19 @@ Entry Wire Line Entry Wire Line 10100 4400 10200 4500 $Comp -L GND #PWR048 +L GND #PWR059 U 1 1 4C699C4D P 9950 2100 -F 0 "#PWR048" H 9950 2100 30 0001 C CNN +F 0 "#PWR059" H 9950 2100 30 0001 C CNN F 1 "GND" H 9950 2030 30 0001 C CNN 1 9950 2100 1 0 0 -1 $EndComp $Comp -L GND #PWR049 +L GND #PWR060 U 1 1 4C699C48 P 4550 2150 -F 0 "#PWR049" H 4550 2150 30 0001 C CNN +F 0 "#PWR060" H 4550 2150 30 0001 C CNN F 1 "GND" H 4550 2080 30 0001 C CNN 1 4550 2150 1 0 0 -1 @@ -601,37 +601,37 @@ F 2 "1206" H 6900 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR050 +L GND #PWR061 U 1 1 4C61D1D3 P 6900 6200 -F 0 "#PWR050" H 6900 6200 30 0001 C CNN +F 0 "#PWR061" H 6900 6200 30 0001 C CNN F 1 "GND" H 6900 6130 30 0001 C CNN 1 6900 6200 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR051 +L +2.5V #PWR062 U 1 1 4C61D1D2 P 6900 5800 -F 0 "#PWR051" H 6900 5750 20 0001 C CNN +F 0 "#PWR062" H 6900 5750 20 0001 C CNN F 1 "+2.5V" H 6900 5900 30 0000 C CNN 1 6900 5800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR052 +L +2.5V #PWR063 U 1 1 4C61D192 P 1700 5800 -F 0 "#PWR052" H 1700 5750 20 0001 C CNN +F 0 "#PWR063" H 1700 5750 20 0001 C CNN F 1 "+2.5V" H 1700 5900 30 0000 C CNN 1 1700 5800 1 0 0 -1 $EndComp $Comp -L GND #PWR053 +L GND #PWR064 U 1 1 4C61D17F P 1700 6200 -F 0 "#PWR053" H 1700 6200 30 0001 C CNN +F 0 "#PWR064" H 1700 6200 30 0001 C CNN F 1 "GND" H 1700 6130 30 0001 C CNN 1 1700 6200 1 0 0 -1 @@ -647,19 +647,19 @@ F 2 "1206" H 1700 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR054 +L +2.5V #PWR065 U 1 1 4C61CFCF P 3050 1750 -F 0 "#PWR054" H 3050 1700 20 0001 C CNN +F 0 "#PWR065" H 3050 1700 20 0001 C CNN F 1 "+2.5V" H 3050 1850 30 0000 C CNN 1 3050 1750 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR055 +L +2.5V #PWR066 U 1 1 4C61CFC6 P 8400 1700 -F 0 "#PWR055" H 8400 1650 20 0001 C CNN +F 0 "#PWR066" H 8400 1650 20 0001 C CNN F 1 "+2.5V" H 8400 1800 30 0000 C CNN 1 8400 1700 1 0 0 -1 @@ -725,37 +725,37 @@ F 2 "0603" H 7450 6000 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR056 +L +2.5V #PWR067 U 1 1 4C61CF9F P 8300 5750 -F 0 "#PWR056" H 8300 5700 20 0001 C CNN +F 0 "#PWR067" H 8300 5700 20 0001 C CNN F 1 "+2.5V" H 8300 5850 30 0000 C CNN 1 8300 5750 1 0 0 -1 $EndComp $Comp -L GND #PWR057 +L GND #PWR068 U 1 1 4C61CF9E P 8300 6350 -F 0 "#PWR057" H 8300 6350 30 0001 C CNN +F 0 "#PWR068" H 8300 6350 30 0001 C CNN F 1 "GND" H 8300 6280 30 0001 C CNN 1 8300 6350 1 0 0 -1 $EndComp $Comp -L GND #PWR058 +L GND #PWR069 U 1 1 4C61CF90 P 3050 6350 -F 0 "#PWR058" H 3050 6350 30 0001 C CNN +F 0 "#PWR069" H 3050 6350 30 0001 C CNN F 1 "GND" H 3050 6280 30 0001 C CNN 1 3050 6350 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR059 +L +2.5V #PWR070 U 1 1 4C61CF89 P 3050 5750 -F 0 "#PWR059" H 3050 5700 20 0001 C CNN +F 0 "#PWR070" H 3050 5700 20 0001 C CNN F 1 "+2.5V" H 3050 5850 30 0000 C CNN 1 3050 5750 1 0 0 -1 @@ -841,19 +841,19 @@ F 2 "0402" H 9950 1750 60 0001 C CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR060 +L +2.5V #PWR071 U 1 1 4C61CE2F P 9950 800 -F 0 "#PWR060" H 9950 750 20 0001 C CNN +F 0 "#PWR071" H 9950 750 20 0001 C CNN F 1 "+2.5V" H 9950 900 30 0000 C CNN 1 9950 800 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR061 +L +2.5V #PWR072 U 1 1 4C61CDF1 P 4550 850 -F 0 "#PWR061" H 4550 800 20 0001 C CNN +F 0 "#PWR072" H 4550 800 20 0001 C CNN F 1 "+2.5V" H 4550 950 30 0000 C CNN 1 4550 850 1 0 0 -1 @@ -936,10 +936,10 @@ $EndComp Text HLabel 5000 5350 2 60 BiDi ~ 0 M0_DQ[0..15] $Comp -L GND #PWR062 +L GND #PWR073 U 1 1 4C58A712 P 3000 5200 -F 0 "#PWR062" H 3000 5200 30 0001 C CNN +F 0 "#PWR073" H 3000 5200 30 0001 C CNN F 1 "GND" H 3000 5130 30 0001 C CNN 1 3000 5200 1 0 0 -1 @@ -1215,10 +1215,10 @@ Entry Wire Line Entry Wire Line 10100 3600 10200 3700 $Comp -L GND #PWR063 +L GND #PWR074 U 1 1 4C437C3F P 8350 5150 -F 0 "#PWR063" H 8350 5150 30 0001 C CNN +F 0 "#PWR074" H 8350 5150 30 0001 C CNN F 1 "GND" H 8350 5080 30 0001 C CNN 1 8350 5150 1 0 0 -1 diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index 487d479..c79e936 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 18 Aug 2010 10:06:32 PM COT +EESchema Schematic File Version 2 date Thu 19 Aug 2010 08:32:00 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -2142,28 +2142,28 @@ VCC02 Text GLabel 5300 6250 3 30 BiDi ~ 0 VCCO2 $Comp -L +3.3V #PWR030 +L +3.3V #PWR041 U 1 1 4C65CF66 P 1650 14300 -F 0 "#PWR030" H 1650 14260 30 0001 C CNN +F 0 "#PWR041" H 1650 14260 30 0001 C CNN F 1 "+3.3V" H 1650 14410 30 0000 C CNN 1 1650 14300 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR031 +L +2.5V #PWR042 U 1 1 4C65C84B P 4600 14300 -F 0 "#PWR031" H 4600 14250 20 0001 C CNN +F 0 "#PWR042" H 4600 14250 20 0001 C CNN F 1 "+2.5V" H 4600 14400 30 0000 C CNN 1 4600 14300 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR032 +L +2.5V #PWR043 U 1 1 4C65C837 P 4600 12350 -F 0 "#PWR032" H 4600 12300 20 0001 C CNN +F 0 "#PWR043" H 4600 12300 20 0001 C CNN F 1 "+2.5V" H 4600 12450 30 0000 C CNN 1 4600 12350 1 0 0 -1 @@ -2210,10 +2210,10 @@ F 1 "470nF" H 6050 12550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR033 +L GND #PWR044 U 1 1 4C656D9B P 4600 12950 -F 0 "#PWR033" H 4600 12950 30 0001 C CNN +F 0 "#PWR044" H 4600 12950 30 0001 C CNN F 1 "GND" H 4600 12880 30 0001 C CNN 1 4600 12950 1 0 0 -1 @@ -2275,10 +2275,10 @@ F 1 "470nF" H 6050 13550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR034 +L GND #PWR045 U 1 1 4C656D47 P 4600 13950 -F 0 "#PWR034" H 4600 13950 30 0001 C CNN +F 0 "#PWR045" H 4600 13950 30 0001 C CNN F 1 "GND" H 4600 13880 30 0001 C CNN 1 4600 13950 1 0 0 -1 @@ -2331,10 +2331,10 @@ F 1 "470nF" H 6050 14500 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR035 +L GND #PWR046 U 1 1 4C656CFD P 4600 14900 -F 0 "#PWR035" H 4600 14900 30 0001 C CNN +F 0 "#PWR046" H 4600 14900 30 0001 C CNN F 1 "GND" H 4600 14830 30 0001 C CNN 1 4600 14900 1 0 0 -1 @@ -2378,10 +2378,10 @@ F 1 "100uF" H 4650 14500 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR036 +L GND #PWR047 U 1 1 4C656CBC P 1650 14900 -F 0 "#PWR036" H 1650 14900 30 0001 C CNN +F 0 "#PWR047" H 1650 14900 30 0001 C CNN F 1 "GND" H 1650 14830 30 0001 C CNN 1 1650 14900 1 0 0 -1 @@ -2427,10 +2427,10 @@ $EndComp Text Notes 1750 13400 0 30 ~ 0 VCC_AUX Decoupling Capacitors (7) $Comp -L GND #PWR037 +L GND #PWR048 U 1 1 4C656C68 P 1650 14000 -F 0 "#PWR037" H 1650 14000 30 0001 C CNN +F 0 "#PWR048" H 1650 14000 30 0001 C CNN F 1 "GND" H 1650 13930 30 0001 C CNN 1 1650 14000 1 0 0 -1 @@ -2499,19 +2499,19 @@ F 1 "100uF" H 1700 13600 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR038 +L +2.5V #PWR049 U 1 1 4C656BBA P 1650 13400 -F 0 "#PWR038" H 1650 13350 20 0001 C CNN +F 0 "#PWR049" H 1650 13350 20 0001 C CNN F 1 "+2.5V" H 1650 13500 30 0000 C CNN 1 1650 13400 1 0 0 -1 $EndComp $Comp -L GND #PWR039 +L GND #PWR050 U 1 1 4C656BA8 P 1650 12950 -F 0 "#PWR039" H 1650 12950 30 0001 C CNN +F 0 "#PWR050" H 1650 12950 30 0001 C CNN F 1 "GND" H 1650 12880 30 0001 C CNN 1 1650 12950 1 0 0 -1 @@ -2546,10 +2546,10 @@ F 1 "4.7uF" H 2050 12550 50 0000 L CNN 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR040 +L +1.2V #PWR051 U 1 1 4C656AA1 P 1650 12350 -F 0 "#PWR040" H 1650 12490 20 0001 C CNN +F 0 "#PWR051" H 1650 12490 20 0001 C CNN F 1 "+1.2V" H 1650 12460 30 0000 C CNN 1 1650 12350 1 0 0 -1 @@ -2614,46 +2614,46 @@ NF_RE_N Text HLabel 18000 7250 2 60 BiDi ~ 0 NF_RNB $Comp -L +3.3V #PWR041 +L +3.3V #PWR052 U 1 1 4C61E5B3 P 15900 6100 -F 0 "#PWR041" H 15900 6060 30 0001 C CNN +F 0 "#PWR052" H 15900 6060 30 0001 C CNN F 1 "+3.3V" H 15900 6210 30 0000 C CNN 1 15900 6100 1 0 0 -1 $EndComp $Comp -L +1.2V #PWR042 +L +1.2V #PWR053 U 1 1 4C61E58C P 16500 9850 -F 0 "#PWR042" H 16500 9990 20 0001 C CNN +F 0 "#PWR053" H 16500 9990 20 0001 C CNN F 1 "+1.2V" H 16500 9960 30 0000 C CNN 1 16500 9850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR043 +L +2.5V #PWR054 U 1 1 4C61E577 P 15000 9850 -F 0 "#PWR043" H 15000 9800 20 0001 C CNN +F 0 "#PWR054" H 15000 9800 20 0001 C CNN F 1 "+2.5V" H 15000 9950 30 0000 C CNN 1 15000 9850 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR044 +L +2.5V #PWR055 U 1 1 4C61E523 P 19700 650 -F 0 "#PWR044" H 19700 600 20 0001 C CNN +F 0 "#PWR055" H 19700 600 20 0001 C CNN F 1 "+2.5V" H 19700 750 30 0000 C CNN 1 19700 650 1 0 0 -1 $EndComp $Comp -L +2.5V #PWR045 +L +2.5V #PWR056 U 1 1 4C61E51F P 8100 650 -F 0 "#PWR045" H 8100 600 20 0001 C CNN +F 0 "#PWR056" H 8100 600 20 0001 C CNN F 1 "+2.5V" H 8100 750 30 0000 C CNN 1 8100 650 1 0 0 -1 @@ -2693,10 +2693,10 @@ M1_BA[0..1] Text HLabel 15750 3950 0 60 Output ~ 0 M1_CS# $Comp -L GND #PWR046 +L GND #PWR057 U 1 1 4C60C21D P 1600 5950 -F 0 "#PWR046" H 1600 5950 30 0001 C CNN +F 0 "#PWR057" H 1600 5950 30 0001 C CNN F 1 "GND" H 1600 5880 30 0001 C CNN 1 1600 5950 -1 0 0 -1 @@ -3108,10 +3108,10 @@ M0_CLK Text HLabel 11150 4650 2 60 Output ~ 0 M0_CLK# $Comp -L GND #PWR047 +L GND #PWR058 U 1 1 4C439B7E P 16400 12650 -F 0 "#PWR047" H 16400 12650 30 0001 C CNN +F 0 "#PWR058" H 16400 12650 30 0001 C CNN F 1 "GND" H 16400 12580 30 0001 C CNN 1 16400 12650 -1 0 0 -1 diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index c4963f3..066dfda 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 18 Aug 2010 10:06:32 PM COT +EESchema Schematic File Version 2 date Thu 19 Aug 2010 08:32:00 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -244,19 +244,19 @@ F 1 "100nF" H 4000 5400 50 0000 L CNN -1 0 0 1 $EndComp $Comp -L GND #PWR02 +L GND #PWR013 U 1 1 4C65D6AB P 9350 3150 -F 0 "#PWR02" H 9350 3150 30 0001 C CNN +F 0 "#PWR013" H 9350 3150 30 0001 C CNN F 1 "GND" H 9350 3080 30 0001 C CNN 1 9350 3150 1 0 0 -1 $EndComp $Comp -L +3.3V #PWR03 +L +3.3V #PWR014 U 1 1 4C65D69B P 9350 2650 -F 0 "#PWR03" H 9350 2610 30 0001 C CNN +F 0 "#PWR014" H 9350 2610 30 0001 C CNN F 1 "+3.3V" H 9350 2760 30 0000 C CNN 1 9350 2650 1 0 0 -1 @@ -320,10 +320,10 @@ SPI_DQ[0..3] Text HLabel 2450 1700 0 60 Input ~ 0 SPI_FLASH_CS# $Comp -L GND #PWR04 +L GND #PWR015 U 1 1 4C65ABE9 P 2650 2450 -F 0 "#PWR04" H 2650 2450 30 0001 C CNN +F 0 "#PWR015" H 2650 2450 30 0001 C CNN F 1 "GND" H 2650 2380 30 0001 C CNN 1 2650 2450 1 0 0 -1 @@ -356,19 +356,19 @@ Entry Wire Line Entry Wire Line 8150 3150 8250 3050 $Comp -L +3.3V #PWR05 +L +3.3V #PWR016 U 1 1 4C646C14 P 7950 2900 -F 0 "#PWR05" H 7950 2860 30 0001 C CNN +F 0 "#PWR016" H 7950 2860 30 0001 C CNN F 1 "+3.3V" H 7950 3010 30 0000 C CNN 1 7950 2900 1 0 0 -1 $EndComp $Comp -L GND #PWR06 +L GND #PWR017 U 1 1 4C646BEA P 7950 3000 -F 0 "#PWR06" H 7950 3000 30 0001 C CNN +F 0 "#PWR017" H 7950 3000 30 0001 C CNN F 1 "GND" H 7950 2930 30 0001 C CNN 1 7950 3000 1 0 0 -1 @@ -418,10 +418,10 @@ SD_DAT3 Text Label 4200 6100 0 30 ~ 0 SD_CMD $Comp -L GND #PWR07 +L GND #PWR018 U 1 1 4C61D875 P 3950 5800 -F 0 "#PWR07" H 3950 5800 30 0001 C CNN +F 0 "#PWR018" H 3950 5800 30 0001 C CNN F 1 "GND" H 3950 5730 30 0001 C CNN 1 3950 5800 1 0 0 -1 @@ -433,19 +433,19 @@ SD_DAT0 Text Label 4200 5850 0 30 ~ 0 SD_DAT1 $Comp -L GND #PWR08 +L GND #PWR019 U 1 1 4C438ADC P 5800 6200 -F 0 "#PWR08" H 5800 6200 30 0001 C CNN +F 0 "#PWR019" H 5800 6200 30 0001 C CNN F 1 "GND" H 5800 6130 30 0001 C CNN 1 5800 6200 1 0 0 -1 $EndComp $Comp -L GND #PWR09 +L GND #PWR020 U 1 1 4C438AD5 P 5350 6550 -F 0 "#PWR09" H 5350 6550 30 0001 C CNN +F 0 "#PWR020" H 5350 6550 30 0001 C CNN F 1 "GND" H 5350 6480 30 0001 C CNN 1 5350 6550 1 0 0 -1 diff --git a/kicad/xue-rnc/PSU.sch b/kicad/xue-rnc/PSU.sch index e12bbf9..12b859f 100644 --- a/kicad/xue-rnc/PSU.sch +++ b/kicad/xue-rnc/PSU.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 18 Aug 2010 10:06:32 PM COT +EESchema Schematic File Version 2 date Thu 19 Aug 2010 08:32:00 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 @@ -59,64 +59,418 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr +Connection ~ 3700 1400 Wire Wire Line - 2100 2700 2100 2650 + 7400 1400 6750 1400 Wire Wire Line - 2100 2700 1800 2700 + 5150 2300 5150 2350 +Connection ~ 5850 2250 Wire Wire Line - 1800 2700 1800 2650 -Connection ~ 4350 2150 + 6000 2200 6000 2250 Wire Wire Line - 4400 2150 4200 2150 + 6000 2250 5650 2250 Wire Wire Line - 4400 2250 4350 2250 + 5850 2250 5850 2350 +Connection ~ 5750 1400 Wire Wire Line - 4350 2250 4350 2150 + 5700 1750 5750 1750 Wire Wire Line - 4200 2150 4200 2200 + 5750 1600 5550 1600 +Connection ~ 5150 1750 Wire Wire Line - 4400 2050 4200 2050 + 3700 2350 3700 2150 +Connection ~ 3800 1400 Wire Wire Line - 4200 2050 4200 1950 + 3900 1400 3400 1400 Wire Wire Line - 1950 2650 1950 2750 -Connection ~ 1950 2700 + 3150 6350 3150 6400 +Wire Wire Line + 3150 6400 2850 6400 +Wire Wire Line + 2850 6400 2850 6350 +Connection ~ 8200 4900 +Wire Wire Line + 8250 4900 8050 4900 +Wire Wire Line + 8250 5000 8200 5000 +Wire Wire Line + 8200 5000 8200 4900 +Wire Wire Line + 8050 4900 8050 4950 +Wire Wire Line + 8250 4800 8050 4800 +Wire Wire Line + 8050 4800 8050 4700 +Wire Wire Line + 3000 6450 3000 6350 +Connection ~ 3000 6400 +Wire Wire Line + 4500 2350 4500 2250 +Wire Wire Line + 3900 1750 3800 1750 +Wire Wire Line + 3800 1750 3800 1400 +Wire Wire Line + 3700 1400 3700 1950 +Wire Wire Line + 5200 1750 5100 1750 +Wire Wire Line + 5150 1800 5150 1600 +Wire Wire Line + 5150 1600 5350 1600 +Wire Wire Line + 5750 1750 5750 1400 +Connection ~ 5750 1600 +Wire Wire Line + 5650 2250 5650 2200 +Wire Wire Line + 6000 2000 6000 1950 +Wire Wire Line + 6000 1950 5650 1950 +Wire Wire Line + 5650 1950 5650 2000 +Wire Wire Line + 5850 1400 5850 1950 +Connection ~ 5850 1950 +Wire Wire Line + 6150 1400 5700 1400 +Connection ~ 5850 1400 +Connection ~ 9350 1400 +Wire Wire Line + 9650 1400 9200 1400 +Connection ~ 9350 1950 +Wire Wire Line + 9350 1400 9350 1950 +Wire Wire Line + 9150 2000 9150 1950 +Wire Wire Line + 9150 1950 9500 1950 +Wire Wire Line + 9500 1950 9500 2000 +Wire Wire Line + 9150 2200 9150 2250 +Connection ~ 9250 1600 +Wire Wire Line + 9250 1400 9250 1750 +Wire Wire Line + 8850 1600 8650 1600 +Wire Wire Line + 8650 1600 8650 1800 +Wire Wire Line + 8700 1750 8600 1750 +Connection ~ 7200 1400 +Wire Wire Line + 7200 1400 7200 1950 +Wire Wire Line + 7300 1400 7300 1750 +Wire Wire Line + 7300 1750 7400 1750 +Connection ~ 7300 1400 +Wire Wire Line + 7200 2350 7200 2150 +Connection ~ 8650 1750 +Wire Wire Line + 9250 1600 9050 1600 +Wire Wire Line + 9250 1750 9200 1750 +Connection ~ 9250 1400 +Wire Wire Line + 9350 2250 9350 2350 +Wire Wire Line + 9150 2250 9500 2250 +Wire Wire Line + 9500 2250 9500 2200 +Connection ~ 9350 2250 +Wire Wire Line + 8650 2300 8650 2350 +Wire Wire Line + 8000 2250 8000 2350 $Comp -L GND #PWR? +L +3.3V #PWR01 +U 1 1 4C6D30A1 +P 6150 1400 +F 0 "#PWR01" H 6150 1360 30 0001 C CNN +F 1 "+3.3V" H 6150 1510 30 0000 C CNN + 1 6150 1400 + 1 0 0 -1 +$EndComp +$Comp +L +1.2V #PWR02 +U 1 1 4C6D3097 +P 9650 1400 +F 0 "#PWR02" H 9650 1540 20 0001 C CNN +F 1 "+1.2V" H 9650 1510 30 0000 C CNN + 1 9650 1400 + 1 0 0 -1 +$EndComp +$Comp +L CAP C82 +U 1 1 4C6D2FD7 +P 7200 2050 +F 0 "C82" H 7250 2150 50 0000 L CNN +F 1 "4.7uF" H 7250 1950 50 0000 L CNN +F 2 "0805" H 7200 2050 60 0001 C CNN + 1 7200 2050 + 1 0 0 -1 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Eth + USB + microSD + CISAREA Eth-jack + id="tspan26304" + x="595.91925" + y="419.76498" + style="fill:#000080">Powersupply USBDDR1host + x="66213.242" + y="40438.074" + id="tspan26312" /> microsd - DDR0 - DDR1 - CIS area - - - - - - - - FPGA + id="tspan26316" + x="42774.434" + y="38940.027" + style="fill:#ff0000">DDR2 diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index 791f0fe..08d223b 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Wed 18 Aug 2010 10:06:32 PM COT +EESchema-LIBRARY Version 2.3 Date: Thu 19 Aug 2010 08:32:00 AM COT # # +1.2V # @@ -50,6 +50,21 @@ P 4 0 1 0 0 0 0 30 0 30 0 30 N ENDDRAW ENDDEF # +# A7108 +# +DEF A7108 U 0 40 Y Y 1 F N +F0 "U" 100 400 60 H V C CNN +F1 "A7108" 100 100 60 H V C CNN +DRAW +S -200 450 400 -250 0 1 0 f +X EN 1 -500 -50 300 R 50 50 1 1 W +X GND 2 100 -550 300 U 50 50 1 1 W +X SW 3 700 300 300 L 50 50 1 1 W +X VIN 4 -500 300 300 R 50 50 1 1 W +X VFB 5 700 -50 300 L 50 50 1 1 W +ENDDRAW +ENDDEF +# # A7130 # DEF A7130 U 0 40 Y Y 1 F N diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index acfa2d0..342b33f 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,20 +1,20 @@ -PCBNEW-BOARD Version 1 date Thu 19 Aug 2010 05:38:16 AM COT +PCBNEW-BOARD Version 1 date Thu 19 Aug 2010 08:38:11 AM COT -# Created by Pcbnew(2010-07-27 BZR 2423)-unstable +# Created by Pcbnew(2010-07-15 BZR 2414)-unstable $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 13FF801F -Links 643 -NoConn 618 +Links 675 +NoConn 650 Di 45200 13470 70189 50668 Ndraw 7 Ntrack 271 Nzone 0 BoardThickness 630 -Nmodule 145 -Nnets 246 +Nmodule 161 +Nnets 252 $EndGENERAL $SHEETDESCR @@ -90,55 +90,55 @@ Na 5 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A11" +Na 6 "/DDR_Banks/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_A12" +Na 7 "/DDR_Banks/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_A2" +Na 8 "/DDR_Banks/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_A6" +Na 9 "/DDR_Banks/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_A9" +Na 10 "/DDR_Banks/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_CAS#" +Na 11 "/DDR_Banks/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_CLK" +Na 12 "/DDR_Banks/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M0_DQ11" +Na 13 "/DDR_Banks/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M0_DQ14" +Na 14 "/DDR_Banks/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M0_DQ3" +Na 15 "/DDR_Banks/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M0_DQ6" +Na 16 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M0_DQ9" +Na 17 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M0_LDQS" +Na 18 "/DDR_Banks/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT @@ -150,375 +150,375 @@ Na 20 "/DDR_Banks/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M1_A2" +Na 21 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M1_A4" +Na 22 "/DDR_Banks/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_A7" +Na 23 "/DDR_Banks/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_A8" +Na 24 "/DDR_Banks/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_A9" +Na 25 "/DDR_Banks/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_BA0" +Na 26 "/DDR_Banks/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_BA1" +Na 27 "/DDR_Banks/M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_CAS#" +Na 28 "/DDR_Banks/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/DDR_Banks/M1_CKE" +Na 29 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/DDR_Banks/M1_CLK" +Na 30 "/DDR_Banks/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/DDR_Banks/M1_CLK#" +Na 31 "/DDR_Banks/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/DDR_Banks/M1_DQ0" +Na 32 "/DDR_Banks/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/DDR_Banks/M1_DQ13" +Na 33 "/DDR_Banks/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/DDR_Banks/M1_DQ2" +Na 34 "/DDR_Banks/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/DDR_Banks/M1_DQ3" +Na 35 "/DDR_Banks/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/DDR_Banks/M1_DQ6" +Na 36 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/DDR_Banks/M1_DQ7" +Na 37 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/DDR_Banks/M1_LDQS" +Na 38 "/Ethernet_Phy/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/DDR_Banks/M1_UDM" +Na 39 "/Ethernet_Phy/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/DDR_Banks/M1_WE#" +Na 40 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_A1.8V" +Na 41 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_A3.3V" +Na 42 "/Ethernet_Phy/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/Ethernet_Phy/ETH_CLK" +Na 43 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/Ethernet_Phy/ETH_COL" +Na 44 "/Ethernet_Phy/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/Ethernet_Phy/ETH_CRS" +Na 45 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/Ethernet_Phy/ETH_LED0" +Na 46 "/Ethernet_Phy/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/Ethernet_Phy/ETH_LED1" +Na 47 "/Ethernet_Phy/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/Ethernet_Phy/ETH_MDC" +Na 48 "/Ethernet_Phy/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/Ethernet_Phy/ETH_PLL1.8V" +Na 49 "/Ethernet_Phy/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/Ethernet_Phy/ETH_RXD1" +Na 50 "/Ethernet_Phy/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/Ethernet_Phy/ETH_RXD3" +Na 51 "/Ethernet_Phy/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/Ethernet_Phy/ETH_TXD0" +Na 52 "/Ethernet_Phy/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/Ethernet_Phy/ETH_TXD2" +Na 53 "/FPGA_Spartan6/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/Ethernet_Phy/ETH_TXD3" +Na 54 "/FPGA_Spartan6/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/Ethernet_Phy/ETH_TXER" +Na 55 "/FPGA_Spartan6/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/ETH_INT" +Na 56 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/ETH_MDIO" +Na 57 "/FPGA_Spartan6/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/ETH_RESET_N" +Na 58 "/FPGA_Spartan6/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/ETH_RXC" +Na 59 "/FPGA_Spartan6/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/ETH_RXD0" +Na 60 "/FPGA_Spartan6/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/ETH_RXD2" +Na 61 "/FPGA_Spartan6/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/ETH_RXDV" +Na 62 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/ETH_RXER" +Na 63 "/FPGA_Spartan6/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/ETH_TXC" +Na 64 "/FPGA_Spartan6/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/ETH_TXD1" +Na 65 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/ETH_TXEN" +Na 66 "/FPGA_Spartan6/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/M0_A0" +Na 67 "/FPGA_Spartan6/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/M0_A1" +Na 68 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_A10" +Na 69 "/FPGA_Spartan6/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_A3" +Na 70 "/FPGA_Spartan6/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_A4" +Na 71 "/FPGA_Spartan6/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_A5" +Na 72 "/FPGA_Spartan6/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_A7" +Na 73 "/FPGA_Spartan6/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_A8" +Na 74 "/FPGA_Spartan6/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_BA0" +Na 75 "/FPGA_Spartan6/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_BA1" +Na 76 "/FPGA_Spartan6/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_CKE" +Na 77 "/FPGA_Spartan6/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_CLK#" +Na 78 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_DQ0" +Na 79 "/FPGA_Spartan6/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 80 "/FPGA_Spartan6/M0_DQ1" +Na 80 "/FPGA_Spartan6/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_DQ10" +Na 81 "/FPGA_Spartan6/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_DQ12" +Na 82 "/FPGA_Spartan6/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_DQ13" +Na 83 "/FPGA_Spartan6/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_DQ15" +Na 84 "/FPGA_Spartan6/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M0_DQ2" +Na 85 "/FPGA_Spartan6/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M0_DQ4" +Na 86 "/FPGA_Spartan6/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M0_DQ5" +Na 87 "/FPGA_Spartan6/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M0_DQ7" +Na 88 "/FPGA_Spartan6/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M0_DQ8" +Na 89 "/FPGA_Spartan6/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M0_LDM" +Na 90 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M0_RAS#" +Na 91 "/FPGA_Spartan6/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M0_UDM" +Na 92 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M0_WE#" +Na 93 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_A0" +Na 94 "/FPGA_Spartan6/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_A1" +Na 95 "/FPGA_Spartan6/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_A11" +Na 96 "/FPGA_Spartan6/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_A12" +Na 97 "/FPGA_Spartan6/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_A3" +Na 98 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_A5" +Na 99 "/FPGA_Spartan6/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_A6" +Na 100 "/FPGA_Spartan6/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_CS#" +Na 101 "/FPGA_Spartan6/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_DQ1" +Na 102 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_DQ10" +Na 103 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_DQ11" +Na 104 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ12" +Na 105 "/FPGA_Spartan6/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_DQ14" +Na 106 "/FPGA_Spartan6/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_DQ15" +Na 107 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_DQ4" +Na 108 "/FPGA_Spartan6/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ5" +Na 109 "/FPGA_Spartan6/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_DQ8" +Na 110 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_DQ9" +Na 111 "/FPGA_Spartan6/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Spartan6/M1_LDM" +Na 112 "/FPGA_Spartan6/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_RAS#" +Na 113 "/FPGA_Spartan6/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT @@ -526,11 +526,11 @@ Na 114 "/FPGA_Spartan6/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/NF_ALE" +Na 115 "/FPGA_Spartan6/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/NF_CLE" +Na 116 "/FPGA_Spartan6/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT @@ -542,407 +542,407 @@ Na 118 "/FPGA_Spartan6/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/NF_D3" +Na 119 "/FPGA_Spartan6/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Spartan6/NF_D4" +Na 120 "/FPGA_Spartan6/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Spartan6/NF_D6" +Na 121 "/FPGA_Spartan6/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Spartan6/NF_D7" +Na 122 "/FPGA_Spartan6/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Spartan6/NF_RE_N" +Na 123 "/FPGA_Spartan6/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Spartan6/NF_RNB" +Na 124 "/FPGA_Spartan6/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Spartan6/NF_WE_N" +Na 125 "/FPGA_Spartan6/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Spartan6/PROG_CCLK" +Na 126 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Spartan6/PROG_CSO" +Na 127 "/FPGA_Spartan6/R_M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Spartan6/PROG_MISO0" +Na 128 "/FPGA_Spartan6/R_M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/FPGA_Spartan6/PROG_MISO1" +Na 129 "/FPGA_Spartan6/R_M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/FPGA_Spartan6/PROG_MISO2" +Na 130 "/FPGA_Spartan6/R_M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/FPGA_Spartan6/PROG_MISO3" +Na 131 "/FPGA_Spartan6/R_M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/FPGA_Spartan6/R_M0_A0" +Na 132 "/FPGA_Spartan6/R_M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/FPGA_Spartan6/R_M0_A1" +Na 133 "/FPGA_Spartan6/R_M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/FPGA_Spartan6/R_M0_A10" +Na 134 "/FPGA_Spartan6/R_M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/FPGA_Spartan6/R_M0_A11" +Na 135 "/FPGA_Spartan6/R_M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/FPGA_Spartan6/R_M0_A12" +Na 136 "/FPGA_Spartan6/R_M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/FPGA_Spartan6/R_M0_A2" +Na 137 "/FPGA_Spartan6/R_M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/FPGA_Spartan6/R_M0_A3" +Na 138 "/FPGA_Spartan6/R_M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/FPGA_Spartan6/R_M0_A4" +Na 139 "/FPGA_Spartan6/R_M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/FPGA_Spartan6/R_M0_A5" +Na 140 "/FPGA_Spartan6/R_M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/FPGA_Spartan6/R_M0_A6" +Na 141 "/FPGA_Spartan6/R_M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/FPGA_Spartan6/R_M0_A7" +Na 142 "/FPGA_Spartan6/R_M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/FPGA_Spartan6/R_M0_A8" +Na 143 "/FPGA_Spartan6/R_M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/FPGA_Spartan6/R_M0_A9" +Na 144 "/FPGA_Spartan6/R_M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 145 "/FPGA_Spartan6/R_M0_BA0" +Na 145 "/FPGA_Spartan6/R_M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 146 "/FPGA_Spartan6/R_M0_BA1" +Na 146 "/FPGA_Spartan6/R_M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 147 "/FPGA_Spartan6/R_M0_CAS#" +Na 147 "/FPGA_Spartan6/R_M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 148 "/FPGA_Spartan6/R_M0_CKE" +Na 148 "/FPGA_Spartan6/R_M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 149 "/FPGA_Spartan6/R_M0_DQ0" +Na 149 "/FPGA_Spartan6/R_M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 150 "/FPGA_Spartan6/R_M0_DQ1" +Na 150 "/FPGA_Spartan6/R_M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "/FPGA_Spartan6/R_M0_DQ10" +Na 151 "/FPGA_Spartan6/R_M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "/FPGA_Spartan6/R_M0_DQ11" +Na 152 "/FPGA_Spartan6/R_M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "/FPGA_Spartan6/R_M0_DQ12" +Na 153 "/FPGA_Spartan6/R_M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "/FPGA_Spartan6/R_M0_DQ13" +Na 154 "/FPGA_Spartan6/R_M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "/FPGA_Spartan6/R_M0_DQ14" +Na 155 "/FPGA_Spartan6/R_M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "/FPGA_Spartan6/R_M0_DQ15" +Na 156 "/FPGA_Spartan6/R_M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "/FPGA_Spartan6/R_M0_DQ2" +Na 157 "/FPGA_Spartan6/R_M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "/FPGA_Spartan6/R_M0_DQ3" +Na 158 "/FPGA_Spartan6/R_M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "/FPGA_Spartan6/R_M0_DQ4" +Na 159 "/FPGA_Spartan6/R_M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "/FPGA_Spartan6/R_M0_DQ5" +Na 160 "/FPGA_Spartan6/R_M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "/FPGA_Spartan6/R_M0_DQ6" +Na 161 "/FPGA_Spartan6/R_M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "/FPGA_Spartan6/R_M0_DQ7" +Na 162 "/FPGA_Spartan6/R_M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "/FPGA_Spartan6/R_M0_DQ8" +Na 163 "/FPGA_Spartan6/R_M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "/FPGA_Spartan6/R_M0_DQ9" +Na 164 "/FPGA_Spartan6/R_M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "/FPGA_Spartan6/R_M0_LDM" +Na 165 "/FPGA_Spartan6/R_M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "/FPGA_Spartan6/R_M0_LDQS" +Na 166 "/FPGA_Spartan6/R_M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "/FPGA_Spartan6/R_M0_RAS#" +Na 167 "/FPGA_Spartan6/R_M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "/FPGA_Spartan6/R_M0_UDM" +Na 168 "/FPGA_Spartan6/R_M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "/FPGA_Spartan6/R_M0_UDQS" +Na 169 "/FPGA_Spartan6/R_M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "/FPGA_Spartan6/R_M0_WE#" +Na 170 "/FPGA_Spartan6/R_M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "/FPGA_Spartan6/R_M1_A0" +Na 171 "/FPGA_Spartan6/R_M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "/FPGA_Spartan6/R_M1_A1" +Na 172 "/FPGA_Spartan6/R_M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "/FPGA_Spartan6/R_M1_A10" +Na 173 "/FPGA_Spartan6/R_M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 174 "/FPGA_Spartan6/R_M1_A11" +Na 174 "/FPGA_Spartan6/R_M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 175 "/FPGA_Spartan6/R_M1_A12" +Na 175 "/FPGA_Spartan6/R_M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 176 "/FPGA_Spartan6/R_M1_A2" +Na 176 "/FPGA_Spartan6/R_M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 177 "/FPGA_Spartan6/R_M1_A3" +Na 177 "/FPGA_Spartan6/R_M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 178 "/FPGA_Spartan6/R_M1_A5" +Na 178 "/FPGA_Spartan6/R_M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 179 "/FPGA_Spartan6/R_M1_A6" +Na 179 "/FPGA_Spartan6/R_M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 180 "/FPGA_Spartan6/R_M1_A7" +Na 180 "/FPGA_Spartan6/R_M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 181 "/FPGA_Spartan6/R_M1_A8" +Na 181 "/FPGA_Spartan6/R_M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 182 "/FPGA_Spartan6/R_M1_A9" +Na 182 "/FPGA_Spartan6/R_M1_CS#" St ~ $EndEQUIPOT $EQUIPOT -Na 183 "/FPGA_Spartan6/R_M1_BA0" +Na 183 "/FPGA_Spartan6/R_M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 184 "/FPGA_Spartan6/R_M1_BA1" +Na 184 "/FPGA_Spartan6/R_M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 185 "/FPGA_Spartan6/R_M1_CAS#" +Na 185 "/FPGA_Spartan6/R_M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 186 "/FPGA_Spartan6/R_M1_CKE" +Na 186 "/FPGA_Spartan6/R_M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 187 "/FPGA_Spartan6/R_M1_CS#" +Na 187 "/FPGA_Spartan6/R_M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 188 "/FPGA_Spartan6/R_M1_DQ0" +Na 188 "/FPGA_Spartan6/R_M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 189 "/FPGA_Spartan6/R_M1_DQ1" +Na 189 "/FPGA_Spartan6/R_M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 190 "/FPGA_Spartan6/R_M1_DQ10" +Na 190 "/FPGA_Spartan6/R_M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 191 "/FPGA_Spartan6/R_M1_DQ11" +Na 191 "/FPGA_Spartan6/R_M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 192 "/FPGA_Spartan6/R_M1_DQ12" +Na 192 "/FPGA_Spartan6/R_M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 193 "/FPGA_Spartan6/R_M1_DQ13" +Na 193 "/FPGA_Spartan6/R_M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 194 "/FPGA_Spartan6/R_M1_DQ14" +Na 194 "/FPGA_Spartan6/R_M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 195 "/FPGA_Spartan6/R_M1_DQ15" +Na 195 "/FPGA_Spartan6/R_M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 196 "/FPGA_Spartan6/R_M1_DQ2" +Na 196 "/FPGA_Spartan6/R_M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 197 "/FPGA_Spartan6/R_M1_DQ3" +Na 197 "/FPGA_Spartan6/R_M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 198 "/FPGA_Spartan6/R_M1_DQ4" +Na 198 "/FPGA_Spartan6/R_M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 199 "/FPGA_Spartan6/R_M1_DQ5" +Na 199 "/FPGA_Spartan6/R_M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 200 "/FPGA_Spartan6/R_M1_DQ6" +Na 200 "/FPGA_Spartan6/R_M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 201 "/FPGA_Spartan6/R_M1_DQ7" +Na 201 "/FPGA_Spartan6/R_M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 202 "/FPGA_Spartan6/R_M1_DQ8" +Na 202 "/FPGA_Spartan6/R_M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 203 "/FPGA_Spartan6/R_M1_DQ9" +Na 203 "/FPGA_Spartan6/R_M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 204 "/FPGA_Spartan6/R_M1_LDM" +Na 204 "/FPGA_Spartan6/R_M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 205 "/FPGA_Spartan6/R_M1_LDQS" +Na 205 "/FPGA_Spartan6/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 206 "/FPGA_Spartan6/R_M1_RAS#" +Na 206 "/FPGA_Spartan6/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 207 "/FPGA_Spartan6/R_M1_UDM" +Na 207 "/FPGA_Spartan6/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 208 "/FPGA_Spartan6/R_M1_UDQS" +Na 208 "/Non_volatile_memories/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 209 "/FPGA_Spartan6/R_M1_WE#" +Na 209 "/Non_volatile_memories/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 210 "/FPGA_Spartan6/SD_CLK" +Na 210 "/Non_volatile_memories/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 211 "/FPGA_Spartan6/SD_CMD" +Na 211 "/Non_volatile_memories/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 212 "/FPGA_Spartan6/SD_DAT1" +Na 212 "/Non_volatile_memories/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 213 "/FPGA_Spartan6/USBA_OE_N" +Na 213 "/Non_volatile_memories/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 214 "/FPGA_Spartan6/USBA_RCV" +Na 214 "/Non_volatile_memories/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 215 "/FPGA_Spartan6/USBA_VM" +Na 215 "/Non_volatile_memories/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 216 "/Non_volatile_memories/NF_CS1_N" +Na 216 "/Non_volatile_memories/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 217 "/Non_volatile_memories/NF_D2" +Na 217 "/Non_volatile_memories/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 218 "/Non_volatile_memories/NF_D5" +Na 218 "/Non_volatile_memories/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 219 "/Non_volatile_memories/SD_DAT0" +Na 219 "/Non_volatile_memories/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT @@ -950,11 +950,11 @@ Na 220 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 221 "/Non_volatile_memories/SD_DAT3" +Na 221 "/USB/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 222 "/USB/USBA_SPD" +Na 222 "/USB/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT @@ -974,67 +974,67 @@ Na 226 "N-000059" St ~ $EndEQUIPOT $EQUIPOT -Na 227 "N-000398" +Na 227 "N-000395" St ~ $EndEQUIPOT $EQUIPOT -Na 228 "N-000407" +Na 228 "N-000396" St ~ $EndEQUIPOT $EQUIPOT -Na 229 "N-000409" +Na 229 "N-000397" St ~ $EndEQUIPOT $EQUIPOT -Na 230 "N-000410" +Na 230 "N-000402" St ~ $EndEQUIPOT $EQUIPOT -Na 231 "N-000411" +Na 231 "N-000403" St ~ $EndEQUIPOT $EQUIPOT -Na 232 "N-000412" +Na 232 "N-000404" St ~ $EndEQUIPOT $EQUIPOT -Na 233 "N-000413" +Na 233 "N-000405" St ~ $EndEQUIPOT $EQUIPOT -Na 234 "N-000415" +Na 234 "N-000406" St ~ $EndEQUIPOT $EQUIPOT -Na 235 "N-000418" +Na 235 "N-000422" St ~ $EndEQUIPOT $EQUIPOT -Na 236 "N-000420" +Na 236 "N-000424" St ~ $EndEQUIPOT $EQUIPOT -Na 237 "N-000422" +Na 237 "N-000425" St ~ $EndEQUIPOT $EQUIPOT -Na 238 "N-000423" +Na 238 "N-000426" St ~ $EndEQUIPOT $EQUIPOT -Na 239 "N-000424" +Na 239 "N-000427" St ~ $EndEQUIPOT $EQUIPOT -Na 240 "N-000425" +Na 240 "N-000429" St ~ $EndEQUIPOT $EQUIPOT -Na 241 "N-000426" +Na 241 "N-000430" St ~ $EndEQUIPOT $EQUIPOT -Na 242 "N-000427" +Na 242 "N-000431" St ~ $EndEQUIPOT $EQUIPOT @@ -1046,7 +1046,31 @@ Na 244 "N-000433" St ~ $EndEQUIPOT $EQUIPOT -Na 245 "VCCO2" +Na 245 "N-000434" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 246 "N-000435" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 247 "N-000436" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 248 "N-000437" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 249 "N-000447" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 250 "N-000466" +St ~ +$EndEQUIPOT +$EQUIPOT +Na 251 "VCCO2" St ~ $EndEQUIPOT $NCLASS @@ -1064,121 +1088,116 @@ AddNet "+1.8V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" -AddNet "/DDR_Banks/M0_A11" -AddNet "/DDR_Banks/M0_A12" -AddNet "/DDR_Banks/M0_A2" -AddNet "/DDR_Banks/M0_A6" -AddNet "/DDR_Banks/M0_A9" -AddNet "/DDR_Banks/M0_CAS#" +AddNet "/DDR_Banks/M0_A0" +AddNet "/DDR_Banks/M0_CKE" AddNet "/DDR_Banks/M0_CLK" +AddNet "/DDR_Banks/M0_CLK#" +AddNet "/DDR_Banks/M0_DQ1" +AddNet "/DDR_Banks/M0_DQ10" AddNet "/DDR_Banks/M0_DQ11" +AddNet "/DDR_Banks/M0_DQ12" +AddNet "/DDR_Banks/M0_DQ13" AddNet "/DDR_Banks/M0_DQ14" -AddNet "/DDR_Banks/M0_DQ3" -AddNet "/DDR_Banks/M0_DQ6" -AddNet "/DDR_Banks/M0_DQ9" +AddNet "/DDR_Banks/M0_LDM" AddNet "/DDR_Banks/M0_LDQS" +AddNet "/DDR_Banks/M0_RAS#" AddNet "/DDR_Banks/M0_UDQS" AddNet "/DDR_Banks/M1_A10" -AddNet "/DDR_Banks/M1_A2" -AddNet "/DDR_Banks/M1_A4" -AddNet "/DDR_Banks/M1_A7" +AddNet "/DDR_Banks/M1_A12" +AddNet "/DDR_Banks/M1_A6" AddNet "/DDR_Banks/M1_A8" -AddNet "/DDR_Banks/M1_A9" AddNet "/DDR_Banks/M1_BA0" AddNet "/DDR_Banks/M1_BA1" -AddNet "/DDR_Banks/M1_CAS#" -AddNet "/DDR_Banks/M1_CKE" -AddNet "/DDR_Banks/M1_CLK" AddNet "/DDR_Banks/M1_CLK#" -AddNet "/DDR_Banks/M1_DQ0" +AddNet "/DDR_Banks/M1_CS#" +AddNet "/DDR_Banks/M1_DQ1" +AddNet "/DDR_Banks/M1_DQ10" +AddNet "/DDR_Banks/M1_DQ11" +AddNet "/DDR_Banks/M1_DQ12" AddNet "/DDR_Banks/M1_DQ13" -AddNet "/DDR_Banks/M1_DQ2" AddNet "/DDR_Banks/M1_DQ3" -AddNet "/DDR_Banks/M1_DQ6" -AddNet "/DDR_Banks/M1_DQ7" AddNet "/DDR_Banks/M1_LDQS" -AddNet "/DDR_Banks/M1_UDM" AddNet "/DDR_Banks/M1_WE#" AddNet "/Ethernet_Phy/ETH_CLK" -AddNet "/Ethernet_Phy/ETH_COL" AddNet "/Ethernet_Phy/ETH_CRS" AddNet "/Ethernet_Phy/ETH_MDC" +AddNet "/Ethernet_Phy/ETH_RXD0" AddNet "/Ethernet_Phy/ETH_RXD1" +AddNet "/Ethernet_Phy/ETH_RXD2" AddNet "/Ethernet_Phy/ETH_RXD3" -AddNet "/Ethernet_Phy/ETH_TXD0" -AddNet "/Ethernet_Phy/ETH_TXD2" -AddNet "/Ethernet_Phy/ETH_TXD3" +AddNet "/Ethernet_Phy/ETH_RXDV" +AddNet "/Ethernet_Phy/ETH_RXER" +AddNet "/Ethernet_Phy/ETH_TXD1" +AddNet "/Ethernet_Phy/ETH_TXEN" AddNet "/Ethernet_Phy/ETH_TXER" +AddNet "/FPGA_Spartan6/ETH_COL" AddNet "/FPGA_Spartan6/ETH_INT" AddNet "/FPGA_Spartan6/ETH_MDIO" AddNet "/FPGA_Spartan6/ETH_RESET_N" AddNet "/FPGA_Spartan6/ETH_RXC" -AddNet "/FPGA_Spartan6/ETH_RXD0" -AddNet "/FPGA_Spartan6/ETH_RXD2" -AddNet "/FPGA_Spartan6/ETH_RXDV" -AddNet "/FPGA_Spartan6/ETH_RXER" AddNet "/FPGA_Spartan6/ETH_TXC" -AddNet "/FPGA_Spartan6/ETH_TXD1" -AddNet "/FPGA_Spartan6/ETH_TXEN" -AddNet "/FPGA_Spartan6/M0_A0" +AddNet "/FPGA_Spartan6/ETH_TXD0" +AddNet "/FPGA_Spartan6/ETH_TXD2" +AddNet "/FPGA_Spartan6/ETH_TXD3" AddNet "/FPGA_Spartan6/M0_A1" AddNet "/FPGA_Spartan6/M0_A10" +AddNet "/FPGA_Spartan6/M0_A11" +AddNet "/FPGA_Spartan6/M0_A12" +AddNet "/FPGA_Spartan6/M0_A2" AddNet "/FPGA_Spartan6/M0_A3" AddNet "/FPGA_Spartan6/M0_A4" AddNet "/FPGA_Spartan6/M0_A5" +AddNet "/FPGA_Spartan6/M0_A6" AddNet "/FPGA_Spartan6/M0_A7" AddNet "/FPGA_Spartan6/M0_A8" +AddNet "/FPGA_Spartan6/M0_A9" AddNet "/FPGA_Spartan6/M0_BA0" AddNet "/FPGA_Spartan6/M0_BA1" -AddNet "/FPGA_Spartan6/M0_CKE" -AddNet "/FPGA_Spartan6/M0_CLK#" +AddNet "/FPGA_Spartan6/M0_CAS#" AddNet "/FPGA_Spartan6/M0_DQ0" -AddNet "/FPGA_Spartan6/M0_DQ1" -AddNet "/FPGA_Spartan6/M0_DQ10" -AddNet "/FPGA_Spartan6/M0_DQ12" -AddNet "/FPGA_Spartan6/M0_DQ13" AddNet "/FPGA_Spartan6/M0_DQ15" AddNet "/FPGA_Spartan6/M0_DQ2" +AddNet "/FPGA_Spartan6/M0_DQ3" AddNet "/FPGA_Spartan6/M0_DQ4" AddNet "/FPGA_Spartan6/M0_DQ5" +AddNet "/FPGA_Spartan6/M0_DQ6" AddNet "/FPGA_Spartan6/M0_DQ7" AddNet "/FPGA_Spartan6/M0_DQ8" -AddNet "/FPGA_Spartan6/M0_LDM" -AddNet "/FPGA_Spartan6/M0_RAS#" +AddNet "/FPGA_Spartan6/M0_DQ9" AddNet "/FPGA_Spartan6/M0_UDM" AddNet "/FPGA_Spartan6/M0_WE#" AddNet "/FPGA_Spartan6/M1_A0" AddNet "/FPGA_Spartan6/M1_A1" AddNet "/FPGA_Spartan6/M1_A11" -AddNet "/FPGA_Spartan6/M1_A12" +AddNet "/FPGA_Spartan6/M1_A2" AddNet "/FPGA_Spartan6/M1_A3" +AddNet "/FPGA_Spartan6/M1_A4" AddNet "/FPGA_Spartan6/M1_A5" -AddNet "/FPGA_Spartan6/M1_A6" -AddNet "/FPGA_Spartan6/M1_CS#" -AddNet "/FPGA_Spartan6/M1_DQ1" -AddNet "/FPGA_Spartan6/M1_DQ10" -AddNet "/FPGA_Spartan6/M1_DQ11" -AddNet "/FPGA_Spartan6/M1_DQ12" +AddNet "/FPGA_Spartan6/M1_A7" +AddNet "/FPGA_Spartan6/M1_A9" +AddNet "/FPGA_Spartan6/M1_CAS#" +AddNet "/FPGA_Spartan6/M1_CKE" +AddNet "/FPGA_Spartan6/M1_CLK" +AddNet "/FPGA_Spartan6/M1_DQ0" AddNet "/FPGA_Spartan6/M1_DQ14" AddNet "/FPGA_Spartan6/M1_DQ15" +AddNet "/FPGA_Spartan6/M1_DQ2" AddNet "/FPGA_Spartan6/M1_DQ4" AddNet "/FPGA_Spartan6/M1_DQ5" +AddNet "/FPGA_Spartan6/M1_DQ6" +AddNet "/FPGA_Spartan6/M1_DQ7" AddNet "/FPGA_Spartan6/M1_DQ8" AddNet "/FPGA_Spartan6/M1_DQ9" AddNet "/FPGA_Spartan6/M1_LDM" AddNet "/FPGA_Spartan6/M1_RAS#" +AddNet "/FPGA_Spartan6/M1_UDM" AddNet "/FPGA_Spartan6/M1_UDQS" -AddNet "/FPGA_Spartan6/NF_ALE" AddNet "/FPGA_Spartan6/NF_CLE" +AddNet "/FPGA_Spartan6/NF_CS1_N" AddNet "/FPGA_Spartan6/NF_D0" AddNet "/FPGA_Spartan6/NF_D1" -AddNet "/FPGA_Spartan6/NF_D3" -AddNet "/FPGA_Spartan6/NF_D4" -AddNet "/FPGA_Spartan6/NF_D6" +AddNet "/FPGA_Spartan6/NF_D5" AddNet "/FPGA_Spartan6/NF_D7" -AddNet "/FPGA_Spartan6/NF_RE_N" -AddNet "/FPGA_Spartan6/NF_RNB" -AddNet "/FPGA_Spartan6/NF_WE_N" AddNet "/FPGA_Spartan6/PROG_CCLK" AddNet "/FPGA_Spartan6/PROG_CSO" AddNet "/FPGA_Spartan6/PROG_MISO0" @@ -1263,41 +1282,52 @@ AddNet "/FPGA_Spartan6/R_M1_RAS#" AddNet "/FPGA_Spartan6/R_M1_UDM" AddNet "/FPGA_Spartan6/R_M1_UDQS" AddNet "/FPGA_Spartan6/R_M1_WE#" -AddNet "/FPGA_Spartan6/SD_CLK" -AddNet "/FPGA_Spartan6/SD_CMD" -AddNet "/FPGA_Spartan6/SD_DAT1" +AddNet "/FPGA_Spartan6/SD_DAT3" AddNet "/FPGA_Spartan6/USBA_OE_N" -AddNet "/FPGA_Spartan6/USBA_RCV" -AddNet "/FPGA_Spartan6/USBA_VM" -AddNet "/Non_volatile_memories/NF_CS1_N" +AddNet "/FPGA_Spartan6/USBA_SPD" +AddNet "/Non_volatile_memories/NF_ALE" AddNet "/Non_volatile_memories/NF_D2" -AddNet "/Non_volatile_memories/NF_D5" +AddNet "/Non_volatile_memories/NF_D3" +AddNet "/Non_volatile_memories/NF_D4" +AddNet "/Non_volatile_memories/NF_D6" +AddNet "/Non_volatile_memories/NF_RE_N" +AddNet "/Non_volatile_memories/NF_RNB" +AddNet "/Non_volatile_memories/NF_WE_N" +AddNet "/Non_volatile_memories/SD_CLK" +AddNet "/Non_volatile_memories/SD_CMD" AddNet "/Non_volatile_memories/SD_DAT0" +AddNet "/Non_volatile_memories/SD_DAT1" AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "/Non_volatile_memories/SD_DAT3" -AddNet "/USB/USBA_SPD" +AddNet "/USB/USBA_RCV" +AddNet "/USB/USBA_VM" AddNet "/USB/USBA_VP" AddNet "GND" AddNet "N-000058" AddNet "N-000059" -AddNet "N-000398" -AddNet "N-000407" -AddNet "N-000409" -AddNet "N-000410" -AddNet "N-000411" -AddNet "N-000412" -AddNet "N-000413" -AddNet "N-000415" -AddNet "N-000418" -AddNet "N-000420" +AddNet "N-000395" +AddNet "N-000396" +AddNet "N-000397" +AddNet "N-000402" +AddNet "N-000403" +AddNet "N-000404" +AddNet "N-000405" +AddNet "N-000406" AddNet "N-000422" -AddNet "N-000423" AddNet "N-000424" AddNet "N-000425" AddNet "N-000426" AddNet "N-000427" +AddNet "N-000429" +AddNet "N-000430" +AddNet "N-000431" AddNet "N-000432" AddNet "N-000433" +AddNet "N-000434" +AddNet "N-000435" +AddNet "N-000436" +AddNet "N-000437" +AddNet "N-000447" +AddNet "N-000466" AddNet "VCCO2" $EndNCLASS $NCLASS @@ -1397,63 +1427,63 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_CLK" +Ne 38 "/Ethernet_Phy/ETH_CLK" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RESET_N" +Ne 56 "/FPGA_Spartan6/ETH_RESET_N" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_RXD0" +Ne 44 "/Ethernet_Phy/ETH_RXD0" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_RXER" +Ne 49 "/Ethernet_Phy/ETH_RXER" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/ETH_TXEN" +Ne 51 "/Ethernet_Phy/ETH_TXEN" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXD3" +Ne 61 "/FPGA_Spartan6/ETH_TXD3" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_INT" +Ne 54 "/FPGA_Spartan6/ETH_INT" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_D7" +Ne 120 "/FPGA_Spartan6/NF_D7" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/NF_D3" +Ne 210 "/Non_volatile_memories/NF_D3" Po 196 -4133 $EndPAD $PAD @@ -1474,14 +1504,14 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_ALE" +Ne 208 "/Non_volatile_memories/NF_ALE" Po 1377 -4133 $EndPAD $PAD Sh "A16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/NF_RNB" +Ne 214 "/Non_volatile_memories/NF_RNB" Po 1771 -4133 $EndPAD $PAD @@ -1495,7 +1525,7 @@ $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 219 "/Non_volatile_memories/SD_DAT0" +Ne 218 "/Non_volatile_memories/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -1565,7 +1595,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_RXD1" +Ne 45 "/Ethernet_Phy/ETH_RXD1" Po -2165 -3739 $EndPAD $PAD @@ -1579,7 +1609,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/ETH_TXER" +Ne 52 "/Ethernet_Phy/ETH_TXER" Po -1377 -3739 $EndPAD $PAD @@ -1593,7 +1623,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_COL" +Ne 53 "/FPGA_Spartan6/ETH_COL" Po -590 -3739 $EndPAD $PAD @@ -1607,7 +1637,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/NF_D4" +Ne 211 "/Non_volatile_memories/NF_D4" Po 196 -3739 $EndPAD $PAD @@ -1635,7 +1665,7 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/NF_RE_N" +Ne 213 "/Non_volatile_memories/NF_RE_N" Po 1771 -3739 $EndPAD $PAD @@ -1649,7 +1679,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 212 "/FPGA_Spartan6/SD_DAT1" +Ne 219 "/Non_volatile_memories/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1684,7 +1714,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/FPGA_Spartan6/R_M0_A11" +Ne 130 "/FPGA_Spartan6/R_M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1712,42 +1742,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_MDIO" +Ne 55 "/FPGA_Spartan6/ETH_MDIO" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_RXD2" +Ne 46 "/Ethernet_Phy/ETH_RXD2" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_RXDV" +Ne 48 "/Ethernet_Phy/ETH_RXDV" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/ETH_TXD1" +Ne 50 "/Ethernet_Phy/ETH_TXD1" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_TXD2" +Ne 60 "/FPGA_Spartan6/ETH_TXD2" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_CRS" +Ne 39 "/Ethernet_Phy/ETH_CRS" Po -590 -3346 $EndPAD $PAD @@ -1761,14 +1791,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 218 "/Non_volatile_memories/NF_D5" +Ne 119 "/FPGA_Spartan6/NF_D5" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/Non_volatile_memories/NF_D2" +Ne 209 "/Non_volatile_memories/NF_D2" Po 590 -3346 $EndPAD $PAD @@ -1782,21 +1812,21 @@ $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/NF_WE_N" +Ne 215 "/Non_volatile_memories/NF_WE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 216 "/Non_volatile_memories/NF_CS1_N" +Ne 116 "/FPGA_Spartan6/NF_CS1_N" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 221 "/Non_volatile_memories/SD_DAT3" +Ne 205 "/FPGA_Spartan6/SD_DAT3" Po 2165 -3346 $EndPAD $PAD @@ -1817,7 +1847,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 181 "/FPGA_Spartan6/R_M1_A8" +Ne 176 "/FPGA_Spartan6/R_M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1831,21 +1861,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 182 "/FPGA_Spartan6/R_M1_A9" +Ne 177 "/FPGA_Spartan6/R_M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/FPGA_Spartan6/R_M0_A12" +Ne 131 "/FPGA_Spartan6/R_M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 148 "/FPGA_Spartan6/R_M0_CKE" +Ne 143 "/FPGA_Spartan6/R_M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1873,42 +1903,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXD3" +Ne 47 "/Ethernet_Phy/ETH_RXD3" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_TXC" +Ne 58 "/FPGA_Spartan6/ETH_TXC" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_RXC" +Ne 57 "/FPGA_Spartan6/ETH_RXC" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_TXD0" +Ne 59 "/FPGA_Spartan6/ETH_TXD0" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_MDC" +Ne 42 "/Ethernet_Phy/ETH_MDC" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/NF_D6" +Ne 212 "/Non_volatile_memories/NF_D6" Po -196 -2952 $EndPAD $PAD @@ -1936,7 +1966,7 @@ $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_CLE" +Ne 115 "/FPGA_Spartan6/NF_CLE" Po 1377 -2952 $EndPAD $PAD @@ -1950,7 +1980,7 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 211 "/FPGA_Spartan6/SD_CMD" +Ne 217 "/Non_volatile_memories/SD_CMD" Po 2165 -2952 $EndPAD $PAD @@ -1978,21 +2008,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 186 "/FPGA_Spartan6/R_M1_CKE" +Ne 181 "/FPGA_Spartan6/R_M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 175 "/FPGA_Spartan6/R_M1_A12" +Ne 170 "/FPGA_Spartan6/R_M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/FPGA_Spartan6/R_M0_A9" +Ne 139 "/FPGA_Spartan6/R_M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -2006,7 +2036,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/FPGA_Spartan6/R_M0_A8" +Ne 138 "/FPGA_Spartan6/R_M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -2097,7 +2127,7 @@ $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 210 "/FPGA_Spartan6/SD_CLK" +Ne 216 "/Non_volatile_memories/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -2125,7 +2155,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 180 "/FPGA_Spartan6/R_M1_A7" +Ne 175 "/FPGA_Spartan6/R_M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -2139,7 +2169,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 176 "/FPGA_Spartan6/R_M1_A2" +Ne 171 "/FPGA_Spartan6/R_M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -2153,14 +2183,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "/FPGA_Spartan6/R_M0_WE#" +Ne 165 "/FPGA_Spartan6/R_M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/FPGA_Spartan6/R_M0_A4" +Ne 134 "/FPGA_Spartan6/R_M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -2272,7 +2302,7 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 174 "/FPGA_Spartan6/R_M1_A11" +Ne 169 "/FPGA_Spartan6/R_M1_A11" Po 2952 -2165 $EndPAD $PAD @@ -2286,21 +2316,21 @@ $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "/FPGA_Spartan6/R_M1_A0" +Ne 166 "/FPGA_Spartan6/R_M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 172 "/FPGA_Spartan6/R_M1_A1" +Ne 167 "/FPGA_Spartan6/R_M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 146 "/FPGA_Spartan6/R_M0_BA1" +Ne 141 "/FPGA_Spartan6/R_M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -2314,14 +2344,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 145 "/FPGA_Spartan6/R_M0_BA0" +Ne 140 "/FPGA_Spartan6/R_M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/FPGA_Spartan6/R_M0_A10" +Ne 129 "/FPGA_Spartan6/R_M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -2426,14 +2456,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 173 "/FPGA_Spartan6/R_M1_A10" +Ne 168 "/FPGA_Spartan6/R_M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 177 "/FPGA_Spartan6/R_M1_A3" +Ne 172 "/FPGA_Spartan6/R_M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2454,42 +2484,42 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/FPGA_Spartan6/R_M0_A1" +Ne 128 "/FPGA_Spartan6/R_M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/FPGA_Spartan6/R_M0_A0" +Ne 127 "/FPGA_Spartan6/R_M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_CLK#" +Ne 9 "/DDR_Banks/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_CLK" +Ne 8 "/DDR_Banks/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/FPGA_Spartan6/R_M0_A2" +Ne 132 "/FPGA_Spartan6/R_M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/FPGA_Spartan6/R_M0_A7" +Ne 137 "/FPGA_Spartan6/R_M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -2559,7 +2589,7 @@ $PAD Sh "H16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 187 "/FPGA_Spartan6/R_M1_CS#" +Ne 182 "/FPGA_Spartan6/R_M1_CS#" Po 1771 -1377 $EndPAD $PAD @@ -2580,35 +2610,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 209 "/FPGA_Spartan6/R_M1_WE#" +Ne 204 "/FPGA_Spartan6/R_M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_CLK" +Ne 100 "/FPGA_Spartan6/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 206 "/FPGA_Spartan6/R_M1_RAS#" +Ne 201 "/FPGA_Spartan6/R_M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 185 "/FPGA_Spartan6/R_M1_CAS#" +Ne 180 "/FPGA_Spartan6/R_M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "/FPGA_Spartan6/R_M0_DQ5" +Ne 155 "/FPGA_Spartan6/R_M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -2622,14 +2652,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 159 "/FPGA_Spartan6/R_M0_DQ4" +Ne 154 "/FPGA_Spartan6/R_M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/FPGA_Spartan6/R_M0_A6" +Ne 136 "/FPGA_Spartan6/R_M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2720,7 +2750,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 183 "/FPGA_Spartan6/R_M1_BA0" +Ne 178 "/FPGA_Spartan6/R_M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2734,14 +2764,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_CLK#" +Ne 26 "/DDR_Banks/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 198 "/FPGA_Spartan6/R_M1_DQ4" +Ne 193 "/FPGA_Spartan6/R_M1_DQ4" Po 3346 -983 $EndPAD $PAD @@ -2755,49 +2785,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 199 "/FPGA_Spartan6/R_M1_DQ5" +Ne 194 "/FPGA_Spartan6/R_M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 162 "/FPGA_Spartan6/R_M0_DQ7" +Ne 157 "/FPGA_Spartan6/R_M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 161 "/FPGA_Spartan6/R_M0_DQ6" +Ne 156 "/FPGA_Spartan6/R_M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/FPGA_Spartan6/R_M0_A5" +Ne 135 "/FPGA_Spartan6/R_M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 147 "/FPGA_Spartan6/R_M0_CAS#" +Ne 142 "/FPGA_Spartan6/R_M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "/FPGA_Spartan6/R_M0_RAS#" +Ne 162 "/FPGA_Spartan6/R_M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/FPGA_Spartan6/R_M0_A3" +Ne 133 "/FPGA_Spartan6/R_M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2874,7 +2904,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 184 "/FPGA_Spartan6/R_M1_BA1" +Ne 179 "/FPGA_Spartan6/R_M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2888,28 +2918,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 179 "/FPGA_Spartan6/R_M1_A6" +Ne 174 "/FPGA_Spartan6/R_M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 178 "/FPGA_Spartan6/R_M1_A5" +Ne 173 "/FPGA_Spartan6/R_M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 200 "/FPGA_Spartan6/R_M1_DQ6" +Ne 195 "/FPGA_Spartan6/R_M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 201 "/FPGA_Spartan6/R_M1_DQ7" +Ne 196 "/FPGA_Spartan6/R_M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2930,14 +2960,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "/FPGA_Spartan6/R_M0_LDQS" +Ne 161 "/FPGA_Spartan6/R_M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "/FPGA_Spartan6/R_M0_LDM" +Ne 160 "/FPGA_Spartan6/R_M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -3042,14 +3072,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 204 "/FPGA_Spartan6/R_M1_LDM" +Ne 199 "/FPGA_Spartan6/R_M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 205 "/FPGA_Spartan6/R_M1_LDQS" +Ne 200 "/FPGA_Spartan6/R_M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -3070,21 +3100,21 @@ $PAD Sh "M1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 158 "/FPGA_Spartan6/R_M0_DQ3" +Ne 153 "/FPGA_Spartan6/R_M0_DQ3" Po -4133 196 $EndPAD $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 157 "/FPGA_Spartan6/R_M0_DQ2" +Ne 152 "/FPGA_Spartan6/R_M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "/FPGA_Spartan6/R_M0_UDM" +Ne 163 "/FPGA_Spartan6/R_M0_UDM" Po -3346 196 $EndPAD $PAD @@ -3189,7 +3219,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 215 "/FPGA_Spartan6/USBA_VM" +Ne 222 "/USB/USBA_VM" Po 2558 196 $EndPAD $PAD @@ -3203,28 +3233,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 207 "/FPGA_Spartan6/R_M1_UDM" +Ne 202 "/FPGA_Spartan6/R_M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 196 "/FPGA_Spartan6/R_M1_DQ2" +Ne 191 "/FPGA_Spartan6/R_M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 197 "/FPGA_Spartan6/R_M1_DQ3" +Ne 192 "/FPGA_Spartan6/R_M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 150 "/FPGA_Spartan6/R_M0_DQ1" +Ne 145 "/FPGA_Spartan6/R_M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -3238,7 +3268,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 149 "/FPGA_Spartan6/R_M0_DQ0" +Ne 144 "/FPGA_Spartan6/R_M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -3329,7 +3359,7 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 214 "/FPGA_Spartan6/USBA_RCV" +Ne 221 "/USB/USBA_RCV" Po 1771 590 $EndPAD $PAD @@ -3357,7 +3387,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 188 "/FPGA_Spartan6/R_M1_DQ0" +Ne 183 "/FPGA_Spartan6/R_M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -3371,21 +3401,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 189 "/FPGA_Spartan6/R_M1_DQ1" +Ne 184 "/FPGA_Spartan6/R_M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "/FPGA_Spartan6/R_M0_DQ9" +Ne 159 "/FPGA_Spartan6/R_M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 163 "/FPGA_Spartan6/R_M0_DQ8" +Ne 158 "/FPGA_Spartan6/R_M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3497,7 +3527,7 @@ $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 213 "/FPGA_Spartan6/USBA_OE_N" +Ne 206 "/FPGA_Spartan6/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -3518,21 +3548,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 202 "/FPGA_Spartan6/R_M1_DQ8" +Ne 197 "/FPGA_Spartan6/R_M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 203 "/FPGA_Spartan6/R_M1_DQ9" +Ne 198 "/FPGA_Spartan6/R_M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 152 "/FPGA_Spartan6/R_M0_DQ11" +Ne 147 "/FPGA_Spartan6/R_M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3546,7 +3576,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "/FPGA_Spartan6/R_M0_DQ10" +Ne 146 "/FPGA_Spartan6/R_M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3658,14 +3688,14 @@ $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 222 "/USB/USBA_SPD" +Ne 207 "/FPGA_Spartan6/USBA_SPD" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 190 "/FPGA_Spartan6/R_M1_DQ10" +Ne 185 "/FPGA_Spartan6/R_M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3679,7 +3709,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 191 "/FPGA_Spartan6/R_M1_DQ11" +Ne 186 "/FPGA_Spartan6/R_M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3693,7 +3723,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "/FPGA_Spartan6/R_M0_UDQS" +Ne 164 "/FPGA_Spartan6/R_M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3714,7 +3744,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/PROG_CSO" +Ne 122 "/FPGA_Spartan6/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -3742,7 +3772,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -983 1771 $EndPAD $PAD @@ -3770,7 +3800,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po 590 1771 $EndPAD $PAD @@ -3826,7 +3856,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 208 "/FPGA_Spartan6/R_M1_UDQS" +Ne 203 "/FPGA_Spartan6/R_M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3840,7 +3870,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 154 "/FPGA_Spartan6/R_M0_DQ13" +Ne 149 "/FPGA_Spartan6/R_M0_DQ13" Po -4133 2165 $EndPAD $PAD @@ -3854,7 +3884,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 153 "/FPGA_Spartan6/R_M0_DQ12" +Ne 148 "/FPGA_Spartan6/R_M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3924,14 +3954,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/PROG_MISO3" +Ne 126 "/FPGA_Spartan6/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/PROG_MISO2" +Ne 125 "/FPGA_Spartan6/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -3973,7 +4003,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 192 "/FPGA_Spartan6/R_M1_DQ12" +Ne 187 "/FPGA_Spartan6/R_M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -3987,21 +4017,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 193 "/FPGA_Spartan6/R_M1_DQ13" +Ne 188 "/FPGA_Spartan6/R_M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "/FPGA_Spartan6/R_M0_DQ15" +Ne 151 "/FPGA_Spartan6/R_M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 155 "/FPGA_Spartan6/R_M0_DQ14" +Ne 150 "/FPGA_Spartan6/R_M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -4043,7 +4073,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -1377 2558 $EndPAD $PAD @@ -4071,7 +4101,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po 196 2558 $EndPAD $PAD @@ -4099,7 +4129,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po 1771 2558 $EndPAD $PAD @@ -4134,14 +4164,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 194 "/FPGA_Spartan6/R_M1_DQ14" +Ne 189 "/FPGA_Spartan6/R_M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 195 "/FPGA_Spartan6/R_M1_DQ15" +Ne 190 "/FPGA_Spartan6/R_M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -4176,7 +4206,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -2558 2952 $EndPAD $PAD @@ -4470,7 +4500,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -3346 3739 $EndPAD $PAD @@ -4498,7 +4528,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -1771 3739 $EndPAD $PAD @@ -4526,7 +4556,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -196 3739 $EndPAD $PAD @@ -4554,7 +4584,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po 1377 3739 $EndPAD $PAD @@ -4582,21 +4612,21 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po 2952 3739 $EndPAD $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/PROG_MISO1" +Ne 124 "/FPGA_Spartan6/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/PROG_CCLK" +Ne 121 "/FPGA_Spartan6/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -4743,7 +4773,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/PROG_MISO0" +Ne 123 "/FPGA_Spartan6/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -4926,14 +4956,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 168 "/FPGA_Spartan6/R_M0_UDM" +Ne 163 "/FPGA_Spartan6/R_M0_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 92 "/FPGA_Spartan6/M0_UDM" +Ne 87 "/FPGA_Spartan6/M0_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -4954,7 +4984,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 169 "/FPGA_Spartan6/R_M0_UDQS" +Ne 164 "/FPGA_Spartan6/R_M0_UDQS" Po -176 0 $EndPAD $PAD @@ -4982,14 +5012,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 148 "/FPGA_Spartan6/R_M0_CKE" +Ne 143 "/FPGA_Spartan6/R_M0_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 77 "/FPGA_Spartan6/M0_CKE" +Ne 7 "/DDR_Banks/M0_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5010,14 +5040,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 12 "/DDR_Banks/M0_CLK" +Ne 8 "/DDR_Banks/M0_CLK" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 78 "/FPGA_Spartan6/M0_CLK#" +Ne 9 "/DDR_Banks/M0_CLK#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5036,56 +5066,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 132 "/FPGA_Spartan6/R_M0_A0" +Ne 127 "/FPGA_Spartan6/R_M0_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 133 "/FPGA_Spartan6/R_M0_A1" +Ne 128 "/FPGA_Spartan6/R_M0_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 137 "/FPGA_Spartan6/R_M0_A2" +Ne 132 "/FPGA_Spartan6/R_M0_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 138 "/FPGA_Spartan6/R_M0_A3" +Ne 133 "/FPGA_Spartan6/R_M0_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 70 "/FPGA_Spartan6/M0_A3" +Ne 67 "/FPGA_Spartan6/M0_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 8 "/DDR_Banks/M0_A2" +Ne 66 "/FPGA_Spartan6/M0_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 68 "/FPGA_Spartan6/M0_A1" +Ne 62 "/FPGA_Spartan6/M0_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 67 "/FPGA_Spartan6/M0_A0" +Ne 6 "/DDR_Banks/M0_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5104,56 +5134,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 167 "/FPGA_Spartan6/R_M0_RAS#" +Ne 162 "/FPGA_Spartan6/R_M0_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 145 "/FPGA_Spartan6/R_M0_BA0" +Ne 140 "/FPGA_Spartan6/R_M0_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 146 "/FPGA_Spartan6/R_M0_BA1" +Ne 141 "/FPGA_Spartan6/R_M0_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 134 "/FPGA_Spartan6/R_M0_A10" +Ne 129 "/FPGA_Spartan6/R_M0_A10" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 69 "/FPGA_Spartan6/M0_A10" +Ne 63 "/FPGA_Spartan6/M0_A10" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 76 "/FPGA_Spartan6/M0_BA1" +Ne 75 "/FPGA_Spartan6/M0_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 75 "/FPGA_Spartan6/M0_BA0" +Ne 74 "/FPGA_Spartan6/M0_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 91 "/FPGA_Spartan6/M0_RAS#" +Ne 18 "/DDR_Banks/M0_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5172,56 +5202,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 166 "/FPGA_Spartan6/R_M0_LDQS" +Ne 161 "/FPGA_Spartan6/R_M0_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 165 "/FPGA_Spartan6/R_M0_LDM" +Ne 160 "/FPGA_Spartan6/R_M0_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 170 "/FPGA_Spartan6/R_M0_WE#" +Ne 165 "/FPGA_Spartan6/R_M0_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 147 "/FPGA_Spartan6/R_M0_CAS#" +Ne 142 "/FPGA_Spartan6/R_M0_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 11 "/DDR_Banks/M0_CAS#" +Ne 76 "/FPGA_Spartan6/M0_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 93 "/FPGA_Spartan6/M0_WE#" +Ne 88 "/FPGA_Spartan6/M0_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 90 "/FPGA_Spartan6/M0_LDM" +Ne 16 "/DDR_Banks/M0_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 18 "/DDR_Banks/M0_LDQS" +Ne 17 "/DDR_Banks/M0_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5240,56 +5270,56 @@ $PAD Sh "1" R 118 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/FPGA_Spartan6/R_M0_A7" +Ne 137 "/FPGA_Spartan6/R_M0_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 141 "/FPGA_Spartan6/R_M0_A6" +Ne 136 "/FPGA_Spartan6/R_M0_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 140 "/FPGA_Spartan6/R_M0_A5" +Ne 135 "/FPGA_Spartan6/R_M0_A5" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 139 "/FPGA_Spartan6/R_M0_A4" +Ne 134 "/FPGA_Spartan6/R_M0_A4" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 71 "/FPGA_Spartan6/M0_A4" +Ne 68 "/FPGA_Spartan6/M0_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 72 "/FPGA_Spartan6/M0_A5" +Ne 69 "/FPGA_Spartan6/M0_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 9 "/DDR_Banks/M0_A6" +Ne 70 "/FPGA_Spartan6/M0_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 73 "/FPGA_Spartan6/M0_A7" +Ne 71 "/FPGA_Spartan6/M0_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5308,56 +5338,56 @@ $PAD Sh "1" R 118 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 136 "/FPGA_Spartan6/R_M0_A12" +Ne 131 "/FPGA_Spartan6/R_M0_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 135 "/FPGA_Spartan6/R_M0_A11" +Ne 130 "/FPGA_Spartan6/R_M0_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/FPGA_Spartan6/R_M0_A9" +Ne 139 "/FPGA_Spartan6/R_M0_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/FPGA_Spartan6/R_M0_A8" +Ne 138 "/FPGA_Spartan6/R_M0_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 74 "/FPGA_Spartan6/M0_A8" +Ne 72 "/FPGA_Spartan6/M0_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 10 "/DDR_Banks/M0_A9" +Ne 73 "/FPGA_Spartan6/M0_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 6 "/DDR_Banks/M0_A11" +Ne 64 "/FPGA_Spartan6/M0_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 7 "/DDR_Banks/M0_A12" +Ne 65 "/FPGA_Spartan6/M0_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5376,56 +5406,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 159 "/FPGA_Spartan6/R_M0_DQ4" +Ne 154 "/FPGA_Spartan6/R_M0_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 160 "/FPGA_Spartan6/R_M0_DQ5" +Ne 155 "/FPGA_Spartan6/R_M0_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 161 "/FPGA_Spartan6/R_M0_DQ6" +Ne 156 "/FPGA_Spartan6/R_M0_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "/FPGA_Spartan6/R_M0_DQ7" +Ne 157 "/FPGA_Spartan6/R_M0_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 88 "/FPGA_Spartan6/M0_DQ7" +Ne 84 "/FPGA_Spartan6/M0_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 16 "/DDR_Banks/M0_DQ6" +Ne 83 "/FPGA_Spartan6/M0_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 87 "/FPGA_Spartan6/M0_DQ5" +Ne 82 "/FPGA_Spartan6/M0_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 86 "/FPGA_Spartan6/M0_DQ4" +Ne 81 "/FPGA_Spartan6/M0_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5444,56 +5474,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 149 "/FPGA_Spartan6/R_M0_DQ0" +Ne 144 "/FPGA_Spartan6/R_M0_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 150 "/FPGA_Spartan6/R_M0_DQ1" +Ne 145 "/FPGA_Spartan6/R_M0_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 157 "/FPGA_Spartan6/R_M0_DQ2" +Ne 152 "/FPGA_Spartan6/R_M0_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 158 "/FPGA_Spartan6/R_M0_DQ3" +Ne 153 "/FPGA_Spartan6/R_M0_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 15 "/DDR_Banks/M0_DQ3" +Ne 80 "/FPGA_Spartan6/M0_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 85 "/FPGA_Spartan6/M0_DQ2" +Ne 79 "/FPGA_Spartan6/M0_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 80 "/FPGA_Spartan6/M0_DQ1" +Ne 10 "/DDR_Banks/M0_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 79 "/FPGA_Spartan6/M0_DQ0" +Ne 77 "/FPGA_Spartan6/M0_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5512,56 +5542,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 163 "/FPGA_Spartan6/R_M0_DQ8" +Ne 158 "/FPGA_Spartan6/R_M0_DQ8" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 164 "/FPGA_Spartan6/R_M0_DQ9" +Ne 159 "/FPGA_Spartan6/R_M0_DQ9" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 151 "/FPGA_Spartan6/R_M0_DQ10" +Ne 146 "/FPGA_Spartan6/R_M0_DQ10" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 152 "/FPGA_Spartan6/R_M0_DQ11" +Ne 147 "/FPGA_Spartan6/R_M0_DQ11" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 13 "/DDR_Banks/M0_DQ11" +Ne 12 "/DDR_Banks/M0_DQ11" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 81 "/FPGA_Spartan6/M0_DQ10" +Ne 11 "/DDR_Banks/M0_DQ10" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 17 "/DDR_Banks/M0_DQ9" +Ne 86 "/FPGA_Spartan6/M0_DQ9" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 89 "/FPGA_Spartan6/M0_DQ8" +Ne 85 "/FPGA_Spartan6/M0_DQ8" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5580,56 +5610,56 @@ $PAD Sh "1" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 153 "/FPGA_Spartan6/R_M0_DQ12" +Ne 148 "/FPGA_Spartan6/R_M0_DQ12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 154 "/FPGA_Spartan6/R_M0_DQ13" +Ne 149 "/FPGA_Spartan6/R_M0_DQ13" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 155 "/FPGA_Spartan6/R_M0_DQ14" +Ne 150 "/FPGA_Spartan6/R_M0_DQ14" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 156 "/FPGA_Spartan6/R_M0_DQ15" +Ne 151 "/FPGA_Spartan6/R_M0_DQ15" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 84 "/FPGA_Spartan6/M0_DQ15" +Ne 78 "/FPGA_Spartan6/M0_DQ15" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 14 "/DDR_Banks/M0_DQ14" +Ne 15 "/DDR_Banks/M0_DQ14" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 83 "/FPGA_Spartan6/M0_DQ13" +Ne 14 "/DDR_Banks/M0_DQ13" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 82 "/FPGA_Spartan6/M0_DQ12" +Ne 13 "/DDR_Banks/M0_DQ12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -5833,7 +5863,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 208 "/FPGA_Spartan6/R_M1_UDQS" +Ne 203 "/FPGA_Spartan6/R_M1_UDQS" Po -176 0 $EndPAD $PAD @@ -5861,14 +5891,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 187 "/FPGA_Spartan6/R_M1_CS#" +Ne 182 "/FPGA_Spartan6/R_M1_CS#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 101 "/FPGA_Spartan6/M1_CS#" +Ne 27 "/DDR_Banks/M1_CS#" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5889,14 +5919,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 186 "/FPGA_Spartan6/R_M1_CKE" +Ne 181 "/FPGA_Spartan6/R_M1_CKE" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 29 "/DDR_Banks/M1_CKE" +Ne 99 "/FPGA_Spartan6/M1_CKE" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5917,14 +5947,14 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 207 "/FPGA_Spartan6/R_M1_UDM" +Ne 202 "/FPGA_Spartan6/R_M1_UDM" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 39 "/DDR_Banks/M1_UDM" +Ne 113 "/FPGA_Spartan6/M1_UDM" Po 176 0 $EndPAD $EndMODULE 0402 @@ -5943,56 +5973,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 195 "/FPGA_Spartan6/R_M1_DQ15" +Ne 190 "/FPGA_Spartan6/R_M1_DQ15" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 194 "/FPGA_Spartan6/R_M1_DQ14" +Ne 189 "/FPGA_Spartan6/R_M1_DQ14" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 193 "/FPGA_Spartan6/R_M1_DQ13" +Ne 188 "/FPGA_Spartan6/R_M1_DQ13" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 192 "/FPGA_Spartan6/R_M1_DQ12" +Ne 187 "/FPGA_Spartan6/R_M1_DQ12" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 105 "/FPGA_Spartan6/M1_DQ12" +Ne 31 "/DDR_Banks/M1_DQ12" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/DDR_Banks/M1_DQ13" +Ne 32 "/DDR_Banks/M1_DQ13" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 106 "/FPGA_Spartan6/M1_DQ14" +Ne 102 "/FPGA_Spartan6/M1_DQ14" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 107 "/FPGA_Spartan6/M1_DQ15" +Ne 103 "/FPGA_Spartan6/M1_DQ15" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6011,56 +6041,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 191 "/FPGA_Spartan6/R_M1_DQ11" +Ne 186 "/FPGA_Spartan6/R_M1_DQ11" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 190 "/FPGA_Spartan6/R_M1_DQ10" +Ne 185 "/FPGA_Spartan6/R_M1_DQ10" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 203 "/FPGA_Spartan6/R_M1_DQ9" +Ne 198 "/FPGA_Spartan6/R_M1_DQ9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 202 "/FPGA_Spartan6/R_M1_DQ8" +Ne 197 "/FPGA_Spartan6/R_M1_DQ8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 110 "/FPGA_Spartan6/M1_DQ8" +Ne 109 "/FPGA_Spartan6/M1_DQ8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 111 "/FPGA_Spartan6/M1_DQ9" +Ne 110 "/FPGA_Spartan6/M1_DQ9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 103 "/FPGA_Spartan6/M1_DQ10" +Ne 29 "/DDR_Banks/M1_DQ10" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 104 "/FPGA_Spartan6/M1_DQ11" +Ne 30 "/DDR_Banks/M1_DQ11" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6081,14 +6111,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/DDR_Banks/M1_CLK#" +Ne 26 "/DDR_Banks/M1_CLK#" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 30 "/DDR_Banks/M1_CLK" +Ne 100 "/FPGA_Spartan6/M1_CLK" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6107,56 +6137,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 175 "/FPGA_Spartan6/R_M1_A12" +Ne 170 "/FPGA_Spartan6/R_M1_A12" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 174 "/FPGA_Spartan6/R_M1_A11" +Ne 169 "/FPGA_Spartan6/R_M1_A11" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 182 "/FPGA_Spartan6/R_M1_A9" +Ne 177 "/FPGA_Spartan6/R_M1_A9" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 181 "/FPGA_Spartan6/R_M1_A8" +Ne 176 "/FPGA_Spartan6/R_M1_A8" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 24 "/DDR_Banks/M1_A8" +Ne 23 "/DDR_Banks/M1_A8" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 25 "/DDR_Banks/M1_A9" +Ne 97 "/FPGA_Spartan6/M1_A9" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 96 "/FPGA_Spartan6/M1_A11" +Ne 91 "/FPGA_Spartan6/M1_A11" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 97 "/FPGA_Spartan6/M1_A12" +Ne 21 "/DDR_Banks/M1_A12" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6175,21 +6205,21 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 180 "/FPGA_Spartan6/R_M1_A7" +Ne 175 "/FPGA_Spartan6/R_M1_A7" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 179 "/FPGA_Spartan6/R_M1_A6" +Ne 174 "/FPGA_Spartan6/R_M1_A6" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 178 "/FPGA_Spartan6/R_M1_A5" +Ne 173 "/FPGA_Spartan6/R_M1_A5" Po 98 -177 $EndPAD $PAD @@ -6203,28 +6233,28 @@ $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 22 "/DDR_Banks/M1_A4" +Ne 94 "/FPGA_Spartan6/M1_A4" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 99 "/FPGA_Spartan6/M1_A5" +Ne 95 "/FPGA_Spartan6/M1_A5" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 100 "/FPGA_Spartan6/M1_A6" +Ne 22 "/DDR_Banks/M1_A6" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 23 "/DDR_Banks/M1_A7" +Ne 96 "/FPGA_Spartan6/M1_A7" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6243,56 +6273,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 188 "/FPGA_Spartan6/R_M1_DQ0" +Ne 183 "/FPGA_Spartan6/R_M1_DQ0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 189 "/FPGA_Spartan6/R_M1_DQ1" +Ne 184 "/FPGA_Spartan6/R_M1_DQ1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 196 "/FPGA_Spartan6/R_M1_DQ2" +Ne 191 "/FPGA_Spartan6/R_M1_DQ2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 197 "/FPGA_Spartan6/R_M1_DQ3" +Ne 192 "/FPGA_Spartan6/R_M1_DQ3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/DDR_Banks/M1_DQ3" +Ne 33 "/DDR_Banks/M1_DQ3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/DDR_Banks/M1_DQ2" +Ne 104 "/FPGA_Spartan6/M1_DQ2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 102 "/FPGA_Spartan6/M1_DQ1" +Ne 28 "/DDR_Banks/M1_DQ1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 32 "/DDR_Banks/M1_DQ0" +Ne 101 "/FPGA_Spartan6/M1_DQ0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6311,56 +6341,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 205 "/FPGA_Spartan6/R_M1_LDQS" +Ne 200 "/FPGA_Spartan6/R_M1_LDQS" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 204 "/FPGA_Spartan6/R_M1_LDM" +Ne 199 "/FPGA_Spartan6/R_M1_LDM" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 209 "/FPGA_Spartan6/R_M1_WE#" +Ne 204 "/FPGA_Spartan6/R_M1_WE#" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 185 "/FPGA_Spartan6/R_M1_CAS#" +Ne 180 "/FPGA_Spartan6/R_M1_CAS#" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 28 "/DDR_Banks/M1_CAS#" +Ne 98 "/FPGA_Spartan6/M1_CAS#" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 40 "/DDR_Banks/M1_WE#" +Ne 35 "/DDR_Banks/M1_WE#" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 112 "/FPGA_Spartan6/M1_LDM" +Ne 111 "/FPGA_Spartan6/M1_LDM" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 38 "/DDR_Banks/M1_LDQS" +Ne 34 "/DDR_Banks/M1_LDQS" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6379,56 +6409,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 198 "/FPGA_Spartan6/R_M1_DQ4" +Ne 193 "/FPGA_Spartan6/R_M1_DQ4" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 199 "/FPGA_Spartan6/R_M1_DQ5" +Ne 194 "/FPGA_Spartan6/R_M1_DQ5" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 200 "/FPGA_Spartan6/R_M1_DQ6" +Ne 195 "/FPGA_Spartan6/R_M1_DQ6" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 201 "/FPGA_Spartan6/R_M1_DQ7" +Ne 196 "/FPGA_Spartan6/R_M1_DQ7" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 37 "/DDR_Banks/M1_DQ7" +Ne 108 "/FPGA_Spartan6/M1_DQ7" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 36 "/DDR_Banks/M1_DQ6" +Ne 107 "/FPGA_Spartan6/M1_DQ6" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 109 "/FPGA_Spartan6/M1_DQ5" +Ne 106 "/FPGA_Spartan6/M1_DQ5" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 108 "/FPGA_Spartan6/M1_DQ4" +Ne 105 "/FPGA_Spartan6/M1_DQ4" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6447,28 +6477,28 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 206 "/FPGA_Spartan6/R_M1_RAS#" +Ne 201 "/FPGA_Spartan6/R_M1_RAS#" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 183 "/FPGA_Spartan6/R_M1_BA0" +Ne 178 "/FPGA_Spartan6/R_M1_BA0" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 184 "/FPGA_Spartan6/R_M1_BA1" +Ne 179 "/FPGA_Spartan6/R_M1_BA1" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 173 "/FPGA_Spartan6/R_M1_A10" +Ne 168 "/FPGA_Spartan6/R_M1_A10" Po 295 -177 $EndPAD $PAD @@ -6482,21 +6512,21 @@ $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 27 "/DDR_Banks/M1_BA1" +Ne 25 "/DDR_Banks/M1_BA1" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 26 "/DDR_Banks/M1_BA0" +Ne 24 "/DDR_Banks/M1_BA0" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 113 "/FPGA_Spartan6/M1_RAS#" +Ne 112 "/FPGA_Spartan6/M1_RAS#" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6515,56 +6545,56 @@ $PAD Sh "1" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 171 "/FPGA_Spartan6/R_M1_A0" +Ne 166 "/FPGA_Spartan6/R_M1_A0" Po -295 -177 $EndPAD $PAD Sh "2" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 172 "/FPGA_Spartan6/R_M1_A1" +Ne 167 "/FPGA_Spartan6/R_M1_A1" Po -98 -177 $EndPAD $PAD Sh "3" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 176 "/FPGA_Spartan6/R_M1_A2" +Ne 171 "/FPGA_Spartan6/R_M1_A2" Po 98 -177 $EndPAD $PAD Sh "4" R 118 157 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 177 "/FPGA_Spartan6/R_M1_A3" +Ne 172 "/FPGA_Spartan6/R_M1_A3" Po 295 -177 $EndPAD $PAD Sh "5" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 98 "/FPGA_Spartan6/M1_A3" +Ne 93 "/FPGA_Spartan6/M1_A3" Po 295 177 $EndPAD $PAD Sh "6" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 21 "/DDR_Banks/M1_A2" +Ne 92 "/FPGA_Spartan6/M1_A2" Po 98 177 $EndPAD $PAD Sh "7" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 95 "/FPGA_Spartan6/M1_A1" +Ne 90 "/FPGA_Spartan6/M1_A1" Po -98 177 $EndPAD $PAD Sh "8" R 118 157 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 94 "/FPGA_Spartan6/M1_A0" +Ne 89 "/FPGA_Spartan6/M1_A0" Po -295 177 $EndPAD $EndMODULE R_PACK4-0402 @@ -6613,14 +6643,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_A1.8V" +Ne 36 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 49 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6648,7 +6678,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_A1.8V" +Ne 36 "/Ethernet_Phy/ETH_A1.8V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6676,7 +6706,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/Ethernet_Phy/ETH_A3.3V" +Ne 37 "/Ethernet_Phy/ETH_A3.3V" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6843,49 +6873,49 @@ $PAD Sh "8" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -750 -1050 $EndPAD $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/PROG_CSO" +Ne 122 "/FPGA_Spartan6/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/FPGA_Spartan6/PROG_MISO3" +Ne 126 "/FPGA_Spartan6/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/PROG_CCLK" +Ne 121 "/FPGA_Spartan6/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/PROG_MISO0" +Ne 123 "/FPGA_Spartan6/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/PROG_MISO1" +Ne 124 "/FPGA_Spartan6/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/PROG_MISO2" +Ne 125 "/FPGA_Spartan6/PROG_MISO2" Po 250 1050 $EndPAD $PAD @@ -7087,7 +7117,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -570 0 $EndPAD $PAD @@ -7283,7 +7313,7 @@ $PAD Sh "1" R 275 510 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -373 0 $EndPAD $PAD @@ -7563,7 +7593,7 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7647,7 +7677,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7731,7 +7761,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7787,7 +7817,7 @@ $PAD Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 245 "VCCO2" +Ne 251 "VCCO2" Po -176 0 $EndPAD $PAD @@ -7886,7 +7916,7 @@ $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 244 "N-000433" +Ne 242 "N-000431" Po 255 1112 $EndPAD $PAD @@ -7935,7 +7965,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 235 "N-000418" +Ne 235 "N-000422" Po -570 0 $EndPAD $PAD @@ -8047,7 +8077,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 244 "N-000433" +Ne 242 "N-000431" Po -294 0 $EndPAD $PAD @@ -8103,7 +8133,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 236 "N-000420" +Ne 244 "N-000433" Po -176 0 $EndPAD $PAD @@ -8131,7 +8161,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 236 "N-000420" +Ne 244 "N-000433" Po -176 0 $EndPAD $PAD @@ -8187,7 +8217,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 235 "N-000418" +Ne 235 "N-000422" Po -294 0 $EndPAD $PAD @@ -8215,14 +8245,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 239 "N-000424" +Ne 240 "N-000429" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 240 "N-000425" +Ne 239 "N-000427" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8243,7 +8273,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 237 "N-000422" +Ne 237 "N-000425" Po -294 0 $EndPAD $PAD @@ -8836,56 +8866,56 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 240 "N-000425" +Ne 239 "N-000427" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 241 "N-000426" +Ne 238 "N-000426" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 242 "N-000427" +Ne 241 "N-000430" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 242 "N-000427" +Ne 241 "N-000430" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 238 "N-000423" +Ne 236 "N-000424" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 238 "N-000423" +Ne 236 "N-000424" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 238 "N-000423" +Ne 236 "N-000424" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 238 "N-000423" +Ne 236 "N-000424" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 @@ -8906,7 +8936,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 239 "N-000424" +Ne 240 "N-000429" Po -570 0 $EndPAD $PAD @@ -8962,7 +8992,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_A3.3V" +Ne 37 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD @@ -9074,7 +9104,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 242 "N-000427" +Ne 241 "N-000430" Po -294 0 $EndPAD $PAD @@ -9102,7 +9132,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 241 "N-000426" +Ne 238 "N-000426" Po -294 0 $EndPAD $PAD @@ -9242,7 +9272,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 41 "/Ethernet_Phy/ETH_A1.8V" +Ne 36 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD @@ -9270,7 +9300,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 42 "/Ethernet_Phy/ETH_A3.3V" +Ne 37 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD @@ -9298,7 +9328,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 49 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD @@ -9382,7 +9412,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 228 "N-000407" +Ne 232 "N-000404" Po -176 0 $EndPAD $PAD @@ -9410,7 +9440,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 238 "N-000423" +Ne 236 "N-000424" Po -176 0 $EndPAD $PAD @@ -9438,7 +9468,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 57 "/FPGA_Spartan6/ETH_MDIO" +Ne 55 "/FPGA_Spartan6/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -9466,7 +9496,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 227 "N-000398" +Ne 228 "N-000396" Po -176 0 $EndPAD $PAD @@ -9501,7 +9531,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 229 "N-000409" +Ne 234 "N-000406" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9529,7 +9559,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 233 "N-000413" +Ne 227 "N-000395" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9557,7 +9587,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 230 "N-000410" +Ne 233 "N-000405" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9585,7 +9615,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 232 "N-000412" +Ne 231 "N-000403" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9606,14 +9636,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 234 "N-000415" +Ne 230 "N-000402" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 46 "/Ethernet_Phy/ETH_LED0" +Ne 40 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9634,14 +9664,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 231 "N-000411" +Ne 229 "N-000397" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 47 "/Ethernet_Phy/ETH_LED1" +Ne 41 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 @@ -9662,7 +9692,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 228 "N-000407" +Ne 232 "N-000404" Po -176 0 $EndPAD $PAD @@ -9690,7 +9720,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 238 "N-000423" +Ne 236 "N-000424" Po -176 0 $EndPAD $PAD @@ -9726,7 +9756,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ0" +Ne 77 "/FPGA_Spartan6/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -9740,14 +9770,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 80 "/FPGA_Spartan6/M0_DQ1" +Ne 10 "/DDR_Banks/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ2" +Ne 79 "/FPGA_Spartan6/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -9761,14 +9791,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M0_DQ3" +Ne 80 "/FPGA_Spartan6/M0_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ4" +Ne 81 "/FPGA_Spartan6/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -9782,14 +9812,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_DQ5" +Ne 82 "/FPGA_Spartan6/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M0_DQ6" +Ne 83 "/FPGA_Spartan6/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -9803,7 +9833,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_DQ7" +Ne 84 "/FPGA_Spartan6/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -9824,7 +9854,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M0_LDQS" +Ne 17 "/DDR_Banks/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -9852,28 +9882,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M0_LDM" +Ne 16 "/DDR_Banks/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M0_WE#" +Ne 88 "/FPGA_Spartan6/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_CAS#" +Ne 76 "/FPGA_Spartan6/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M0_RAS#" +Ne 18 "/DDR_Banks/M0_RAS#" Po 1535 2176 $EndPAD $PAD @@ -9894,49 +9924,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_BA0" +Ne 74 "/FPGA_Spartan6/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_BA1" +Ne 75 "/FPGA_Spartan6/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_A10" +Ne 63 "/FPGA_Spartan6/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_A0" +Ne 6 "/DDR_Banks/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_A1" +Ne 62 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_A2" +Ne 66 "/FPGA_Spartan6/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_A3" +Ne 67 "/FPGA_Spartan6/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -9957,56 +9987,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_A4" +Ne 68 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_A5" +Ne 69 "/FPGA_Spartan6/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_A6" +Ne 70 "/FPGA_Spartan6/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_A7" +Ne 71 "/FPGA_Spartan6/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_A8" +Ne 72 "/FPGA_Spartan6/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_A9" +Ne 73 "/FPGA_Spartan6/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A11" +Ne 64 "/FPGA_Spartan6/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_A12" +Ne 65 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -10020,28 +10050,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_CLK#" +Ne 9 "/DDR_Banks/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_CKE" +Ne 7 "/DDR_Banks/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_CLK" +Ne 8 "/DDR_Banks/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M0_UDM" +Ne 87 "/FPGA_Spartan6/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -10090,7 +10120,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M0_DQ8" +Ne 85 "/FPGA_Spartan6/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10104,14 +10134,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M0_DQ9" +Ne 86 "/FPGA_Spartan6/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ10" +Ne 11 "/DDR_Banks/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -10125,14 +10155,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M0_DQ11" +Ne 12 "/DDR_Banks/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ12" +Ne 13 "/DDR_Banks/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10146,14 +10176,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ13" +Ne 14 "/DDR_Banks/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M0_DQ14" +Ne 15 "/DDR_Banks/M0_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10167,7 +10197,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ15" +Ne 78 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10203,7 +10233,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/DDR_Banks/M1_DQ0" +Ne 101 "/FPGA_Spartan6/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -10217,14 +10247,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ1" +Ne 28 "/DDR_Banks/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/DDR_Banks/M1_DQ2" +Ne 104 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD @@ -10238,14 +10268,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/DDR_Banks/M1_DQ3" +Ne 33 "/DDR_Banks/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ4" +Ne 105 "/FPGA_Spartan6/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -10259,14 +10289,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ5" +Ne 106 "/FPGA_Spartan6/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/DDR_Banks/M1_DQ6" +Ne 107 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -10280,7 +10310,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/DDR_Banks/M1_DQ7" +Ne 108 "/FPGA_Spartan6/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -10301,7 +10331,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/DDR_Banks/M1_LDQS" +Ne 34 "/DDR_Banks/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -10329,35 +10359,35 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_LDM" +Ne 111 "/FPGA_Spartan6/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/DDR_Banks/M1_WE#" +Ne 35 "/DDR_Banks/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_CAS#" +Ne 98 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_RAS#" +Ne 112 "/FPGA_Spartan6/M1_RAS#" Po 1535 2176 $EndPAD $PAD Sh "24" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_CS#" +Ne 27 "/DDR_Banks/M1_CS#" Po 1791 2176 $EndPAD $PAD @@ -10371,14 +10401,14 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_BA0" +Ne 24 "/DDR_Banks/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_BA1" +Ne 25 "/DDR_Banks/M1_BA1" Po 2558 2176 $EndPAD $PAD @@ -10392,28 +10422,28 @@ $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A0" +Ne 89 "/FPGA_Spartan6/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A1" +Ne 90 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_A2" +Ne 92 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_A3" +Ne 93 "/FPGA_Spartan6/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -10434,56 +10464,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_A4" +Ne 94 "/FPGA_Spartan6/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_A5" +Ne 95 "/FPGA_Spartan6/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_A6" +Ne 22 "/DDR_Banks/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_A7" +Ne 96 "/FPGA_Spartan6/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_A8" +Ne 23 "/DDR_Banks/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_A9" +Ne 97 "/FPGA_Spartan6/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_A11" +Ne 91 "/FPGA_Spartan6/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_A12" +Ne 21 "/DDR_Banks/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -10497,28 +10527,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/DDR_Banks/M1_CLK#" +Ne 26 "/DDR_Banks/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/DDR_Banks/M1_CKE" +Ne 99 "/FPGA_Spartan6/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/DDR_Banks/M1_CLK" +Ne 100 "/FPGA_Spartan6/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/DDR_Banks/M1_UDM" +Ne 113 "/FPGA_Spartan6/M1_UDM" Po 767 -2176 $EndPAD $PAD @@ -10567,7 +10597,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_DQ8" +Ne 109 "/FPGA_Spartan6/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -10581,14 +10611,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_DQ9" +Ne 110 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ10" +Ne 29 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -10602,14 +10632,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ11" +Ne 30 "/DDR_Banks/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ12" +Ne 31 "/DDR_Banks/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -10623,14 +10653,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/DDR_Banks/M1_DQ13" +Ne 32 "/DDR_Banks/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ14" +Ne 102 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -10644,7 +10674,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ15" +Ne 103 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -10687,14 +10717,14 @@ $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 222 "/USB/USBA_SPD" +Ne 207 "/FPGA_Spartan6/USBA_SPD" Po -511 -1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 214 "/FPGA_Spartan6/USBA_RCV" +Ne 221 "/USB/USBA_RCV" Po -255 -1112 $EndPAD $PAD @@ -10708,7 +10738,7 @@ $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 215 "/FPGA_Spartan6/USBA_VM" +Ne 222 "/USB/USBA_VM" Po 255 -1112 $EndPAD $PAD @@ -10736,21 +10766,21 @@ $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 213 "/FPGA_Spartan6/USBA_OE_N" +Ne 206 "/FPGA_Spartan6/USBA_OE_N" Po 511 1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 241 "N-000426" +Ne 238 "N-000426" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 242 "N-000427" +Ne 241 "N-000430" Po 0 1112 $EndPAD $PAD @@ -10791,35 +10821,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 228 "N-000407" +Ne 232 "N-000404" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 228 "N-000407" +Ne 232 "N-000404" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 228 "N-000407" +Ne 232 "N-000404" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 228 "N-000407" +Ne 232 "N-000404" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 229 "N-000409" +Ne 234 "N-000406" Po -1750 -2500 $EndPAD $PAD @@ -10840,14 +10870,14 @@ $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 230 "N-000410" +Ne 233 "N-000405" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 233 "N-000413" +Ne 227 "N-000395" Po -1250 -3500 $EndPAD $PAD @@ -10868,7 +10898,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 232 "N-000412" +Ne 231 "N-000403" Po 1750 -3500 $EndPAD $PAD @@ -10882,7 +10912,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 234 "N-000415" +Ne 230 "N-000402" Po -1150 -5400 $EndPAD $PAD @@ -10896,7 +10926,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 231 "N-000411" +Ne 229 "N-000397" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -10928,14 +10958,14 @@ $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 221 "/Non_volatile_memories/SD_DAT3" +Ne 205 "/FPGA_Spartan6/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 211 "/FPGA_Spartan6/SD_CMD" +Ne 217 "/Non_volatile_memories/SD_CMD" Po -433 0 $EndPAD $PAD @@ -10949,7 +10979,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 210 "/FPGA_Spartan6/SD_CLK" +Ne 216 "/Non_volatile_memories/SD_CLK" Po 433 0 $EndPAD $PAD @@ -10963,14 +10993,14 @@ $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 219 "/Non_volatile_memories/SD_DAT0" +Ne 218 "/Non_volatile_memories/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 212 "/FPGA_Spartan6/SD_DAT1" +Ne 219 "/Non_volatile_memories/SD_DAT1" Po 1732 0 $EndPAD $PAD @@ -11262,28 +11292,28 @@ $PAD Sh "6" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/NF_RNB" +Ne 214 "/Non_volatile_memories/NF_RNB" Po -1280 3850 $EndPAD $PAD Sh "7" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/NF_RNB" +Ne 214 "/Non_volatile_memories/NF_RNB" Po -1090 3850 $EndPAD $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/NF_RE_N" +Ne 213 "/Non_volatile_memories/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 216 "/Non_volatile_memories/NF_CS1_N" +Ne 116 "/FPGA_Spartan6/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -11332,21 +11362,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_CLE" +Ne 115 "/FPGA_Spartan6/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_ALE" +Ne 208 "/Non_volatile_memories/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/NF_WE_N" +Ne 215 "/Non_volatile_memories/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -11437,14 +11467,14 @@ $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 217 "/Non_volatile_memories/NF_D2" +Ne 209 "/Non_volatile_memories/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/NF_D3" +Ne 210 "/Non_volatile_memories/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -11507,28 +11537,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/NF_D4" +Ne 211 "/Non_volatile_memories/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 218 "/Non_volatile_memories/NF_D5" +Ne 119 "/FPGA_Spartan6/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/NF_D6" +Ne 212 "/Non_volatile_memories/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/NF_D7" +Ne 120 "/FPGA_Spartan6/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -11585,21 +11615,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/ETH_RXER" +Ne 49 "/Ethernet_Phy/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/ETH_RXC" +Ne 57 "/FPGA_Spartan6/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/ETH_RXDV" +Ne 48 "/Ethernet_Phy/ETH_RXDV" Po -1613 491 $EndPAD $PAD @@ -11620,63 +11650,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/ETH_RXD0" +Ne 44 "/Ethernet_Phy/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/Ethernet_Phy/ETH_RXD1" +Ne 45 "/Ethernet_Phy/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/ETH_RXD2" +Ne 46 "/Ethernet_Phy/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/Ethernet_Phy/ETH_RXD3" +Ne 47 "/Ethernet_Phy/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/Ethernet_Phy/ETH_MDC" +Ne 42 "/Ethernet_Phy/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/ETH_MDIO" +Ne 55 "/FPGA_Spartan6/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/ETH_RESET_N" +Ne 56 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/Ethernet_Phy/ETH_CLK" +Ne 38 "/Ethernet_Phy/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -11711,14 +11741,14 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 229 "N-000409" +Ne 234 "N-000406" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 233 "N-000413" +Ne 227 "N-000395" Po 491 -1613 $EndPAD $PAD @@ -11732,35 +11762,35 @@ $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_A3.3V" +Ne 37 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 227 "N-000398" +Ne 228 "N-000396" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/ETH_INT" +Ne 54 "/FPGA_Spartan6/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/Ethernet_Phy/ETH_LED0" +Ne 40 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/Ethernet_Phy/ETH_LED1" +Ne 41 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -11788,21 +11818,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_A1.8V" +Ne 36 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 232 "N-000412" +Ne 231 "N-000403" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 230 "N-000410" +Ne 233 "N-000405" Po 1613 -491 $EndPAD $PAD @@ -11837,63 +11867,63 @@ $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/Ethernet_Phy/ETH_TXER" +Ne 52 "/Ethernet_Phy/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/ETH_TXC" +Ne 58 "/FPGA_Spartan6/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/ETH_TXEN" +Ne 51 "/Ethernet_Phy/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/Ethernet_Phy/ETH_TXD0" +Ne 59 "/FPGA_Spartan6/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/ETH_TXD1" +Ne 50 "/Ethernet_Phy/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/Ethernet_Phy/ETH_TXD2" +Ne 60 "/FPGA_Spartan6/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/Ethernet_Phy/ETH_TXD3" +Ne 61 "/FPGA_Spartan6/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/Ethernet_Phy/ETH_COL" +Ne 53 "/FPGA_Spartan6/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/Ethernet_Phy/ETH_CRS" +Ne 39 "/Ethernet_Phy/ETH_CRS" Po 688 1613 $EndPAD $PAD @@ -11939,6 +11969,510 @@ Ne 224 "GND" Po 570 0 $EndPAD $EndMODULE 1206 +$MODULE SOT23-5 +Po 61220 48622 900 15 451B82FA 4C6D2BAF ~~ +Li SOT23-5 +Cd SOT23-5 +Sc 4C6D2BAF +AR /4C69ED5F/4C6D2AA5 +Op 0 0 0 +At SMD +T0 0 -150 300 250 900 50 N V 21 N"U11" +T1 0 150 300 250 900 50 N I 21 N"A7108" +DS 600 -350 600 350 50 21 +DS 600 350 -600 350 50 21 +DS -600 350 -600 -350 50 21 +DS -600 -350 600 -350 50 21 +$PAD +Sh "1" R 200 300 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 247 "N-000436" +Po -375 500 +$EndPAD +$PAD +Sh "3" R 200 300 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 249 "N-000447" +Po 375 500 +$EndPAD +$PAD +Sh "5" R 200 300 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 248 "N-000437" +Po -375 -500 +$EndPAD +$PAD +Sh "2" R 200 300 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "GND" +Po 0 500 +$EndPAD +$PAD +Sh "4" R 200 300 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 247 "N-000436" +Po 375 -500 +$EndPAD +$SHAPE3D +Na "smd/SOT23_5.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SOT23-5 +$MODULE SOT23-5 +Po 60827 45866 900 15 451B82FA 4C6D2BB1 ~~ +Li SOT23-5 +Cd SOT23-5 +Sc 4C6D2BB1 +AR /4C69ED5F/4C6D2AE0 +Op 0 0 0 +At SMD +T0 0 -150 300 250 900 50 N V 21 N"U12" +T1 0 150 300 250 900 50 N I 21 N"A7108" +DS 600 -350 600 350 50 21 +DS 600 350 -600 350 50 21 +DS -600 350 -600 -350 50 21 +DS -600 -350 600 -350 50 21 +$PAD +Sh "1" R 200 300 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 245 "N-000434" +Po -375 500 +$EndPAD +$PAD +Sh "3" R 200 300 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 250 "N-000466" +Po 375 500 +$EndPAD +$PAD +Sh "5" R 200 300 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 246 "N-000435" +Po -375 -500 +$EndPAD +$PAD +Sh "2" R 200 300 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "GND" +Po 0 500 +$EndPAD +$PAD +Sh "4" R 200 300 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 245 "N-000434" +Po 375 -500 +$EndPAD +$SHAPE3D +Na "smd/SOT23_5.wrl" +Sc 0.100000 0.100000 0.100000 +Of 0.000000 0.000000 0.000000 +Ro 0.000000 0.000000 0.000000 +$EndSHAPE3D +$EndMODULE SOT23-5 +$MODULE 0402 +Po 63582 49213 2700 15 4C5FF890 4C6D30F3 ~~ +Li 0402 +Sc 4C6D30F3 +AR /4C69ED5F/4C6D2C7F +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 25 N"C79" +T1 0 150 200 200 2700 40 N I 25 N"22pF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 248 "N-000437" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 62401 49213 900 15 4C5FF890 4C6D30F5 ~~ +Li 0402 +Sc 4C6D30F5 +AR /4C69ED5F/4C6D2DBC +Op 0 0 0 +At SMD +T0 0 -150 200 200 900 40 N V 25 N"R25" +T1 0 150 200 200 900 40 N I 25 N"R" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 248 "N-000437" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 62992 49213 2700 15 4C5FF890 4C6D30F7 ~~ +Li 0402 +Sc 4C6D30F7 +AR /4C69ED5F/4C6D2DDD +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 25 N"R26" +T1 0 150 200 200 2700 40 N I 25 N"R" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 248 "N-000437" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 65945 48622 2700 15 4C5FF890 4C6D30F9 ~~ +Li 0402 +Sc 4C6D30F9 +AR /4C69ED5F/4C6D2F0B +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 25 N"C81" +T1 0 150 200 200 2700 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 64961 45669 2700 15 4C5FF890 4C6D30FB ~~ +Li 0402 +Sc 4C6D30FB +AR /4C69ED5F/4C6D2FD0 +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 25 N"C85" +T1 0 150 200 200 2700 40 N I 25 N"100nF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 63189 46457 900 15 4C5FF890 4C6D30FD ~~ +Li 0402 +Sc 4C6D30FD +AR /4C69ED5F/4C6D2FD2 +Op 0 0 0 +At SMD +T0 0 -150 200 200 900 40 N V 25 N"R28" +T1 0 150 200 200 900 40 N I 25 N"R" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 246 "N-000435" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 62008 46457 2700 15 4C5FF890 4C6D30FF ~~ +Li 0402 +Sc 4C6D30FF +AR /4C69ED5F/4C6D2FD3 +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 21 N"R27" +T1 0 150 200 200 2700 40 N I 21 N"R" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 246 "N-000435" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "GND" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0402 +Po 62598 46457 900 15 4C5FF890 4C6D3101 ~~ +Li 0402 +Sc 4C6D3101 +AR /4C69ED5F/4C6D2FD6 +Op 0 0 0 +At SMD +T0 0 -150 200 200 900 40 N V 25 N"C83" +T1 0 150 200 200 900 40 N I 25 N"22pF" +DS -305 168 -305 -168 50 21 +DS -305 -168 305 -168 50 21 +DS 305 -168 305 168 50 21 +DS 305 168 -305 168 50 21 +$PAD +Sh "1" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -176 0 +$EndPAD +$PAD +Sh "2" R 157 236 0 0 900 +Dr 0 0 0 +At SMD N 00888000 +Ne 246 "N-000435" +Po 176 0 +$EndPAD +$EndMODULE 0402 +$MODULE 0805 +Po 60039 48622 2700 15 4C5FF890 4C6D3102 ~~ +Li 0805 +Sc 4C6D3102 +AR /4C69ED5F/4C6D2C7C +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 25 N"C78" +T1 0 150 200 200 2700 40 N I 25 N"4.7uF" +DS -561 305 -561 -305 50 21 +DS -561 -305 561 -305 50 21 +DS 561 -305 561 305 50 21 +DS 561 305 -561 305 50 21 +$PAD +Sh "1" R 275 510 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 247 "N-000436" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 0805 +Po 59646 45866 2700 15 4C5FF890 4C6D3104 ~~ +Li 0805 +Sc 4C6D3104 +AR /4C69ED5F/4C6D2FD7 +Op 0 0 0 +At SMD +T0 0 -150 200 200 2700 40 N V 25 N"C82" +T1 0 150 200 200 2700 40 N I 25 N"4.7uF" +DS -561 305 -561 -305 50 21 +DS -561 -305 561 -305 50 21 +DS 561 -305 561 305 50 21 +DS 561 305 -561 305 50 21 +$PAD +Sh "1" R 275 510 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 245 "N-000434" +Po -373 0 +$EndPAD +$PAD +Sh "2" R 275 510 0 0 2700 +Dr 0 0 0 +At SMD N 00888000 +Ne 224 "GND" +Po 373 0 +$EndPAD +$EndMODULE 0805 +$MODULE 1206 +Po 64763 48622 2700 15 4C5FF890 4C6D3105 ~~ +Li 1206 +Sc 4C6D3105 +AR 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4C5FF890 4C6D3108 ~~ +Li 1210 +Sc 4C6D3108 +AR /4C69ED5F/4C6D2E6A +Op 0 0 0 +At SMD +T0 0 -150 200 200 1800 40 N V 25 N"L8" +T1 0 150 200 200 1800 40 N I 25 N"2.2uH" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 4 "+3.3V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 249 "N-000447" +Po 570 0 +$EndPAD +$EndMODULE 1210 +$MODULE 1210 +Po 62598 45079 1800 15 4C5FF890 4C6D310A ~~ +Li 1210 +Sc 4C6D310A +AR /4C69ED5F/4C6D2FD1 +Op 0 0 0 +At SMD +T0 0 -150 200 200 1800 40 N V 25 N"L9" +T1 0 150 200 200 1800 40 N I 25 N"2.2uH" +DS -798 542 -798 -542 50 21 +DS -798 -542 798 -542 50 21 +DS 798 -542 798 542 50 21 +DS 798 542 -798 542 50 21 +$PAD +Sh "1" R 355 984 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 1 "+1.2V" +Po -570 0 +$EndPAD +$PAD +Sh "2" R 355 984 0 0 1800 +Dr 0 0 0 +At SMD N 00888000 +Ne 250 "N-000466" +Po 570 0 +$EndPAD +$EndMODULE 1210 $COTATION Ge 0 25 0 Va 35827 @@ -11990,544 +12524,544 @@ Po 0 53317 30639 53317 30443 39 -1 De 15 0 4 0 800 Po 0 53317 30443 53319 30441 39 -1 De 15 0 4 0 0 -Po 0 50995 31064 50651 31064 39 -1 -De 15 0 8 0 800 -Po 0 50395 31302 50177 31302 39 -1 -De 0 0 8 0 400 -Po 0 50642 31055 50395 31302 39 -1 -De 0 0 8 0 0 -Po 3 50642 31055 50642 31055 157 -1 -De 15 1 8 0 0 -Po 0 50651 31064 50642 31055 39 -1 -De 15 0 8 0 0 -Po 0 51858 33439 52896 33439 39 -1 -De 3 0 12 0 0 -Po 0 51677 33439 51858 33439 39 -1 -De 3 0 12 0 0 -Po 3 53126 33209 53126 33209 157 -1 -De 15 1 12 0 0 -Po 0 53126 33209 53317 33018 39 -1 -De 15 0 12 0 0 -Po 0 53317 33018 53317 33001 39 -1 -De 15 0 12 0 400 -Po 0 52896 33439 53126 33209 39 -1 -De 3 0 12 0 0 -Po 0 51551 33439 51568 33439 39 -1 -De 3 0 12 0 0 -Po 0 51568 33439 51618 33489 39 -1 -De 3 0 12 0 0 -Po 0 51677 33439 51668 33439 39 -1 -De 3 0 12 0 0 -Po 0 51668 33439 51618 33489 39 -1 -De 3 0 12 0 0 -Po 0 51618 33439 51618 33489 39 -1 -De 3 0 12 0 0 -Po 0 51618 33489 51618 33543 39 -1 -De 3 0 12 0 0 -Po 0 51568 33593 51370 33593 39 -1 -De 0 0 12 0 400 -Po 0 51598 33563 51568 33593 39 -1 -De 0 0 12 0 0 -Po 3 51598 33563 51598 33563 157 -1 -De 15 1 12 0 0 -Po 0 51618 33543 51598 33563 39 -1 -De 3 0 12 0 0 -Po 0 46643 33623 46922 33623 39 -1 -De 15 0 12 0 800 -Po 0 47112 33439 51551 33439 39 -1 -De 3 0 12 0 0 -Po 0 51551 33439 51618 33439 39 -1 -De 3 0 12 0 0 -Po 0 51618 33439 51677 33439 39 -1 -De 3 0 12 0 0 -Po 0 46925 33626 47112 33439 39 -1 -De 3 0 12 0 0 -Po 3 46925 33626 46925 33626 157 -1 -De 15 1 12 0 0 -Po 0 46922 33623 46925 33626 39 -1 -De 15 0 12 0 0 -Po 0 51370 33567 51370 33593 39 -1 -De 0 0 12 0 400 -Po 0 47062 26960 47560 26960 39 -1 -De 15 0 43 0 800 -Po 0 53317 29917 53317 30245 39 -1 -De 15 0 43 0 400 -Po 0 53300 29900 53317 29917 39 -1 -De 15 0 43 0 0 -Po 3 53300 29900 53300 29900 157 -1 -De 15 1 43 0 0 -Po 0 52800 29400 53300 29900 39 -1 -De 0 0 43 0 0 -Po 0 50000 29400 52800 29400 39 -1 -De 0 0 43 0 0 -Po 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24271 49294 24138 79 -1 -De 0 0 47 0 400 -Po 0 49354 24331 49294 24271 79 -1 -De 0 0 47 0 0 -Po 3 49354 24331 49354 24331 157 -1 -De 15 1 47 0 0 -Po 0 49363 24340 49354 24331 79 -1 -De 15 0 47 0 0 -Po 0 54104 30639 54104 30635 39 -1 -De 15 0 50 0 800 -Po 0 53445 29436 52384 29436 39 -1 -De 15 0 50 0 0 -Po 0 53909 29900 53445 29436 39 -1 -De 15 0 50 0 0 -Po 0 53909 30440 53909 29900 39 -1 -De 15 0 50 0 0 -Po 0 54104 30635 53909 30440 39 -1 -De 15 0 50 0 0 -Po 0 47996 28193 47996 27894 39 -1 -De 15 0 51 0 0 -Po 0 54092 31426 53906 31240 39 -1 -De 15 0 51 0 0 -Po 0 53906 31240 53614 31240 39 -1 -De 15 0 51 0 0 -Po 0 53614 31240 53516 31142 39 -1 -De 15 0 51 0 0 -Po 0 53516 31142 53516 31008 39 -1 -De 15 0 51 0 0 -Po 0 53516 31008 53378 30870 39 -1 -De 15 0 51 0 0 -Po 0 53378 30870 53323 30870 39 -1 -De 15 0 51 0 0 -Po 0 53323 30870 53157 30704 39 -1 -De 15 0 51 0 0 -Po 0 53157 30704 53157 29996 39 -1 -De 15 0 51 0 0 -Po 0 53157 29996 52921 29760 39 -1 -De 15 0 51 0 0 -Po 0 52921 29760 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0 138 0 0 +De 3 0 133 0 0 Po 3 49567 30996 49567 30996 157 -1 -De 15 1 138 0 0 +De 15 1 133 0 0 Po 0 49676 31105 49567 30996 39 -1 -De 0 0 138 0 0 +De 0 0 133 0 0 $EndTRACK $ZONE $EndZONE diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 9159401..bb95b9d 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,5 +1,75 @@ -# EESchema Netlist Version 1.1 created Wed 18 Aug 2010 10:06:46 PM COT +# EESchema Netlist Version 1.1 created Thu 19 Aug 2010 08:32:08 AM COT ( + ( /4C69ED5F/4C6D2FD7 0805 C82 4.7uF {Lib=CAP} + ( 1 N-000434 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2FD6 0402 C83 22pF {Lib=CAP} + ( 1 +1.2V ) + ( 2 N-000435 ) + ) + ( /4C69ED5F/4C6D2FD5 1206 C84 10uF {Lib=CAP} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2FD3 0402 R27 R {Lib=R} + ( 1 N-000435 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2FD2 0402 R28 R {Lib=R} + ( 1 +1.2V ) + ( 2 N-000435 ) + ) + ( /4C69ED5F/4C6D2FD1 1210 L9 2.2uH {Lib=INDUCTOR} + ( 1 +1.2V ) + ( 2 N-000466 ) + ) + ( /4C69ED5F/4C6D2FD0 0402 C85 100nF {Lib=CAP} + ( 1 +1.2V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2F0B 0402 C81 100nF {Lib=CAP} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2E6A 1210 L8 2.2uH {Lib=INDUCTOR} + ( 1 +3.3V ) + ( 2 N-000447 ) + ) + ( /4C69ED5F/4C6D2DDD 0402 R26 R {Lib=R} + ( 1 +3.3V ) + ( 2 N-000437 ) + ) + ( /4C69ED5F/4C6D2DBC 0402 R25 R {Lib=R} + ( 1 N-000437 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2C83 1206 C80 10uF {Lib=CAP} + ( 1 +3.3V ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2C7F 0402 C79 22pF {Lib=CAP} + ( 1 +3.3V ) + ( 2 N-000437 ) + ) + ( /4C69ED5F/4C6D2C7C 0805 C78 4.7uF {Lib=CAP} + ( 1 N-000436 ) + ( 2 GND ) + ) + ( /4C69ED5F/4C6D2AE0 SOT23-5 U12 A7108 {Lib=A7108} + ( 1 N-000434 ) + ( 2 GND ) + ( 3 N-000466 ) + ( 4 N-000434 ) + ( 5 N-000435 ) + ) + ( /4C69ED5F/4C6D2AA5 SOT23-5 U11 A7108 {Lib=A7108} + ( 1 N-000436 ) + ( 2 GND ) + ( 3 N-000447 ) + ( 4 N-000436 ) + ( 5 N-000437 ) + ) ( /4C69ED5F/4C6C9DB9 DFN10 U10 A7130 {Lib=A7130} ( PAD GND ) ( 1 ? ) @@ -67,13 +137,13 @@ ( COM GND ) ( CD ? ) ( 1 /Non_volatile_memories/SD_DAT2 ) - ( 2 /Non_volatile_memories/SD_DAT3 ) - ( 3 /FPGA_Spartan6/SD_CMD ) + ( 2 /FPGA_Spartan6/SD_DAT3 ) + ( 3 /Non_volatile_memories/SD_CMD ) ( 4 +3.3V ) - ( 5 /FPGA_Spartan6/SD_CLK ) + ( 5 /Non_volatile_memories/SD_CLK ) ( 6 GND ) ( 7 /Non_volatile_memories/SD_DAT0 ) - ( 8 /FPGA_Spartan6/SD_DAT1 ) + ( 8 /Non_volatile_memories/SD_DAT1 ) ) ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} ( 1 ? ) @@ -81,10 +151,10 @@ ( 3 ? ) ( 4 ? ) ( 5 ? ) - ( 6 /FPGA_Spartan6/NF_RNB ) - ( 7 /FPGA_Spartan6/NF_RNB ) - ( 8 /FPGA_Spartan6/NF_RE_N ) - ( 9 /Non_volatile_memories/NF_CS1_N ) + ( 6 /Non_volatile_memories/NF_RNB ) + ( 7 /Non_volatile_memories/NF_RNB ) + ( 8 /Non_volatile_memories/NF_RE_N ) + ( 9 /FPGA_Spartan6/NF_CS1_N ) ( 10 ? ) ( 11 ? ) ( 12 +3.3V ) @@ -92,8 +162,8 @@ ( 14 ? ) ( 15 ? ) ( 16 /FPGA_Spartan6/NF_CLE ) - ( 17 /FPGA_Spartan6/NF_ALE ) - ( 18 /FPGA_Spartan6/NF_WE_N ) + ( 17 /Non_volatile_memories/NF_ALE ) + ( 18 /Non_volatile_memories/NF_WE_N ) ( 19 +3.3V ) ( 20 ? ) ( 21 ? ) @@ -107,7 +177,7 @@ ( 29 /FPGA_Spartan6/NF_D0 ) ( 30 /FPGA_Spartan6/NF_D1 ) ( 31 /Non_volatile_memories/NF_D2 ) - ( 32 /FPGA_Spartan6/NF_D3 ) + ( 32 /Non_volatile_memories/NF_D3 ) ( 33 ? ) ( 34 ? ) ( 35 ? ) @@ -116,9 +186,9 @@ ( 38 ? ) ( 39 ? ) ( 40 ? ) - ( 41 /FPGA_Spartan6/NF_D4 ) - ( 42 /Non_volatile_memories/NF_D5 ) - ( 43 /FPGA_Spartan6/NF_D6 ) + ( 41 /Non_volatile_memories/NF_D4 ) + ( 42 /FPGA_Spartan6/NF_D5 ) + ( 43 /Non_volatile_memories/NF_D6 ) ( 44 /FPGA_Spartan6/NF_D7 ) ( 45 ? ) ( 46 ? ) @@ -134,7 +204,7 @@ ( 7 GND ) ( 8 GND ) ( 9 ? ) - ( 10 N-000433 ) + ( 10 N-000431 ) ( 11 N-000432 ) ( 12 +3.3V ) ( 14 +3.3V ) @@ -152,11 +222,11 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552BA $noname F2 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000418 ) + ( 1 N-000422 ) ( 2 +5V ) ) ( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000433 ) + ( 1 N-000431 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03} @@ -164,11 +234,11 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C} - ( 1 N-000420 ) + ( 1 N-000433 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R} - ( 1 N-000420 ) + ( 1 N-000433 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} @@ -176,27 +246,27 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552B0 0603 L6 FB {Lib=INDUCTOR} - ( 1 N-000418 ) + ( 1 N-000422 ) ( 2 ? ) ) ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000424 ) - ( 2 N-000425 ) + ( 1 N-000429 ) + ( 2 N-000427 ) ) ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000422 ) + ( 1 N-000425 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000423 ) + ( 1 N-000424 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000423 ) + ( 1 N-000424 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000427 ) + ( 1 N-000430 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} @@ -204,18 +274,18 @@ ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000424 ) + ( 1 N-000429 ) ( 2 +5V ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000423 ) - ( S2 N-000423 ) - ( S3 N-000423 ) - ( S4 N-000423 ) - ( 1 N-000425 ) + ( S1 N-000424 ) + ( S2 N-000424 ) + ( S3 N-000424 ) + ( S4 N-000424 ) + ( 1 N-000427 ) ( 2 N-000426 ) - ( 3 N-000427 ) - ( 4 N-000422 ) + ( 3 N-000430 ) + ( 4 N-000425 ) ) ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} ( 1 +2.5V ) @@ -231,15 +301,15 @@ ) ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) - ( 2 /USB/USBA_SPD ) - ( 3 /FPGA_Spartan6/USBA_RCV ) + ( 2 /FPGA_Spartan6/USBA_SPD ) + ( 3 /USB/USBA_RCV ) ( 4 /USB/USBA_VP ) - ( 5 /FPGA_Spartan6/USBA_VM ) + ( 5 /USB/USBA_VM ) ( 7 GND ) ( 8 GND ) ( 9 /FPGA_Spartan6/USBA_OE_N ) ( 10 N-000426 ) - ( 11 N-000427 ) + ( 11 N-000430 ) ( 12 +3.3V ) ( 14 +3.3V ) ) @@ -261,11 +331,11 @@ ) ( /4C431A63/4C6B216B 0402 R24 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M0_CKE ) - ( 2 /FPGA_Spartan6/M0_CKE ) + ( 2 /DDR_Banks/M0_CKE ) ) ( /4C431A63/4C6B1B90 0402 R21 120 {Lib=R} ( 1 /DDR_Banks/M0_CLK ) - ( 2 /FPGA_Spartan6/M0_CLK# ) + ( 2 /DDR_Banks/M0_CLK# ) ) ( /4C431A63/4C6A0D58 R_PACK4-0402 RP14 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_A0 ) @@ -273,9 +343,9 @@ ( 3 /FPGA_Spartan6/R_M0_A2 ) ( 4 /FPGA_Spartan6/R_M0_A3 ) ( 5 /FPGA_Spartan6/M0_A3 ) - ( 6 /DDR_Banks/M0_A2 ) + ( 6 /FPGA_Spartan6/M0_A2 ) ( 7 /FPGA_Spartan6/M0_A1 ) - ( 8 /FPGA_Spartan6/M0_A0 ) + ( 8 /DDR_Banks/M0_A0 ) ) ( /4C431A63/4C6A0D57 R_PACK4-0402 RP15 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_RAS# ) @@ -285,16 +355,16 @@ ( 5 /FPGA_Spartan6/M0_A10 ) ( 6 /FPGA_Spartan6/M0_BA1 ) ( 7 /FPGA_Spartan6/M0_BA0 ) - ( 8 /FPGA_Spartan6/M0_RAS# ) + ( 8 /DDR_Banks/M0_RAS# ) ) ( /4C431A63/4C6A0D56 R_PACK4-0402 RP16 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_LDQS ) ( 2 /FPGA_Spartan6/R_M0_LDM ) ( 3 /FPGA_Spartan6/R_M0_WE# ) ( 4 /FPGA_Spartan6/R_M0_CAS# ) - ( 5 /DDR_Banks/M0_CAS# ) + ( 5 /FPGA_Spartan6/M0_CAS# ) ( 6 /FPGA_Spartan6/M0_WE# ) - ( 7 /FPGA_Spartan6/M0_LDM ) + ( 7 /DDR_Banks/M0_LDM ) ( 8 /DDR_Banks/M0_LDQS ) ) ( /4C431A63/4C6A0D55 R_PACK4-0402 RP17 R_PACK4 {Lib=R_PACK4} @@ -304,7 +374,7 @@ ( 4 /FPGA_Spartan6/R_M0_A4 ) ( 5 /FPGA_Spartan6/M0_A4 ) ( 6 /FPGA_Spartan6/M0_A5 ) - ( 7 /DDR_Banks/M0_A6 ) + ( 7 /FPGA_Spartan6/M0_A6 ) ( 8 /FPGA_Spartan6/M0_A7 ) ) ( /4C431A63/4C6A0D54 R_PACK4-0402 RP18 R_PACK4 {Lib=R_PACK4} @@ -313,9 +383,9 @@ ( 3 /FPGA_Spartan6/R_M0_A9 ) ( 4 /FPGA_Spartan6/R_M0_A8 ) ( 5 /FPGA_Spartan6/M0_A8 ) - ( 6 /DDR_Banks/M0_A9 ) - ( 7 /DDR_Banks/M0_A11 ) - ( 8 /DDR_Banks/M0_A12 ) + ( 6 /FPGA_Spartan6/M0_A9 ) + ( 7 /FPGA_Spartan6/M0_A11 ) + ( 8 /FPGA_Spartan6/M0_A12 ) ) ( /4C431A63/4C69FCE8 R_PACK4-0402 RP12 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M0_DQ4 ) @@ -323,7 +393,7 @@ ( 3 /FPGA_Spartan6/R_M0_DQ6 ) ( 4 /FPGA_Spartan6/R_M0_DQ7 ) ( 5 /FPGA_Spartan6/M0_DQ7 ) - ( 6 /DDR_Banks/M0_DQ6 ) + ( 6 /FPGA_Spartan6/M0_DQ6 ) ( 7 /FPGA_Spartan6/M0_DQ5 ) ( 8 /FPGA_Spartan6/M0_DQ4 ) ) @@ -332,9 +402,9 @@ ( 2 /FPGA_Spartan6/R_M0_DQ1 ) ( 3 /FPGA_Spartan6/R_M0_DQ2 ) ( 4 /FPGA_Spartan6/R_M0_DQ3 ) - ( 5 /DDR_Banks/M0_DQ3 ) + ( 5 /FPGA_Spartan6/M0_DQ3 ) ( 6 /FPGA_Spartan6/M0_DQ2 ) - ( 7 /FPGA_Spartan6/M0_DQ1 ) + ( 7 /DDR_Banks/M0_DQ1 ) ( 8 /FPGA_Spartan6/M0_DQ0 ) ) ( /4C431A63/4C69FCE6 R_PACK4-0402 RP11 R_PACK4 {Lib=R_PACK4} @@ -343,8 +413,8 @@ ( 3 /FPGA_Spartan6/R_M0_DQ10 ) ( 4 /FPGA_Spartan6/R_M0_DQ11 ) ( 5 /DDR_Banks/M0_DQ11 ) - ( 6 /FPGA_Spartan6/M0_DQ10 ) - ( 7 /DDR_Banks/M0_DQ9 ) + ( 6 /DDR_Banks/M0_DQ10 ) + ( 7 /FPGA_Spartan6/M0_DQ9 ) ( 8 /FPGA_Spartan6/M0_DQ8 ) ) ( /4C431A63/4C69FC19 R_PACK4-0402 RP10 R_PACK4 {Lib=R_PACK4} @@ -354,8 +424,8 @@ ( 4 /FPGA_Spartan6/R_M0_DQ15 ) ( 5 /FPGA_Spartan6/M0_DQ15 ) ( 6 /DDR_Banks/M0_DQ14 ) - ( 7 /FPGA_Spartan6/M0_DQ13 ) - ( 8 /FPGA_Spartan6/M0_DQ12 ) + ( 7 /DDR_Banks/M0_DQ13 ) + ( 8 /DDR_Banks/M0_DQ12 ) ) ( /4C431A63/4C69E7DD 0402 R19 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_UDQS ) @@ -363,15 +433,15 @@ ) ( /4C431A63/4C69E92D 0402 R20 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CS# ) - ( 2 /FPGA_Spartan6/M1_CS# ) + ( 2 /DDR_Banks/M1_CS# ) ) ( /4C431A63/4C69E7F8 0402 R17 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_CKE ) - ( 2 /DDR_Banks/M1_CKE ) + ( 2 /FPGA_Spartan6/M1_CKE ) ) ( /4C431A63/4C69E7C2 0402 R18 33 {Lib=R} ( 1 /FPGA_Spartan6/R_M1_UDM ) - ( 2 /DDR_Banks/M1_UDM ) + ( 2 /FPGA_Spartan6/M1_UDM ) ) ( /4C431A63/4C69E3A6 $noname RP9 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ11 ) @@ -380,22 +450,22 @@ ( 4 /FPGA_Spartan6/R_M1_DQ8 ) ( 5 /FPGA_Spartan6/M1_DQ8 ) ( 6 /FPGA_Spartan6/M1_DQ9 ) - ( 7 /FPGA_Spartan6/M1_DQ10 ) - ( 8 /FPGA_Spartan6/M1_DQ11 ) + ( 7 /DDR_Banks/M1_DQ10 ) + ( 8 /DDR_Banks/M1_DQ11 ) ) ( /4C431A63/4C69E299 $noname RP8 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ15 ) ( 2 /FPGA_Spartan6/R_M1_DQ14 ) ( 3 /FPGA_Spartan6/R_M1_DQ13 ) ( 4 /FPGA_Spartan6/R_M1_DQ12 ) - ( 5 /FPGA_Spartan6/M1_DQ12 ) + ( 5 /DDR_Banks/M1_DQ12 ) ( 6 /DDR_Banks/M1_DQ13 ) ( 7 /FPGA_Spartan6/M1_DQ14 ) ( 8 /FPGA_Spartan6/M1_DQ15 ) ) ( /4C431A63/4C69DF7A 0402 R16 120 {Lib=R} ( 1 /DDR_Banks/M1_CLK# ) - ( 2 /DDR_Banks/M1_CLK ) + ( 2 /FPGA_Spartan6/M1_CLK ) ) ( /4C431A63/4C69DC05 $noname RP7 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A12 ) @@ -403,19 +473,19 @@ ( 3 /FPGA_Spartan6/R_M1_A9 ) ( 4 /FPGA_Spartan6/R_M1_A8 ) ( 5 /DDR_Banks/M1_A8 ) - ( 6 /DDR_Banks/M1_A9 ) + ( 6 /FPGA_Spartan6/M1_A9 ) ( 7 /FPGA_Spartan6/M1_A11 ) - ( 8 /FPGA_Spartan6/M1_A12 ) + ( 8 /DDR_Banks/M1_A12 ) ) ( /4C431A63/4C69DA8A $noname RP6 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_A7 ) ( 2 /FPGA_Spartan6/R_M1_A6 ) ( 3 /FPGA_Spartan6/R_M1_A5 ) ( 4 ? ) - ( 5 /DDR_Banks/M1_A4 ) + ( 5 /FPGA_Spartan6/M1_A4 ) ( 6 /FPGA_Spartan6/M1_A5 ) - ( 7 /FPGA_Spartan6/M1_A6 ) - ( 8 /DDR_Banks/M1_A7 ) + ( 7 /DDR_Banks/M1_A6 ) + ( 8 /FPGA_Spartan6/M1_A7 ) ) ( /4C431A63/4C69D3A9 $noname RP5 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_DQ0 ) @@ -423,16 +493,16 @@ ( 3 /FPGA_Spartan6/R_M1_DQ2 ) ( 4 /FPGA_Spartan6/R_M1_DQ3 ) ( 5 /DDR_Banks/M1_DQ3 ) - ( 6 /DDR_Banks/M1_DQ2 ) - ( 7 /FPGA_Spartan6/M1_DQ1 ) - ( 8 /DDR_Banks/M1_DQ0 ) + ( 6 /FPGA_Spartan6/M1_DQ2 ) + ( 7 /DDR_Banks/M1_DQ1 ) + ( 8 /FPGA_Spartan6/M1_DQ0 ) ) ( /4C431A63/4C69D3A4 $noname RP3 R_PACK4 {Lib=R_PACK4} ( 1 /FPGA_Spartan6/R_M1_LDQS ) ( 2 /FPGA_Spartan6/R_M1_LDM ) ( 3 /FPGA_Spartan6/R_M1_WE# ) ( 4 /FPGA_Spartan6/R_M1_CAS# ) - ( 5 /DDR_Banks/M1_CAS# ) + ( 5 /FPGA_Spartan6/M1_CAS# ) ( 6 /DDR_Banks/M1_WE# ) ( 7 /FPGA_Spartan6/M1_LDM ) ( 8 /DDR_Banks/M1_LDQS ) @@ -442,8 +512,8 @@ ( 2 /FPGA_Spartan6/R_M1_DQ5 ) ( 3 /FPGA_Spartan6/R_M1_DQ6 ) ( 4 /FPGA_Spartan6/R_M1_DQ7 ) - ( 5 /DDR_Banks/M1_DQ7 ) - ( 6 /DDR_Banks/M1_DQ6 ) + ( 5 /FPGA_Spartan6/M1_DQ7 ) + ( 6 /FPGA_Spartan6/M1_DQ6 ) ( 7 /FPGA_Spartan6/M1_DQ5 ) ( 8 /FPGA_Spartan6/M1_DQ4 ) ) @@ -463,7 +533,7 @@ ( 3 /FPGA_Spartan6/R_M1_A2 ) ( 4 /FPGA_Spartan6/R_M1_A3 ) ( 5 /FPGA_Spartan6/M1_A3 ) - ( 6 /DDR_Banks/M1_A2 ) + ( 6 /FPGA_Spartan6/M1_A2 ) ( 7 /FPGA_Spartan6/M1_A1 ) ( 8 /FPGA_Spartan6/M1_A0 ) ) @@ -641,7 +711,7 @@ ( L20 /FPGA_Spartan6/R_M1_LDQS ) ( K20 /FPGA_Spartan6/R_M1_A5 ) ( J20 /FPGA_Spartan6/R_M1_DQ4 ) - ( H20 /DDR_Banks/M1_CLK ) + ( H20 /FPGA_Spartan6/M1_CLK ) ( G20 /FPGA_Spartan6/R_M1_A3 ) ( F20 ? ) ( E20 /FPGA_Spartan6/R_M1_A7 ) @@ -706,7 +776,7 @@ ( L3 /FPGA_Spartan6/R_M0_LDQS ) ( K3 /FPGA_Spartan6/R_M0_A5 ) ( J3 /FPGA_Spartan6/R_M0_DQ4 ) - ( H3 /FPGA_Spartan6/M0_CLK# ) + ( H3 /DDR_Banks/M0_CLK# ) ( G3 /FPGA_Spartan6/R_M0_BA0 ) ( F3 /FPGA_Spartan6/R_M0_A4 ) ( E3 /FPGA_Spartan6/R_M0_A8 ) @@ -716,24 +786,24 @@ ( G10 +3.3V ) ( D10 /Ethernet_Phy/ETH_MDC ) ( C10 /Ethernet_Phy/ETH_CRS ) - ( B10 /Ethernet_Phy/ETH_COL ) + ( B10 /FPGA_Spartan6/ETH_COL ) ( A10 /FPGA_Spartan6/ETH_INT ) ( E9 +3.3V ) - ( D9 /Ethernet_Phy/ETH_TXD0 ) - ( C9 /Ethernet_Phy/ETH_TXD2 ) - ( A9 /Ethernet_Phy/ETH_TXD3 ) + ( D9 /FPGA_Spartan6/ETH_TXD0 ) + ( C9 /FPGA_Spartan6/ETH_TXD2 ) + ( A9 /FPGA_Spartan6/ETH_TXD3 ) ( D8 /FPGA_Spartan6/ETH_RXC ) - ( C8 /FPGA_Spartan6/ETH_TXD1 ) + ( C8 /Ethernet_Phy/ETH_TXD1 ) ( B8 /Ethernet_Phy/ETH_TXER ) - ( A8 /FPGA_Spartan6/ETH_TXEN ) + ( A8 /Ethernet_Phy/ETH_TXEN ) ( D7 /FPGA_Spartan6/ETH_TXC ) - ( C7 /FPGA_Spartan6/ETH_RXDV ) + ( C7 /Ethernet_Phy/ETH_RXDV ) ( B7 +3.3V ) - ( A7 /FPGA_Spartan6/ETH_RXER ) + ( A7 /Ethernet_Phy/ETH_RXER ) ( D6 /Ethernet_Phy/ETH_RXD3 ) - ( C6 /FPGA_Spartan6/ETH_RXD2 ) + ( C6 /Ethernet_Phy/ETH_RXD2 ) ( B6 /Ethernet_Phy/ETH_RXD1 ) - ( A6 /FPGA_Spartan6/ETH_RXD0 ) + ( A6 /Ethernet_Phy/ETH_RXD0 ) ( C5 /FPGA_Spartan6/ETH_MDIO ) ( A5 /FPGA_Spartan6/ETH_RESET_N ) ( B4 +3.3V ) @@ -741,23 +811,23 @@ ( A3 ? ) ( U19 ? ) ( T19 ? ) - ( R19 /USB/USBA_SPD ) + ( R19 /FPGA_Spartan6/USBA_SPD ) ( P19 ? ) ( B19 +3.3V ) - ( B18 /FPGA_Spartan6/SD_DAT1 ) + ( B18 /Non_volatile_memories/SD_DAT1 ) ( A18 /Non_volatile_memories/SD_DAT0 ) ( E17 +3.3V ) - ( D17 /FPGA_Spartan6/SD_CMD ) - ( C17 /Non_volatile_memories/SD_DAT3 ) + ( D17 /Non_volatile_memories/SD_CMD ) + ( C17 /FPGA_Spartan6/SD_DAT3 ) ( A17 /Non_volatile_memories/SD_DAT2 ) - ( E16 /FPGA_Spartan6/SD_CLK ) - ( C16 /Non_volatile_memories/NF_CS1_N ) - ( B16 /FPGA_Spartan6/NF_RE_N ) - ( A16 /FPGA_Spartan6/NF_RNB ) + ( E16 /Non_volatile_memories/SD_CLK ) + ( C16 /FPGA_Spartan6/NF_CS1_N ) + ( B16 /Non_volatile_memories/NF_RE_N ) + ( A16 /Non_volatile_memories/NF_RNB ) ( D15 /FPGA_Spartan6/NF_CLE ) - ( C15 /FPGA_Spartan6/NF_WE_N ) + ( C15 /Non_volatile_memories/NF_WE_N ) ( B15 +3.3V ) - ( A15 /FPGA_Spartan6/NF_ALE ) + ( A15 /Non_volatile_memories/NF_ALE ) ( G14 +3.3V ) ( D14 /FPGA_Spartan6/NF_D0 ) ( C14 ? ) @@ -766,10 +836,10 @@ ( E13 +3.3V ) ( C13 /Non_volatile_memories/NF_D2 ) ( A13 /FPGA_Spartan6/NF_D1 ) - ( C12 /Non_volatile_memories/NF_D5 ) - ( B12 /FPGA_Spartan6/NF_D4 ) - ( A12 /FPGA_Spartan6/NF_D3 ) - ( D11 /FPGA_Spartan6/NF_D6 ) + ( C12 /FPGA_Spartan6/NF_D5 ) + ( B12 /Non_volatile_memories/NF_D4 ) + ( A12 /Non_volatile_memories/NF_D3 ) + ( D11 /Non_volatile_memories/NF_D6 ) ( C11 ? ) ( B11 +3.3V ) ( A11 /FPGA_Spartan6/NF_D7 ) @@ -817,7 +887,7 @@ ( U18 +2.5V ) ( P18 /FPGA_Spartan6/USBA_OE_N ) ( N18 +2.5V ) - ( M18 /FPGA_Spartan6/USBA_VM ) + ( M18 /USB/USBA_VM ) ( K18 ? ) ( J18 +2.5V ) ( H18 ? ) @@ -830,7 +900,7 @@ ( H17 ? ) ( G17 ? ) ( F17 ? ) - ( N16 /FPGA_Spartan6/USBA_RCV ) + ( N16 /USB/USBA_RCV ) ( M16 ? ) ( L16 +2.5V ) ( K16 ? ) @@ -1130,7 +1200,7 @@ ( 2 +3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000398 ) + ( 1 N-000396 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} @@ -1142,35 +1212,35 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000407 ) + ( 1 N-000404 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000407 ) + ( 1 N-000404 ) ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} ( 1 /FPGA_Spartan6/ETH_MDIO ) ( 2 /Ethernet_Phy/ETH_MDC ) ( 3 /Ethernet_Phy/ETH_RXD3 ) - ( 4 /FPGA_Spartan6/ETH_RXD2 ) + ( 4 /Ethernet_Phy/ETH_RXD2 ) ( 5 /Ethernet_Phy/ETH_RXD1 ) - ( 6 /FPGA_Spartan6/ETH_RXD0 ) + ( 6 /Ethernet_Phy/ETH_RXD0 ) ( 7 +3.3V ) ( 8 GND ) - ( 9 /FPGA_Spartan6/ETH_RXDV ) + ( 9 /Ethernet_Phy/ETH_RXDV ) ( 10 /FPGA_Spartan6/ETH_RXC ) - ( 11 /FPGA_Spartan6/ETH_RXER ) + ( 11 /Ethernet_Phy/ETH_RXER ) ( 12 GND ) ( 13 +1.8V ) ( 14 /Ethernet_Phy/ETH_TXER ) ( 15 /FPGA_Spartan6/ETH_TXC ) - ( 16 /FPGA_Spartan6/ETH_TXEN ) - ( 17 /Ethernet_Phy/ETH_TXD0 ) - ( 18 /FPGA_Spartan6/ETH_TXD1 ) - ( 19 /Ethernet_Phy/ETH_TXD2 ) - ( 20 /Ethernet_Phy/ETH_TXD3 ) - ( 21 /Ethernet_Phy/ETH_COL ) + ( 16 /Ethernet_Phy/ETH_TXEN ) + ( 17 /FPGA_Spartan6/ETH_TXD0 ) + ( 18 /Ethernet_Phy/ETH_TXD1 ) + ( 19 /FPGA_Spartan6/ETH_TXD2 ) + ( 20 /FPGA_Spartan6/ETH_TXD3 ) + ( 21 /FPGA_Spartan6/ETH_COL ) ( 22 /Ethernet_Phy/ETH_CRS ) ( 23 GND ) ( 24 +3.3V ) @@ -1181,16 +1251,16 @@ ( 29 ? ) ( 30 ? ) ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000412 ) - ( 33 N-000410 ) + ( 32 N-000403 ) + ( 33 N-000405 ) ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000398 ) + ( 37 N-000396 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) - ( 40 N-000413 ) - ( 41 N-000409 ) + ( 40 N-000395 ) + ( 41 N-000406 ) ( 42 ? ) ( 43 ? ) ( 44 GND ) @@ -1201,58 +1271,58 @@ ) ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000409 ) + ( 2 N-000406 ) ) ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000413 ) + ( 2 N-000395 ) ) ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000412 ) + ( 2 N-000403 ) ) ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} ( 1 +3.3V ) - ( 2 N-000410 ) + ( 2 N-000405 ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000411 ) + ( 1 N-000397 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000415 ) + ( 1 N-000402 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000409 ) - ( 2 N-000413 ) + ( 1 N-000406 ) + ( 2 N-000395 ) ( 3 +3.3V ) ( 4 GND ) ( 5 GND ) ( 6 +3.3V ) - ( 7 N-000410 ) - ( 8 N-000412 ) + ( 7 N-000405 ) + ( 8 N-000403 ) ( 9 +3.3V ) - ( 10 N-000415 ) + ( 10 N-000402 ) ( 11 +3.3V ) - ( 12 N-000411 ) - ( 13 N-000407 ) - ( 14 N-000407 ) + ( 12 N-000397 ) + ( 13 N-000404 ) + ( 14 N-000404 ) ) ( /4C421DD3/4C609C8E $noname U3 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /DDR_Banks/M1_DQ0 ) + ( 2 /FPGA_Spartan6/M1_DQ0 ) ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M1_DQ1 ) - ( 5 /DDR_Banks/M1_DQ2 ) + ( 4 /DDR_Banks/M1_DQ1 ) + ( 5 /FPGA_Spartan6/M1_DQ2 ) ( 6 GND ) ( 7 /DDR_Banks/M1_DQ3 ) ( 8 /FPGA_Spartan6/M1_DQ4 ) ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M1_DQ5 ) - ( 11 /DDR_Banks/M1_DQ6 ) + ( 11 /FPGA_Spartan6/M1_DQ6 ) ( 12 GND ) - ( 13 /DDR_Banks/M1_DQ7 ) + ( 13 /FPGA_Spartan6/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) ( 16 /DDR_Banks/M1_LDQS ) @@ -1261,32 +1331,32 @@ ( 19 ? ) ( 20 /FPGA_Spartan6/M1_LDM ) ( 21 /DDR_Banks/M1_WE# ) - ( 22 /DDR_Banks/M1_CAS# ) + ( 22 /FPGA_Spartan6/M1_CAS# ) ( 23 /FPGA_Spartan6/M1_RAS# ) - ( 24 /FPGA_Spartan6/M1_CS# ) + ( 24 /DDR_Banks/M1_CS# ) ( 25 ? ) ( 26 /DDR_Banks/M1_BA0 ) ( 27 /DDR_Banks/M1_BA1 ) ( 28 /DDR_Banks/M1_A10 ) ( 29 /FPGA_Spartan6/M1_A0 ) ( 30 /FPGA_Spartan6/M1_A1 ) - ( 31 /DDR_Banks/M1_A2 ) + ( 31 /FPGA_Spartan6/M1_A2 ) ( 32 /FPGA_Spartan6/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) - ( 35 /DDR_Banks/M1_A4 ) + ( 35 /FPGA_Spartan6/M1_A4 ) ( 36 /FPGA_Spartan6/M1_A5 ) - ( 37 /FPGA_Spartan6/M1_A6 ) - ( 38 /DDR_Banks/M1_A7 ) + ( 37 /DDR_Banks/M1_A6 ) + ( 38 /FPGA_Spartan6/M1_A7 ) ( 39 /DDR_Banks/M1_A8 ) - ( 40 /DDR_Banks/M1_A9 ) + ( 40 /FPGA_Spartan6/M1_A9 ) ( 41 /FPGA_Spartan6/M1_A11 ) - ( 42 /FPGA_Spartan6/M1_A12 ) + ( 42 /DDR_Banks/M1_A12 ) ( 43 ? ) ( 44 /DDR_Banks/M1_CLK# ) - ( 45 /DDR_Banks/M1_CKE ) - ( 46 /DDR_Banks/M1_CLK ) - ( 47 /DDR_Banks/M1_UDM ) + ( 45 /FPGA_Spartan6/M1_CKE ) + ( 46 /FPGA_Spartan6/M1_CLK ) + ( 47 /FPGA_Spartan6/M1_UDM ) ( 48 GND ) ( 49 N-000058 ) ( 50 ? ) @@ -1296,10 +1366,10 @@ ( 54 /FPGA_Spartan6/M1_DQ8 ) ( 55 +2.5V ) ( 56 /FPGA_Spartan6/M1_DQ9 ) - ( 57 /FPGA_Spartan6/M1_DQ10 ) + ( 57 /DDR_Banks/M1_DQ10 ) ( 58 GND ) - ( 59 /FPGA_Spartan6/M1_DQ11 ) - ( 60 /FPGA_Spartan6/M1_DQ12 ) + ( 59 /DDR_Banks/M1_DQ11 ) + ( 60 /DDR_Banks/M1_DQ12 ) ( 61 +2.5V ) ( 62 /DDR_Banks/M1_DQ13 ) ( 63 /FPGA_Spartan6/M1_DQ14 ) @@ -1407,14 +1477,14 @@ ( 1 +2.5V ) ( 2 /FPGA_Spartan6/M0_DQ0 ) ( 3 +2.5V ) - ( 4 /FPGA_Spartan6/M0_DQ1 ) + ( 4 /DDR_Banks/M0_DQ1 ) ( 5 /FPGA_Spartan6/M0_DQ2 ) ( 6 GND ) - ( 7 /DDR_Banks/M0_DQ3 ) + ( 7 /FPGA_Spartan6/M0_DQ3 ) ( 8 /FPGA_Spartan6/M0_DQ4 ) ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M0_DQ5 ) - ( 11 /DDR_Banks/M0_DQ6 ) + ( 11 /FPGA_Spartan6/M0_DQ6 ) ( 12 GND ) ( 13 /FPGA_Spartan6/M0_DQ7 ) ( 14 ? ) @@ -1423,32 +1493,32 @@ ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Spartan6/M0_LDM ) + ( 20 /DDR_Banks/M0_LDM ) ( 21 /FPGA_Spartan6/M0_WE# ) - ( 22 /DDR_Banks/M0_CAS# ) - ( 23 /FPGA_Spartan6/M0_RAS# ) + ( 22 /FPGA_Spartan6/M0_CAS# ) + ( 23 /DDR_Banks/M0_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /FPGA_Spartan6/M0_BA0 ) ( 27 /FPGA_Spartan6/M0_BA1 ) ( 28 /FPGA_Spartan6/M0_A10 ) - ( 29 /FPGA_Spartan6/M0_A0 ) + ( 29 /DDR_Banks/M0_A0 ) ( 30 /FPGA_Spartan6/M0_A1 ) - ( 31 /DDR_Banks/M0_A2 ) + ( 31 /FPGA_Spartan6/M0_A2 ) ( 32 /FPGA_Spartan6/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M0_A4 ) ( 36 /FPGA_Spartan6/M0_A5 ) - ( 37 /DDR_Banks/M0_A6 ) + ( 37 /FPGA_Spartan6/M0_A6 ) ( 38 /FPGA_Spartan6/M0_A7 ) ( 39 /FPGA_Spartan6/M0_A8 ) - ( 40 /DDR_Banks/M0_A9 ) - ( 41 /DDR_Banks/M0_A11 ) - ( 42 /DDR_Banks/M0_A12 ) + ( 40 /FPGA_Spartan6/M0_A9 ) + ( 41 /FPGA_Spartan6/M0_A11 ) + ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) - ( 44 /FPGA_Spartan6/M0_CLK# ) - ( 45 /FPGA_Spartan6/M0_CKE ) + ( 44 /DDR_Banks/M0_CLK# ) + ( 45 /DDR_Banks/M0_CKE ) ( 46 /DDR_Banks/M0_CLK ) ( 47 /FPGA_Spartan6/M0_UDM ) ( 48 GND ) @@ -1459,13 +1529,13 @@ ( 53 ? ) ( 54 /FPGA_Spartan6/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /DDR_Banks/M0_DQ9 ) - ( 57 /FPGA_Spartan6/M0_DQ10 ) + ( 56 /FPGA_Spartan6/M0_DQ9 ) + ( 57 /DDR_Banks/M0_DQ10 ) ( 58 GND ) ( 59 /DDR_Banks/M0_DQ11 ) - ( 60 /FPGA_Spartan6/M0_DQ12 ) + ( 60 /DDR_Banks/M0_DQ12 ) ( 61 +2.5V ) - ( 62 /FPGA_Spartan6/M0_DQ13 ) + ( 62 /DDR_Banks/M0_DQ13 ) ( 63 /DDR_Banks/M0_DQ14 ) ( 64 GND ) ( 65 /FPGA_Spartan6/M0_DQ15 ) @@ -1474,6 +1544,70 @@ ) * { Allowed footprints by component: +$component C82 + SM* + C? + C1-1 +$endlist +$component C83 + SM* + C? + C1-1 +$endlist +$component C84 + SM* + C? + C1-1 +$endlist +$component R27 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R28 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C85 + SM* + C? + C1-1 +$endlist +$component C81 + SM* + C? + C1-1 +$endlist +$component R26 + R? + SM0603 + SM0805 + R?-* +$endlist +$component R25 + R? + SM0603 + SM0805 + R?-* +$endlist +$component C80 + SM* + C? + C1-1 +$endlist +$component C79 + SM* + C? + C1-1 +$endlist +$component C78 + SM* + C? + C1-1 +$endlist $component C75 SM* C? @@ -2009,46 +2143,46 @@ $endfootprintlist Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" U8 1 U1 T5 -Net 2 "/FPGA Spartan6/NF_RE_N" "NF_RE_N" - U1 B16 +Net 2 "/Non volatile memories/NF_RE_N" "NF_RE_N" U5 8 -Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" + U1 B16 +Net 3 "/FPGA Spartan6/NF_CS1_N" "NF_CS1_N" U1 C16 U5 9 -Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE" +Net 4 "/Non volatile memories/NF_ALE" "NF_ALE" U5 17 U1 A15 Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" - U1 D7 U4 15 + U1 D7 Net 6 "/FPGA Spartan6/ETH_RXC" "ETH_RXC" U1 D8 U4 10 Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK" U4 46 U1 A4 -Net 8 "/USB/USBA_SPD" "USBA_SPD" - U1 R19 +Net 8 "/FPGA Spartan6/USBA_SPD" "USBA_SPD" U6 2 + U1 R19 Net 9 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" - U6 9 U1 P18 -Net 10 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" - U6 3 + U6 9 +Net 10 "/USB/USBA_RCV" "USBA_RCV" U1 N16 + U6 3 Net 11 "/USB/USBA_VP" "USBA_VP" - U6 4 U1 P17 -Net 12 "/FPGA Spartan6/USBA_VM" "USBA_VM" + U6 4 +Net 12 "/USB/USBA_VM" "USBA_VM" U1 M18 U6 5 -Net 13 "/Ethernet Phy/ETH_COL" "ETH_COL" +Net 13 "/FPGA Spartan6/ETH_COL" "ETH_COL" U1 B10 U4 21 Net 14 "/Ethernet Phy/ETH_CRS" "ETH_CRS" - U4 22 U1 C10 -Net 15 "/FPGA Spartan6/SD_CLK" "SD_CLK" + U4 22 +Net 15 "/Non volatile memories/SD_CLK" "SD_CLK" J1 5 U1 E16 Net 16 "/FPGA Spartan6/ETH_INT" "ETH_INT" @@ -2059,1084 +2193,1128 @@ Net 17 "/Ethernet Phy/ETH_MDC" "ETH_MDC" U1 D10 Net 18 "/FPGA Spartan6/ETH_MDIO" "ETH_MDIO" U1 C5 - R1 1 U4 1 + R1 1 Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" - U4 48 U1 A5 -Net 20 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" + U4 48 +Net 20 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" U4 9 U1 C7 -Net 21 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" - U1 A7 +Net 21 "/Ethernet Phy/ETH_RXER" "ETH_RXER" U4 11 + U1 A7 Net 22 "/Ethernet Phy/ETH_TXER" "ETH_TXER" - U1 B8 U4 14 -Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" - U1 A8 + U1 B8 +Net 23 "/Ethernet Phy/ETH_TXEN" "ETH_TXEN" U4 16 -Net 24 "/FPGA Spartan6/M1_CS#" "M1_CS#" - U3 24 + U1 A8 +Net 24 "/DDR Banks/M1_CS#" "M1_CS#" R20 2 -Net 25 "/DDR Banks/M1_UDM" "M1_UDM" - U3 47 + U3 24 +Net 25 "/FPGA Spartan6/M1_UDM" "M1_UDM" R18 2 + U3 47 Net 26 "/DDR Banks/M1_LDQS" "M1_LDQS" - U3 16 RP3 8 + U3 16 Net 27 "/FPGA Spartan6/M1_LDM" "M1_LDM" U3 20 RP3 7 Net 28 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" - R19 2 U3 51 + R19 2 Net 29 "/DDR Banks/M0_UDQS" "M0_UDQS" - U2 51 R22 2 -Net 30 "/FPGA Spartan6/M0_LDM" "M0_LDM" + U2 51 +Net 30 "/DDR Banks/M0_LDM" "M0_LDM" U2 20 RP16 7 -Net 31 "/DDR Banks/M1_CAS#" "M1_CAS#" +Net 31 "/FPGA Spartan6/M1_CAS#" "M1_CAS#" RP3 5 U3 22 -Net 32 "/DDR Banks/M1_CKE" "M1_CKE" - R17 2 +Net 32 "/FPGA Spartan6/M1_CKE" "M1_CKE" U3 45 -Net 33 "/DDR Banks/M1_CLK" "M1_CLK" + R17 2 +Net 33 "/FPGA Spartan6/M1_CLK" "M1_CLK" U3 46 U1 H20 R16 2 Net 34 "/DDR Banks/M1_CLK#" "M1_CLK#" - U1 J19 U3 44 + U1 J19 R16 1 Net 35 "GND" "GND" - U4 12 - U2 48 - U1 AA13 - U4 35 - U1 AB22 - C76 2 - U1 AA9 - U1 W19 - U1 R18 - U2 12 - C18 2 - U2 52 - U2 64 - C9 2 - C6 2 - U4 36 - C5 2 - C77 2 - U2 58 - U2 66 - U1 AA17 - U1 AA5 - U1 W16 - U1 B17 - C34 2 - C71 2 - C70 2 - U1 N17 C29 2 - C8 2 + C28 2 + C33 2 + C22 2 + C23 2 + C25 2 + C24 2 + C26 2 + C21 2 C31 2 - C7 2 - U1 D18 - U1 G18 - U4 23 - U1 L18 C30 2 C32 2 C27 2 - C21 2 - C26 2 - C24 2 - C25 2 - C23 2 - U2 34 - C22 2 - C4 2 - C2 2 - C33 2 - C28 2 - U2 24 - C47 2 - C75 1 - C44 2 - C41 2 - C39 2 - U1 J9 - U1 L9 - U1 N9 - U1 K10 - U1 M10 - U1 P10 - U1 V10 - U1 E11 - U1 J11 - C48 2 - C72 2 - C45 2 - C73 2 - C42 2 - C58 2 - C55 2 - C68 2 - U8 4 - C65 2 - C62 2 - C59 2 - C56 2 - C74 2 - C50 2 - C67 2 - U1 J13 - C69 2 - U1 L13 - C54 2 - U1 N13 - C57 2 - U1 K14 - C60 2 - U1 M14 - U1 P14 - U1 V14 - U1 E15 - U1 J15 - U1 E21 - U1 J21 - U1 N21 - U1 U21 - U1 AB1 - U1 K12 - U1 M12 - U1 P12 - U1 A22 - U1 B13 - U1 L11 - U1 N11 - U1 A1 - U1 E2 - U1 J2 - U1 N2 - U1 U2 - U1 D4 - C63 2 - U1 V4 - U1 B5 - U1 G5 - U1 L5 - C66 2 - U1 R5 - U1 E7 - U1 H7 - U1 U7 - U1 W7 - C61 2 - C64 2 - U1 B9 - U5 13 U5 36 + U2 64 + C18 2 C20 2 R12 2 R14 2 + C77 2 + C76 2 U2 6 - J1 CASE - J1 CASE + U8 4 + U5 13 + C75 1 + C74 2 + C73 2 + C34 2 + C72 2 + C71 2 + C70 2 + U2 34 + U2 24 + U2 52 + U2 12 + U2 66 + U1 A22 + U1 P12 + U1 M12 + U1 K12 + U1 AB1 + U1 U21 + U1 N21 + U1 J21 + U1 E21 + U1 N11 + U1 AB22 + U1 AA9 + U1 W19 + U1 R18 + U1 L18 + U1 G18 + U1 D18 + U1 N17 + U1 L11 + U1 J11 + U1 E11 + U1 V10 + U1 P10 + U1 M10 + U1 K10 + U1 N9 + U1 L9 + U1 J9 + U1 B9 + U1 J13 + U1 B13 + C67 2 + C69 2 + C54 2 + C57 2 + C60 2 + C40 2 + C43 2 + C52 2 + C46 2 + C49 2 + C51 2 + C53 2 + C41 2 + C44 2 + C47 2 + C50 2 + C56 2 + C39 2 + C42 2 + C45 2 + C48 2 + C59 2 + C62 2 + C65 2 + C68 2 + C55 2 + C58 2 + C61 2 + C64 2 + C66 2 + C63 2 + U1 W7 + U1 U7 + U1 H7 + U1 E7 + U1 R5 + U1 L5 + U1 G5 + U1 B5 + U1 V4 + U1 D4 + U1 U2 + U1 N2 + U1 J2 + U1 E2 + U1 A1 J1 CASE J1 COM J1 6 - C53 2 - C51 2 - C49 2 - C46 2 - C52 2 - C43 2 - C40 2 - J4 5 - J4 4 - U4 39 - U6 7 - C13 2 - C14 2 + J1 CASE + J1 CASE + U1 E15 + U1 V14 + U1 P14 + U1 M14 + U1 K14 + U1 N13 + U1 L13 + U1 AA17 + U1 AA13 + U1 B17 + U1 W16 + U1 AA5 + U1 J15 + L5 2 + U3 64 + U3 34 + R10 2 + U3 52 + U7 8 + U7 7 + U3 58 + U3 48 + C16 2 + V1 2 + V2 2 C15 2 + C14 2 + C13 2 + U6 7 + U6 8 + L7 2 + C37 2 + C36 2 + C35 2 + U4 39 + U4 23 + U4 44 + U4 35 + U4 36 + U3 66 + U3 12 + U3 6 R15 2 C38 2 V3 2 V4 2 - C37 2 - C36 2 - C35 2 - L5 2 - L7 2 - U3 66 - U3 12 - U3 6 - U3 64 - U3 34 - U3 52 - U3 58 - U3 48 - U7 7 - U7 8 + U10 2 + U10 5 U10 PAD + R25 2 + C80 2 + C78 2 + U12 2 + R27 2 + C85 2 + C81 2 U9 8 U9 PAD - U10 5 - U10 2 - V2 2 - V1 2 - C16 2 - R10 2 - U6 8 - C10 2 + U11 2 + C82 2 + C84 2 + C9 2 + C6 2 + C4 2 + C2 2 + C8 2 + C7 2 + J4 4 + J4 5 C12 2 R9 2 U4 8 + U4 12 + C5 2 + U2 58 + U2 48 C3 2 C1 2 R2 2 C11 2 - U4 44 -Net 36 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" - U1 H3 + C10 2 +Net 36 "/DDR Banks/M0_CLK#" "M0_CLK#" U2 44 + U1 H3 R21 2 Net 37 "/DDR Banks/M0_CLK" "M0_CLK" - U1 H4 - R21 1 U2 46 -Net 38 "/FPGA Spartan6/M0_CKE" "M0_CKE" - U2 45 + R21 1 + U1 H4 +Net 38 "/DDR Banks/M0_CKE" "M0_CKE" R24 2 -Net 39 "/DDR Banks/M0_CAS#" "M0_CAS#" - RP16 5 + U2 45 +Net 39 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" U2 22 + RP16 5 Net 40 "/DDR Banks/M1_WE#" "M1_WE#" - U3 21 RP3 6 + U3 21 Net 41 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" - U3 23 RP2 8 -Net 42 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" + U3 23 +Net 42 "/DDR Banks/M0_RAS#" "M0_RAS#" U2 23 RP15 8 Net 43 "/FPGA Spartan6/M0_WE#" "M0_WE#" - U2 21 RP16 6 + U2 21 Net 44 "/DDR Banks/M0_LDQS" "M0_LDQS" - RP16 8 U2 16 + RP16 8 Net 45 "/FPGA Spartan6/M0_UDM" "M0_UDM" U2 47 R23 2 Net 46 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" - U8 6 U1 AA21 -Net 47 "/FPGA Spartan6/NF_RNB" "NF_RNB" + U8 6 +Net 47 "/Non volatile memories/NF_RNB" "NF_RNB" U5 7 U5 6 U1 A16 -Net 48 "/FPGA Spartan6/NF_WE_N" "NF_WE_N" - U5 18 +Net 48 "/Non volatile memories/NF_WE_N" "NF_WE_N" U1 C15 + U5 18 Net 49 "/FPGA Spartan6/NF_CLE" "NF_CLE" U5 16 U1 D15 -Net 50 "/FPGA Spartan6/SD_CMD" "SD_CMD" - U1 D17 +Net 50 "/Non volatile memories/SD_CMD" "SD_CMD" J1 3 + U1 D17 Net 56 "+2.5V" "+2.5V" - U1 L2 - U1 H15 - U1 K15 - U1 M15 - U1 U11 - U1 G12 - U1 R2 + U3 3 U1 R12 - U1 D16 + C25 1 + U2 9 + U1 U11 + C33 1 + C22 1 + U1 C2 + U1 G12 + C23 1 U1 R10 U1 F11 - U1 C2 - U1 R6 - U1 V6 - U1 G2 - U1 L8 + C24 1 U1 N8 + C26 1 U1 H9 - U1 W21 + C21 1 + C43 1 + C40 1 + C57 1 + C54 1 + U1 J5 U1 L7 - U1 J18 - U1 L21 - U1 U18 - U1 E19 - U1 L16 - U1 N18 - U1 G21 - U1 C21 - U1 R21 - U1 F4 C68 1 - C65 1 - C62 1 - C59 1 - C56 1 - U1 W2 - U1 F6 - U1 U5 + U1 F4 + U2 3 C53 1 C51 1 C49 1 C46 1 C52 1 - C43 1 - C40 1 - U1 N5 - U1 J5 - C77 1 - R13 1 - C32 1 - U2 9 - C27 1 - U2 3 U2 1 - U3 15 - U3 9 - U3 33 - U3 18 - U3 55 - U3 1 - U3 61 - U3 3 - C60 1 - C57 1 - C54 1 - C21 1 - C26 1 - C24 1 - C25 1 - C23 1 - C22 1 - U2 55 - U2 18 + C27 1 + C32 1 + C30 1 + C31 1 + C29 1 + C28 1 + C65 1 + C62 1 + C59 1 + C56 1 + U1 J18 + U1 U18 + U1 E19 + U1 N18 + C37 1 + U1 V6 U2 61 - U2 33 + U2 18 + U1 L8 + U1 C21 + U1 L16 + U1 G21 + U1 L21 + U1 R21 + U1 G2 + U1 W21 + U1 R6 + C17 1 U7 1 - C70 1 - C71 1 - C34 1 - C66 1 - C63 1 + U3 18 C19 1 R11 1 - C29 1 - U6 1 - C31 1 - C15 1 - C37 1 - C30 1 - C17 1 - C28 1 + U3 55 + U3 1 + C60 1 + C63 1 + C66 1 + U2 55 + U3 15 + U3 33 U2 15 - C33 1 + C34 1 + C77 1 + C71 1 + C15 1 + C70 1 + U6 1 + U3 9 + R13 1 + U1 H15 + U3 61 + U1 K15 + U1 M15 + U1 D16 + U2 33 + U1 U5 + U1 F6 + U1 N5 + U1 L2 + U1 W2 + U1 R2 Net 58 "" "" - C19 2 - C20 1 - R14 1 U3 49 R13 2 + C20 1 + C19 2 + R14 1 Net 59 "" "" U2 49 - C18 1 + R11 2 R12 1 C17 2 - R11 2 -Net 98 "+3.3V" "+3.3V" - L2 1 - C5 1 - C3 1 - J1 4 - U4 7 - C1 1 - R1 2 - C11 1 - C10 1 - U4 24 - U1 B7 - J4 11 - U7 14 - C35 1 - U1 B4 - C36 1 - C14 1 - U1 E17 - C13 1 - U6 12 - U6 14 - U1 B15 - U1 G14 - U1 B11 - U1 E13 - U1 B19 - U1 G10 - U1 E9 - R5 1 - U5 19 - R6 1 - U5 12 - R4 1 - R3 1 - U5 37 - U7 12 - C72 1 - J4 3 - C73 1 - J4 6 - J4 9 - C74 1 - C50 1 - C47 1 - C75 2 - C44 1 - C41 1 -Net 99 "VCCO2" "VCCO2" + C18 1 +Net 68 "VCCO2" "VCCO2" + U1 AA15 + U1 W5 + U1 V16 + U1 V8 + U1 T9 + U1 V12 + U1 T13 + U1 AA19 + U1 AA11 + U1 AA7 + C69 1 + C67 1 + C64 1 C61 1 C58 1 - C64 1 - U1 W5 C55 1 - U1 V8 U8 8 - U1 AA15 - U1 V12 - C69 1 - U1 AA19 - U1 T13 - C67 1 - U1 V16 - U1 AA11 U1 AA3 - U1 AA7 - U1 T9 -Net 101 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1" - U1 G1 - RP15 3 -Net 102 "/FPGA Spartan6/R_M0_A2" "R_M0_A2" - RP14 3 - U1 H5 -Net 103 "/FPGA Spartan6/R_M0_A5" "R_M0_A5" - U1 K3 - RP17 3 -Net 104 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" - RP11 2 - U1 P1 -Net 105 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" - RP11 4 - U1 R1 -Net 106 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10" - U1 R3 - RP11 3 -Net 107 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" - U1 N1 - RP13 2 -Net 108 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" - U1 M1 - RP13 4 -Net 109 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" - RP12 1 - U1 J3 -Net 110 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" - U1 K2 - RP12 3 -Net 111 "/FPGA Spartan6/R_M0_A4" "R_M0_A4" +Net 87 "+3.3V" "+3.3V" + C10 1 + C11 1 + U1 B4 + U1 B7 + R26 1 + C80 1 + C79 1 + C81 1 + L8 1 + U4 24 + J4 3 + J4 6 + J4 9 + J4 11 + L2 1 + C5 1 + U4 7 + C3 1 + C1 1 + R1 2 + C14 1 + C13 1 + U7 14 + U7 12 + U6 12 + U6 14 + C36 1 + C35 1 + R3 1 + R4 1 + R6 1 + R5 1 + U1 B15 + U1 G14 + U1 E13 + U1 B11 + U1 G10 + C50 1 + C47 1 + C44 1 + C41 1 + C72 1 + C73 1 + C74 1 + C75 2 + U5 12 + U1 E17 + U5 37 + U1 B19 + U5 19 + J1 4 + U1 E9 +Net 100 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" + RP1 2 + U1 F22 +Net 101 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" + RP1 3 + U1 E22 +Net 103 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" + U1 C22 + RP7 3 +Net 104 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" + RP7 1 + U1 D22 +Net 105 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" + RP6 3 + U1 K20 +Net 109 "/FPGA Spartan6/R_M0_A4" "R_M0_A4" RP17 4 U1 F3 -Net 112 "/FPGA Spartan6/R_M0_A3" "R_M0_A3" +Net 110 "/FPGA Spartan6/R_M0_A3" "R_M0_A3" U1 K6 RP14 4 -Net 113 "/FPGA Spartan6/R_M0_A9" "R_M0_A9" +Net 111 "/FPGA Spartan6/R_M0_A9" "R_M0_A9" U1 E1 RP18 3 -Net 114 "/FPGA Spartan6/R_M0_A11" "R_M0_A11" - U1 C1 +Net 112 "/FPGA Spartan6/R_M0_A11" "R_M0_A11" RP18 2 -Net 115 "/FPGA Spartan6/R_M0_A1" "R_M0_A1" - RP14 2 + U1 C1 +Net 113 "/FPGA Spartan6/R_M0_A1" "R_M0_A1" U1 H1 -Net 138 "+1.2V" "+1.2V" - C76 1 + RP14 2 +Net 114 "/FPGA Spartan6/R_M0_BA1" "R_M0_BA1" + U1 G1 + RP15 3 +Net 115 "/FPGA Spartan6/R_M0_A2" "R_M0_A2" + RP14 3 + U1 H5 +Net 116 "/FPGA Spartan6/R_M0_A5" "R_M0_A5" + U1 K3 + RP17 3 +Net 117 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" + RP10 3 + U1 V2 +Net 118 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" + RP10 1 + U1 U3 +Net 119 "/FPGA Spartan6/R_M0_DQ9" "R_M0_DQ9" + U1 P1 + RP11 2 +Net 120 "/FPGA Spartan6/R_M0_DQ11" "R_M0_DQ11" + RP11 4 + U1 R1 +Net 121 "/FPGA Spartan6/R_M0_DQ10" "R_M0_DQ10" + RP11 3 + U1 R3 +Net 122 "/FPGA Spartan6/R_M0_DQ1" "R_M0_DQ1" + U1 N1 + RP13 2 +Net 167 "+1.2V" "+1.2V" U1 K9 U1 M9 U1 P9 - U1 J10 - U1 L10 - U1 N10 - U1 K11 - U1 M11 - U1 J8 U1 K13 U1 M13 - U1 P13 - U1 J14 + U1 K11 + U1 J10 U1 L14 U1 N14 + U1 L10 + U1 N10 U1 R14 - U1 P11 - U1 J12 - U1 L12 + U1 P13 + U1 J14 U1 N12 - C48 1 - C45 1 - C42 1 + U1 L12 + U1 J12 + U1 P11 + U1 M11 C39 1 -Net 145 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" - U1 J17 + C42 1 + C45 1 + C48 1 + C84 1 + C83 1 + C85 1 + C76 1 + U1 J8 + L9 1 + R28 1 +Net 168 "/FPGA Spartan6/R_M1_BA0" "R_M1_BA0" RP2 2 -Net 156 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" - RP8 1 - U1 V22 -Net 157 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" - U1 U22 - RP8 3 -Net 159 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" - U1 R22 - RP9 1 -Net 160 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" - RP9 3 - U1 P22 -Net 161 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" - U1 N22 - RP5 2 -Net 162 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" - U1 M22 - RP5 4 -Net 164 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" - RP4 4 - U1 K22 -Net 165 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" - U1 J22 - RP4 2 -Net 172 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" - U1 K19 - RP6 2 -Net 173 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" - U1 H19 - RP3 3 -Net 174 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" - RP2 4 - U1 G19 -Net 175 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" - RP7 2 - U1 F19 -Net 183 "/FPGA Spartan6/R_M1_A5" "R_M1_A5" - U1 K20 - RP6 3 -Net 184 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" - U1 J20 - RP4 1 -Net 185 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" - U1 G20 - RP1 4 -Net 187 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" - RP6 1 - U1 E20 -Net 189 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" - RP7 4 - U1 C20 -Net 206 "/FPGA Spartan6/R_M1_A1" "R_M1_A1" - RP1 2 - U1 F22 -Net 207 "/FPGA Spartan6/R_M1_A2" "R_M1_A2" - U1 E22 - RP1 3 -Net 208 "/FPGA Spartan6/R_M1_A12" "R_M1_A12" - U1 D22 - RP7 1 -Net 209 "/FPGA Spartan6/R_M1_A9" "R_M1_A9" - U1 C22 - RP7 3 -Net 211 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" - RP8 2 - U1 V21 -Net 212 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" - U1 P21 - RP9 4 -Net 213 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" - RP5 3 - U1 M21 -Net 214 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" - RP4 3 - U1 K21 -Net 215 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" - RP2 1 - U1 H21 -Net 216 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" - RP1 1 - U1 F21 -Net 221 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" + U1 J17 +Net 169 "/FPGA Spartan6/R_M0_DQ3" "R_M0_DQ3" + U1 M1 + RP13 4 +Net 170 "/FPGA Spartan6/R_M0_DQ4" "R_M0_DQ4" + U1 J3 + RP12 1 +Net 171 "/FPGA Spartan6/R_M0_DQ6" "R_M0_DQ6" + RP12 3 + U1 K2 +Net 172 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" + U1 R20 + RP9 2 +Net 173 "/FPGA Spartan6/R_M1_DQ12" "R_M1_DQ12" RP8 4 U1 U20 -Net 223 "/FPGA Spartan6/R_M1_DQ10" "R_M1_DQ10" - RP9 2 - U1 R20 -Net 225 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" +Net 174 "/FPGA Spartan6/R_M1_DQ2" "R_M1_DQ2" + RP5 3 + U1 M21 +Net 175 "/FPGA Spartan6/R_M1_DQ0" "R_M1_DQ0" U1 N20 RP5 1 -Net 226 "/FPGA Spartan6/R_M0_RAS#" "R_M0_RAS#" - RP15 1 - U1 K5 -Net 227 "/FPGA Spartan6/R_M0_CAS#" "R_M0_CAS#" +Net 180 "/FPGA Spartan6/R_M1_WE#" "R_M1_WE#" + RP3 3 + U1 H19 +Net 196 "/FPGA Spartan6/R_M1_DQ15" "R_M1_DQ15" + RP8 1 + U1 V22 +Net 197 "/FPGA Spartan6/R_M1_DQ13" "R_M1_DQ13" + U1 U22 + RP8 3 +Net 199 "/FPGA Spartan6/R_M1_DQ11" "R_M1_DQ11" + U1 R22 + RP9 1 +Net 200 "/FPGA Spartan6/R_M1_DQ9" "R_M1_DQ9" + RP9 3 + U1 P22 +Net 207 "/FPGA Spartan6/R_M1_A6" "R_M1_A6" + U1 K19 + RP6 2 +Net 208 "/FPGA Spartan6/R_M1_A10" "R_M1_A10" + U1 G19 + RP2 4 +Net 209 "/FPGA Spartan6/R_M1_A11" "R_M1_A11" + U1 F19 + RP7 2 +Net 212 "/FPGA Spartan6/R_M0_CAS#" "R_M0_CAS#" U1 K4 RP16 4 -Net 315 "/FPGA Spartan6/R_M0_A10" "R_M0_A10" - RP15 4 - U1 G4 -Net 320 "/FPGA Spartan6/R_M0_DQ12" "R_M0_DQ12" - U1 U3 - RP10 1 -Net 323 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" - RP13 1 - U1 N3 -Net 324 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0" - RP15 2 - U1 G3 -Net 325 "/FPGA Spartan6/R_M0_A8" "R_M0_A8" - RP18 4 - U1 E3 -Net 330 "/FPGA Spartan6/R_M0_DQ14" "R_M0_DQ14" - U1 V2 - RP10 3 -Net 331 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS" - R22 1 - U1 T2 -Net 334 "/FPGA Spartan6/R_M0_A7" "R_M0_A7" - U1 H6 - RP17 1 -Net 348 "/FPGA Spartan6/R_M0_A6" "R_M0_A6" - RP17 2 - U1 J4 -Net 349 "/FPGA Spartan6/R_M0_A12" "R_M0_A12" - RP18 1 - U1 D1 -Net 368 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" - RP11 1 - U1 P2 -Net 369 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" - U1 M2 - RP13 3 -Net 370 "/FPGA Spartan6/R_M0_A0" "R_M0_A0" - RP14 1 - U1 H2 -Net 375 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" - RP10 4 - U1 V1 -Net 376 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" - U1 U1 - RP10 2 -Net 379 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" - U1 K1 - RP12 4 -Net 380 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" - U1 J1 - RP12 2 -Net 382 "/FPGA Spartan6/R_M0_LDQS" "R_M0_LDQS" - RP16 1 - U1 L3 -Net 383 "/FPGA Spartan6/R_M0_LDM" "R_M0_LDM" - RP16 2 - U1 L4 -Net 384 "/FPGA Spartan6/R_M0_WE#" "R_M0_WE#" - RP16 3 - U1 F2 -Net 385 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" - U1 T21 - R19 1 -Net 386 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" - U1 D21 - R17 1 -Net 387 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" - U1 M20 - R18 1 -Net 388 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" - U1 H16 - R20 1 -Net 389 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" - U1 K17 - RP2 3 -Net 390 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" +Net 213 "/FPGA Spartan6/R_M1_LDQS" "R_M1_LDQS" U1 L20 RP3 1 -Net 391 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" - U1 L19 +Net 214 "/FPGA Spartan6/R_M1_LDM" "R_M1_LDM" RP3 2 -Net 392 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" + U1 L19 +Net 215 "/FPGA Spartan6/R_M1_UDM" "R_M1_UDM" + U1 M20 + R18 1 +Net 244 "/FPGA Spartan6/R_M0_DQ15" "R_M0_DQ15" + U1 V1 + RP10 4 +Net 245 "/FPGA Spartan6/R_M0_DQ13" "R_M0_DQ13" + RP10 2 + U1 U1 +Net 248 "/FPGA Spartan6/R_M0_DQ7" "R_M0_DQ7" + RP12 4 + U1 K1 +Net 249 "/FPGA Spartan6/R_M0_DQ5" "R_M0_DQ5" + RP12 2 + U1 J1 +Net 251 "/FPGA Spartan6/R_M0_A12" "R_M0_A12" + RP18 1 + U1 D1 +Net 311 "/FPGA Spartan6/R_M1_DQ4" "R_M1_DQ4" + U1 J20 + RP4 1 +Net 312 "/FPGA Spartan6/R_M1_A3" "R_M1_A3" + RP1 4 + U1 G20 +Net 314 "/FPGA Spartan6/R_M1_A7" "R_M1_A7" + RP6 1 + U1 E20 +Net 316 "/FPGA Spartan6/R_M1_A8" "R_M1_A8" + RP7 4 + U1 C20 +Net 332 "/FPGA Spartan6/R_M1_DQ1" "R_M1_DQ1" + U1 N22 + RP5 2 +Net 333 "/FPGA Spartan6/R_M1_DQ3" "R_M1_DQ3" + RP5 4 + U1 M22 +Net 335 "/FPGA Spartan6/R_M1_DQ7" "R_M1_DQ7" + U1 K22 + RP4 4 +Net 336 "/FPGA Spartan6/R_M1_DQ5" "R_M1_DQ5" + U1 J22 + RP4 2 +Net 339 "/FPGA Spartan6/R_M1_DQ14" "R_M1_DQ14" + RP8 2 + U1 V21 +Net 340 "/FPGA Spartan6/R_M1_DQ8" "R_M1_DQ8" + U1 P21 + RP9 4 +Net 341 "/FPGA Spartan6/R_M1_DQ6" "R_M1_DQ6" + U1 K21 + RP4 3 +Net 342 "/FPGA Spartan6/R_M1_A0" "R_M1_A0" + U1 F21 + RP1 1 +Net 353 "/FPGA Spartan6/R_M0_DQ0" "R_M0_DQ0" + RP13 1 + U1 N3 +Net 354 "/FPGA Spartan6/R_M0_LDQS" "R_M0_LDQS" + RP16 1 + U1 L3 +Net 355 "/FPGA Spartan6/R_M0_BA0" "R_M0_BA0" + RP15 2 + U1 G3 +Net 356 "/FPGA Spartan6/R_M0_A8" "R_M0_A8" + U1 E3 + RP18 4 +Net 361 "/FPGA Spartan6/R_M0_DQ8" "R_M0_DQ8" + U1 P2 + RP11 1 +Net 362 "/FPGA Spartan6/R_M0_DQ2" "R_M0_DQ2" + U1 M2 + RP13 3 +Net 363 "/FPGA Spartan6/R_M0_A0" "R_M0_A0" + RP14 1 + U1 H2 +Net 367 "/FPGA Spartan6/R_M0_A7" "R_M0_A7" + RP17 1 + U1 H6 +Net 381 "/FPGA Spartan6/R_M0_A6" "R_M0_A6" + RP17 2 + U1 J4 +Net 382 "/FPGA Spartan6/R_M0_A10" "R_M0_A10" + U1 G4 + RP15 4 +Net 383 "/FPGA Spartan6/R_M1_UDQS" "R_M1_UDQS" + U1 T21 + R19 1 +Net 384 "/FPGA Spartan6/R_M1_CKE" "R_M1_CKE" + R17 1 + U1 D21 +Net 385 "/FPGA Spartan6/R_M1_CS#" "R_M1_CS#" + U1 H16 + R20 1 +Net 386 "/FPGA Spartan6/R_M1_BA1" "R_M1_BA1" + RP2 3 + U1 K17 +Net 387 "/FPGA Spartan6/R_M1_RAS#" "R_M1_RAS#" + RP2 1 + U1 H21 +Net 388 "/FPGA Spartan6/R_M1_CAS#" "R_M1_CAS#" U1 H22 RP3 4 -Net 393 "/FPGA Spartan6/R_M0_CKE" "R_M0_CKE" +Net 389 "/FPGA Spartan6/R_M0_UDQS" "R_M0_UDQS" + U1 T2 + R22 1 +Net 390 "/FPGA Spartan6/R_M0_RAS#" "R_M0_RAS#" + RP15 1 + U1 K5 +Net 391 "/FPGA Spartan6/R_M0_CKE" "R_M0_CKE" R24 1 U1 D2 -Net 394 "/FPGA Spartan6/R_M0_UDM" "R_M0_UDM" +Net 392 "/FPGA Spartan6/R_M0_UDM" "R_M0_UDM" R23 1 U1 M3 -Net 396 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" - L3 1 - U4 31 - L1 2 - C6 1 -Net 397 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - L2 2 - C8 1 - C7 1 - U4 38 -Net 398 "" "" +Net 393 "/FPGA Spartan6/R_M0_LDM" "R_M0_LDM" + RP16 2 + U1 L4 +Net 394 "/FPGA Spartan6/R_M0_WE#" "R_M0_WE#" + RP16 3 + U1 F2 +Net 395 "" "" + R4 2 + U4 40 + J4 2 +Net 396 "" "" R2 1 U4 37 -Net 401 "+1.8V" "+1.8V" +Net 397 "" "" + J4 12 + R8 1 +Net 398 "/Ethernet Phy/ETH_LED1" "ETH_LED1" + R8 2 + U4 27 +Net 399 "+1.8V" "+1.8V" U4 13 C2 1 C4 1 L1 1 -Net 404 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" - U4 47 +Net 400 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" L3 2 C9 1 -Net 407 "" "" - C12 1 - R9 1 + U4 47 +Net 401 "/Ethernet Phy/ETH_LED0" "ETH_LED0" + U4 26 + R7 2 +Net 402 "" "" + J4 10 + R7 1 +Net 403 "" "" + R6 2 + J4 8 + U4 32 +Net 404 "" "" J4 14 J4 13 -Net 408 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - R7 2 - U4 26 -Net 409 "" "" + R9 1 + C12 1 +Net 405 "" "" + J4 7 + U4 33 + R5 2 +Net 406 "" "" + U4 41 J4 1 R3 2 - U4 41 -Net 410 "" "" - R5 2 - U4 33 - J4 7 -Net 411 "" "" - J4 12 - R8 1 -Net 412 "" "" - U4 32 - J4 8 - R6 2 -Net 413 "" "" - R4 2 - U4 40 - J4 2 -Net 414 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - R8 2 - U4 27 -Net 415 "" "" - R7 1 - J4 10 -Net 418 "" "" - L6 1 - F2 1 -Net 419 "+5V" "+5V" - F2 2 - F1 2 -Net 420 "" "" - C38 1 - R15 1 +Net 412 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + U4 31 + L3 1 + C6 1 + L1 2 +Net 415 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" + C7 1 + C8 1 + L2 2 + U4 38 Net 422 "" "" - L5 1 - J5 4 -Net 423 "" "" - J5 S4 - J5 S1 - R10 1 - J5 S2 - C16 1 - J5 S3 + F2 1 + L6 1 Net 424 "" "" - F1 1 - L4 1 + C16 1 + J5 S1 + J5 S2 + J5 S3 + J5 S4 + R10 1 Net 425 "" "" - J5 1 - L4 2 + J5 4 + L5 1 Net 426 "" "" + U6 10 J5 2 V2 1 V2 1 - U6 10 Net 427 "" "" + J5 1 + L4 2 +Net 428 "+5V" "+5V" + F2 2 + F1 2 +Net 429 "" "" + L4 1 + F1 1 +Net 430 "" "" U6 11 J5 3 V1 1 V1 1 +Net 431 "" "" + U7 10 + V4 1 + V4 1 Net 432 "" "" U7 11 V3 1 V3 1 Net 433 "" "" - V4 1 - V4 1 - U7 10 -Net 461 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" + C38 1 + R15 1 +Net 434 "" "" + C82 1 + U12 1 + U12 4 +Net 435 "" "" + C83 2 + R28 2 + U12 5 + R27 1 +Net 436 "" "" + U11 1 + U11 4 + C78 1 +Net 437 "" "" + R25 1 + U11 5 + R26 2 + C79 2 +Net 447 "" "" + U11 3 + L8 2 +Net 466 "" "" + L9 2 + U12 3 +Net 467 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" U1 U13 U8 7 -Net 462 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" +Net 468 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" U1 U14 U8 3 -Net 463 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" +Net 469 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" U1 AA20 U8 2 -Net 464 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" - U8 5 +Net 470 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" U1 AB20 -Net 465 "/FPGA Spartan6/NF_D7" "NF_D7" - U1 A11 + U8 5 +Net 471 "/FPGA Spartan6/NF_D7" "NF_D7" U5 44 -Net 466 "/FPGA Spartan6/NF_D6" "NF_D6" - U5 43 + U1 A11 +Net 472 "/Non volatile memories/NF_D6" "NF_D6" U1 D11 -Net 467 "/Non volatile memories/NF_D5" "NF_D5" - U5 42 + U5 43 +Net 473 "/FPGA Spartan6/NF_D5" "NF_D5" U1 C12 -Net 468 "/FPGA Spartan6/NF_D4" "NF_D4" - U5 41 + U5 42 +Net 474 "/Non volatile memories/NF_D4" "NF_D4" U1 B12 -Net 469 "/FPGA Spartan6/NF_D3" "NF_D3" - U1 A12 + U5 41 +Net 475 "/Non volatile memories/NF_D3" "NF_D3" U5 32 -Net 470 "/Non volatile memories/NF_D2" "NF_D2" - U1 C13 + U1 A12 +Net 476 "/Non volatile memories/NF_D2" "NF_D2" U5 31 -Net 471 "/FPGA Spartan6/NF_D1" "NF_D1" - U5 30 + U1 C13 +Net 477 "/FPGA Spartan6/NF_D1" "NF_D1" U1 A13 -Net 472 "/FPGA Spartan6/NF_D0" "NF_D0" - U5 29 + U5 30 +Net 478 "/FPGA Spartan6/NF_D0" "NF_D0" U1 D14 -Net 473 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" + U5 29 +Net 479 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" U4 20 U1 A9 -Net 474 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" +Net 480 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" U4 19 U1 C9 -Net 475 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" - U4 18 +Net 481 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" U1 C8 -Net 476 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" + U4 18 +Net 482 "/FPGA Spartan6/ETH_TXD0" "ETH_TXD0" U4 17 U1 D9 -Net 477 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" - U1 D6 +Net 483 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" U4 3 -Net 478 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" - U1 C6 + U1 D6 +Net 484 "/Ethernet Phy/ETH_RXD2" "ETH_RXD2" U4 4 -Net 479 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" + U1 C6 +Net 485 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" U1 B6 U4 5 -Net 480 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" +Net 486 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" U1 A6 U4 6 -Net 481 "/FPGA Spartan6/M0_BA1" "M0_BA1" - RP15 6 +Net 487 "/FPGA Spartan6/M0_BA1" "M0_BA1" U2 27 -Net 482 "/FPGA Spartan6/M0_BA0" "M0_BA0" - RP15 7 + RP15 6 +Net 488 "/FPGA Spartan6/M0_BA0" "M0_BA0" U2 26 -Net 483 "/DDR Banks/M1_BA1" "M1_BA1" - RP2 6 + RP15 7 +Net 489 "/DDR Banks/M1_BA1" "M1_BA1" U3 27 -Net 484 "/DDR Banks/M1_BA0" "M1_BA0" - U3 26 + RP2 6 +Net 490 "/DDR Banks/M1_BA0" "M1_BA0" RP2 7 -Net 485 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" - RP8 8 + U3 26 +Net 491 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" U3 65 -Net 486 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" + RP8 8 +Net 492 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" RP8 7 U3 63 -Net 487 "/DDR Banks/M1_DQ13" "M1_DQ13" - U3 62 +Net 493 "/DDR Banks/M1_DQ13" "M1_DQ13" RP8 6 -Net 488 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" - RP8 5 + U3 62 +Net 494 "/DDR Banks/M1_DQ12" "M1_DQ12" U3 60 -Net 489 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" + RP8 5 +Net 495 "/DDR Banks/M1_DQ11" "M1_DQ11" RP9 8 U3 59 -Net 490 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" +Net 496 "/DDR Banks/M1_DQ10" "M1_DQ10" U3 57 RP9 7 -Net 491 "/Non volatile memories/SD_DAT3" "SD_DAT3" +Net 497 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" U1 C17 J1 2 -Net 492 "/Non volatile memories/SD_DAT2" "SD_DAT2" - U1 A17 +Net 498 "/Non volatile memories/SD_DAT2" "SD_DAT2" J1 1 -Net 493 "/FPGA Spartan6/SD_DAT1" "SD_DAT1" - J1 8 + U1 A17 +Net 499 "/Non volatile memories/SD_DAT1" "SD_DAT1" U1 B18 -Net 494 "/Non volatile memories/SD_DAT0" "SD_DAT0" + J1 8 +Net 500 "/Non volatile memories/SD_DAT0" "SD_DAT0" U1 A18 J1 7 -Net 495 "/DDR Banks/M1_A7" "M1_A7" +Net 501 "/FPGA Spartan6/M1_A7" "M1_A7" RP6 8 U3 38 -Net 496 "/FPGA Spartan6/M1_A6" "M1_A6" - U3 37 +Net 502 "/DDR Banks/M1_A6" "M1_A6" RP6 7 -Net 497 "/FPGA Spartan6/M1_A5" "M1_A5" + U3 37 +Net 503 "/FPGA Spartan6/M1_A5" "M1_A5" U3 36 RP6 6 -Net 498 "/DDR Banks/M1_A4" "M1_A4" - RP6 5 +Net 504 "/FPGA Spartan6/M1_A4" "M1_A4" U3 35 -Net 499 "/FPGA Spartan6/M1_A3" "M1_A3" + RP6 5 +Net 505 "/FPGA Spartan6/M1_A3" "M1_A3" U3 32 RP1 5 -Net 500 "/DDR Banks/M1_A2" "M1_A2" - RP1 6 +Net 506 "/FPGA Spartan6/M1_A2" "M1_A2" U3 31 -Net 501 "/FPGA Spartan6/M1_A1" "M1_A1" - U3 30 + RP1 6 +Net 507 "/FPGA Spartan6/M1_A1" "M1_A1" RP1 7 -Net 502 "/FPGA Spartan6/M1_A0" "M1_A0" - RP1 8 + U3 30 +Net 508 "/FPGA Spartan6/M1_A0" "M1_A0" U3 29 -Net 503 "/DDR Banks/M0_A12" "M0_A12" + RP1 8 +Net 509 "/FPGA Spartan6/M0_A12" "M0_A12" U2 42 RP18 8 -Net 504 "/DDR Banks/M0_A11" "M0_A11" - RP18 7 +Net 510 "/FPGA Spartan6/M0_A11" "M0_A11" U2 41 -Net 505 "/FPGA Spartan6/M0_A10" "M0_A10" + RP18 7 +Net 511 "/FPGA Spartan6/M0_A10" "M0_A10" U2 28 RP15 5 -Net 506 "/DDR Banks/M0_A9" "M0_A9" +Net 512 "/FPGA Spartan6/M0_A9" "M0_A9" RP18 6 U2 40 -Net 507 "/FPGA Spartan6/M0_A8" "M0_A8" +Net 513 "/FPGA Spartan6/M0_A8" "M0_A8" RP18 5 U2 39 -Net 508 "/FPGA Spartan6/M0_A7" "M0_A7" - U2 38 +Net 514 "/FPGA Spartan6/M0_A7" "M0_A7" RP17 8 -Net 509 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" + U2 38 +Net 515 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" RP9 6 U3 56 -Net 510 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" - RP9 5 +Net 516 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" U3 54 -Net 511 "/DDR Banks/M1_DQ7" "M1_DQ7" - U3 13 + RP9 5 +Net 517 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" RP4 5 -Net 512 "/DDR Banks/M1_DQ6" "M1_DQ6" + U3 13 +Net 518 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" U3 11 RP4 6 -Net 513 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" - RP4 7 +Net 519 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" U3 10 -Net 514 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" + RP4 7 +Net 520 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" U3 8 RP4 8 -Net 515 "/DDR Banks/M1_DQ3" "M1_DQ3" - RP5 5 +Net 521 "/DDR Banks/M1_DQ3" "M1_DQ3" U3 7 -Net 516 "/DDR Banks/M1_DQ2" "M1_DQ2" + RP5 5 +Net 522 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" U3 5 RP5 6 -Net 517 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" +Net 523 "/DDR Banks/M1_DQ1" "M1_DQ1" U3 4 RP5 7 -Net 518 "/DDR Banks/M1_DQ0" "M1_DQ0" +Net 524 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" RP5 8 U3 2 -Net 519 "/FPGA Spartan6/M1_A12" "M1_A12" +Net 525 "/DDR Banks/M1_A12" "M1_A12" RP7 8 U3 42 -Net 520 "/FPGA Spartan6/M1_A11" "M1_A11" - U3 41 +Net 526 "/FPGA Spartan6/M1_A11" "M1_A11" RP7 7 -Net 521 "/DDR Banks/M1_A10" "M1_A10" + U3 41 +Net 527 "/DDR Banks/M1_A10" "M1_A10" RP2 5 U3 28 -Net 522 "/DDR Banks/M1_A9" "M1_A9" +Net 528 "/FPGA Spartan6/M1_A9" "M1_A9" RP7 6 U3 40 -Net 523 "/DDR Banks/M1_A8" "M1_A8" - RP7 5 +Net 529 "/DDR Banks/M1_A8" "M1_A8" U3 39 -Net 524 "/DDR Banks/M0_DQ3" "M0_DQ3" - RP13 5 + RP7 5 +Net 530 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" U2 7 -Net 525 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" + RP13 5 +Net 531 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" RP13 6 U2 5 -Net 526 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" +Net 532 "/DDR Banks/M0_DQ1" "M0_DQ1" RP13 7 U2 4 -Net 527 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" - RP13 8 +Net 533 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" U2 2 -Net 528 "/DDR Banks/M0_A6" "M0_A6" + RP13 8 +Net 534 "/FPGA Spartan6/M0_A6" "M0_A6" RP17 7 U2 37 -Net 529 "/FPGA Spartan6/M0_A5" "M0_A5" +Net 535 "/FPGA Spartan6/M0_A5" "M0_A5" U2 36 RP17 6 -Net 530 "/FPGA Spartan6/M0_A4" "M0_A4" - U2 35 +Net 536 "/FPGA Spartan6/M0_A4" "M0_A4" RP17 5 -Net 531 "/FPGA Spartan6/M0_A3" "M0_A3" + U2 35 +Net 537 "/FPGA Spartan6/M0_A3" "M0_A3" U2 32 RP14 5 -Net 532 "/DDR Banks/M0_A2" "M0_A2" - U2 31 +Net 538 "/FPGA Spartan6/M0_A2" "M0_A2" RP14 6 -Net 533 "/FPGA Spartan6/M0_A1" "M0_A1" + U2 31 +Net 539 "/FPGA Spartan6/M0_A1" "M0_A1" RP14 7 U2 30 -Net 534 "/FPGA Spartan6/M0_A0" "M0_A0" - RP14 8 +Net 540 "/DDR Banks/M0_A0" "M0_A0" U2 29 -Net 535 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" + RP14 8 +Net 541 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" RP10 5 U2 65 -Net 536 "/DDR Banks/M0_DQ14" "M0_DQ14" +Net 542 "/DDR Banks/M0_DQ14" "M0_DQ14" U2 63 RP10 6 -Net 537 "/FPGA Spartan6/M0_DQ13" "M0_DQ13" - RP10 7 +Net 543 "/DDR Banks/M0_DQ13" "M0_DQ13" U2 62 -Net 538 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" + RP10 7 +Net 544 "/DDR Banks/M0_DQ12" "M0_DQ12" RP10 8 U2 60 -Net 539 "/DDR Banks/M0_DQ11" "M0_DQ11" - RP11 5 +Net 545 "/DDR Banks/M0_DQ11" "M0_DQ11" U2 59 -Net 540 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" + RP11 5 +Net 546 "/DDR Banks/M0_DQ10" "M0_DQ10" RP11 6 U2 57 -Net 541 "/DDR Banks/M0_DQ9" "M0_DQ9" +Net 547 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" RP11 7 U2 56 -Net 542 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" +Net 548 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" U2 54 RP11 8 -Net 543 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" - RP12 5 +Net 549 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" U2 13 -Net 544 "/DDR Banks/M0_DQ6" "M0_DQ6" + RP12 5 +Net 550 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" U2 11 RP12 6 -Net 545 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" +Net 551 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" RP12 7 U2 10 -Net 546 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" - RP12 8 +Net 552 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" U2 8 + RP12 8 } #End diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index d7b8dd8..af79a14 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Thu 19 Aug 2010 05:38:44 AM COT +update=Thu 19 Aug 2010 08:41:55 AM COT version=1 last_client=pcbnew [common] diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index 99f01ac..63d0d11 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Wed 18 Aug 2010 10:06:32 PM COT +EESchema Schematic File Version 2 date Thu 19 Aug 2010 08:32:00 AM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03