From fae8765d04c89be1cc0b6edf121c488fdf855978 Mon Sep 17 00:00:00 2001 From: Andres Calderon Date: Fri, 13 Aug 2010 22:09:52 -0500 Subject: [PATCH] improved placement --- kicad/xue-rnc/DRAM.sch | 4 +- kicad/xue-rnc/FPGA.sch | 76 +- kicad/xue-rnc/NV_MEMORIES.sch | 4 +- kicad/xue-rnc/USB.sch | 4 +- kicad/xue-rnc/eth_phy.sch | 4 +- kicad/xue-rnc/xue-rnc-cache.lib | 2 +- kicad/xue-rnc/xue-rnc.brd | 1422 ++++++++++++++++--------------- kicad/xue-rnc/xue-rnc.net | 1292 ++++++++++++++-------------- kicad/xue-rnc/xue-rnc.pro | 8 +- kicad/xue-rnc/xue-rnc.sch | 4 +- 10 files changed, 1423 insertions(+), 1397 deletions(-) diff --git a/kicad/xue-rnc/DRAM.sch b/kicad/xue-rnc/DRAM.sch index f2fc2f9..df37911 100644 --- a/kicad/xue-rnc/DRAM.sch +++ b/kicad/xue-rnc/DRAM.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:37:07 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -48,7 +48,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 6 6 Title "" -Date "13 aug 2010" +Date "14 aug 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/FPGA.sch b/kicad/xue-rnc/FPGA.sch index c3442d3..44d586f 100644 --- a/kicad/xue-rnc/FPGA.sch +++ b/kicad/xue-rnc/FPGA.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:37:07 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -48,7 +48,7 @@ EELAYER END $Descr A2 23400 16535 Sheet 4 6 Title "" -Date "13 aug 2010" +Date "14 aug 2010" Rev "" Comp "" Comment1 "" @@ -56,39 +56,8 @@ Comment2 "" Comment3 "" Comment4 "" $EndDescr -$Comp -L +3.3V #PWR28 -U 1 1 4C65CF66 -P 1650 14300 -F 0 "#PWR28" H 1650 14260 30 0001 C CNN -F 1 "+3.3V" H 1650 14410 30 0000 C CNN - 1 1650 14300 - 1 0 0 -1 -$EndComp -$Comp -L +2.5V #PWR33 -U 1 1 4C65C84B -P 4600 14300 -F 0 "#PWR33" H 4600 14250 20 0001 C CNN -F 1 "+2.5V" H 4600 14400 30 0000 C CNN - 1 4600 14300 - 1 0 0 -1 -$EndComp -$Comp -L +2.5V #PWR30 -U 1 1 4C65C837 -P 4600 12350 -F 0 "#PWR30" H 4600 12300 20 0001 C CNN -F 1 "+2.5V" H 4600 12450 30 0000 C CNN - 1 4600 12350 - 1 0 0 -1 -$EndComp -Text GLabel 4600 13350 1 30 BiDi ~ 0 -VCCO2 -Text Label 2200 7800 2 60 ~ 0 -PROG_MISO3 -Text Label 2200 7700 2 60 ~ 0 -PROG_MISO2 +Wire Wire Line + 16400 12400 16400 12650 Wire Wire Line 1650 7800 2250 7800 Wire Wire Line @@ -464,8 +433,6 @@ Wire Wire Line Connection ~ 16250 6200 Wire Wire Line 16250 6200 16250 6250 -Wire Wire Line - 16400 12650 16400 12500 Wire Wire Line 16000 600 16000 750 Connection ~ 16300 700 @@ -1145,6 +1112,41 @@ Wire Wire Line 1650 7600 2250 7600 Wire Wire Line 1650 7500 2250 7500 +Wire Wire Line + 15900 12400 15900 12500 +$Comp +L +3.3V #PWR28 +U 1 1 4C65CF66 +P 1650 14300 +F 0 "#PWR28" H 1650 14260 30 0001 C CNN +F 1 "+3.3V" H 1650 14410 30 0000 C CNN + 1 1650 14300 + 1 0 0 -1 +$EndComp +$Comp +L +2.5V #PWR33 +U 1 1 4C65C84B +P 4600 14300 +F 0 "#PWR33" H 4600 14250 20 0001 C CNN +F 1 "+2.5V" H 4600 14400 30 0000 C CNN + 1 4600 14300 + 1 0 0 -1 +$EndComp +$Comp +L +2.5V #PWR30 +U 1 1 4C65C837 +P 4600 12350 +F 0 "#PWR30" H 4600 12300 20 0001 C CNN +F 1 "+2.5V" H 4600 12450 30 0000 C CNN + 1 4600 12350 + 1 0 0 -1 +$EndComp +Text GLabel 4600 13350 1 30 BiDi ~ 0 +VCCO2 +Text Label 2200 7800 2 60 ~ 0 +PROG_MISO3 +Text Label 2200 7700 2 60 ~ 0 +PROG_MISO2 Entry Wire Line 1550 7700 1650 7800 Entry Wire Line diff --git a/kicad/xue-rnc/NV_MEMORIES.sch b/kicad/xue-rnc/NV_MEMORIES.sch index a710eeb..dfe9ebc 100644 --- a/kicad/xue-rnc/NV_MEMORIES.sch +++ b/kicad/xue-rnc/NV_MEMORIES.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:37:07 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -48,7 +48,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 2 6 Title "" -Date "13 aug 2010" +Date "14 aug 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/USB.sch b/kicad/xue-rnc/USB.sch index 68390f9..9f66fdf 100644 --- a/kicad/xue-rnc/USB.sch +++ b/kicad/xue-rnc/USB.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:37:07 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -48,7 +48,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 2 6 Title "" -Date "13 aug 2010" +Date "14 aug 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/eth_phy.sch b/kicad/xue-rnc/eth_phy.sch index 96984c8..41173b8 100644 --- a/kicad/xue-rnc/eth_phy.sch +++ b/kicad/xue-rnc/eth_phy.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:37:07 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -48,7 +48,7 @@ EELAYER END $Descr A4 11700 8267 Sheet 4 6 Title "" -Date "13 aug 2010" +Date "14 aug 2010" Rev "" Comp "" Comment1 "" diff --git a/kicad/xue-rnc/xue-rnc-cache.lib b/kicad/xue-rnc/xue-rnc-cache.lib index e09baec..6ddd2ab 100644 --- a/kicad/xue-rnc/xue-rnc-cache.lib +++ b/kicad/xue-rnc/xue-rnc-cache.lib @@ -1,4 +1,4 @@ -EESchema-LIBRARY Version 2.3 Date: Fri 13 Aug 2010 06:37:07 PM COT +EESchema-LIBRARY Version 2.3 Date: Fri 13 Aug 2010 07:13:52 PM COT # # +1.2V # diff --git a/kicad/xue-rnc/xue-rnc.brd b/kicad/xue-rnc/xue-rnc.brd index 79c1dcd..c3a5674 100644 --- a/kicad/xue-rnc/xue-rnc.brd +++ b/kicad/xue-rnc/xue-rnc.brd @@ -1,4 +1,4 @@ -PCBNEW-BOARD Version 1 date Fri 13 Aug 2010 06:38:04 PM COT +PCBNEW-BOARD Version 1 date Fri 13 Aug 2010 07:16:05 PM COT # Created by Pcbnew(2010-07-15 BZR 2414)-unstable @@ -6,10 +6,10 @@ $GENERAL LayerCount 6 Ly 1FFF801F EnabledLayers 1FFF801F -Links 536 -NoConn 536 +Links 538 +NoConn 538 Di 40724 13449 70210 50403 -Ndraw 2 +Ndraw 4 Ntrack 0 Nzone 0 BoardThickness 630 @@ -20,7 +20,7 @@ $EndGENERAL $SHEETDESCR Sheet A4 11700 8267 Title "" -Date "13 aug 2010" +Date "14 aug 2010" Rev "" Comp "" Comment1 "" @@ -59,8 +59,8 @@ TextPcbSize 600 800 EdgeModWidth 150 TextModSize 600 600 TextModWidth 120 -PadSize 600 600 -PadDrill 320 +PadSize 157 157 +PadDrill 0 Pad2MaskClearance 100 AuxiliaryAxisOrg 0 0 $EndSETUP @@ -86,303 +86,303 @@ Na 4 "+5V" St ~ $EndEQUIPOT $EQUIPOT -Na 5 "/DDR_Banks/M0_A3" +Na 5 "/DDR_Banks/M0_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 6 "/DDR_Banks/M0_A5" +Na 6 "/DDR_Banks/M0_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 7 "/DDR_Banks/M0_BA1" +Na 7 "/DDR_Banks/M0_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 8 "/DDR_Banks/M0_DQ13" +Na 8 "/DDR_Banks/M0_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 9 "/DDR_Banks/M0_LDM" +Na 9 "/DDR_Banks/M0_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 10 "/DDR_Banks/M0_LDQS" +Na 10 "/DDR_Banks/M0_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 11 "/DDR_Banks/M0_UDM" +Na 11 "/DDR_Banks/M0_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 12 "/DDR_Banks/M0_UDQS" +Na 12 "/DDR_Banks/M0_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 13 "/DDR_Banks/M1_A0" +Na 13 "/DDR_Banks/M0_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 14 "/DDR_Banks/M1_A1" +Na 14 "/DDR_Banks/M0_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 15 "/DDR_Banks/M1_A10" +Na 15 "/DDR_Banks/M0_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 16 "/DDR_Banks/M1_A12" +Na 16 "/DDR_Banks/M0_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 17 "/DDR_Banks/M1_A5" +Na 17 "/DDR_Banks/M0_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 18 "/DDR_Banks/M1_BA1" +Na 18 "/DDR_Banks/M0_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 19 "/DDR_Banks/M1_CLK#" +Na 19 "/DDR_Banks/M0_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 20 "/DDR_Banks/M1_DQ1" +Na 20 "/DDR_Banks/M0_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 21 "/DDR_Banks/M1_DQ12" +Na 21 "/DDR_Banks/M0_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 22 "/DDR_Banks/M1_DQ15" +Na 22 "/DDR_Banks/M0_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 23 "/DDR_Banks/M1_DQ3" +Na 23 "/DDR_Banks/M0_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 24 "/DDR_Banks/M1_DQ6" +Na 24 "/DDR_Banks/M1_A0" St ~ $EndEQUIPOT $EQUIPOT -Na 25 "/DDR_Banks/M1_DQ7" +Na 25 "/DDR_Banks/M1_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 26 "/DDR_Banks/M1_DQ9" +Na 26 "/DDR_Banks/M1_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 27 "/DDR_Banks/M1_LDQS" +Na 27 "/DDR_Banks/M1_BA1" St ~ $EndEQUIPOT $EQUIPOT -Na 28 "/DDR_Banks/M1_WE#" +Na 28 "/DDR_Banks/M1_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 29 "/Ethernet_Phy/ETH_1.8V" +Na 29 "/DDR_Banks/M1_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 30 "/Ethernet_Phy/ETH_A1.8V" +Na 30 "/DDR_Banks/M1_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 31 "/Ethernet_Phy/ETH_A3.3V" +Na 31 "/DDR_Banks/M1_DQ4" St ~ $EndEQUIPOT $EQUIPOT -Na 32 "/Ethernet_Phy/ETH_INT" +Na 32 "/DDR_Banks/M1_LDM" St ~ $EndEQUIPOT $EQUIPOT -Na 33 "/Ethernet_Phy/ETH_LED0" +Na 33 "/DDR_Banks/M1_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 34 "/Ethernet_Phy/ETH_LED1" +Na 34 "/Ethernet_Phy/ETH_1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 35 "/Ethernet_Phy/ETH_MDIO" +Na 35 "/Ethernet_Phy/ETH_A1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 36 "/Ethernet_Phy/ETH_PLL1.8V" +Na 36 "/Ethernet_Phy/ETH_A3.3V" St ~ $EndEQUIPOT $EQUIPOT -Na 37 "/Ethernet_Phy/ETH_RXD0" +Na 37 "/Ethernet_Phy/ETH_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 38 "/Ethernet_Phy/ETH_RXD1" +Na 38 "/Ethernet_Phy/ETH_COL" St ~ $EndEQUIPOT $EQUIPOT -Na 39 "/Ethernet_Phy/ETH_RXD3" +Na 39 "/Ethernet_Phy/ETH_INT" St ~ $EndEQUIPOT $EQUIPOT -Na 40 "/Ethernet_Phy/ETH_TXD0" +Na 40 "/Ethernet_Phy/ETH_LED0" St ~ $EndEQUIPOT $EQUIPOT -Na 41 "/Ethernet_Phy/ETH_TXD1" +Na 41 "/Ethernet_Phy/ETH_LED1" St ~ $EndEQUIPOT $EQUIPOT -Na 42 "/Ethernet_Phy/ETH_TXD2" +Na 42 "/Ethernet_Phy/ETH_MDIO" St ~ $EndEQUIPOT $EQUIPOT -Na 43 "/FPGA_Spartan6/ETH_CLK" +Na 43 "/Ethernet_Phy/ETH_PLL1.8V" St ~ $EndEQUIPOT $EQUIPOT -Na 44 "/FPGA_Spartan6/ETH_COL" +Na 44 "/Ethernet_Phy/ETH_RXC" St ~ $EndEQUIPOT $EQUIPOT -Na 45 "/FPGA_Spartan6/ETH_CRS" +Na 45 "/Ethernet_Phy/ETH_RXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 46 "/FPGA_Spartan6/ETH_MDC" +Na 46 "/Ethernet_Phy/ETH_RXDV" St ~ $EndEQUIPOT $EQUIPOT -Na 47 "/FPGA_Spartan6/ETH_RESET_N" +Na 47 "/Ethernet_Phy/ETH_RXER" St ~ $EndEQUIPOT $EQUIPOT -Na 48 "/FPGA_Spartan6/ETH_RXC" +Na 48 "/Ethernet_Phy/ETH_TXC" St ~ $EndEQUIPOT $EQUIPOT -Na 49 "/FPGA_Spartan6/ETH_RXD2" +Na 49 "/Ethernet_Phy/ETH_TXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 50 "/FPGA_Spartan6/ETH_RXDV" +Na 50 "/Ethernet_Phy/ETH_TXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 51 "/FPGA_Spartan6/ETH_RXER" +Na 51 "/Ethernet_Phy/ETH_TXER" St ~ $EndEQUIPOT $EQUIPOT -Na 52 "/FPGA_Spartan6/ETH_TXC" +Na 52 "/FPGA_Spartan6/ETH_CRS" St ~ $EndEQUIPOT $EQUIPOT -Na 53 "/FPGA_Spartan6/ETH_TXD3" +Na 53 "/FPGA_Spartan6/ETH_MDC" St ~ $EndEQUIPOT $EQUIPOT -Na 54 "/FPGA_Spartan6/ETH_TXEN" +Na 54 "/FPGA_Spartan6/ETH_RESET_N" St ~ $EndEQUIPOT $EQUIPOT -Na 55 "/FPGA_Spartan6/ETH_TXER" +Na 55 "/FPGA_Spartan6/ETH_RXD0" St ~ $EndEQUIPOT $EQUIPOT -Na 56 "/FPGA_Spartan6/M0_A0" +Na 56 "/FPGA_Spartan6/ETH_RXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 57 "/FPGA_Spartan6/M0_A1" +Na 57 "/FPGA_Spartan6/ETH_RXD3" St ~ $EndEQUIPOT $EQUIPOT -Na 58 "/FPGA_Spartan6/M0_A10" +Na 58 "/FPGA_Spartan6/ETH_TXD1" St ~ $EndEQUIPOT $EQUIPOT -Na 59 "/FPGA_Spartan6/M0_A11" +Na 59 "/FPGA_Spartan6/ETH_TXD2" St ~ $EndEQUIPOT $EQUIPOT -Na 60 "/FPGA_Spartan6/M0_A12" +Na 60 "/FPGA_Spartan6/ETH_TXEN" St ~ $EndEQUIPOT $EQUIPOT -Na 61 "/FPGA_Spartan6/M0_A2" +Na 61 "/FPGA_Spartan6/M0_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 62 "/FPGA_Spartan6/M0_A4" +Na 62 "/FPGA_Spartan6/M0_A12" St ~ $EndEQUIPOT $EQUIPOT -Na 63 "/FPGA_Spartan6/M0_A6" +Na 63 "/FPGA_Spartan6/M0_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 64 "/FPGA_Spartan6/M0_A7" +Na 64 "/FPGA_Spartan6/M0_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 65 "/FPGA_Spartan6/M0_A8" +Na 65 "/FPGA_Spartan6/M0_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 66 "/FPGA_Spartan6/M0_A9" +Na 66 "/FPGA_Spartan6/M0_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 67 "/FPGA_Spartan6/M0_BA0" +Na 67 "/FPGA_Spartan6/M0_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 68 "/FPGA_Spartan6/M0_CAS#" +Na 68 "/FPGA_Spartan6/M0_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 69 "/FPGA_Spartan6/M0_CKE" +Na 69 "/FPGA_Spartan6/M0_BA0" St ~ $EndEQUIPOT $EQUIPOT -Na 70 "/FPGA_Spartan6/M0_CLK" +Na 70 "/FPGA_Spartan6/M0_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 71 "/FPGA_Spartan6/M0_CLK#" +Na 71 "/FPGA_Spartan6/M0_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 72 "/FPGA_Spartan6/M0_DQ0" +Na 72 "/FPGA_Spartan6/M0_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 73 "/FPGA_Spartan6/M0_DQ1" +Na 73 "/FPGA_Spartan6/M0_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 74 "/FPGA_Spartan6/M0_DQ10" +Na 74 "/FPGA_Spartan6/M0_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 75 "/FPGA_Spartan6/M0_DQ11" +Na 75 "/FPGA_Spartan6/M0_DQ10" St ~ $EndEQUIPOT $EQUIPOT -Na 76 "/FPGA_Spartan6/M0_DQ12" +Na 76 "/FPGA_Spartan6/M0_DQ11" St ~ $EndEQUIPOT $EQUIPOT -Na 77 "/FPGA_Spartan6/M0_DQ14" +Na 77 "/FPGA_Spartan6/M0_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 78 "/FPGA_Spartan6/M0_DQ15" +Na 78 "/FPGA_Spartan6/M0_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 79 "/FPGA_Spartan6/M0_DQ2" +Na 79 "/FPGA_Spartan6/M0_DQ15" St ~ $EndEQUIPOT $EQUIPOT @@ -390,147 +390,147 @@ Na 80 "/FPGA_Spartan6/M0_DQ3" St ~ $EndEQUIPOT $EQUIPOT -Na 81 "/FPGA_Spartan6/M0_DQ4" +Na 81 "/FPGA_Spartan6/M0_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 82 "/FPGA_Spartan6/M0_DQ5" +Na 82 "/FPGA_Spartan6/M0_RAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 83 "/FPGA_Spartan6/M0_DQ6" +Na 83 "/FPGA_Spartan6/M1_A1" St ~ $EndEQUIPOT $EQUIPOT -Na 84 "/FPGA_Spartan6/M0_DQ7" +Na 84 "/FPGA_Spartan6/M1_A10" St ~ $EndEQUIPOT $EQUIPOT -Na 85 "/FPGA_Spartan6/M0_DQ8" +Na 85 "/FPGA_Spartan6/M1_A11" St ~ $EndEQUIPOT $EQUIPOT -Na 86 "/FPGA_Spartan6/M0_DQ9" +Na 86 "/FPGA_Spartan6/M1_A2" St ~ $EndEQUIPOT $EQUIPOT -Na 87 "/FPGA_Spartan6/M0_RAS#" +Na 87 "/FPGA_Spartan6/M1_A3" St ~ $EndEQUIPOT $EQUIPOT -Na 88 "/FPGA_Spartan6/M0_WE#" +Na 88 "/FPGA_Spartan6/M1_A4" St ~ $EndEQUIPOT $EQUIPOT -Na 89 "/FPGA_Spartan6/M1_A11" +Na 89 "/FPGA_Spartan6/M1_A5" St ~ $EndEQUIPOT $EQUIPOT -Na 90 "/FPGA_Spartan6/M1_A2" +Na 90 "/FPGA_Spartan6/M1_A6" St ~ $EndEQUIPOT $EQUIPOT -Na 91 "/FPGA_Spartan6/M1_A3" +Na 91 "/FPGA_Spartan6/M1_A7" St ~ $EndEQUIPOT $EQUIPOT -Na 92 "/FPGA_Spartan6/M1_A4" +Na 92 "/FPGA_Spartan6/M1_A8" St ~ $EndEQUIPOT $EQUIPOT -Na 93 "/FPGA_Spartan6/M1_A6" +Na 93 "/FPGA_Spartan6/M1_A9" St ~ $EndEQUIPOT $EQUIPOT -Na 94 "/FPGA_Spartan6/M1_A7" +Na 94 "/FPGA_Spartan6/M1_CAS#" St ~ $EndEQUIPOT $EQUIPOT -Na 95 "/FPGA_Spartan6/M1_A8" +Na 95 "/FPGA_Spartan6/M1_CKE" St ~ $EndEQUIPOT $EQUIPOT -Na 96 "/FPGA_Spartan6/M1_A9" +Na 96 "/FPGA_Spartan6/M1_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 97 "/FPGA_Spartan6/M1_BA0" +Na 97 "/FPGA_Spartan6/M1_CLK#" St ~ $EndEQUIPOT $EQUIPOT -Na 98 "/FPGA_Spartan6/M1_CAS#" +Na 98 "/FPGA_Spartan6/M1_DQ0" St ~ $EndEQUIPOT $EQUIPOT -Na 99 "/FPGA_Spartan6/M1_CKE" +Na 99 "/FPGA_Spartan6/M1_DQ1" St ~ $EndEQUIPOT $EQUIPOT -Na 100 "/FPGA_Spartan6/M1_CLK" +Na 100 "/FPGA_Spartan6/M1_DQ12" St ~ $EndEQUIPOT $EQUIPOT -Na 101 "/FPGA_Spartan6/M1_DQ0" +Na 101 "/FPGA_Spartan6/M1_DQ13" St ~ $EndEQUIPOT $EQUIPOT -Na 102 "/FPGA_Spartan6/M1_DQ10" +Na 102 "/FPGA_Spartan6/M1_DQ14" St ~ $EndEQUIPOT $EQUIPOT -Na 103 "/FPGA_Spartan6/M1_DQ11" +Na 103 "/FPGA_Spartan6/M1_DQ15" St ~ $EndEQUIPOT $EQUIPOT -Na 104 "/FPGA_Spartan6/M1_DQ13" +Na 104 "/FPGA_Spartan6/M1_DQ2" St ~ $EndEQUIPOT $EQUIPOT -Na 105 "/FPGA_Spartan6/M1_DQ14" +Na 105 "/FPGA_Spartan6/M1_DQ5" St ~ $EndEQUIPOT $EQUIPOT -Na 106 "/FPGA_Spartan6/M1_DQ2" +Na 106 "/FPGA_Spartan6/M1_DQ6" St ~ $EndEQUIPOT $EQUIPOT -Na 107 "/FPGA_Spartan6/M1_DQ4" +Na 107 "/FPGA_Spartan6/M1_DQ7" St ~ $EndEQUIPOT $EQUIPOT -Na 108 "/FPGA_Spartan6/M1_DQ5" +Na 108 "/FPGA_Spartan6/M1_DQ8" St ~ $EndEQUIPOT $EQUIPOT -Na 109 "/FPGA_Spartan6/M1_DQ8" +Na 109 "/FPGA_Spartan6/M1_DQ9" St ~ $EndEQUIPOT $EQUIPOT -Na 110 "/FPGA_Spartan6/M1_LDM" +Na 110 "/FPGA_Spartan6/M1_LDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 111 "/FPGA_Spartan6/M1_RAS#" +Na 111 "/FPGA_Spartan6/M1_UDM" St ~ $EndEQUIPOT $EQUIPOT -Na 112 "/FPGA_Spartan6/M1_UDM" +Na 112 "/FPGA_Spartan6/M1_UDQS" St ~ $EndEQUIPOT $EQUIPOT -Na 113 "/FPGA_Spartan6/M1_UDQS" +Na 113 "/FPGA_Spartan6/M1_WE#" St ~ $EndEQUIPOT $EQUIPOT -Na 114 "/FPGA_Spartan6/NF_CLE" +Na 114 "/FPGA_Spartan6/NF_ALE" St ~ $EndEQUIPOT $EQUIPOT -Na 115 "/FPGA_Spartan6/NF_D1" +Na 115 "/FPGA_Spartan6/NF_D2" St ~ $EndEQUIPOT $EQUIPOT -Na 116 "/FPGA_Spartan6/NF_D4" +Na 116 "/FPGA_Spartan6/NF_RE_N" St ~ $EndEQUIPOT $EQUIPOT @@ -538,111 +538,111 @@ Na 117 "/FPGA_Spartan6/NF_RNB" St ~ $EndEQUIPOT $EQUIPOT -Na 118 "/FPGA_Spartan6/NF_WE_N" +Na 118 "/FPGA_Spartan6/PROG_CCLK" St ~ $EndEQUIPOT $EQUIPOT -Na 119 "/FPGA_Spartan6/PROG_CCLK" +Na 119 "/FPGA_Spartan6/PROG_CSO" St ~ $EndEQUIPOT $EQUIPOT -Na 120 "/FPGA_Spartan6/PROG_CSO" +Na 120 "/FPGA_Spartan6/PROG_MISO0" St ~ $EndEQUIPOT $EQUIPOT -Na 121 "/FPGA_Spartan6/PROG_MISO0" +Na 121 "/FPGA_Spartan6/PROG_MISO1" St ~ $EndEQUIPOT $EQUIPOT -Na 122 "/FPGA_Spartan6/PROG_MISO1" +Na 122 "/FPGA_Spartan6/PROG_MISO2" St ~ $EndEQUIPOT $EQUIPOT -Na 123 "/FPGA_Spartan6/PROG_MISO2" +Na 123 "/FPGA_Spartan6/PROG_MISO3" St ~ $EndEQUIPOT $EQUIPOT -Na 124 "/FPGA_Spartan6/PROG_MISO3" +Na 124 "/FPGA_Spartan6/SD_CLK" St ~ $EndEQUIPOT $EQUIPOT -Na 125 "/FPGA_Spartan6/SD_CLK" +Na 125 "/FPGA_Spartan6/SD_CMD" St ~ $EndEQUIPOT $EQUIPOT -Na 126 "/FPGA_Spartan6/SD_CMD" +Na 126 "/FPGA_Spartan6/SD_DAT1" St ~ $EndEQUIPOT $EQUIPOT -Na 127 "/FPGA_Spartan6/SD_DAT0" +Na 127 "/FPGA_Spartan6/USBA_OE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 128 "/FPGA_Spartan6/SD_DAT3" +Na 128 "/FPGA_Spartan6/USBA_RCV" St ~ $EndEQUIPOT $EQUIPOT -Na 129 "/FPGA_Spartan6/USBA_RCV" +Na 129 "/Non_volatile_memories/NF_CLE" St ~ $EndEQUIPOT $EQUIPOT -Na 130 "/FPGA_Spartan6/USBA_VP" +Na 130 "/Non_volatile_memories/NF_CS1_N" St ~ $EndEQUIPOT $EQUIPOT -Na 131 "/Non_volatile_memories/NF_ALE" +Na 131 "/Non_volatile_memories/NF_D0" St ~ $EndEQUIPOT $EQUIPOT -Na 132 "/Non_volatile_memories/NF_CS1_N" +Na 132 "/Non_volatile_memories/NF_D1" St ~ $EndEQUIPOT $EQUIPOT -Na 133 "/Non_volatile_memories/NF_D0" +Na 133 "/Non_volatile_memories/NF_D3" St ~ $EndEQUIPOT $EQUIPOT -Na 134 "/Non_volatile_memories/NF_D2" +Na 134 "/Non_volatile_memories/NF_D4" St ~ $EndEQUIPOT $EQUIPOT -Na 135 "/Non_volatile_memories/NF_D3" +Na 135 "/Non_volatile_memories/NF_D5" St ~ $EndEQUIPOT $EQUIPOT -Na 136 "/Non_volatile_memories/NF_D5" +Na 136 "/Non_volatile_memories/NF_D6" St ~ $EndEQUIPOT $EQUIPOT -Na 137 "/Non_volatile_memories/NF_D6" +Na 137 "/Non_volatile_memories/NF_D7" St ~ $EndEQUIPOT $EQUIPOT -Na 138 "/Non_volatile_memories/NF_D7" +Na 138 "/Non_volatile_memories/NF_WE_N" St ~ $EndEQUIPOT $EQUIPOT -Na 139 "/Non_volatile_memories/NF_RE_N" +Na 139 "/Non_volatile_memories/SD_DAT0" St ~ $EndEQUIPOT $EQUIPOT -Na 140 "/Non_volatile_memories/SD_DAT1" +Na 140 "/Non_volatile_memories/SD_DAT2" St ~ $EndEQUIPOT $EQUIPOT -Na 141 "/Non_volatile_memories/SD_DAT2" +Na 141 "/Non_volatile_memories/SD_DAT3" St ~ $EndEQUIPOT $EQUIPOT -Na 142 "/USB/USBA_OE_N" +Na 142 "/USB/USBA_SPD" St ~ $EndEQUIPOT $EQUIPOT -Na 143 "/USB/USBA_SPD" +Na 143 "/USB/USBA_VM" St ~ $EndEQUIPOT $EQUIPOT -Na 144 "/USB/USBA_VM" +Na 144 "/USB/USBA_VP" St ~ $EndEQUIPOT $EQUIPOT @@ -670,95 +670,95 @@ Na 150 "N-000054" St ~ $EndEQUIPOT $EQUIPOT -Na 151 "N-000124" +Na 151 "N-000147" St ~ $EndEQUIPOT $EQUIPOT -Na 152 "N-000316" +Na 152 "N-000314" St ~ $EndEQUIPOT $EQUIPOT -Na 153 "N-000317" +Na 153 "N-000315" St ~ $EndEQUIPOT $EQUIPOT -Na 154 "N-000319" +Na 154 "N-000317" St ~ $EndEQUIPOT $EQUIPOT -Na 155 "N-000320" +Na 155 "N-000318" St ~ $EndEQUIPOT $EQUIPOT -Na 156 "N-000323" +Na 156 "N-000321" St ~ $EndEQUIPOT $EQUIPOT -Na 157 "N-000328" +Na 157 "N-000326" St ~ $EndEQUIPOT $EQUIPOT -Na 158 "N-000329" +Na 158 "N-000327" St ~ $EndEQUIPOT $EQUIPOT -Na 159 "N-000330" +Na 159 "N-000328" St ~ $EndEQUIPOT $EQUIPOT -Na 160 "N-000331" +Na 160 "N-000329" St ~ $EndEQUIPOT $EQUIPOT -Na 161 "N-000333" +Na 161 "N-000331" St ~ $EndEQUIPOT $EQUIPOT -Na 162 "N-000339" +Na 162 "N-000337" St ~ $EndEQUIPOT $EQUIPOT -Na 163 "N-000340" +Na 163 "N-000338" St ~ $EndEQUIPOT $EQUIPOT -Na 164 "N-000341" +Na 164 "N-000339" St ~ $EndEQUIPOT $EQUIPOT -Na 165 "N-000347" +Na 165 "N-000345" St ~ $EndEQUIPOT $EQUIPOT -Na 166 "N-000351" +Na 166 "N-000349" St ~ $EndEQUIPOT $EQUIPOT -Na 167 "N-000352" +Na 167 "N-000350" St ~ $EndEQUIPOT $EQUIPOT -Na 168 "N-000353" +Na 168 "N-000351" St ~ $EndEQUIPOT $EQUIPOT -Na 169 "N-000354" +Na 169 "N-000352" St ~ $EndEQUIPOT $EQUIPOT -Na 170 "N-000355" +Na 170 "N-000353" St ~ $EndEQUIPOT $EQUIPOT -Na 171 "N-000356" +Na 171 "N-000354" St ~ $EndEQUIPOT $EQUIPOT -Na 172 "N-000357" +Na 172 "N-000355" St ~ $EndEQUIPOT $EQUIPOT -Na 173 "N-000358" +Na 173 "N-000356" St ~ $EndEQUIPOT $EQUIPOT @@ -779,120 +779,119 @@ AddNet "+1.2V" AddNet "+2.5V" AddNet "+3.3V" AddNet "+5V" +AddNet "/DDR_Banks/M0_A0" +AddNet "/DDR_Banks/M0_A10" +AddNet "/DDR_Banks/M0_A11" AddNet "/DDR_Banks/M0_A3" -AddNet "/DDR_Banks/M0_A5" +AddNet "/DDR_Banks/M0_A8" AddNet "/DDR_Banks/M0_BA1" +AddNet "/DDR_Banks/M0_DQ0" AddNet "/DDR_Banks/M0_DQ13" +AddNet "/DDR_Banks/M0_DQ2" +AddNet "/DDR_Banks/M0_DQ4" +AddNet "/DDR_Banks/M0_DQ5" +AddNet "/DDR_Banks/M0_DQ6" +AddNet "/DDR_Banks/M0_DQ8" +AddNet "/DDR_Banks/M0_DQ9" AddNet "/DDR_Banks/M0_LDM" AddNet "/DDR_Banks/M0_LDQS" AddNet "/DDR_Banks/M0_UDM" AddNet "/DDR_Banks/M0_UDQS" +AddNet "/DDR_Banks/M0_WE#" AddNet "/DDR_Banks/M1_A0" -AddNet "/DDR_Banks/M1_A1" -AddNet "/DDR_Banks/M1_A10" AddNet "/DDR_Banks/M1_A12" -AddNet "/DDR_Banks/M1_A5" +AddNet "/DDR_Banks/M1_BA0" AddNet "/DDR_Banks/M1_BA1" -AddNet "/DDR_Banks/M1_CLK#" -AddNet "/DDR_Banks/M1_DQ1" -AddNet "/DDR_Banks/M1_DQ12" -AddNet "/DDR_Banks/M1_DQ15" +AddNet "/DDR_Banks/M1_DQ10" +AddNet "/DDR_Banks/M1_DQ11" AddNet "/DDR_Banks/M1_DQ3" -AddNet "/DDR_Banks/M1_DQ6" -AddNet "/DDR_Banks/M1_DQ7" -AddNet "/DDR_Banks/M1_DQ9" -AddNet "/DDR_Banks/M1_LDQS" -AddNet "/DDR_Banks/M1_WE#" +AddNet "/DDR_Banks/M1_DQ4" +AddNet "/DDR_Banks/M1_LDM" +AddNet "/DDR_Banks/M1_RAS#" AddNet "/Ethernet_Phy/ETH_1.8V" AddNet "/Ethernet_Phy/ETH_A1.8V" AddNet "/Ethernet_Phy/ETH_A3.3V" +AddNet "/Ethernet_Phy/ETH_CLK" +AddNet "/Ethernet_Phy/ETH_COL" AddNet "/Ethernet_Phy/ETH_INT" AddNet "/Ethernet_Phy/ETH_LED0" AddNet "/Ethernet_Phy/ETH_LED1" AddNet "/Ethernet_Phy/ETH_MDIO" AddNet "/Ethernet_Phy/ETH_PLL1.8V" -AddNet "/Ethernet_Phy/ETH_RXD0" +AddNet "/Ethernet_Phy/ETH_RXC" AddNet "/Ethernet_Phy/ETH_RXD1" -AddNet "/Ethernet_Phy/ETH_RXD3" +AddNet "/Ethernet_Phy/ETH_RXDV" +AddNet "/Ethernet_Phy/ETH_RXER" +AddNet "/Ethernet_Phy/ETH_TXC" AddNet "/Ethernet_Phy/ETH_TXD0" -AddNet "/Ethernet_Phy/ETH_TXD1" -AddNet "/Ethernet_Phy/ETH_TXD2" -AddNet "/FPGA_Spartan6/ETH_CLK" -AddNet "/FPGA_Spartan6/ETH_COL" +AddNet "/Ethernet_Phy/ETH_TXD3" +AddNet "/Ethernet_Phy/ETH_TXER" AddNet "/FPGA_Spartan6/ETH_CRS" AddNet "/FPGA_Spartan6/ETH_MDC" AddNet "/FPGA_Spartan6/ETH_RESET_N" -AddNet "/FPGA_Spartan6/ETH_RXC" +AddNet "/FPGA_Spartan6/ETH_RXD0" AddNet "/FPGA_Spartan6/ETH_RXD2" -AddNet "/FPGA_Spartan6/ETH_RXDV" -AddNet "/FPGA_Spartan6/ETH_RXER" -AddNet "/FPGA_Spartan6/ETH_TXC" -AddNet "/FPGA_Spartan6/ETH_TXD3" +AddNet "/FPGA_Spartan6/ETH_RXD3" +AddNet "/FPGA_Spartan6/ETH_TXD1" +AddNet "/FPGA_Spartan6/ETH_TXD2" AddNet "/FPGA_Spartan6/ETH_TXEN" -AddNet "/FPGA_Spartan6/ETH_TXER" -AddNet "/FPGA_Spartan6/M0_A0" AddNet "/FPGA_Spartan6/M0_A1" -AddNet "/FPGA_Spartan6/M0_A10" -AddNet "/FPGA_Spartan6/M0_A11" AddNet "/FPGA_Spartan6/M0_A12" AddNet "/FPGA_Spartan6/M0_A2" AddNet "/FPGA_Spartan6/M0_A4" +AddNet "/FPGA_Spartan6/M0_A5" AddNet "/FPGA_Spartan6/M0_A6" AddNet "/FPGA_Spartan6/M0_A7" -AddNet "/FPGA_Spartan6/M0_A8" AddNet "/FPGA_Spartan6/M0_A9" AddNet "/FPGA_Spartan6/M0_BA0" AddNet "/FPGA_Spartan6/M0_CAS#" AddNet "/FPGA_Spartan6/M0_CKE" AddNet "/FPGA_Spartan6/M0_CLK" AddNet "/FPGA_Spartan6/M0_CLK#" -AddNet "/FPGA_Spartan6/M0_DQ0" AddNet "/FPGA_Spartan6/M0_DQ1" AddNet "/FPGA_Spartan6/M0_DQ10" AddNet "/FPGA_Spartan6/M0_DQ11" AddNet "/FPGA_Spartan6/M0_DQ12" AddNet "/FPGA_Spartan6/M0_DQ14" AddNet "/FPGA_Spartan6/M0_DQ15" -AddNet "/FPGA_Spartan6/M0_DQ2" AddNet "/FPGA_Spartan6/M0_DQ3" -AddNet "/FPGA_Spartan6/M0_DQ4" -AddNet "/FPGA_Spartan6/M0_DQ5" -AddNet "/FPGA_Spartan6/M0_DQ6" AddNet "/FPGA_Spartan6/M0_DQ7" -AddNet "/FPGA_Spartan6/M0_DQ8" -AddNet "/FPGA_Spartan6/M0_DQ9" AddNet "/FPGA_Spartan6/M0_RAS#" -AddNet "/FPGA_Spartan6/M0_WE#" +AddNet "/FPGA_Spartan6/M1_A1" +AddNet "/FPGA_Spartan6/M1_A10" AddNet "/FPGA_Spartan6/M1_A11" AddNet "/FPGA_Spartan6/M1_A2" AddNet "/FPGA_Spartan6/M1_A3" AddNet "/FPGA_Spartan6/M1_A4" +AddNet "/FPGA_Spartan6/M1_A5" AddNet "/FPGA_Spartan6/M1_A6" AddNet "/FPGA_Spartan6/M1_A7" AddNet "/FPGA_Spartan6/M1_A8" AddNet "/FPGA_Spartan6/M1_A9" -AddNet "/FPGA_Spartan6/M1_BA0" AddNet "/FPGA_Spartan6/M1_CAS#" AddNet "/FPGA_Spartan6/M1_CKE" AddNet "/FPGA_Spartan6/M1_CLK" +AddNet "/FPGA_Spartan6/M1_CLK#" AddNet "/FPGA_Spartan6/M1_DQ0" -AddNet "/FPGA_Spartan6/M1_DQ10" -AddNet "/FPGA_Spartan6/M1_DQ11" +AddNet "/FPGA_Spartan6/M1_DQ1" +AddNet "/FPGA_Spartan6/M1_DQ12" AddNet "/FPGA_Spartan6/M1_DQ13" AddNet "/FPGA_Spartan6/M1_DQ14" +AddNet "/FPGA_Spartan6/M1_DQ15" AddNet "/FPGA_Spartan6/M1_DQ2" -AddNet "/FPGA_Spartan6/M1_DQ4" AddNet "/FPGA_Spartan6/M1_DQ5" +AddNet "/FPGA_Spartan6/M1_DQ6" +AddNet "/FPGA_Spartan6/M1_DQ7" AddNet "/FPGA_Spartan6/M1_DQ8" -AddNet "/FPGA_Spartan6/M1_LDM" -AddNet "/FPGA_Spartan6/M1_RAS#" +AddNet "/FPGA_Spartan6/M1_DQ9" +AddNet "/FPGA_Spartan6/M1_LDQS" AddNet "/FPGA_Spartan6/M1_UDM" AddNet "/FPGA_Spartan6/M1_UDQS" -AddNet "/FPGA_Spartan6/NF_CLE" -AddNet "/FPGA_Spartan6/NF_D1" -AddNet "/FPGA_Spartan6/NF_D4" +AddNet "/FPGA_Spartan6/M1_WE#" +AddNet "/FPGA_Spartan6/NF_ALE" +AddNet "/FPGA_Spartan6/NF_D2" +AddNet "/FPGA_Spartan6/NF_RE_N" AddNet "/FPGA_Spartan6/NF_RNB" -AddNet "/FPGA_Spartan6/NF_WE_N" AddNet "/FPGA_Spartan6/PROG_CCLK" AddNet "/FPGA_Spartan6/PROG_CSO" AddNet "/FPGA_Spartan6/PROG_MISO0" @@ -901,53 +900,54 @@ AddNet "/FPGA_Spartan6/PROG_MISO2" AddNet "/FPGA_Spartan6/PROG_MISO3" AddNet "/FPGA_Spartan6/SD_CLK" AddNet "/FPGA_Spartan6/SD_CMD" -AddNet "/FPGA_Spartan6/SD_DAT0" -AddNet "/FPGA_Spartan6/SD_DAT3" +AddNet "/FPGA_Spartan6/SD_DAT1" +AddNet "/FPGA_Spartan6/USBA_OE_N" AddNet "/FPGA_Spartan6/USBA_RCV" -AddNet "/FPGA_Spartan6/USBA_VP" -AddNet "/Non_volatile_memories/NF_ALE" +AddNet "/Non_volatile_memories/NF_CLE" AddNet "/Non_volatile_memories/NF_CS1_N" AddNet "/Non_volatile_memories/NF_D0" -AddNet "/Non_volatile_memories/NF_D2" +AddNet "/Non_volatile_memories/NF_D1" AddNet "/Non_volatile_memories/NF_D3" +AddNet "/Non_volatile_memories/NF_D4" AddNet "/Non_volatile_memories/NF_D5" AddNet "/Non_volatile_memories/NF_D6" AddNet "/Non_volatile_memories/NF_D7" -AddNet "/Non_volatile_memories/NF_RE_N" -AddNet "/Non_volatile_memories/SD_DAT1" +AddNet "/Non_volatile_memories/NF_WE_N" +AddNet "/Non_volatile_memories/SD_DAT0" AddNet "/Non_volatile_memories/SD_DAT2" -AddNet "/USB/USBA_OE_N" +AddNet "/Non_volatile_memories/SD_DAT3" AddNet "/USB/USBA_SPD" AddNet "/USB/USBA_VM" +AddNet "/USB/USBA_VP" AddNet "3.3V" AddNet "GND" AddNet "N-000050" AddNet "N-000051" AddNet "N-000052" AddNet "N-000054" -AddNet "N-000124" -AddNet "N-000316" +AddNet "N-000147" +AddNet "N-000314" +AddNet "N-000315" AddNet "N-000317" -AddNet "N-000319" -AddNet "N-000320" -AddNet "N-000323" +AddNet "N-000318" +AddNet "N-000321" +AddNet "N-000326" +AddNet "N-000327" AddNet "N-000328" AddNet "N-000329" -AddNet "N-000330" AddNet "N-000331" -AddNet "N-000333" +AddNet "N-000337" +AddNet "N-000338" AddNet "N-000339" -AddNet "N-000340" -AddNet "N-000341" -AddNet "N-000347" +AddNet "N-000345" +AddNet "N-000349" +AddNet "N-000350" AddNet "N-000351" AddNet "N-000352" AddNet "N-000353" AddNet "N-000354" AddNet "N-000355" AddNet "N-000356" -AddNet "N-000357" -AddNet "N-000358" AddNet "VCCO2" $EndNCLASS $MODULE 1206 @@ -979,9 +979,9 @@ Po 570 0 $EndPAD $EndMODULE 1206 $MODULE FGG484bga-p10 -Po 56450 33930 0 15 4C4325AE 4C431E53 ~~ +Po 56450 33930 0 15 4C4325AE 4C65E045 ~~ Li FGG484bga-p10 -Sc 4C431E53 +Sc 4C65E045 AR /4C431A63/4C431E53 Op 0 0 0 At SMD @@ -1020,70 +1020,70 @@ $PAD Sh "A4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Ethernet_Phy/ETH_INT" +Ne 39 "/Ethernet_Phy/ETH_INT" Po -2952 -4133 $EndPAD $PAD Sh "A5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_MDIO" +Ne 42 "/Ethernet_Phy/ETH_MDIO" Po -2558 -4133 $EndPAD $PAD Sh "A6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_RXD1" +Ne 45 "/Ethernet_Phy/ETH_RXD1" Po -2165 -4133 $EndPAD $PAD Sh "A7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Spartan6/ETH_RXDV" +Ne 46 "/Ethernet_Phy/ETH_RXDV" Po -1771 -4133 $EndPAD $PAD Sh "A8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_TXER" +Ne 51 "/Ethernet_Phy/ETH_TXER" Po -1377 -4133 $EndPAD $PAD Sh "A9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_TXD2" +Ne 59 "/FPGA_Spartan6/ETH_TXD2" Po -983 -4133 $EndPAD $PAD Sh "A10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/FPGA_Spartan6/ETH_COL" +Ne 38 "/Ethernet_Phy/ETH_COL" Po -590 -4133 $EndPAD $PAD Sh "A11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/Non_volatile_memories/NF_D7" +Ne 137 "/Non_volatile_memories/NF_D7" Po -196 -4133 $EndPAD $PAD Sh "A12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/Non_volatile_memories/NF_D3" +Ne 133 "/Non_volatile_memories/NF_D3" Po 196 -4133 $EndPAD $PAD Sh "A13" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_D1" +Ne 132 "/Non_volatile_memories/NF_D1" Po 590 -4133 $EndPAD $PAD @@ -1097,7 +1097,7 @@ $PAD Sh "A15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/Non_volatile_memories/NF_ALE" +Ne 114 "/FPGA_Spartan6/NF_ALE" Po 1377 -4133 $EndPAD $PAD @@ -1111,14 +1111,14 @@ $PAD Sh "A17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 141 "/Non_volatile_memories/SD_DAT2" +Ne 140 "/Non_volatile_memories/SD_DAT2" Po 2165 -4133 $EndPAD $PAD Sh "A18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 127 "/FPGA_Spartan6/SD_DAT0" +Ne 139 "/Non_volatile_memories/SD_DAT0" Po 2558 -4133 $EndPAD $PAD @@ -1188,7 +1188,7 @@ $PAD Sh "B6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/FPGA_Spartan6/ETH_RXD2" +Ne 56 "/FPGA_Spartan6/ETH_RXD2" Po -2165 -3739 $EndPAD $PAD @@ -1202,7 +1202,7 @@ $PAD Sh "B8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/ETH_RXER" +Ne 47 "/Ethernet_Phy/ETH_RXER" Po -1377 -3739 $EndPAD $PAD @@ -1216,7 +1216,7 @@ $PAD Sh "B10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/FPGA_Spartan6/ETH_CRS" +Ne 52 "/FPGA_Spartan6/ETH_CRS" Po -590 -3739 $EndPAD $PAD @@ -1230,7 +1230,7 @@ $PAD Sh "B12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_D4" +Ne 134 "/Non_volatile_memories/NF_D4" Po 196 -3739 $EndPAD $PAD @@ -1258,7 +1258,7 @@ $PAD Sh "B16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/Non_volatile_memories/NF_RE_N" +Ne 116 "/FPGA_Spartan6/NF_RE_N" Po 1771 -3739 $EndPAD $PAD @@ -1272,7 +1272,7 @@ $PAD Sh "B18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 140 "/Non_volatile_memories/SD_DAT1" +Ne 126 "/FPGA_Spartan6/SD_DAT1" Po 2558 -3739 $EndPAD $PAD @@ -1307,7 +1307,7 @@ $PAD Sh "C1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/M0_A11" +Ne 7 "/DDR_Banks/M0_A11" Po -4133 -3346 $EndPAD $PAD @@ -1335,42 +1335,42 @@ $PAD Sh "C5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/FPGA_Spartan6/ETH_MDC" +Ne 53 "/FPGA_Spartan6/ETH_MDC" Po -2558 -3346 $EndPAD $PAD Sh "C6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_RXD3" +Ne 57 "/FPGA_Spartan6/ETH_RXD3" Po -2165 -3346 $EndPAD $PAD Sh "C7" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_RXD0" +Ne 55 "/FPGA_Spartan6/ETH_RXD0" Po -1771 -3346 $EndPAD $PAD Sh "C8" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_TXD0" +Ne 49 "/Ethernet_Phy/ETH_TXD0" Po -1377 -3346 $EndPAD $PAD Sh "C9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_TXD1" +Ne 58 "/FPGA_Spartan6/ETH_TXD1" Po -983 -3346 $EndPAD $PAD Sh "C10" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/FPGA_Spartan6/ETH_CLK" +Ne 37 "/Ethernet_Phy/ETH_CLK" Po -590 -3346 $EndPAD $PAD @@ -1384,14 +1384,14 @@ $PAD Sh "C12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/Non_volatile_memories/NF_D5" +Ne 135 "/Non_volatile_memories/NF_D5" Po 196 -3346 $EndPAD $PAD Sh "C13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/Non_volatile_memories/NF_D2" +Ne 115 "/FPGA_Spartan6/NF_D2" Po 590 -3346 $EndPAD $PAD @@ -1405,21 +1405,21 @@ $PAD Sh "C15" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/NF_WE_N" +Ne 138 "/Non_volatile_memories/NF_WE_N" Po 1377 -3346 $EndPAD $PAD Sh "C16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/Non_volatile_memories/NF_CS1_N" +Ne 130 "/Non_volatile_memories/NF_CS1_N" Po 1771 -3346 $EndPAD $PAD Sh "C17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 128 "/FPGA_Spartan6/SD_DAT3" +Ne 141 "/Non_volatile_memories/SD_DAT3" Po 2165 -3346 $EndPAD $PAD @@ -1440,7 +1440,7 @@ $PAD Sh "C20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A8" +Ne 92 "/FPGA_Spartan6/M1_A8" Po 3346 -3346 $EndPAD $PAD @@ -1454,21 +1454,21 @@ $PAD Sh "C22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_A9" +Ne 93 "/FPGA_Spartan6/M1_A9" Po 4133 -3346 $EndPAD $PAD Sh "D1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/M0_A12" +Ne 62 "/FPGA_Spartan6/M0_A12" Po -4133 -2952 $EndPAD $PAD Sh "D2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_CKE" +Ne 71 "/FPGA_Spartan6/M0_CKE" Po -3739 -2952 $EndPAD $PAD @@ -1496,42 +1496,42 @@ $PAD Sh "D6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/FPGA_Spartan6/ETH_RESET_N" +Ne 54 "/FPGA_Spartan6/ETH_RESET_N" Po -2165 -2952 $EndPAD $PAD Sh "D7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_TXD3" +Ne 50 "/Ethernet_Phy/ETH_TXD3" Po -1771 -2952 $EndPAD $PAD Sh "D8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_TXC" +Ne 48 "/Ethernet_Phy/ETH_TXC" Po -1377 -2952 $EndPAD $PAD Sh "D9" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_TXEN" +Ne 60 "/FPGA_Spartan6/ETH_TXEN" Po -983 -2952 $EndPAD $PAD Sh "D10" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/FPGA_Spartan6/ETH_RXC" +Ne 44 "/Ethernet_Phy/ETH_RXC" Po -590 -2952 $EndPAD $PAD Sh "D11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/Non_volatile_memories/NF_D6" +Ne 136 "/Non_volatile_memories/NF_D6" Po -196 -2952 $EndPAD $PAD @@ -1552,14 +1552,14 @@ $PAD Sh "D14" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/Non_volatile_memories/NF_D0" +Ne 131 "/Non_volatile_memories/NF_D0" Po 983 -2952 $EndPAD $PAD Sh "D15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/NF_CLE" +Ne 129 "/Non_volatile_memories/NF_CLE" Po 1377 -2952 $EndPAD $PAD @@ -1573,7 +1573,7 @@ $PAD Sh "D17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 126 "/FPGA_Spartan6/SD_CMD" +Ne 125 "/FPGA_Spartan6/SD_CMD" Po 2165 -2952 $EndPAD $PAD @@ -1601,21 +1601,21 @@ $PAD Sh "D21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_CKE" +Ne 95 "/FPGA_Spartan6/M1_CKE" Po 3739 -2952 $EndPAD $PAD Sh "D22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M1_A12" +Ne 25 "/DDR_Banks/M1_A12" Po 4133 -2952 $EndPAD $PAD Sh "E1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A9" +Ne 68 "/FPGA_Spartan6/M0_A9" Po -4133 -2558 $EndPAD $PAD @@ -1629,7 +1629,7 @@ $PAD Sh "E3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A8" +Ne 9 "/DDR_Banks/M0_A8" Po -3346 -2558 $EndPAD $PAD @@ -1685,7 +1685,7 @@ $PAD Sh "E11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 146 "GND" Po -196 -2558 $EndPAD $PAD @@ -1720,7 +1720,7 @@ $PAD Sh "E16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 125 "/FPGA_Spartan6/SD_CLK" +Ne 124 "/FPGA_Spartan6/SD_CLK" Po 1771 -2558 $EndPAD $PAD @@ -1748,7 +1748,7 @@ $PAD Sh "E20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A7" +Ne 91 "/FPGA_Spartan6/M1_A7" Po 3346 -2558 $EndPAD $PAD @@ -1762,7 +1762,7 @@ $PAD Sh "E22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A2" +Ne 86 "/FPGA_Spartan6/M1_A2" Po 4133 -2558 $EndPAD $PAD @@ -1776,14 +1776,14 @@ $PAD Sh "F2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_WE#" +Ne 23 "/DDR_Banks/M0_WE#" Po -3739 -2165 $EndPAD $PAD Sh "F3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/M0_A4" +Ne 64 "/FPGA_Spartan6/M0_A4" Po -3346 -2165 $EndPAD $PAD @@ -1895,35 +1895,35 @@ $PAD Sh "F19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A11" +Ne 85 "/FPGA_Spartan6/M1_A11" Po 2952 -2165 $EndPAD $PAD Sh "F20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A4" +Ne 88 "/FPGA_Spartan6/M1_A4" Po 3346 -2165 $EndPAD $PAD Sh "F21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M1_A0" +Ne 24 "/DDR_Banks/M1_A0" Po 3739 -2165 $EndPAD $PAD Sh "F22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M1_A1" +Ne 83 "/FPGA_Spartan6/M1_A1" Po 4133 -2165 $EndPAD $PAD Sh "G1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_BA1" +Ne 10 "/DDR_Banks/M0_BA1" Po -4133 -1771 $EndPAD $PAD @@ -1937,14 +1937,14 @@ $PAD Sh "G3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_BA0" +Ne 69 "/FPGA_Spartan6/M0_BA0" Po -3346 -1771 $EndPAD $PAD Sh "G4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/M0_A10" +Ne 6 "/DDR_Banks/M0_A10" Po -2952 -1771 $EndPAD $PAD @@ -2049,14 +2049,14 @@ $PAD Sh "G19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M1_A10" +Ne 84 "/FPGA_Spartan6/M1_A10" Po 2952 -1771 $EndPAD $PAD Sh "G20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A3" +Ne 87 "/FPGA_Spartan6/M1_A3" Po 3346 -1771 $EndPAD $PAD @@ -2077,42 +2077,42 @@ $PAD Sh "H1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/M0_A1" +Ne 61 "/FPGA_Spartan6/M0_A1" Po -4133 -1377 $EndPAD $PAD Sh "H2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/M0_A0" +Ne 5 "/DDR_Banks/M0_A0" Po -3739 -1377 $EndPAD $PAD Sh "H3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_CLK#" +Ne 73 "/FPGA_Spartan6/M0_CLK#" Po -3346 -1377 $EndPAD $PAD Sh "H4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_CLK" +Ne 72 "/FPGA_Spartan6/M0_CLK" Po -2952 -1377 $EndPAD $PAD Sh "H5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/M0_A2" +Ne 63 "/FPGA_Spartan6/M0_A2" Po -2558 -1377 $EndPAD $PAD Sh "H6" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A7" +Ne 67 "/FPGA_Spartan6/M0_A7" Po -2165 -1377 $EndPAD $PAD @@ -2203,35 +2203,35 @@ $PAD Sh "H19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_WE#" +Ne 113 "/FPGA_Spartan6/M1_WE#" Po 2952 -1377 $EndPAD $PAD Sh "H20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_CLK" +Ne 96 "/FPGA_Spartan6/M1_CLK" Po 3346 -1377 $EndPAD $PAD Sh "H21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_RAS#" +Ne 33 "/DDR_Banks/M1_RAS#" Po 3739 -1377 $EndPAD $PAD Sh "H22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_CAS#" +Ne 94 "/FPGA_Spartan6/M1_CAS#" Po 4133 -1377 $EndPAD $PAD Sh "J1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ5" +Ne 15 "/DDR_Banks/M0_DQ5" Po -4133 -983 $EndPAD $PAD @@ -2245,14 +2245,14 @@ $PAD Sh "J3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ4" +Ne 14 "/DDR_Banks/M0_DQ4" Po -3346 -983 $EndPAD $PAD Sh "J4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M0_A6" +Ne 66 "/FPGA_Spartan6/M0_A6" Po -2952 -983 $EndPAD $PAD @@ -2343,7 +2343,7 @@ $PAD Sh "J17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_BA0" +Ne 26 "/DDR_Banks/M1_BA0" Po 2165 -983 $EndPAD $PAD @@ -2357,14 +2357,14 @@ $PAD Sh "J19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M1_CLK#" +Ne 97 "/FPGA_Spartan6/M1_CLK#" Po 2952 -983 $EndPAD $PAD Sh "J20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ4" +Ne 31 "/DDR_Banks/M1_DQ4" Po 3346 -983 $EndPAD $PAD @@ -2378,49 +2378,49 @@ $PAD Sh "J22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ5" +Ne 105 "/FPGA_Spartan6/M1_DQ5" Po 4133 -983 $EndPAD $PAD Sh "K1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ7" +Ne 81 "/FPGA_Spartan6/M0_DQ7" Po -4133 -590 $EndPAD $PAD Sh "K2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ6" +Ne 16 "/DDR_Banks/M0_DQ6" Po -3739 -590 $EndPAD $PAD Sh "K3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A5" +Ne 65 "/FPGA_Spartan6/M0_A5" Po -3346 -590 $EndPAD $PAD Sh "K4" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_CAS#" +Ne 70 "/FPGA_Spartan6/M0_CAS#" Po -2952 -590 $EndPAD $PAD Sh "K5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_RAS#" +Ne 82 "/FPGA_Spartan6/M0_RAS#" Po -2558 -590 $EndPAD $PAD Sh "K6" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_A3" +Ne 8 "/DDR_Banks/M0_A3" Po -2165 -590 $EndPAD $PAD @@ -2462,7 +2462,7 @@ $PAD Sh "K12" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 0 "" +Ne 146 "GND" Po 196 -590 $EndPAD $PAD @@ -2497,7 +2497,7 @@ $PAD Sh "K17" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M1_BA1" +Ne 27 "/DDR_Banks/M1_BA1" Po 2165 -590 $EndPAD $PAD @@ -2511,28 +2511,28 @@ $PAD Sh "K19" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_A6" +Ne 90 "/FPGA_Spartan6/M1_A6" Po 2952 -590 $EndPAD $PAD Sh "K20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M1_A5" +Ne 89 "/FPGA_Spartan6/M1_A5" Po 3346 -590 $EndPAD $PAD Sh "K21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_DQ6" +Ne 106 "/FPGA_Spartan6/M1_DQ6" Po 3739 -590 $EndPAD $PAD Sh "K22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_DQ7" +Ne 107 "/FPGA_Spartan6/M1_DQ7" Po 4133 -590 $EndPAD $PAD @@ -2553,14 +2553,14 @@ $PAD Sh "L3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_LDQS" +Ne 20 "/DDR_Banks/M0_LDQS" Po -3346 -196 $EndPAD $PAD Sh "L4" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_LDM" +Ne 19 "/DDR_Banks/M0_LDM" Po -2952 -196 $EndPAD $PAD @@ -2665,14 +2665,14 @@ $PAD Sh "L19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_LDM" +Ne 32 "/DDR_Banks/M1_LDM" Po 2952 -196 $EndPAD $PAD Sh "L20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_LDQS" +Ne 110 "/FPGA_Spartan6/M1_LDQS" Po 3346 -196 $EndPAD $PAD @@ -2700,14 +2700,14 @@ $PAD Sh "M2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ2" +Ne 13 "/DDR_Banks/M0_DQ2" Po -3739 196 $EndPAD $PAD Sh "M3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_UDM" +Ne 21 "/DDR_Banks/M0_UDM" Po -3346 196 $EndPAD $PAD @@ -2812,7 +2812,7 @@ $PAD Sh "M18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 144 "/USB/USBA_VM" +Ne 143 "/USB/USBA_VM" Po 2558 196 $EndPAD $PAD @@ -2826,28 +2826,28 @@ $PAD Sh "M20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_UDM" +Ne 111 "/FPGA_Spartan6/M1_UDM" Po 3346 196 $EndPAD $PAD Sh "M21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ2" +Ne 104 "/FPGA_Spartan6/M1_DQ2" Po 3739 196 $EndPAD $PAD Sh "M22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_DQ3" +Ne 30 "/DDR_Banks/M1_DQ3" Po 4133 196 $EndPAD $PAD Sh "N1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_DQ1" +Ne 74 "/FPGA_Spartan6/M0_DQ1" Po -4133 590 $EndPAD $PAD @@ -2861,7 +2861,7 @@ $PAD Sh "N3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_DQ0" +Ne 11 "/DDR_Banks/M0_DQ0" Po -3346 590 $EndPAD $PAD @@ -2952,7 +2952,7 @@ $PAD Sh "N16" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 129 "/FPGA_Spartan6/USBA_RCV" +Ne 128 "/FPGA_Spartan6/USBA_RCV" Po 1771 590 $EndPAD $PAD @@ -2980,7 +2980,7 @@ $PAD Sh "N20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ0" +Ne 98 "/FPGA_Spartan6/M1_DQ0" Po 3346 590 $EndPAD $PAD @@ -2994,21 +2994,21 @@ $PAD Sh "N22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_DQ1" +Ne 99 "/FPGA_Spartan6/M1_DQ1" Po 4133 590 $EndPAD $PAD Sh "P1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ9" +Ne 18 "/DDR_Banks/M0_DQ9" Po -4133 983 $EndPAD $PAD Sh "P2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ8" +Ne 17 "/DDR_Banks/M0_DQ8" Po -3739 983 $EndPAD $PAD @@ -3113,14 +3113,14 @@ $PAD Sh "P17" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 130 "/FPGA_Spartan6/USBA_VP" +Ne 144 "/USB/USBA_VP" Po 2165 983 $EndPAD $PAD Sh "P18" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 142 "/USB/USBA_OE_N" +Ne 127 "/FPGA_Spartan6/USBA_OE_N" Po 2558 983 $EndPAD $PAD @@ -3141,21 +3141,21 @@ $PAD Sh "P21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ8" +Ne 108 "/FPGA_Spartan6/M1_DQ8" Po 3739 983 $EndPAD $PAD Sh "P22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_DQ9" +Ne 109 "/FPGA_Spartan6/M1_DQ9" Po 4133 983 $EndPAD $PAD Sh "R1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_DQ11" +Ne 76 "/FPGA_Spartan6/M0_DQ11" Po -4133 1377 $EndPAD $PAD @@ -3169,7 +3169,7 @@ $PAD Sh "R3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_DQ10" +Ne 75 "/FPGA_Spartan6/M0_DQ10" Po -3346 1377 $EndPAD $PAD @@ -3281,14 +3281,14 @@ $PAD Sh "R19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 143 "/USB/USBA_SPD" +Ne 142 "/USB/USBA_SPD" Po 2952 1377 $EndPAD $PAD Sh "R20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ10" +Ne 28 "/DDR_Banks/M1_DQ10" Po 3346 1377 $EndPAD $PAD @@ -3302,7 +3302,7 @@ $PAD Sh "R22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ11" +Ne 29 "/DDR_Banks/M1_DQ11" Po 4133 1377 $EndPAD $PAD @@ -3316,7 +3316,7 @@ $PAD Sh "T2" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_UDQS" +Ne 22 "/DDR_Banks/M0_UDQS" Po -3739 1771 $EndPAD $PAD @@ -3337,7 +3337,7 @@ $PAD Sh "T5" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/PROG_CSO" +Ne 119 "/FPGA_Spartan6/PROG_CSO" Po -2558 1771 $EndPAD $PAD @@ -3365,7 +3365,7 @@ $PAD Sh "T9" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po -983 1771 $EndPAD $PAD @@ -3393,7 +3393,7 @@ $PAD Sh "T13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po 590 1771 $EndPAD $PAD @@ -3449,7 +3449,7 @@ $PAD Sh "T21" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_UDQS" +Ne 112 "/FPGA_Spartan6/M1_UDQS" Po 3739 1771 $EndPAD $PAD @@ -3463,7 +3463,7 @@ $PAD Sh "U1" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_DQ13" +Ne 12 "/DDR_Banks/M0_DQ13" Po -4133 2165 $EndPAD $PAD @@ -3477,7 +3477,7 @@ $PAD Sh "U3" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ12" +Ne 77 "/FPGA_Spartan6/M0_DQ12" Po -3346 2165 $EndPAD $PAD @@ -3547,14 +3547,14 @@ $PAD Sh "U13" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/PROG_MISO3" +Ne 123 "/FPGA_Spartan6/PROG_MISO3" Po 590 2165 $EndPAD $PAD Sh "U14" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/PROG_MISO2" +Ne 122 "/FPGA_Spartan6/PROG_MISO2" Po 983 2165 $EndPAD $PAD @@ -3596,7 +3596,7 @@ $PAD Sh "U20" O 158 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_DQ12" +Ne 100 "/FPGA_Spartan6/M1_DQ12" Po 3346 2165 $EndPAD $PAD @@ -3610,21 +3610,21 @@ $PAD Sh "U22" O 157 158 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ13" +Ne 101 "/FPGA_Spartan6/M1_DQ13" Po 4133 2165 $EndPAD $PAD Sh "V1" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ15" +Ne 79 "/FPGA_Spartan6/M0_DQ15" Po -4133 2558 $EndPAD $PAD Sh "V2" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ14" +Ne 78 "/FPGA_Spartan6/M0_DQ14" Po -3739 2558 $EndPAD $PAD @@ -3666,7 +3666,7 @@ $PAD Sh "V8" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po -1377 2558 $EndPAD $PAD @@ -3694,7 +3694,7 @@ $PAD Sh "V12" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po 196 2558 $EndPAD $PAD @@ -3722,7 +3722,7 @@ $PAD Sh "V16" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po 1771 2558 $EndPAD $PAD @@ -3757,14 +3757,14 @@ $PAD Sh "V21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ14" +Ne 102 "/FPGA_Spartan6/M1_DQ14" Po 3739 2558 $EndPAD $PAD Sh "V22" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_DQ15" +Ne 103 "/FPGA_Spartan6/M1_DQ15" Po 4133 2558 $EndPAD $PAD @@ -3799,7 +3799,7 @@ $PAD Sh "W5" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po -2558 2952 $EndPAD $PAD @@ -4093,7 +4093,7 @@ $PAD Sh "AA3" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po -3346 3739 $EndPAD $PAD @@ -4121,7 +4121,7 @@ $PAD Sh "AA7" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po -1771 3739 $EndPAD $PAD @@ -4149,7 +4149,7 @@ $PAD Sh "AA11" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po -196 3739 $EndPAD $PAD @@ -4177,7 +4177,7 @@ $PAD Sh "AA15" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po 1377 3739 $EndPAD $PAD @@ -4205,21 +4205,21 @@ $PAD Sh "AA19" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 151 "N-000124" +Ne 151 "N-000147" Po 2952 3739 $EndPAD $PAD Sh "AA20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/PROG_MISO1" +Ne 121 "/FPGA_Spartan6/PROG_MISO1" Po 3346 3739 $EndPAD $PAD Sh "AA21" O 157 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/PROG_CCLK" +Ne 118 "/FPGA_Spartan6/PROG_CCLK" Po 3739 3739 $EndPAD $PAD @@ -4366,7 +4366,7 @@ $PAD Sh "AB20" O 158 157 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/PROG_MISO0" +Ne 120 "/FPGA_Spartan6/PROG_MISO0" Po 3346 4133 $EndPAD $PAD @@ -4385,7 +4385,7 @@ Po 4133 4133 $EndPAD $EndMODULE FGG484bga-p10 $MODULE LQFP48 -Po 50591 26772 900 15 4C433D64 4C432132 ~~ +Po 51575 26772 900 15 4C433D64 4C432132 ~~ Li LQFP48 Sc 4C432132 AR /4C4320F3/4C432132 @@ -4409,21 +4409,21 @@ $PAD Sh "11" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 51 "/FPGA_Spartan6/ETH_RXER" +Ne 47 "/Ethernet_Phy/ETH_RXER" Po -1613 885 $EndPAD $PAD Sh "10" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 48 "/FPGA_Spartan6/ETH_RXC" +Ne 44 "/Ethernet_Phy/ETH_RXC" Po -1613 688 $EndPAD $PAD Sh "9" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 50 "/FPGA_Spartan6/ETH_RXDV" +Ne 46 "/Ethernet_Phy/ETH_RXDV" Po -1613 491 $EndPAD $PAD @@ -4444,63 +4444,63 @@ $PAD Sh "6" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 37 "/Ethernet_Phy/ETH_RXD0" +Ne 55 "/FPGA_Spartan6/ETH_RXD0" Po -1613 -98 $EndPAD $PAD Sh "5" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 38 "/Ethernet_Phy/ETH_RXD1" +Ne 45 "/Ethernet_Phy/ETH_RXD1" Po -1613 -295 $EndPAD $PAD Sh "4" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 49 "/FPGA_Spartan6/ETH_RXD2" +Ne 56 "/FPGA_Spartan6/ETH_RXD2" Po -1613 -491 $EndPAD $PAD Sh "3" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 39 "/Ethernet_Phy/ETH_RXD3" +Ne 57 "/FPGA_Spartan6/ETH_RXD3" Po -1613 -688 $EndPAD $PAD Sh "2" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 46 "/FPGA_Spartan6/ETH_MDC" +Ne 53 "/FPGA_Spartan6/ETH_MDC" Po -1613 -885 $EndPAD $PAD Sh "1" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 35 "/Ethernet_Phy/ETH_MDIO" +Ne 42 "/Ethernet_Phy/ETH_MDIO" Po -1613 -1082 $EndPAD $PAD Sh "48" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 47 "/FPGA_Spartan6/ETH_RESET_N" +Ne 54 "/FPGA_Spartan6/ETH_RESET_N" Po -1082 -1613 $EndPAD $PAD Sh "47" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" Po -885 -1613 $EndPAD $PAD Sh "46" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 43 "/FPGA_Spartan6/ETH_CLK" +Ne 37 "/Ethernet_Phy/ETH_CLK" Po -688 -1613 $EndPAD $PAD @@ -4535,14 +4535,14 @@ $PAD Sh "41" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 154 "N-000319" +Ne 154 "N-000317" Po 295 -1613 $EndPAD $PAD Sh "40" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 159 "N-000330" +Ne 159 "N-000328" Po 491 -1613 $EndPAD $PAD @@ -4556,35 +4556,35 @@ $PAD Sh "38" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A3.3V" +Ne 36 "/Ethernet_Phy/ETH_A3.3V" Po 885 -1613 $EndPAD $PAD Sh "37" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 157 "N-000328" +Ne 157 "N-000326" Po 1082 -1613 $EndPAD $PAD Sh "25" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 32 "/Ethernet_Phy/ETH_INT" +Ne 39 "/Ethernet_Phy/ETH_INT" Po 1613 1082 $EndPAD $PAD Sh "26" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 33 "/Ethernet_Phy/ETH_LED0" +Ne 40 "/Ethernet_Phy/ETH_LED0" Po 1613 885 $EndPAD $PAD Sh "27" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 34 "/Ethernet_Phy/ETH_LED1" +Ne 41 "/Ethernet_Phy/ETH_LED1" Po 1613 688 $EndPAD $PAD @@ -4612,21 +4612,21 @@ $PAD Sh "31" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/Ethernet_Phy/ETH_A1.8V" +Ne 35 "/Ethernet_Phy/ETH_A1.8V" Po 1613 -98 $EndPAD $PAD Sh "32" R 315 98 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 158 "N-000329" +Ne 158 "N-000327" Po 1613 -295 $EndPAD $PAD Sh "33" R 315 99 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 155 "N-000320" +Ne 155 "N-000318" Po 1613 -491 $EndPAD $PAD @@ -4654,70 +4654,70 @@ $PAD Sh "13" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/Ethernet_Phy/ETH_1.8V" +Ne 34 "/Ethernet_Phy/ETH_1.8V" Po -1082 1613 $EndPAD $PAD Sh "14" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 55 "/FPGA_Spartan6/ETH_TXER" +Ne 51 "/Ethernet_Phy/ETH_TXER" Po -885 1613 $EndPAD $PAD Sh "15" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 52 "/FPGA_Spartan6/ETH_TXC" +Ne 48 "/Ethernet_Phy/ETH_TXC" Po -688 1613 $EndPAD $PAD Sh "16" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 54 "/FPGA_Spartan6/ETH_TXEN" +Ne 60 "/FPGA_Spartan6/ETH_TXEN" Po -491 1613 $EndPAD $PAD Sh "17" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 40 "/Ethernet_Phy/ETH_TXD0" +Ne 49 "/Ethernet_Phy/ETH_TXD0" Po -295 1613 $EndPAD $PAD Sh "18" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 41 "/Ethernet_Phy/ETH_TXD1" +Ne 58 "/FPGA_Spartan6/ETH_TXD1" Po -98 1613 $EndPAD $PAD Sh "19" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 42 "/Ethernet_Phy/ETH_TXD2" +Ne 59 "/FPGA_Spartan6/ETH_TXD2" Po 98 1613 $EndPAD $PAD Sh "20" R 98 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 53 "/FPGA_Spartan6/ETH_TXD3" +Ne 50 "/Ethernet_Phy/ETH_TXD3" Po 295 1613 $EndPAD $PAD Sh "21" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 44 "/FPGA_Spartan6/ETH_COL" +Ne 38 "/Ethernet_Phy/ETH_COL" Po 491 1613 $EndPAD $PAD Sh "22" R 99 315 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 45 "/FPGA_Spartan6/ETH_CRS" +Ne 52 "/FPGA_Spartan6/ETH_CRS" Po 688 1613 $EndPAD $PAD @@ -5009,14 +5009,14 @@ $PAD Sh "8" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 139 "/Non_volatile_memories/NF_RE_N" +Ne 116 "/FPGA_Spartan6/NF_RE_N" Po -890 3850 $EndPAD $PAD Sh "9" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 132 "/Non_volatile_memories/NF_CS1_N" +Ne 130 "/Non_volatile_memories/NF_CS1_N" Po -690 3850 $EndPAD $PAD @@ -5065,21 +5065,21 @@ $PAD Sh "16" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 114 "/FPGA_Spartan6/NF_CLE" +Ne 129 "/Non_volatile_memories/NF_CLE" Po 690 3850 $EndPAD $PAD Sh "17" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 131 "/Non_volatile_memories/NF_ALE" +Ne 114 "/FPGA_Spartan6/NF_ALE" Po 880 3850 $EndPAD $PAD Sh "18" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 118 "/FPGA_Spartan6/NF_WE_N" +Ne 138 "/Non_volatile_memories/NF_WE_N" Po 1080 3850 $EndPAD $PAD @@ -5156,28 +5156,28 @@ $PAD Sh "29" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 133 "/Non_volatile_memories/NF_D0" +Ne 131 "/Non_volatile_memories/NF_D0" Po 1470 -3850 $EndPAD $PAD Sh "30" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 115 "/FPGA_Spartan6/NF_D1" +Ne 132 "/Non_volatile_memories/NF_D1" Po 1280 -3850 $EndPAD $PAD Sh "31" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 134 "/Non_volatile_memories/NF_D2" +Ne 115 "/FPGA_Spartan6/NF_D2" Po 1080 -3850 $EndPAD $PAD Sh "32" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 135 "/Non_volatile_memories/NF_D3" +Ne 133 "/Non_volatile_memories/NF_D3" Po 880 -3850 $EndPAD $PAD @@ -5240,28 +5240,28 @@ $PAD Sh "41" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 116 "/FPGA_Spartan6/NF_D4" +Ne 134 "/Non_volatile_memories/NF_D4" Po -890 -3850 $EndPAD $PAD Sh "42" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 136 "/Non_volatile_memories/NF_D5" +Ne 135 "/Non_volatile_memories/NF_D5" Po -1090 -3850 $EndPAD $PAD Sh "43" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 137 "/Non_volatile_memories/NF_D6" +Ne 136 "/Non_volatile_memories/NF_D6" Po -1280 -3850 $EndPAD $PAD Sh "44" R 100 600 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 138 "/Non_volatile_memories/NF_D7" +Ne 137 "/Non_volatile_memories/NF_D7" Po -1480 -3850 $EndPAD $PAD @@ -5314,21 +5314,21 @@ $PAD Sh "1" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 141 "/Non_volatile_memories/SD_DAT2" +Ne 140 "/Non_volatile_memories/SD_DAT2" Po -1299 0 $EndPAD $PAD Sh "2" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 128 "/FPGA_Spartan6/SD_DAT3" +Ne 141 "/Non_volatile_memories/SD_DAT3" Po -866 0 $EndPAD $PAD Sh "3" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 126 "/FPGA_Spartan6/SD_CMD" +Ne 125 "/FPGA_Spartan6/SD_CMD" Po -433 0 $EndPAD $PAD @@ -5342,7 +5342,7 @@ $PAD Sh "5" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 125 "/FPGA_Spartan6/SD_CLK" +Ne 124 "/FPGA_Spartan6/SD_CLK" Po 433 0 $EndPAD $PAD @@ -5356,14 +5356,14 @@ $PAD Sh "7" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 127 "/FPGA_Spartan6/SD_DAT0" +Ne 139 "/Non_volatile_memories/SD_DAT0" Po 1299 0 $EndPAD $PAD Sh "8" R 315 590 0 0 0 Dr 0 0 0 At STD N 00440001 -Ne 140 "/Non_volatile_memories/SD_DAT1" +Ne 126 "/FPGA_Spartan6/SD_DAT1" Po 1732 0 $EndPAD $PAD @@ -5411,35 +5411,35 @@ $PAD Sh "13" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 152 "N-000316" +Ne 152 "N-000314" Po 2250 0 $EndPAD $PAD Sh "13" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 152 "N-000316" +Ne 152 "N-000314" Po 3100 -1200 $EndPAD $PAD Sh "14" C 1646 1646 0 0 1800 Dr 1252 0 0 At STD N 0CC0FFFF -Ne 152 "N-000316" +Ne 152 "N-000314" Po -2250 0 $EndPAD $PAD Sh "14" C 984 984 0 0 1800 Dr 640 0 0 At STD N 0CC0FFFF -Ne 152 "N-000316" +Ne 152 "N-000314" Po -3100 -1200 $EndPAD $PAD Sh "1" R 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 154 "N-000319" +Ne 154 "N-000317" Po -1750 -2500 $EndPAD $PAD @@ -5460,14 +5460,14 @@ $PAD Sh "7" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 155 "N-000320" +Ne 155 "N-000318" Po 1250 -2500 $EndPAD $PAD Sh "2" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 159 "N-000330" +Ne 159 "N-000328" Po -1250 -3500 $EndPAD $PAD @@ -5488,7 +5488,7 @@ $PAD Sh "8" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 158 "N-000329" +Ne 158 "N-000327" Po 1750 -3500 $EndPAD $PAD @@ -5502,7 +5502,7 @@ $PAD Sh "10" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 153 "N-000317" +Ne 153 "N-000315" Po -1150 -5400 $EndPAD $PAD @@ -5516,7 +5516,7 @@ $PAD Sh "12" C 540 540 0 0 1800 Dr 350 0 0 At STD N 0CC0FFFF -Ne 161 "N-000333" +Ne 161 "N-000331" Po 2150 -5400 $EndPAD $EndMODULE SD-48025 @@ -5552,28 +5552,28 @@ $PAD Sh "2" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 143 "/USB/USBA_SPD" +Ne 142 "/USB/USBA_SPD" Po -511 -1112 $EndPAD $PAD Sh "3" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 129 "/FPGA_Spartan6/USBA_RCV" +Ne 128 "/FPGA_Spartan6/USBA_RCV" Po -255 -1112 $EndPAD $PAD Sh "4" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 130 "/FPGA_Spartan6/USBA_VP" +Ne 144 "/USB/USBA_VP" Po 0 -1112 $EndPAD $PAD Sh "5" R 137 570 0 0 900 Dr 0 0 0 At SMD N 00440001 -Ne 144 "/USB/USBA_VM" +Ne 143 "/USB/USBA_VM" Po 255 -1112 $EndPAD $PAD @@ -5601,21 +5601,21 @@ $PAD Sh "9" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 142 "/USB/USBA_OE_N" +Ne 127 "/FPGA_Spartan6/USBA_OE_N" Po 511 1112 $EndPAD $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 162 "N-000339" +Ne 162 "N-000337" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 173 "N-000358" +Ne 173 "N-000356" Po 0 1112 $EndPAD $PAD @@ -5665,7 +5665,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 101 "/FPGA_Spartan6/M1_DQ0" +Ne 98 "/FPGA_Spartan6/M1_DQ0" Po -3838 2176 $EndPAD $PAD @@ -5679,14 +5679,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 20 "/DDR_Banks/M1_DQ1" +Ne 99 "/FPGA_Spartan6/M1_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 106 "/FPGA_Spartan6/M1_DQ2" +Ne 104 "/FPGA_Spartan6/M1_DQ2" Po -3070 2176 $EndPAD $PAD @@ -5700,14 +5700,14 @@ $PAD Sh "7" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 23 "/DDR_Banks/M1_DQ3" +Ne 30 "/DDR_Banks/M1_DQ3" Po -2558 2176 $EndPAD $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 107 "/FPGA_Spartan6/M1_DQ4" +Ne 31 "/DDR_Banks/M1_DQ4" Po -2303 2176 $EndPAD $PAD @@ -5721,14 +5721,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 108 "/FPGA_Spartan6/M1_DQ5" +Ne 105 "/FPGA_Spartan6/M1_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 24 "/DDR_Banks/M1_DQ6" +Ne 106 "/FPGA_Spartan6/M1_DQ6" Po -1535 2176 $EndPAD $PAD @@ -5742,7 +5742,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 25 "/DDR_Banks/M1_DQ7" +Ne 107 "/FPGA_Spartan6/M1_DQ7" Po -1023 2176 $EndPAD $PAD @@ -5763,7 +5763,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 27 "/DDR_Banks/M1_LDQS" +Ne 110 "/FPGA_Spartan6/M1_LDQS" Po -255 2176 $EndPAD $PAD @@ -5791,28 +5791,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 110 "/FPGA_Spartan6/M1_LDM" +Ne 32 "/DDR_Banks/M1_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 28 "/DDR_Banks/M1_WE#" +Ne 113 "/FPGA_Spartan6/M1_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 98 "/FPGA_Spartan6/M1_CAS#" +Ne 94 "/FPGA_Spartan6/M1_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 111 "/FPGA_Spartan6/M1_RAS#" +Ne 33 "/DDR_Banks/M1_RAS#" Po 1535 2176 $EndPAD $PAD @@ -5833,49 +5833,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 97 "/FPGA_Spartan6/M1_BA0" +Ne 26 "/DDR_Banks/M1_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 18 "/DDR_Banks/M1_BA1" +Ne 27 "/DDR_Banks/M1_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 15 "/DDR_Banks/M1_A10" +Ne 84 "/FPGA_Spartan6/M1_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 13 "/DDR_Banks/M1_A0" +Ne 24 "/DDR_Banks/M1_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 14 "/DDR_Banks/M1_A1" +Ne 83 "/FPGA_Spartan6/M1_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 90 "/FPGA_Spartan6/M1_A2" +Ne 86 "/FPGA_Spartan6/M1_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 91 "/FPGA_Spartan6/M1_A3" +Ne 87 "/FPGA_Spartan6/M1_A3" Po 3838 2176 $EndPAD $PAD @@ -5896,56 +5896,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 92 "/FPGA_Spartan6/M1_A4" +Ne 88 "/FPGA_Spartan6/M1_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 17 "/DDR_Banks/M1_A5" +Ne 89 "/FPGA_Spartan6/M1_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 93 "/FPGA_Spartan6/M1_A6" +Ne 90 "/FPGA_Spartan6/M1_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 94 "/FPGA_Spartan6/M1_A7" +Ne 91 "/FPGA_Spartan6/M1_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 95 "/FPGA_Spartan6/M1_A8" +Ne 92 "/FPGA_Spartan6/M1_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 96 "/FPGA_Spartan6/M1_A9" +Ne 93 "/FPGA_Spartan6/M1_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 89 "/FPGA_Spartan6/M1_A11" +Ne 85 "/FPGA_Spartan6/M1_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 16 "/DDR_Banks/M1_A12" +Ne 25 "/DDR_Banks/M1_A12" Po 2047 -2176 $EndPAD $PAD @@ -5959,28 +5959,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 19 "/DDR_Banks/M1_CLK#" +Ne 97 "/FPGA_Spartan6/M1_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 99 "/FPGA_Spartan6/M1_CKE" +Ne 95 "/FPGA_Spartan6/M1_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 100 "/FPGA_Spartan6/M1_CLK" +Ne 96 "/FPGA_Spartan6/M1_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 112 "/FPGA_Spartan6/M1_UDM" +Ne 111 "/FPGA_Spartan6/M1_UDM" Po 767 -2176 $EndPAD $PAD @@ -6008,7 +6008,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 113 "/FPGA_Spartan6/M1_UDQS" +Ne 112 "/FPGA_Spartan6/M1_UDQS" Po -255 -2176 $EndPAD $PAD @@ -6029,7 +6029,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 109 "/FPGA_Spartan6/M1_DQ8" +Ne 108 "/FPGA_Spartan6/M1_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6043,14 +6043,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 26 "/DDR_Banks/M1_DQ9" +Ne 109 "/FPGA_Spartan6/M1_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 102 "/FPGA_Spartan6/M1_DQ10" +Ne 28 "/DDR_Banks/M1_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -6064,14 +6064,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 103 "/FPGA_Spartan6/M1_DQ11" +Ne 29 "/DDR_Banks/M1_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 21 "/DDR_Banks/M1_DQ12" +Ne 100 "/FPGA_Spartan6/M1_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6085,14 +6085,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 104 "/FPGA_Spartan6/M1_DQ13" +Ne 101 "/FPGA_Spartan6/M1_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 105 "/FPGA_Spartan6/M1_DQ14" +Ne 102 "/FPGA_Spartan6/M1_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -6106,7 +6106,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 22 "/DDR_Banks/M1_DQ15" +Ne 103 "/FPGA_Spartan6/M1_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -6142,7 +6142,7 @@ $PAD Sh "2" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 72 "/FPGA_Spartan6/M0_DQ0" +Ne 11 "/DDR_Banks/M0_DQ0" Po -3838 2176 $EndPAD $PAD @@ -6156,14 +6156,14 @@ $PAD Sh "4" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 73 "/FPGA_Spartan6/M0_DQ1" +Ne 74 "/FPGA_Spartan6/M0_DQ1" Po -3326 2176 $EndPAD $PAD Sh "5" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 79 "/FPGA_Spartan6/M0_DQ2" +Ne 13 "/DDR_Banks/M0_DQ2" Po -3070 2176 $EndPAD $PAD @@ -6184,7 +6184,7 @@ $PAD Sh "8" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 81 "/FPGA_Spartan6/M0_DQ4" +Ne 14 "/DDR_Banks/M0_DQ4" Po -2303 2176 $EndPAD $PAD @@ -6198,14 +6198,14 @@ $PAD Sh "10" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 82 "/FPGA_Spartan6/M0_DQ5" +Ne 15 "/DDR_Banks/M0_DQ5" Po -1791 2176 $EndPAD $PAD Sh "11" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 83 "/FPGA_Spartan6/M0_DQ6" +Ne 16 "/DDR_Banks/M0_DQ6" Po -1535 2176 $EndPAD $PAD @@ -6219,7 +6219,7 @@ $PAD Sh "13" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 84 "/FPGA_Spartan6/M0_DQ7" +Ne 81 "/FPGA_Spartan6/M0_DQ7" Po -1023 2176 $EndPAD $PAD @@ -6240,7 +6240,7 @@ $PAD Sh "16" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 10 "/DDR_Banks/M0_LDQS" +Ne 20 "/DDR_Banks/M0_LDQS" Po -255 2176 $EndPAD $PAD @@ -6268,28 +6268,28 @@ $PAD Sh "20" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 9 "/DDR_Banks/M0_LDM" +Ne 19 "/DDR_Banks/M0_LDM" Po 767 2176 $EndPAD $PAD Sh "21" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 88 "/FPGA_Spartan6/M0_WE#" +Ne 23 "/DDR_Banks/M0_WE#" Po 1023 2176 $EndPAD $PAD Sh "22" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 68 "/FPGA_Spartan6/M0_CAS#" +Ne 70 "/FPGA_Spartan6/M0_CAS#" Po 1279 2176 $EndPAD $PAD Sh "23" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 87 "/FPGA_Spartan6/M0_RAS#" +Ne 82 "/FPGA_Spartan6/M0_RAS#" Po 1535 2176 $EndPAD $PAD @@ -6310,49 +6310,49 @@ $PAD Sh "26" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 67 "/FPGA_Spartan6/M0_BA0" +Ne 69 "/FPGA_Spartan6/M0_BA0" Po 2302 2176 $EndPAD $PAD Sh "27" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 7 "/DDR_Banks/M0_BA1" +Ne 10 "/DDR_Banks/M0_BA1" Po 2558 2176 $EndPAD $PAD Sh "28" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 58 "/FPGA_Spartan6/M0_A10" +Ne 6 "/DDR_Banks/M0_A10" Po 2814 2176 $EndPAD $PAD Sh "29" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 56 "/FPGA_Spartan6/M0_A0" +Ne 5 "/DDR_Banks/M0_A0" Po 3070 2176 $EndPAD $PAD Sh "30" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 57 "/FPGA_Spartan6/M0_A1" +Ne 61 "/FPGA_Spartan6/M0_A1" Po 3326 2176 $EndPAD $PAD Sh "31" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 61 "/FPGA_Spartan6/M0_A2" +Ne 63 "/FPGA_Spartan6/M0_A2" Po 3582 2176 $EndPAD $PAD Sh "32" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 5 "/DDR_Banks/M0_A3" +Ne 8 "/DDR_Banks/M0_A3" Po 3838 2176 $EndPAD $PAD @@ -6373,56 +6373,56 @@ $PAD Sh "35" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 62 "/FPGA_Spartan6/M0_A4" +Ne 64 "/FPGA_Spartan6/M0_A4" Po 3838 -2176 $EndPAD $PAD Sh "36" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 6 "/DDR_Banks/M0_A5" +Ne 65 "/FPGA_Spartan6/M0_A5" Po 3582 -2176 $EndPAD $PAD Sh "37" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 63 "/FPGA_Spartan6/M0_A6" +Ne 66 "/FPGA_Spartan6/M0_A6" Po 3326 -2176 $EndPAD $PAD Sh "38" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 64 "/FPGA_Spartan6/M0_A7" +Ne 67 "/FPGA_Spartan6/M0_A7" Po 3070 -2176 $EndPAD $PAD Sh "39" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 65 "/FPGA_Spartan6/M0_A8" +Ne 9 "/DDR_Banks/M0_A8" Po 2814 -2176 $EndPAD $PAD Sh "40" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 66 "/FPGA_Spartan6/M0_A9" +Ne 68 "/FPGA_Spartan6/M0_A9" Po 2558 -2176 $EndPAD $PAD Sh "41" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 59 "/FPGA_Spartan6/M0_A11" +Ne 7 "/DDR_Banks/M0_A11" Po 2303 -2176 $EndPAD $PAD Sh "42" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 60 "/FPGA_Spartan6/M0_A12" +Ne 62 "/FPGA_Spartan6/M0_A12" Po 2047 -2176 $EndPAD $PAD @@ -6436,28 +6436,28 @@ $PAD Sh "44" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 71 "/FPGA_Spartan6/M0_CLK#" +Ne 73 "/FPGA_Spartan6/M0_CLK#" Po 1535 -2176 $EndPAD $PAD Sh "45" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 69 "/FPGA_Spartan6/M0_CKE" +Ne 71 "/FPGA_Spartan6/M0_CKE" Po 1279 -2176 $EndPAD $PAD Sh "46" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 70 "/FPGA_Spartan6/M0_CLK" +Ne 72 "/FPGA_Spartan6/M0_CLK" Po 1023 -2176 $EndPAD $PAD Sh "47" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 11 "/DDR_Banks/M0_UDM" +Ne 21 "/DDR_Banks/M0_UDM" Po 767 -2176 $EndPAD $PAD @@ -6485,7 +6485,7 @@ $PAD Sh "51" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 12 "/DDR_Banks/M0_UDQS" +Ne 22 "/DDR_Banks/M0_UDQS" Po -255 -2176 $EndPAD $PAD @@ -6506,7 +6506,7 @@ $PAD Sh "54" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 85 "/FPGA_Spartan6/M0_DQ8" +Ne 17 "/DDR_Banks/M0_DQ8" Po -1023 -2176 $EndPAD $PAD @@ -6520,14 +6520,14 @@ $PAD Sh "56" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 86 "/FPGA_Spartan6/M0_DQ9" +Ne 18 "/DDR_Banks/M0_DQ9" Po -1535 -2176 $EndPAD $PAD Sh "57" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 74 "/FPGA_Spartan6/M0_DQ10" +Ne 75 "/FPGA_Spartan6/M0_DQ10" Po -1791 -2176 $EndPAD $PAD @@ -6541,14 +6541,14 @@ $PAD Sh "59" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 75 "/FPGA_Spartan6/M0_DQ11" +Ne 76 "/FPGA_Spartan6/M0_DQ11" Po -2303 -2176 $EndPAD $PAD Sh "60" R 137 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 76 "/FPGA_Spartan6/M0_DQ12" +Ne 77 "/FPGA_Spartan6/M0_DQ12" Po -2558 -2176 $EndPAD $PAD @@ -6562,14 +6562,14 @@ $PAD Sh "62" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 8 "/DDR_Banks/M0_DQ13" +Ne 12 "/DDR_Banks/M0_DQ13" Po -3070 -2176 $EndPAD $PAD Sh "63" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 77 "/FPGA_Spartan6/M0_DQ14" +Ne 78 "/FPGA_Spartan6/M0_DQ14" Po -3326 -2176 $EndPAD $PAD @@ -6583,7 +6583,7 @@ $PAD Sh "65" R 138 275 0 0 900 Dr 0 0 0 At SMD N 00888000 -Ne 78 "/FPGA_Spartan6/M0_DQ15" +Ne 79 "/FPGA_Spartan6/M0_DQ15" Po -3838 -2176 $EndPAD $PAD @@ -6611,7 +6611,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 163 "N-000340" +Ne 163 "N-000338" Po -176 0 $EndPAD $PAD @@ -6639,7 +6639,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 152 "N-000316" +Ne 152 "N-000314" Po -176 0 $EndPAD $PAD @@ -6651,7 +6651,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 50591 24409 2700 0 4C5FF890 4C5D71DB ~~ +Po 51575 24409 2700 0 4C5FF890 4C5D71DB ~~ Li 0402 Sc 4C5D71DB AR /4C4320F3/4C5D71DB @@ -6667,19 +6667,19 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 161 "N-000333" +Ne 161 "N-000331" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 34 "/Ethernet_Phy/ETH_LED1" +Ne 41 "/Ethernet_Phy/ETH_LED1" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51181 24409 2700 0 4C5FF890 4C5D719D ~~ +Po 52165 24409 2700 0 4C5FF890 4C5D719D ~~ Li 0402 Sc 4C5D719D AR /4C4320F3/4C5D719D @@ -6695,14 +6695,14 @@ $PAD Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 153 "N-000317" +Ne 153 "N-000315" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 33 "/Ethernet_Phy/ETH_LED0" +Ne 40 "/Ethernet_Phy/ETH_LED0" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6730,7 +6730,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 158 "N-000329" +Ne 158 "N-000327" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6758,7 +6758,7 @@ $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 155 "N-000320" +Ne 155 "N-000318" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6786,7 +6786,7 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 159 "N-000330" +Ne 159 "N-000328" Po 176 0 $EndPAD $EndMODULE 0402 @@ -6814,12 +6814,12 @@ $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 154 "N-000319" +Ne 154 "N-000317" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 48819 25394 1800 0 4C5FF890 4C5D7ECF ~~ +Po 49803 25394 1800 0 4C5FF890 4C5D7ECF ~~ Li 0402 Sc 4C5D7ECF AR /4C4320F3/4C5D7ECF @@ -6835,7 +6835,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 157 "N-000328" +Ne 157 "N-000326" Po -176 0 $EndPAD $PAD @@ -6863,7 +6863,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00440001 -Ne 35 "/Ethernet_Phy/ETH_MDIO" +Ne 42 "/Ethernet_Phy/ETH_MDIO" Po -176 0 $EndPAD $PAD @@ -6891,7 +6891,7 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 163 "N-000340" +Ne 163 "N-000338" Po -176 0 $EndPAD $PAD @@ -6919,7 +6919,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 152 "N-000316" +Ne 152 "N-000314" Po -176 0 $EndPAD $PAD @@ -6931,7 +6931,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 50787 27953 0 0 4C5FF890 4C5D7E43 ~~ +Po 51771 27953 0 0 4C5FF890 4C5D7E43 ~~ Li 0402 Sc 4C5D7E43 AR /4C4320F3/4C5D7E43 @@ -6959,7 +6959,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 51969 25787 2700 0 4C5FF890 4C5D7E41 ~~ +Po 52953 25787 2700 0 4C5FF890 4C5D7E41 ~~ Li 0402 Sc 4C5D7E41 AR /4C4320F3/4C5D7E41 @@ -7003,19 +7003,19 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "N-000331" +Ne 160 "N-000329" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 49606 25984 0 0 4C5FF890 4C5D7FA7 ~~ +Po 50590 25984 0 0 4C5FF890 4C5D7FA7 ~~ Li 0402 Sc 4C5D7FA7 AR /4C4320F3/4C5D7FA7 @@ -7031,7 +7031,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00440001 -Ne 31 "/Ethernet_Phy/ETH_A3.3V" +Ne 36 "/Ethernet_Phy/ETH_A3.3V" Po -176 0 $EndPAD $PAD @@ -7059,14 +7059,14 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/Ethernet_Phy/ETH_A1.8V" +Ne 35 "/Ethernet_Phy/ETH_A1.8V" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 160 "N-000331" +Ne 160 "N-000329" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7115,14 +7115,14 @@ $PAD Sh "1" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 156 "N-000323" +Ne 156 "N-000321" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 160 "N-000331" +Ne 160 "N-000329" Po 176 0 $EndPAD $EndMODULE 0402 @@ -7171,7 +7171,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 29 "/Ethernet_Phy/ETH_1.8V" +Ne 34 "/Ethernet_Phy/ETH_1.8V" Po -176 0 $EndPAD $PAD @@ -7199,7 +7199,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 162 "N-000339" +Ne 162 "N-000337" Po -294 0 $EndPAD $PAD @@ -7227,7 +7227,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 173 "N-000358" +Ne 173 "N-000356" Po -294 0 $EndPAD $PAD @@ -7255,14 +7255,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/Ethernet_Phy/ETH_A1.8V" +Ne 35 "/Ethernet_Phy/ETH_A1.8V" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 36 "/Ethernet_Phy/ETH_PLL1.8V" +Ne 43 "/Ethernet_Phy/ETH_PLL1.8V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7290,7 +7290,7 @@ $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A3.3V" +Ne 36 "/Ethernet_Phy/ETH_A3.3V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7311,14 +7311,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 156 "N-000323" +Ne 156 "N-000321" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 30 "/Ethernet_Phy/ETH_A1.8V" +Ne 35 "/Ethernet_Phy/ETH_A1.8V" Po 294 0 $EndPAD $EndMODULE 0603 @@ -7339,7 +7339,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 172 "N-000357" +Ne 172 "N-000355" Po -294 0 $EndPAD $PAD @@ -7367,7 +7367,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 172 "N-000357" +Ne 172 "N-000355" Po -294 0 $EndPAD $PAD @@ -7395,7 +7395,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 172 "N-000357" +Ne 172 "N-000355" Po -294 0 $EndPAD $PAD @@ -7423,7 +7423,7 @@ $PAD Sh "1" R 197 354 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 31 "/Ethernet_Phy/ETH_A3.3V" +Ne 36 "/Ethernet_Phy/ETH_A3.3V" Po -294 0 $EndPAD $PAD @@ -7479,7 +7479,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 171 "N-000356" +Ne 171 "N-000354" Po -570 0 $EndPAD $PAD @@ -7512,251 +7512,251 @@ $PAD Sh "1" R 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 170 "N-000355" +Ne 170 "N-000353" Po 0 -2362 $EndPAD $PAD Sh "2" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 162 "N-000339" +Ne 162 "N-000337" Po 0 -1575 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 173 "N-000358" +Ne 173 "N-000356" Po 0 -787 $EndPAD $PAD Sh "3" C 470 470 0 0 1800 Dr 360 0 0 At STD N 0CC0FFFF -Ne 173 "N-000358" +Ne 173 "N-000356" Po 0 0 $EndPAD $PAD Sh "S1" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 163 "N-000340" +Ne 163 "N-000338" Po 1077 287 $EndPAD $PAD Sh "S2" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 163 "N-000340" +Ne 163 "N-000338" Po -1077 287 $EndPAD $PAD Sh "S3" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 163 "N-000340" +Ne 163 "N-000338" Po 1077 -2468 $EndPAD $PAD Sh "S4" C 670 670 0 0 1800 Dr 532 0 0 At STD N 0CC0FFFF -Ne 163 "N-000340" +Ne 163 "N-000338" Po -1077 -2468 $EndPAD $EndMODULE USB-48204 $MODULE 0402 -Po 45000 29500 0 15 4C5FF890 4C61CC73 ~~ +Po 47441 32874 900 0 4C5FF890 4C61CC73 ~~ Li 0402 Sc 4C61CC73 AR /4C421DD3/4C61CC73 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C17" -T1 0 150 200 200 0 40 N I 25 N"100nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 900 40 M V 20 N"C17" +T1 0 -150 200 200 900 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 900 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 900 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 149 "N-000052" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 46000 29000 0 15 4C5FF890 4C61CC96 ~~ +Po 47441 33661 2700 0 4C5FF890 4C61CC96 ~~ Li 0402 Sc 4C61CC96 AR /4C421DD3/4C61CC96 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C18" -T1 0 150 200 200 0 40 N I 25 N"100nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 2700 40 M V 20 N"C18" +T1 0 -150 200 200 2700 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 2700 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 149 "N-000052" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 2700 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 150 "N-000054" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 62205 29134 0 15 4C5FF890 4C61CCE2 ~~ +Po 62205 33858 0 0 4C5FF890 4C61CCE2 ~~ Li 0402 Sc 4C61CCE2 AR /4C421DD3/4C61CCE2 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C20" -T1 0 150 200 200 0 40 N I 25 N"100nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 0 40 M V 20 N"C20" +T1 0 -150 200 200 0 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 148 "N-000051" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 147 "N-000050" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 63976 28937 0 15 4C5FF890 4C61CCE3 ~~ +Po 62205 33071 1800 0 4C5FF890 4C61CCE3 ~~ Li 0402 Sc 4C61CCE3 AR /4C421DD3/4C61CCE3 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C19" -T1 0 150 200 200 0 40 N I 25 N"100nF" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"C19" +T1 0 -150 200 200 1800 40 M I 20 N"100nF" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 148 "N-000051" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 45000 34500 0 15 4C5FF890 4C61CD4A ~~ +Po 48031 32874 900 0 4C5FF890 4C61CD4A ~~ Li 0402 Sc 4C61CD4A AR /4C421DD3/4C61CD4A Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"R11" -T1 0 150 200 200 0 40 N I 25 N"1K_1%" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 900 40 M V 20 N"R11" +T1 0 -150 200 200 900 40 M I 20 N"1K_1%" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 900 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 900 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 149 "N-000052" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 45000 33500 0 15 4C5FF890 4C61CDB5 ~~ +Po 48031 33661 2700 0 4C5FF890 4C61CDB5 ~~ Li 0402 Sc 4C61CDB5 AR /4C421DD3/4C61CDB5 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"R12" -T1 0 150 200 200 0 40 N I 25 N"1K_1%" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 2700 40 M V 20 N"R12" +T1 0 -150 200 200 2700 40 M I 20 N"1K_1%" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 2700 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 149 "N-000052" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 2700 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 150 "N-000054" Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 65000 29000 0 15 4C5FF890 4C61CE31 ~~ +Po 62205 32677 1800 0 4C5FF890 4C61CE31 ~~ Li 0402 Sc 4C61CE31 AR /4C421DD3/4C61CE31 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"R13" -T1 0 150 200 200 0 40 N I 25 N"1K_1%" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 1800 40 M V 20 N"R13" +T1 0 -150 200 200 1800 40 M I 20 N"1K_1%" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 2 "+2.5V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 1800 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 148 "N-000051" Po 176 0 $EndPAD @@ -8042,7 +8042,7 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0603 -Po 45079 36811 0 0 4C5FF890 4C61CF2F ~~ +Po 49016 29921 0 0 4C5FF890 4C61CF2F ~~ Li 0603 Sc 4C61CF2F AR /4C421DD3/4C61CF2F @@ -8098,29 +8098,29 @@ Po 294 0 $EndPAD $EndMODULE 0603 $MODULE 0402 -Po 63000 29000 0 15 4C5FF890 4C61CE30 ~~ +Po 62205 33465 0 0 4C5FF890 4C61CE30 ~~ Li 0402 Sc 4C61CE30 AR /4C421DD3/4C61CE30 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"R14" -T1 0 150 200 200 0 40 N I 25 N"1K_1%" -DS -305 168 -305 -168 50 21 -DS -305 -168 305 -168 50 21 -DS 305 -168 305 168 50 21 -DS 305 168 -305 168 50 21 +T0 0 150 200 200 0 40 M V 20 N"R14" +T1 0 -150 200 200 0 40 M I 20 N"1K_1%" +DS -305 -168 -305 168 50 20 +DS -305 168 305 168 50 20 +DS 305 168 305 -168 50 20 +DS 305 -168 -305 -168 50 20 $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 148 "N-000051" Po -176 0 $EndPAD $PAD Sh "2" R 157 236 0 0 0 Dr 0 0 0 -At SMD N 00888000 +At SMD N 00440001 Ne 147 "N-000050" Po 176 0 $EndPAD @@ -8142,7 +8142,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 166 "N-000351" +Ne 166 "N-000349" Po -294 0 $EndPAD $PAD @@ -8170,14 +8170,14 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 171 "N-000356" +Ne 171 "N-000354" Po -294 0 $EndPAD $PAD Sh "2" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 170 "N-000355" +Ne 170 "N-000353" Po 294 0 $EndPAD $EndMODULE 0603 @@ -8198,7 +8198,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 164 "N-000341" +Ne 164 "N-000339" Po -294 0 $EndPAD $PAD @@ -8254,7 +8254,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "N-000354" +Ne 169 "N-000352" Po -176 0 $EndPAD $PAD @@ -8282,7 +8282,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 169 "N-000354" +Ne 169 "N-000352" Po -176 0 $EndPAD $PAD @@ -8310,7 +8310,7 @@ $PAD Sh "1" R 157 236 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "N-000353" +Ne 168 "N-000351" Po -176 0 $EndPAD $PAD @@ -8338,7 +8338,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 167 "N-000352" +Ne 167 "N-000350" Po -294 0 $EndPAD $PAD @@ -8366,7 +8366,7 @@ $PAD Sh "1" R 197 354 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 165 "N-000347" +Ne 165 "N-000345" Po -294 0 $EndPAD $PAD @@ -8394,7 +8394,7 @@ $PAD Sh "1" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "N-000353" +Ne 168 "N-000351" Po -373 0 $EndPAD $PAD @@ -8422,7 +8422,7 @@ $PAD Sh "1" R 275 510 0 0 0 Dr 0 0 0 At SMD N 00888000 -Ne 168 "N-000353" +Ne 168 "N-000351" Po -373 0 $EndPAD $PAD @@ -8450,7 +8450,7 @@ $PAD Sh "1" R 355 984 0 0 1800 Dr 0 0 0 At SMD N 00888000 -Ne 164 "N-000341" +Ne 164 "N-000339" Po -570 0 $EndPAD $PAD @@ -8549,14 +8549,14 @@ $PAD Sh "10" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 167 "N-000352" +Ne 167 "N-000350" Po 255 1112 $EndPAD $PAD Sh "11" R 137 570 0 0 2700 Dr 0 0 0 At SMD N 00440001 -Ne 165 "N-000347" +Ne 165 "N-000345" Po 0 1112 $EndPAD $PAD @@ -9507,42 +9507,42 @@ $PAD Sh "1" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 120 "/FPGA_Spartan6/PROG_CSO" +Ne 119 "/FPGA_Spartan6/PROG_CSO" Po -750 1050 $EndPAD $PAD Sh "7" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 124 "/FPGA_Spartan6/PROG_MISO3" +Ne 123 "/FPGA_Spartan6/PROG_MISO3" Po -250 -1050 $EndPAD $PAD Sh "6" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 119 "/FPGA_Spartan6/PROG_CCLK" +Ne 118 "/FPGA_Spartan6/PROG_CCLK" Po 250 -1050 $EndPAD $PAD Sh "5" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 121 "/FPGA_Spartan6/PROG_MISO0" +Ne 120 "/FPGA_Spartan6/PROG_MISO0" Po 750 -1050 $EndPAD $PAD Sh "2" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 122 "/FPGA_Spartan6/PROG_MISO1" +Ne 121 "/FPGA_Spartan6/PROG_MISO1" Po -250 1050 $EndPAD $PAD Sh "3" R 200 450 0 0 2700 Dr 0 0 0 At SMD N 00888000 -Ne 123 "/FPGA_Spartan6/PROG_MISO2" +Ne 122 "/FPGA_Spartan6/PROG_MISO2" Po 250 1050 $EndPAD $PAD @@ -9616,27 +9616,27 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 55906 23031 0 15 4C5FF890 4C65D736 ~~ +Po 54528 26181 900 15 4C5FF890 4C65D736 ~~ Li 0402 Sc 4C65D736 AR /4C4227FE/4C65D661 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C72" -T1 0 150 200 200 0 40 N I 25 N"100nF" +T0 0 -150 200 200 900 40 N V 25 N"C72" +T1 0 150 200 200 900 40 N I 25 N"100nF" DS -305 168 -305 -168 50 21 DS -305 -168 305 -168 50 21 DS 305 -168 305 168 50 21 DS 305 168 -305 168 50 21 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 3 "+3.3V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 146 "GND" @@ -9644,27 +9644,27 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0402 -Po 57874 23228 0 15 4C5FF890 4C65D738 ~~ +Po 63780 26575 2700 15 4C5FF890 4C65D738 ~~ Li 0402 Sc 4C65D738 AR /4C4227FE/4C65D67C Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C73" -T1 0 150 200 200 0 40 N I 25 N"100nF" +T0 0 -150 200 200 2700 40 N V 25 N"C73" +T1 0 150 200 200 2700 40 N I 25 N"100nF" DS -305 168 -305 -168 50 21 DS -305 -168 305 -168 50 21 DS 305 -168 305 168 50 21 DS 305 168 -305 168 50 21 $PAD -Sh "1" R 157 236 0 0 0 +Sh "1" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 Ne 3 "+3.3V" Po -176 0 $EndPAD $PAD -Sh "2" R 157 236 0 0 0 +Sh "2" R 157 236 0 0 2700 Dr 0 0 0 At SMD N 00888000 Ne 146 "GND" @@ -9672,33 +9672,43 @@ Po 176 0 $EndPAD $EndMODULE 0402 $MODULE 0603 -Po 60039 23228 0 15 4C5FF890 4C65D739 ~~ +Po 54528 24803 900 15 4C5FF890 4C65D739 ~~ Li 0603 Sc 4C65D739 AR /4C4227FE/4C65D681 Op 0 0 0 At SMD -T0 0 -150 200 200 0 40 N V 25 N"C74" -T1 0 150 200 200 0 40 N I 25 N"1uF" +T0 0 -150 200 200 900 40 N V 25 N"C74" +T1 0 150 200 200 900 40 N I 25 N"1uF" DS -443 227 -443 -227 50 21 DS -443 -227 443 -227 50 21 DS 443 -227 443 227 50 21 DS 443 227 -443 227 50 21 $PAD -Sh "1" R 197 354 0 0 0 +Sh "1" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 3 "+3.3V" Po -294 0 $EndPAD $PAD -Sh "2" R 197 354 0 0 0 +Sh "2" R 197 354 0 0 900 Dr 0 0 0 At SMD N 00888000 Ne 146 "GND" Po 294 0 $EndPAD $EndMODULE 0603 +$TEXTPCB +Te "otra fuente" +Po 65945 22244 600 800 120 0 +De 0 1 0 Normal +$EndTEXTPCB +$TEXTPCB +Te "Una fuente por acá" +Po 44291 26772 600 800 120 0 +De 0 1 0 Normal +$EndTEXTPCB $COTATION Ge 0 24 0 Va 21654 @@ -9729,4 +9739,16 @@ $TRACK $EndTRACK $ZONE $EndZONE +$CZONE_OUTLINE +ZInfo 4C65DF3E 0 "" +ZLayer 15 +ZAux 4 N +ZClearance 200 T +ZMinThickness 100 +ZOptions 0 16 F 200 200 +ZCorner 67126 44685 0 +ZCorner 67126 14567 0 +ZCorner 45079 14567 0 +ZCorner 45079 44685 1 +$endCZONE_OUTLINE $EndBOARD diff --git a/kicad/xue-rnc/xue-rnc.net b/kicad/xue-rnc/xue-rnc.net index 488e748..537ab02 100644 --- a/kicad/xue-rnc/xue-rnc.net +++ b/kicad/xue-rnc/xue-rnc.net @@ -1,4 +1,4 @@ -# EESchema Netlist Version 1.1 created Fri 13 Aug 2010 06:37:14 PM COT +# EESchema Netlist Version 1.1 created Fri 13 Aug 2010 07:14:02 PM COT ( ( /4C4227FE/4C65D681 0603 C74 1uF {Lib=CAP} ( 1 +3.3V ) @@ -27,13 +27,13 @@ ( COM GND ) ( CD ? ) ( 1 /Non_volatile_memories/SD_DAT2 ) - ( 2 /FPGA_Spartan6/SD_DAT3 ) + ( 2 /Non_volatile_memories/SD_DAT3 ) ( 3 /FPGA_Spartan6/SD_CMD ) ( 4 ? ) ( 5 /FPGA_Spartan6/SD_CLK ) ( 6 GND ) - ( 7 /FPGA_Spartan6/SD_DAT0 ) - ( 8 /Non_volatile_memories/SD_DAT1 ) + ( 7 /Non_volatile_memories/SD_DAT0 ) + ( 8 /FPGA_Spartan6/SD_DAT1 ) ) ( /4C4227FE/4B76F108 $noname U5 NAND {Lib=HY27UG088G5M} ( 1 ? ) @@ -43,7 +43,7 @@ ( 5 ? ) ( 6 /FPGA_Spartan6/NF_RNB ) ( 7 /FPGA_Spartan6/NF_RNB ) - ( 8 /Non_volatile_memories/NF_RE_N ) + ( 8 /FPGA_Spartan6/NF_RE_N ) ( 9 /Non_volatile_memories/NF_CS1_N ) ( 10 ? ) ( 11 ? ) @@ -51,9 +51,9 @@ ( 13 GND ) ( 14 ? ) ( 15 ? ) - ( 16 /FPGA_Spartan6/NF_CLE ) - ( 17 /Non_volatile_memories/NF_ALE ) - ( 18 /FPGA_Spartan6/NF_WE_N ) + ( 16 /Non_volatile_memories/NF_CLE ) + ( 17 /FPGA_Spartan6/NF_ALE ) + ( 18 /Non_volatile_memories/NF_WE_N ) ( 19 3.3V ) ( 20 ? ) ( 21 ? ) @@ -65,8 +65,8 @@ ( 27 ? ) ( 28 ? ) ( 29 /Non_volatile_memories/NF_D0 ) - ( 30 /FPGA_Spartan6/NF_D1 ) - ( 31 /Non_volatile_memories/NF_D2 ) + ( 30 /Non_volatile_memories/NF_D1 ) + ( 31 /FPGA_Spartan6/NF_D2 ) ( 32 /Non_volatile_memories/NF_D3 ) ( 33 ? ) ( 34 ? ) @@ -76,7 +76,7 @@ ( 38 ? ) ( 39 ? ) ( 40 ? ) - ( 41 /FPGA_Spartan6/NF_D4 ) + ( 41 /Non_volatile_memories/NF_D4 ) ( 42 /Non_volatile_memories/NF_D5 ) ( 43 /Non_volatile_memories/NF_D6 ) ( 44 /Non_volatile_memories/NF_D7 ) @@ -94,41 +94,41 @@ ( 7 GND ) ( 8 GND ) ( 9 ? ) - ( 10 N-000352 ) - ( 11 N-000347 ) + ( 10 N-000350 ) + ( 11 N-000345 ) ( 12 3.3V ) ( 14 3.3V ) ) ( /4C5F1EDC/4C6552BE $noname C35 1uF {Lib=C} - ( 1 N-000353 ) + ( 1 N-000351 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552BD $noname C36 1uF {Lib=C} - ( 1 N-000353 ) + ( 1 N-000351 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552BC $noname C37 470nF {Lib=C} - ( 1 N-000353 ) + ( 1 N-000351 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552BA $noname F2 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000341 ) + ( 1 N-000339 ) ( 2 +5V ) ) ( /4C5F1EDC/4C6552B9 $noname V4 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000352 ) + ( 1 N-000350 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B8 $noname V3 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000347 ) + ( 1 N-000345 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B7 $noname C38 4.7nF {Lib=C} - ( 1 N-000354 ) + ( 1 N-000352 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B6 $noname R15 1M {Lib=R} - ( 1 N-000354 ) + ( 1 N-000352 ) ( 2 GND ) ) ( /4C5F1EDC/4C6552B1 0603 L7 FB {Lib=INDUCTOR} @@ -136,70 +136,70 @@ ( 2 GND ) ) ( /4C5F1EDC/4C6552B0 0603 L6 FB {Lib=INDUCTOR} - ( 1 N-000341 ) + ( 1 N-000339 ) ( 2 ? ) ) ( /4C5F1EDC/4C63F252 0603 L4 FB {Lib=INDUCTOR} - ( 1 N-000356 ) - ( 2 N-000355 ) + ( 1 N-000354 ) + ( 2 N-000353 ) ) ( /4C5F1EDC/4C63F248 0603 L5 FB {Lib=INDUCTOR} - ( 1 N-000351 ) + ( 1 N-000349 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D27 $noname R10 1M {Lib=R} - ( 1 N-000340 ) + ( 1 N-000338 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2D1E $noname C16 4.7nF {Lib=C} - ( 1 N-000340 ) + ( 1 N-000338 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA7 $noname V1 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000358 ) + ( 1 N-000356 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2CA3 $noname V2 V0402MHS03 {Lib=V0402MHS03} - ( 1 N-000339 ) + ( 1 N-000337 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2B55 $noname F1 MICROSMD075F {Lib=MICROSMD075F} - ( 1 N-000356 ) + ( 1 N-000354 ) ( 2 +5V ) ) ( /4C5F1EDC/4C5F23DD $noname J5 USB-48204-0001 {Lib=USB-48204-0001} - ( S1 N-000340 ) - ( S2 N-000340 ) - ( S3 N-000340 ) - ( S4 N-000340 ) - ( 1 N-000355 ) - ( 2 N-000339 ) - ( 3 N-000358 ) - ( 4 N-000351 ) + ( S1 N-000338 ) + ( S2 N-000338 ) + ( S3 N-000338 ) + ( S4 N-000338 ) + ( 1 N-000353 ) + ( 2 N-000337 ) + ( 3 N-000356 ) + ( 4 N-000349 ) ) ( /4C5F1EDC/4C5F2039 $noname C15 470nF {Lib=C} - ( 1 N-000357 ) + ( 1 N-000355 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2037 $noname C14 1uF {Lib=C} - ( 1 N-000357 ) + ( 1 N-000355 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2033 $noname C13 1uF {Lib=C} - ( 1 N-000357 ) + ( 1 N-000355 ) ( 2 GND ) ) ( /4C5F1EDC/4C5F2025 $noname U6 MIC2550AYTS {Lib=MIC2550AYTS} ( 1 +2.5V ) ( 2 /USB/USBA_SPD ) ( 3 /FPGA_Spartan6/USBA_RCV ) - ( 4 /FPGA_Spartan6/USBA_VP ) + ( 4 /USB/USBA_VP ) ( 5 /USB/USBA_VM ) ( 7 GND ) ( 8 GND ) - ( 9 /USB/USBA_OE_N ) - ( 10 N-000339 ) - ( 11 N-000358 ) + ( 9 /FPGA_Spartan6/USBA_OE_N ) + ( 10 N-000337 ) + ( 11 N-000356 ) ( 12 3.3V ) ( 14 3.3V ) ) @@ -357,7 +357,7 @@ ( E5 ? ) ( D5 ? ) ( U4 ? ) - ( H21 /FPGA_Spartan6/M1_RAS# ) + ( H21 /DDR_Banks/M1_RAS# ) ( G21 +2.5V ) ( F21 /DDR_Banks/M1_A0 ) ( D21 /FPGA_Spartan6/M1_CKE ) @@ -366,15 +366,15 @@ ( A21 ? ) ( W20 ? ) ( V20 ? ) - ( U20 /DDR_Banks/M1_DQ12 ) + ( U20 /FPGA_Spartan6/M1_DQ12 ) ( T20 ? ) - ( R20 /FPGA_Spartan6/M1_DQ10 ) + ( R20 /DDR_Banks/M1_DQ10 ) ( P20 ? ) ( N20 /FPGA_Spartan6/M1_DQ0 ) ( M20 /FPGA_Spartan6/M1_UDM ) - ( L20 /DDR_Banks/M1_LDQS ) - ( K20 /DDR_Banks/M1_A5 ) - ( J20 /FPGA_Spartan6/M1_DQ4 ) + ( L20 /FPGA_Spartan6/M1_LDQS ) + ( K20 /FPGA_Spartan6/M1_A5 ) + ( J20 /DDR_Banks/M1_DQ4 ) ( H20 /FPGA_Spartan6/M1_CLK ) ( G20 /FPGA_Spartan6/M1_A3 ) ( F20 /FPGA_Spartan6/M1_A4 ) @@ -392,13 +392,13 @@ ( V2 /FPGA_Spartan6/M0_DQ14 ) ( T2 /DDR_Banks/M0_UDQS ) ( R2 +2.5V ) - ( P2 /FPGA_Spartan6/M0_DQ8 ) - ( M2 /FPGA_Spartan6/M0_DQ2 ) + ( P2 /DDR_Banks/M0_DQ8 ) + ( M2 /DDR_Banks/M0_DQ2 ) ( L2 +2.5V ) - ( K2 /FPGA_Spartan6/M0_DQ6 ) - ( H2 /FPGA_Spartan6/M0_A0 ) + ( K2 /DDR_Banks/M0_DQ6 ) + ( H2 /DDR_Banks/M0_A0 ) ( G2 +2.5V ) - ( F2 /FPGA_Spartan6/M0_WE# ) + ( F2 /DDR_Banks/M0_WE# ) ( D2 /FPGA_Spartan6/M0_CKE ) ( C2 +2.5V ) ( B2 ? ) @@ -409,12 +409,12 @@ ( U1 /DDR_Banks/M0_DQ13 ) ( T1 ? ) ( R1 /FPGA_Spartan6/M0_DQ11 ) - ( P1 /FPGA_Spartan6/M0_DQ9 ) + ( P1 /DDR_Banks/M0_DQ9 ) ( N1 /FPGA_Spartan6/M0_DQ1 ) ( M1 /FPGA_Spartan6/M0_DQ3 ) ( L1 ? ) ( K1 /FPGA_Spartan6/M0_DQ7 ) - ( J1 /FPGA_Spartan6/M0_DQ5 ) + ( J1 /DDR_Banks/M0_DQ5 ) ( H1 /FPGA_Spartan6/M0_A1 ) ( G1 /DDR_Banks/M0_BA1 ) ( T4 ? ) @@ -426,7 +426,7 @@ ( K4 /FPGA_Spartan6/M0_CAS# ) ( J4 /FPGA_Spartan6/M0_A6 ) ( H4 /FPGA_Spartan6/M0_CLK ) - ( G4 /FPGA_Spartan6/M0_A10 ) + ( G4 /DDR_Banks/M0_A10 ) ( F4 +2.5V ) ( E4 ? ) ( C4 ? ) @@ -436,36 +436,36 @@ ( T3 ? ) ( R3 /FPGA_Spartan6/M0_DQ10 ) ( P3 ? ) - ( N3 /FPGA_Spartan6/M0_DQ0 ) + ( N3 /DDR_Banks/M0_DQ0 ) ( M3 /DDR_Banks/M0_UDM ) ( L3 /DDR_Banks/M0_LDQS ) - ( K3 /DDR_Banks/M0_A5 ) - ( J3 /FPGA_Spartan6/M0_DQ4 ) + ( K3 /FPGA_Spartan6/M0_A5 ) + ( J3 /DDR_Banks/M0_DQ4 ) ( H3 /FPGA_Spartan6/M0_CLK# ) ( G3 /FPGA_Spartan6/M0_BA0 ) ( F3 /FPGA_Spartan6/M0_A4 ) - ( E3 /FPGA_Spartan6/M0_A8 ) + ( E3 /DDR_Banks/M0_A8 ) ( D3 ? ) ( C3 ? ) ( G10 +3.3V ) - ( D10 /FPGA_Spartan6/ETH_RXC ) - ( C10 /FPGA_Spartan6/ETH_CLK ) + ( D10 /Ethernet_Phy/ETH_RXC ) + ( C10 /Ethernet_Phy/ETH_CLK ) ( B10 /FPGA_Spartan6/ETH_CRS ) - ( A10 /FPGA_Spartan6/ETH_COL ) + ( A10 /Ethernet_Phy/ETH_COL ) ( E9 +3.3V ) ( D9 /FPGA_Spartan6/ETH_TXEN ) - ( C9 /Ethernet_Phy/ETH_TXD1 ) - ( A9 /Ethernet_Phy/ETH_TXD2 ) - ( D8 /FPGA_Spartan6/ETH_TXC ) + ( C9 /FPGA_Spartan6/ETH_TXD1 ) + ( A9 /FPGA_Spartan6/ETH_TXD2 ) + ( D8 /Ethernet_Phy/ETH_TXC ) ( C8 /Ethernet_Phy/ETH_TXD0 ) - ( B8 /FPGA_Spartan6/ETH_RXER ) - ( A8 /FPGA_Spartan6/ETH_TXER ) - ( D7 /FPGA_Spartan6/ETH_TXD3 ) - ( C7 /Ethernet_Phy/ETH_RXD0 ) + ( B8 /Ethernet_Phy/ETH_RXER ) + ( A8 /Ethernet_Phy/ETH_TXER ) + ( D7 /Ethernet_Phy/ETH_TXD3 ) + ( C7 /FPGA_Spartan6/ETH_RXD0 ) ( B7 +3.3V ) - ( A7 /FPGA_Spartan6/ETH_RXDV ) + ( A7 /Ethernet_Phy/ETH_RXDV ) ( D6 /FPGA_Spartan6/ETH_RESET_N ) - ( C6 /Ethernet_Phy/ETH_RXD3 ) + ( C6 /FPGA_Spartan6/ETH_RXD3 ) ( B6 /FPGA_Spartan6/ETH_RXD2 ) ( A6 /Ethernet_Phy/ETH_RXD1 ) ( C5 /FPGA_Spartan6/ETH_MDC ) @@ -478,30 +478,30 @@ ( P19 ? ) ( N19 ? ) ( B19 +3.3V ) - ( B18 /Non_volatile_memories/SD_DAT1 ) - ( A18 /FPGA_Spartan6/SD_DAT0 ) + ( B18 /FPGA_Spartan6/SD_DAT1 ) + ( A18 /Non_volatile_memories/SD_DAT0 ) ( E17 +3.3V ) ( D17 /FPGA_Spartan6/SD_CMD ) - ( C17 /FPGA_Spartan6/SD_DAT3 ) + ( C17 /Non_volatile_memories/SD_DAT3 ) ( A17 /Non_volatile_memories/SD_DAT2 ) ( E16 /FPGA_Spartan6/SD_CLK ) ( C16 /Non_volatile_memories/NF_CS1_N ) - ( B16 /Non_volatile_memories/NF_RE_N ) + ( B16 /FPGA_Spartan6/NF_RE_N ) ( A16 /FPGA_Spartan6/NF_RNB ) - ( D15 /FPGA_Spartan6/NF_CLE ) - ( C15 /FPGA_Spartan6/NF_WE_N ) + ( D15 /Non_volatile_memories/NF_CLE ) + ( C15 /Non_volatile_memories/NF_WE_N ) ( B15 +3.3V ) - ( A15 /Non_volatile_memories/NF_ALE ) + ( A15 /FPGA_Spartan6/NF_ALE ) ( G14 +3.3V ) ( D14 /Non_volatile_memories/NF_D0 ) ( C14 ? ) ( B14 ? ) ( A14 ? ) ( E13 +3.3V ) - ( C13 /Non_volatile_memories/NF_D2 ) - ( A13 /FPGA_Spartan6/NF_D1 ) + ( C13 /FPGA_Spartan6/NF_D2 ) + ( A13 /Non_volatile_memories/NF_D1 ) ( C12 /Non_volatile_memories/NF_D5 ) - ( B12 /FPGA_Spartan6/NF_D4 ) + ( B12 /Non_volatile_memories/NF_D4 ) ( A12 /Non_volatile_memories/NF_D3 ) ( D11 /Non_volatile_memories/NF_D6 ) ( C11 ? ) @@ -512,19 +512,19 @@ ( F16 ? ) ( L15 ? ) ( W22 ? ) - ( V22 /DDR_Banks/M1_DQ15 ) + ( V22 /FPGA_Spartan6/M1_DQ15 ) ( U22 /FPGA_Spartan6/M1_DQ13 ) ( T22 ? ) - ( R22 /FPGA_Spartan6/M1_DQ11 ) - ( P22 /DDR_Banks/M1_DQ9 ) - ( N22 /DDR_Banks/M1_DQ1 ) + ( R22 /DDR_Banks/M1_DQ11 ) + ( P22 /FPGA_Spartan6/M1_DQ9 ) + ( N22 /FPGA_Spartan6/M1_DQ1 ) ( M22 /DDR_Banks/M1_DQ3 ) ( L22 ? ) - ( K22 /DDR_Banks/M1_DQ7 ) + ( K22 /FPGA_Spartan6/M1_DQ7 ) ( J22 /FPGA_Spartan6/M1_DQ5 ) ( H22 /FPGA_Spartan6/M1_CAS# ) ( G22 ? ) - ( F22 /DDR_Banks/M1_A1 ) + ( F22 /FPGA_Spartan6/M1_A1 ) ( E22 /FPGA_Spartan6/M1_A2 ) ( D22 /DDR_Banks/M1_A12 ) ( C22 /FPGA_Spartan6/M1_A9 ) @@ -536,29 +536,29 @@ ( P21 /FPGA_Spartan6/M1_DQ8 ) ( M21 /FPGA_Spartan6/M1_DQ2 ) ( L21 +2.5V ) - ( K21 /DDR_Banks/M1_DQ6 ) + ( K21 /FPGA_Spartan6/M1_DQ6 ) ( M19 ? ) - ( L19 /FPGA_Spartan6/M1_LDM ) + ( L19 /DDR_Banks/M1_LDM ) ( K19 /FPGA_Spartan6/M1_A6 ) - ( J19 /DDR_Banks/M1_CLK# ) - ( H19 /DDR_Banks/M1_WE# ) - ( G19 /DDR_Banks/M1_A10 ) + ( J19 /FPGA_Spartan6/M1_CLK# ) + ( H19 /FPGA_Spartan6/M1_WE# ) + ( G19 /FPGA_Spartan6/M1_A10 ) ( F19 /FPGA_Spartan6/M1_A11 ) ( E19 +2.5V ) ( D19 ? ) ( U18 +2.5V ) - ( P18 /USB/USBA_OE_N ) + ( P18 /FPGA_Spartan6/USBA_OE_N ) ( N18 +2.5V ) ( M18 /USB/USBA_VM ) ( K18 ? ) ( J18 +2.5V ) ( H18 ? ) ( F18 ? ) - ( P17 /FPGA_Spartan6/USBA_VP ) + ( P17 /USB/USBA_VP ) ( M17 ? ) ( L17 ? ) ( K17 /DDR_Banks/M1_BA1 ) - ( J17 /FPGA_Spartan6/M1_BA0 ) + ( J17 /DDR_Banks/M1_BA0 ) ( H17 ? ) ( G17 ? ) ( F17 ? ) @@ -589,7 +589,7 @@ ( N12 +1.2V ) ( M12 GND ) ( L12 +1.2V ) - ( K12 ? ) + ( K12 GND ) ( J12 +1.2V ) ( H12 ? ) ( G12 +2.5V ) @@ -672,7 +672,7 @@ ( H11 ? ) ( G11 ? ) ( F11 +2.5V ) - ( E11 ? ) + ( E11 GND ) ( V10 GND ) ( R10 +2.5V ) ( P10 GND ) @@ -695,7 +695,7 @@ ( V18 ? ) ( T18 ? ) ( AB7 ? ) - ( AA7 N-000124 ) + ( AA7 N-000147 ) ( Y17 ? ) ( W17 ? ) ( V17 ? ) @@ -704,7 +704,7 @@ ( AB6 ? ) ( AA6 ? ) ( Y16 ? ) - ( V16 N-000124 ) + ( V16 N-000147 ) ( U16 ? ) ( T16 ? ) ( R16 ? ) @@ -720,17 +720,17 @@ ( F1 ? ) ( E1 /FPGA_Spartan6/M0_A9 ) ( D1 /FPGA_Spartan6/M0_A12 ) - ( C1 /FPGA_Spartan6/M0_A11 ) + ( C1 /DDR_Banks/M0_A11 ) ( B1 ? ) ( AB19 ? ) - ( AA19 N-000124 ) + ( AA19 N-000147 ) ( AB18 ? ) ( AA18 ? ) ( AB17 ? ) ( AB16 ? ) ( AA16 ? ) ( AB15 ? ) - ( AA15 N-000124 ) + ( AA15 N-000147 ) ( AB14 ? ) ( AA14 ? ) ( AB13 ? ) @@ -740,7 +740,7 @@ ( AB21 ? ) ( AA21 /FPGA_Spartan6/PROG_CCLK ) ( AB11 ? ) - ( AA11 N-000124 ) + ( AA11 N-000147 ) ( AB20 /FPGA_Spartan6/PROG_MISO0 ) ( AA20 /FPGA_Spartan6/PROG_MISO1 ) ( AB10 ? ) @@ -749,11 +749,11 @@ ( Y19 ? ) ( V9 ? ) ( U9 ? ) - ( T9 N-000124 ) + ( T9 N-000147 ) ( R9 ? ) ( Y8 ? ) ( W8 ? ) - ( V8 N-000124 ) + ( V8 N-000147 ) ( U8 ? ) ( T8 ? ) ( R8 ? ) @@ -766,7 +766,7 @@ ( U6 ? ) ( T6 ? ) ( Y5 ? ) - ( W5 N-000124 ) + ( W5 N-000147 ) ( V5 ? ) ( T5 /FPGA_Spartan6/PROG_CSO ) ( Y4 ? ) @@ -782,18 +782,18 @@ ( U14 /FPGA_Spartan6/PROG_MISO2 ) ( T14 ? ) ( AB3 ? ) - ( AA3 N-000124 ) + ( AA3 N-000147 ) ( Y13 ? ) ( W13 ? ) ( V13 ? ) ( U13 /FPGA_Spartan6/PROG_MISO3 ) - ( T13 N-000124 ) + ( T13 N-000147 ) ( R13 ? ) ( AB2 ? ) ( AA2 ? ) ( Y12 ? ) ( W12 ? ) - ( V12 N-000124 ) + ( V12 N-000147 ) ( U12 ? ) ( T12 ? ) ( Y11 ? ) @@ -810,7 +810,7 @@ ) ( /4C4320F3/4C5D8114 $noname C9 C {Lib=C} ( 1 /Ethernet_Phy/ETH_PLL1.8V ) - ( 2 N-000331 ) + ( 2 N-000329 ) ) ( /4C4320F3/4C5D810A $noname L3 INDUCTOR {Lib=INDUCTOR} ( 1 /Ethernet_Phy/ETH_A1.8V ) @@ -818,15 +818,15 @@ ) ( /4C4320F3/4C5D8104 $noname C6 C {Lib=C} ( 1 /Ethernet_Phy/ETH_A1.8V ) - ( 2 N-000331 ) + ( 2 N-000329 ) ) ( /4C4320F3/4C5D80F3 $noname L1 INDUCTOR {Lib=INDUCTOR} - ( 1 N-000323 ) + ( 1 N-000321 ) ( 2 /Ethernet_Phy/ETH_A1.8V ) ) ( /4C4320F3/4C5D80F0 $noname C4 C {Lib=C} - ( 1 N-000323 ) - ( 2 N-000331 ) + ( 1 N-000321 ) + ( 2 N-000329 ) ) ( /4C4320F3/4C5D80ED $noname C2 C {Lib=C} ( 1 /Ethernet_Phy/ETH_1.8V ) @@ -861,7 +861,7 @@ ( 2 3.3V ) ) ( /4C4320F3/4C5D7ECF $noname R2 6.65K {Lib=R} - ( 1 N-000328 ) + ( 1 N-000326 ) ( 2 GND ) ) ( /4C4320F3/4C5D7E43 $noname C11 100nF {Lib=C} @@ -873,35 +873,35 @@ ( 2 GND ) ) ( /4C4320F3/4C5D7DCB $noname C12 47nF {Lib=C} - ( 1 N-000316 ) + ( 1 N-000314 ) ( 2 GND ) ) ( /4C4320F3/4C5D7DC4 $noname R9 1M {Lib=R} - ( 1 N-000316 ) + ( 1 N-000314 ) ( 2 GND ) ) ( /4C4320F3/4C432132 $noname U4 K8001 {Lib=K8001} ( 1 /Ethernet_Phy/ETH_MDIO ) ( 2 /FPGA_Spartan6/ETH_MDC ) - ( 3 /Ethernet_Phy/ETH_RXD3 ) + ( 3 /FPGA_Spartan6/ETH_RXD3 ) ( 4 /FPGA_Spartan6/ETH_RXD2 ) ( 5 /Ethernet_Phy/ETH_RXD1 ) - ( 6 /Ethernet_Phy/ETH_RXD0 ) + ( 6 /FPGA_Spartan6/ETH_RXD0 ) ( 7 3.3V ) ( 8 GND ) - ( 9 /FPGA_Spartan6/ETH_RXDV ) - ( 10 /FPGA_Spartan6/ETH_RXC ) - ( 11 /FPGA_Spartan6/ETH_RXER ) + ( 9 /Ethernet_Phy/ETH_RXDV ) + ( 10 /Ethernet_Phy/ETH_RXC ) + ( 11 /Ethernet_Phy/ETH_RXER ) ( 12 GND ) ( 13 /Ethernet_Phy/ETH_1.8V ) - ( 14 /FPGA_Spartan6/ETH_TXER ) - ( 15 /FPGA_Spartan6/ETH_TXC ) + ( 14 /Ethernet_Phy/ETH_TXER ) + ( 15 /Ethernet_Phy/ETH_TXC ) ( 16 /FPGA_Spartan6/ETH_TXEN ) ( 17 /Ethernet_Phy/ETH_TXD0 ) - ( 18 /Ethernet_Phy/ETH_TXD1 ) - ( 19 /Ethernet_Phy/ETH_TXD2 ) - ( 20 /FPGA_Spartan6/ETH_TXD3 ) - ( 21 /FPGA_Spartan6/ETH_COL ) + ( 18 /FPGA_Spartan6/ETH_TXD1 ) + ( 19 /FPGA_Spartan6/ETH_TXD2 ) + ( 20 /Ethernet_Phy/ETH_TXD3 ) + ( 21 /Ethernet_Phy/ETH_COL ) ( 22 /FPGA_Spartan6/ETH_CRS ) ( 23 GND ) ( 24 3.3V ) @@ -912,63 +912,63 @@ ( 29 ? ) ( 30 ? ) ( 31 /Ethernet_Phy/ETH_A1.8V ) - ( 32 N-000329 ) - ( 33 N-000320 ) + ( 32 N-000327 ) + ( 33 N-000318 ) ( 34 ? ) ( 35 GND ) ( 36 GND ) - ( 37 N-000328 ) + ( 37 N-000326 ) ( 38 /Ethernet_Phy/ETH_A3.3V ) ( 39 GND ) - ( 40 N-000330 ) - ( 41 N-000319 ) + ( 40 N-000328 ) + ( 41 N-000317 ) ( 42 ? ) ( 43 ? ) ( 44 GND ) ( 45 ? ) - ( 46 /FPGA_Spartan6/ETH_CLK ) + ( 46 /Ethernet_Phy/ETH_CLK ) ( 47 /Ethernet_Phy/ETH_PLL1.8V ) ( 48 /FPGA_Spartan6/ETH_RESET_N ) ) ( /4C4320F3/4C5D7AFE $noname R3 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000319 ) + ( 2 N-000317 ) ) ( /4C4320F3/4C5D7AFC $noname R4 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000330 ) + ( 2 N-000328 ) ) ( /4C4320F3/4C5D7AF9 $noname R6 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000329 ) + ( 2 N-000327 ) ) ( /4C4320F3/4C5D7AF7 $noname R5 49.9 {Lib=R} ( 1 3.3V ) - ( 2 N-000320 ) + ( 2 N-000318 ) ) ( /4C4320F3/4C5D71DB $noname R8 220 {Lib=R} - ( 1 N-000333 ) + ( 1 N-000331 ) ( 2 /Ethernet_Phy/ETH_LED1 ) ) ( /4C4320F3/4C5D719D $noname R7 220 {Lib=R} - ( 1 N-000317 ) + ( 1 N-000315 ) ( 2 /Ethernet_Phy/ETH_LED0 ) ) ( /4C4320F3/4C5D6F5A $noname J4 RJ45-48025 {Lib=RJ45-48025} - ( 1 N-000319 ) - ( 2 N-000330 ) + ( 1 N-000317 ) + ( 2 N-000328 ) ( 3 3.3V ) ( 4 GND ) ( 5 GND ) ( 6 3.3V ) - ( 7 N-000320 ) - ( 8 N-000329 ) + ( 7 N-000318 ) + ( 8 N-000327 ) ( 9 3.3V ) - ( 10 N-000317 ) + ( 10 N-000315 ) ( 11 3.3V ) - ( 12 N-000333 ) - ( 13 N-000316 ) - ( 14 N-000316 ) + ( 12 N-000331 ) + ( 13 N-000314 ) + ( 14 N-000314 ) ) ( /4C421DD3/4C65D2A9 0402 C70 10nF {Lib=CAP} ( 1 +2.5V ) @@ -1070,39 +1070,39 @@ ( 1 +2.5V ) ( 2 /FPGA_Spartan6/M1_DQ0 ) ( 3 +2.5V ) - ( 4 /DDR_Banks/M1_DQ1 ) + ( 4 /FPGA_Spartan6/M1_DQ1 ) ( 5 /FPGA_Spartan6/M1_DQ2 ) ( 6 GND ) ( 7 /DDR_Banks/M1_DQ3 ) - ( 8 /FPGA_Spartan6/M1_DQ4 ) + ( 8 /DDR_Banks/M1_DQ4 ) ( 9 +2.5V ) ( 10 /FPGA_Spartan6/M1_DQ5 ) - ( 11 /DDR_Banks/M1_DQ6 ) + ( 11 /FPGA_Spartan6/M1_DQ6 ) ( 12 GND ) - ( 13 /DDR_Banks/M1_DQ7 ) + ( 13 /FPGA_Spartan6/M1_DQ7 ) ( 14 ? ) ( 15 +2.5V ) - ( 16 /DDR_Banks/M1_LDQS ) + ( 16 /FPGA_Spartan6/M1_LDQS ) ( 17 ? ) ( 18 +2.5V ) ( 19 ? ) - ( 20 /FPGA_Spartan6/M1_LDM ) - ( 21 /DDR_Banks/M1_WE# ) + ( 20 /DDR_Banks/M1_LDM ) + ( 21 /FPGA_Spartan6/M1_WE# ) ( 22 /FPGA_Spartan6/M1_CAS# ) - ( 23 /FPGA_Spartan6/M1_RAS# ) + ( 23 /DDR_Banks/M1_RAS# ) ( 24 GND ) ( 25 ? ) - ( 26 /FPGA_Spartan6/M1_BA0 ) + ( 26 /DDR_Banks/M1_BA0 ) ( 27 /DDR_Banks/M1_BA1 ) - ( 28 /DDR_Banks/M1_A10 ) + ( 28 /FPGA_Spartan6/M1_A10 ) ( 29 /DDR_Banks/M1_A0 ) - ( 30 /DDR_Banks/M1_A1 ) + ( 30 /FPGA_Spartan6/M1_A1 ) ( 31 /FPGA_Spartan6/M1_A2 ) ( 32 /FPGA_Spartan6/M1_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M1_A4 ) - ( 36 /DDR_Banks/M1_A5 ) + ( 36 /FPGA_Spartan6/M1_A5 ) ( 37 /FPGA_Spartan6/M1_A6 ) ( 38 /FPGA_Spartan6/M1_A7 ) ( 39 /FPGA_Spartan6/M1_A8 ) @@ -1110,7 +1110,7 @@ ( 41 /FPGA_Spartan6/M1_A11 ) ( 42 /DDR_Banks/M1_A12 ) ( 43 ? ) - ( 44 /DDR_Banks/M1_CLK# ) + ( 44 /FPGA_Spartan6/M1_CLK# ) ( 45 /FPGA_Spartan6/M1_CKE ) ( 46 /FPGA_Spartan6/M1_CLK ) ( 47 /FPGA_Spartan6/M1_UDM ) @@ -1122,30 +1122,30 @@ ( 53 ? ) ( 54 /FPGA_Spartan6/M1_DQ8 ) ( 55 +2.5V ) - ( 56 /DDR_Banks/M1_DQ9 ) - ( 57 /FPGA_Spartan6/M1_DQ10 ) + ( 56 /FPGA_Spartan6/M1_DQ9 ) + ( 57 /DDR_Banks/M1_DQ10 ) ( 58 GND ) - ( 59 /FPGA_Spartan6/M1_DQ11 ) - ( 60 /DDR_Banks/M1_DQ12 ) + ( 59 /DDR_Banks/M1_DQ11 ) + ( 60 /FPGA_Spartan6/M1_DQ12 ) ( 61 +2.5V ) ( 62 /FPGA_Spartan6/M1_DQ13 ) ( 63 /FPGA_Spartan6/M1_DQ14 ) ( 64 GND ) - ( 65 /DDR_Banks/M1_DQ15 ) + ( 65 /FPGA_Spartan6/M1_DQ15 ) ( 66 GND ) ) ( /4C421DD3/4C609B99 $noname U2 MT46V32M16TG {Lib=MT46V32M16TG} ( 1 +2.5V ) - ( 2 /FPGA_Spartan6/M0_DQ0 ) + ( 2 /DDR_Banks/M0_DQ0 ) ( 3 +2.5V ) ( 4 /FPGA_Spartan6/M0_DQ1 ) - ( 5 /FPGA_Spartan6/M0_DQ2 ) + ( 5 /DDR_Banks/M0_DQ2 ) ( 6 GND ) ( 7 /FPGA_Spartan6/M0_DQ3 ) - ( 8 /FPGA_Spartan6/M0_DQ4 ) + ( 8 /DDR_Banks/M0_DQ4 ) ( 9 +2.5V ) - ( 10 /FPGA_Spartan6/M0_DQ5 ) - ( 11 /FPGA_Spartan6/M0_DQ6 ) + ( 10 /DDR_Banks/M0_DQ5 ) + ( 11 /DDR_Banks/M0_DQ6 ) ( 12 GND ) ( 13 /FPGA_Spartan6/M0_DQ7 ) ( 14 ? ) @@ -1155,27 +1155,27 @@ ( 18 +2.5V ) ( 19 ? ) ( 20 /DDR_Banks/M0_LDM ) - ( 21 /FPGA_Spartan6/M0_WE# ) + ( 21 /DDR_Banks/M0_WE# ) ( 22 /FPGA_Spartan6/M0_CAS# ) ( 23 /FPGA_Spartan6/M0_RAS# ) ( 24 GND ) ( 25 ? ) ( 26 /FPGA_Spartan6/M0_BA0 ) ( 27 /DDR_Banks/M0_BA1 ) - ( 28 /FPGA_Spartan6/M0_A10 ) - ( 29 /FPGA_Spartan6/M0_A0 ) + ( 28 /DDR_Banks/M0_A10 ) + ( 29 /DDR_Banks/M0_A0 ) ( 30 /FPGA_Spartan6/M0_A1 ) ( 31 /FPGA_Spartan6/M0_A2 ) ( 32 /DDR_Banks/M0_A3 ) ( 33 +2.5V ) ( 34 GND ) ( 35 /FPGA_Spartan6/M0_A4 ) - ( 36 /DDR_Banks/M0_A5 ) + ( 36 /FPGA_Spartan6/M0_A5 ) ( 37 /FPGA_Spartan6/M0_A6 ) ( 38 /FPGA_Spartan6/M0_A7 ) - ( 39 /FPGA_Spartan6/M0_A8 ) + ( 39 /DDR_Banks/M0_A8 ) ( 40 /FPGA_Spartan6/M0_A9 ) - ( 41 /FPGA_Spartan6/M0_A11 ) + ( 41 /DDR_Banks/M0_A11 ) ( 42 /FPGA_Spartan6/M0_A12 ) ( 43 ? ) ( 44 /FPGA_Spartan6/M0_CLK# ) @@ -1188,9 +1188,9 @@ ( 51 /DDR_Banks/M0_UDQS ) ( 52 GND ) ( 53 ? ) - ( 54 /FPGA_Spartan6/M0_DQ8 ) + ( 54 /DDR_Banks/M0_DQ8 ) ( 55 +2.5V ) - ( 56 /FPGA_Spartan6/M0_DQ9 ) + ( 56 /DDR_Banks/M0_DQ9 ) ( 57 /FPGA_Spartan6/M0_DQ10 ) ( 58 GND ) ( 59 /FPGA_Spartan6/M0_DQ11 ) @@ -1671,40 +1671,40 @@ $endfootprintlist Net 1 "/FPGA Spartan6/PROG_CSO" "PROG_CSO" U8 1 U1 T5 -Net 2 "/Non volatile memories/NF_RE_N" "NF_RE_N" - U5 8 +Net 2 "/FPGA Spartan6/NF_RE_N" "NF_RE_N" U1 B16 + U5 8 Net 3 "/Non volatile memories/NF_CS1_N" "NF_CS1_N" U5 9 U1 C16 -Net 4 "/Non volatile memories/NF_ALE" "NF_ALE" +Net 4 "/FPGA Spartan6/NF_ALE" "NF_ALE" U1 A15 U5 17 -Net 5 "/FPGA Spartan6/ETH_TXC" "ETH_TXC" - U4 15 +Net 5 "/Ethernet Phy/ETH_TXC" "ETH_TXC" U1 D8 -Net 6 "/FPGA Spartan6/ETH_RXC" "ETH_RXC" + U4 15 +Net 6 "/Ethernet Phy/ETH_RXC" "ETH_RXC" U1 D10 U4 10 -Net 7 "/FPGA Spartan6/ETH_CLK" "ETH_CLK" - U4 46 +Net 7 "/Ethernet Phy/ETH_CLK" "ETH_CLK" U1 C10 + U4 46 Net 8 "/USB/USBA_SPD" "USBA_SPD" U1 R19 U6 2 -Net 9 "/USB/USBA_OE_N" "USBA_OE_N" +Net 9 "/FPGA Spartan6/USBA_OE_N" "USBA_OE_N" U6 9 U1 P18 Net 10 "/FPGA Spartan6/USBA_RCV" "USBA_RCV" - U1 N16 U6 3 -Net 11 "/FPGA Spartan6/USBA_VP" "USBA_VP" - U6 4 + U1 N16 +Net 11 "/USB/USBA_VP" "USBA_VP" U1 P17 + U6 4 Net 12 "/USB/USBA_VM" "USBA_VM" U1 M18 U6 5 -Net 13 "/FPGA Spartan6/ETH_COL" "ETH_COL" +Net 13 "/Ethernet Phy/ETH_COL" "ETH_COL" U4 21 U1 A10 Net 14 "/FPGA Spartan6/ETH_CRS" "ETH_CRS" @@ -1714,42 +1714,42 @@ Net 15 "/FPGA Spartan6/SD_CLK" "SD_CLK" J1 5 U1 E16 Net 16 "/Ethernet Phy/ETH_INT" "ETH_INT" - U1 A4 U4 25 + U1 A4 Net 17 "/FPGA Spartan6/ETH_MDC" "ETH_MDC" U1 C5 U4 2 Net 18 "/Ethernet Phy/ETH_MDIO" "ETH_MDIO" - R1 1 - U4 1 U1 A5 + U4 1 + R1 1 Net 19 "/FPGA Spartan6/ETH_RESET_N" "ETH_RESET_N" U4 48 U1 D6 -Net 20 "/FPGA Spartan6/ETH_RXDV" "ETH_RXDV" +Net 20 "/Ethernet Phy/ETH_RXDV" "ETH_RXDV" U1 A7 U4 9 -Net 21 "/FPGA Spartan6/ETH_RXER" "ETH_RXER" +Net 21 "/Ethernet Phy/ETH_RXER" "ETH_RXER" U1 B8 U4 11 -Net 22 "/FPGA Spartan6/ETH_TXER" "ETH_TXER" - U4 14 +Net 22 "/Ethernet Phy/ETH_TXER" "ETH_TXER" U1 A8 + U4 14 Net 23 "/FPGA Spartan6/ETH_TXEN" "ETH_TXEN" U1 D9 U4 16 Net 24 "/FPGA Spartan6/M1_UDM" "M1_UDM" U3 47 U1 M20 -Net 25 "/DDR Banks/M1_LDQS" "M1_LDQS" +Net 25 "/FPGA Spartan6/M1_LDQS" "M1_LDQS" U1 L20 U3 16 -Net 26 "/FPGA Spartan6/M1_LDM" "M1_LDM" +Net 26 "/DDR Banks/M1_LDM" "M1_LDM" U1 L19 U3 20 Net 27 "/FPGA Spartan6/M1_UDQS" "M1_UDQS" - U3 51 U1 T21 + U3 51 Net 28 "/DDR Banks/M0_UDQS" "M0_UDQS" U2 51 U1 T2 @@ -1763,49 +1763,37 @@ Net 31 "/FPGA Spartan6/M1_CKE" "M1_CKE" U3 45 U1 D21 Net 32 "/FPGA Spartan6/M1_CLK" "M1_CLK" - U3 46 U1 H20 -Net 33 "/DDR Banks/M1_CLK#" "M1_CLK#" + U3 46 +Net 33 "/FPGA Spartan6/M1_CLK#" "M1_CLK#" U1 J19 U3 44 Net 34 "GND" "GND" - U1 R5 - U2 52 - U1 E7 - U2 12 - U1 J13 - C67 2 - C69 2 - U2 66 - C54 2 - C57 2 - C60 2 - U2 6 - C63 2 - C66 2 - U3 58 - U3 48 - U1 L5 - J1 COM - J1 CASE - J1 CASE - J1 CASE - U1 N13 - U1 AA5 - U1 L13 - J1 6 - U3 52 - U1 V4 - U1 B5 + U2 34 + U2 24 + U3 64 + U2 64 + U1 A22 + U1 P12 + C47 2 + C44 2 + C41 2 + U3 6 + C53 2 + C51 2 + C49 2 + C46 2 + C2 2 C55 2 - U1 G5 - U1 D4 + U3 52 C58 2 - U3 12 - U1 U2 C61 2 - U3 66 + U3 12 + C64 2 C40 2 + U3 66 + C43 2 + C52 2 C50 2 C56 2 C59 2 @@ -1814,60 +1802,47 @@ Net 34 "GND" "GND" U3 34 U3 24 C68 2 - C41 2 - C44 2 - C47 2 - U1 A22 - U2 64 - U2 34 - U2 24 - U1 B13 - U2 58 - U2 48 - C64 2 - C43 2 - U1 N2 - U1 J2 - C52 2 - U1 P12 - U3 64 - U1 E2 - C46 2 - C49 2 - C51 2 - U1 A1 - C53 2 - U3 6 - U1 W7 - U8 4 - U1 J11 - U1 L11 - U1 H7 - U1 U7 - U1 J9 - U1 L9 - U1 N9 - U1 J15 - U1 B9 + U1 AA17 + U1 K14 + U1 M14 + U1 P14 + U1 V14 + U1 E15 C72 2 C73 2 C74 2 - U1 K10 - U1 E21 - U5 13 - U1 J21 - U1 N21 - U1 U21 - U1 AB1 - U1 M10 - U1 M12 - U5 36 - U1 N11 + U8 4 + U2 12 + J1 6 + U1 J13 + J1 COM + J1 CASE + J1 CASE + J1 CASE + U1 L13 + U1 N13 C39 2 C42 2 C45 2 - C48 2 - U1 V10 + U2 58 + U2 48 + C67 2 + C69 2 + C54 2 + C57 2 + U1 B13 + U2 66 + C60 2 + C63 2 + U2 6 + C66 2 + U3 58 + U3 48 + U2 52 + U1 AB1 + U5 36 + U1 K12 + U1 M12 U1 W16 U1 B17 U1 N17 @@ -1879,26 +1854,14 @@ Net 34 "GND" "GND" U1 AA9 U1 AB22 U1 AA13 - U1 AA17 - U1 K14 - U1 M14 - U1 P10 - U1 P14 - U1 V14 - U1 E15 - V2 2 - C16 2 - R10 2 - U6 8 - U6 7 - C13 2 - C14 2 - C15 2 - V1 2 - V3 2 - C38 2 - R15 2 - V4 2 + C48 2 + U1 N11 + U5 13 + U1 E21 + U1 J21 + U1 N21 + U1 U21 + C27 2 C32 2 C30 2 C31 2 @@ -1907,41 +1870,80 @@ Net 34 "GND" "GND" C22 2 C23 2 C25 2 - U4 44 + C24 2 + C26 2 + C21 2 + U1 K10 + U1 M10 + U4 35 + U4 36 U4 8 U4 12 U4 23 - U4 36 - U4 35 - C27 2 - J4 4 - J4 5 - U4 39 - C33 2 + U1 W7 C34 2 C71 2 C70 2 - C1 2 - C24 2 - C3 2 - C26 2 - C5 2 - C21 2 - C7 2 - C8 2 - R9 2 + U1 B9 + U1 P10 + U1 V10 + U1 E11 + U1 J11 + U1 L11 + U1 E7 + U1 H7 + U1 U7 + C33 2 + V3 2 + V4 2 + U1 N2 + C15 2 + C14 2 + C13 2 + U1 U2 + U6 7 + U6 8 + L7 2 + U1 A1 + U1 E2 + U1 J2 + R15 2 + C38 2 C12 2 - C10 2 - C11 2 + R9 2 + C8 2 + C7 2 + C5 2 + C3 2 + C1 2 + U4 44 + U1 D4 + U1 V4 + U1 B5 + U1 G5 + U1 L5 + U1 R5 + R10 2 + C16 2 + V2 2 + V1 2 + U4 39 + J4 5 + J4 4 R2 2 + C11 2 + C10 2 + U1 AA5 + U1 J15 + U7 7 + U7 8 C35 2 C36 2 C37 2 L5 2 - U7 7 - U7 8 - C2 2 - L7 2 + U1 N9 + U1 J9 + U1 L9 Net 35 "/FPGA Spartan6/M0_CLK#" "M0_CLK#" U1 H3 U2 44 @@ -1954,146 +1956,146 @@ Net 37 "/FPGA Spartan6/M0_CKE" "M0_CKE" Net 38 "/FPGA Spartan6/M0_CAS#" "M0_CAS#" U1 K4 U2 22 -Net 39 "/DDR Banks/M1_WE#" "M1_WE#" - U1 H19 +Net 39 "/FPGA Spartan6/M1_WE#" "M1_WE#" U3 21 -Net 40 "/FPGA Spartan6/M1_RAS#" "M1_RAS#" - U1 H21 + U1 H19 +Net 40 "/DDR Banks/M1_RAS#" "M1_RAS#" U3 23 + U1 H21 Net 41 "/FPGA Spartan6/M0_RAS#" "M0_RAS#" U2 23 U1 K5 -Net 42 "/FPGA Spartan6/M0_WE#" "M0_WE#" - U2 21 +Net 42 "/DDR Banks/M0_WE#" "M0_WE#" U1 F2 + U2 21 Net 43 "/DDR Banks/M0_LDQS" "M0_LDQS" - U1 L3 U2 16 + U1 L3 Net 44 "/DDR Banks/M0_UDM" "M0_UDM" - U2 47 U1 M3 + U2 47 Net 45 "/FPGA Spartan6/PROG_CCLK" "PROG_CCLK" - U8 6 U1 AA21 + U8 6 Net 46 "/FPGA Spartan6/NF_RNB" "NF_RNB" - U1 A16 - U5 7 U5 6 -Net 47 "/FPGA Spartan6/NF_WE_N" "NF_WE_N" - U1 C15 + U5 7 + U1 A16 +Net 47 "/Non volatile memories/NF_WE_N" "NF_WE_N" U5 18 -Net 48 "/FPGA Spartan6/NF_CLE" "NF_CLE" + U1 C15 +Net 48 "/Non volatile memories/NF_CLE" "NF_CLE" U1 D15 U5 16 Net 49 "/FPGA Spartan6/SD_CMD" "SD_CMD" - J1 3 U1 D17 + J1 3 Net 50 "" "" R14 2 C20 2 Net 51 "" "" R14 1 - R13 2 - C20 1 C19 2 + C20 1 U3 49 + R13 2 Net 52 "" "" + U2 49 C17 2 C18 1 - R11 2 R12 1 - U2 49 + R11 2 Net 53 "+2.5V" "+2.5V" - U2 33 - U1 R12 - C49 1 - C51 1 - U3 9 - C53 1 - U3 3 - U2 55 - U2 15 - C63 1 - U2 1 + U1 J5 + U1 U18 + U1 D16 + U1 M15 + U1 K15 + U1 H15 U1 C2 - U2 18 - U1 G2 - U1 L2 - U1 R2 - C54 1 - U2 9 + U1 H9 U1 W2 - C57 1 - C60 1 - U2 3 - C59 1 + U1 R2 + U1 L2 + U1 G2 U1 R6 U1 V6 - C62 1 - C65 1 - U7 1 + U1 N18 + U1 J18 U1 E19 U1 W21 U1 R21 - U1 M15 - U1 J18 - U1 D16 - C56 1 - U3 1 - C17 1 - C19 1 - R11 1 - U1 L8 - U1 N8 - U1 H9 - C52 1 - C46 1 U1 L21 U1 G21 - U3 33 - C68 1 - U3 61 U1 C21 U1 L16 - U3 18 - C40 1 - C43 1 U1 R10 - U3 55 - U3 15 U1 F11 - U1 K15 - C22 1 - U1 U18 - R13 1 - U1 F4 - C21 1 - C26 1 - C24 1 - U1 F6 - U1 U5 - U1 N5 - C25 1 - C23 1 - U1 J5 - C31 1 - C30 1 - C32 1 - C27 1 - U1 N18 - U1 H15 - C28 1 - C29 1 - U6 1 - C66 1 - U2 61 - U1 L7 - U1 G12 - U1 U11 + U1 L8 + U1 N8 C70 1 C71 1 C34 1 C33 1 + U6 1 + U7 1 + C21 1 + C26 1 + C24 1 + C25 1 + C23 1 + C22 1 + R13 1 + C28 1 + C29 1 + C31 1 + C30 1 + C32 1 + C27 1 + U1 U5 + U1 F6 + U1 F4 + U1 L7 + U1 G12 + U1 U11 + U2 61 + C66 1 + U2 1 + U2 3 + C63 1 + U2 9 + C60 1 + C57 1 + C54 1 + U2 18 + U2 33 + U1 R12 + U1 N5 + U3 18 + U3 61 + C68 1 + U3 33 + C65 1 + C62 1 + C59 1 + C56 1 + U2 15 + U2 55 + U3 3 + C53 1 + U3 9 + C51 1 + C49 1 + C46 1 + R11 1 + C19 1 + C17 1 + U3 1 + U3 15 + C52 1 + U3 55 + C43 1 + C40 1 Net 54 "" "" R12 2 C18 2 @@ -2122,436 +2124,436 @@ Net 99 "3.3V" "3.3V" U5 12 U5 19 Net 100 "VCCO2" "VCCO2" - C55 1 - C58 1 - C61 1 U8 8 - C64 1 - C67 1 C69 1 + C67 1 + C64 1 + C61 1 + C58 1 + C55 1 Net 101 "+3.3V" "+3.3V" - U5 37 - U1 E13 + C72 1 + C73 1 U1 B4 C74 1 - C73 1 - C72 1 + U1 G10 + U1 E9 + C50 1 + U1 B7 + U1 B15 + U1 G14 + C41 1 + C44 1 + C47 1 + U1 E13 U1 B11 U1 B19 U1 E17 - C50 1 - U1 G10 - U1 E9 - C44 1 - C41 1 - U1 G14 - U1 B15 - C47 1 - U1 B7 -Net 124 "" "" - U1 V12 - U1 W5 - U1 V16 - U1 V8 - U1 AA11 - U1 AA3 + U5 37 +Net 147 "" "" U1 T13 - U1 AA15 - U1 AA7 + U1 AA3 U1 T9 + U1 AA11 U1 AA19 -Net 236 "+1.2V" "+1.2V" + U1 AA15 + U1 V8 + U1 V16 + U1 W5 + U1 V12 + U1 AA7 +Net 234 "+1.2V" "+1.2V" + U1 P9 C48 1 + U1 J10 C45 1 - C42 1 U1 M11 U1 P11 - U1 J12 - U1 L12 U1 J14 U1 L14 U1 N14 U1 R14 - U1 M9 - U1 K9 - U1 J8 - U1 K11 - U1 N10 - U1 L10 - U1 J10 - U1 P9 - C39 1 + C42 1 U1 N12 + U1 L12 + C39 1 U1 P13 + U1 J12 U1 M13 U1 K13 -Net 316 "" "" - J4 13 + U1 L10 + U1 N10 + U1 K11 + U1 J8 + U1 K9 + U1 M9 +Net 314 "" "" J4 14 - C12 1 + J4 13 R9 1 -Net 317 "" "" + C12 1 +Net 315 "" "" J4 10 R7 1 -Net 318 "/Ethernet Phy/ETH_LED0" "ETH_LED0" - U4 26 +Net 316 "/Ethernet Phy/ETH_LED0" "ETH_LED0" R7 2 -Net 319 "" "" + U4 26 +Net 317 "" "" R3 2 J4 1 U4 41 -Net 320 "" "" - R5 2 - J4 7 +Net 318 "" "" U4 33 -Net 321 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" - U4 13 + J4 7 + R5 2 +Net 319 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V" C2 1 -Net 322 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" + U4 13 +Net 320 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V" C6 1 - L1 2 L3 1 U4 31 -Net 323 "" "" + L1 2 +Net 321 "" "" C4 1 L1 1 -Net 324 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" - L2 2 +Net 322 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V" C8 1 - C7 1 U4 38 -Net 325 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" + L2 2 + C7 1 +Net 323 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V" L3 2 C9 1 U4 47 -Net 328 "" "" - R2 1 +Net 326 "" "" U4 37 -Net 329 "" "" - R6 2 + R2 1 +Net 327 "" "" U4 32 + R6 2 J4 8 -Net 330 "" "" +Net 328 "" "" + J4 2 R4 2 U4 40 - J4 2 -Net 331 "" "" +Net 329 "" "" + C4 2 C6 2 C9 2 - C4 2 -Net 332 "/Ethernet Phy/ETH_LED1" "ETH_LED1" - R8 2 +Net 330 "/Ethernet Phy/ETH_LED1" "ETH_LED1" U4 27 -Net 333 "" "" - R8 1 + R8 2 +Net 331 "" "" J4 12 -Net 339 "" "" - U6 10 + R8 1 +Net 337 "" "" J5 2 V2 1 V2 1 -Net 340 "" "" + U6 10 +Net 338 "" "" J5 S1 J5 S2 J5 S3 J5 S4 R10 1 C16 1 -Net 341 "" "" +Net 339 "" "" L6 1 F2 1 -Net 343 "+5V" "+5V" - F2 2 +Net 341 "+5V" "+5V" F1 2 -Net 347 "" "" + F2 2 +Net 345 "" "" V3 1 V3 1 U7 11 -Net 351 "" "" +Net 349 "" "" L5 1 J5 4 -Net 352 "" "" - V4 1 - V4 1 +Net 350 "" "" U7 10 -Net 353 "" "" + V4 1 + V4 1 +Net 351 "" "" C35 1 C36 1 C37 1 -Net 354 "" "" +Net 352 "" "" C38 1 R15 1 -Net 355 "" "" +Net 353 "" "" L4 2 J5 1 -Net 356 "" "" +Net 354 "" "" F1 1 L4 1 -Net 357 "" "" +Net 355 "" "" C13 1 C14 1 C15 1 -Net 358 "" "" +Net 356 "" "" + U6 11 V1 1 J5 3 V1 1 - U6 11 -Net 359 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" - U1 U13 +Net 357 "/FPGA Spartan6/PROG_MISO3" "PROG_MISO3" U8 7 -Net 360 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" - U1 U14 + U1 U13 +Net 358 "/FPGA Spartan6/PROG_MISO2" "PROG_MISO2" U8 3 -Net 361 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" - U8 2 + U1 U14 +Net 359 "/FPGA Spartan6/PROG_MISO1" "PROG_MISO1" U1 AA20 -Net 362 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" + U8 2 +Net 360 "/FPGA Spartan6/PROG_MISO0" "PROG_MISO0" U8 5 U1 AB20 -Net 363 "/Non volatile memories/NF_D7" "NF_D7" +Net 361 "/Non volatile memories/NF_D7" "NF_D7" U1 A11 U5 44 -Net 364 "/Non volatile memories/NF_D6" "NF_D6" +Net 362 "/Non volatile memories/NF_D6" "NF_D6" U5 43 U1 D11 -Net 365 "/Non volatile memories/NF_D5" "NF_D5" +Net 363 "/Non volatile memories/NF_D5" "NF_D5" U1 C12 U5 42 -Net 366 "/FPGA Spartan6/NF_D4" "NF_D4" +Net 364 "/Non volatile memories/NF_D4" "NF_D4" U1 B12 U5 41 -Net 367 "/Non volatile memories/NF_D3" "NF_D3" - U1 A12 +Net 365 "/Non volatile memories/NF_D3" "NF_D3" U5 32 -Net 368 "/Non volatile memories/NF_D2" "NF_D2" - U1 C13 + U1 A12 +Net 366 "/FPGA Spartan6/NF_D2" "NF_D2" U5 31 -Net 369 "/FPGA Spartan6/NF_D1" "NF_D1" + U1 C13 +Net 367 "/Non volatile memories/NF_D1" "NF_D1" U5 30 U1 A13 -Net 370 "/Non volatile memories/NF_D0" "NF_D0" - U1 D14 +Net 368 "/Non volatile memories/NF_D0" "NF_D0" U5 29 -Net 371 "/FPGA Spartan6/ETH_TXD3" "ETH_TXD3" - U1 D7 + U1 D14 +Net 369 "/Ethernet Phy/ETH_TXD3" "ETH_TXD3" U4 20 -Net 372 "/Ethernet Phy/ETH_TXD2" "ETH_TXD2" + U1 D7 +Net 370 "/FPGA Spartan6/ETH_TXD2" "ETH_TXD2" U4 19 U1 A9 -Net 373 "/Ethernet Phy/ETH_TXD1" "ETH_TXD1" - U4 18 +Net 371 "/FPGA Spartan6/ETH_TXD1" "ETH_TXD1" U1 C9 -Net 374 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" - U4 17 + U4 18 +Net 372 "/Ethernet Phy/ETH_TXD0" "ETH_TXD0" U1 C8 -Net 375 "/Ethernet Phy/ETH_RXD3" "ETH_RXD3" + U4 17 +Net 373 "/FPGA Spartan6/ETH_RXD3" "ETH_RXD3" U1 C6 U4 3 -Net 376 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" +Net 374 "/FPGA Spartan6/ETH_RXD2" "ETH_RXD2" U1 B6 U4 4 -Net 377 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" - U4 5 +Net 375 "/Ethernet Phy/ETH_RXD1" "ETH_RXD1" U1 A6 -Net 378 "/Ethernet Phy/ETH_RXD0" "ETH_RXD0" + U4 5 +Net 376 "/FPGA Spartan6/ETH_RXD0" "ETH_RXD0" U4 6 U1 C7 -Net 379 "/DDR Banks/M0_BA1" "M0_BA1" +Net 377 "/DDR Banks/M0_BA1" "M0_BA1" U1 G1 U2 27 -Net 380 "/FPGA Spartan6/M0_BA0" "M0_BA0" +Net 378 "/FPGA Spartan6/M0_BA0" "M0_BA0" U1 G3 U2 26 -Net 381 "/DDR Banks/M1_BA1" "M1_BA1" - U3 27 +Net 379 "/DDR Banks/M1_BA1" "M1_BA1" U1 K17 -Net 382 "/FPGA Spartan6/M1_BA0" "M1_BA0" + U3 27 +Net 380 "/DDR Banks/M1_BA0" "M1_BA0" U3 26 U1 J17 -Net 383 "/DDR Banks/M1_DQ15" "M1_DQ15" - U1 V22 +Net 381 "/FPGA Spartan6/M1_DQ15" "M1_DQ15" U3 65 -Net 384 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" + U1 V22 +Net 382 "/FPGA Spartan6/M1_DQ14" "M1_DQ14" U3 63 U1 V21 -Net 385 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" +Net 383 "/FPGA Spartan6/M1_DQ13" "M1_DQ13" U3 62 U1 U22 -Net 386 "/DDR Banks/M1_DQ12" "M1_DQ12" +Net 384 "/FPGA Spartan6/M1_DQ12" "M1_DQ12" U3 60 U1 U20 -Net 387 "/FPGA Spartan6/M1_DQ11" "M1_DQ11" +Net 385 "/DDR Banks/M1_DQ11" "M1_DQ11" U1 R22 U3 59 -Net 388 "/FPGA Spartan6/M1_DQ10" "M1_DQ10" - U3 57 +Net 386 "/DDR Banks/M1_DQ10" "M1_DQ10" U1 R20 -Net 389 "/FPGA Spartan6/SD_DAT3" "SD_DAT3" - J1 2 + U3 57 +Net 387 "/Non volatile memories/SD_DAT3" "SD_DAT3" U1 C17 -Net 390 "/Non volatile memories/SD_DAT2" "SD_DAT2" - U1 A17 + J1 2 +Net 388 "/Non volatile memories/SD_DAT2" "SD_DAT2" J1 1 -Net 391 "/Non volatile memories/SD_DAT1" "SD_DAT1" - J1 8 + U1 A17 +Net 389 "/FPGA Spartan6/SD_DAT1" "SD_DAT1" U1 B18 -Net 392 "/FPGA Spartan6/SD_DAT0" "SD_DAT0" - J1 7 + J1 8 +Net 390 "/Non volatile memories/SD_DAT0" "SD_DAT0" U1 A18 -Net 393 "/FPGA Spartan6/M1_A7" "M1_A7" + J1 7 +Net 391 "/FPGA Spartan6/M1_A7" "M1_A7" U1 E20 U3 38 -Net 394 "/FPGA Spartan6/M1_A6" "M1_A6" - U1 K19 +Net 392 "/FPGA Spartan6/M1_A6" "M1_A6" U3 37 -Net 395 "/DDR Banks/M1_A5" "M1_A5" + U1 K19 +Net 393 "/FPGA Spartan6/M1_A5" "M1_A5" U1 K20 U3 36 -Net 396 "/FPGA Spartan6/M1_A4" "M1_A4" +Net 394 "/FPGA Spartan6/M1_A4" "M1_A4" U3 35 U1 F20 -Net 397 "/FPGA Spartan6/M1_A3" "M1_A3" +Net 395 "/FPGA Spartan6/M1_A3" "M1_A3" U3 32 U1 G20 -Net 398 "/FPGA Spartan6/M1_A2" "M1_A2" +Net 396 "/FPGA Spartan6/M1_A2" "M1_A2" U1 E22 U3 31 -Net 399 "/DDR Banks/M1_A1" "M1_A1" - U1 F22 +Net 397 "/FPGA Spartan6/M1_A1" "M1_A1" U3 30 -Net 400 "/DDR Banks/M1_A0" "M1_A0" - U1 F21 + U1 F22 +Net 398 "/DDR Banks/M1_A0" "M1_A0" U3 29 -Net 401 "/FPGA Spartan6/M0_A12" "M0_A12" - U2 42 + U1 F21 +Net 399 "/FPGA Spartan6/M0_A12" "M0_A12" U1 D1 -Net 402 "/FPGA Spartan6/M0_A11" "M0_A11" - U1 C1 + U2 42 +Net 400 "/DDR Banks/M0_A11" "M0_A11" U2 41 -Net 403 "/FPGA Spartan6/M0_A10" "M0_A10" - U2 28 + U1 C1 +Net 401 "/DDR Banks/M0_A10" "M0_A10" U1 G4 -Net 404 "/FPGA Spartan6/M0_A9" "M0_A9" + U2 28 +Net 402 "/FPGA Spartan6/M0_A9" "M0_A9" U1 E1 U2 40 -Net 405 "/FPGA Spartan6/M0_A8" "M0_A8" - U2 39 +Net 403 "/DDR Banks/M0_A8" "M0_A8" U1 E3 -Net 406 "/FPGA Spartan6/M0_A7" "M0_A7" - U1 H6 + U2 39 +Net 404 "/FPGA Spartan6/M0_A7" "M0_A7" U2 38 -Net 407 "/DDR Banks/M1_DQ9" "M1_DQ9" - U3 56 + U1 H6 +Net 405 "/FPGA Spartan6/M1_DQ9" "M1_DQ9" U1 P22 -Net 408 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" - U3 54 + U3 56 +Net 406 "/FPGA Spartan6/M1_DQ8" "M1_DQ8" U1 P21 -Net 409 "/DDR Banks/M1_DQ7" "M1_DQ7" + U3 54 +Net 407 "/FPGA Spartan6/M1_DQ7" "M1_DQ7" U3 13 U1 K22 -Net 410 "/DDR Banks/M1_DQ6" "M1_DQ6" +Net 408 "/FPGA Spartan6/M1_DQ6" "M1_DQ6" U3 11 U1 K21 -Net 411 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" - U1 J22 +Net 409 "/FPGA Spartan6/M1_DQ5" "M1_DQ5" U3 10 -Net 412 "/FPGA Spartan6/M1_DQ4" "M1_DQ4" - U1 J20 + U1 J22 +Net 410 "/DDR Banks/M1_DQ4" "M1_DQ4" U3 8 -Net 413 "/DDR Banks/M1_DQ3" "M1_DQ3" - U1 M22 + U1 J20 +Net 411 "/DDR Banks/M1_DQ3" "M1_DQ3" U3 7 -Net 414 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" + U1 M22 +Net 412 "/FPGA Spartan6/M1_DQ2" "M1_DQ2" U1 M21 U3 5 -Net 415 "/DDR Banks/M1_DQ1" "M1_DQ1" - U1 N22 +Net 413 "/FPGA Spartan6/M1_DQ1" "M1_DQ1" U3 4 -Net 416 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" + U1 N22 +Net 414 "/FPGA Spartan6/M1_DQ0" "M1_DQ0" U1 N20 U3 2 -Net 417 "/DDR Banks/M1_A12" "M1_A12" +Net 415 "/DDR Banks/M1_A12" "M1_A12" U1 D22 U3 42 -Net 418 "/FPGA Spartan6/M1_A11" "M1_A11" - U1 F19 +Net 416 "/FPGA Spartan6/M1_A11" "M1_A11" U3 41 -Net 419 "/DDR Banks/M1_A10" "M1_A10" - U3 28 + U1 F19 +Net 417 "/FPGA Spartan6/M1_A10" "M1_A10" U1 G19 -Net 420 "/FPGA Spartan6/M1_A9" "M1_A9" - U1 C22 + U3 28 +Net 418 "/FPGA Spartan6/M1_A9" "M1_A9" U3 40 -Net 421 "/FPGA Spartan6/M1_A8" "M1_A8" + U1 C22 +Net 419 "/FPGA Spartan6/M1_A8" "M1_A8" U1 C20 U3 39 -Net 422 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" - U1 M1 +Net 420 "/FPGA Spartan6/M0_DQ3" "M0_DQ3" U2 7 -Net 423 "/FPGA Spartan6/M0_DQ2" "M0_DQ2" - U2 5 + U1 M1 +Net 421 "/DDR Banks/M0_DQ2" "M0_DQ2" U1 M2 -Net 424 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" - U1 N1 + U2 5 +Net 422 "/FPGA Spartan6/M0_DQ1" "M0_DQ1" U2 4 -Net 425 "/FPGA Spartan6/M0_DQ0" "M0_DQ0" + U1 N1 +Net 423 "/DDR Banks/M0_DQ0" "M0_DQ0" U2 2 U1 N3 -Net 426 "/FPGA Spartan6/M0_A6" "M0_A6" +Net 424 "/FPGA Spartan6/M0_A6" "M0_A6" U2 37 U1 J4 -Net 427 "/DDR Banks/M0_A5" "M0_A5" +Net 425 "/FPGA Spartan6/M0_A5" "M0_A5" U1 K3 U2 36 -Net 428 "/FPGA Spartan6/M0_A4" "M0_A4" - U2 35 +Net 426 "/FPGA Spartan6/M0_A4" "M0_A4" U1 F3 -Net 429 "/DDR Banks/M0_A3" "M0_A3" + U2 35 +Net 427 "/DDR Banks/M0_A3" "M0_A3" U1 K6 U2 32 -Net 430 "/FPGA Spartan6/M0_A2" "M0_A2" +Net 428 "/FPGA Spartan6/M0_A2" "M0_A2" U2 31 U1 H5 -Net 431 "/FPGA Spartan6/M0_A1" "M0_A1" - U1 H1 +Net 429 "/FPGA Spartan6/M0_A1" "M0_A1" U2 30 -Net 432 "/FPGA Spartan6/M0_A0" "M0_A0" + U1 H1 +Net 430 "/DDR Banks/M0_A0" "M0_A0" U1 H2 U2 29 -Net 433 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" +Net 431 "/FPGA Spartan6/M0_DQ15" "M0_DQ15" U1 V1 U2 65 -Net 434 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" - U2 63 +Net 432 "/FPGA Spartan6/M0_DQ14" "M0_DQ14" U1 V2 -Net 435 "/DDR Banks/M0_DQ13" "M0_DQ13" - U1 U1 + U2 63 +Net 433 "/DDR Banks/M0_DQ13" "M0_DQ13" U2 62 -Net 436 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" + U1 U1 +Net 434 "/FPGA Spartan6/M0_DQ12" "M0_DQ12" U1 U3 U2 60 -Net 437 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" - U1 R1 +Net 435 "/FPGA Spartan6/M0_DQ11" "M0_DQ11" U2 59 -Net 438 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" + U1 R1 +Net 436 "/FPGA Spartan6/M0_DQ10" "M0_DQ10" U1 R3 U2 57 -Net 439 "/FPGA Spartan6/M0_DQ9" "M0_DQ9" - U2 56 +Net 437 "/DDR Banks/M0_DQ9" "M0_DQ9" U1 P1 -Net 440 "/FPGA Spartan6/M0_DQ8" "M0_DQ8" - U1 P2 + U2 56 +Net 438 "/DDR Banks/M0_DQ8" "M0_DQ8" U2 54 -Net 441 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" + U1 P2 +Net 439 "/FPGA Spartan6/M0_DQ7" "M0_DQ7" U2 13 U1 K1 -Net 442 "/FPGA Spartan6/M0_DQ6" "M0_DQ6" - U1 K2 +Net 440 "/DDR Banks/M0_DQ6" "M0_DQ6" U2 11 -Net 443 "/FPGA Spartan6/M0_DQ5" "M0_DQ5" - U1 J1 + U1 K2 +Net 441 "/DDR Banks/M0_DQ5" "M0_DQ5" U2 10 -Net 444 "/FPGA Spartan6/M0_DQ4" "M0_DQ4" + U1 J1 +Net 442 "/DDR Banks/M0_DQ4" "M0_DQ4" U2 8 U1 J3 } diff --git a/kicad/xue-rnc/xue-rnc.pro b/kicad/xue-rnc/xue-rnc.pro index 54dbf63..f051cbe 100644 --- a/kicad/xue-rnc/xue-rnc.pro +++ b/kicad/xue-rnc/xue-rnc.pro @@ -1,4 +1,4 @@ -update=Fri 13 Aug 2010 06:39:58 PM COT +update=Fri 13 Aug 2010 07:16:08 PM COT version=1 last_client=pcbnew [common] @@ -91,9 +91,9 @@ LibName42=../library/pasives-connectors LibName43=/home/afc/devel/Qi/xue/kicad/library/x25x64mb [pcbnew] version=1 -PadDrlX=320 -PadDimH=600 -PadDimV=600 +PadDrlX=0 +PadDimH=157 +PadDimV=157 BoardThickness=630 SgPcb45=1 TxtPcbV=800 diff --git a/kicad/xue-rnc/xue-rnc.sch b/kicad/xue-rnc/xue-rnc.sch index b86849f..26ead1c 100644 --- a/kicad/xue-rnc/xue-rnc.sch +++ b/kicad/xue-rnc/xue-rnc.sch @@ -1,4 +1,4 @@ -EESchema Schematic File Version 2 date Fri 13 Aug 2010 06:37:07 PM COT +EESchema Schematic File Version 2 date Fri 13 Aug 2010 07:13:52 PM COT LIBS:power LIBS:v0402mhs03 LIBS:usb-48204-0001 @@ -48,7 +48,7 @@ EELAYER END $Descr A3 16535 11700 Sheet 1 6 Title "" -Date "13 aug 2010" +Date "14 aug 2010" Rev "" Comp "" Comment1 ""