EESchema Schematic File Version 2  date Sun 08 Aug 2010 05:25:00 PM COT
LIBS:power,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./xue-rnc.cache
EELAYER 24  0
EELAYER END
$Descr A3 16535 11700
Sheet 1 6
Title ""
Date "4 aug 2010"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 10650 4900 1150 1100
U 4C5F1EDC
F0 "USB" 60
F1 "USB.sch" 60
$EndSheet
Wire Bus Line
	4700 5150 5950 5150
Wire Wire Line
	4700 4000 5950 4000
Wire Wire Line
	4700 6050 5950 6050
Wire Bus Line
	4700 5050 5950 5050
Wire Bus Line
	5950 5050 5950 5100
Wire Wire Line
	9750 6350 9300 6350
Wire Wire Line
	4700 6150 5950 6150
Wire Wire Line
	5950 4100 4700 4100
Wire Bus Line
	4700 3050 5950 3050
$Sheet
S 9750 6250 1450 2200
U 4C4320F3
F0 "Ethernet Phy" 60
F1 "eth_phy.sch" 60
F2 "ETH_RXC" O L 9750 6500 60 
F3 "ETH_RST_N" I L 9750 6600 60 
F4 "ETH_CRS" O L 9750 6700 60 
F5 "ETH_COL" O L 9750 6800 60 
F6 "ETH_INT" O L 9750 6350 60 
F7 "ETH_MDIO" B L 9750 6900 60 
F8 "ETH_MDC" I L 9750 7000 60 
F9 "ETH_RXD[0..3]" O L 9750 7200 60 
F10 "ETH_RXDV" O L 9750 7300 60 
F11 "ETH_RXER" O L 9750 7400 60 
F12 "ETH_TXC" B L 9750 7500 60 
F13 "ETH_TXD[0..3]" I L 9750 7600 60 
F14 "ETH_TXEN" I L 9750 7700 60 
F15 "ETH_TXER" I L 9750 7800 60 
F16 "ETH_CLK" I L 9750 7900 60 
$EndSheet
$Sheet
S 5950 2700 3350 5800
U 4C431A63
F0 "FPGA Spartan6" 60
F1 "FPGA.sch" 60
F2 "M1_CLK" O L 5950 4000 60 
F3 "M1_CLK#" O L 5950 4100 60 
F4 "M0_CLK" O L 5950 6050 60 
F5 "M0_CLK#" O L 5950 6150 60 
F6 "ETH_INT" I R 9300 6350 60 
F7 "M0_A[0..12]" O L 5950 5150 60 
F8 "M1_A[0..12]" O L 5950 3050 60 
F9 "M0_DQ[0..15]" B L 5950 5050 60 
$EndSheet
$Sheet
S 10650 2700 1150 1850
U 4C4227FE
F0 "Non volatile memories" 60
F1 "NV_MEMORIES.sch" 60
$EndSheet
$Sheet
S 3600 2700 1100 4000
U 4C421DD3
F0 "DDR Banks" 60
F1 "DRAM.sch" 60
F2 "M0_BA[0..1]" I R 4700 5250 60 
F3 "M1_BA[0..1]" I R 4700 3150 60 
F4 "M0_WE#" I R 4700 6550 60 
F5 "M0_RAS#" I R 4700 6400 60 
F6 "M1_RAS#" I R 4700 4350 60 
F7 "M1_WE#" I R 4700 4500 60 
F8 "M0_CAS#" I R 4700 6300 60 
F9 "M0_CKE" I R 4700 5950 60 
F10 "M0_CLK" I R 4700 6050 60 
F11 "M0_CLK#" I R 4700 6150 60 
F12 "M0_CS#" I R 4700 4900 60 
F13 "M1_CLK#" I R 4700 4100 60 
F14 "M1_CLK" I R 4700 4000 60 
F15 "M1_CKE" I R 4700 3900 60 
F16 "M1_CAS#" I R 4700 4250 60 
F17 "M0_DQ[0..15]" B R 4700 5050 60 
F18 "M0_UDM" I R 4700 5700 60 
F19 "M0_LDQS" I R 4700 5500 60 
F20 "M0_A[0..12]" I R 4700 5150 60 
F21 "M0_LDM" I R 4700 5800 60 
F22 "M0_UDQS" I R 4700 5400 60 
F23 "M1_UDQS" I R 4700 3350 60 
F24 "M1_LDM" I R 4700 3750 60 
F25 "M1_LDQS" I R 4700 3450 60 
F26 "M1_UDM" I R 4700 3650 60 
F27 "M1_CS#" I R 4700 2800 60 
F28 "M1_A[0..12]" I R 4700 3050 60 
F29 "M1_DQ[0..15]" B R 4700 2950 60 
$EndSheet
$EndSCHEMATC