EESchema Schematic File Version 2  date Mon 06 Sep 2010 09:03:31 PM COT
LIBS:power
LIBS:r_pack2
LIBS:v0402mhs03
LIBS:usb-48204-0001
LIBS:microsmd075f
LIBS:mic2550
LIBS:rj45-48025
LIBS:xue-nv
LIBS:xc6slx75fgg484
LIBS:xc6slx45fgg484
LIBS:micron_mobile_ddr
LIBS:micron_ddr_512Mb
LIBS:k8001
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:pasives-connectors
LIBS:x25x64mb
LIBS:attiny
LIBS:PSU
LIBS:xue-rnc-cache
EELAYER 24  0
EELAYER END
$Descr A4 11700 8267
Sheet 4 9
Title ""
Date "7 sep 2010"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L CONN_8X2 J6
U 1 1 4C716CAB
P 2550 2350
F 0 "J6" H 2550 2800 60  0000 C CNN
F 1 "CONN_8X2" V 2550 2350 50  0000 C CNN
	1    2550 2350
	1    0    0    -1  
$EndComp
Wire Wire Line
	2150 2200 1900 2200
Text HLabel 1900 2200 0    60   BiDi ~ 0
FPGA_TDO
Text HLabel 1900 2300 0    60   BiDi ~ 0
FPGA_TDI
Wire Wire Line
	2150 2300 1900 2300
Wire Wire Line
	2150 2100 1900 2100
Text HLabel 1900 2100 0    60   BiDi ~ 0
FPGA_TMS
Text HLabel 1900 2000 0    60   BiDi ~ 0
FPGA_TCK
Wire Wire Line
	2150 2000 1900 2000
$EndSCHEMATC