EESchema Schematic File Version 2 date Sun 10 Oct 2010 06:23:22 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 LIBS:usb-48204-0001 LIBS:microsmd075f LIBS:mic2550 LIBS:rj45-48025 LIBS:xue-nv LIBS:xc6slx75fgg484 LIBS:xc6slx45fgg484 LIBS:micron_mobile_ddr LIBS:micron_ddr_512Mb LIBS:k8001 LIBS:device LIBS:transistors LIBS:conn LIBS:linear LIBS:regul LIBS:74xx LIBS:cmos4000 LIBS:adc-dac LIBS:memory LIBS:xilinx LIBS:special LIBS:microcontrollers LIBS:dsp LIBS:microchip LIBS:analog_switches LIBS:motorola LIBS:texas LIBS:intel LIBS:audio LIBS:interface LIBS:digital-audio LIBS:philips LIBS:display LIBS:cypress LIBS:siliconi LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves LIBS:pasives-connectors LIBS:x25x64mb LIBS:attiny LIBS:PSU LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A4 11700 8267 Sheet 2 12 Title "" Date "10 oct 2010" Rev "" Comp "" Comment1 "" Comment2 "" Comment3 "" Comment4 "" $EndDescr Text Label 1650 1450 0 60 ~ 0 FPGA_BANK0_IO_0 Text Label 1650 1550 0 60 ~ 0 FPGA_BANK0_IO_1 Text Label 1650 1750 0 60 ~ 0 FPGA_BANK0_IO_3 Text Label 1650 1650 0 60 ~ 0 FPGA_BANK0_IO_2 Text Label 1650 2050 0 60 ~ 0 FPGA_BANK0_IO_6 Text Label 1650 2150 0 60 ~ 0 FPGA_BANK0_IO_7 Text Label 1650 1950 0 60 ~ 0 FPGA_BANK0_IO_5 Text Label 1650 1850 0 60 ~ 0 FPGA_BANK0_IO_4 Text Label 1650 2650 0 60 ~ 0 FPGA_BANK0_IO_12 Text Label 1650 2750 0 60 ~ 0 FPGA_BANK0_IO_13 Text Label 1650 2950 0 60 ~ 0 FPGA_BANK0_IO_15 Text Label 1650 2850 0 60 ~ 0 FPGA_BANK0_IO_14 Text Label 1650 2450 0 60 ~ 0 FPGA_BANK0_IO_10 Text Label 1650 2550 0 60 ~ 0 FPGA_BANK0_IO_11 Text Label 1650 2350 0 60 ~ 0 FPGA_BANK0_IO_9 Text Label 1650 2250 0 60 ~ 0 FPGA_BANK0_IO_8 Entry Wire Line 2550 1450 2650 1550 Entry Wire Line 2550 1650 2650 1750 Entry Wire Line 2550 1550 2650 1650 Entry Wire Line 2550 1750 2650 1850 Entry Wire Line 2550 1850 2650 1950 Entry Wire Line 2550 1950 2650 2050 Entry Wire Line 2550 2050 2650 2150 Entry Wire Line 2550 2150 2650 2250 Entry Wire Line 2550 2250 2650 2350 Entry Wire Line 2550 2950 2650 3050 Entry Wire Line 2550 2850 2650 2950 Entry Wire Line 2550 2750 2650 2850 Entry Wire Line 2550 2550 2650 2650 Entry Wire Line 2550 2450 2650 2550 Entry Wire Line 2550 2350 2650 2450 Entry Wire Line 2550 2650 2650 2750 Text HLabel 3550 1300 2 60 BiDi ~ 0 FPGA_BANK0_IO_[0..64] Text Label 1650 3050 0 60 ~ 0 FPGA_BANK0_IO_16 Text Label 1650 3150 0 60 ~ 0 FPGA_BANK0_IO_17 Text Label 1650 3350 0 60 ~ 0 FPGA_BANK0_IO_19 Text Label 1650 3250 0 60 ~ 0 FPGA_BANK0_IO_18 Text Label 1650 3650 0 60 ~ 0 FPGA_BANK0_IO_22 Text Label 1650 3750 0 60 ~ 0 FPGA_BANK0_IO_23 Text Label 1650 3550 0 60 ~ 0 FPGA_BANK0_IO_21 Text Label 1650 3450 0 60 ~ 0 FPGA_BANK0_IO_20 Text Label 1650 4250 0 60 ~ 0 FPGA_BANK0_IO_28 Text Label 1650 4350 0 60 ~ 0 FPGA_BANK0_IO_29 Text Label 1650 4550 0 60 ~ 0 FPGA_BANK0_IO_31 Text Label 1650 4450 0 60 ~ 0 FPGA_BANK0_IO_30 Text Label 1650 4050 0 60 ~ 0 FPGA_BANK0_IO_26 Text Label 1650 4150 0 60 ~ 0 FPGA_BANK0_IO_27 Text Label 1650 3950 0 60 ~ 0 FPGA_BANK0_IO_25 Text Label 1650 3850 0 60 ~ 0 FPGA_BANK0_IO_24 Text Label 1650 4650 0 60 ~ 0 FPGA_BANK0_IO_32 Text Label 1650 4750 0 60 ~ 0 FPGA_BANK0_IO_33 Entry Wire Line 2850 5150 2950 5050 Entry Wire Line 2850 5050 2950 4950 Text Label 2950 4950 0 60 ~ 0 FPGA_BANK0_IO_35 Text Label 2950 5050 0 60 ~ 0 FPGA_BANK0_IO_34 Text Label 2950 4850 0 60 ~ 0 FPGA_BANK0_IO_36 Text Label 2950 4750 0 60 ~ 0 FPGA_BANK0_IO_37 Entry Wire Line 2850 4850 2950 4750 Entry Wire Line 2850 4950 2950 4850 Entry Wire Line 2850 4750 2950 4650 Entry Wire Line 2850 4650 2950 4550 Text Label 2950 4550 0 60 ~ 0 FPGA_BANK0_IO_39 Text Label 2950 4650 0 60 ~ 0 FPGA_BANK0_IO_38 Text Label 2950 4450 0 60 ~ 0 FPGA_BANK0_IO_40 Text Label 2950 4350 0 60 ~ 0 FPGA_BANK0_IO_41 Entry Wire Line 2850 4450 2950 4350 Entry Wire Line 2850 4550 2950 4450 Entry Wire Line 2850 4350 2950 4250 Entry Wire Line 2850 4250 2950 4150 Text Label 2950 4150 0 60 ~ 0 FPGA_BANK0_IO_43 Text Label 2950 4250 0 60 ~ 0 FPGA_BANK0_IO_42 Text Label 2950 4050 0 60 ~ 0 FPGA_BANK0_IO_44 Text Label 2950 3950 0 60 ~ 0 FPGA_BANK0_IO_45 Entry Wire Line 2850 4050 2950 3950 Entry Wire Line 2850 4150 2950 4050 Entry Wire Line 2850 3950 2950 3850 Entry Wire Line 2850 3850 2950 3750 Text Label 2950 3750 0 60 ~ 0 FPGA_BANK0_IO_47 Text Label 2950 3850 0 60 ~ 0 FPGA_BANK0_IO_46 Text Label 2950 3650 0 60 ~ 0 FPGA_BANK0_IO_48 Text Label 2950 3550 0 60 ~ 0 FPGA_BANK0_IO_49 Entry Wire Line 2850 3650 2950 3550 Entry Wire Line 2850 3750 2950 3650 Entry Wire Line 2850 3550 2950 3450 Entry Wire Line 2850 3450 2950 3350 Text Label 2950 3350 0 60 ~ 0 FPGA_BANK0_IO_51 Text Label 2950 3450 0 60 ~ 0 FPGA_BANK0_IO_50 Text Label 2950 3250 0 60 ~ 0 FPGA_BANK0_IO_52 Text Label 2950 3150 0 60 ~ 0 FPGA_BANK0_IO_53 Entry Wire Line 2850 3250 2950 3150 Entry Wire Line 2850 3350 2950 3250 Entry Wire Line 2850 3150 2950 3050 Entry Wire Line 2850 3050 2950 2950 Text Label 2950 2950 0 60 ~ 0 FPGA_BANK0_IO_55 Text Label 2950 3050 0 60 ~ 0 FPGA_BANK0_IO_54 Text Label 2950 2250 0 60 ~ 0 FPGA_BANK0_IO_62 Text Label 2950 2150 0 60 ~ 0 FPGA_BANK0_IO_63 Text Label 2950 2350 0 60 ~ 0 FPGA_BANK0_IO_61 Text Label 2950 2450 0 60 ~ 0 FPGA_BANK0_IO_60 Text Label 2950 2050 0 60 ~ 0 FPGA_BANK0_IO_64 Text Label 2950 2850 0 60 ~ 0 FPGA_BANK0_IO_56 Text Label 2950 2750 0 60 ~ 0 FPGA_BANK0_IO_57 Text Label 2950 2550 0 60 ~ 0 FPGA_BANK0_IO_59 Text Label 2950 2650 0 60 ~ 0 FPGA_BANK0_IO_58 Entry Wire Line 2550 4250 2650 4350 Entry Wire Line 2550 3950 2650 4050 Entry Wire Line 2550 4050 2650 4150 Entry Wire Line 2550 4150 2650 4250 Entry Wire Line 2550 4350 2650 4450 Entry Wire Line 2550 4450 2650 4550 Entry Wire Line 2550 4550 2650 4650 Entry Wire Line 2550 3850 2650 3950 Entry Wire Line 2550 3750 2650 3850 Entry Wire Line 2550 3650 2650 3750 Entry Wire Line 2550 3550 2650 3650 Entry Wire Line 2550 3450 2650 3550 Entry Wire Line 2550 3350 2650 3450 Entry Wire Line 2550 3150 2650 3250 Entry Wire Line 2550 3250 2650 3350 Entry Wire Line 2550 3050 2650 3150 Entry Wire Line 2550 4750 2650 4850 Entry Wire Line 2550 4650 2650 4750 Text Label 1650 5050 0 60 ~ 0 FPGA_BANK0_IO_36 Text Label 1650 4850 0 60 ~ 0 FPGA_BANK0_IO_34 Text Label 1650 4950 0 60 ~ 0 FPGA_BANK0_IO_35 Entry Wire Line 2550 4950 2650 5050 Entry Wire Line 2550 5050 2650 5150 Entry Wire Line 2550 4850 2650 4950 Wire Bus Line 2650 5250 2850 5250 Wire Bus Line 2650 1550 2650 5250 Wire Wire Line 1650 4950 2550 4950 Wire Wire Line 2550 4750 1650 4750 Wire Wire Line 3800 2050 2950 2050 Wire Wire Line 3800 2250 2950 2250 Wire Wire Line 3800 2150 2950 2150 Wire Wire Line 3800 2350 2950 2350 Wire Wire Line 3800 2450 2950 2450 Wire Wire Line 3800 3250 2950 3250 Wire Wire Line 3800 3150 2950 3150 Wire Wire Line 3800 2950 2950 2950 Wire Wire Line 3800 3050 2950 3050 Wire Wire Line 2550 3050 1650 3050 Wire Wire Line 1650 4650 2550 4650 Wire Wire Line 2550 1450 1650 1450 Wire Wire Line 2550 1550 1650 1550 Wire Wire Line 2550 1750 1650 1750 Wire Wire Line 2550 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Wire Line 3800 5050 2950 5050 Wire Wire Line 3800 4850 2950 4850 Wire Wire Line 3800 4750 2950 4750 Wire Wire Line 3800 4550 2950 4550 Wire Wire Line 3800 4650 2950 4650 Wire Wire Line 3800 4450 2950 4450 Wire Wire Line 3800 4350 2950 4350 Wire Wire Line 3800 4150 2950 4150 Wire Wire Line 3800 4250 2950 4250 Wire Wire Line 3800 4050 2950 4050 Wire Wire Line 3800 3950 2950 3950 Wire Wire Line 3800 3750 2950 3750 Wire Wire Line 3800 3850 2950 3850 Wire Wire Line 3800 3650 2950 3650 Wire Wire Line 3800 3550 2950 3550 Wire Wire Line 3800 3350 2950 3350 Wire Wire Line 3800 3450 2950 3450 Wire Wire Line 3800 2850 2950 2850 Wire Wire Line 3800 2750 2950 2750 Wire Wire Line 3800 2550 2950 2550 Wire Wire Line 3800 2650 2950 2650 Wire Wire Line 2550 4850 1650 4850 Wire Wire Line 1650 5050 2550 5050 Wire Bus Line 2850 1300 2850 5250 Wire Bus Line 2850 1300 3550 1300 Entry Wire Line 2850 2950 2950 2850 Entry Wire Line 2850 2850 2950 2750 Entry Wire Line 2850 2750 2950 2650 Entry Wire Line 2850 2650 2950 2550 Entry Wire Line 2850 2550 2950 2450 Entry Wire Line 2850 2450 2950 2350 Entry Wire Line 2850 2350 2950 2250 Entry Wire Line 2850 2250 2950 2150 Entry Wire Line 2850 2150 2950 2050 $Comp L CONN_20X2 P2 U 1 1 4CB0D9BF P 6200 1900 F 0 "P2" H 6200 2950 60 0000 C CNN F 1 "CONN_20X2" V 6200 1900 50 0000 C CNN F 2 "header20x2_smd_100mil" H 6140 3010 60 0001 C CNN 1 6200 1900 1 0 0 -1 $EndComp $EndSCHEMATC