EESchema Schematic File Version 2 date Sun 10 Oct 2010 06:23:22 PM COT LIBS:power LIBS:r_pack2 LIBS:v0402mhs03 LIBS:usb-48204-0001 LIBS:microsmd075f LIBS:mic2550 LIBS:rj45-48025 LIBS:xue-nv LIBS:xc6slx75fgg484 LIBS:xc6slx45fgg484 LIBS:micron_mobile_ddr LIBS:micron_ddr_512Mb LIBS:k8001 LIBS:device LIBS:transistors LIBS:conn LIBS:linear LIBS:regul LIBS:74xx LIBS:cmos4000 LIBS:adc-dac LIBS:memory LIBS:xilinx LIBS:special LIBS:microcontrollers LIBS:dsp LIBS:microchip LIBS:analog_switches LIBS:motorola LIBS:texas LIBS:intel LIBS:audio LIBS:interface LIBS:digital-audio LIBS:philips LIBS:display LIBS:cypress LIBS:siliconi LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves LIBS:pasives-connectors LIBS:x25x64mb LIBS:attiny LIBS:PSU LIBS:tps793xx LIBS:reg102 LIBS:mt9m033 LIBS:m12-tu400a LIBS:xue-rnc-cache EELAYER 24 0 EELAYER END $Descr A3 16535 11700 Sheet 1 12 Title "" Date "10 oct 2010" Rev "" Comp "" Comment1 "" Comment2 "" Comment3 "" Comment4 "" $EndDescr Wire Bus Line 9550 5600 10900 5600 Wire Wire Line 5200 4050 6200 4050 Wire Wire Line 5200 3050 6200 3050 Wire Wire Line 5200 3850 6200 3850 Wire Wire Line 5200 3650 6200 3650 Wire Wire Line 6200 3450 5200 3450 Wire Wire Line 5200 3250 6200 3250 Wire Bus Line 6200 4550 5200 4550 Wire Wire Line 3400 4750 3650 4750 Wire Wire Line 3400 4450 3650 4450 Wire Wire Line 3400 4150 3650 4150 Wire Wire Line 10850 10100 9500 10100 Wire Wire Line 10850 9900 9500 9900 Wire Wire Line 6200 5750 5200 5750 Wire Wire Line 6200 5550 5200 5550 Wire Wire Line 10900 4600 9550 4600 Wire Wire Line 10900 4500 9550 4500 Wire Wire Line 10900 4150 9550 4150 Wire Wire Line 10900 3950 9550 3950 Wire Wire Line 10900 3850 9550 3850 Wire Bus Line 10900 4250 9550 4250 Wire Wire Line 10850 1300 9550 1300 Wire Wire Line 9550 3200 10900 3200 Wire Bus Line 10850 1800 9550 1800 Wire Bus Line 9550 2200 10850 2200 Wire Wire Line 10850 9500 9500 9500 Wire Wire Line 10850 9300 9500 9300 Wire Wire Line 9550 2500 10850 2500 Wire Wire Line 9550 2300 10850 2300 Wire Wire Line 9550 2100 10850 2100 Wire Wire Line 9550 1900 10850 1900 Wire Wire Line 9550 1600 10850 1600 Wire Wire Line 9550 1200 10850 1200 Wire Wire Line 9550 950 10850 950 Wire Bus Line 4950 6800 6200 6800 Wire Wire Line 4950 7200 6200 7200 Wire Wire Line 4950 7300 6200 7300 Wire Wire Line 4950 7500 6200 7500 Wire Wire Line 4950 8350 6200 8350 Wire Wire Line 4950 8200 6200 8200 Wire Wire Line 4950 8750 6200 8750 Wire Wire Line 4950 10250 6200 10250 Wire Wire Line 4950 9350 6200 9350 Wire Wire Line 4950 9650 6200 9650 Wire Bus Line 4950 9000 6200 9000 Wire Wire Line 4950 7850 6200 7850 Wire Wire Line 4950 9900 6200 9900 Wire Bus Line 4950 8900 6200 8900 Wire Bus Line 6200 8900 6200 8950 Wire Wire Line 4950 10000 6200 10000 Wire Wire Line 6200 7950 4950 7950 Wire Bus Line 4950 6900 6200 6900 Wire Wire Line 4950 9250 6200 9250 Wire Wire Line 4950 9550 6200 9550 Wire Wire Line 4950 10150 6200 10150 Wire Bus Line 4950 9100 6200 9100 Wire Wire Line 4950 10400 6200 10400 Wire Wire Line 4950 9800 6200 9800 Wire Wire Line 4950 8100 6200 8100 Wire Wire Line 4950 7750 6200 7750 Wire Wire Line 4950 7600 6200 7600 Wire Wire Line 4950 6650 6200 6650 Wire Bus Line 4950 7000 6200 7000 Wire Wire Line 9550 1100 10850 1100 Wire Wire Line 10850 1500 9550 1500 Wire Wire Line 9550 2000 10850 2000 Wire Wire Line 9550 2400 10850 2400 Wire Wire Line 10850 9200 9500 9200 Wire Wire Line 10850 9400 9500 9400 Wire Wire Line 10850 9600 9500 9600 Wire Wire Line 9550 3100 10900 3100 Wire Bus Line 9550 3300 10900 3300 Wire Wire Line 10850 1400 9550 1400 Wire Wire Line 9550 3750 10900 3750 Wire Wire Line 10900 4050 9550 4050 Wire Wire Line 10900 3650 9550 3650 Wire Bus Line 10900 4700 9550 4700 Wire Wire Line 6200 5450 5200 5450 Wire Wire Line 5200 5650 6200 5650 Wire Wire Line 10850 9800 9500 9800 Wire Wire Line 10850 10000 9500 10000 Wire Wire Line 10850 10200 9500 10200 Wire Wire Line 3400 4300 3650 4300 Wire Wire Line 3400 4600 3650 4600 Wire Wire Line 6200 3150 5200 3150 Wire Wire Line 5200 3350 6200 3350 Wire Wire Line 5200 3550 6200 3550 Wire Wire Line 5200 3750 6200 3750 Wire Wire Line 6200 2950 5200 2950 Wire Wire Line 5200 3950 6200 3950 Wire Wire Line 5200 4150 6200 4150 $Sheet S 10900 5250 1050 800 U 4CB0D95D F0 "FPGA GPIOS" 60 F1 "expantion.sch" 60 $EndSheet $Sheet S 3650 2850 1550 2050 U 4C9E2AF4 F0 "Image Sensor" 60 F1 "sensor.sch" 60 F2 "+2.8_VDDIO" B L 3650 4300 60 F3 "+1.8_VDD" B L 3650 4450 60 F4 "+2.8_VAA" B L 3650 4750 60 F5 "+2.8_VAAPIX" B L 3650 4600 60 F6 "+2.8_VDDPLL" B L 3650 4150 60 F7 "IS_TRIGGER" I R 5200 2950 60 F8 "IS_FLASH" O R 5200 3050 60 F9 "IS_SDA" B R 5200 3150 60 F10 "IS_SCL" B R 5200 3250 60 F11 "IS_I2C_ADDR" I R 5200 3350 60 F12 "IS_EXTCLK" I R 5200 3450 60 F13 "IS_RESET_N" I R 5200 3550 60 F14 "IS_OE_N" I R 5200 3650 60 F15 "IS_STANDBY" I R 5200 3750 60 F16 "IS_TEST" I R 5200 3850 60 F17 "IS_PIXEL" O R 5200 3950 60 F18 "IS_LINE" O R 5200 4050 60 F19 "IS_FRAME" O R 5200 4150 60 F20 "IS_DOUT[0..11]" O R 5200 4550 60 $EndSheet $Sheet S 2300 3850 1100 1000 U 4C9E2B0F F0 "Snesor PSU" 60 F1 "sensor_psu.sch" 60 F2 "+2.8_VDDPLL" B R 3400 4150 60 F3 "+2.8_VDDIO" B R 3400 4300 60 F4 "+1.8_VDD" B R 3400 4450 60 F5 "+2.8_VAAPIX" B R 3400 4600 60 F6 "+2.8_VAA" B R 3400 4750 60 $EndSheet $Sheet S 6200 700 3350 5450 U 4C7BC2B2 F0 "FPGA, Port0, Port2, PROG IF" 60 F1 "FPGA_0_2_PROG.sch" 60 F2 "S6_TCK" I L 6200 5450 60 F3 "S6_TDI" I L 6200 5550 60 F4 "S6_TDO" O L 6200 5650 60 F5 "S6_TMS" I L 6200 5750 60 F6 "PROG_MISO[0..3]" B R 9550 4700 60 F7 "PROG_CCLK" O R 9550 4600 60 F8 "PROG_CSO" O R 9550 4500 60 F9 "NF_D[0..7]" B R 9550 4250 60 F10 "ETH_COL" B R 9550 1400 60 F11 "ETH_CRS" B R 9550 1300 60 F12 "NF_WE_N" O R 9550 3950 60 F13 "NF_ALE" O R 9550 3750 60 F14 "NF_CLE" O R 9550 3850 60 F15 "NF_CS1_N" O R 9550 3650 60 F16 "NF_RE_N" O R 9550 4050 60 F17 "NF_RNB" B R 9550 4150 60 F18 "SD_CLK" B R 9550 3100 60 F19 "SD_CMD" B R 9550 3200 60 F20 "SD_DAT[0..3]" B R 9550 3300 60 F21 "ETH_CLK" B R 9550 2500 60 F22 "ETH_RXC" B R 9550 1100 60 F23 "ETH_TXC" B R 9550 2100 60 F24 "ETH_TXD[0..3]" O R 9550 2200 60 F25 "ETH_TXEN" B R 9550 2300 60 F26 "ETH_TXER" B R 9550 2400 60 F27 "ETH_RXER" B R 9550 2000 60 F28 "ETH_RXDV" B R 9550 1900 60 F29 "ETH_RXD[0..3]" I R 9550 1800 60 F30 "ETH_RESET_N" B R 9550 1200 60 F31 "ETH_MDIO" B R 9550 1500 60 F32 "ETH_MDC" B R 9550 1600 60 F33 "ETH_INT" B R 9550 950 60 F34 "IS_DOUT[0..11]" I L 6200 4550 60 F35 "IS_TEST" O L 6200 3850 60 F36 "IS_STANDBY" O L 6200 3750 60 F37 "IS_OE_N" O L 6200 3650 60 F38 "IS_RESET_N" O L 6200 3550 60 F39 "IS_EXTCLK" O L 6200 3450 60 F40 "IS_I2C_ADDR" O L 6200 3350 60 F41 "IS_SCL" B L 6200 3250 60 F42 "IS_SDA" B L 6200 3150 60 F43 "IS_FRAME" I L 6200 4150 60 F44 "IS_LINE" I L 6200 4050 60 F45 "IS_PIXEL" I L 6200 3950 60 F46 "IS_FLASH" I L 6200 3050 60 F47 "IS_TRIGGER" O L 6200 2950 60 F48 "FPGA_BANK0_IO_[0..64]" B R 9550 5600 60 $EndSheet $Sheet S 6200 6400 3300 4350 U 4C7BC2A2 F0 "FPGA Port 1, Port 3 DDR, USB" 60 F1 "FPGA_1_3.sch" 60 F2 "USBD_VP" B R 9500 10100 60 F3 "USBD_SPD" B R 9500 9800 60 F4 "USBD_OE_N" B R 9500 9900 60 F5 "USBD_RCV" B R 9500 10000 60 F6 "USBD_VM" B R 9500 10200 60 F7 "M0_CKE" O L 6200 9800 60 F8 "M0_UDM" O L 6200 9550 60 F9 "M0_UDQS" O L 6200 9250 60 F10 "M0_BA[0..1]" O L 6200 9100 60 F11 "M0_CAS#" O L 6200 10150 60 F12 "M0_RAS#" O L 6200 10250 60 F13 "M0_WE#" O L 6200 10400 60 F14 "M0_LDM" O L 6200 9650 60 F15 "M0_LDQS" O L 6200 9350 60 F16 "M1_UDQS" O L 6200 7200 60 F17 "M1_UDM" O L 6200 7500 60 F18 "M1_LDQS" O L 6200 7300 60 F19 "M1_LDM" O L 6200 7600 60 F20 "M1_WE#" O L 6200 8350 60 F21 "M1_CKE" O L 6200 7750 60 F22 "M1_RAS#" O L 6200 8200 60 F23 "M1_CAS#" O L 6200 8100 60 F24 "M1_BA[0..1]" O L 6200 7000 60 F25 "M1_CS#" O L 6200 6650 60 F26 "USBA_VM" B R 9500 9600 60 F27 "USBA_VP" B R 9500 9500 60 F28 "USBA_RCV" B R 9500 9400 60 F29 "USBA_OE_N" B R 9500 9300 60 F30 "USBA_SPD" B R 9500 9200 60 F31 "M1_DQ[0..15]" B L 6200 6800 60 F32 "M0_CS#" O L 6200 8750 60 F33 "M0_DQ[0..15]" B L 6200 8900 60 F34 "M0_A[0..12]" O L 6200 9000 60 F35 "M1_A[0..12]" O L 6200 6900 60 F36 "M1_CLK" O L 6200 7850 60 F37 "M1_CLK#" O L 6200 7950 60 F38 "M0_CLK" O L 6200 9900 60 F39 "M0_CLK#" O L 6200 10000 60 F40 "FPGA_2.5V_IO_M17" B R 9500 7050 60 F41 "FPGA_2.5V_IO_N16" B R 9500 7150 60 F42 "FPGA_2.5V_IO_P19" B R 9500 7250 60 F43 "FPGA_2.5V_IO_P17" B R 9500 7350 60 F44 "FPGA_2.5V_IO_P18" B R 9500 7450 60 F45 "FPGA_2.5V_IO_U19" B R 9500 7550 60 F46 "FPGA_2.5V_IO_T20" B R 9500 7650 60 F47 "FPGA_2.5V_IO_V20" B R 9500 7750 60 F48 "FPGA_2.5V_IO_W20" B R 9500 7850 60 F49 "FPGA_2.5V_IO_W22" B R 9500 7950 60 F50 "FPGA_2.5V_IO_V3" B R 9500 8050 60 F51 "FPGA_2.5V_IO_U4" B R 9500 8150 60 F52 "FPGA_2.5V_IO_T3" B R 9500 8250 60 F53 "FPGA_2.5V_IO_T4" B R 9500 8350 60 F54 "FPGA_2.5V_IO_P7" B R 9500 8450 60 F55 "FPGA_2.5V_IO_P8" B R 9500 8550 60 F56 "FPGA_2.5V_IO_W1" B R 9500 8650 60 F57 "FPGA_2.5V_IO_W3" B R 9500 8750 60 F58 "FPGA_2.5V_IO_Y1" B R 9500 8850 60 F59 "FPGA_2.5V_IO_Y2" B R 9500 8950 60 $EndSheet $Sheet S 4000 5400 1200 700 U 4C716A4D F0 "DBG_PRG" 60 F1 "DBG_PRG.sch" 60 F2 "FPGA_TDO" B R 5200 5650 60 F3 "FPGA_TDI" B R 5200 5550 60 F4 "FPGA_TMS" B R 5200 5750 60 F5 "FPGA_TCK" B R 5200 5450 60 $EndSheet $Sheet S 4000 950 1200 750 U 4C69ED5F F0 "PSU" 60 F1 "PSU.sch" 60 $EndSheet $Sheet S 10900 2900 1050 1950 U 4C4227FE F0 "Non volatile memories" 60 F1 "NV_MEMORIES.sch" 60 F2 "SD_CMD" I L 10900 3200 60 F3 "SD_CLK" I L 10900 3100 60 F4 "SD_DAT[0..3]" B L 10900 3300 60 F5 "NF_D[0..7]" B L 10900 4250 60 F6 "NF_ALE" B L 10900 3750 60 F7 "NF_CLE" B L 10900 3850 60 F8 "NF_WE_N" B L 10900 3950 60 F9 "NF_CS1_N" B L 10900 3650 60 F10 "NF_RE_N" B L 10900 4050 60 F11 "NF_RNB" B L 10900 4150 60 F12 "SPI_CLK" I L 10900 4600 60 F13 "SPI_FLASH_CS#" I L 10900 4500 60 F14 "SPI_DQ[0..3]" B L 10900 4700 60 $EndSheet $Sheet S 10850 9150 1100 1150 U 4C5F1EDC F0 "USB" 60 F1 "USB.sch" 60 F2 "USBA_SPD" B L 10850 9200 60 F3 "USBA_OE_N" B L 10850 9300 60 F4 "USBA_RCV" B L 10850 9400 60 F5 "USBA_VP" B L 10850 9500 60 F6 "USBA_VM" B L 10850 9600 60 F7 "USBD_SPD" B L 10850 9800 60 F8 "USBD_OE_N" B L 10850 9900 60 F9 "USBD_RCV" B L 10850 10000 60 F10 "USBD_VP" B L 10850 10100 60 F11 "USBD_VM" B L 10850 10200 60 $EndSheet Text Notes 19700 15650 0 60 ~ 0 Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com $Sheet S 10850 850 1300 1800 U 4C4320F3 F0 "Ethernet Phy" 60 F1 "eth_phy.sch" 60 F2 "ETH_RXC" O L 10850 1100 60 F3 "ETH_RST_N" I L 10850 1200 60 F4 "ETH_CRS" O L 10850 1300 60 F5 "ETH_COL" O L 10850 1400 60 F6 "ETH_MDIO" B L 10850 1500 60 F7 "ETH_MDC" I L 10850 1600 60 F8 "ETH_RXD[0..3]" O L 10850 1800 60 F9 "ETH_RXDV" O L 10850 1900 60 F10 "ETH_RXER" O L 10850 2000 60 F11 "ETH_TXC" B L 10850 2100 60 F12 "ETH_TXD[0..3]" I L 10850 2200 60 F13 "ETH_TXEN" I L 10850 2300 60 F14 "ETH_TXER" I L 10850 2400 60 F15 "ETH_CLK" I L 10850 2500 60 F16 "ETH_INT" O L 10850 950 60 $EndSheet $Sheet S 3850 6550 1100 4000 U 4C421DD3 F0 "DDR Banks" 60 F1 "DRAM.sch" 60 F2 "M0_BA[0..1]" I R 4950 9100 60 F3 "M1_BA[0..1]" I R 4950 7000 60 F4 "M0_WE#" I R 4950 10400 60 F5 "M0_RAS#" I R 4950 10250 60 F6 "M1_RAS#" I R 4950 8200 60 F7 "M1_WE#" I R 4950 8350 60 F8 "M0_CAS#" I R 4950 10150 60 F9 "M0_CKE" I R 4950 9800 60 F10 "M0_CLK" I R 4950 9900 60 F11 "M0_CLK#" I R 4950 10000 60 F12 "M0_CS#" I R 4950 8750 60 F13 "M1_CLK#" I R 4950 7950 60 F14 "M1_CLK" I R 4950 7850 60 F15 "M1_CKE" I R 4950 7750 60 F16 "M1_CAS#" I R 4950 8100 60 F17 "M0_DQ[0..15]" B R 4950 8900 60 F18 "M0_UDM" I R 4950 9550 60 F19 "M0_LDQS" I R 4950 9350 60 F20 "M0_A[0..12]" I R 4950 9000 60 F21 "M0_LDM" I R 4950 9650 60 F22 "M0_UDQS" I R 4950 9250 60 F23 "M1_UDQS" I R 4950 7200 60 F24 "M1_LDM" I R 4950 7600 60 F25 "M1_LDQS" I R 4950 7300 60 F26 "M1_UDM" I R 4950 7500 60 F27 "M1_CS#" I R 4950 6650 60 F28 "M1_A[0..12]" I R 4950 6900 60 F29 "M1_DQ[0..15]" B R 4950 6800 60 $EndSheet $EndSCHEMATC