# EESchema Netlist Version 1.1 created  Wed 04 Aug 2010 12:20:48 PM COT
(
 ( /4C4320F3/4C432132 $noname  U4 K8001 {Lib=K8001}
  (    1 ? )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 ? )
  (    7 N-000412 )
  (    8 N-000411 )
  (    9 ? )
  (   10 ? )
  (   11 ? )
  (   12 N-000411 )
  (   13 N-000412 )
  (   14 ? )
  (   15 ? )
  (   16 ? )
  (   17 ? )
  (   18 ? )
  (   19 ? )
  (   20 ? )
  (   21 ? )
  (   22 ? )
  (   23 N-000411 )
  (   24 N-000412 )
  (   25 /Ethernet_Phy/ETH_INT )
  (   26 ? )
  (   27 ? )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 N-000412 )
  (   32 ? )
  (   33 ? )
  (   34 ? )
  (   35 N-000411 )
  (   36 N-000411 )
  (   37 ? )
  (   38 N-000412 )
  (   39 N-000411 )
  (   40 ? )
  (   41 ? )
  (   42 ? )
  (   43 ? )
  (   44 N-000411 )
  (   45 ? )
  (   46 ? )
  (   47 N-000412 )
  (   48 ? )
 )
 ( /4C431A63/4C431E53 $noname  U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
  (   P7 ? )
  (   N7 ? )
  (   M7 ? )
  (   L7 N-000170 )
  (   K7 ? )
  (   J7 ? )
  (   G7 ? )
  (   F7 ? )
  (   P6 ? )
  (   N6 ? )
  (   M6 ? )
  (   L6 ? )
  (   K6 /FPGA_Spartan6/M0_A3 )
  (   J6 ? )
  (   H6 /FPGA_Spartan6/M0_A7 )
  (   G6 ? )
  (   F6 N-000170 )
  (   E6 ? )
  (   U5 N-000170 )
  (   P5 ? )
  (   N5 N-000170 )
  (   M5 ? )
  (   K5 ? )
  (   J5 N-000170 )
  (   H5 /FPGA_Spartan6/M0_A2 )
  (   F5 ? )
  (   E5 ? )
  (   D5 ? )
  (   U4 ? )
  (  H21 ? )
  (  G21 N-000130 )
  (  F21 /DDR_Banks/M1_A0 )
  (  D21 ? )
  (  C21 N-000130 )
  (  B21 ? )
  (  A21 ? )
  (  W20 ? )
  (  V20 ? )
  (  U20 ? )
  (  T20 ? )
  (  R20 ? )
  (  P20 ? )
  (  N20 ? )
  (  M20 ? )
  (  L20 ? )
  (  K20 /FPGA_Spartan6/M1_A5 )
  (  J20 ? )
  (  H20 /DDR_Banks/M1_CLK )
  (  G20 /DDR_Banks/M1_A3 )
  (  F20 /FPGA_Spartan6/M1_A4 )
  (  E20 /FPGA_Spartan6/M1_A7 )
  (  D20 ? )
  (  C20 /FPGA_Spartan6/M1_A8 )
  (  B20 ? )
  (  A20 ? )
  (   P8 ? )
  (   M8 ? )
  (   K8 ? )
  (   H8 ? )
  (   B3 ? )
  (   W2 N-000170 )
  (   V2 /FPGA_Spartan6/M0_DQ14 )
  (   T2 ? )
  (   R2 N-000170 )
  (   P2 /FPGA_Spartan6/M0_DQ8 )
  (   M2 /DDR_Banks/M0_DQ2 )
  (   L2 N-000170 )
  (   K2 /FPGA_Spartan6/M0_DQ6 )
  (   H2 /FPGA_Spartan6/M0_A0 )
  (   G2 N-000170 )
  (   F2 ? )
  (   D2 ? )
  (   C2 N-000170 )
  (   B2 ? )
  (   A2 ? )
  (   Y1 ? )
  (   W1 ? )
  (   V1 /FPGA_Spartan6/M0_DQ15 )
  (   U1 /FPGA_Spartan6/M0_DQ13 )
  (   T1 ? )
  (   R1 /FPGA_Spartan6/M0_DQ11 )
  (   P1 /FPGA_Spartan6/M0_DQ9 )
  (   N1 /DDR_Banks/M0_DQ1 )
  (   M1 /FPGA_Spartan6/M0_DQ3 )
  (   L1 ? )
  (   K1 /FPGA_Spartan6/M0_DQ7 )
  (   J1 /FPGA_Spartan6/M0_DQ5 )
  (   H1 /DDR_Banks/M0_A1 )
  (   G1 ? )
  (   T4 ? )
  (   R4 ? )
  (   P4 ? )
  (   N4 ? )
  (   M4 ? )
  (   L4 ? )
  (   K4 ? )
  (   J4 /FPGA_Spartan6/M0_A6 )
  (   H4 /FPGA_Spartan6/M0_CLK )
  (   G4 /FPGA_Spartan6/M0_A10 )
  (   F4 N-000170 )
  (   E4 ? )
  (   C4 ? )
  (   W3 ? )
  (   V3 ? )
  (   U3 /FPGA_Spartan6/M0_DQ12 )
  (   T3 ? )
  (   R3 /FPGA_Spartan6/M0_DQ10 )
  (   P3 ? )
  (   N3 /FPGA_Spartan6/M0_DQ0 )
  (   M3 ? )
  (   L3 ? )
  (   K3 /FPGA_Spartan6/M0_A5 )
  (   J3 /DDR_Banks/M0_DQ4 )
  (   H3 /DDR_Banks/M0_CLK# )
  (   G3 ? )
  (   F3 /FPGA_Spartan6/M0_A4 )
  (   E3 /DDR_Banks/M0_A8 )
  (   D3 ? )
  (   C3 ? )
  (  G10 N-000138 )
  (  D10 ? )
  (  C10 ? )
  (  B10 ? )
  (  A10 ? )
  (   E9 N-000138 )
  (   D9 ? )
  (   C9 ? )
  (   A9 ? )
  (   D8 ? )
  (   C8 ? )
  (   B8 ? )
  (   A8 ? )
  (   D7 ? )
  (   C7 ? )
  (   B7 N-000138 )
  (   A7 ? )
  (   D6 ? )
  (   C6 ? )
  (   B6 ? )
  (   A6 ? )
  (   C5 ? )
  (   A5 /Ethernet_Phy/ETH_INT )
  (   B4 N-000138 )
  (   A4 ? )
  (  U19 ? )
  (  T19 ? )
  (  R19 ? )
  (  P19 ? )
  (  N19 ? )
  (  B19 N-000138 )
  (  B18 ? )
  (  A18 ? )
  (  E17 N-000138 )
  (  D17 ? )
  (  C17 ? )
  (  A17 ? )
  (  E16 ? )
  (  C16 ? )
  (  B16 ? )
  (  A16 ? )
  (  D15 ? )
  (  C15 ? )
  (  B15 N-000138 )
  (  A15 ? )
  (  G14 N-000138 )
  (  D14 ? )
  (  C14 ? )
  (  B14 ? )
  (  A14 ? )
  (  E13 N-000138 )
  (  C13 ? )
  (  A13 ? )
  (  C12 ? )
  (  B12 ? )
  (  A12 ? )
  (  D11 ? )
  (  C11 ? )
  (  B11 N-000138 )
  (  A11 ? )
  (  H16 ? )
  (  G16 ? )
  (  F16 ? )
  (  L15 ? )
  (  W22 ? )
  (  V22 ? )
  (  U22 ? )
  (  T22 ? )
  (  R22 ? )
  (  P22 ? )
  (  N22 ? )
  (  M22 ? )
  (  L22 ? )
  (  K22 ? )
  (  J22 ? )
  (  H22 ? )
  (  G22 ? )
  (  F22 /DDR_Banks/M1_A1 )
  (  E22 /FPGA_Spartan6/M1_A2 )
  (  D22 /DDR_Banks/M1_A12 )
  (  C22 /DDR_Banks/M1_A9 )
  (  B22 ? )
  (  W21 N-000130 )
  (  V21 ? )
  (  T21 ? )
  (  R21 N-000130 )
  (  P21 ? )
  (  M21 ? )
  (  L21 N-000130 )
  (  K21 ? )
  (  M19 ? )
  (  L19 ? )
  (  K19 /DDR_Banks/M1_A6 )
  (  J19 /FPGA_Spartan6/M1_CLK# )
  (  H19 ? )
  (  G19 /FPGA_Spartan6/M1_A10 )
  (  F19 /FPGA_Spartan6/M1_A11 )
  (  E19 N-000130 )
  (  D19 ? )
  (  U18 N-000130 )
  (  P18 ? )
  (  N18 N-000130 )
  (  M18 ? )
  (  K18 ? )
  (  J18 N-000130 )
  (  H18 ? )
  (  F18 ? )
  (  P17 ? )
  (  M17 ? )
  (  L17 ? )
  (  K17 ? )
  (  J17 ? )
  (  H17 ? )
  (  G17 ? )
  (  F17 ? )
  (  N16 ? )
  (  M16 ? )
  (  L16 N-000130 )
  (  K16 ? )
  (  J16 ? )
  (  J14 N-000171 )
  (  H14 ? )
  (  F14 ? )
  (  E14 ? )
  (  P13 N-000171 )
  (  N13 GND )
  (  M13 N-000171 )
  (  L13 GND )
  (  K13 N-000171 )
  (  J13 GND )
  (  H13 ? )
  (  G13 ? )
  (  F13 ? )
  (  D13 ? )
  (  B13 GND )
  (  Y22 ? )
  (  A22 GND )
  (  R12 N-000172 )
  (  P12 GND )
  (  N12 N-000171 )
  (  M12 GND )
  (  L12 N-000171 )
  (  K12 GND )
  (  J12 N-000171 )
  (  H12 ? )
  (  G12 N-000172 )
  (  F12 ? )
  (  E12 ? )
  (  D12 ? )
  (  AB1 GND )
  (  A19 ? )
  (  R18 GND )
  (  L18 GND )
  (  G18 GND )
  (  E18 ? )
  (  D18 GND )
  (  C18 ? )
  (  R17 ? )
  (  N17 GND )
  (  B17 GND )
  (  W16 GND )
  (  P16 ? )
  (  D16 N-000172 )
  (  AA5 GND )
  (  P15 ? )
  (  N15 ? )
  (  M15 N-000172 )
  (  K15 N-000172 )
  (  J15 GND )
  (  H15 N-000172 )
  (  G15 ? )
  (  F15 ? )
  (  E15 GND )
  (  V14 GND )
  (  R14 N-000171 )
  (  P14 GND )
  (  N14 N-000171 )
  (  M14 GND )
  (  L14 N-000171 )
  (  K14 GND )
  (   L9 GND )
  (   K9 N-000171 )
  (   J9 GND )
  (   H9 N-000172 )
  (   G9 ? )
  (   F9 ? )
  (   B9 GND )
  (   N8 N-000172 )
  (   L8 N-000172 )
  (   J8 N-000171 )
  (   G8 ? )
  (   F8 ? )
  (   E8 ? )
  (   W7 GND )
  (   U7 GND )
  (   H7 GND )
  (   E7 GND )
  (   V6 N-000172 )
  (   R6 N-000172 )
  (   R5 GND )
  (   L5 GND )
  (   G5 GND )
  (   B5 GND )
  (   V4 GND )
  (   D4 GND )
  (   U2 GND )
  (   N2 GND )
  (   J2 GND )
  (   E2 GND )
  (   A1 GND )
  (  AA1 ? )
  (  U21 GND )
  (  N21 GND )
  (  J21 GND )
  (  E21 GND )
  (  U11 N-000172 )
  (  P11 N-000171 )
  (  N11 GND )
  (  M11 N-000171 )
  (  L11 GND )
  (  K11 N-000171 )
  (  J11 GND )
  (  H11 ? )
  (  G11 ? )
  (  F11 N-000172 )
  (  E11 GND )
  (  V10 GND )
  (  R10 N-000172 )
  (  P10 GND )
  (  N10 N-000171 )
  (  M10 GND )
  (  L10 N-000171 )
  (  K10 GND )
  (  J10 N-000171 )
  (  H10 ? )
  (  F10 ? )
  (  E10 ? )
  (   P9 N-000171 )
  (   N9 GND )
  (   M9 N-000171 )
  (  V19 ? )
  (  AB8 ? )
  (  AA8 ? )
  (  Y18 ? )
  (  W18 ? )
  (  V18 ? )
  (  T18 ? )
  (  AB7 ? )
  (  AA7 N-000169 )
  (  Y17 ? )
  (  W17 ? )
  (  V17 ? )
  (  U17 ? )
  (  T17 ? )
  (  AB6 ? )
  (  AA6 ? )
  (  Y16 ? )
  (  V16 N-000169 )
  (  U16 ? )
  (  T16 ? )
  (  R16 ? )
  (  AB5 ? )
  (  Y15 ? )
  (  W15 ? )
  (  V15 ? )
  (  U15 ? )
  (  T15 ? )
  (  R15 ? )
  (  AB4 ? )
  (  AA4 ? )
  (   F1 ? )
  (   E1 /FPGA_Spartan6/M0_A9 )
  (   D1 /FPGA_Spartan6/M0_A12 )
  (   C1 /FPGA_Spartan6/M0_A11 )
  (   B1 ? )
  ( AB19 ? )
  ( AA19 N-000169 )
  ( AB18 ? )
  ( AA18 ? )
  ( AB17 ? )
  ( AB16 ? )
  ( AA16 ? )
  ( AB15 ? )
  ( AA15 N-000169 )
  ( AB14 ? )
  ( AA14 ? )
  ( AB13 ? )
  ( AA22 ? )
  ( AB12 ? )
  ( AA12 ? )
  ( AB21 ? )
  ( AA21 ? )
  ( AB11 ? )
  ( AA11 N-000169 )
  ( AB20 ? )
  ( AA20 ? )
  ( AB10 ? )
  ( AA10 ? )
  (  AB9 ? )
  (  Y19 ? )
  (   V9 ? )
  (   U9 ? )
  (   T9 N-000169 )
  (   R9 ? )
  (   Y8 ? )
  (   W8 ? )
  (   V8 N-000169 )
  (   U8 ? )
  (   T8 ? )
  (   R8 ? )
  (   Y7 ? )
  (   V7 ? )
  (   T7 ? )
  (   R7 ? )
  (   Y6 ? )
  (   W6 ? )
  (   U6 ? )
  (   T6 ? )
  (   Y5 ? )
  (   W5 N-000169 )
  (   V5 ? )
  (   T5 ? )
  (   Y4 ? )
  (   W4 ? )
  (   Y3 ? )
  ( AA17 GND )
  ( AA13 GND )
  ( AB22 GND )
  (  AA9 GND )
  (  W19 GND )
  (  Y14 ? )
  (  W14 ? )
  (  U14 ? )
  (  T14 ? )
  (  AB3 ? )
  (  AA3 N-000169 )
  (  Y13 ? )
  (  W13 ? )
  (  V13 ? )
  (  U13 ? )
  (  T13 N-000169 )
  (  R13 ? )
  (  AB2 ? )
  (  AA2 ? )
  (  Y12 ? )
  (  W12 ? )
  (  V12 N-000169 )
  (  U12 ? )
  (  T12 ? )
  (  Y11 ? )
  (  W11 ? )
  (  V11 ? )
  (  T11 ? )
  (  R11 ? )
  (  Y10 ? )
  (  W10 ? )
  (  U10 ? )
  (  T10 ? )
  (   Y9 ? )
  (   W9 ? )
 )
 ( /4C4227FE/4B76F5E2 $noname  J1 MICROSD {Lib=MICROSD}
  ( CASE GND )
  (  COM GND )
  (   CD ? )
  (    1 ? )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 ? )
  (    7 ? )
  (    8 ? )
 )
 ( /4C4227FE/4B76F108 $noname  U5 NAND {Lib=HY27UG088G5M}
  (    1 ? )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 /Non_volatile_memories/FRB_N )
  (    7 /Non_volatile_memories/FRB_N )
  (    8 ? )
  (    9 ? )
  (   10 ? )
  (   11 ? )
  (   12 3.3V )
  (   13 GND )
  (   14 ? )
  (   15 ? )
  (   16 ? )
  (   17 ? )
  (   18 ? )
  (   19 3.3V )
  (   20 ? )
  (   21 ? )
  (   22 ? )
  (   23 ? )
  (   24 ? )
  (   25 ? )
  (   26 ? )
  (   27 ? )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 ? )
  (   32 ? )
  (   33 ? )
  (   34 ? )
  (   35 ? )
  (   36 GND )
  (   37 3.3V )
  (   38 ? )
  (   39 ? )
  (   40 ? )
  (   41 ? )
  (   42 ? )
  (   43 ? )
  (   44 ? )
  (   45 ? )
  (   46 ? )
  (   47 ? )
  (   48 ? )
 )
 ( /4C421DD3/4C58CA3A 60fbga_ddr  U3 MT46V32M16FN {Lib=MT46V32M16FN}
  (   A7 N-000036 )
  (   B7 ? )
  (   C7 ? )
  (   D7 ? )
  (   E7 ? )
  (   F7 ? )
  (   G7 ? )
  (   H7 ? )
  (   J7 ? )
  (   K7 /DDR_Banks/M1_A0 )
  (   L7 /FPGA_Spartan6/M1_A2 )
  (   M7 N-000036 )
  (   A8 ? )
  (   B8 GND )
  (   C8 N-000036 )
  (   D8 GND )
  (   E8 N-000036 )
  (   F8 N-000036 )
  (   G8 ? )
  (   H8 ? )
  (   J8 ? )
  (   K8 /FPGA_Spartan6/M1_A10 )
  (   L8 /DDR_Banks/M1_A1 )
  (   M8 /DDR_Banks/M1_A3 )
  (   A9 N-000036 )
  (   B9 ? )
  (   C9 ? )
  (   D9 ? )
  (   E9 ? )
  (   F9 ? )
  (   A1 GND )
  (   B1 ? )
  (   C1 ? )
  (   D1 ? )
  (   E1 ? )
  (   F1 ? )
  (   A2 ? )
  (   B2 N-000036 )
  (   C2 GND )
  (   D2 N-000036 )
  (   E2 GND )
  (   F2 GND )
  (   G2 /DDR_Banks/M1_CLK )
  (   H2 /DDR_Banks/M1_A12 )
  (   J2 /FPGA_Spartan6/M1_A11 )
  (   K2 /FPGA_Spartan6/M1_A8 )
  (   L2 /DDR_Banks/M1_A6 )
  (   M2 /FPGA_Spartan6/M1_A4 )
  (   A3 GND )
  (   B3 ? )
  (   C3 ? )
  (   D3 ? )
  (   E3 ? )
  (   F3 ? )
  (   G3 /FPGA_Spartan6/M1_CLK# )
  (   H3 ? )
  (   J3 /DDR_Banks/M1_A9 )
  (   K3 /FPGA_Spartan6/M1_A7 )
  (   L3 /FPGA_Spartan6/M1_A5 )
  (   M3 GND )
 )
 ( /4C421DD3/4C58C847 60fbga_ddr  U2 MT46V32M16FN {Lib=MT46V32M16FN}
  (   A7 N-000040 )
  (   B7 /DDR_Banks/M0_DQ2 )
  (   C7 /DDR_Banks/M0_DQ4 )
  (   D7 /FPGA_Spartan6/M0_DQ6 )
  (   E7 ? )
  (   F7 ? )
  (   G7 ? )
  (   H7 ? )
  (   J7 ? )
  (   K7 /FPGA_Spartan6/M0_A0 )
  (   L7 /FPGA_Spartan6/M0_A2 )
  (   M7 N-000040 )
  (   A8 /FPGA_Spartan6/M0_DQ0 )
  (   B8 GND )
  (   C8 N-000040 )
  (   D8 GND )
  (   E8 N-000040 )
  (   F8 N-000040 )
  (   G8 ? )
  (   H8 ? )
  (   J8 ? )
  (   K8 /FPGA_Spartan6/M0_A10 )
  (   L8 /DDR_Banks/M0_A1 )
  (   M8 /FPGA_Spartan6/M0_A3 )
  (   A9 N-000040 )
  (   B9 /DDR_Banks/M0_DQ1 )
  (   C9 /FPGA_Spartan6/M0_DQ3 )
  (   D9 /FPGA_Spartan6/M0_DQ5 )
  (   E9 /FPGA_Spartan6/M0_DQ7 )
  (   F9 ? )
  (   A1 GND )
  (   B1 /FPGA_Spartan6/M0_DQ14 )
  (   C1 /FPGA_Spartan6/M0_DQ12 )
  (   D1 /FPGA_Spartan6/M0_DQ10 )
  (   E1 /FPGA_Spartan6/M0_DQ8 )
  (   F1 ? )
  (   A2 /FPGA_Spartan6/M0_DQ15 )
  (   B2 N-000040 )
  (   C2 GND )
  (   D2 N-000040 )
  (   E2 GND )
  (   F2 GND )
  (   G2 /FPGA_Spartan6/M0_CLK )
  (   H2 /FPGA_Spartan6/M0_A12 )
  (   J2 /FPGA_Spartan6/M0_A11 )
  (   K2 /DDR_Banks/M0_A8 )
  (   L2 /FPGA_Spartan6/M0_A6 )
  (   M2 /FPGA_Spartan6/M0_A4 )
  (   A3 GND )
  (   B3 /FPGA_Spartan6/M0_DQ13 )
  (   C3 /FPGA_Spartan6/M0_DQ11 )
  (   D3 /FPGA_Spartan6/M0_DQ9 )
  (   E3 ? )
  (   F3 ? )
  (   G3 /DDR_Banks/M0_CLK# )
  (   H3 ? )
  (   J3 /FPGA_Spartan6/M0_A9 )
  (   K3 /FPGA_Spartan6/M0_A7 )
  (   L3 /FPGA_Spartan6/M0_A5 )
  (   M3 GND )
 )
)
*
{ Pin List by Nets
Net 25 "/DDR Banks/M1_CLK" "M1_CLK"
 U1 H20
 U3 G2
Net 26 "/FPGA Spartan6/M1_CLK#" "M1_CLK#"
 U1 J19
 U3 G3
Net 27 "/FPGA Spartan6/M0_CLK" "M0_CLK"
 U2 G2
 U1 H4
Net 28 "/DDR Banks/M0_CLK#" "M0_CLK#"
 U2 G3
 U1 H3
Net 29 "/Ethernet Phy/ETH_INT" "ETH_INT"
 U4 25
 U1 A5
Net 36 "" ""
 U3 M7
 U3 A7
 U3 C8
 U3 E8
 U3 F8
 U3 B2
 U3 D2
 U3 A9
Net 39 "GND" "GND"
 U1 A1
 U1 B9
 U5 36
 U5 13
 J1 CASE
 J1 CASE
 J1 CASE
 J1 COM
 U1 W7
 U1 U7
 U1 H7
 U1 J11
 U1 L11
 U1 N11
 U2 M3
 U1 E21
 U1 J21
 U1 N21
 U1 U21
 U2 B8
 U2 D8
 U1 K12
 U1 E15
 U1 V14
 U1 P14
 U1 N9
 U1 K10
 U1 M14
 U1 K14
 U1 M10
 U1 P10
 U2 E2
 U2 F2
 U1 V10
 U2 A3
 U1 N13
 U1 L13
 U1 E7
 U1 R5
 U1 L5
 U1 G5
 U1 B5
 U1 J13
 U2 A1
 U1 B13
 U1 A22
 U1 P12
 U2 C2
 U1 AB1
 U1 J9
 U1 L9
 U1 M12
 U1 E11
 U1 D18
 U1 N17
 U1 B17
 U1 W16
 U1 AA5
 U1 J15
 U1 J2
 U1 AA17
 U1 AA13
 U1 AB22
 U1 AA9
 U1 W19
 U1 R18
 U1 E2
 U1 V4
 U1 D4
 U1 U2
 U1 N2
 U1 L18
 U1 G18
 U3 A3
 U3 F2
 U3 E2
 U3 C2
 U3 A1
 U3 D8
 U3 B8
 U3 M3
Net 40 "" ""
 U2 A7
 U2 A9
 U2 M7
 U2 C8
 U2 E8
 U2 F8
 U2 B2
 U2 D2
Net 45 "3.3V" "3.3V"
 U5 19
 U5 12
 U5 37
Net 49 "/Non volatile memories/FRB_N" "FRB_N"
 U5 6
 U5 7
Net 130 "" ""
 U1 W21
 U1 R21
 U1 L21
 U1 L16
 U1 G21
 U1 C21
 U1 E19
 U1 J18
 U1 N18
 U1 U18
Net 138 "" ""
 U1 B4
 U1 B7
 U1 E13
 U1 G14
 U1 B15
 U1 B11
 U1 G10
 U1 E9
 U1 B19
 U1 E17
Net 169 "" ""
 U1 AA7
 U1 V16
 U1 AA3
 U1 AA19
 U1 AA11
 U1 AA15
 U1 W5
 U1 V12
 U1 T13
 U1 V8
 U1 T9
Net 170 "" ""
 U1 L7
 U1 J5
 U1 N5
 U1 R2
 U1 L2
 U1 G2
 U1 C2
 U1 F4
 U1 F6
 U1 U5
 U1 W2
Net 171 "" ""
 U1 K13
 U1 N10
 U1 L10
 U1 J10
 U1 P9
 U1 M9
 U1 K9
 U1 M13
 U1 P13
 U1 J14
 U1 L14
 U1 N14
 U1 R14
 U1 J12
 U1 L12
 U1 N12
 U1 J8
 U1 P11
 U1 M11
 U1 K11
Net 172 "" ""
 U1 U11
 U1 H9
 U1 F11
 U1 R10
 U1 D16
 U1 M15
 U1 K15
 U1 H15
 U1 N8
 U1 L8
 U1 V6
 U1 R6
 U1 R12
 U1 G12
Net 411 "" ""
 U4 39
 U4 12
 U4 44
 U4 36
 U4 23
 U4 8
 U4 35
Net 412 "" ""
 U4 7
 U4 13
 U4 31
 U4 38
 U4 47
 U4 24
Net 422 "/FPGA Spartan6/M0_DQ7" "M0_DQ7"
 U1 K1
 U2 E9
Net 423 "/FPGA Spartan6/M0_DQ8" "M0_DQ8"
 U1 P2
 U2 E1
Net 424 "/FPGA Spartan6/M0_DQ9" "M0_DQ9"
 U1 P1
 U2 D3
Net 425 "/FPGA Spartan6/M0_DQ10" "M0_DQ10"
 U1 R3
 U2 D1
Net 426 "/FPGA Spartan6/M0_DQ11" "M0_DQ11"
 U1 R1
 U2 C3
Net 427 "/FPGA Spartan6/M0_DQ12" "M0_DQ12"
 U2 C1
 U1 U3
Net 428 "/FPGA Spartan6/M0_DQ13" "M0_DQ13"
 U2 B3
 U1 U1
Net 429 "/FPGA Spartan6/M0_DQ14" "M0_DQ14"
 U1 V2
 U2 B1
Net 430 "/FPGA Spartan6/M0_DQ15" "M0_DQ15"
 U1 V1
 U2 A2
Net 431 "/FPGA Spartan6/M0_A0" "M0_A0"
 U2 K7
 U1 H2
Net 432 "/DDR Banks/M0_A1" "M0_A1"
 U2 L8
 U1 H1
Net 433 "/FPGA Spartan6/M0_A2" "M0_A2"
 U1 H5
 U2 L7
Net 434 "/FPGA Spartan6/M0_A3" "M0_A3"
 U2 M8
 U1 K6
Net 435 "/FPGA Spartan6/M0_A4" "M0_A4"
 U2 M2
 U1 F3
Net 436 "/FPGA Spartan6/M0_A5" "M0_A5"
 U1 K3
 U2 L3
Net 437 "/FPGA Spartan6/M0_A6" "M0_A6"
 U2 L2
 U1 J4
Net 438 "/FPGA Spartan6/M0_A7" "M0_A7"
 U2 K3
 U1 H6
Net 439 "/DDR Banks/M0_A8" "M0_A8"
 U1 E3
 U2 K2
Net 440 "/FPGA Spartan6/M0_DQ0" "M0_DQ0"
 U2 A8
 U1 N3
Net 441 "/DDR Banks/M0_DQ1" "M0_DQ1"
 U2 B9
 U1 N1
Net 442 "/DDR Banks/M0_DQ2" "M0_DQ2"
 U1 M2
 U2 B7
Net 443 "/FPGA Spartan6/M0_DQ3" "M0_DQ3"
 U1 M1
 U2 C9
Net 444 "/DDR Banks/M0_DQ4" "M0_DQ4"
 U1 J3
 U2 C7
Net 445 "/FPGA Spartan6/M0_DQ5" "M0_DQ5"
 U2 D9
 U1 J1
Net 446 "/FPGA Spartan6/M0_DQ6" "M0_DQ6"
 U2 D7
 U1 K2
Net 447 "/DDR Banks/M1_A9" "M1_A9"
 U3 J3
 U1 C22
Net 448 "/FPGA Spartan6/M1_A10" "M1_A10"
 U3 K8
 U1 G19
Net 449 "/FPGA Spartan6/M1_A11" "M1_A11"
 U1 F19
 U3 J2
Net 450 "/DDR Banks/M1_A12" "M1_A12"
 U3 H2
 U1 D22
Net 467 "/FPGA Spartan6/M0_A9" "M0_A9"
 U1 E1
 U2 J3
Net 468 "/FPGA Spartan6/M0_A10" "M0_A10"
 U1 G4
 U2 K8
Net 469 "/FPGA Spartan6/M0_A11" "M0_A11"
 U1 C1
 U2 J2
Net 470 "/FPGA Spartan6/M0_A12" "M0_A12"
 U2 H2
 U1 D1
Net 471 "/DDR Banks/M1_A0" "M1_A0"
 U1 F21
 U3 K7
Net 472 "/DDR Banks/M1_A1" "M1_A1"
 U1 F22
 U3 L8
Net 473 "/FPGA Spartan6/M1_A2" "M1_A2"
 U1 E22
 U3 L7
Net 474 "/DDR Banks/M1_A3" "M1_A3"
 U1 G20
 U3 M8
Net 475 "/FPGA Spartan6/M1_A4" "M1_A4"
 U1 F20
 U3 M2
Net 476 "/FPGA Spartan6/M1_A5" "M1_A5"
 U1 K20
 U3 L3
Net 477 "/DDR Banks/M1_A6" "M1_A6"
 U3 L2
 U1 K19
Net 478 "/FPGA Spartan6/M1_A7" "M1_A7"
 U1 E20
 U3 K3
Net 479 "/FPGA Spartan6/M1_A8" "M1_A8"
 U3 K2
 U1 C20
}
#End