EESchema Schematic File Version 2  date Sat 07 Aug 2010 12:35:03 PM COT
LIBS:power,/home/juan64bits/emQbit/xue/kicad/library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,./xue-rnc.cache
EELAYER 24  0
EELAYER END
$Descr A4 11700 8267
Sheet 1 5
Title ""
Date "4 aug 2010"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Bus Line
	2750 3350 4000 3350
Wire Wire Line
	2750 2200 4000 2200
Wire Wire Line
	2750 4250 4000 4250
Wire Bus Line
	2750 3250 4000 3250
Wire Bus Line
	4000 3250 4000 3300
Wire Wire Line
	7800 4550 7350 4550
Wire Wire Line
	2750 4350 4000 4350
Wire Wire Line
	4000 2300 2750 2300
Wire Bus Line
	2750 1250 4000 1250
$Sheet
S 7800 4450 1450 2200
U 4C4320F3
F0 "Ethernet Phy" 60
F1 "eth_phy.sch" 60
F2 "ETH_RXC" O L 7800 4700 60 
F3 "ETH_RST_N" I L 7800 4800 60 
F4 "ETH_CRS" O L 7800 4900 60 
F5 "ETH_COL" O L 7800 5000 60 
F6 "ETH_INT" O L 7800 4550 60 
F7 "ETH_MDIO" B L 7800 5100 60 
F8 "ETH_MDC" I L 7800 5200 60 
F9 "ETH_RXD[0..3]" O L 7800 5400 60 
F10 "ETH_RXDV" O L 7800 5500 60 
F11 "ETH_RXER" O L 7800 5600 60 
F12 "ETH_TXC" B L 7800 5700 60 
F13 "ETH_TXD[0..3]" I L 7800 5800 60 
F14 "ETH_TXEN" I L 7800 5900 60 
F15 "ETH_TXER" I L 7800 6000 60 
F16 "ETH_CLK" I L 7800 6100 60 
$EndSheet
$Sheet
S 4000 900  3350 5800
U 4C431A63
F0 "FPGA Spartan6" 60
F1 "FPGA.sch" 60
F2 "M1_CLK" O L 4000 2200 60 
F3 "M1_CLK#" O L 4000 2300 60 
F4 "M0_CLK" O L 4000 4250 60 
F5 "M0_CLK#" O L 4000 4350 60 
F6 "ETH_INT" I R 7350 4550 60 
F7 "M0_A[0..12]" O L 4000 3350 60 
F8 "M1_A[0..12]" O L 4000 1250 60 
F9 "M0_DQ[0..15]" B L 4000 3250 60 
$EndSheet
$Sheet
S 8700 900  1150 1850
U 4C4227FE
F0 "Non volatile memories" 60
F1 "NV_MEMORIES.sch" 60
$EndSheet
$Sheet
S 1650 900  1100 4000
U 4C421DD3
F0 "DDR Banks" 60
F1 "DRAM.sch" 60
F2 "M0_BA[0..1]" I R 2750 3450 60 
F3 "M1_BA[0..1]" I R 2750 1350 60 
F4 "M0_WE#" I R 2750 4750 60 
F5 "M0_RAS#" I R 2750 4600 60 
F6 "M1_RAS#" I R 2750 2550 60 
F7 "M1_WE#" I R 2750 2700 60 
F8 "M0_CAS#" I R 2750 4500 60 
F9 "M0_CKE" I R 2750 4150 60 
F10 "M0_CLK" I R 2750 4250 60 
F11 "M0_CLK#" I R 2750 4350 60 
F12 "M0_CS#" I R 2750 3100 60 
F13 "M1_CLK#" I R 2750 2300 60 
F14 "M1_CLK" I R 2750 2200 60 
F15 "M1_CKE" I R 2750 2100 60 
F16 "M1_CAS#" I R 2750 2450 60 
F17 "M0_DQ[0..15]" B R 2750 3250 60 
F18 "M0_UDM" I R 2750 3900 60 
F19 "M0_LDQS" I R 2750 3700 60 
F20 "M0_A[0..12]" I R 2750 3350 60 
F21 "M0_LDM" I R 2750 4000 60 
F22 "M0_UDQS" I R 2750 3600 60 
F23 "M1_UDQS" I R 2750 1550 60 
F24 "M1_LDM" I R 2750 1950 60 
F25 "M1_LDQS" I R 2750 1650 60 
F26 "M1_UDM" I R 2750 1850 60 
F27 "M1_CS#" I R 2750 1000 60 
F28 "M1_A[0..12]" I R 2750 1250 60 
F29 "M1_DQ[0..15]" B R 2750 1150 60 
$EndSheet
$EndSCHEMATC