# EESchema Netlist Version 1.1 created  Mon 09 Aug 2010 03:31:28 PM COT
(
 ( /4C431A63/4C431E53 $noname  U1 XC6SLX45FGG484 {Lib=XC6SLX45FGG484}
  (   H9 N-000119 )
  (  U11 N-000119 )
  (  F11 N-000119 )
  (   R6 N-000119 )
  (  M15 N-000119 )
  (   V6 N-000119 )
  (  G12 N-000119 )
  (  H15 N-000119 )
  (  D16 N-000119 )
  (  K15 N-000119 )
  (  R12 N-000119 )
  (   N8 N-000119 )
  (  R10 N-000119 )
  (   L8 N-000119 )
  (  N10 N-000118 )
  (  P11 N-000118 )
  (  P13 N-000118 )
  (   P9 N-000118 )
  (  R14 N-000118 )
  (  N12 N-000118 )
  (  J10 N-000118 )
  (  J12 N-000118 )
  (  J14 N-000118 )
  (   J8 N-000118 )
  (  K11 N-000118 )
  (  K13 N-000118 )
  (   K9 N-000118 )
  (  L10 N-000118 )
  (  L12 N-000118 )
  (  L14 N-000118 )
  (  M11 N-000118 )
  (  M13 N-000118 )
  (   M9 N-000118 )
  (  N14 N-000118 )
  (  G13 ? )
  (   G8 ? )
  (   G9 ? )
  (  H10 ? )
  (  H11 ? )
  (  H12 ? )
  (  H13 ? )
  (  H14 ? )
  (  P16 ? )
  (  D13 ? )
  (  AA1 ? )
  (  N15 ? )
  (  G15 ? )
  (  E18 ? )
  (  A19 ? )
  (  C18 ? )
  (  G11 ? )
  (   F9 ? )
  (   F8 ? )
  (  F15 ? )
  (  F14 ? )
  (  F13 ? )
  (  F12 ? )
  (  F10 ? )
  (   E8 ? )
  (  E14 ? )
  (  E12 ? )
  (  E10 ? )
  (  D12 ? )
  (  P15 ? )
  (  R17 ? )
  (  Y22 ? )
  (  P10 GND )
  (  V10 GND )
  (  M10 GND )
  (  K10 GND )
  (  L13 GND )
  (   A1 GND )
  (  N13 GND )
  (  A22 GND )
  (   R5 GND )
  ( AA13 GND )
  (  W19 GND )
  ( AA17 GND )
  (  K14 GND )
  (  AA5 GND )
  (   L5 GND )
  (  AA9 GND )
  (  M14 GND )
  (  AB1 GND )
  (   N2 GND )
  ( AB22 GND )
  (  P14 GND )
  (  B13 GND )
  (  U21 GND )
  (  B17 GND )
  (   V4 GND )
  (   B5 GND )
  (   J9 GND )
  (   B9 GND )
  (  K12 GND )
  (  D18 GND )
  (  L11 GND )
  (   D4 GND )
  (  L18 GND )
  (  E11 GND )
  (   L9 GND )
  (  E15 GND )
  (  M12 GND )
  (   E2 GND )
  (  N11 GND )
  (  E21 GND )
  (  N17 GND )
  (   E7 GND )
  (  N21 GND )
  (  G18 GND )
  (  P12 GND )
  (   G5 GND )
  (  R18 GND )
  (   H7 GND )
  (   U2 GND )
  (  J11 GND )
  (   U7 GND )
  (  J13 GND )
  (  V14 GND )
  (  J15 GND )
  (  W16 GND )
  (   J2 GND )
  (   W7 GND )
  (  J21 GND )
  (   N9 GND )
  ( AA15 N-000123 )
  (  V16 N-000123 )
  (  T13 N-000123 )
  (   V8 N-000123 )
  (  V12 N-000123 )
  (  AA3 N-000123 )
  (   T9 N-000123 )
  ( AA19 N-000123 )
  ( AA11 N-000123 )
  (   W5 N-000123 )
  (  AA7 N-000123 )
  ( AA12 ? )
  ( AB12 ? )
  (  Y11 ? )
  ( AB11 ? )
  (  R11 ? )
  (  T11 ? )
  ( AA10 ? )
  ( AB10 ? )
  (  V11 ? )
  (  W11 ? )
  (   Y9 ? )
  (  AB9 ? )
  (  W10 ? )
  (  Y10 ? )
  (  AA8 ? )
  (  AB8 ? )
  (   W8 ? )
  (   V7 ? )
  (   W9 ? )
  (   Y8 ? )
  (   Y7 ? )
  (  AB7 ? )
  (  AA6 ? )
  (  AB6 ? )
  (   U9 ? )
  (   V9 ? )
  (   T8 ? )
  (   U8 ? )
  (  T10 ? )
  (  U10 ? )
  (   W6 ? )
  (   Y6 ? )
  (   Y5 ? )
  (  AB5 ? )
  (  AA4 ? )
  (  AB4 ? )
  (   Y3 ? )
  (  AB3 ? )
  (   R9 ? )
  (   R8 ? )
  (   T7 ? )
  (   R7 ? )
  (   W4 ? )
  (   Y4 ? )
  (   U6 ? )
  (   V5 ? )
  (  AA2 ? )
  (  AB2 ? )
  (   T6 ? )
  (   T5 ? )
  ( AB13 ? )
  (  Y13 ? )
  (  Y12 ? )
  (  W12 ? )
  (  R13 ? )
  (  T14 ? )
  (  U12 ? )
  (  T12 ? )
  ( AB15 ? )
  (  Y15 ? )
  (  Y14 ? )
  (  W14 ? )
  ( AB16 ? )
  ( AA16 ? )
  (  W13 ? )
  (  V13 ? )
  (  W15 ? )
  (  Y16 ? )
  ( AB14 ? )
  ( AA14 ? )
  ( AB17 ? )
  (  Y17 ? )
  ( AB18 ? )
  ( AA18 ? )
  (  V15 ? )
  (  U15 ? )
  (  U13 ? )
  (  U14 ? )
  (  W17 ? )
  (  V17 ? )
  (  R15 ? )
  (  R16 ? )
  (  V18 ? )
  (  V19 ? )
  (  U16 ? )
  (  U17 ? )
  (  T15 ? )
  (  T16 ? )
  (  Y18 ? )
  (  W18 ? )
  ( AB19 ? )
  (  Y19 ? )
  (  T17 ? )
  (  T18 ? )
  ( AB20 ? )
  ( AA20 ? )
  ( AB21 ? )
  ( AA21 ? )
  ( AA22 ? )
  (   W2 N-000120 )
  (   L2 N-000120 )
  (   L7 N-000120 )
  (   C2 N-000120 )
  (   N5 N-000120 )
  (   R2 N-000120 )
  (   U5 N-000120 )
  (   G2 N-000120 )
  (   F4 N-000120 )
  (   F6 N-000120 )
  (   J5 N-000120 )
  (   M3 /DDR_Banks/M0_UDM )
  (   L4 /DDR_Banks/M0_LDM )
  (   K5 /DDR_Banks/M0_RAS# )
  (   K4 /DDR_Banks/M0_CAS# )
  (   K3 /DDR_Banks/M0_A5 )
  (   J4 /DDR_Banks/M0_A6 )
  (   K6 /DDR_Banks/M0_A3 )
  (   J6 ? )
  (   H4 /DDR_Banks/M0_CLK )
  (   H3 /DDR_Banks/M0_CLK# )
  (   H2 /DDR_Banks/M0_A0 )
  (   H1 /DDR_Banks/M0_A1 )
  (   G3 ? )
  (   G1 ? )
  (   H6 /DDR_Banks/M0_A7 )
  (   H5 /DDR_Banks/M0_A2 )
  (   F2 /DDR_Banks/M0_WE# )
  (   F1 ? )
  (   G4 /DDR_Banks/M0_A10 )
  (   F3 /DDR_Banks/M0_A4 )
  (   E3 /DDR_Banks/M0_A8 )
  (   E1 /DDR_Banks/M0_A9 )
  (   D2 /DDR_Banks/M0_CKE )
  (   D1 /DDR_Banks/M0_A12 )
  (   C3 ? )
  (   C1 /DDR_Banks/M0_A11 )
  (   G6 ? )
  (   F5 ? )
  (   K7 ? )
  (   K8 ? )
  (   D5 ? )
  (   E4 ? )
  (   J7 ? )
  (   H8 ? )
  (   B2 ? )
  (   B1 ? )
  (   G7 ? )
  (   F7 ? )
  (   D3 ? )
  (   C4 ? )
  (   E5 ? )
  (   E6 ? )
  (   A2 ? )
  (   B3 ? )
  (   J1 /DDR_Banks/M0_DQ5 )
  (   J3 /DDR_Banks/M0_DQ4 )
  (   K1 /DDR_Banks/M0_DQ7 )
  (   K2 /DDR_Banks/M0_DQ6 )
  (   L1 ? )
  (   L3 /DDR_Banks/M0_LDQS )
  (   M1 /DDR_Banks/M0_DQ3 )
  (   M2 /DDR_Banks/M0_DQ2 )
  (   N1 /DDR_Banks/M0_DQ1 )
  (   N3 /DDR_Banks/M0_DQ0 )
  (   P1 /DDR_Banks/M0_DQ9 )
  (   P2 /DDR_Banks/M0_DQ8 )
  (   R1 /DDR_Banks/M0_DQ11 )
  (   R3 /DDR_Banks/M0_DQ10 )
  (   T1 ? )
  (   T2 /DDR_Banks/M0_UDQS )
  (   U1 /DDR_Banks/M0_DQ13 )
  (   U3 /DDR_Banks/M0_DQ12 )
  (   V1 /DDR_Banks/M0_DQ15 )
  (   V2 /DDR_Banks/M0_DQ14 )
  (   M4 ? )
  (   M5 ? )
  (   N4 ? )
  (   P3 ? )
  (   L6 ? )
  (   M6 ? )
  (   P4 ? )
  (   R4 ? )
  (   M8 ? )
  (   M7 ? )
  (   N7 ? )
  (   N6 ? )
  (   V3 ? )
  (   U4 ? )
  (   T3 ? )
  (   T4 ? )
  (   P5 ? )
  (   P6 ? )
  (   P7 ? )
  (   P8 ? )
  (   W1 ? )
  (   W3 ? )
  (   Y1 ? )
  (  W21 N-000121 )
  (  C21 N-000121 )
  (  G21 N-000121 )
  (  J18 N-000121 )
  (  L16 N-000121 )
  (  L21 N-000121 )
  (  N18 N-000121 )
  (  R21 N-000121 )
  (  U18 N-000121 )
  (  E19 N-000121 )
  (  L19 /DDR_Banks/M1_LDM )
  (  J20 /DDR_Banks/M1_DQ4 )
  (  J22 /DDR_Banks/M1_DQ5 )
  (  K21 /DDR_Banks/M1_DQ6 )
  (  K22 /DDR_Banks/M1_DQ7 )
  (  L20 /DDR_Banks/M1_LDQS )
  (  L22 ? )
  (  M21 /DDR_Banks/M1_DQ2 )
  (  M22 /DDR_Banks/M1_DQ3 )
  (  N20 /DDR_Banks/M1_DQ0 )
  (  N22 /DDR_Banks/M1_DQ1 )
  (  P21 /DDR_Banks/M1_DQ8 )
  (  P22 /DDR_Banks/M1_DQ9 )
  (  R20 /DDR_Banks/M1_DQ10 )
  (  R22 /DDR_Banks/M1_DQ11 )
  (  T21 /DDR_Banks/M1_UDQS )
  (  T22 ? )
  (  U20 /DDR_Banks/M1_DQ12 )
  (  U22 /DDR_Banks/M1_DQ13 )
  (  V21 /DDR_Banks/M1_DQ14 )
  (  V22 /DDR_Banks/M1_DQ15 )
  (  M19 ? )
  (  N19 ? )
  (  M16 ? )
  (  L15 ? )
  (  P19 ? )
  (  P20 ? )
  (  W20 ? )
  (  W22 ? )
  (  L17 ? )
  (  K18 ? )
  (  U19 ? )
  (  V20 ? )
  (  M17 ? )
  (  M18 ? )
  (  P17 ? )
  (  N16 ? )
  (  P18 ? )
  (  R19 ? )
  (  T19 ? )
  (  T20 ? )
  (  M20 /DDR_Banks/M1_UDM )
  (  H22 /DDR_Banks/M1_CAS# )
  (  H21 /DDR_Banks/M1_RAS# )
  (  K19 /DDR_Banks/M1_A6 )
  (  K20 /DDR_Banks/M1_A5 )
  (  G22 ? )
  (  G20 /DDR_Banks/M1_A3 )
  (  J19 /DDR_Banks/M1_CLK# )
  (  H20 /DDR_Banks/M1_CLK )
  (  F22 /DDR_Banks/M1_A1 )
  (  F21 /DDR_Banks/M1_A0 )
  (  K17 ? )
  (  J17 ? )
  (  E22 /DDR_Banks/M1_A2 )
  (  E20 /DDR_Banks/M1_A7 )
  (  H18 ? )
  (  H19 /DDR_Banks/M1_WE# )
  (  F20 /DDR_Banks/M1_A4 )
  (  G19 /DDR_Banks/M1_A10 )
  (  C22 /DDR_Banks/M1_A9 )
  (  C20 /DDR_Banks/M1_A8 )
  (  D22 /DDR_Banks/M1_A12 )
  (  D21 /DDR_Banks/M1_CKE )
  (  F19 /DDR_Banks/M1_A11 )
  (  F18 ? )
  (  D20 ? )
  (  D19 ? )
  (  H17 ? )
  (  H16 ? )
  (  J16 ? )
  (  K16 ? )
  (  A21 ? )
  (  A20 ? )
  (  B22 ? )
  (  B21 ? )
  (  F17 ? )
  (  F16 ? )
  (  G17 ? )
  (  G16 ? )
  (  B20 ? )
  (   B4 N-000122 )
  (   B7 N-000122 )
  (  E13 N-000122 )
  (  E17 N-000122 )
  (  G10 N-000122 )
  (  G14 N-000122 )
  (  B11 N-000122 )
  (  B15 N-000122 )
  (  B19 N-000122 )
  (   E9 N-000122 )
  (  A11 ? )
  (  D11 ? )
  (  C12 ? )
  (  B12 ? )
  (  A12 ? )
  (  C13 ? )
  (  A13 ? )
  (  D14 ? )
  (  C14 ? )
  (  B14 ? )
  (  A14 ? )
  (  C15 ? )
  (  A15 ? )
  (  D15 ? )
  (  C16 ? )
  (  B16 ? )
  (  A16 ? )
  (  C17 ? )
  (  A17 ? )
  (  B18 ? )
  (  A18 ? )
  (  E16 ? )
  (  D17 ? )
  (  C11 ? )
  (  A10 ? )
  (  B10 ? )
  (  C10 ? )
  (  D10 ? )
  (   D8 ? )
  (   D7 ? )
  (   A9 ? )
  (   C9 ? )
  (   C8 ? )
  (   D9 ? )
  (   A8 ? )
  (   B8 ? )
  (   A7 ? )
  (   C7 ? )
  (   A6 ? )
  (   B6 ? )
  (   C6 ? )
  (   D6 ? )
  (   A5 /FPGA_Spartan6/ETH_INT )
  (   C5 ? )
  (   A4 ? )
 )
 ( /4C5F1EDC/4C5F2D27 $noname  R? 1M {Lib=R}
  (    1 N-000412 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2D1E $noname  C? 4.7nF {Lib=C}
  (    1 N-000412 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2CA7 $noname  V? V0402MHS03 {Lib=V0402MHS03}
  (    1 N-000410 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2CA3 $noname  V? V0402MHS03 {Lib=V0402MHS03}
  (    1 N-000409 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2B55 $noname  F? MICROSMD075F {Lib=MICROSMD075F}
  (    1 N-000411 )
  (    2 ? )
 )
 ( /4C5F1EDC/4C5F23DD $noname  J? USB-48204-0001 {Lib=USB-48204-0001}
  (   S1 N-000412 )
  (   S2 N-000412 )
  (   S3 N-000412 )
  (   S4 N-000412 )
  (    1 N-000411 )
  (    2 N-000409 )
  (    3 N-000410 )
  (    4 GND )
 )
 ( /4C5F1EDC/4C5F2039 $noname  C? 470nF {Lib=C}
  (    1 N-000068 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2037 $noname  C? 1uF {Lib=C}
  (    1 N-000068 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2033 $noname  C? 1uF {Lib=C}
  (    1 N-000068 )
  (    2 GND )
 )
 ( /4C5F1EDC/4C5F2025 $noname  U6 MIC2550AYTS {Lib=MIC2550AYTS}
  (    1 N-000068 )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    7 GND )
  (    8 GND )
  (    9 ? )
  (   10 N-000409 )
  (   11 N-000410 )
  (   12 N-000068 )
  (   14 N-000068 )
 )
 ( /4C4320F3/4C5D8114 $noname  C? C {Lib=C}
  (    1 /Ethernet_Phy/ETH_PLL1.8V )
  (    2 N-000395 )
 )
 ( /4C4320F3/4C5D810A $noname  L? INDUCTOR {Lib=INDUCTOR}
  (    1 /Ethernet_Phy/ETH_A1.8V )
  (    2 /Ethernet_Phy/ETH_PLL1.8V )
 )
 ( /4C4320F3/4C5D8104 $noname  C? C {Lib=C}
  (    1 /Ethernet_Phy/ETH_A1.8V )
  (    2 N-000395 )
 )
 ( /4C4320F3/4C5D80F3 $noname  L? INDUCTOR {Lib=INDUCTOR}
  (    1 N-000394 )
  (    2 /Ethernet_Phy/ETH_A1.8V )
 )
 ( /4C4320F3/4C5D80F0 $noname  C? C {Lib=C}
  (    1 N-000394 )
  (    2 N-000395 )
 )
 ( /4C4320F3/4C5D80ED $noname  C? C {Lib=C}
  (    1 /Ethernet_Phy/ETH_1.8V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FB7 $noname  L? FB {Lib=INDUCTOR}
  (    1 N-000068 )
  (    2 /Ethernet_Phy/ETH_A3.3V )
 )
 ( /4C4320F3/4C5D7FA7 $noname  C? 100nF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA5 $noname  C? 1uF {Lib=C}
  (    1 /Ethernet_Phy/ETH_A3.3V )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA3 $noname  C? 100nF {Lib=C}
  (    1 N-000068 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7FA1 $noname  C? 100nF {Lib=C}
  (    1 N-000068 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7F9F $noname  C? 1uF {Lib=C}
  (    1 N-000068 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7F39 $noname  R? 4.7K {Lib=R}
  (    1 /ETH_MDIO )
  (    2 N-000068 )
 )
 ( /4C4320F3/4C5D7ECF $noname  R? 6.65K {Lib=R}
  (    1 N-000384 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7E43 $noname  C? 100nF {Lib=C}
  (    1 N-000068 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7E41 $noname  C? 100nF {Lib=C}
  (    1 N-000068 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7DCB $noname  C? 47nF {Lib=C}
  (    1 N-000393 )
  (    2 GND )
 )
 ( /4C4320F3/4C5D7DC4 $noname  R? 1M {Lib=R}
  (    1 N-000393 )
  (    2 GND )
 )
 ( /4C4320F3/4C432132 $noname  U4 K8001 {Lib=K8001}
  (    1 /ETH_MDIO )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 ? )
  (    7 N-000068 )
  (    8 GND )
  (    9 ? )
  (   10 ? )
  (   11 ? )
  (   12 GND )
  (   13 /Ethernet_Phy/ETH_1.8V )
  (   14 ? )
  (   15 ? )
  (   16 ? )
  (   17 ? )
  (   18 ? )
  (   19 ? )
  (   20 ? )
  (   21 ? )
  (   22 ? )
  (   23 GND )
  (   24 N-000068 )
  (   25 /FPGA_Spartan6/ETH_INT )
  (   26 /Ethernet_Phy/ETH_LED0 )
  (   27 /Ethernet_Phy/ETH_LED1 )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 /Ethernet_Phy/ETH_A1.8V )
  (   32 N-000385 )
  (   33 N-000392 )
  (   34 ? )
  (   35 GND )
  (   36 GND )
  (   37 N-000384 )
  (   38 /Ethernet_Phy/ETH_A3.3V )
  (   39 GND )
  (   40 N-000386 )
  (   41 N-000391 )
  (   42 ? )
  (   43 ? )
  (   44 GND )
  (   45 ? )
  (   46 ? )
  (   47 /Ethernet_Phy/ETH_PLL1.8V )
  (   48 ? )
 )
 ( /4C4320F3/4C5D7AFE $noname  R? 49.9 {Lib=R}
  (    1 N-000068 )
  (    2 N-000391 )
 )
 ( /4C4320F3/4C5D7AFC $noname  R? 49.9 {Lib=R}
  (    1 N-000068 )
  (    2 N-000386 )
 )
 ( /4C4320F3/4C5D7AF9 $noname  R? 49.9 {Lib=R}
  (    1 N-000068 )
  (    2 N-000385 )
 )
 ( /4C4320F3/4C5D7AF7 $noname  R? 49.9 {Lib=R}
  (    1 N-000068 )
  (    2 N-000392 )
 )
 ( /4C4320F3/4C5D71DB $noname  R? 220 {Lib=R}
  (    1 N-000388 )
  (    2 /Ethernet_Phy/ETH_LED1 )
 )
 ( /4C4320F3/4C5D719D $noname  R? 220 {Lib=R}
  (    1 N-000389 )
  (    2 /Ethernet_Phy/ETH_LED0 )
 )
 ( /4C4320F3/4C5D6F5A $noname  J4 RJ45-48025 {Lib=RJ45-48025}
  (    1 N-000391 )
  (    2 N-000386 )
  (    3 N-000068 )
  (    4 GND )
  (    5 GND )
  (    6 N-000068 )
  (    7 N-000392 )
  (    8 N-000385 )
  (    9 N-000068 )
  (   10 N-000389 )
  (   11 N-000068 )
  (   12 N-000388 )
  (   13 N-000393 )
  (   14 N-000393 )
 )
 ( /4C4227FE/4B76F5E2 $noname  J1 MICROSD {Lib=MICROSD}
  ( CASE GND )
  (   CD ? )
  (  COM GND )
  (    1 ? )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 ? )
  (    7 ? )
  (    8 ? )
 )
 ( /4C4227FE/4B76F108 $noname  U5 NAND {Lib=HY27UG088G5M}
  (    1 ? )
  (    2 ? )
  (    3 ? )
  (    4 ? )
  (    5 ? )
  (    6 /Non_volatile_memories/FRB_N )
  (    7 /Non_volatile_memories/FRB_N )
  (    8 ? )
  (    9 ? )
  (   10 ? )
  (   11 ? )
  (   12 N-000068 )
  (   13 GND )
  (   14 ? )
  (   15 ? )
  (   16 ? )
  (   17 ? )
  (   18 ? )
  (   19 N-000068 )
  (   20 ? )
  (   21 ? )
  (   22 ? )
  (   23 ? )
  (   24 ? )
  (   25 ? )
  (   26 ? )
  (   27 ? )
  (   28 ? )
  (   29 ? )
  (   30 ? )
  (   31 ? )
  (   32 ? )
  (   33 ? )
  (   34 ? )
  (   35 ? )
  (   36 GND )
  (   37 N-000068 )
  (   38 ? )
  (   39 ? )
  (   40 ? )
  (   41 ? )
  (   42 ? )
  (   43 ? )
  (   44 ? )
  (   45 ? )
  (   46 ? )
  (   47 ? )
  (   48 ? )
 )
 ( /4C421DD3/4C58CA3A 60fbga_ddr  U3 MT46V32M16FN {Lib=MT46V32M16FN}
  (   A7 N-000048 )
  (   F8 N-000048 )
  (   M7 N-000048 )
  (   A9 N-000048 )
  (   B2 N-000048 )
  (   C8 N-000048 )
  (   D2 N-000048 )
  (   E8 N-000048 )
  (   B7 /DDR_Banks/M1_DQ2 )
  (   C9 /DDR_Banks/M1_DQ3 )
  (   C7 /DDR_Banks/M1_DQ4 )
  (   D9 /DDR_Banks/M1_DQ5 )
  (   D7 /DDR_Banks/M1_DQ6 )
  (   E9 /DDR_Banks/M1_DQ7 )
  (   E1 /DDR_Banks/M1_DQ8 )
  (   D3 /DDR_Banks/M1_DQ9 )
  (   D1 /DDR_Banks/M1_DQ10 )
  (   C3 /DDR_Banks/M1_DQ11 )
  (   C1 /DDR_Banks/M1_DQ12 )
  (   B3 /DDR_Banks/M1_DQ13 )
  (   B1 /DDR_Banks/M1_DQ14 )
  (   A2 /DDR_Banks/M1_DQ15 )
  (   F7 /DDR_Banks/M1_LDM )
  (   E7 /DDR_Banks/M1_LDQS )
  (   F9 ? )
  (   H7 /DDR_Banks/M1_RAS# )
  (   F3 /DDR_Banks/M1_UDM )
  (   E3 /DDR_Banks/M1_UDQS )
  (   F1 ? )
  (   G7 /DDR_Banks/M1_WE# )
  (   B9 /DDR_Banks/M1_DQ1 )
  (   A8 /DDR_Banks/M1_DQ0 )
  (   H8 ? )
  (   G3 /DDR_Banks/M1_CLK# )
  (   G2 /DDR_Banks/M1_CLK )
  (   H3 /DDR_Banks/M1_CKE )
  (   G8 /DDR_Banks/M1_CAS# )
  (   J7 ? )
  (   J8 ? )
  (   H2 /DDR_Banks/M1_A12 )
  (   J2 /DDR_Banks/M1_A11 )
  (   K8 /DDR_Banks/M1_A10 )
  (   J3 /DDR_Banks/M1_A9 )
  (   K2 /DDR_Banks/M1_A8 )
  (   K3 /DDR_Banks/M1_A7 )
  (   L2 /DDR_Banks/M1_A6 )
  (   L3 /DDR_Banks/M1_A5 )
  (   M2 /DDR_Banks/M1_A4 )
  (   M8 /DDR_Banks/M1_A3 )
  (   L7 /DDR_Banks/M1_A2 )
  (   L8 /DDR_Banks/M1_A1 )
  (   K7 /DDR_Banks/M1_A0 )
  (   A3 GND )
  (   F2 GND )
  (   M3 GND )
  (   A1 GND )
  (   B8 GND )
  (   C2 GND )
  (   D8 GND )
  (   E2 GND )
 )
 ( /4C421DD3/4C58C847 60fbga_ddr  U2 MT46V32M16FN {Lib=MT46V32M16FN}
  (   A7 N-000046 )
  (   F8 N-000046 )
  (   M7 N-000046 )
  (   A9 N-000046 )
  (   B2 N-000046 )
  (   C8 N-000046 )
  (   D2 N-000046 )
  (   E8 N-000046 )
  (   B7 /DDR_Banks/M0_DQ2 )
  (   C9 /DDR_Banks/M0_DQ3 )
  (   C7 /DDR_Banks/M0_DQ4 )
  (   D9 /DDR_Banks/M0_DQ5 )
  (   D7 /DDR_Banks/M0_DQ6 )
  (   E9 /DDR_Banks/M0_DQ7 )
  (   E1 /DDR_Banks/M0_DQ8 )
  (   D3 /DDR_Banks/M0_DQ9 )
  (   D1 /DDR_Banks/M0_DQ10 )
  (   C3 /DDR_Banks/M0_DQ11 )
  (   C1 /DDR_Banks/M0_DQ12 )
  (   B3 /DDR_Banks/M0_DQ13 )
  (   B1 /DDR_Banks/M0_DQ14 )
  (   A2 /DDR_Banks/M0_DQ15 )
  (   F7 /DDR_Banks/M0_LDM )
  (   E7 /DDR_Banks/M0_LDQS )
  (   F9 ? )
  (   H7 /DDR_Banks/M0_RAS# )
  (   F3 /DDR_Banks/M0_UDM )
  (   E3 /DDR_Banks/M0_UDQS )
  (   F1 ? )
  (   G7 /DDR_Banks/M0_WE# )
  (   B9 /DDR_Banks/M0_DQ1 )
  (   A8 /DDR_Banks/M0_DQ0 )
  (   H8 ? )
  (   G3 /DDR_Banks/M0_CLK# )
  (   G2 /DDR_Banks/M0_CLK )
  (   H3 /DDR_Banks/M0_CKE )
  (   G8 /DDR_Banks/M0_CAS# )
  (   J7 ? )
  (   J8 ? )
  (   H2 /DDR_Banks/M0_A12 )
  (   J2 /DDR_Banks/M0_A11 )
  (   K8 /DDR_Banks/M0_A10 )
  (   J3 /DDR_Banks/M0_A9 )
  (   K2 /DDR_Banks/M0_A8 )
  (   K3 /DDR_Banks/M0_A7 )
  (   L2 /DDR_Banks/M0_A6 )
  (   L3 /DDR_Banks/M0_A5 )
  (   M2 /DDR_Banks/M0_A4 )
  (   M8 /DDR_Banks/M0_A3 )
  (   L7 /DDR_Banks/M0_A2 )
  (   L8 /DDR_Banks/M0_A1 )
  (   K7 /DDR_Banks/M0_A0 )
  (   A3 GND )
  (   F2 GND )
  (   M3 GND )
  (   A1 GND )
  (   B8 GND )
  (   C2 GND )
  (   D8 GND )
  (   E2 GND )
 )
)
*
{ Allowed footprints by component:
$component R?
 R?
 SM0603
 SM0805
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component R?
 R?
 SM0603
 SM0805
$endlist
$component R?
 R?
 SM0603
 SM0805
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component C?
 SM*
 C?
 C1-1
$endlist
$component R?
 R?
 SM0603
 SM0805
$endlist
$component R?
 R?
 SM0603
 SM0805
$endlist
$component R?
 R?
 SM0603
 SM0805
$endlist
$component R?
 R?
 SM0603
 SM0805
$endlist
$component R?
 R?
 SM0603
 SM0805
$endlist
$component R?
 R?
 SM0603
 SM0805
$endlist
$component R?
 R?
 SM0603
 SM0805
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 9 "/ETH_MDIO" "ETH_MDIO"
 R? 1
 U4 1
Net 13 "/DDR Banks/M1_LDM" "M1_LDM"
 U3 F7
 U1 L19
Net 14 "/DDR Banks/M1_CKE" "M1_CKE"
 U3 H3
 U1 D21
Net 15 "/DDR Banks/M1_CAS#" "M1_CAS#"
 U3 G8
 U1 H22
Net 16 "/DDR Banks/M0_CKE" "M0_CKE"
 U2 H3
 U1 D2
Net 17 "/DDR Banks/M0_WE#" "M0_WE#"
 U2 G7
 U1 F2
Net 18 "/DDR Banks/M0_CAS#" "M0_CAS#"
 U2 G8
 U1 K4
Net 19 "/DDR Banks/M0_UDM" "M0_UDM"
 U2 F3
 U1 M3
Net 20 "/DDR Banks/M0_UDQS" "M0_UDQS"
 U2 E3
 U1 T2
Net 21 "/DDR Banks/M1_CLK#" "M1_CLK#"
 U3 G3
 U1 J19
Net 22 "/DDR Banks/M0_CLK#" "M0_CLK#"
 U2 G3
 U1 H3
Net 23 "/DDR Banks/M0_CLK" "M0_CLK"
 U2 G2
 U1 H4
Net 24 "/DDR Banks/M1_CLK" "M1_CLK"
 U3 G2
 U1 H20
Net 25 "/DDR Banks/M0_LDM" "M0_LDM"
 U2 F7
 U1 L4
Net 26 "/DDR Banks/M0_LDQS" "M0_LDQS"
 U2 E7
 U1 L3
Net 27 "/DDR Banks/M0_RAS#" "M0_RAS#"
 U2 H7
 U1 K5
Net 29 "/DDR Banks/M1_RAS#" "M1_RAS#"
 U3 H7
 U1 H21
Net 30 "/DDR Banks/M1_WE#" "M1_WE#"
 U3 G7
 U1 H19
Net 31 "/DDR Banks/M1_UDM" "M1_UDM"
 U3 F3
 U1 M20
Net 32 "/DDR Banks/M1_LDQS" "M1_LDQS"
 U3 E7
 U1 L20
Net 33 "/DDR Banks/M1_UDQS" "M1_UDQS"
 U3 E3
 U1 T21
Net 34 "/FPGA Spartan6/ETH_INT" "ETH_INT"
 U1 A5
 U4 25
Net 45 "GND" "GND"
 U3 A3
 U3 F2
 U3 M3
 U3 A1
 U3 B8
 U3 C2
 U3 D8
 U3 E2
 U2 A3
 U2 F2
 U2 M3
 U2 A1
 U2 B8
 U2 C2
 U2 D8
 U2 E2
 J1 CASE
 J1 CASE
 J1 CASE
 J1 COM
 U5 36
 U5 13
 U1 P10
 U1 V10
 U1 M10
 U1 K10
 U1 L13
 U1 A1
 U1 N13
 U1 A22
 U1 R5
 U1 AA13
 U1 W19
 U1 AA17
 U1 K14
 U1 AA5
 U1 L5
 U1 AA9
 U1 M14
 U1 AB1
 U1 N2
 U1 AB22
 U1 P14
 U1 B13
 U1 U21
 U1 B17
 U1 V4
 U1 B5
 U1 J9
 U1 B9
 U1 K12
 U1 D18
 U1 L11
 U1 D4
 U1 L18
 U1 E11
 U1 L9
 U1 E15
 U1 M12
 U1 E2
 U1 N11
 U1 E21
 U1 N17
 U1 E7
 U1 N21
 U1 G18
 U1 P12
 U1 G5
 U1 R18
 U1 H7
 U1 U2
 U1 J11
 U1 U7
 U1 J13
 U1 V14
 U1 J15
 U1 W16
 U1 J2
 U1 W7
 U1 J21
 U1 N9
 C? 2
 C? 2
 C? 2
 C? 2
 C? 2
 C? 2
 R? 2
 C? 2
 C? 2
 C? 2
 R? 2
 U4 8
 U4 12
 U4 23
 U4 35
 U4 36
 U4 39
 U4 44
 J4 5
 J4 4
 R? 2
 C? 2
 V? 2
 V? 2
 J? 4
 C? 2
 C? 2
 C? 2
 U6 8
 U6 7
Net 46 "" ""
 U2 A7
 U2 F8
 U2 M7
 U2 A9
 U2 B2
 U2 C8
 U2 D2
 U2 E8
Net 48 "" ""
 U3 A7
 U3 F8
 U3 M7
 U3 A9
 U3 B2
 U3 C8
 U3 D2
 U3 E8
Net 68 "" ""
 U5 37
 U5 19
 U5 12
 L? 1
 C? 1
 C? 1
 C? 1
 R? 2
 C? 1
 C? 1
 U4 7
 U4 24
 R? 1
 R? 1
 R? 1
 R? 1
 J4 11
 J4 9
 J4 6
 J4 3
 C? 1
 C? 1
 C? 1
 U6 14
 U6 12
 U6 1
Net 71 "/Non volatile memories/FRB_N" "FRB_N"
 U5 7
 U5 6
Net 118 "" ""
 U1 N10
 U1 P11
 U1 P13
 U1 P9
 U1 R14
 U1 N12
 U1 J10
 U1 J12
 U1 J14
 U1 J8
 U1 K11
 U1 K13
 U1 K9
 U1 L10
 U1 L12
 U1 L14
 U1 M11
 U1 M13
 U1 M9
 U1 N14
Net 119 "" ""
 U1 H9
 U1 U11
 U1 F11
 U1 R6
 U1 M15
 U1 V6
 U1 G12
 U1 H15
 U1 D16
 U1 K15
 U1 R12
 U1 N8
 U1 R10
 U1 L8
Net 120 "" ""
 U1 W2
 U1 L2
 U1 L7
 U1 C2
 U1 N5
 U1 R2
 U1 U5
 U1 G2
 U1 F4
 U1 F6
 U1 J5
Net 121 "" ""
 U1 W21
 U1 C21
 U1 G21
 U1 J18
 U1 L16
 U1 L21
 U1 N18
 U1 R21
 U1 U18
 U1 E19
Net 122 "" ""
 U1 B4
 U1 B7
 U1 E13
 U1 E17
 U1 G10
 U1 G14
 U1 B11
 U1 B15
 U1 B19
 U1 E9
Net 123 "" ""
 U1 AA15
 U1 V16
 U1 T13
 U1 V8
 U1 V12
 U1 AA3
 U1 T9
 U1 AA19
 U1 AA11
 U1 W5
 U1 AA7
Net 382 "/Ethernet Phy/ETH_A1.8V" "ETH_A1.8V"
 L? 1
 C? 1
 L? 2
 U4 31
Net 383 "/Ethernet Phy/ETH_A3.3V" "ETH_A3.3V"
 L? 2
 C? 1
 C? 1
 U4 38
Net 384 "" ""
 R? 1
 U4 37
Net 385 "" ""
 U4 32
 R? 2
 J4 8
Net 386 "" ""
 U4 40
 R? 2
 J4 2
Net 387 "/Ethernet Phy/ETH_LED1" "ETH_LED1"
 U4 27
 R? 2
Net 388 "" ""
 R? 1
 J4 12
Net 389 "" ""
 R? 1
 J4 10
Net 390 "/Ethernet Phy/ETH_LED0" "ETH_LED0"
 U4 26
 R? 2
Net 391 "" ""
 U4 41
 R? 2
 J4 1
Net 392 "" ""
 U4 33
 R? 2
 J4 7
Net 393 "" ""
 C? 1
 R? 1
 J4 13
 J4 14
Net 394 "" ""
 L? 1
 C? 1
Net 395 "" ""
 C? 2
 C? 2
 C? 2
Net 396 "/Ethernet Phy/ETH_1.8V" "ETH_1.8V"
 C? 1
 U4 13
Net 397 "/Ethernet Phy/ETH_PLL1.8V" "ETH_PLL1.8V"
 C? 1
 L? 2
 U4 47
Net 409 "" ""
 V? 1
 V? 1
 J? 2
 U6 10
Net 410 "" ""
 V? 1
 V? 1
 J? 3
 U6 11
Net 411 "" ""
 F? 1
 J? 1
Net 412 "" ""
 R? 1
 C? 1
 J? S1
 J? S2
 J? S3
 J? S4
Net 423 "/DDR Banks/M0_A0" "M0_A0"
 U2 K7
 U1 H2
Net 424 "/DDR Banks/M0_A1" "M0_A1"
 U2 L8
 U1 H1
Net 425 "/DDR Banks/M0_A2" "M0_A2"
 U2 L7
 U1 H5
Net 426 "/DDR Banks/M0_A3" "M0_A3"
 U2 M8
 U1 K6
Net 427 "/DDR Banks/M0_A4" "M0_A4"
 U2 M2
 U1 F3
Net 428 "/DDR Banks/M0_A5" "M0_A5"
 U2 L3
 U1 K3
Net 429 "/DDR Banks/M0_A6" "M0_A6"
 U2 L2
 U1 J4
Net 430 "/DDR Banks/M0_A7" "M0_A7"
 U2 K3
 U1 H6
Net 431 "/DDR Banks/M0_A8" "M0_A8"
 U2 K2
 U1 E3
Net 432 "/DDR Banks/M0_A9" "M0_A9"
 U2 J3
 U1 E1
Net 433 "/DDR Banks/M0_A10" "M0_A10"
 U2 K8
 U1 G4
Net 434 "/DDR Banks/M0_A11" "M0_A11"
 U2 J2
 U1 C1
Net 435 "/DDR Banks/M0_A12" "M0_A12"
 U2 H2
 U1 D1
Net 436 "/DDR Banks/M1_A0" "M1_A0"
 U3 K7
 U1 F21
Net 437 "/DDR Banks/M1_A1" "M1_A1"
 U3 L8
 U1 F22
Net 438 "/DDR Banks/M1_A2" "M1_A2"
 U3 L7
 U1 E22
Net 439 "/DDR Banks/M1_A3" "M1_A3"
 U3 M8
 U1 G20
Net 440 "/DDR Banks/M1_A4" "M1_A4"
 U3 M2
 U1 F20
Net 441 "/DDR Banks/M1_A5" "M1_A5"
 U3 L3
 U1 K20
Net 442 "/DDR Banks/M1_A6" "M1_A6"
 U3 L2
 U1 K19
Net 443 "/DDR Banks/M1_A7" "M1_A7"
 U3 K3
 U1 E20
Net 444 "/DDR Banks/M1_A8" "M1_A8"
 U3 K2
 U1 C20
Net 445 "/DDR Banks/M1_A9" "M1_A9"
 U3 J3
 U1 C22
Net 446 "/DDR Banks/M1_A10" "M1_A10"
 U3 K8
 U1 G19
Net 447 "/DDR Banks/M1_A11" "M1_A11"
 U3 J2
 U1 F19
Net 448 "/DDR Banks/M1_A12" "M1_A12"
 U3 H2
 U1 D22
Net 449 "/DDR Banks/M0_DQ0" "M0_DQ0"
 U2 A8
 U1 N3
Net 450 "/DDR Banks/M0_DQ1" "M0_DQ1"
 U2 B9
 U1 N1
Net 451 "/DDR Banks/M0_DQ2" "M0_DQ2"
 U2 B7
 U1 M2
Net 452 "/DDR Banks/M0_DQ3" "M0_DQ3"
 U2 C9
 U1 M1
Net 453 "/DDR Banks/M0_DQ4" "M0_DQ4"
 U2 C7
 U1 J3
Net 454 "/DDR Banks/M0_DQ5" "M0_DQ5"
 U2 D9
 U1 J1
Net 455 "/DDR Banks/M0_DQ6" "M0_DQ6"
 U2 D7
 U1 K2
Net 456 "/DDR Banks/M0_DQ7" "M0_DQ7"
 U2 E9
 U1 K1
Net 457 "/DDR Banks/M0_DQ8" "M0_DQ8"
 U2 E1
 U1 P2
Net 458 "/DDR Banks/M0_DQ9" "M0_DQ9"
 U2 D3
 U1 P1
Net 459 "/DDR Banks/M0_DQ10" "M0_DQ10"
 U2 D1
 U1 R3
Net 460 "/DDR Banks/M0_DQ11" "M0_DQ11"
 U2 C3
 U1 R1
Net 461 "/DDR Banks/M0_DQ12" "M0_DQ12"
 U2 C1
 U1 U3
Net 462 "/DDR Banks/M0_DQ13" "M0_DQ13"
 U2 B3
 U1 U1
Net 463 "/DDR Banks/M0_DQ14" "M0_DQ14"
 U2 B1
 U1 V2
Net 464 "/DDR Banks/M0_DQ15" "M0_DQ15"
 U2 A2
 U1 V1
Net 465 "/DDR Banks/M1_DQ0" "M1_DQ0"
 U3 A8
 U1 N20
Net 466 "/DDR Banks/M1_DQ1" "M1_DQ1"
 U3 B9
 U1 N22
Net 467 "/DDR Banks/M1_DQ2" "M1_DQ2"
 U3 B7
 U1 M21
Net 468 "/DDR Banks/M1_DQ3" "M1_DQ3"
 U3 C9
 U1 M22
Net 469 "/DDR Banks/M1_DQ4" "M1_DQ4"
 U3 C7
 U1 J20
Net 470 "/DDR Banks/M1_DQ5" "M1_DQ5"
 U3 D9
 U1 J22
Net 471 "/DDR Banks/M1_DQ6" "M1_DQ6"
 U3 D7
 U1 K21
Net 472 "/DDR Banks/M1_DQ7" "M1_DQ7"
 U3 E9
 U1 K22
Net 473 "/DDR Banks/M1_DQ8" "M1_DQ8"
 U3 E1
 U1 P21
Net 474 "/DDR Banks/M1_DQ9" "M1_DQ9"
 U3 D3
 U1 P22
Net 475 "/DDR Banks/M1_DQ10" "M1_DQ10"
 U3 D1
 U1 R20
Net 476 "/DDR Banks/M1_DQ11" "M1_DQ11"
 U3 C3
 U1 R22
Net 477 "/DDR Banks/M1_DQ12" "M1_DQ12"
 U3 C1
 U1 U20
Net 478 "/DDR Banks/M1_DQ13" "M1_DQ13"
 U3 B3
 U1 U22
Net 479 "/DDR Banks/M1_DQ14" "M1_DQ14"
 U3 B1
 U1 V21
Net 480 "/DDR Banks/M1_DQ15" "M1_DQ15"
 U3 A2
 U1 V22
}
#End