EESchema Schematic File Version 2  date Sun 18 Jul 2010 08:11:40 PM COT
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:k8001
LIBS:micron_mobile_ddr
LIBS:xc6slx45fgg484
LIBS:chie-nv
LIBS:chie-rnc-cache
EELAYER 24  0
EELAYER END
$Descr A4 11700 8267
Sheet 1 5
Title ""
Date "19 jul 2010"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Wire Bus Line
	4000 1200 4000 1150
Wire Bus Line
	4000 1150 2750 1150
Wire Bus Line
	2750 3250 4000 3250
Wire Bus Line
	4000 3250 4000 3300
$Sheet
S 8650 3550 1450 1300
U 4C4320F3
F0 "Ethernet Phy" 60
F1 "eth_phy.sch" 60
$EndSheet
$Sheet
S 4000 900  3500 4000
U 4C431A63
F0 "FPGA Spartan6" 60
F1 "FPGA.sch" 60
F2 "M1_DQ[0..31]" B L 4000 1150 60 
F3 "M0_DQ[0..31]" B L 4000 3250 60 
$EndSheet
$Sheet
S 8700 900  1150 1850
U 4C4227FE
F0 "Non volatile memories" 60
F1 "NV_MEMORIES.sch" 60
$EndSheet
$Sheet
S 1650 900  1100 4000
U 4C421DD3
F0 "DDR Banks" 60
F1 "DRAM.sch" 60
F2 "M1_DQ[0..31]" B R 2750 1150 60 
F3 "M0_DQ[0..31]" B R 2750 3250 60 
F4 "M0_BA[0..1]" I R 2750 3700 60 
F5 "M1_BA[0..1]" I R 2750 1600 60 
F6 "M0_DM[0..3]" I R 2750 3850 60 
F7 "M1_DM[0..3]" I R 2750 1750 60 
F8 "M1_A[0..13]" I R 2750 1450 60 
F9 "M0_A[0..13]" I R 2750 3550 60 
F10 "M0_WE#" I R 2750 4600 60 
F11 "M0_RAS#" I R 2750 4450 60 
F12 "M1_RAS#" I R 2750 2350 60 
F13 "M1_WE#" I R 2750 2500 60 
F14 "M0_CAS#" I R 2750 4350 60 
F15 "M0_CKE" I R 2750 4000 60 
F16 "M0_CLK" I R 2750 4100 60 
F17 "M0_CLK#" I R 2750 4200 60 
F18 "M0_CS#" I R 2750 3100 60 
F19 "M1_CS#" I R 2750 1000 60 
F20 "M1_CLK#" I R 2750 2100 60 
F21 "M1_CLK" I R 2750 2000 60 
F22 "M1_CKE" I R 2750 1900 60 
F23 "M1_CAS#" I R 2750 2250 60 
F24 "M1_DQS[0..3]" B R 2750 1300 60 
F25 "M0_DQS[0..3]" B R 2750 3400 60 
$EndSheet
$EndSCHEMATC